Freescale Semiconductor Document Number: QFN_Addendum Rev. 0, 07/2014 Addendum Addendum for New QFN Package Migration This addendum provides the changes to the 98A case outline numbers for products covered in this book. Case outlines were changed because of the migration from gold wire to copper wire in some packages. See the table below for the old (gold wire) package versus the new (copper wire) package. To view the new drawing, go to Freescale.com and search on the new 98A package number for your device. For more information about QFN package use, see EB806: Electrical Connection Recommendations for the Exposed Pad on QFN and DFN Packages. ©Freescale Semiconductor, Inc., 2014. All rights reserved.

Original (gold wire) Current (copper wire) Part Number Package Description package document number package document number MC68HC908JW32 48 QFN 98ARH99048A 98ASA00466D MC9S08AC16 MC9S908AC60 MC9S08AC128 MC9S08AW60 MC9S08GB60A MC9S08GT16A MC9S08JM16 MC9S08JM60 MC9S08LL16 MC9S08QE128 MC9S08QE32 MC9S08RG60 MCF51CN128 MC9RS08LA8 48 QFN 98ARL10606D 98ASA00466D MC9S08GT16A 32 QFN 98ARH99035A 98ASA00473D MC9S908QE32 32 QFN 98ARE10566D 98ASA00473D MC9S908QE8 32 QFN 98ASA00071D 98ASA00736D MC9S08JS16 24 QFN 98ARL10608D 98ASA00734D MC9S08QB8 MC9S08QG8 24 QFN 98ARL10605D 98ASA00474D MC9S08SH8 24 QFN 98ARE10714D 98ASA00474D MC9RS08KB12 24 QFN 98ASA00087D 98ASA00602D MC9S08QG8 16 QFN 98ARE10614D 98ASA00671D MC9RS08KB12 8 DFN 98ARL10557D 98ASA00672D MC9S08QG8 MC9RS08KA2 6 DFN 98ARL10602D 98ASA00735D Addendum for New QFN Package Migration, Rev. 0 2 Freescale Semiconductor

Freescale Semiconductor Document Number: MC9S08LL16 Data Sheet: Technical Data Rev. 7, 1/2013 An Energy Efficient Solution by Freescale MC9S08LL16 Series 64-LQFP 48-LQFP Case 840F Case 932 Covers: MC9S08LL16 and MC9S08LL8 48-QFN 1314 Features • 8-Bit HCS08 Central Processor Unit (CPU) – On-chip in-circuit emulator (ICE) debug module containing – Up to 20-MHz CPU at 3.6V to 1.8V across temperature range three comparators and nine trigger modes. Eight deep FIFO for of -40°C to 85°C storing change-of-flow addresses and event-only data. Debug – HC08 instruction set with added BGND instruction module supports both tag and force breakpoints – Support for up to 32 interrupt/reset sources • Peripherals • On-Chip Memory – LCD — 4x28 or 8x24 LCD driver with internal charge pump – Dual Array FLASH read/program/erase over full operating and option to provide an internally regulated LCD reference voltage and temperature that can be trimmed for contrast control. – Random-access memory (RAM) – ADC — 8-channel, 12-bit resolution; 2.5 μs conversion time; – Security circuitry to prevent unauthorized access to RAM and automatic compare function; temperature sensor; internal FLASH contents bandgap reference channel; operation in stop3; fully functional • Power-Saving Modes from 3.6V to 1.8V – Two low power stop modes – ACMP — Analog comparator with selectable interrupt on – Reduced power wait mode rising, falling, or either edge of comparator output; compare – Low power run and wait modes allow peripherals to run while option to fixed internal bandgap reference voltage; outputs can voltage regulator is in standby be optionally routed to TPM module; operation in stop3 – Peripheral clock gating register can disable clocks to unused – SCI — Full duplex non-return to zero (NRZ); LIN master modules, thereby reducing currents. extended break generation; LIN slave extended break – Very low power external oscillator that can be used in stop2 or detection; wake up on active edge stop3 modes to provide accurate clock source to real time – SPI— Full-duplex or single-wire bidirectional; counter Double-buffered transmit and receive; Master or Slave mode; – 6 usec typical wake up time from stop3 mode MSB-first or LSB-first shifting • Clock Source Options – IIC — IIC with up to 100 kbps with maximum bus loading; – Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal Multi-master operation; Programmable slave address; or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz Interrupt driven byte-by-byte data transfer; supports broadcast to 16 MHz mode and 10-bit addressing – Internal Clock Source (ICS) — Internal clock source module – TPMx — Two 2-channel (TPM1 and TPM2); Selectable input containing a frequency-locked-loop (FLL) controlled by capture, output compare, or buffered edge- or center-aligned internal or external reference; precision trimming of internal PWM on each channel; reference allows 0.2% resolution and 2% deviation over – TOD— (Time Of Day) 8-bit quarter second counter with temperature and voltage; supports bus frequencies from 1MHz match register; External clock source for precise time base, to 10 MHz. time-of-day, calendar or task scheduling functions; Free • System Protection running on-chip low power oscillator (1 kHz) for cyclic – Watchdog computer operating properly (COP) reset with wake-up without external components. option to run from dedicated 1-kHz internal clock source or • Input/Output bus clock – 38 GPIOs, 2 output-only pins – Low-Voltage Warning with interrupt – 8 KBI interrupts with selectable polarity – Low-Voltage Detection with reset or interrupt – Hysteresis and configurable pull up device on all input pins; – Illegal opcode and illegal address detection with reset Configurable slew rate and drive strength on all output pins. – Flash block protection • Package Options • Development Support – 64-LQFP, 48-LQFP and 48-QFN – Single-wire background debug interface – Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module)

Table of Contents 1 Devices in the MC9S08LL16 Series . . . . . . . . . . . . . . 4 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . .30 2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.10.1Control Timing. . . . . . . . . . . . . . . . . . . . . .30 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9 3.10.2TPM Module Timing . . . . . . . . . . . . . . . . .31 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .32 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9 3.11 Analog Comparator (ACMP) Electricals . . . . . . .35 3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . 10 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .35 3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . 11 3.13 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . .39 3.5 ESD Protection and Latch-Up Immunity . . . . . . 12 3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .39 3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 13 3.15 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .40 3.7 Supply Current Characteristics . . . . . . . . . . . . . 25 3.15.1Radiated Emissions . . . . . . . . . . . . . . . . .40 3.8 External Oscillator (XOSCVLP) Characteristics 27 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.9 Internal Clock Source (ICS) Characteristics . . . 28 4.1 Device Numbering System. . . . . . . . . . . . . . . . .41 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev Date Description of Changes 1 9/2008 Initial Release. 2 10/2008 Updated electrical characteristics. Corrected 48-Pin QFN/LQFP pinouts for pins 29, 30, 32, and 32 in Figure3. Extracted Stop Mode Adders from the Supply Current table and created a Separate 3 01/2009 table for the data (See Table10). Added missing power consumption parameters in Supply Current Characteristics (Table9). Completed all the TBDs. Changed V to V , V to V , I to I DDAD DDA SSAD SSA DDAD DDA. Corrected the data in the Table8, and added |I |. Completed the Figure in the InT 4 07/21/2009 Section3.6, “DC Characteristics.” Corrected RI in FEI mode with all modules on, WI at 8 MHz, FEI mode with all DD DD modules off, S2I , S3I ; added ApS3I in the Table9. DD DD DD Corrected E , DNL, INL, E , E , E , and E in the Table18. TUE ZS FS Q IL Updated R /R data in the Table8. 5 10/13/2009 PU PD Added Figure5. Changed the Max. of R /R at PTA[4:5], PTD[0:77] and PTE[0:7] to 69.5 kΩ in the 6 10/27/2010 PU PD Table8. 7 1/23/2013 Updated |I | in the Table8. In MC9S08LL16 Series MCU Data Sheet, Rev. 7 2 Freescale Semiconductor

Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9S08LL16RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 3

Devices in the MC9S08LL16 Series 1 Devices in the MC9S08LL16 Series Table1 summarizes the feature set available in the MC9S08LL16 series of MCUs. Table1. MC9S08LL16 Series Fteatures by MCU and Package Feature MC9S08LL16 MC9S08LL8 64-pin 48-pin 48-pin Package LQFP QFN/LQFP QFN/LQFP 10,240 16,384 FLASH (8K and 2K (Dual 8K Arrays) arrays) RAM 2080 2080 2080 ACMP yes yes yes ADC 8-ch 8-ch 8-ch IIC yes yes yes IRQ yes yes yes KBI 8 8 8 SCI yes yes yes SPI yes yes yes TPM1 2-ch 2-ch 2-ch TPM2 2-ch - - TOD Yes Yes Yes 8x24 8x16 8x16 LCD 4x28 4x20 4x20 I/O pins1 38 31 31 1 I/O does not include two output-only port pins. The block diagram in Figure 1 shows the structure of the MC9S08LL16 series MCU. MC9S08LL16 Series MCU Data Sheet, Rev. 7 4 Freescale Semiconductor

Devices in the MC9S08LL16 Series HCS08 CORE ON-CHIP ICE PTA0/KBIP0/SS/ADP0 DEBUG MODULE (DBG) CPU INT PTA1/KBIP1/SPSCK/ADP1 PTA2/KBIP2/SDA/MISO/ADP2 A BKGD BKP TIME OF DAY MODULE RT PTA3/KBIP3/SCL/MOSI/ADP3 (TOD) O P PTA4/KBIP4/ADP4/LCD30 HCS08 SYSTEM CONTROL KBI[7:0] PTA5/KBIP5/ADP5/LCD31 8-BIT KEYBOARD PTA6/KBIP6/ADP6/ACMP+ INTERRUPT (KBI) RESETS AND INTERRUPTS PTA7/KBIP7/ADP7/ACMP– MODES OF OPERATION BKGD/MS POWER MANAGEMENT SS SPSCK SERIAL PERIPHERAL MISO PTB7/SS COP RESET INTERFACE (SPI) MOSI PTB6/SPSCK IRQ SCL IRQ LVD IIC MODULE (IIC) SDA B PTB5/MOSI/SCL TPM2CH0 RT PTB4/MISO/SDA USER FLASH A O (LL16 = 8K BYTES) 2-CHANNEL TIMER/PWM TPM2CH1 P PTB3 (LL8 = 8K BYTES) (TPM2) TCLK PTB2/RESET TPM1CH0 PTB1/XTAL USER FLASH B 2-CHANNEL TIMER/PWM TPM1CH1 PTB0/EXTAL (LL16 = 8K BYTES) (TPM1) TCLK (LL8 = 2K BYTES) PTC7/IRQ/TCLK SERIAL COMMUNICATIONS TxD PTC6/ACMPO//BKGD/MS USER RAM INTERFACE (SCI) RxD PTC5/TPM2CH1 PTC4/TPM2CH0 (LL16 = 2K BYTES) C (LL8 = 2K BYTES) RT O PTC3/TPM1CH1 P XTAL INTERNAL CLOCK PTC2/TPM1CH0 Source (ICS) PTC1/TxD EXTAL PTC0/RxD LOW-POWER OSCILLATOR VLCD 12-BIT VLL1 ANALOG-TO-DIGITAL AD[7:0] D VLL2 LIQUID CRYSTAL CONVERTER (ADC) RT PTD[7:0]/LCD[7:0] O VLL3 DISPLAY DRIVER P VCAP1 LCD ANALOG COMPARATOR ACMP– (ACMP) ACMP+ VCAP2 LCD[31:0] ACMPO T E PTE[7:0]/LCD[15:8] R O V P DD VOLTAGE V REGULATOR KEY: SS Pins not available on 48-pin packages. LCD[23:16] not available on 48-pin packages. Notes: When PTB2 is configured as RESET, pin becomes bi-directional with V /V DDA REFH output being open-drain drive containing an internal pull-up device. V /V SSA REFL When PTC6 is configured as BKGD, pin becomes bi-directional. Figure1. MC9S08LL16 Series Block Diagram MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 5

Pin Assignments 2 Pin Assignments This section shows the pin assignments for the MC9S08LL16 series devices. 012345 111111 DDDDDD CCCCCC 2/L3/L4/L5/L6/L7/L16171819202122232425 EEEEEEDDDDDDDDDD TTTTTTCCCCCCCCCC PPPPPPLLLLLLLLLL PTE1/LCD9 16463626160595857565554535251504948 LCD26 PTE0/LCD8 2 47 LCD27 PTD7/LCD7 3 46 LCD28 PTD6/LCD6 4 45 LCD29 PTD5/LCD5 5 44 PTA5/KBIP5/ADP5/LCD30 PTD4/LCD4 6 43 PTA4/KBIP4/ADP4/LCD31 PTD3/LCD3 7 64-Pin LQFP 42 PTA3/KBIP3/SCL/MOSI/ADP3 PTD2/LCD2 8 41 PTA2/KBIP2/SDA/MISO/ADP2 PTD1/LCD1 9 40 PTA1/KBIP1/SPSCK/ADP1 PTD0/LCD0 10 39 PTA0/KBIP0/SS/ADP0 V 11 38 PTC7/IRQ/TCLK CAP1 V 12 37 PTC6/ACMPO/BKGD/MS CAP2 V 13 36 PTC5/TPM2CH1 LL1 V 14 35 PTC4/TPM2CH0 LL2 V 15 34 PTC3/TPM1CH1 LL3 V 16 33 PTC2/TPM1CH0 LCD 7890123456789012 1112222222222333 +– L HLL D ST3ALKSDD ADP6/ACMPADP7/ACMPVVSSA/REFV/VDDAREFPTB0/EXTAPTB1/XTAVDVSPTB2/RESEPTBB4/MISO/SDB5/MOSI/SCPTB6/SPSCPTB7/SPTC0/RxPTC1/Tx P6/P7/ PTPT BIBI KK 6/7/ AA TT PP Note: V /V are internally connected to V /V . REFH REFL DDA SSA Figure2. MC9S08LL16 Series in 64-pin LQFP Package MC9S08LL16 Series MCU Data Sheet, Rev. 7 6 Freescale Semiconductor

Pin Assignments 0 1 2 3 4 5 8 9 1 1 1 1 1 1 D D D D D D D D C C C C C C C C E0/L E1/L E2/L E3/L E4/L E5/L E6/L E7/L D24 D25 D26 D27 T T T T T T T T C C C C P P P P P P P P L L L L 48 37 47 46 45 44 43 42 41 40 39 38 PTD7/LCD7 1 36 LCD28 PTD6/LCD6 2 35 LCD29 PTD5/LCD5 3 34 PTA5/KBIP5/ADP5/LCD30 PTD4/LCD4/ 4 33 PTA4/KBIP4/ADP4/LCD31 PTD3/LCD3 5 32 PTA3/KBIP3/SCL/MOSI/ADP3 PTD2/LCD2 6 48-Pin QFN/LQFP 31 PTA2/KBIP2/SDA/MISO/ADP2 PTD1/LCD1 7 30 PTA1/KBIP1/SPSCK/ADP1 PTD0/LCD0 8 29 PTA0/KBIP0/SS/ADP0 V 9 28 PTC7/IRQ/TCLK CAP1 V 10 27 PTC6/ACMPO/BKGD/MS CAP2 VLL1 11 26 PTC3/TPM1CH1 VLL2 12 25 PTC2/TPM1CH0 14 15 16 17 18 19 20 21 22 23 13 24 3 + – L H L L D S T D D VLL ADP6/ACMP ADP7/ACMP VVSSA/REF V/VDDAREF PTB0/EXTA PTB1/XTA VD VS PTB2/RESE PTC0/Rx PTC1/Tx 6/ 7/ P P BI BI K K 6/ 7/ A A T T P P Note: V /V are internally connected to V /V REFH REFL DDA SSA Figure3. MC9S08LL16 Series in 48-Pin QFN/LQFP Packages MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 7

Pin Assignments Table2. Pin Availability by Package Pin-Count <-- Lowest Priority --> Highest 64 48 Port Pin Alt 1 Alt 2 Alt3 Alt4 1 47 PTE1 LCD9 2 48 PTE0 LCD8 3 1 PTD7 LCD7 4 2 PTD6 LCD6 5 3 PTD5 LCD5 6 4 PTD4 LCD4 7 5 PTD3 LCD3 8 6 PTD2 LCD2 9 7 PTD1 LCD1 10 8 PTD0 LCD0 11 9 V cap1 12 10 V cap2 13 11 V LL1 14 12 V LL2 15 13 V LL3 16 — V LCD 17 14 PTA6 KBIP6 ADP6 ACMP+ 18 15 PTA7 KBIP7 ADP7 ACMP– V SSA 19 16 V REFL V REFH 20 17 V DDA 21 18 PTB0 EXTAL 22 19 PTB1 XTAL 23 20 V DD 24 21 V SS 25 22 PTB2 RESET 26 — PTB3 27 — PTB4 — MISO SDA 28 — PTB5 — MOSI SCL 29 — PTB6 — SPSCK 30 — PTB7 — SS 31 23 PTC0 RxD 32 24 PTC1 TxD 33 25 PTC2 TPM1CH0 34 26 PTC3 TPM1CH1 35 — PTC4 TPM2CH0 36 — PTC5 TPM2CH1 37 27 PTC6 ACMPO BKGD MS 38 28 PTC7 IRQ TCLK 39 29 PTA0 KBIP0 — SS ADP0 MC9S08LL16 Series MCU Data Sheet, Rev. 7 8 Freescale Semiconductor

Electrical Characteristics Table2. Pin Availability by Package Pin-Count (continued) <-- Lowest Priority --> Highest 64 48 Port Pin Alt 1 Alt 2 Alt3 Alt4 40 30 PTA1 KBIP1 — SPSCK ADP1 41 31 PTA2 KBIP2 SDA MISO ADP2 42 32 PTA3 KBIP3 SCL MOSI ADP3 43 33 PTA4 KBIP4 ADP4 LCD31 44 34 PTA5 KBIP5 ADP5 LCD30 45 35 LCD29 46 36 LCD28 47 37 LCD27 48 38 LCD26 49 39 LCD25 50 40 LCD24 51 — LCD23 52 — LCD22 53 — LCD21 54 — LCD20 55 LCD19 56 LCD18 57 LCD17 58 LCD16 59 41 PTE7 LCD15 60 42 PTE6 LCD14 61 43 PTE5 LCD13 62 44 PTE4 LCD12 63 45 PTE3 LCD11 64 46 PTE2 LCD10 3 Electrical Characteristics 3.1 Introduction This section contains electrical and timing specifications for the MC9S08LL16 series of microcontrollers available at the time of publication. 3.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 9

Electrical Characteristics Table3. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant C sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices T under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the programmable SS DD pull-up resistor associated with the pin is enabled. Table4. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage V –0.3 to 3.8 V DD Maximum current into V I 120 mA DD DD Digital input voltage V –0.3 to V +0.3 V In DD Instantaneous maximum current I ± 25 mA D Single pin limit (applies to all port pins)1,2,3 Storage temperature range T –55 to 150 °C stg 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (V ) and negative (V ) clamp DD SS voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTB2 are internally clamped to V and V . SS DD 3 Power supply must maintain regulation within operating V range during instantaneous and DD operating maximum current conditions. If positive injection current (V > V ) is greater than In DD I , the injection current may flow out of V and could result in external power supply going DD DD out of regulation. Ensure external V load will shunt current greater than maximum injection DD current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). MC9S08LL16 Series MCU Data Sheet, Rev. 7 10 Freescale Semiconductor

Electrical Characteristics 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine the difference between actual pin I/O voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high SS DD pin current (heavy loads), the difference between pin voltage and V or V will be very small. SS DD Table5. Thermal Characteristics Rating Symbol Value Unit Operating temperature range T to T T L H °C (packaged) A –40 to 85 Maximum junction temperature T 95 °C JM Thermal resistance Single-layer board 64-pin LQFP 72 48-pin QFN θ 84 °C/W JA 48-pin LQFP 81 Thermal resistance Four-layer board 64-pin LQFP 54 48-pin QFN θ 30 °C/W JA 48-pin LQFP 57 The average chip-junction temperature (T ) in °C can be obtained from: J T = T + (P × θ ) Eqn.3-1 J A D JA where: T = Ambient temperature, °C A θ = Package thermal resistance, junction-to-ambient, °C/W JA P = P + P D int I/O P = I × V , Watts — chip internal power int DD DD P = Power dissipation on input and output pins — user determined I/O For most applications, P << P and can be neglected. An approximate relationship between P and T I/O int D J (if P is neglected) is: I/O P = K ÷ (T + 273°C) Eqn.3-2 D J Solving Equation 3-1 and Equation 3-2 for K gives: K = P × (T + 273°C) + θ × (P )2 Eqn.3-3 D A JA D MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 11

Electrical Characteristics where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by D A D J solving Equation 3-1 and Equation 3-2 iteratively for any value of T . A 3.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification. Table6. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Series resistance R1 1500 Ω Human Storage capacitance C 100 pF Body Model Number of pulses per pin — 3 Series resistance R1 0 Ω Charge Device Storage capacitance C 200 pF Model Number of pulses per pin — 3 Minimum input voltage limit –2.5 V Latch-up Maximum input voltage limit 7.5 V Table7. ESD and Latch-Up Protection Characteristics No. Rating1 Symbol Min Max Unit 1 Human body model (HBM) VHBM ±2000 — V 2 Charge device model (CDM) VCDM ±500 — V 3 Latch-up current at TA = 85°C ILAT ±100 — mA 1 Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. MC9S08LL16 Series MCU Data Sheet, Rev. 7 12 Freescale Semiconductor

Electrical Characteristics 3.6 DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table8. DC Characteristics Num C Characteristic Symbol Condition Min Typ1 Max Unit 1 Operating voltage 1.8 3.6 V PTA[0:3], PTA[6:7], V >1.8 V C PTB[0:7], PTC[0:7]2, DD V – 0.5 — — I = –0.6 mA DD low-drive strength Load Output high 2 V V > 2.7 V V P voltage PTA[0:3], PTA[6:7], OH I DD = –10 mA VDD – 0.5 — — PTB[0:7], PTC[0:7]2, Load V > 1.8 V C high-drive strength DD V – 0.5 — — I = –3 mA DD Load PTA[4:5], PTD[0:7], V > 1.8 V C PTE[0:7], DD V – 0.5 — — I = –0.5 mA DD low-drive strength Load Output high 3 V V > 2.7 V V P voltage PTA[4:5], PTD[0:7], OH I DD = –3 mA VDD – 0.5 — — Load PTE[0:7], V > 1.8 V C high-drive strength DD V – 0.5 — — I = –1 mA DD Load Output high 4 D Max total I for all ports I — — 100 mA current OH OHT PTA[0:3], PTA[6:7], V >1.8 V C PTB[0:7], PTC[0:7], DD — — 0.5 I = 0.6 mA low-drive strength Load Output low 5 V V > 2.7 V V P voltage PTA[0:3], PTA[6:7], OL DD — — 0.5 I = 10 mA Load PTB[0:7], PTC[0:7], V > 1.8 V C high-drive strength DD — — 0.5 I = 3 mA Load PTA[4:5], PTD[0:7], V > 1.8 V C PTE[0:7], DD — — 0.5 I = 0.5 mA low-drive strength Load Output low 6 V V > 2.7 V V P voltage PTA[4:5], PTD[0:7], OL DD — — 0.5 I = 3 mA Load PTE[0:7], V > 1.8 V C high-drive strength DD — — 0.5 I = 1 mA Load Output low 7 D Max total I for all ports I — — 100 mA current OL OLT P Input high all digital inputs VDD > 2.7 V 0.70 × VDD — — 8 V C voltage IH V > 1.8 V 0.85 × V — — DD DD V P Input low all digital inputs VDD > 2.7 V — — 0.35 x VDD 9 V C voltage IL V > 1.8 V — — 0.30 x V DD DD Input all digital inputs 10 C V 0.06 × V — — mV hysteresis hys DD MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 13

Electrical Characteristics Table8. DC Characteristics (continued) Num C Characteristic Symbol Condition Min Typ1 Max Unit all input only pins except for V = V — 0.025 1 μA In DD LCD only pins (LCD 16-29) Input leakage VIn = VSS — 0.025 1 μA 11 P |I | current In V = V — 100 150 μA In DD LCD only pins (LCD 16-29) V = V — 0.025 1 μA In SS Hi-Z (off-state) all input/output 12 P leakage (per pin) |IOZ| VIn = VDD or VSS — 0.025 1 μA current Total leakage Total leakage current for all — 13 P current3 pins |IInT| VIn = VDD or VSS — 2 μA Pullup, PTA[0:3], PTA[6:7], P 52.5 pulldown PTB[0:7], PTC[0:7] R 14 PU, — 17.5 — kΩ resistors when PTA[4:5], PTD[0:7], RPD P 69.5 enabled PTE[0:7] Single pin limit –0.2 — 0.2 mA DC injection 15 D current 4, 5, 6 Total MCU limit, includes IIC VIN < VSS, VIN > VDD –5 — 5 mA sum of allstressed pins 16 C Input capacitance, all pins C — — 8 pF In 17 C RAM retention voltage V — 0.6 1.0 V RAM 18 C POR re-arm voltage7 V 0.9 1.4 2.0 V POR 19 D POR re-arm time t 10 — — μs POR V falling 1.80 1.84 1.88 20 P Low-voltage detection threshold V DD V LVD V rising 1.88 1.92 1.96 DD V falling 21 P Low-voltage warning threshold V DD 2.08 2.14 2.2 V LVW V rising DD 22 P Low-voltage inhibit reset/recover hysteresis V — 80 — mV hys 23 P Bandgap voltage reference8 V 1.15 1.17 1.18 V BG 1 Typical values are measured at 25 °C. Characterized, not tested 2 All I/O pins except for LCD pins in open drain mode. 3 Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250 nA. 4 All functional non-supply pins, except for PTB2 are internally clamped to V and V . SS DD 5 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6 Power supply must maintain regulation within operating V range during instantaneous and operating maximum current DD conditions. If the positive injection current (V > V ) is greater than I , the injection current may flow out of V and could In DD DD DD result in external power supply going out of regulation. Ensure that external V load will shunt current greater than maximum DD injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 7 POR will occur below the minimum voltage. 8 Factory trimmed at V = 3.0 V, Temp = 25 °C. DD MC9S08LL16 Series MCU Data Sheet, Rev. 7 14 Freescale Semiconductor

Electrical Characteristics Figure4. Non-LCD pins I/O Pullup and Pulldown Typical Resistor Values (V = 3.0 V) DD MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 15

Electrical Characteristics Figure5. LCD/GPIO Pins I/O Pullup/Pulldown Typical Resistor Values MC9S08LL16 Series MCU Data Sheet, Rev. 7 16 Freescale Semiconductor

Electrical Characteristics Figure6. Typical Low-Side Driver (Sink) Characteristics (Non-LCD pins) — Low Drive (PTxDSn = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 17

Electrical Characteristics Figure7. Typical Low-Side Driver (Sink) Characteristics(Non-LCD pins) — High Drive (PTxDSn = 1) MC9S08LL16 Series MCU Data Sheet, Rev. 7 18 Freescale Semiconductor

Electrical Characteristics Figure8. Typical High-Side (Source) Characteristics (Non-LCD Pins) — Low Drive (PTxDSn = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 19

Electrical Characteristics Figure9. Typical High-Side (Source) Characteristics(Non-LCD Pins) — High Drive (PTxDSn = 1) MC9S08LL16 Series MCU Data Sheet, Rev. 7 20 Freescale Semiconductor

Electrical Characteristics Preliminary I (mA) OL Figure10. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins) — Low Drive (PTxDSn = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 21

Electrical Characteristics Figure11. Typical Low-Side Driver (Sink) Characteristics(LCD/GPIO Pins) — High Drive (PTxDSn = 1) MC9S08LL16 Series MCU Data Sheet, Rev. 7 22 Freescale Semiconductor

Electrical Characteristics Figure12. Typical High-Side (Source) Characteristics (LCD/GPIO Pins) — Low Drive (PTxDSn = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 23

Electrical Characteristics Figure13. Typical High-Side (Source) Characteristics(LCD/GPIO pins) — High Drive (PTxDSn = 1) MC9S08LL16 Series MCU Data Sheet, Rev. 7 24 Freescale Semiconductor

Electrical Characteristics 3.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table9. Supply Current Characteristics Num C Parameter Symbol Bus VDD Typ1 Max Unit Temp Freq (V) (°C) P Run supply current 8 MHz 4.2 5.7 mA 1 RI –40 to 85 °C T FEI mode, all modules on DD 1 MHz 3 1 1.52 T Run supply current 10 MHz 3.60 — 2 RI mA –40 to 85 °C T FEI mode, all modules off DD 1 MHz 3 0.50 — 16 kHz T 165 — Run supply current FBILP 3 RI 3 μA –40 to 85 °C LPRS=0, all modules off DD 16 kHz T 105 — FBELP 16 kHz T Run supply current FBILP 77 — 4 LPRS=1, all modules off; running RI 3 μA –40 to 85 °C DD 16 kHz T from Flash 21 — FBELP 16 kHz T Run supply current FBILP 77 — 5 LPRS=1, all modules off; running RI 3 μA –40 to 85 °C DD 16 kHz T from RAM 7.3 — FBELP P Wait mode supply current 8 MHz 1.4 3.5 6 WI 3 mA –40 to 85 °C C FEI mode, all modules off DD 1 MHz 0.8 1.15 Wait mode supply current WI 16 kHz 3 1.3 — μA –40 to 85 °C 7 T DD LPRS = 1, all modules off FBELP 350 930 –40 to 25 °C 1000 — 50 °C P n/a 3 2500 4000 70 °C 8 Stop2 mode supply current S2I 5100 — nA 85 °C DD 250 — –40 to 25 °C C n/a 2 2000 — 70 °C 4000 — 85 °C 400 1030 –40 to 25 °C 1300 — 50 °C P n/a 3 4000 6000 70 °C Stop3 mode supply current 9 S3I 8000 — nA 85 °C No clocks active DD 350 — –40 to 25 °C C n/a 2 3000 — 70 °C 6000 — 85 °C MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 25

Electrical Characteristics Table9. Supply Current Characteristics (continued) Num C Parameter Symbol Bus VDD Typ1 Max Unit Temp Freq (V) (°C) Application Stop3 mode supply 10 C current2 ApS3IDD n/a 3 6.1 — μA 25 °C Application Stop3 mode supply 11 C current2 ApS3IDD n/a 3 7.5 — μA 50 °C 1 Typical values are measured at 25 °C. Characterized, not tested. 2 32 kHz crystal enabled in low power mode. TOD module enabled. V enabled for 3 V LCD glass 500pf 8x24 LCD glass at IREG 32 Hz frame rate with LCD Charge pump clock set to low setting and every other segment “on.” Table10. Stop Mode Adders Temperature (°C) Num C Parameter Condition Units –40 25 70 85 1 T LPO 100 100 150 175 nA 2 T ERREFSTEN RANGE=HGO=0 250 360 400 460 nA 3 T IREFSTEN1 63 70 77 81 μA 4 T TOD Does not include clock source current 50 50 75 100 nA 5 T LVD1 LVDSE=1 110 110 112 115 μA 6 T ACMP1 Not using the bandgap (BGBE=0) 12 12 20 23 μA ADLPC=ADLSMP=1 7 T ADC1 95 95 101 120 μA Not using the bandgap (BGBE=0) VIREG enabled for Contrast control, 1/8 Duty cycle, 8x24 configuration for 8 T LCD 1 1 4.2 12 μA driving 192 Segments, 32Hz frame rate, No LCD glass connected. 1 Not available in stop2 mode. MC9S08LL16 Series MCU Data Sheet, Rev. 7 26 Freescale Semiconductor

Electrical Characteristics 3.8 External Oscillator (XOSCVLP) Characteristics Refer to Figure 14 and Figure 15 for crystal or resonator circuits. Table11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85 °C Ambient) Num C Characteristic Symbol Min Typ1 Max Unit Oscillator crystal or resonator (EREFS=1, ERCLKEN = 1) Low range (RANGE = 0) flo 32 — 38.4 kHz 1 C High range (RANGE = 1), high gain (HGO = 1) fhi 1 — 16 MHz High range (RANGE = 1), low power (HGO = 0) f 1 — 8 MHz hi Load capacitors Low range (RANGE=0), low power (HGO=0) See Note 2 2 D Other oscillator settings C1,C2 See Note 3 Feedback resistor Low range, low power (RANGE=0, HGO=0)2 — — — 3 D R MΩ Low range, high gain (RANGE=0, HGO=1) F — 10 — High range (RANGE=1, HGO=X) — 1 — Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 — — — Low range, high gain (RANGE = 0, HGO = 1) — 100 — High range, low power (RANGE = 1, HGO = 0) — 0 — 4 D High range, high gain (RANGE = 1, HGO = 1) RS kΩ ≥ 8 MHz — 0 0 4 MHz — 0 10 1 MHz — 0 20 Crystal start-up time 4 Low range, low power — 600 — t 5 C Low range, high gain CSTL — 400 — ms High range, low power — 5 — t High range, high gain CSTH — 15 — Square wave input clock frequency (EREFS=0, ERCLKEN = 1) 6 D FEE mode fextal 0.03125 — 20 MHz FBE or FBELP mode 0 — 20 MHz 1 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. 2 Load capacitors (C C ), feedback resistor (R ) and series resistor (R ) are incorporated internally when RANGE=HGO=0. 1, 2 F S 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 27

Electrical Characteristics XOSCVLP EXTAL XTAL R R S F Crystal or Resonator C 1 C 2 Figure14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain XOSCVLP EXTAL XTAL Crystal or Resonator Figure15. Typical Crystal or Resonator Circuit: Low Range/Low Power 3.9 Internal Clock Source (ICS) Characteristics Table12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) Num C Characteristic Symbol Min Typ1 Max Unit Average internal reference frequency — factory trimmed at 1 P VDD = 3.6 V and temperature = 25 °C fint_ft — 32.768 — kHz 2 P Average internal reference frequency - trimmed fint_t 31.25 — 39.063 kHz 3 T Internal reference start-up time tIRST — — 6 μs 4 P DCO output frequency range - untrimmed fdco_ut 12.8 16.8 21.33 MHz 5 P DCO output frequency range - trimmed fdco_t 16 — 20 MHz Resolution of trimmed DCO output frequency at fixed 6 C voltage and temperature (using FTRIM) Δfdco_res_t — ±0.1 ±0.2 %fdco Resolution of trimmed DCO output frequency at fixed 7 C voltage and temperature (not using FTRIM) Δfdco_res_t — ±0.2 ±0.4 %fdco Total deviation from trimmed DCO output frequency over + 0.5 8 C voltage and temperature Δfdco_t — –1.0 ±2 %fdco MC9S08LL16 Series MCU Data Sheet, Rev. 7 28 Freescale Semiconductor

Electrical Characteristics Table12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued) Num C Characteristic Symbol Min Typ1 Max Unit Total deviation from trimmed DCO output frequency over 9 C fixed voltage and temperature range of 0°C to 70 °C Δfdco_t — ±0.5 ±1 %fdco 10 C FLL acquisition time 2 tAcquire — — 1 ms Long term jitter of DCO output clock (averaged over 2-ms 11 C interval) 3 CJitter — 0.02 0.2 %fdco 1 Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value. 2 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . Bus Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via V and V and variation in the crystal oscillator frequency increase the C DD SS Jitter percentage for a given interval. Figure16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V) MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 29

Electrical Characteristics 3.10 AC Characteristics This section describes timing characteristics for each peripheral system. 3.10.1 Control Timing Table13. Control Timing Num C Rating Symbol Min Typ1 Max Unit 1 D Bus frequency (tcyc = 1/fBus) fBus dc — 10 MHz 2 D Internal low power oscillator period tLPO 700 — 1300 μs 3 D External reset pulse width2 textrst 100 — — ns 4 D Reset low drive trstdrv 34 × tcyc — — ns BKGD/MS setup time after issuing background debug 500 5 D force reset to enter user or BDM modes tMSSU — — ns BKGD/MS hold time after issuing background debug 100 6 D force reset to enter user or BDM modes 3 tMSH — — μs IRQ pulse width 7 D Asynchronous path2 t t 100 — — ns ILIH, IHIL Synchronous path4 1.5 × t — — cyc D Keyboard interrupt pulse width 8 Asynchronous path2 t t 100 — — ns ILIH, IHIL Synchronous path4 1.5 × t — — cyc Port rise and fall time — Non-LCD Pins Low output drive (PTxDS = 0) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) tRise, tFall — 16 — ns Slew rate control enabled (PTxSE = 1) — 23 — 9 C Port rise and fall time — Non-LCD Pins High output drive (PTxDS = 1) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) tRise, tFall — 5 — ns Slew rate control enabled (PTxSE = 1) — 9 — 10 C Voltage Regulator Recovery time tVRR — 6 10 us 1 Typical values are based on characterization data at V = 3.0 V, 25 °C unless otherwise stated. DD 2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t after V MSH DD rises above V . LVD 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5 Timing is shown with respect to 20% V and 80% V levels. Temperature range –40 °C to 85 °C. DD DD 6 Except for LCD pins in Open Drain mode. MC9S08LL16 Series MCU Data Sheet, Rev. 7 30 Freescale Semiconductor

Electrical Characteristics t extrst RESET PIN Figure17. Reset Timing t IHIL IRQ/KBIPx IRQ/KBIPx t ILIH Figure18. IRQ/KBIPx Timing 3.10.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table14. TP Input Timing No. C Function Symbol Min Max Unit 1 D External clock frequency f 0 f /4 Hz TCLK Bus 2 D External clock period t 4 — t TCLK cyc 3 D External clock high time t 1.5 — t clkh cyc 4 D External clock low time t 1.5 — t clkl cyc 5 D Input capture pulse width t 1.5 — t ICPW cyc t TCLK t clkh TCLK t clkl Figure19. Timer External Clock MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 31

Electrical Characteristics t ICPW TPMCHn TPMCHn t ICPW Figure20. Timer Input Capture Pulse 3.10.3 SPI Timing Table 15 and Figure21 through Figure 24 describe the timing requirements for the SPI system. Table15. SPI Timing No. C Function Symbol Min Max Unit — Operating frequency D Master f f /2048 f /2 Hz op Bus Bus Slave 0 f /4 Bus SPSCK period 1 D Master tSPSCK 2 2048 tcyc Slave 4 — t cyc Enable lead time 2 D Master tLead 1/2 — tSPSCK Slave 1 — t cyc Enable lag time 3 D Master tLag 1/2 — tSPSCK Slave 1 — t cyc Clock (SPSCK) high or low time 4 D Master tWSPSCK tcyc – 30 1024 tcyc ns Slave t – 30 — ns cyc Data setup time (inputs) 5 D Master tSU 15 — ns Slave 15 — ns Data hold time (inputs) 6 D Master tHI 0 — ns Slave 25 — ns D Slave access time t — 1 t 7 a cyc D Slave MISO disable time t — 1 t 8 dis cyc Data valid (after SPSCK edge) 9 D Master tv — 25 ns Slave — 25 ns MC9S08LL16 Series MCU Data Sheet, Rev. 7 32 Freescale Semiconductor

Electrical Characteristics Table15. SPI Timing (continued) No. C Function Symbol Min Max Unit Data hold time (outputs) 10 D Master tHO 0 — ns Slave 0 — ns Rise time 11 D Input tRI — tcyc – 25 ns Output t — 25 ns RO Fall time 12 D Input tFI — tcyc – 25 ns Output t — 25 ns FO SS1 (OUTPUT) 2 1 11 3 SPSCK 4 (CPOL = 0) (OUTPUT) 4 12 SPSCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MS BIN2 BIT 6 . . . 1 LSB IN 9 9 10 MOSI (OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure21. SPI Master Timing (CPHA = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 33

Electrical Characteristics SS1 (OUTPUT) 1 2 12 11 3 SPSCK (CPOL = 0) (OUTPUT) 4 4 11 12 SPSCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 9 10 MOSI PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA (OUTPUT) NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure22. SPI Master Timing (CPHA =1) SS (INPUT) 1 12 11 3 SPSCK (CPOL = 0) (INPUT) 2 4 4 11 12 SPSCK (CPOL = 1) (INPUT) 8 7 9 10 10 MISO SEE (OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE 1 5 6 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally MSB of character just received. Figure23. SPI Slave Timing (CPHA = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 7 34 Freescale Semiconductor

Electrical Characteristics SS (INPUT) 1 3 2 12 11 SPSCK (CPOL = 0) (INPUT) 4 4 11 12 SPSCK (CPOL = 1) (INPUT) 9 10 8 MISO SEE (OUTPUT) NOTE 1 SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT 7 5 6 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received. Figure24. SPI Slave Timing (CPHA = 1) 3.11 Analog Comparator (ACMP) Electricals Table16. Analog Comparator Electrical Specifications C Characteristic Symbol Min Typical Max Unit D Supply voltage VDD 1.8 — 3.6 V C Supply current (active) IDDAC — 20 35 μA D Analog input voltage V V – 0.3 — V V AIN SS DD P Analog input offset voltage V 20 40 mV AIO C Analog comparator hysteresis VH 3.0 9.0 15.0 mV P Analog input leakage current IALKG — — 1.0 μA C Analog comparator initialization delay t — — 1.0 μs AINIT 3.12 ADC Characteristics Table17. 12-bit ADC Operating Conditions Characteristic Conditions Symb Min Typ1 Max Unit Comment Absolute V 1.8 — 3.6 V DDA Supply voltage Delta to V (V –V )2 ΔV –100 0 100 mV DD DD DDA DDA Ground voltage Delta to V (V –V )2 ΔV –100 0 100 mV SS SS SSA SSA MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 35

Electrical Characteristics Table17. 12-bit ADC Operating Conditions Characteristic Conditions Symb Min Typ1 Max Unit Comment Ref Voltage V 1.8 V V V High REFH DDA DDA Input Voltage V V — V V ADIN REFL REFH Input C — 4.5 5.5 pF Capacitance ADIN Input R — 5 7 kΩ Resistance ADIN 12-bit mode f > 4MHz — — 2 ADCK f < 4MHz — — 5 ADCK Analog Source 10-bit mode R kΩ External to MCU Resistance AS f > 4MHz — — 5 ADCK f < 4MHz — — 10 ADCK 8-bit mode (all valid f ) — — 10 ADCK ADC High speed (ADLPC = 0) 0.4 — 8.0 Conversion f MHz ADCK Clock Freq. Low power (ADLPC = 1) 0.4 — 4.0 1 Typical values assume V = 3.0 V, Temp = 25 °C, f =1.0 MHz unless otherwise stated. Typical values are for DDA ADCK reference only and are not tested in production. 2 DC potential difference. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad ZAS leakage CHANNEL SELECT due to CIRCUIT ADC SAR R input R ENGINE AS protection ADIN + V ADIN – C V + AS AS – R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure25. ADC Input Impedance Equivalency Diagram MC9S08LL16 Series MCU Data Sheet, Rev. 7 36 Freescale Semiconductor

Electrical Characteristics Table18. 12-bit ADC Characteristics (V = V , V = V ) REFH DDA REFL SSA C Characteristic Conditions Symb Min Typ1 Max Unit Comment Supply Current ADLPC=1 T I — 120 — μA ADLSMP=1 DDA ADCO=1 Supply Current ADLPC=1 T I — 200 — μA ADLSMP=0 DDA ADCO=1 Supply Current ADLPC=0 T I — 290 — μA ADLSMP=1 DDA ADCO=1 Supply Current ADLPC=0 P I — 0.53 1 mA ADLSMP=0 DDA ADCO=1 P ADC High Speed (ADLPC=0) 2 3.3 5 t = Asynchronous f MHz ADACK ADACK 1/f C Clock Source Low Power (ADLPC=1) 1.25 2 3.3 ADACK P Conversion Short Sample (ADLSMP=0) — 20 — See ADC ADCK Time (Including t chapter in the ADC cycles C sample time) Long Sample (ADLSMP=1) — 40 — LL16 Reference P Short Sample (ADLSMP=0) — 3.5 — Manual for ADCK Sample Time tADS cycles conversion C Long Sample (ADLSMP=1) — 23.5 — time variances 12-bit mode, –2.5 to T — –1 to 3 3.6>VDDA>2.7V 5.5 Total 12-bit mode, –3.0 to Unadjusted 2.7>VDDA>1.8V ETUE — –1 to 3 6.0 LSB2 quIanncltuizdaetiso n Error P 10-bit mode — ±1 ±2.5 T 8-bit mode — ±0.5 ±1.0 –1.5 to T 12-bit mode — ±1 2.0 Differential DNL LSB2 P Non-Linearity 10-bit mode3 — ±0.5 ±1.0 T 8-bit mode3 — ±0.3 ±0.5 –2.5 to T 12-bit mode — ±1.5 1.0 Integral INL LSB2 P Non-Linearity 10-bit mode — ±0.5 ±1.0 T 8-bit mode — ±0.3 ±0.5 MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 37

Electrical Characteristics Table18. 12-bit ADC Characteristics (V = V , V = V ) (continued) REFH DDA REFL SSA C Characteristic Conditions Symb Min Typ1 Max Unit Comment T 12-bit mode — ±1.5 ±2.5 Zero-Scale P 10-bit mode E — ±0.5 ±1.5 LSB2 V = V Error ZS ADIN SSA T 8-bit mode — ±0.5 ±0.5 –3.5 to T 12-bit mode — ±1 1.0 Full-Scale E LSB2 V = V P Error 10-bit mode FS — ±0.5 ±1 ADIN DDA T 8-bit mode — ±0.5 ±0.5 12-bit mode — –1 to 0 — Quantization D 10-bit mode E — — ±0.5 LSB2 Error Q 8-bit mode — — ±0.5 12-bit mode — ±2 — Input Leakage Pad leakage4 * D 10-bit mode E — ±0.2 ±4 LSB2 Error IL R AS 8-bit mode — ±0.1 ±1.2 –40 °C to 25 °C — 1.646 — Temp Sensor D m mV/°C Slope 25 °C to 85 °C — 1.769 — Temp Sensor D 25 °C V — 701.2 — mV Voltage TEMP25 1 Typical values assume V = 3.0 V, Temp = 25 °C, f =1.0 MHz unless otherwise stated. Typical values are for reference DDA ADCK only and are not tested in production. 2 1 LSB = (V – V )/2N REFH REFL 3 Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes 4 Based on input pad leakage current. Refer to pad electricals. MC9S08LL16 Series MCU Data Sheet, Rev. 7 38 Freescale Semiconductor

Electrical Characteristics 3.13 LCD Specifications Table19. LCD Electricals, 3 V Glass C Characteristic Symbol Min Typ Max Unit D LCD Supply Voltage V V LCD 0.9 1.5 1.8 D LCD Frame Frequency f 28 30 58 Hz Frame D LCD Charge Pump Capacitance C 100 100 nF LCD D LCD Bypass Capacitance C 100 100 nF BYLCD D LCD Glass Capacitance C 2000 8000 pF glass D V HRefSel = 0 V .89 1.00 1.15 IREG IREG V HRefSel = 1 1.49 1.67 1.851 D V TRIM Resolution Δ 1.5 % IREG RTRIM V IREG D V Ripple HRefSel = 0 0.1 IREG V HRefSel = 1 0.15 D V Buffered Adder2 I 1 μA LCD Buff 1 V Max can not exceed V – 0.15 V IREG DD 2 VSUPPLY = 10, BYPASS = 0 3.14 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal V supply. DD For more detailed information about program/erase operations, see the Memory section. MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 39

Electrical Characteristics Table20. Flash Characteristics C Characteristic Symbol Min Typical Max Unit Supply voltage for program/erase D -40°C to 85°C V 1.8 3.6 V prog/erase D Supply voltage for read operation V 1.8 3.6 V Read D Internal FCLK frequency1 f 150 200 kHz FCLK D Internal FCLK period (1/FCLK) t 5 6.67 μs Fcyc P Byte program time (random location)2 t 9 t prog Fcyc P Byte program time (burst mode)2 t 4 t Burst Fcyc P Page erase time2 t 4000 t Page Fcyc P Mass erase time2 t 20,000 t Mass Fcyc D Byte program current3 RI — 4 — mA DDBP D Page erase current3 RI — 6 — mA DDPE Program/erase endurance4 C T to T = –40°C to + 85°C 10,000 — — cycles L H T = 25°C 100,000 — C Data retention5 t 15 100 — years D_ret 1 The frequency of this clock is controlled by a software setting. 2 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures DD with V = 3.0 V, bus frequency = 4.0 MHz. DD 4 Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 3.15 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 3.15.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). MC9S08LL16 Series MCU Data Sheet, Rev. 7 40 Freescale Semiconductor

Ordering Information The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table21. Radiated Emissions, Electric Field Level1 Parameter Symbol Conditions Frequency f /f Unit OSC BUS (Max) V V = 3.3 V 0.15 – 50 MHz 32 kHz crystal –7 dBμV RE_TEM DD T = 25 oC 10 MHz bus A 50 – 150 MHz –9 package type 64-pin LQFP 150 – 500 MHz –6 Radiated emissions, electric field 500 – 1000 MHz –6 IEC Level N — SAE Level 1 — 1 Data based on qualification test results. 4 Ordering Information This section contains the ordering information and the device numbering system for the MC9S08LL16 Series. 4.1 Device Numbering System Example of the device numbering system: MC9 S08 LL 16 C XX Status (MC = Fully Qualified) Package designator (see Table22) Temperature range Memory (C = –40 °C to 85 °C) (9 = Flash-based) Core Family Approximate FLASH size in KB 5 Package Information and Mechanical Drawings Table 22 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MC9S08LL16 Series Product Summary pages at http://www.freescale.com. To view the latest drawing, either: • Click on the appropriate link in Table 22, or • Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number (from Table 22) in the “Enter Keyword” search box at the top of the page. MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 41

Package Information and Mechanical Drawings Table22. Package Descriptions Pin Count Package Type Abbreviation Designator Case No. Document No. 64 Low Quad Flat Package LQFP LH 840F 98ASS23234W 48 Low Quad Flat Package LQFP LF 932 98ASH00962A 48 Quad Flat No-Leads QFN GT 1314 98ARH99048A MC9S08LL16 Series MCU Data Sheet, Rev. 7 42 Freescale Semiconductor

Package Information and Mechanical Drawings MC9S08LL16 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 43

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