Freescale Semiconductor MC9S08LL64 Rev. 7.1, 08/2012 MC9S08LL64 Series Data Sheet by: Automotive and Industrial Solutions Group This is the MC9S08LL64 Series Data Sheet set consisting of the following files: • MC9S08LL64 Data Sheet Addendum, Rev 1 • MC9S08LL64 Series Data Sheet, Rev 7 ©Freescale Semiconductor, Inc., 2012. All rights reserved.

Freescale Semiconductor MC9S08LL64AD Rev. 1, 08/2012 Data Sheet Addendum MC9S08LL64 Data Sheet Addendum by: Automotive and Industrial Solutions Group This document describes corrections to the Table of Contents MC9S08LL64 Series Data Sheet, order number 1 Addendum for Revision 7 . . . . . . . . . . . . . . . . . . . 2 2 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 2 MC9S08LL64. For convenience, the addenda items are grouped by revision. Please check our website at http://www.freescale.com for the latest updates. The current available version of the MC9S08LL64 Series Data Sheet is Revision 7. ©Freescale Semiconductor, Inc., 2012. All rights reserved.

Addendum for Revision 7 1 Addendum for Revision 7 Table1. MC9S08LL64 Data Sheet Rev 7 Addendum Location Description Section 3.7, “Supply Current In the table, for numbers 3 and 4, change “LPS” to “LPR”. Characteristics”/Table 9/Page 23 Section 3.12, “ADC Add the following data of the ADC conversion clock frequency: Characteristics”/Page 33 Characteris Conditions Symb Min Typ Max Unit tic ADC ADLPC=0, ADHSC=1 f 1.0 — 8 MHz ADCK Conversion ADLPC=0, ADHSC=0 1.0 — 5 Clock Frequency ADLPC=1, ADHSC=0 1.0 — 2.5 2 Revision History Table 2 provides a revision history for this document. Table2. Revision History Table Rev. Number Substantive Changes Date of Release 1.0 Initial release. Correct errors in the following sections: 07/2012 (cid:129) Section 3.7, “Supply Current Characteristics” (cid:129) Section 3.12, “ADC Characteristics” MC9S08LL64 Data Sheet Addendum, Rev. 1 2 Freescale Semiconductor

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Freescale Semiconductor Document Number: MC9S08LL64 Data Sheet: Technical Data Rev. 7, 4/2012 An Energy Efficient Solution by Freescale MC9S08LL64 Series 64-LQFP 80-LQFP Case 840F Case 917A Covers: MC9S08LL64 and MC9S08LL36 • 8-Bit HCS08 Central Processor Unit (CPU) – Up to 40 MHz CPU at 3.6V to 2.1V across temperature • Peripherals range of –40 °C to 85 °C – LCD — Up to 8×36 or 4×40 LCD driver with internal – Up to 20MHz at 2.1V to 1.8V across temperature range charge pump and option to provide an of –40 °C to 85 °C internally-regulated LCD reference that can be trimmed – HC08 instruction set with added BGND instruction for contrast control – Support for up to 32 interrupt/reset sources – ADC —10-channel, 12-bit resolution; up to 2.5μs • On-Chip Memory conversion time; automatic compare function; – Dual array flash read/program/erase over full operating temperature sensor; operation in stop3; fully functional voltage and temperature from 3.6V to 1.8V – Random-access memory (RAM) – IIC — Inter-integrated circuit bus module to operate at up – Security circuitry to prevent unauthorized access to RAM to 100kbps with maximum bus loading; multi-master and flash contents operation; programmable slave address; interrupt-driven • Power-Saving Modes byte-by-byte data transfer; broadcast mode; 10-bit – Two low-power stop modes addressing – Reduced-power wait mode – ACMP — Analog comparator with selectable interrupt on – Low-power run and wait modes allow peripherals to run rising, falling, or either edge of comparator output; while voltage regulator is in standby compare option to fixed internal reference voltage; – Peripheral clock gating register can disable clocks to outputs can be optionally routed to TPM module; unused modules, thereby reducing currents operation in stop3 – Very low-power external oscillator that can be used in – SCIx — Two full-duplex non-return to zero (NRZ) stop2 or stop3 modes to provide accurate clock source to modules (SCI1 and SCI2); LIN master extended break time-of-day (TOD) module generation; LIN slave extended break detection; wakeup – 6 μs typical wakeup time from stop3 mode on active edge • Clock Source Options – SPI — Full-duplex or single-wire bidirectional; – Oscillator (XOSC) — Loop-control Pierce oscillator; double-buffered transmit and receive; master or slave crystal or ceramic resonator range of 31.25kHz to mode; MSB-first or LSB-first shifting 38.4kHz or 1MHz to 16MHz – TPMx — Two 2-channel (TPM1 and TPM2); selectable – Internal Clock Source (ICS) — Internal clock source input capture, output compare, or buffered edge- or module containing a frequency-locked-loop (FLL) center-aligned PWM on each channel controlled by internal or external reference; precision – TOD — (Time-of-day) 8-bit, quarter second counter with trimming of internal reference allows 0.2% resolution and match register; external clock source for precise time 2% deviation over temperature and voltage; supporting base, time-of-day, calendar, or task scheduling functions bus frequencies from 1MHz to 20MHz – VREFx—Trimmable via an 8-bit register in 0.5 mV • System Protection steps; automatically loaded with room temperature value – Watchdog computer operating properly (COP) reset with upon reset; can be enabled to operate in stop3 mode; option to run from dedicated 1 kHz internal clock source trim register is not available in stop modes. or bus clock • Input/Output – Low-voltage warning with interrupt – Dedicated accurate voltage reference output pin, 1.15V – Low-voltage detection with reset or interrupt output (VREFOx); trimmable with 0.5mV resolution – Illegal opcode detection with reset; illegal address – Up to 39 GPIOs, two output-only pins detection with reset – Hysteresis and configurable pullup device on all input – Flash block protection pins; configurable slew rate and drive strength on all • Development Support output pins – Single-wire background debug interface • Package Options – Breakpoint capability to allow single breakpoint setting – 14mm × 14mm80-pin LQFP, 10mm ×10mm64-pin during in-circuit debugging (plus two more breakpoints in LQFP on-chip debug module) – On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes ©Freescale Semiconductor, Inc., 2009-2012. All rights reserved.

Contents 1 Devices in the MC9S08LL64 Series. . . . . . . . . . . . . . . . . . . . .3 3.10.2 TPM Module Timing. . . . . . . . . . . . . . . . . . . . . .29 2 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.10.3 SPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .33 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . . .9 3.13 VREF Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .9 3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .10 3.15 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.5 ESD Protection and Latch-Up Immunity. . . . . . . . . . . .11 3.16 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.16.1 Radiated Emissions. . . . . . . . . . . . . . . . . . . . . .40 3.7 Supply Current Characteristics. . . . . . . . . . . . . . . . . . .23 4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.8 External Oscillator (XOSCVLP) Characteristics. . . . . .25 4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .41 3.9 Internal Clock Source (ICS) Characteristics. . . . . . . . .26 4.2 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.10.1 Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . .28 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev Date Description of Changes 3 03/2009 Incorporated revisions for customer release. 4 08/2009 Completed all the TBDs; corrected Pin out in the Figure2, Figure3 and Table2; updated V , OH |I |, |I |, R , R , added |I | in the Table8; updated Table9; updated ERREFSTEN and In OZ PU PD INT added LCD in the Table10; updated f , E , DNL, INL, E and E in the Table18. ADACK TUE ZS FS updated V Room Temp in the Table19. 5 1/2010 Added 80-pin LQFP package information for MC9S08LL36. 6 6/2011 Changed the ERREFSTEN to EREFSTEN, updated the VREFOx to 1.15 V Added LCD specification in the Table10. 7 4/2012 Updated |I | in the Table8. In Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual —MC9S08LL64RM Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. ©Freescale Semiconductor, Inc., 2009-2012. All rights reserved.

1 Devices in the MC9S08LL64 Series Table1 summarizes the feature set available in the MC9S08LL64 series of MCUs. Table1. MC9S08LL64 Series Features by MCU and Package Feature MC9S08LL64 MC9S08LL36 80-pin 64-pin 80-pin 64-pin Package LQFP LQFP LQFP LQFP 64 KB 36 KB FLASH (32,768 and 32,768 Arrays) (24,576 and 12,288 Arrays) RAM 4000 4000 ACMP yes yes ADC 10-ch 8-ch 10-ch 8-ch IIC yes yes IRQ yes yes KBI 8 8 SCI1 yes yes SCI2 yes yes SPI yes yes TPM1 2-ch 2-ch TPM2 2-ch 2-ch TOD yes yes 8×36 8×24 8×36 8×24 LCD 4×40 4×28 4×40 4×28 VREFO1 yes no yes no VREFO2 no yes no yes I/O pins1 39 37 39 37 1 The 39 I/O pins include two output-only pins and 18 LCD GPIO. The block diagram in Figure 1 shows the structure of the MC9S08LL64 series MCU. MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 3

HCS08 CORE ON-CHIP ICE PTA7/KBIP7/ADP11/ACMP– DEBUG MODULE (DBG) PTA6/KBIP6/ADP10/ACMP+ CPU INT PTA5/KBIP5/ADP9/LCD42 BKGD BKP TIME OF DAY MODULE RT A PTA4/KBIP4/ADP8/LCD43 (TOD) O PTA3/KBIP3/SCL/MOSI/ADP7 P PTA2/KBIP2/SDA/MISO/ADP6 KBI[7:0] HCS08 SYSTEM CONTROL 8-BIT KEYBOARD PTA1/KBIP1/SPSCK/ADP5 INTERRUPT (KBI) RESETS AND INTERRUPTS PTA0/KBIP0/SS/ADP4 MODES OF OPERATION BKGD/MS SS POWER MANAGEMENT SPSCK SERIAL PERIPHERAL MISO PTB7/TxD2/SS INTERFACE (SPI) PTB6/RxD2/SPSCK RESET MOSI COP IRQ SCL IRQ LVD IIC MODULE (IIC) SDA B PTB5/MOSI/SCL RT PTB4/MISO/SDA USER FLASH A O (LL64 = 32,768 BYTES) TPM2CH0 P (LL36 = 24,576 BYTES) 2-CHANNEL TIMER/PWM TPM2CH1 PTB2/RESET ∞ (TPM2) TCLK PTB1/XTAL USER FLASH B PTB0/EXTAL TPM1CH0 (LL64 = 32,768 BYTES) (LL36 = 12,288 BYTES) 2-CHANNEL TIMER/PWM TPM1CH1 PTC7/IRQ/TCLK (TPM1) TCLK PTC6/ACMPO//BKGD/MS◊ PTC5/TPM2CH1 USER RAM SERIAL COMMUNICATIONS TxD1 PTC4/TPM2CH0 RxD1 4 KB INTERFACE (SCI1) T C R O PTC3/TPM1CH1 P INTERNAL CLOCK SERIAL COMMUNICATIONS TxD2 PTC2/TPM1CH0 SOURCE (ICS) XTAL INTERFACE (SCI2) RxD2 PTC1/TxD1 PTC0/RxD1 LOW-POWER OSCILLATOR EXTAL • VDDA ADP[11:4] ADP0 ♦ VSSA 12-BIT ADP0 • ADP12 • ♦ VREFH ANALOG-TO-DIGITAL VREFL CONVERTER (ADC) ADP12 • VDD VOLTAGE RT D PTD[7:0]/LCD[7:0] VSS REGULATOR PO • VREFO1 VREF1 ANALOG COMPARATOR ACMP– ♦ VREFO2 VREF2 (ACMP) ACMP+ E VLCD ACMPO ORT PTE[7:0]/LCD[13:20] VLL1 NOTES P VLL2 • Pins are not available on 64-pin packages. LCD[8:12] and LCD[31:37] are VLL3 LIQUID CRYSTAL not available on the 64-pin package. VCAP1 DISPLAY ♦ V and V are internally connected to V and V for the 64-pin VCAP2 (LCD) paRcEkFaHge. VRREEFFOL2 is available only on the 64-pDiDnA packagSeS.A ∞ When PTB2 is configured as RESET, the pin becomes bi-directional with LCD[43:0] output being an open-drain drive. ◊ When PTC6 is configured as BKGD, the pin becomes bi-directional. Figure1. MC9S08LL64 Series Block Diagram MC9S08LL64 Series MCU Data Sheet, Rev. 7 4 Freescale Semiconductor

2 Pin Assignments This section shows the pin assignments for the This section shows the pin assignments for the MC9S08LL64 series devices. 567890 111112 DDDDDD CCCCCC 2/L3/L4/L5/L6/L7/L21222324252627282930 EEEEEEDDDDDDDDDD TTTTTTCCCCCCCCCC PPPPPPLLLLLLLLLL PTE1/LCD14 16463626160595857565554535251504948 LCD38 PTE0/LCD13 2 47 LCD39 PTD7/LCD7 3 46 LCD40 PTD6/LCD6 4 45 LCD41 PTD5/LCD5 5 44 PTA5/KBIP5/ADP9/LCD42 PTD4/LCD4 6 43 PTA4/KBIP4/ADP8/LCD43 PTD3/LCD3 7 64-Pin LQFP 42 PTA3/KBIP3/SCL/MOSI/ADP7 PTD2/LCD2 8 41 PTA2/KBIP2/SDA/MISO/ADP6 PTD1/LCD1 9 40 PTA1/KBIP1/SPSCK/ADP5 PTD0/LCD0 10 39 PTA0/KBIP0/SS/ADP4 VCAP1 11 38 PTC7/IRQ/TCLK V CAP2 12 37 PTC6/ACMPO/BKGD/MS V LL1 13 36 PTC5/TPM2CH1 V LL2 14 35 PTC4/TPM2CH0 V LL3 15 34 PTC3/TPM1CH1 V LCD 16 33 PTC2/TPM1CH0 7890123456789012 1112222222222333 +– L HLL D ST2ALKS11 DP10/ACMPDP11/ACMPV/VSSAREFV/VDDAREFPTB0/EXTAPTB1/XTAVDVSPTB2/RESEVREFOB4/MISO/SDB5/MOSI/SCRxD2/SPSCTB7/TxD2/SPTC0/RxDPTC1/TxD AA TT6/P 6/7/ PPB PP T BIBI P KK 6/7/ AA TT PP Figure2. 64-Pin LQFP MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 5

4567890 1111112 DDDDDDD CCCCCCC E1/LE2/LE3/LE4/LE5/LE6/LE7/LD21D22D23D24D25D26D27D28D29D30D31D32D33 TTTTTTTCCCCCCCCCCCCC PPPPPPPLLLLLLLLLLLLL 09876543210987654321 PTE0/LCD13 18777777777766666666660 LCD34 LCD12 2 59 LCD35 LCD11 3 58 LCD36 LCD10 4 57 LCD37 LCD9 5 56 LCD38 LCD8 6 55 LCD39 PTD7/LCD7 7 54 LCD40 PTD6/LCD6 8 53 LCD41 PTD5/LCD5 9 80-Pin 52 PTA5/KBIP5/ADP9/LCD42 PTD4/LCD4 10 51 PTA4/KBIP4/ADP8/LCD43 LQFP PTD3/LCD3 11 50 PTA3/KBIP3/SCL/MOSI/ADP7 PTD2/LCD2 12 49 PTA2/KBIP2/SDA/MISO/ADP6 PTD1/LCD1 13 48 PTA1/KBIP1/SPSCK/ADP5 PTD0/LCD0 14 47 PTA0/KBIP0/SS/ADP4 VCAP1 15 46 PTC7/IRQ/TCLK VCAP2 16 45 PTC6/ACMPO/BKGD/MS VLL1 17 44 PTC5/TPM2CH1 VLL2 18 43 PTC4/TPM2CH0 VLL3 19 42 PTC3/TPM1CH1 VLCD 20 41 PTC2/TPM1CH0 12345678901234567890 22222222233333333334 DP10/ACMP+DP11/ACMP–VSSAVREFLADP0ADP12VREFO1VREFHVDDA PTB0/EXTALPTB1/XTALVDDVSSPTB2/RESETB4/MISO/SDAB5/MOSI/SCLRxD2/SPSCKTB7/TxD2/SSPTC0/RxD1PTC1/TxD1 AA TT6/P 6/7/ PPB PP T BIBI P KK 6/7/ AA TT PP Figure3. 80-Pin LQFP Table2. Pin Availability by Package Pin-Count <-- Lowest Priority --> Highest 80 64 Port Pin Alt 1 Alt 2 Alt3 Alt4 1 2 PTE0 LCD13 2 LCD12 3 LCD11 4 LCD10 5 LCD9 6 LCD8 MC9S08LL64 Series MCU Data Sheet, Rev. 7 6 Freescale Semiconductor

Table2. Pin Availability by Package Pin-Count (continued) <-- Lowest Priority --> Highest 80 64 Port Pin Alt 1 Alt 2 Alt3 Alt4 7 3 PTD7 LCD7 8 4 PTD6 LCD6 9 5 PTD5 LCD5 10 6 PTD4 LCD4 11 7 PTD3 LCD3 12 8 PTD2 LCD2 13 9 PTD1 LCD1 14 10 PTD0 LCD0 15 11 V CAP1 16 12 V CAP2 17 13 V LL1 18 14 V LL2 19 15 V LL3 20 16 V LCD 21 17 PTA6 KBIP6 ADP10 ACMP+ 22 18 PTA7 KBIP7 ADP11 ACMP– 23 V SSA 19 24 V REFL 25 ADP0 26 ADP12 27 VREFO1 28 V REFH 20 29 V DDA 30 21 PTB0 EXTAL 31 22 PTB1 XTAL 32 23 V DD 33 24 V SS 34 25 PTB2 RESET 26 VREFO2 35 27 PTB4 MISO SDA 36 28 PTB5 MOSI SCL 37 29 PTB6 RxD2 SPSCK 38 30 PTB7 TxD2 SS 39 31 PTC0 RxD1 40 32 PTC1 TxD1 41 33 PTC2 TPM1CH0 42 34 PTC3 TPM1CH1 43 35 PTC4 TPM2CH0 MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 7

Table2. Pin Availability by Package Pin-Count (continued) <-- Lowest Priority --> Highest 80 64 Port Pin Alt 1 Alt 2 Alt3 Alt4 44 36 PTC5 TPM2CH1 45 37 PTC6 ACMPO BKGD MS 46 38 PTC7 IRQ TCLK 47 39 PTA0 KBIP0 SS ADP4 48 40 PTA1 KBIP1 SPSCK ADP5 49 41 PTA2 KBIP2 SDA MISO ADP6 50 42 PTA3 KBIP3 SCL MOSI ADP7 51 43 PTA4 KBIP4 ADP8 LCD43 52 44 PTA5 KBIP5 ADP9 LCD42 53 45 LCD41 54 46 LCD40 55 47 LCD39 56 48 LCD38 57 LCD37 58 LCD36 59 LCD35 60 LCD34 61 LCD33 62 LCD32 63 LCD31 64 49 LCD30 65 50 LCD29 66 51 LCD28 67 52 LCD27 68 53 LCD26 69 54 LCD25 70 55 LCD24 71 56 LCD23 72 57 LCD22 73 58 LCD21 74 59 PTE7 LCD20 75 60 PTE6 LCD19 76 61 PTE5 LCD18 77 62 PTE4 LCD17 78 63 PTE3 LCD16 79 64 PTE2 LCD15 80 1 PTE1 LCD14 MC9S08LL64 Series MCU Data Sheet, Rev. 7 8 Freescale Semiconductor

Introduction 3 Electrical Characteristics 3.1 Introduction This section contains electrical and timing specifications for the MC9S08LL64 series of microcontrollers available at the time of publication. 3.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table3. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant C sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices T under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the programmable SS DD pullup resistor associated with the pin is enabled. MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 9

Thermal Characteristics Table4. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage V –0.3 to +3.8 V DD Maximum current into V I 120 mA DD DD Digital input voltage V –0.3 to V +0.3 V In DD Instantaneous maximum current I ± 25 mA D Single pin limit (applies to all port pins)1,2,3 Storage temperature range T –55 to 150 °C stg 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (V ) and negative (V ) clamp DD SS voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTB2 are internally clamped to V and V . SS DD 3 Power supply must maintain regulation within operating V range during instantaneous and DD operating maximum current conditions. If positive injection current (V > V ) is greater than In DD I , the injection current may flow out of V and could result in external power supply going DD DD out of regulation. Ensure external V load will shunt current greater than maximum injection DD current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine the difference between actual pin I/O voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high SS DD pin current (heavy loads), the difference between pin voltage and V or V will be very small. SS DD Table5. Thermal Characteristics Rating Symbol Value Unit Operating temperature range T to T T L H °C (packaged) A –40 to 85 Maximum junction temperature T 95 °C J Thermal resistance Single-layer board 80-pin LQFP 55 θ °C/W JA 64-pin LQFP 73 Thermal resistance Four-layer board 80-pin LQFP 42 θ °C/W JA 64-pin LQFP 54 The average chip-junction temperature (T ) in °C can be obtained from: J MC9S08LL64 Series MCU Data Sheet, Rev. 7 10 Freescale Semiconductor

ESD Protection and Latch-Up Immunity T = T + (P × θ ) Eqn.1 J A D JA where: T = Ambient temperature, °C A θ = Package thermal resistance, junction-to-ambient, °C/W JA P = P + P D int I/O P = I × V , Watts — chip internal power int DD DD P = Power dissipation on input and output pins — user determined I/O For most applications, P << P and can be neglected. An approximate relationship between P and T I/O int D J (if P is neglected) is: I/O P = K ÷ (T + 273°C) Eqn.2 D J Solving Equation 1 and Equation 2 for K gives: K = P × (T + 273°C) + θ × (P )2 Eqn.3 D A JA D where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by D A D J solving Equation 1 and Equation 2 iteratively for any value of T . A 3.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification. Table6. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Series resistance R1 1500 Ω Human Storage capacitance C 100 pF body model Number of pulses per pin — 3 Series resistance R1 0 Ω Charge device Storage capacitance C 200 pF model Number of pulses per pin — 3 MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 11

DC Characteristics Table6. ESD and Latch-up Test Conditions (continued) Model Description Symbol Value Unit Minimum input voltage limit –2.5 V Latch-up Maximum input voltage limit 7.5 V Table7. ESD and Latch-Up Protection Characteristics No. Rating1 Symbol Min Max Unit 1 Human body model (HBM) V ±2000 — V HBM 2 Charge device model (CDM) V ±500 — V CDM 3 Latch-up current at T = 85°C I ±100 — mA A LAT 1 Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. 3.6 DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table8. DC Characteristics Num C Characteristic Symbol Condition Min Typ1 Max Unit 1 Operating Voltage 1.8 3.6 V PTA[0:3], PTA[6:7], V >1.8 V C PTB[0:7], PTC[0:7]2, DD V – 0.5 — — I = –0.6 mA DD low-drive strength Load Output high 2 V V > 2.7 V V P voltage PTA[0:3], PTA[6:7], OH I DD = –10 mA VDD – 0.5 — — PTB[0:7], PTC[0:7]2, Load V > 1.8 V C high-drive strength DD V – 0.5 — — I = –3 mA DD Load PTA[4:5], PTD[0:7], V > 1.8 V C PTE[0:7], DD V – 0.5 — — I = –0.5 mA DD low-drive strength Load Output high 3 V V > 2.7 V V P voltage PTA[4:5], PTD[0:7], OH I DD = –2.5 mA VDD – 0.5 — — Load PTE[0:7], V > 1.8 V C high-drive strength DD V – 0.5 — — I = –1 mA DD Load Output high 4 D Max total I for all ports I — — 100 mA current OH OHT PTA[0:3], PTA[6:7], V >1.8 V C PTB[0:7], PTC[0:7], DD — — 0.5 I = 0.6 mA low-drive strength Load Output low 5 V V > 2.7 V V P voltage PTA[0:3], PTA[6:7], OL DD — — 0.5 I = 10 mA Load PTB[0:7], PTC[0:7], V > 1.8 V C high-drive strength DD — — 0.5 I = 3 mA Load MC9S08LL64 Series MCU Data Sheet, Rev. 7 12 Freescale Semiconductor

DC Characteristics Table8. DC Characteristics (continued) Num C Characteristic Symbol Condition Min Typ1 Max Unit PTA[4:5], PTD[0:7], V > 1.8 V C PTE[0:7], DD — — 0.5 I = 0.5 mA low-drive strength Load Output low 6 V V > 2.7 V V P voltage PTA[4:5], PTD[0:7], OL DD — — 0.5 I = 3 mA Load PTE[0:7], V > 1.8 V C high-drive strength DD — — 0.5 I = 1 mA Load Output low 7 D Max total I for all ports I — — 100 mA current OL OLT P Input high VDD > 2.7 V 0.70 x VDD — — 8 all digital inputs V C voltage IH V > 1.8 V 0.85 x V — — DD DD V P Input low VDD > 2.7 V — — 0.35 x VDD 9 all digital inputs V C voltage IL V > 1.8 V — — 0.30 x V DD DD Input 10 C all digital inputs V 0.06 x V — — mV hysteresis hys DD all input only pins except for V = V — 0.025 1 μA In DD LCD only pins (LCD 8-12, Input 21-41) VIn = VSS — 0.025 1 μA 11 P leakage |I | In current V = V — 100 150 μA In DD LCD only pins (LCD 8-12, V = V 21-41) In SS — 0.025 1 μA Hi-Z (off-state) all input/output 12 P leakage (per pin) |IOZ| VIn = VDD or VSS — 0.025 1 μA current Total Total leakage current for all 13 P leakage pins |IInT| VIn = VDD or VSS — — 3 μA current3 Pullup, all non-LCD pins when R 14 P Pulldown PU, 17.5 — 52.5 kΩ enabled R resistors PD Pullup, LCD/GPIO pins when R 15 P Pulldown PU, 35 — 77 kΩ enabled R resistors PD DC injection Single pin limit –0.2 — 0.2 mA 16 D current 4, 5, Total MCU limit, includes IIC VIN < VSS, VIN > VDD 6 –5 — 5 mA sum of allstressed pins 17 C Input Capacitance, all pins C — — 8 pF In 18 C RAM retention voltage V — 0.6 1.0 V RAM 19 C POR re-arm voltage7 V 0.9 1.4 2.0 V POR 20 D POR re-arm time t 10 — — μs POR V falling 1.80 1.84 1.88 21 P Low-voltage detection threshold V DD V LVD V rising 1.88 1.92 1.96 DD MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 13

DC Characteristics Table8. DC Characteristics (continued) Num C Characteristic Symbol Condition Min Typ1 Max Unit V falling 22 P Low-voltage warning threshold V DD 2.08 2.14 2.2 V LVW V rising DD Low-voltage inhibit reset/recover 23 P V — 80 — mV hysteresis hys 24 P Bandgap Voltage Reference8 V 1.15 1.17 1.18 V BG 1 Typical values are measured at 25°C. Characterized, not tested 2 All I/O pins except for LCD pins in Open Drain mode. 3 Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250 nA. 4 All functional non-supply pins, except for PTB2 are internally clamped to V and V . SS DD 5 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6 Power supply must maintain regulation within operating V range during instantaneous and operating maximum current DD conditions. If the positive injection current (V > V ) is greater than I , the injection current may flow out of V and could In DD DD DD result in external power supply going out of regulation. Ensure that external V load will shunt current greater than maximum DD injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 7 POR will occur below the minimum voltage. 8 Factory trimmed at V = 3.0 V, Temp = 25 °C DD Figure4. Non LCD pins I/O Pullup Typical Resistor Values MC9S08LL64 Series MCU Data Sheet, Rev. 7 14 Freescale Semiconductor

DC Characteristics Figure5. Typical Low-Side Driver (Sink) Characteristics (Non LCD Pins) — Low Drive (PTxDSn = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 15

DC Characteristics Figure6. Typical Low-Side Driver (Sink) Characteristics(Non LCD Pins) — High Drive (PTxDSn = 1) MC9S08LL64 Series MCU Data Sheet, Rev. 7 16 Freescale Semiconductor

DC Characteristics Figure7. Typical High-Side (Source) Characteristics (Non LCD Pins)— Low Drive (PTxDSn = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 17

DC Characteristics Figure8. Typical High-Side (Source) Characteristics(Non LCD Pins) — High Drive (PTxDSn = 1) MC9S08LL64 Series MCU Data Sheet, Rev. 7 18 Freescale Semiconductor

DC Characteristics Figure9. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins)— Low Drive (PTxDSn = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 19

DC Characteristics Figure10. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins) — High Drive (PTxDSn = 1) MC9S08LL64 Series MCU Data Sheet, Rev. 7 20 Freescale Semiconductor

DC Characteristics Figure11. Typical High-Side (Source) Characteristics (LCD/GPIO Pins)— Low Drive (PTxDSn = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 21

DC Characteristics Figure12. Typical High-Side (Source) Characteristics (LCD/GPIO Pins) — High Drive (PTxDSn = 1) MC9S08LL64 Series MCU Data Sheet, Rev. 7 22 Freescale Semiconductor

Supply Current Characteristics 3.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table9. Supply Current Characteristics Bus V Temp Num C Parameter Symbol DD Typ1 Max Unit Freq (V) (°C) T 20 MHz 13.75 17.9 Run supply current 1 T RI 10 MHz 3 7 — mA –40 to 85 FEI mode, all modules on DD T 1 MHz 2 — T 20 MHz 8.9 — Run supply current 2 T FEI mode, all modules off RI 10 MHz 3 5.5 — mA –40 to 85 DD T 1 MHz 0.9 — 16 kHz T 185 — Run supply current FBILP 3 RI 3 μA –-40 to 85 LPS=0, all modules on DD 16 kHz T 115 — FBELP Run supply current — 0 to 70 T LPS=1, all modules off, running 25 — –40 to 85 from Flash 16 kHz 4 RI 3 μA Run supply current DD FBELP — 0 to 70 T LPS=1, all modules off, running 7.3 — –40 to 85 from RAM T 20 MHz 4.57 6 Wait mode supply current 5 T WI 8 MHz 3 2 — mA –40 to 85 FEI mode, all modules off DD T 1 MHz 0.73 — P 0.4 1.3 –40 to 25 C 3 4 6 70 P 8.5 13 85 6 Stop2 mode supply current S2I n/a μA C DD 0.35 1 –40 to 25 C 2 3.9 5 70 C 7.7 10 85 P 0.65 1.8 –40 to 25 C 3 5.7 8 70 P Stop3 mode supply current 12.2 20 85 7 S3I n/a μA C No clocks active DD 0.6 1.5 –40 to 25 C 2 5 6.8 70 C 11.5 14 85 1 Typical values are measured at 25 °C. Characterized, not tested MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 23

Supply Current Characteristics Table10. Stop Mode Adders Temperature (°C) Num C Parameter Condition Units –40 25 70 85 1 T LPO 100 100 150 175 nA 2 T EREFSTEN RANGE=HGO=0 750 750 800 850 nA 3 T IREFSTEN1 63 70 77 81 μA 4 T TOD Does not include clock source current 50 50 75 100 nA 5 T LVD1 LVDSE=1 110 110 112 115 μA 6 T ACMP1 Not using the bandgap (BGBE=0) 12 12 20 23 μA ADLPC=ADLSMP=1 7 T ADC1 95 95 101 120 μA Not using the bandgap (BGBE=0) VIREG enabled for Contrast control, 1/8 Duty cycle, 8x24 configuration for driving 192 8 T LCD 1 1 6 13 μA segments, 32 Hz frame rate, No LCD glass connected. LCD configured for 1/8 duty cycle, 8x24 9 T LCD configuration for driving 192 segments, 32 Hz 0.2 0.24 0.5 0.65 μA frame rate, no LCD glass connected. 1 Not available in stop2 mode. Figure13. Typical Run I for FBE and FEI, I vs. V DD DD DD (ADC and ACMP off, All Other Modules Enabled) MC9S08LL64 Series MCU Data Sheet, Rev. 7 24 Freescale Semiconductor

External Oscillator (XOSCVLP) Characteristics 3.8 External Oscillator (XOSCVLP) Characteristics Reference Figure 14 and Figure15 for crystal or resonator circuits. Table11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient) Num C Characteristic Symbol Min Typ1 Max Unit Oscillator crystal or resonator (EREFS=1, ERCLKEN = 1) Low range (RANGE = 0) flo 32 — 38.4 kHz 1 C High range (RANGE = 1), high gain (HGO = 1) fhi 1 — 16 MHz High range (RANGE = 1), low power (HGO = 0) f 1 — 8 MHz hi Load capacitors See Note 2 2 D Low range (RANGE=0), low power (HGO=0) C1,C2 See Note 3 Other oscillator settings Feedback resistor Low range, low power (RANGE=0, HGO=0)2 — — — 3 D R MΩ Low range, high gain (RANGE=0, HGO=1) F — 10 — High range (RANGE=1, HGO=X) — 1 — Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 — — — Low range, high gain (RANGE = 0, HGO = 1) — 100 — High range, low power (RANGE = 1, HGO = 0) — 0 — 4 D High range, high gain (RANGE = 1, HGO = 1) RS kΩ ≥ 8 MHz — 0 0 4 MHz — 0 10 1 MHz — 0 20 Crystal start-up time 4 Low range, low power — 600 — t 5 C Low range, high gain CSTL — 400 — ms High range, low power — 5 — t High range, high gain CSTH — 15 — Square wave input clock frequency (EREFS=0, ERCLKEN = 1) 6 D FEE mode fextal 0.03125 — 20 MHz FBE or FBELP mode 0 — 20 MHz 1 Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value. 2 Load capacitors (C C ), feedback resistor (R ) and series resistor (R ) are incorporated internally when RANGE = HGO = 0. 1, 2 F S 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 25

Internal Clock Source (ICS) Characteristics XOSCVLP EXTAL XTAL R R S F Crystal or Resonator C 1 C 2 Figure14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain XOSCVLP EXTAL XTAL Crystal or Resonator Figure15. Typical Crystal or Resonator Circuit: Low Range/Low Power 3.9 Internal Clock Source (ICS) Characteristics Table12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) Num C Characteristic Symbol Min Typ1 Max Unit 1 C Average internal reference frequency — untrimmed f 25 32.7 41.66 kHz int_ut 2 P Average internal reference frequency — user-trimmed f 31.25 — 39.06 kHz int_t 3 P Average internal reference frequency — factory-trimmed f — 32.7 — kHz int_t 4 T Internal reference start-up time t — 60 100 μs IRST P Low range (DFR = 00) 12.8 16.8 21.33 DCO output frequency 5 f MHz range — untrimmed dco_ut C Mid range (DFR = 01) 25.6 33.6 42.67 P Low range (DFR = 00) 16 — 20 DCO output frequency 6 f MHz range — trimmed dco_t P Mid range (DFR = 01) 32 — 40 Resolution of trimmed DCO output frequency at fixed 7 C Δf — ±0.1 ±0.2 %f voltage and temperature (using FTRIM) dco_res_t dco Resolution of trimmed DCO output frequency at fixed 8 C Δf — ± 0.2 ±0.4 %f voltage and temperature (not using FTRIM) dco_res_t dco MC9S08LL64 Series MCU Data Sheet, Rev. 7 26 Freescale Semiconductor

Internal Clock Source (ICS) Characteristics Table12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued) Num C Characteristic Symbol Min Typ1 Max Unit Total deviation of trimmed DCO output frequency over + 0.5 9 C Δf — ±2 %f voltage and temperature dco_t –1.0 dco Total deviation of trimmed DCO output frequency over fixed 10 C Δf — ± 0.5 ±1 %f voltage and temperature range of 0 °C to 70 °C dco_t dco 11 C FLL acquisition time2 t — — 1 ms Acquire Long term jitter of DCO output clock (averaged over 2 ms 12 C C — 0.02 0.2 %f interval)3 Jitter dco 1 Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value. 2 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . Bus Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via V and V and variation in crystal oscillator frequency increase the C percentage DD SS Jitter for a given interval. Figure16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 27

AC Characteristics 3.10 AC Characteristics This section describes timing characteristics for each peripheral system. 3.10.1 Control Timing Table13. Control Timing Num C Rating Symbol Min Typ1 Max Unit Bus frequency (t = 1/f ) cyc Bus 1 D V ≤ 2.1V f dc — 10 MHz DD Bus V > 2.1V dc — 20 DD 2 D Internal low power oscillator period tLPO 700 — 1300 μs 3 D External reset pulse width2 textrst 100 — — ns 4 D Reset low drive trstdrv 34 × tcyc — — ns BKGD/MS setup time after issuing background debug 5 D force reset to enter user or BDM modes tMSSU 500 — — ns BKGD/MS hold time after issuing background debug 6 D force reset to enter user or BDM modes 3 tMSH 100 — — μs IRQ pulse width 7 D Asynchronous path2 100 — — t t ns Synchronous path4 ILIH, IHIL 1.5 × t — — cyc Keyboard interrupt pulse width 8 D Asynchronous path2 100 — — t t ns Synchronous path4 ILIH, IHIL 1.5 × t — — cyc Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) tRise, tFall — 16 — ns Slew rate control enabled (PTxSE = 1) — 23 — 9 C Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) tRise, tFall — 5 — ns Slew rate control enabled (PTxSE = 1) — 9 — 1 Typical values are based on characterization data at V = 3.0 V, 25 °C unless otherwise stated. DD 2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t after V MSH DD rises above V . LVD 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5 Timing is shown with respect to 20% V and 80% V levels. Temperature range –40 °C to 85 °C. DD DD 6 Except for LCD pins in open drain mode. MC9S08LL64 Series MCU Data Sheet, Rev. 7 28 Freescale Semiconductor

AC Characteristics t extrst RESET PIN Figure17. Reset Timing t IHIL IRQ/KBIPx IRQ/KBIPx t ILIH Figure18. IRQ/KBIPx Timing 3.10.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table14. TPM Input Timing No. C Function Symbol Min Max Unit 1 D External clock frequency f 0 f /4 Hz TCLK Bus 2 D External clock period t 4 — t TCLK cyc 3 D External clock high time t 1.5 — t clkh cyc 4 D External clock low time t 1.5 — t clkl cyc 5 D Input capture pulse width t 1.5 — t ICPW cyc t TCLK t clkh TCLK t clkl Figure19. Timer External Clock MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 29

AC Characteristics t ICPW TPMCHn TPMCHn t ICPW Figure20. Timer Input Capture Pulse 3.10.3 SPI Timing Table 15 and Figure21 through Figure 24 describe the timing requirements for the SPI system. Table15. SPI Timing No. C Function Symbol Min Max Unit Operating frequency — D Master f f /2048 f /2 Hz op Bus Bus Slave 0 f /4 Bus SPSCK period D Master t 2 2048 t 1 SPSCK cyc Slave 4 — t cyc Enable lead time D Master t 1/2 — t 2 Lead SPSCK Slave 1 — t cyc Enable lag time D Master t 1/2 — t 3 Lag SPSCK Slave 1 — t cyc Clock (SPSCK) high or low time D Master t t – 30 1024 t ns 4 WSPSCK cyc cyc Slave t – 30 — ns cyc Data setup time (inputs) D Master t 15 — ns 5 SU Slave 15 — ns Data hold time (inputs) D Master t 0 — ns 6 HI Slave 25 — ns D Slave access time t — 1 t 7 a cyc D Slave MISO disable time t — 1 t 8 dis cyc Data valid (after SPSCK edge) D Master t — 25 ns 9 v Slave — 25 ns MC9S08LL64 Series MCU Data Sheet, Rev. 7 30 Freescale Semiconductor

AC Characteristics Table15. SPI Timing (continued) No. C Function Symbol Min Max Unit Data hold time (outputs) D Master t 0 — ns 10 HO Slave 0 — ns Rise time D Input t — t – 25 ns 11 RI cyc Output t — 25 ns RO Fall time D Input t — t – 25 ns 12 FI cyc Output t — 25 ns FO SS1 (OUTPUT) 2 1 11 3 SPSCK 4 (CPOL = 0) (OUTPUT) 4 12 SPSCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MS BIN2 BIT 6 . . . 1 LSB IN 9 9 10 MOSI (OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure21. SPI Master Timing (CPHA = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 31

AC Characteristics SS1 (OUTPUT) 1 2 12 11 3 SPSCK (CPOL = 0) (OUTPUT) 4 4 11 12 SPSCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 9 10 MOSI PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA (OUTPUT) NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure22. SPI Master Timing (CPHA =1) SS (INPUT) 1 12 11 3 SPSCK (CPOL = 0) (INPUT) 2 4 4 11 12 SPSCK (CPOL = 1) (INPUT) 8 7 9 10 10 MISO SEE (OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE 1 5 6 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally MSB of character just received. Figure23. SPI Slave Timing (CPHA = 0) MC9S08LL64 Series MCU Data Sheet, Rev. 7 32 Freescale Semiconductor

Analog Comparator (ACMP) Electricals SS (INPUT) 1 3 2 12 11 SPSCK (CPOL = 0) (INPUT) 4 4 11 12 SPSCK (CPOL = 1) (INPUT) 9 10 c MISO SEE (OUTPUT) NOTE 1 SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT 7 ‘c 6 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure24. SPI Slave Timing (CPHA = 1) 3.11 Analog Comparator (ACMP) Electricals Table16. Analog Comparator Electrical Specifications No C Characteristic Symbol Min Typical Max Unit 1 D Supply voltage VDD 1.8 — 3.6 V 2 P Supply current (active) IDDAC — 20 35 μA 3 D Analog input voltage V V – 0.3 — V V AIN SS DD 4 P Analog input offset voltage V — 20 40 mV AIO 5 C Analog comparator hysteresis VH 3.0 9.0 15.0 mV 6 P Analog input leakage current IALKG — — 1.0 μA 7 C Analog comparator initialization delay t — — 1.0 μs AINIT 3.12 ADC Characteristics Table17. 12-Bit ADC Operating Conditions No. Characteristic Conditions Symb Min Typ1 Max Unit Absolute V 1.8 — 3.6 V DDA 1 Supply voltage Delta to VDD (V – V )2 ΔV –100 0 100 mV DD DDA DDA MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 33

ADC Characteristics Table17. 12-Bit ADC Operating Conditions (continued) No. Characteristic Conditions Symb Min Typ1 Max Unit Delta to V 2 Ground voltage SS ΔV –100 0 100 mV (V – V )2 SSA SS SSA 3 Reference voltage high — V 1.8 V V V REFH DDA DDA 4 Reference voltage low — V V V V V REFL SSA SSA SSA 5 Input voltage — V V — V V ADIN REFL REFH 6 Input capacitance 8/10/12-bit modes C — 4 5 pF ADIN 7 Input resistance — R — 5 7 kΩ ADIN 1 Typical values assume V = 3.0 V, Temp = 25 °C, f = 1.0 MHz unless otherwise stated. Typical values are for DDA ADCK reference only and are not tested in production. 2 DC potential difference. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad ZAS leakage CHANNEL SELECT due to CIRCUIT ADC SAR R input R ENGINE AS protection ADIN + V ADIN – C V + AS AS – R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure25. ADC Input Impedance Equivalency Diagram MC9S08LL64 Series MCU Data Sheet, Rev. 7 34 Freescale Semiconductor

ADC Characteristics Table18. 12-Bit ADC Characteristics (V = V , V = V ) REFH DDA REFL SSA # Characteristic Conditions C Symb Min Typ1 Max Unit Comment ADLPC = 1 ADHSC = 0 1 Supply current T I — 200 — μA ADLSMP = 0 DDA ADCO = 1 ADLPC = 1 ADHSC = 1 2 Supply current T I — 280 — μA ADLSMP = 0 DDA ADCO = 1 ADLPC = 0 ADHSC = 0 3 Supply current T I — 370 — μA ADLSMP = 0 DDA ADCO = 1 ADLPC = 0 ADHSC = 1 4 Supply current T I — 0.61 — mA ADLSMP = 0 DDA ADCO = 1 Stop, reset, module 5 Supply current I — 0.01 0.8 μA off DDA High speed 2 3.3 5 ADC (ADLPC = 0) t = 6 asynchronous P f MHz ADACK ADACK 1/f clock source Low power ADACK 1.25 2 3.3 (ADLPC = 1) Single/first continuous ADLSMP = 0 ADHSC = 0 7 Sample time ADLSMP = 0 C ts — 6 — ADCK ADLSTS = XX ADHSC = 1 ADLSMP = 0 C ts — 10 — ADLSTS = XX Subsequent continuous ADLSMP = 0 ADHSC = 0 8 Sample time ADLSMP = 0 C ts — 4 — ADCK ADLSTS = XX ADHSC = 1 ADLSMP = 0 C ts — 8 — ADLSTS = XX MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 35

ADC Characteristics Table18. 12-Bit ADC Characteristics (V = V , V = V ) (continued) REFH DDA REFL SSA # Characteristic Conditions C Symb Min Typ1 Max Unit Comment Subsequent Continuous or Single/First Continuous ADLSMP = 1 ADHSC = 0 ADLSMP = 1 C ts — 24 — ADLSTS = 00 ADHSC = 0 ADLSMP = 1 C ts — 16 — ADLSTS = 01 ADHSC = 0 ADLSMP = 1 C ts — 10 — ADLSTS = 10 9 Sample time ADHSC = 0 ADLSMP = 1 C ts — 6 — ADLSTS = 11 ADHSC = 1 ADLSMP = 1 C ts — 28 — ADLSTS = 00 ADHSC = 1 ADLSMP = 1 C ts — 20 — ADLSTS = 01 ADHSC = 1 ADLSMP = 1 C ts — 14 — ADLSTS = 10 ADHSC = 1 ADLSMP = 1 C ts — 10 — ADLSTS = 11 12-bit mode –2.5 to T — ±4 3.6 > V > 2.7V 3.25 DDA Total 12-bit mode, –5.5 to 10 unadjusted 2.7 > VDDA > 1.8V T ETUE ±3.25 6.5 LSB2 quInacnltuizdaetiso n error 10-bit mode T — ±1 ±2.5 8-bit mode T — ±0.5 ±1.0 –1 to –1.5 to 12-bit mode T — 1.75 2.5 Differential 11 DNL LSB2 non-linearity 10-bit mode3 T — ±0.5 ±1.0 8-bit mode3 T — ±0.3 ±0.5 MC9S08LL64 Series MCU Data Sheet, Rev. 7 36 Freescale Semiconductor

ADC Characteristics Table18. 12-Bit ADC Characteristics (V = V , V = V ) (continued) REFH DDA REFL SSA # Characteristic Conditions C Symb Min Typ1 Max Unit Comment –1.5 to 12-bit mode T — ±2.75 2.25 Integral 12 INL LSB2 non-linearity 10-bit mode T — ±0.5 ±1.0 8-bit mode T — ±0.3 ±0.5 –1.25 12-bit mode T — ±1 to 1 Zero-scale 13 E LSB2 V = V error 10-bit mode T ZS — ±0.5 ±1 ADIN SSA 8-bit mode T — ±0.5 ±0.5 –3.5 to 12-bit mode T — ±1.0 2.25 14 Full-scale error E LSB2 V = V 10-bit mode T FS — ±0.5 ±1 ADIN DDA 8-bit mode T — ±0.5 ±0.5 12-bit mode — –1 to 0 — Quantization 15 10-bit mode D E — — ±0.5 LSB2 error Q 8-bit mode — — ±0.5 12-bit mode — ±2 — Input leakage Pad leakage4 * 16 10-bit mode D E — ±0.2 ±4 LSB2 error IL R AS 8-bit mode — ±0.1 ±1.2 –40 °C– 25 °C — 1.646 — Temp sensor 17 D m mV/°C slope 25 °C– 125 °C — 1.769 — Temp sensor 18 25°C D V — 701.2 — mV voltage TEMP25 1 Typical values assume V = 3.0 V, Temp = 25 °C, f = 1.0 MHz unless otherwise stated. Typical values are for reference DDA ADCK only and are not tested in production. 2 1 LSB = (V – V )/2N REFH REFL 3 Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes. 4 Based on input pad leakage current. Refer to pad electricals. MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 37

VREF Specifications 3.13 VREF Specifications Table19. VREF Electrical Specifications Num Characteristic Symbol Typical Min Max Unit 1 Supply voltage V — 1.80 3.60 V DD 2 Operating temperature range T — –40 105 °C op 3 Maximum load — — — 10 mA Operation across Temperature 4 V Room Temp V Room Temp 1.15 — — V –2 to –6 from Room Temp mV 5 Untrimmed –40 °C Untrimmed –40 °C — Voltage 6 Trimmed –40 °C Trimmed –40 °C — ± 1 from Room Temp Voltage mV +1 to –2 from Room Temp mV Untrimmed 0 °C Untrimmed 0 °C — 7 Voltage Trimmed 0 °C Trimmed 0 °C — ± 0.5from Room Temp Voltage mV +1 to –2 from Room Temp mV 8 Untrimmed 50 °C Untrimmed 50 °C — Voltage 9 Trimmed 50 °C Trimmed 50 °C — ± 0.5 from Room Temp Voltage mV 10 Untrimmed 85 °C Untrimmed 85 °C — 0 to –4 from Room Temp Voltage mV 11 Trimmed 85 °C Trimmed 85 °C — ± 0.5 from Room Temp Voltage mV –2 to –6 from Room Temp mV 12 Untrimmed 125 °C Untrimmed 125 °C — Voltage 13 Trimmed 125 °C Trimmed 125 °C — ± 1 from Room Temp Voltage mV 14 Load bandwidth — — — — — 15 Load regulation mode = 10 at 1mA load Mode = 10 — 20 100 μV/mA DC — ± 0.1from Room Temp Voltage mV 16 Line regulation (power supply rejection) AC — –60 dB Power Consumption Powered down Current (Stop Mode, μA 17 I — — .100 VREFEN = 0, VRSTEN = 0) 18 Bandgap only (Mode[1:0] 00) I — — 75 μA 19 Low-power buffer (Mode[1:0] 01) I — — 125 μA 20 Tight-regulation buffer (Mode[1:0] 10) I — — 1.1 mA 21 RESERVED (Mode[1:0] 11) — — — — — MC9S08LL64 Series MCU Data Sheet, Rev. 7 38 Freescale Semiconductor

LCD Specifications 3.14 LCD Specifications Table20. LCD Electricals, 3-V Glass No. C Characteristic Symbol Min Typ Max Unit 1 D LCD supply voltage V .9 1.5 1.8 V LCD 2 D LCD frame frequency f 28 30 58 Hz Frame 3 D LCD charge pump capacitance C — 100 100 nF LCD 4 D LCD bypass capacitance C — 100 100 nF BYLCD 5 D LCD glass capacitance C — 2000 8000 pF glass 6 HRefSel = 0 V .89 1.00 1.15 IREG D V V 7 IREG HRefSel = 1 1.49 1.67 1.851 8 D V trim resolution Δ 1.5 — — % V IREG RTRIM IREG 9 HRefSel = 0 — — — .1 D V ripple V IREG 10 HRefSel = 1 — — — .15 D 11 V buffered adder2 I — 1 μA LCD Buff 1 V Max can not exceed V –.15 V IREG DD 2 VSUPPLY = 10, BYPASS = 0 3.15 Flash Specifications This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal V supply. DD For more detailed information about program/erase operations, see the Memory section. Table21. Flash Characteristics No. C Characteristic Symbol Min Typical Max Unit Supply voltage for program/erase 1 D V 1.8 — 3.6 V –40 °C to 85 °C prog/erase 2 D Supply voltage for read operation V 1.8 — 3.6 V Read 3 D Internal FCLK frequency1 f 150 — 200 kHz FCLK 4 D Internal FCLK period (1/FCLK) t 5 — 6.67 μs Fcyc 5 P Byte program time (random location)2 t 9 t prog Fcyc 6 P Byte program time (burst mode)2 t 4 t Burst Fcyc 7 P Page erase time2 t 4000 t Page Fcyc 8 P Mass erase time2 t 20,000 t Mass Fcyc 9 D Byte program current3 R — 4 — mA IDDBP MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 39

EMC Performance Table21. Flash Characteristics (continued) No. C Characteristic Symbol Min Typical Max Unit 10 D Page erase current3 R — 6 — mA IDDPE Program/erase endurance4 — 11 C T to T = –40°C to 85°C 10,000 — — cycles L H T = 25°C 100,000 — 12 C Data retention5 t 15 100 — years D_ret 1 The frequency of this clock is controlled by a software setting. 2 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures with DD V = 3.0 V, bus frequency = 4.0 MHz. DD 4 Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 °C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 3.16 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 3.16.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). 4 Ordering Information This appendix contains ordering information for the device numbering system MC9S08LL64 and MC9S08LL36 devices. See Table 1 for feature summary by package information. MC9S08LL64 Series MCU Data Sheet, Rev. 7 40 Freescale Semiconductor

Device Numbering System Table22. Device Numbering System Memory Device Number1 Available Packages2 Flash RAM 64 KB 4000 80 LQFP MC9S08LL64 64 KB 4000 64 LQFP 36 KB 4000 80 LQFP MC9S08LL36 36 KB 4000 64 LQFP 1 See Table1 for a complete description of modules included on each device. 2 See Table23 for package information. 4.1 Device Numbering System Example of the device numbering system: MC9 S08 LL 64 C XX Status (MC = Fully qualified) Package designator (see Table23) Temperature range Memory (C = –40 °C to 85 °C) (9 = Flash-based) Core Family Approximate flash size in KB 4.2 Package Information Table23. Package Descriptions Pin Count Package Type Abbreviation Designator Case No. Document No. 80 Low Quad Flat Package LQFP LK 917A 98ASS23237W 64 Low Quad Flat Package LQFP LH 840F 98ASS23234W 4.3 Mechanical Drawings Table 23 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MC9S08LL64 series Product Summary pages at http://www.freescale.com. To view the latest drawing, either: • Click on the appropriate link in Table 23, or • Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate document number (from Table 23) in the “Enter Keyword” search box at the top of the page. MC9S08LL64 Series MCU Data Sheet, Rev. 7 Freescale Semiconductor 41

Mechanical Drawings MC9S08LL64 Series MCU Data Sheet, Rev. 7 42 Freescale Semiconductor

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