Freescale Semiconductor Document Number: QFN_Addendum Rev. 0, 07/2014 Addendum Addendum for New QFN Package Migration This addendum provides the changes to the 98A case outline numbers for products covered in this book. Case outlines were changed because of the migration from gold wire to copper wire in some packages. See the table below for the old (gold wire) package versus the new (copper wire) package. To view the new drawing, go to Freescale.com and search on the new 98A package number for your device. For more information about QFN package use, see EB806: Electrical Connection Recommendations for the Exposed Pad on QFN and DFN Packages. ©Freescale Semiconductor, Inc., 2014. All rights reserved.

Original (gold wire) Current (copper wire) Part Number Package Description package document number package document number MC68HC908JW32 48 QFN 98ARH99048A 98ASA00466D MC9S08AC16 MC9S908AC60 MC9S08AC128 MC9S08AW60 MC9S08GB60A MC9S08GT16A MC9S08JM16 MC9S08JM60 MC9S08LL16 MC9S08QE128 MC9S08QE32 MC9S08RG60 MCF51CN128 MC9RS08LA8 48 QFN 98ARL10606D 98ASA00466D MC9S08GT16A 32 QFN 98ARH99035A 98ASA00473D MC9S908QE32 32 QFN 98ARE10566D 98ASA00473D MC9S908QE8 32 QFN 98ASA00071D 98ASA00736D MC9S08JS16 24 QFN 98ARL10608D 98ASA00734D MC9S08QB8 MC9S08QG8 24 QFN 98ARL10605D 98ASA00474D MC9S08SH8 24 QFN 98ARE10714D 98ASA00474D MC9RS08KB12 24 QFN 98ASA00087D 98ASA00602D MC9S08QG8 16 QFN 98ARE10614D 98ASA00671D MC9RS08KB12 8 DFN 98ARL10557D 98ASA00672D MC9S08QG8 MC9RS08KA2 6 DFN 98ARL10602D 98ASA00735D Addendum for New QFN Package Migration, Rev. 0 2 Freescale Semiconductor

MC9S08GT16A MC9S08GT8A Data Sheet HCS08 Microcontrollers MC9S08GT16A Rev. 1 7/2006 freescale.com

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MC9S08GT16A/GT8A Features 8-Bit HCS08 Central Processor Unit (CPU) • Software selectable pullups on ports when used as input • 40-MHz HCS08 CPU • Internal pullup onRESET and IRQ pin to reduce • HC08 instruction set with added BGND instruction customer system cost • Support for up to 32 interrupt/reset sources • Up to 38general-purpose input/output (I/O) pins, plus one output-only pin, depending on package Memory Options selection • FLASH read/program/erase down to 1.8 V Development Support • Up to 16K FLASH; up to 2K RAM • Background debugging system Power-Saving Modes • Breakpointcapability to allow single breakpoint setting during in-circuit debugging (plus two more • Three very low power stop modes breakpoints in on-chip debug module) • Reduced power wait mode • On-chip, in-circuit emulation (ICE) debug module • Very low power real time interrupt for use in run, with real-time bus capture. On-chip ICE debug wait, and stop modulecontainingtwocomparatorsandninetrigger modes.EightdeepFIFOforstoringchange-of-flow Clock Source Options addresses and event-only data. • Single-wire background debug interface • Clock sources to internal hardware frequency locked-loop (FLL): internal, external, crystal, or Package Options resonator • Internal clock with±0.2% trimming resolution and • 48-pin QFN ±0.5% deviation across voltage or across • 44-pin QFP temperature • 42-pin PSDIP System Protection • 32-pin QFN • Optional watchdog computer operating properly (COP) reset • Low-voltage detection with reset or interrupt • Illegalopcode detection withreset • Illegaladdress detection withreset • FLASH block protect and security Peripherals • ATD — 8-channel, 10-bit analog-to-digital converter • SCI — Two serial communications interface modules • SPI — Serial peripheral interface module • IIC — Inter-integrated circuit bus module • Timer—One3-channeltimerPWMmodule(TPM) plus one 2-channel TPM • KBI — 8-pin keyboard interrupt module Input/Output • 8 high-current pins (20 mA each)

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MC9S08GT16A/GT8A Data Sheet Covers: MC9S08GT16A MC9S08GT8A MC9S08GT16A Rev. 1 7/2006 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. ©Freescale Semiconductor, Inc., 2006. All rights reserved.

Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will bethemostcurrent.Yourprintedcopymaybeanearlierrevision.Toverifyyouhavethelatestinformation available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. Revision Revision Description of Changes Number Date 1 07/17/2006 Initial public release ©Freescale Semiconductor, Inc., 2006. All rights reserved. ® This product incorporates SuperFlash Technology licensed from SST.

List of Chapters Chapter 1 Device Overview......................................................................19 Chapter 2 Pins and Connections.............................................................23 Chapter 3 Modes of Operation.................................................................33 Chapter 4 Memory.....................................................................................41 Chapter 5 Resets, Interrupts, and System Configuration .....................63 Chapter 6 Parallel Input/Output ...............................................................79 Chapter 7 Keyboard Interrupt (S08KBIV1)..............................................99 Chapter 8 Central Processor Unit (S08CPUV2)....................................105 Chapter 9 Internal Clock Generator (S08ICGV4)..................................125 Chapter 10 Timer/PWM (S08TPMV2) ......................................................153 Chapter 11 Serial Communications Interface (S08SCIV1).....................169 Chapter 12 Serial Peripheral Interface (S08SPIV3) ................................187 Chapter 13 Inter-Integrated Circuit (S08IICV1).......................................205 Chapter 14 Analog-to-Digital Converter (S08ATDV3)............................221 Chapter 15 Development Support ...........................................................237 Appendix A Electrical Characteristics......................................................259 Appendix B Ordering Information and Mechanical Drawings................285 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 7

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Contents Section Number Title Page Chapter 1 Device Overview 1.1 Introduction .....................................................................................................................................19 1.1.1 Devices in the MC9S08GT16A/GT8A Series ..................................................................19 1.1.2 MCU Block Diagram ........................................................................................................19 1.2 System Clock Distribution ..............................................................................................................21 Chapter 2 Pins and Connections 2.1 Introduction .....................................................................................................................................23 2.2 Device Pin Assignment ...................................................................................................................23 2.3 Recommended System Connections ...............................................................................................27 2.3.1 V , V , V , V , V , V — Power and Voltage References ...............28 DD SS DDAD SSAD REFH REFL 2.3.2 PTG1/XTAL, PTG2/EXTAL — Oscillator ......................................................................28 2.3.3 RESET — External Reset Pin ...........................................................................................29 2.3.4 PTG0/BKGD/MS — Background / Mode Select .............................................................29 2.3.5 IRQ — External Interrupt Request Pin .............................................................................30 2.3.6 General-Purpose I/O and Peripheral Ports ........................................................................30 2.3.7 Signal Properties Summary ...............................................................................................31 Chapter 3 Modes of Operation 3.1 Introduction .....................................................................................................................................33 3.1.1 Features .............................................................................................................................33 3.2 Run Mode ........................................................................................................................................33 3.3 Active Background Mode ................................................................................................................33 3.4 Wait Mode .......................................................................................................................................34 3.5 Stop Modes ......................................................................................................................................35 3.5.1 Stop1 Mode .......................................................................................................................35 3.5.2 Stop2 Mode .......................................................................................................................35 3.5.3 Stop3 Mode .......................................................................................................................36 3.5.4 Active BDM Enabled in Stop Mode .................................................................................37 3.5.5 LVD Enabled in Stop Mode ..............................................................................................37 3.5.6 On-Chip Peripheral Modules in Stop Modes ....................................................................38 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor NON-DISCLOSURE AGREEMENT REQUIRED 9

Section Number Title Page Chapter 4 Memory 4.1 MC9S08GT16A/GT8A Memory Map ............................................................................................41 4.1.1 Reset and Interrupt Vector Assignments ...........................................................................42 4.2 Register Addresses and Bit Assignments ........................................................................................43 4.3 RAM ................................................................................................................................................48 4.4 FLASH ............................................................................................................................................48 4.4.1 Features .............................................................................................................................48 4.4.2 Program and Erase Times .................................................................................................49 4.4.3 Program and Erase Command Execution .........................................................................49 4.4.4 Burst Program Execution ..................................................................................................51 4.4.5 Access Errors ....................................................................................................................53 4.4.6 FLASH Block Protection ..................................................................................................53 4.4.7 Vector Redirection ............................................................................................................54 4.5 Security ............................................................................................................................................54 4.6 Register Definition ..........................................................................................................................56 4.6.1 FLASH Clock Divider Register (FCDIV) ........................................................................56 4.6.2 FLASH Options Register (FOPT and NVOPT)................................................................57 4.6.3 FLASH Configuration Register (FCNFG) ........................................................................58 4.6.4 FLASH Protection Register (FPROT and NVPROT) .......................................................58 4.6.5 FLASH Status Register (FSTAT) ......................................................................................59 4.6.6 FLASH Command Register (FCMD) ...............................................................................60 Chapter 5 Resets, Interrupts, and System Configuration 5.1 Introduction .....................................................................................................................................63 5.1.1 Features .............................................................................................................................63 5.2 MCU Reset ......................................................................................................................................63 5.3 Computer Operating Properly (COP) Watchdog .............................................................................64 5.4 Interrupts .........................................................................................................................................64 5.4.1 Interrupt Stack Frame .......................................................................................................65 5.4.2 IRQ — External Interrupt Request Pin .............................................................................66 5.4.2.1 Pin Configuration Options ..............................................................................66 5.4.2.2 Edge and Level Sensitivity ..............................................................................67 5.4.3 Interrupt Vectors, Sources, and Local Masks ....................................................................67 5.5 Low-Voltage Detect (LVD) System ................................................................................................69 5.5.1 Power-On Reset Operation ...............................................................................................69 5.5.2 LVD Reset Operation ........................................................................................................69 5.5.3 LVD Interrupt Operation ...................................................................................................69 5.5.4 Low-Voltage Warning (LVW) ...........................................................................................69 5.6 Real-Time Interrupt (RTI) ...............................................................................................................69 5.7 Register Definition ..........................................................................................................................70 MC9S08GT16A/GT8A Data Sheet, Rev. 1 10 Freescale Semiconductor

Section Number Title Page 5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................71 5.7.2 System Reset Status Register (SRS) .................................................................................72 5.7.3 System Background Debug Force Reset Register (SBDFR) ............................................73 5.7.4 System Options Register (SOPT) .....................................................................................74 5.7.5 System Device Identification Register (SDIDH, SDIDL) ................................................75 5.7.6 System Real-Time Interrupt Status and Control Register (SRTISC) ................................76 5.7.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................77 5.7.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................78 Chapter 6 Parallel Input/Output 6.1 Introduction .....................................................................................................................................79 6.1.1 Features .............................................................................................................................79 6.1.2 Block Diagram ..................................................................................................................81 6.2 External Signal Description ............................................................................................................82 6.2.1 Port A and Keyboard Interrupts ........................................................................................82 6.2.2 Port B and Analog to Digital Converter Inputs .................................................................82 6.2.3 Port C and SCI2, IIC, and High-Current Drivers ..............................................................83 6.2.4 Port D, TPM1 and TPM2 ..................................................................................................83 6.2.5 Port E, SCI1, and SPI ........................................................................................................84 6.2.6 Port G, BKGD/MS, and Oscillator ...................................................................................84 6.3 Parallel I/O Controls ........................................................................................................................85 6.3.1 Data Direction Control ......................................................................................................85 6.3.2 Internal Pullup Control .....................................................................................................85 6.3.3 Slew Rate Control .............................................................................................................85 6.4 Stop Modes ......................................................................................................................................86 6.5 Register Definition ..........................................................................................................................86 6.5.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD) .................................................86 6.5.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) .................................................89 6.5.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) .................................................91 6.5.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) ...............................................93 6.5.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) ..................................................95 6.5.6 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) ...............................................97 Chapter 7 Keyboard Interrupt (S08KBIV1) 7.1 Introduction .....................................................................................................................................99 7.1.1 Port A and Keyboard Interrupt Pins ..................................................................................99 7.1.2 Features .............................................................................................................................99 7.1.3 KBI Block Diagram ........................................................................................................101 7.2 Register Definition ........................................................................................................................101 7.2.1 KBI Status and Control Register (KBISC) .....................................................................102 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 11

Section Number Title Page 7.2.2 KBI Pin Enable Register (KBIPE) ..................................................................................103 7.3 Functional Description ..................................................................................................................103 7.3.1 Pin Enables ......................................................................................................................103 7.3.2 Edge and Level Sensitivity ..............................................................................................103 7.3.3 KBI Interrupt Controls ....................................................................................................104 Chapter 8 Central Processor Unit (S08CPUV2) 8.1 Introduction ...................................................................................................................................105 8.1.1 Features ...........................................................................................................................105 8.2 Programmer’s Model and CPU Registers .....................................................................................106 8.2.1 Accumulator (A) .............................................................................................................106 8.2.2 Index Register (H:X) .......................................................................................................106 8.2.3 Stack Pointer (SP) ...........................................................................................................107 8.2.4 Program Counter (PC) ....................................................................................................107 8.2.5 Condition Code Register (CCR) .....................................................................................107 8.3 Addressing Modes .........................................................................................................................109 8.3.1 Inherent Addressing Mode (INH) ...................................................................................109 8.3.2 Relative Addressing Mode (REL) ...................................................................................109 8.3.3 Immediate Addressing Mode (IMM) ..............................................................................109 8.3.4 Direct Addressing Mode (DIR) ......................................................................................109 8.3.5 Extended Addressing Mode (EXT) ................................................................................110 8.3.6 Indexed Addressing Mode ..............................................................................................110 8.3.6.1 Indexed, No Offset (IX) ................................................................................110 8.3.6.2 Indexed, No Offset with Post Increment (IX+) .............................................110 8.3.6.3 Indexed, 8-Bit Offset (IX1) ...........................................................................110 8.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) .......................................110 8.3.6.5 Indexed, 16-Bit Offset (IX2) .........................................................................110 8.3.6.6 SP-Relative, 8-Bit Offset (SP1) ....................................................................110 8.3.6.7 SP-Relative, 16-Bit Offset (SP2) ..................................................................111 8.4 Special Operations .........................................................................................................................111 8.4.1 Reset Sequence ...............................................................................................................111 8.4.2 Interrupt Sequence ..........................................................................................................111 8.4.3 Wait Mode Operation ......................................................................................................112 8.4.4 Stop Mode Operation ......................................................................................................112 8.4.5 BGND Instruction ...........................................................................................................113 8.5 HCS08 Instruction Set Summary ..................................................................................................114 MC9S08GT16A/GT8A Data Sheet, Rev. 1 12 Freescale Semiconductor

Section Number Title Page Chapter 9 Internal Clock Generator (S08ICGV4) 9.1 Introduction ...................................................................................................................................125 9.1.1 Features ...........................................................................................................................127 9.1.2 Modes of Operation ........................................................................................................128 9.1.3 Block Diagram ................................................................................................................129 9.2 External Signal Description ..........................................................................................................129 9.2.1 EXTAL — External Reference Clock / Oscillator Input ................................................129 9.2.2 XTAL — Oscillator Output ............................................................................................129 9.2.3 External Clock Connections ...........................................................................................130 9.2.4 External Crystal/Resonator Connections ........................................................................130 9.3 Register Definition ........................................................................................................................131 9.3.1 ICG Control Register 1 (ICGC1) ....................................................................................131 9.3.2 ICG Control Register 2 (ICGC2) ....................................................................................133 9.3.3 ICG Status Register 1 (ICGS1) .......................................................................................134 9.3.4 ICG Status Register 2 (ICGS2) .......................................................................................135 9.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ..................................................................135 9.3.6 ICG Trim Register (ICGTRM) .......................................................................................136 9.4 Functional Description ..................................................................................................................136 9.4.1 Off Mode (Off) ................................................................................................................137 9.4.1.1 BDM Active ..................................................................................................137 9.4.1.2 OSCSTEN Bit Set .........................................................................................137 9.4.1.3 Stop/Off Mode Recovery ..............................................................................137 9.4.2 Self-Clocked Mode (SCM) .............................................................................................137 9.4.3 FLL Engaged, Internal Clock (FEI) Mode .....................................................................138 9.4.4 FLL Engaged Internal Unlocked ....................................................................................139 9.4.5 FLL Engaged Internal Locked ........................................................................................139 9.4.6 FLL Bypassed, External Clock (FBE) Mode ..................................................................139 9.4.7 FLL Engaged, External Clock (FEE) Mode ...................................................................139 9.4.7.1 FLL Engaged External Unlocked .................................................................140 9.4.7.2 FLL Engaged External Locked .....................................................................140 9.4.8 FLL Lock and Loss-of-Lock Detection ..........................................................................140 9.4.9 FLL Loss-of-Clock Detection .........................................................................................141 9.4.10 Clock Mode Requirements .............................................................................................142 9.4.11 Fixed Frequency Clock ...................................................................................................143 9.4.12 High Gain Oscillator .......................................................................................................143 9.5 Initialization/Application Information ..........................................................................................143 9.5.1 Introduction .....................................................................................................................143 9.5.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ...........................145 9.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ..............................147 9.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ......................149 9.5.5 Example #4: Internal Clock Generator Trim ..................................................................151 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 13

Section Number Title Page Chapter 10 Timer/PWM (S08TPMV2) 10.1 Introduction ...................................................................................................................................153 10.1.1 Features ...........................................................................................................................153 10.1.2 Features ...........................................................................................................................155 10.1.3 Block Diagram ................................................................................................................155 10.2 External Signal Description ..........................................................................................................157 10.2.1 External TPM Clock Sources ..........................................................................................157 10.2.2 TPMxCHn — TPMx Channel n I/O Pins .......................................................................157 10.3 Register Definition ........................................................................................................................157 10.3.1 Timer x Status and Control Register (TPMxSC) ............................................................158 10.3.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) ................................................159 10.3.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) ...............................160 10.3.4 Timer x Channel n Status and Control Register (TPMxCnSC) ......................................161 10.3.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ......................................162 10.4 Functional Description ..................................................................................................................163 10.4.1 Counter ............................................................................................................................163 10.4.2 Channel Mode Selection .................................................................................................164 10.4.2.1 Input Capture Mode ......................................................................................164 10.4.2.2 Output Compare Mode .................................................................................165 10.4.2.3 Edge-Aligned PWM Mode ...........................................................................165 10.4.3 Center-Aligned PWM Mode ...........................................................................................166 10.5 TPM Interrupts ..............................................................................................................................167 10.5.1 Clearing Timer Interrupt Flags .......................................................................................167 10.5.2 Timer Overflow Interrupt Description ............................................................................167 10.5.3 Channel Event Interrupt Description ..............................................................................168 10.5.4 PWM End-of-Duty-Cycle Events ...................................................................................168 Chapter 11 Serial Communications Interface (S08SCIV1) 11.1 Introduction ...................................................................................................................................169 11.1.1 Features ...........................................................................................................................171 11.1.2 Modes of Operation ........................................................................................................171 11.1.3 Block Diagram ................................................................................................................172 11.2 Register Definition ........................................................................................................................174 11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) ..........................................................174 11.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................175 11.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................176 11.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................177 11.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................179 11.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................179 11.2.7 SCI Data Register (SCIxD) .............................................................................................180 MC9S08GT16A/GT8A Data Sheet, Rev. 1 14 Freescale Semiconductor

Section Number Title Page 11.3 Functional Description ..................................................................................................................181 11.3.1 Baud Rate Generation .....................................................................................................181 11.3.2 Transmitter Functional Description ................................................................................181 11.3.2.1 Send Break and Queued Idle .........................................................................182 11.3.3 Receiver Functional Description .....................................................................................182 11.3.3.1 Data Sampling Technique .............................................................................183 11.3.3.2 Receiver Wakeup Operation .........................................................................183 11.3.3.2.1Idle-Line Wakeup .....................................................................184 11.3.3.2.2Address-Mark Wakeup .............................................................184 11.3.4 Interrupts and Status Flags ..............................................................................................184 11.3.5 Additional SCI Functions ...............................................................................................185 11.3.5.1 8- and 9-Bit Data Modes ...............................................................................185 11.3.5.2 Stop Mode Operation ....................................................................................185 11.3.5.3 Loop Mode ....................................................................................................186 11.3.5.4 Single-Wire Operation ..................................................................................186 Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.1 Introduction ...................................................................................................................................187 12.1.1 Features ...........................................................................................................................189 12.1.2 Block Diagrams ..............................................................................................................190 12.1.2.1 SPI System Block Diagram ..........................................................................190 12.1.2.2 SPI Module Block Diagram ..........................................................................190 12.1.3 SPI Baud Rate Generation ..............................................................................................191 12.2 External Signal Description ..........................................................................................................192 12.2.1 SPSCK — SPI Serial Clock ............................................................................................192 12.2.2 MOSI — Master Data Out, Slave Data In ......................................................................192 12.2.3 MISO — Master Data In, Slave Data Out ......................................................................192 12.2.4 SS — Slave Select ...........................................................................................................192 12.3 Modes of Operation .......................................................................................................................193 12.3.1 SPI in Stop Modes ..........................................................................................................193 12.4 Register Definition ........................................................................................................................193 12.4.1 SPI Control Register 1 (SPIC1) ......................................................................................193 12.4.2 SPI Control Register 2 (SPIC2) ......................................................................................194 12.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................195 12.4.4 SPI Status Register (SPIS) ..............................................................................................196 12.4.5 SPI Data Register (SPID) ................................................................................................197 12.5 Functional Description ..................................................................................................................198 12.5.1 SPI Clock Formats ..........................................................................................................198 12.5.2 SPI Interrupts ..................................................................................................................201 12.5.3 Mode Fault Detection .....................................................................................................201 12.6 Initialization/Application Information ..........................................................................................201 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 15

Section Number Title Page 12.6.1 SPI Module Initialization Example .................................................................................201 12.6.1.1 Initialization Sequence ..................................................................................201 12.6.1.2 Pseudo—Code Example ...............................................................................202 Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.1 Introduction ...................................................................................................................................205 13.1.1 Features ...........................................................................................................................207 13.1.2 Modes of Operation ........................................................................................................207 13.1.3 Block Diagram ................................................................................................................208 13.2 External Signal Description ..........................................................................................................208 13.2.1 SCL — Serial Clock Line ...............................................................................................208 13.2.2 SDA — Serial Data Line ................................................................................................208 13.3 Register Definition ........................................................................................................................208 13.3.1 IIC Address Register (IICA) ...........................................................................................209 13.3.2 IIC Frequency Divider Register (IICF) ...........................................................................209 13.3.3 IIC Control Register (IICC) ............................................................................................212 13.3.4 IIC Status Register (IICS) ...............................................................................................213 13.3.5 IIC Data I/O Register (IICD) ..........................................................................................214 13.4 Functional Description ..................................................................................................................215 13.4.1 IIC Protocol .....................................................................................................................215 13.4.1.1 START Signal ...............................................................................................216 13.4.1.2 Slave Address Transmission .........................................................................216 13.4.1.3 Data Transfer .................................................................................................216 13.4.1.4 STOP Signal ..................................................................................................217 13.4.1.5 Repeated START Signal ...............................................................................217 13.4.1.6 Arbitration Procedure ....................................................................................217 13.4.1.7 Clock Synchronization ..................................................................................217 13.4.1.8 Handshaking .................................................................................................218 13.4.1.9 Clock Stretching ............................................................................................218 13.5 Resets ............................................................................................................................................218 13.6 Interrupts .......................................................................................................................................218 13.6.1 Byte Transfer Interrupt ....................................................................................................219 13.6.2 Address Detect Interrupt .................................................................................................219 13.6.3 Arbitration Lost Interrupt ................................................................................................219 Chapter 14 Analog-to-Digital Converter (S08ATDV3) 14.1 Introduction ...................................................................................................................................223 14.1.1 Features ...........................................................................................................................223 14.1.2 Modes of Operation ........................................................................................................223 14.1.2.1 Stop Mode .....................................................................................................223 MC9S08GT16A/GT8A Data Sheet, Rev. 1 16 Freescale Semiconductor

Section Number Title Page 14.1.2.2 Power Down Mode .......................................................................................223 14.1.3 Block Diagram ................................................................................................................223 14.2 External Signal Description ..........................................................................................................224 14.2.1 ADP7–ADP0 — Channel Input Pins ..............................................................................225 14.2.2 V , V — ATD Reference Pins .........................................................................225 REFH REFL 14.2.3 V , V — ATD Supply Pins ............................................................................225 DDAD SSAD 14.3 Register Definition ........................................................................................................................225 14.3.1 ATD Control (ATDC) .....................................................................................................225 14.3.2 ATD Status and Control (ATDSC) ..................................................................................228 14.3.3 ATD Result Data (ATDRH, ATDRL) .............................................................................229 14.3.4 ATD Pin Enable (ATDPE) ..............................................................................................229 14.4 Functional Description ..................................................................................................................230 14.4.1 Mode Control ..................................................................................................................230 14.4.2 Sample and Hold .............................................................................................................230 14.4.3 Analog Input Multiplexer ................................................................................................232 14.4.4 ATD Module Accuracy Definitions ................................................................................232 14.5 Resets ............................................................................................................................................235 14.6 Interrupts .......................................................................................................................................235 Chapter 15 Development Support 15.1 Introduction ...................................................................................................................................237 15.1.1 Features ...........................................................................................................................238 15.2 Background Debug Controller (BDC) ..........................................................................................238 15.2.1 BKGD Pin Description ...................................................................................................239 15.2.2 Communication Details ..................................................................................................240 15.2.3 BDC Commands .............................................................................................................244 15.2.4 BDC Hardware Breakpoint .............................................................................................246 15.3 On-Chip Debug System (DBG) ....................................................................................................247 15.3.1 Comparators A and B ......................................................................................................247 15.3.2 Bus Capture Information and FIFO Operation ...............................................................247 15.3.3 Change-of-Flow Information ..........................................................................................248 15.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................248 15.3.5 Trigger Modes .................................................................................................................249 15.3.6 Hardware Breakpoints ....................................................................................................251 15.4 Register Definition ........................................................................................................................251 15.4.1 BDC Registers and Control Bits .....................................................................................251 15.4.1.1 BDC Status and Control Register (BDCSCR) ..............................................252 15.4.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................253 15.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................253 15.4.3 DBG Registers and Control Bits .....................................................................................254 15.4.3.1 Debug Comparator A High Register (DBGCAH) ........................................254 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 17

Section Number Title Page 15.4.3.2 Debug Comparator A Low Register (DBGCAL) .........................................254 15.4.3.3 Debug Comparator B High Register (DBGCBH) .........................................254 15.4.3.4 Debug Comparator B Low Register (DBGCBL) ..........................................254 15.4.3.5 Debug FIFO High Register (DBGFH) ..........................................................255 15.4.3.6 Debug FIFO Low Register (DBGFL) ...........................................................255 15.4.3.7 Debug Control Register (DBGC) ..................................................................256 15.4.3.8 Debug Trigger Register (DBGT) ..................................................................257 15.4.3.9 Debug Status Register (DBGS) .....................................................................258 Appendix A Electrical Characteristics A.1 Introduction ...................................................................................................................................259 A.2 Parameter Classification ................................................................................................................259 A.3 Absolute Maximum Ratings ..........................................................................................................259 A.4 Thermal Characteristics .................................................................................................................260 A.5 Electrostatic Discharge (ESD) Protection Characteristics ............................................................262 A.6 DC Characteristics .........................................................................................................................262 A.7 Supply Current Characteristics ......................................................................................................266 A.8 ATD Characteristics ......................................................................................................................272 A.9 Internal Clock Generation Module Characteristics .......................................................................274 A.9.1 ICG Frequency Specifications ........................................................................................275 A.10 AC Characteristics .........................................................................................................................276 A.10.1 Control Timing ...............................................................................................................277 A.10.2 Timer/PWM (TPM) Module Timing ..............................................................................278 A.10.3 SPI Timing ......................................................................................................................280 A.11 FLASH Specifications ...................................................................................................................283 Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................285 B.1.1 Device Numbering Scheme ............................................................................................285 B.2 Mechanical Drawings ....................................................................................................................285 MC9S08GT16A/GT8A Data Sheet, Rev. 1 18 Freescale Semiconductor

Chapter 1 Device Overview 1.1 Introduction The MC9S08GT16A/GT8A are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types (see Table1-1). 1.1.1 Devices in the MC9S08GT16A/GT8A Series Table1-1liststhedevicesavailableintheMC9S08GT16A/GT8Aseriesandsummarizesthedifferences among them. Table1-1. Devices in the MC9S08GT16A/GT8A Series Device FLASH RAM TPM ATD KBI I/O Packages (1)3-ch,(1)2-ch,16-bit 8 8 39 48 QFN (2) 2-ch, 16-bit 8 8 36 44 QFP MC9S08GT16A 16K 2K (2) 2-ch, 16-bit 8 8 34 42 SDIP (1)2-ch,(1)1-ch,16-bit 4 4 24 32 QFN MC9S08GT8A 8K 1K (1)3-ch,(1)2-ch,16-bit 8 8 39 48 QFN (2) 2-ch, 16-bit 8 8 36 44 QFP (2) 2-ch, 16-bit 8 8 34 42 SDIP (1)2-ch,(1)1-ch,16-bit 4 4 24 32 QFN 1.1.2 MCU Block Diagram This block diagrams show the structure of the MC9S08GT16A/GT8A MCUs. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 19

Device Overview VREFLVREFHVSSADVDDAD 4 HCS08 CORE BKGD 8IN-BTIETR KREUYPBTO (AKRBDI) 8 PORT A 4 PPPTTTAAA347///KKKBBBIIIPPP347–– NOTE 6 PTA0/KBIP0 CPU BDC 4 10-BIT 8 T B PPTTBB74//AADDPP74– ANALOG-TO-DIGITAL OR 4 HCS08 SYSTEM CONTROL CONVERTER (ATD) P PTB3/ADP3– RESET PTB0/ADP0 NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION PTC7 POWER MANAGEMENT PTC6 PTC5 RTI COP INTER-IC (IIC) SSDCAL PORT C PPPTTTCCC432//SSCDAL NOTE 5 IRQ IRQ LVD RXD2 NOTES 2, 3 SERIAL COMMUNICATIONS PTC1/RxD2 TXD2 INTERFACE (SCI2) PTC0/TxD2 CH1 USER FLASH 2-CHANNEL TIMER/PWM PTD4/TPM2CH1 CH0 (GT16A = 16,384 BYTES) (TPM2) PTD3/TPM2CLK/TPM2CH0 (GT8A = 8192 BYTES) D CH0 RT O PTD2/TPM1CH2 3-CHANNEL TIMER/PWM CH1 P PTD1/TPM1CH1 (TPM1) CH2 PTD0/TPM1CLK/TPM1CH0 USER RAM (GT16A = 2048 BYTES) SPSCK (GT8A = 1024 BYTES) PTE5/SPSCK MOSI SERIAL PERIPHERAL PTE4/MOSI MISO ON-CHIP ICE INTERFACE (SPI) SS RT E PPTTEE32//SMSISO DEBUG O RXD1 P MODULE (DBG) SERIAL COMMUNICATIONS PTE1/RxD1 TXD1 INTERFACE (SCI1) PTE0/TxD1 INTERNAL CLOCK GENERATOR (ICG) PTG3 EXTAL G PTG2/EXTAL XTAL T LOW-POWER OSCILLATOR R PTG1/XTAL BKGD O P PTG0/BKGD/MS V DD VOLTAGE V SS REGULATOR = Pins not available in 44-, 42-, or 32-pin packages V SS = Pins not available in 42- or 32-pin packages = Pins not available in 32-pin packages NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE=1). 3. IRQ does not have a clamp diode to V . IRQ should not be driven above V . DD DD 4. Pin contains integrated pullup device. 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1). Figure1-1. MC9S08GT16A/GT8A Block Diagram MC9S08GT16A/GT8A Data Sheet, Rev. 1 20 Freescale Semiconductor

Device Overview Table1-2 lists the functional versions of the on-chip modules. Table1-2. Block Versions Module Version Analog-to-Digital Converter (ATD) 3 Internal Clock Generator (ICG) 4 Inter-Integrated Circuit (IIC) 1 Keyboard Interrupt (KBI) 1 Serial Communications Interface (SCI) 1 Serial Peripheral Interface (SPI) 3 Timer Pulse-Width Modulator (TPM) 2 Central Processing Unit (CPU) 2 1.2 System Clock Distribution SYSTEM CONTROL TPM1 TPM2 IIC SCI1 SCI2 SPI LOGIC ICGERCLK RTI FFE ÷ 2 ICG FIXED FREQ CLOCK (XCLK) ICGOUT ÷ BUSCLK 2 ICGLCLK* CPU BDC COP ATD RAM FLASH ATD has min and max FLASH has frequency frequency requirements. requirements for program * ICGLCLK is the alternate BDC clock source for the MC9S08GT16A/GT8A. SeeChapter14, “Ana- and erase operation. log-to-Digital Converter SeeAppendixA, “Electrical (S08ATDV3)” Characteristics”. andAppendixA, “Electrical Characteristics.” Figure1-2. System Clock Distribution Diagram MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 21

Device Overview Some of the modules inside the MCU have clock source choices.Figure1-2 shows a simplified clock connection diagram. The ICG supplies the clock sources: • ICGOUT is an output of the ICG module. It is one of the following: — The external crystal oscillator — An external clock source — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop sub-module Control bits inside the ICG determine which source is connected. • FFEisacontrolsignalgeneratedinsidetheICG.IfthefrequencyofICGOUT>4×thefrequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be the ICGERCLK. Otherwise the fixed-frequency clock will be BUSCLK. • ICGLCLK — Development tools can select this internal self-clocked source (~ 8MHz) to speed up BDC communications in systems where the bus clock is slow. • ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. MC9S08GT16A/GT8A Data Sheet, Rev. 1 22 Freescale Semiconductor

Chapter 2 Pins and Connections 2.1 Introduction Thissectiondescribessignalsthatconnecttopackagepins.Itincludesapinoutdiagram,atableofsignal properties, and detailed discussion of signals. 2.2 Device Pin Assignment S M TAL AL GD/ P7 P6 P5 P4 P3 P2 X T K BI BI BI BI BI BI E X B K K K K K K G3 G2/ G1/ G0/ SAD DAD A7/ A6/ A5/ A4/ A3/ A2/ T T T T S D T T T T T T P P P P V V P P P P P P RESET 1 48 47 46 45 44 43 42 41 40 39 38 3736 PTA1/KBIP1 PTC0/TxD2 2 35 PTA0/KBIP0 PTC1/RxD2 3 34 VREFL PTC2/SDA 4 33 VREFH PTC3/SCL 5 32 PTB7/ADP7 PTC4 6 31 PTB6/ADP6 PTC5 7 30 PTB5/ADP5 PTC6 8 29 PTB4/ADP4 PTC7 9 28 PTB3/ADP3 PTE0/TxD1 10 27 PTB2/ADP2 PTE1/RxD1 11 26 PTB1/ADP1 IRQ 12 25 PTB0/ADP0 13 14 15 16 17 18 19 20 21 22 23 24 PTE2/SS PTE3/MISO PTE4/MOSI TE5/SPSCK VSS1 VSS2 VDD K/TPM1CH0 1/TPM1CH1 2/TPM1CH2 K/TPM2CH0 4/TPM2CH1 P L D D L D C T T C T 1 P P 2 P M M P P T T 0/ 3/ D D T T P P Figure2-1. MC9S08GT16A/GT8A in 48-Pin QFN Package MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 23

Pins and Connections S M TAL AL GD/ P7 P6 P5 P4 P3 P2 X T K BI BI BI BI BI BI E X B K K K K K K G2/ G1/ G0/ SAD DAD A7/ A6/ A5/ A4/ A3/ A2/ T T T S D T T T T T T P P P V V P P P P P P RESET 1 44 43 42 41 40 39 38 37 36 35 3433 PTA1/KBIP1 PTC0/TxD2 2 32 PTA0/KBIP0 PTC1/RxD2 3 31 VREFL PTC2/SDA 4 30 VREFH PTC3/SCL 5 29 PTB7/ADP7 PTC4 6 28 PTB6/ADP6 PTC5 7 27 PTB5/ADP5 PTC6 8 26 PTB4/ADP4 PTE0/TxD1 9 25 PTB3/ADP3 PTE1/RxD1 10 24 PTB2/ADP2 IRQ 11 23 PTB1/ADP1 12 13 14 15 16 17 18 19 20 21 22 E2/SS MISO MOSI PSCK VSS VDD 1CH0 1CH1 2CH0 2CH1 ADP0 T 3/ 4/ S M M M M 0/ P E E 5/ P P P P B T T E T T T T T P P T K/ 1/ K/ 4/ P P L D L D C T C T 1 P 2 P M M P P T T 0/ 3/ D D T T P P Figure2-2. MC9S08GT16A/GT8A in 44-Pin QFP Package MC9S08GT16A/GT8A Data Sheet, Rev. 1 24 Freescale Semiconductor

Pins and Connections VDDAD 1 42 PTA7/KBIP7 VSSAD 2 41 PTA6/KBIP6 PTG0/BKGD/MS 3 40 PTA5/KBIP5 PTG1/XTAL 4 39 PTA4/KBIP4 PTG2/EXTAL 5 38 PTA3/KBIP3 RESET 6 37 PTA2/KBIP2 PTC0/TxD2 7 36 PTA1/KBIP1 PTC1/RXD2 8 35 PTA0/KBIP0 PTC2/SDA 9 34 VREFL PTC3/SCL 10 33 V REFH PTC4 11 32 PTB7/ADP7 PTE0/TxD1 12 31 PTB6/ADP6 PTE1/RxD1 13 30 PTB5/ADP5 IRQ 14 29 PTB4/ADP4 PTE2/SS 15 28 PTB3/ADP3 PTE3/MISO 16 27 PTB2/ADP2 PTE4/MOSI 17 26 PTB1/ADP1 PTE5/SPSCK 18 25 PTB0/ADP0 VSS 19 24 PTD4/TPM2CH1 VDD 20 23 PTD3/TPM2CLK/TPM2CH0 PTD0/TPM1CLK/TPM1CH0 21 22 PTD1/TPM1CH1 Figure2-3. MC9S08GT16A/GT8A in 42-Pin SDIP Package MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 25

Pins and Connections L XTA TAL KGD BIP7 BIP6 BIP5 E X B K K K TG2/ TG1/ TG0/ SSAD DDAD TA7/ TA6/ TA5/ P P P V V P P P 32 31 30 29 28 27 26 25 RESET 1 24 PTA4/KBIP4 PTC0/TxD2 2 23 VREFL PTC1/RxD2 3 22 VREFH PTC2/SDA 4 21 PTB3/ADP3 PTC3/SCL 5 20 PTB2/ADP2 PTE0/TxD1 6 19 PTB1/ADP1 PTE1/RxD1 7 18 PTB0/ADP0 IRQ 8 17 PTD3/TPM2CLK/TPM2CH0 9 10 11 12 13 14 15 16 TE2/SS 3/MISO 4/MOSI SPSCK VSS VDD M1CH0 M1CH1 P E E 5/ P P T T E T T P P T K/ 1/ P L D C T 1 P M P T 0/ D T P Figure2-4. MC9S08GT16A/GT8A in 32-Pin QFN Package MC9S08GT16A/GT8A Data Sheet, Rev. 1 26 Freescale Semiconductor

Pins and Connections 2.3 Recommended System Connections Figure2-5showspinconnectionsthatarecommontoalmostallMC9S08GT16Aapplicationsystems.A more detailed discussion of system connections follows. VREFH PTA0/KBIP0 VDDAD MC9S08GT16A PTA1/KBIP1 C BYAD PTA2/KBIP2 0.1µF PTA3/KBIP3 V PORT SYSTEM VDD VSSAD A PTA4/KBIP4 POWER VREFL PTA5/KBIP5 DD + PTA6/KBIP6 3 V 1C0BµLKF+ 0.1CµBFY PTA7/KBIP7 V SS NOTE4 PTB0/ADP0 V SS PTB1/ADP1 BACKGROUND HEADER PTB2/ADP2 V BKGD/MS PORT PTB3/ADP3 DD B PTB4/ADP4 V DD PTB5/ADP5 I/O AND PTB6/ADP6 4.7 kΩ–10 kΩ PTB7/ADP7 PERIPHERAL 0.1 µF RNEOSTEET 3 PTC0/TxD2 INTERFACE TO PTC1/RxD2 APPLICATION OPTIONAL MANUAL VDD PTC2/SDA SYSTEM RESET PORT PTC3/SCL 4.7 kΩ–10 kΩ C PTC4 ASYNCHRONOUS PTC5 INTERRUPT IRQ INPUT 0.1 µF NOTE 3 PTC6 PTC7 PTD0/TPM1CLK/TPM1CH0 PTG0/BKDG/MS PTD1/TPM1CH1 PTG1/XTAL PORT PORT PTD2/TPM1CH2 PTG2/EXTAL G D PTD3/TPM2CLK/TPM2CH0 PTG3 PTD4/TPM2CH1 NOTE 1 R F RS XTAL PTE0/TxD1 PTE1/RxD1 C1 X1 C2 PTE2/SS PORT E PTE3/MISO EXTAL PTE4/MOSI PTE5/SPSCK NOTES: 1. Not required if using the internal oscillator option. 2. The 48-pin QFN has 2 V pins (V and V ), both of which must be connected to GND. SS SS1 SS2 3. RC filters onRESET and IRQ are recommended for EMC-sensitive applications and systems. Figure2-5. Basic System Connections MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 27

Pins and Connections 2.3.1 V , V , V , V , V , V — Power and Voltage DD SS DDAD SSAD REFH REFL References V and V are the primary power supply pins for the MCU. This voltage source supplies power to all DD SS I/Obuffercircuitryandtoaninternalvoltageregulator.Theinternalvoltageregulatorprovidesregulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there shouldbeabulkelectrolyticcapacitor,suchasa10-µFtantalumcapacitor,toprovidebulkchargestorage for the overall system and a 0.1-µF ceramic bypass capacitor located as close to the MCU power pins as practical to suppress high-frequency noise. NOTE The 48-pin QFN version of the MC9S08GT16A/GT8A has two adjacent V pins. Both pins must be connected to ground with zero impedance SS between them. V andV aretheanalogpowersupplypinsfortheMCU.Thisvoltagesourcesuppliespowerto DDAD SSAD theATD.A0.1-µFceramicbypasscapacitorshouldbelocatedasclosetotheMCUpowerpinsaspractical to suppress high-frequency noise. V and V are the reference voltages for the analog-to-digital converter and for most accurate REFH REFL performance, they must be connected directly to V and V with the shortest traces possible. DDAD SSAD 2.3.2 PTG1/XTAL, PTG2/EXTAL — Oscillator Immediatelyafterreset,theMCUusesaninternallygeneratedclock(self-clockedmode—f ),that Self_reset is approximately equivalent to an 8-MHz crystal rate. This frequency source is used during reset startup andcanbeenabledastheclocksourceforstoprecoverytoavoidtheneedforalongcrystalstartupdelay. This MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the MCU. For more information on the ICG, seeChapter9, “Internal Clock Generator (S08ICGV4).” TheoscillatoramplitudeonXTALandEXTALisgainlimitedforlow-poweroscillation.Typically,these pinshavea1-Vpeak-to-peaksignal.Fornoisyenvironments,thehighgainoutput(HGO)bitcanbesetto enable rail-to-rail oscillation. The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in eitheroftwofrequencyrangesselectedbytheRANGEbitintheICGC1register.Ratherthanacrystalor ceramicresonator,anexternaloscillatorcanbeconnectedtotheEXTALinputpin,andtheXTALoutput pin can be used as general I/O. The external oscillator amplitude must not exceed V . DD Refer to Figure2-5 for the following discussion. R (when used) and R should be low-inductance S F resistorssuchascarboncompositionresistors.Wire-woundresistors,andsomemetalfilmresistors,have toomuchinductance.C1andC2normallyshouldbehigh-qualityceramiccapacitorsthatarespecifically designed for high-frequency applications. R isusedtoprovideabiaspathtokeeptheEXTALinputinitslinearrangeduringcrystalstartupandits F valueisnotgenerallycritical.Typicalsystemsuse1MΩto10MΩ.Highervaluesaresensitivetohumidity and lower values reduce gain and (in extreme cases) could prevent startup. MC9S08GT16A/GT8A Data Sheet, Rev. 1 28 Freescale Semiconductor

Pins and Connections C1andC2aretypicallyinthe5-pFto25-pFrangeandarechosentomatchtherequirementsofaspecific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitancewhensizingC1andC2.Thecrystalmanufacturertypicallyspecifiesaloadcapacitancewhich is the series combination of C1 and C2 which are usually the same size. As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). 2.3.3 RESET — External Reset Pin RESETisadedicatedpinwithapullupdevicebuiltin.Ithasinputhysteresis,ahighcurrentoutputdriver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debugconnectorsoadevelopmentsystemcandirectlyresettheMCUsystem.Ifdesired,amanualexternal reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). Wheneveranyresetisinitiated(whetherfromanexternalsignalorfromaninternalsystem),theresetpin is driven low for approximately 34 cycles of f , released, and sampled again approximately Self_reset 38cyclesoff later.Ifresetwascausedbyaninternalsourcesuchaslow-voltageresetorwatchdog Self_reset timeout,thecircuitryexpectstheresetpinsampletoreturnalogic1.Theresetcircuitrydecodesthecause of reset and records it by setting a corresponding bit in the system control reset status register (SRS). ForEMC-sensitiveapplications,anexternalRCfilterisrecommendedontheRESETpin.SeeFigure 2-5 for an example. 2.3.4 PTG0/BKGD/MS — Background / Mode Select Thebackground/modeselect(BKGD/MS)sharesitsfunctionwithanI/Oportpin.Whileinreset,thepin functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and can be used for background debug communication. While functioning as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew rate control. When used as an I/O port (PTG0) the pin is limited to output only. Ifnothingisconnectedtothispin,theMCUwillenternormaloperatingmodeattherisingedgeofreset. Ifadebugsystemisconnectedtothe6-pinstandardbackgrounddebugheader,itcanholdBKGD/MSlow during the rising edge of reset which forces the MCU to active background mode. TheBKGDpinisusedprimarilyforbackgrounddebugcontroller(BDC)communicationsusingacustom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clockcouldbeasfastasthemaximumbusclockrate,sothereshouldneverbeanysignificantcapacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cablesandtheabsolutevalueoftheinternalpullupdeviceplayalmostnoroleindeterminingriseandfall times on the BKGD pin. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 29

Pins and Connections 2.3.5 IRQ — External Interrupt Request Pin IRQisadedicatedpinwithbothpullupandpulldowndevicesbuiltin.Thispinhasnooutputcapabilities. Afterasystemreset,theIRQpinisdisabledandmustbeenabledbeforeuse.SeeSection5.4.2,“IRQ— External Interrupt Request Pin” for more details. ForEMC-sensitiveapplications,anexternalRCfilterisrecommendedontheIRQpin.SeeFigure2-5for an example. 2.3.6 General-Purpose I/O and Peripheral Ports The remaining 36 pins are shared among general-purpose I/O and on-chip peripheral functions such as timersandserialI/Osystems.(Threeofthesepinsarenotbondedoutonthe44-pinpackage,fivearenot bonded out on the 42-pin package, and 15 are not bonded out on the 32-pin package.) Immediately after reset, all 36 of these pins are configured as high-impedance general-purpose inputs with internal pullup devices disabled. NOTE Toavoidextracurrentdrainfromfloatinginputpins,theresetinitialization routine in the application program should either enable on-chip pullup devicesorchangethedirectionofunusedpinstooutputssothepinsdonot float. For information about controlling these pins as general-purpose I/O pins, seeChapter6, “Parallel Input/Output.”Forinformationabouthowandwhenon-chipperipheralsystemsusethesepins,refertothe appropriate section fromTable 2-1. Table2-1. Pin Sharing References Port Pins Alternate Function Reference1 PTA7–PTA0 KBIP7–KBIP0 Chapter7, “Keyboard Interrupt (S08KBIV1)” PTB7–PTB0 ADP7–ADP0 Chapter14, “Analog-to-Digital Converter (S08ATDV3)” PTC7–PTC4 PTC3–PTC2 SCL–SDA Chapter13, “Inter-Integrated Circuit (S08IICV1)” PTC1–PTC0 RxD2–TxD2 Chapter11, “Serial Communications Interface (S08SCIV1)” PTD4–PTD3 TPM2CH1–TPM2CH0, TPM2CLK Chapter10, “Timer/PWM (S08TPMV2)” PTD2–PTD0 TPM1CH2–TPM1CH0, TPM1CLK Chapter10, “Timer/PWM (S08TPMV2)” PTE5 SPSCK PTE4 MISO Chapter12, “Serial Peripheral Interface (S08SPIV3)” PTE3 MOSI PTE2 SS PTE1–PTE0 RxD1–TxD1 Chapter11, “Serial Communications Interface (S08SCIV1)” PTG3 PTG2–PTG1 EXTAL–XTAL Chapter9, “Internal Clock Generator (S08ICGV4)” PTG0 BKGD/MS Chapter15, “Development Support” 1 See this section for information about modules that share these pins. MC9S08GT16A/GT8A Data Sheet, Rev. 1 30 Freescale Semiconductor

Pins and Connections Whenanon-chipperipheralsystemiscontrollingapin,datadirectioncontrolbitsstilldeterminewhatis read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin’s output buffer. SeeChapter6, “Parallel Input/Output,” for details. Pullupenablebitsforeachinputpincontrolwhetheron-chippullupdevicesareenabledwheneverthepin isactingasaninputevenifitisbeingcontrolledbyanon-chipperipheralmodule.WhenthePTA7–PTA4 pinsarecontrolledbytheKBImoduleandareconfiguredforrising-edge/high-levelsensitivity,thepullup enablecontrolbitsenablepulldowndevicesratherthanpullupdevices.Similarly,whenIRQisconfigured astheIRQinputandissettodetectrisingedges,thepullupenablecontrolbitenablesapulldowndevice rather than a pullup device. 2.3.7 Signal Properties Summary Table2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the common pin interfaces are hardwired to internal circuits. Table2-2. Signal Properties Pin HighCurrent Output Dir Pull-Up2 Comments Name Pin Slew1 VDD — — — The 48-pin QFN package has two V pins VSS — — — — V and V . SS SS1 SS2 VDDAD — — — VSSAD — — — VREFH — — — VREFL — — — RESET I/O Y N Y Pin contains integrated pullup. IRQPE must be set to enable IRQ function. IRQ does not have a clamp diode to V . DD IRQ should not be driven above V . DD Pullup/pulldown active when IRQ pin IRQ I — — Y function enabled. Pullup forced on when IRQ enabled for falling edges; pulldown forced on when IRQ enabled for rising edges. PTA0/KBIP0 I/O N SWC SWC PTA1/KBIP1 I/O N SWC SWC PTA2/KBIP2 I/O N SWC SWC PTA3/KBIP3 I/O N SWC SWC PTA4/KBIP4 I/O N SWC SWC Pullup/pulldown active when KBI pin PTA5/KBIP5 I/O N SWC SWC function enabled. Pullup forced on when KBIPx enabled for falling edges; pulldown PTA6/KBIP6 I/O N SWC SWC forced on when KBIPx enabled for rising PTA7/KBIP7 I/O N SWC SWC edges. PTB0/ADP0 I/O N SWC SWC PTB1/ADP1 I/O N SWC SWC PTB2/ADP2 I/O N SWC SWC MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 31

Pins and Connections Table2-2. Signal Properties (continued) Pin HighCurrent Output Dir Pull-Up2 Comments Name Pin Slew1 PTB3/ADP3 I/O N SWC SWC PTB4/ADP4 I/O N SWC SWC Not available on 32-pin pkg PTB5/ADP5 I/O N SWC SWC Not available on 32-pin pkg PTB6/ADP6 I/O N SWC SWC Not available on 32-pin pkg PTB7/ADP7 I/O N SWC SWC Not available on 32-pin pkg PTC0/TxD2 I/O Y SWC SWC WhenpinisconfiguredforSCIfunction,pin PTC1/RxD2 I/O Y SWC SWC is configured for partial output drive. PTC2/SDA I/O Y SWC SWC PTC3/SCL I/O Y SWC SWC PTC4 I/O Y SWC SWC Not available on 32-pin pkg PTC5 I/O Y SWC SWC Not available on 32-pin or 42-pin pkg PTC6 I/O Y SWC SWC Not available on 32-pin or 42-pin pkg PTC7 I/O Y SWC SWC Not available on 32-pin, 42- or 44-pin pkg PTD0/TPM1CLK/TPM1CH0 I/O N SWC SWC PTD1/TPM1CH1 I/O N SWC SWC PTD2/TPM1CH2 I/O N SWC SWC Not available on 32-pin, 42- or 44-pin pkg PTD3/TPM2CLK/TPM2CH0 I/O N SWC SWC PTD4/TPM2CH1 I/O N SWC SWC Not available on 32-pin pkg PTE0/TxD1 I/O N SWC SWC PTE1/RxD1 I/O N SWC SWC PTE2/SS I/O N SWC SWC PTE3/MISO I/O N SWC SWC PTE4/MOSI I/O N SWC SWC PTE5/SPSCK I/O N SWC SWC Pullupenabledandslewratedisabledwhen PTG0/BKGD/MS O N SWC SWC BDM function enabled. Pullup and slew rate disabled when XTAL PTG1/XTAL I/O N SWC SWC pin function. Pullup and slew rate disabled when EXTAL PTG2/EXTAL I/O N SWC SWC pin function. PTG3 I/O N SWC SWC Not available on 32-pin, 42-, or 44-pin pkg 1 SWC is software controlled slew rate, the register is associated with the respective port. 2 SWC is software controlled pullup resistor, the register is associated with the respective port. MC9S08GT16A/GT8A Data Sheet, Rev. 1 32 Freescale Semiconductor

Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08GT16A/GT8A are described in this section. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.1.1 Features • Active background mode for code development • Wait mode: — CPU shuts down to conserve power — System clocks running — Full voltage regulation maintained • Stop modes: — Stop1 — Full power down of internal circuits for maximum power savings — Stop2 — Partial power down of internal circuits, RAM contents retained — Stop3 — All internal circuits powered for fast recovery 3.2 Run Mode This is the normal operating mode for the MC9S08GT16A/GT8A. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset. 3.3 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip ICE debug module (DBG), provide the means for analyzing MCU operation during software development. Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 33

Modes of Operation Afterenteringactivebackgroundmode,theCPUisheldinasuspendedstatewaitingforserialbackground commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run mode; non-intrusive commands can also be executed while the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command • Activebackgroundcommands,whichcanbeexecutedonlywhiletheMCUisinactivebackground mode. Active background commands include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user’s application program (GO) TheactivebackgroundmodeisusedtoprogramabootloaderoruserapplicationprogramintotheFLASH program memory before the MCU is operated in run mode for the first time. When the MC9S08GT16A/GT8A is shipped from the Freescale Semiconductor factory, the FLASH program memoryiserasedbydefaultunlessspecificallynotedsothereisnoprogramthatcouldbeexecutedinrun modeuntiltheFLASHmemoryisinitiallyprogrammed.Theactivebackgroundmodecanalsobeusedto erase and reprogram the FLASH memory after it has been previously programmed. For additional information about the active background mode, refer toChapter15, “Development Support.” 3.4 Wait Mode WaitmodeisenteredbyexecutingaWAITinstruction.UponexecutionoftheWAITinstruction,theCPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available whentheMCUisinwaitmode.Thememory-access-with-statuscommandsdonotallowmemoryaccess, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. MC9S08GT16A/GT8A Data Sheet, Rev. 1 34 Freescale Semiconductor

Modes of Operation 3.5 Stop Modes One of three stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In all stop modes, all internal clocks are halted. If the STOPE bit is not set whentheCPUexecutesaSTOPinstruction,theMCUwillnotenteranyofthestopmodesandanillegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2. Table3-1 summarizes the behavior of the MCU in each of the stop modes. Table3-1. Stop Mode Behavior CPU, Digital Mode PDC PPDC Peripherals, RAM ICG ATD Regulator I/O Pins RTI FLASH Stop1 1 0 Off Off Off Disabled1 Off Reset Off Stop2 1 1 Off Standby Off Disabled Standby States Optionally on held Stop3 0 Don’t Standby Standby Off2 Disabled Standby States Optionally on care held 1 Either ATD stop mode or power-down mode depending on the state of ATDPU. 2 Crystal oscillator can be configured to run in stop3. Please see the ICG registers. 3.5.1 Stop1 Mode Thestop1modeprovidesthelowestpossiblestandbypowerconsumptionbycausingtheinternalcircuitry oftheMCUtobepowereddown.Stop1canbeenteredonlyiftheLVDcircuitisnotenabledinstopmodes (either LVDE or LVDSE not set). WhentheMCUisinstop1mode,allinternalcircuitsthatarepoweredfromthevoltageregulatorareturned off. The voltage regulator is in a low-power standby state, as is the ATD. Exitfromstop1isperformedbyassertingeitherofthewake-uppinsontheMCU:RESETorIRQ.IRQis alwaysanactivelowinputwhentheMCUisinstop1,regardlessofhowitwasconfiguredbeforeentering stop1. Enteringstop1modeautomaticallyassertsLVD.Stop1cannotbeexiteduntilV >V rising(V DD LVDH/L DD must rise above the LVI rearm voltage). Upon wake-up from stop1 mode, the MCU will start up as from a power-on reset (POR). The CPU will take the reset vector. 3.5.2 Stop2 Mode The stop2 mode provides very low standby power consumption and maintains the contents of RAM and thecurrentstate ofalloftheI/Opins. Stop2canbe enteredonly iftheLVD circuitisnot enabledin stop modes (either LVDE or LVDSE not set). MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 35

Modes of Operation Beforeenteringstop2mode,theusermustsavethecontentsoftheI/Oportregisters,aswellasanyother memory-mappedregisterstheywanttorestoreafterexitofstop2,tolocationsinRAM.Uponexitofstop2, these values can be restored by user software before pin latches are opened. WhentheMCUisinstop2mode,allinternalcircuitsthatarepoweredfromthevoltageregulatorareturned off,exceptfortheRAM.Thevoltageregulatorisinalow-powerstandbystate,asistheATD.Uponentry intostop2,thestatesoftheI/Opinsarelatched.Thestatesareheldwhileinstop2modeandafterexiting stop2 mode until a 1 is written to PPDACK in SPMSC2. Exit from stop2 is performed by asserting either of the wake-up pins:RESET or IRQ, or by an RTI interrupt.IRQisalwaysanactivelowinputwhentheMCUisinstop2,regardlessofhowitwasconfigured before entering stop2. Uponwake-upfromstop2mode,theMCUwillstartupasfromapower-onreset(POR)exceptpinstates remainlatched.TheCPUwilltaketheresetvector.Thesystemandallperipheralswillbeintheirdefault reset states and must be initialized. Afterwakingupfromstop2,thePPDFbitinSPMSC2isset.Thisflagmaybeusedtodirectusercodeto gotoastop2recoveryroutine.PPDFremainssetandtheI/Opinstatesremainlatcheduntila1iswritten to PPDACK in SPMSC2. To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the registerbitswillassumetheirresetstateswhentheI/OpinlatchesareopenedandtheI/Opinswillswitch to their reset states. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.5.3 Stop3 Mode Uponenteringthestop3mode,alloftheclocksintheMCU,includingtheoscillatoritself,arehalted.The ICGisturnedoff,theATDisdisabled,andthevoltageregulatorisputinstandby.Thestatesofallofthe internalregistersandlogic,aswellastheRAMcontent,aremaintained.TheI/Opinstatesarenotlatched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained. Exitfromstop3isperformedbyassertingRESET,anasynchronousinterruptpin,orthroughthereal-time interrupt. The asynchronous interrupt pins are the IRQ or KBI pins. Ifstop3isexitedbymeansoftheRESETpin,thentheMCUwillberesetandoperationwillresumeafter takingtheresetvector.Exitbymeansofanasynchronousinterruptorthereal-timeinterruptwillresultin the MCU taking the appropriate interrupt vector. A separate self-clocked source (≈1kHz) for the real-time interrupt allows a wakeup from stop2 or stop3 mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function MC9S08GT16A/GT8A Data Sheet, Rev. 1 36 Freescale Semiconductor

Modes of Operation andthis1-kHzsourcearedisabled.Powerconsumptionislowerwhenthe1-kHzsourceisdisabled,butin that case the real-time interrupt cannot wake the MCU from stop. 3.5.4 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. ThisregisterisdescribedintheChapter15,“DevelopmentSupport,”sectionofthisdatasheet.IfENBDM issetwhentheCPUexecutesaSTOPinstruction,thesystemclockstothebackgrounddebuglogicremain activewhentheMCUentersstopmodesobackgrounddebugcommunicationisstillpossible.Inaddition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the user attempts to enter either stop1 or stop2 with ENBDM set, the MCU will instead enter stop3. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After the device enters background debug mode, all backgroundcommandsareavailable.ThetablebelowsummarizesthebehavioroftheMCUinstopwhen entry into the background debug mode is enabled. Table3-2. BDM Enabled Stop Mode Behavior CPU, Digital Mode PDC PPDC Peripherals, RAM ICG ATD Regulator I/O Pins RTI FLASH Stop3 Don’t Don’t Standby Standby Active Disabled1 Active States Optionally on care care held 1 Either ATD stop mode or power-down mode depending on the state of ATDPU. 3.5.5 LVD Enabled in Stop Mode TheLVDsystemiscapableofgeneratingeitheraninterruptoraresetwhenthesupplyvoltagedropsbelow theLVDvoltage.IftheLVDisenabledinstopbysettingtheLVDEandtheLVDSEbitsinSPMSC1when the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the user attempts to enter either stop1 or stop2 with the LVD enabled for stop (LVDSE= 1), the MCU will instead enter stop3. The table below summarizes the behavior of the MCU in stop when the LVD is enabled. Table3-3. LVD Enabled Stop Mode Behavior CPU, Digital Mode PDC PPDC Peripherals, RAM ICG ATD Regulator I/O Pins RTI FLASH Stop3 Don’t Don’t Standby Standby Standby Disabled1 Active States Optionally on care care held 1 Either ATD stop mode or power-down mode depending on the state of ATDPU. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 37

Modes of Operation 3.5.6 On-Chip Peripheral Modules in Stop Modes WhentheMCUentersanystopmode,systemclockstotheinternalperipheralmodulesarestopped.Even in the exception case (ENBDM =1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer toSection3.5.1, “Stop1 Mode,”Section3.5.2,“Stop2Mode,”andSection3.5.3,“Stop3Mode,”forspecificinformationonsystem behavior in stop modes. I/O Pins • All I/O pin states remain unchanged when the MCU enters stop3 mode. • IftheMCUisconfiguredtogointostop2mode,allI/Opinsstatesarelatchedbeforeenteringstop. • If the MCU is configured to go into stop1 mode, all I/O pins are forced to their default reset state upon entry into stop. Memory • All RAM and register contents are preserved while the MCU is in stop3 mode. • All registers will be reset upon wake-up from stop2, but the contents of RAM are preserved and pinstatesremainlatcheduntilthePPDACKbitiswritten.Theusermaysaveanymemory-mapped register data into RAM before entering stop2 and restore the data upon exit from stop2. • All registers will be reset upon wake-up from stop1 and the contents of RAM are not preserved. The MCU must be initialized as upon reset. The contents of the FLASH memory are nonvolatile and are preserved in any of the stop modes. ICG — In stop3 mode, the ICG enters its low-power standby state. Either the oscillator or the internal reference may be kept running when the ICG is in standby by setting the appropriate control bit. In both stop2andstop1modes,theICGisturnedoff.Neithertheoscillatornortheinternalreferencecanbekept running in stop2 or stop1, even if enabled within the ICG module. TPM—WhentheMCUentersstopmode,theclocktotheTPM1andTPM2modulesstop.Themodules halt operation. If the MCU is configured to go into stop2 or stop1 mode, the TPM modules will be reset upon wake-up from stop and must be reinitialized. ATD—WhentheMCUentersstopmode,theATDwillenteralow-powerstandbystate. Noconversion operationwilloccurwhileinstop.IftheMCUisconfiguredtogointostop2orstop1mode,theATDwill be reset upon wake-up from stop and must be reinitialized. KBI — During stop3, the KBI pins that are enabled continue to function as interrupt sources that are capableofwakingtheMCUfromstop3.TheKBIisdisabledinstop1andstop2andmustbereinitialized after waking up from either of these modes. SCI — When the MCU enters stop mode, the clocks to the SCI1 and SCI2 modules stop. The modules halt operation. If the MCU is configured to go into stop2 or stop1 mode, the SCI modules will be reset upon wake-up from stop and must be reinitialized. SPI—WhentheMCUentersstopmode,theclockstotheSPImodulestop.Themodulehaltsoperation. IftheMCUisconfiguredtogointostop2orstop1mode,theSPImodulewillberesetuponwake-upfrom stop and must be reinitialized. MC9S08GT16A/GT8A Data Sheet, Rev. 1 38 Freescale Semiconductor

Modes of Operation IIC—WhentheMCUentersstopmode,theclockstotheIICmodulestops.Themodulehaltsoperation. IftheMCUisconfiguredtogointostop2orstop1mode,theIICmodulewillberesetuponwake-upfrom stop and must be reinitialized. VoltageRegulator—Thevoltageregulatorentersalow-powerstandbystatewhentheMCUentersany of the stop modes unless the LVD is enabled in stop mode or BDM is enabled. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 39

Modes of Operation MC9S08GT16A/GT8A Data Sheet, Rev. 1 40 Freescale Semiconductor

Chapter 4 Memory 4.1 MC9S08GT16A/GT8A Memory Map AsshowninFigure4-1,on-chipmemoryintheMC9S08GT16A/GT8AseriesofMCUsconsistsofRAM, FLASHprogrammemoryfornonvolatiledatastorage,plusI/Oandcontrol/statusregisters.Theregisters are divided into three groups: • Direct-page registers (0x0000 through 0x007F) • High-page registers (0x1800 through 0x182B) • Nonvolatile registers (0xFFB0 through 0xFFBF) 0x0000 0x0000 DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS 0x007F 0x007F 0x0080 0x0080 RAM 1024 BYTES RAM 2048 BYTES 0x047F 0x0480 Reserved 1024 BYTES 0x087F 0x087F 0x0880 0x0880 UNIMPLEMENTED UUNNIIMMPPLLEEMMEENNTTEEDD 3968 BYTES 4939926 8B BYYTETESS 0x17FF 0x17FF 0x1800 0x1800 HIGH PAGE REGISTERS HIGH PAGE REGISTERS 0x182B 0x182B 0x182C 0x182C UNIMPLEMENTED UNIMPLEMENTED 42964 BYTES 42964 BYTES 0xBFFF 0xBFFF 0xC000 Reserved 0xC000 FLASH 8192 BYTES 16384 BYTES 0xDFFF 0xE000 FLASH 8192 BYTES 0xFFFF 0xFFFF MC9S08GT16A MC9S08GT8A Figure4-1. MC9S08GT16A/GT8A Memory Map MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 41

Memory 4.1.1 Reset and Interrupt Vector Assignments Table4-1showsaddressassignmentsforresetandinterruptvectors.Thevectornamesshowninthistable arethelabelsusedintheFreescale-providedequatefilefortheMC9S08GT16A/GT8A.Formoredetails about resets, interrupts, interrupt priority, and local interrupt mask controls, refer toChapter5, “Resets, Interrupts, and System Configuration.” Table4-1. Reset and Interrupt Vectors Address Vector Vector Name (High/Low) 0xFFC0:FFC1 Unused Vector Space (available for user program) 0xFFCA:FFCB 0xFFCC:FFCD RTI Vrti 0xFFCE:FFCF IIC Viic 0xFFD0:FFD1 ATD Conversion Vatd 0xFFD2:FFD3 Keyboard Vkeyboard 0xFFD4:FFD5 SCI2 Transmit Vsci2tx 0xFFD6:FFD7 SCI2 Receive Vsci2rx 0xFFD8:FFD9 SCI2 Error Vsci2err 0xFFDA:FFDB SCI1 Transmit Vsci1tx 0xFFDC:FFDD SCI1 Receive Vsci1rx 0xFFDE:FFDF SCI1 Error Vsci1err 0xFFE0:FFE1 SPI Vspi 0xFFE2:FFE3 TPM2 Overflow Vtpm2ovf Unused Vector Space 0xFFE4:FFE9 (available for user program) 0xFFEA:FFEB TPM2 Channel 1 Vtpm2ch1 0xFFEC:FFED TPM2 Channel 0 Vtpm2ch0 0xFFEE:FFEF TPM1 Overflow Vtpm1ovf 0xFFF0:FFF1 TPM1 Channel 2 Vtpm1ch2 0xFFF2:FFF3 TPM1 Channel 1 Vtpm1ch1 0xFFF4:FFF5 TPM1 Channel 0 Vtpm1ch0 0xFFF6:FFF7 ICG Vicg 0xFFF8:FFF9 Low Voltage Detect Vlvd 0xFFFA:FFFB IRQ Virq 0xFFFC:FFFD SWI Vswi 0xFFFE:FFFF Reset Vreset MC9S08GT16A/GT8A Data Sheet, Rev. 1 42 Freescale Semiconductor

Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08GT16A/GT8A are divided into these three groups: • Direct-page registers are located in the first 128 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables. • The nonvolatile register area consists of a block of 16 locations in FLASH memory at 0xFFB0–0xFFBF. Nonvolatile register locations include: — Three values which are loaded into working registers at reset — An 8-byte backdoor comparison key which optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations. Direct-pageregisterscanbeaccessedwithefficientdirectaddressingmodeinstructions.Bitmanipulation instructions can be used to access any bit in any direct-page register.Table4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers inTable 4-2 can use the more efficient direct addressing mode which only requires the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. InTable4-3 and Table4-4 the whole address in column one is shown in bold. In Table4-2,Table4-3,andTable4-4,theregisternamesincolumntwoareshowninboldtosetthemapart fromthebitnamestotheright.Cellsthatarenotassociatedwithnamedbitsareshaded.Ashadedcellwith a0indicatesthisunusedbitalwaysreadsasa0.Shadedcellswithdashesindicateunusedorreservedbit locations that could read as 1s or 0s. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 43

Memory Table4-2. Direct-Page Register Summary (Sheet 1 of 3) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 PTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 0x0001 PTAPE PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 0x0002 PTASE PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 0x0003 PTADD PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0 0x0004 PTBD PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 0x0005 PTBPE PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0x0006 PTBSE PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 0x0007 PTBDD PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0 0x0008 PTCD PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 0x0009 PTCPE PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0x000A PTCSE PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0 0x000B PTCDD PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0 0x000C PTDD 0 0 0 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0 0x000D PTDPE 0 0 0 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 0x000E PTDSE 0 0 0 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 0x000F PTDDD 0 0 0 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0 0x0010 PTED 0 0 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0 0x0011 PTEPE 0 0 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 0x0012 PTESE 0 0 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0 0x0013 PTEDD 0 0 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0 0x0014 IRQSC 0 0 IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD 0x0015 Reserved — — — — — — — — 0x0016 KBISC KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBF KBACK KBIE KBIMOD 0x0017 KBIPE KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 0x0018 SCI1BDH 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 0x0019 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x001A SCI1C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0x001B SCI1C2 TIE TCIE RIE ILIE TE RE RWU SBK 0x001C SCI1S1 TDRE TC RDRF IDLE OR NF FE PF 0x001D SCI1S2 0 0 0 0 0 0 0 RAF 0x001E SCI1C3 R8 T8 TXDIR 0 ORIE NEIE FEIE PEIE 0x001F SCI1D Bit 7 6 5 4 3 2 1 Bit 0 0x0020 SCI2BDH 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 0x0021 SCI2BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x0022 SCI2C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0x0023 SCI2C2 TIE TCIE RIE ILIE TE RE RWU SBK 0x0024 SCI2S1 TDRE TC RDRF IDLE OR NF FE PF 0x0025 SCI2S2 0 0 0 0 0 0 0 RAF 0x0026 SCI2C3 R8 T8 TXDIR 0 ORIE NEIE FEIE PEIE 0x0027 SCI2D Bit 7 6 5 4 3 2 1 Bit 0 MC9S08GT16A/GT8A Data Sheet, Rev. 1 44 Freescale Semiconductor

Memory Table4-2. Direct-Page Register Summary (Sheet 2 of 3) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0028 SPIC1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0x0029 SPIC2 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0 0x002A SPIBR 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0 0x002B SPIS SPRF 0 SPTEF MODF 0 0 0 0 0x002C Reserved 0 0 0 0 0 0 0 0 0x002D SPID Bit 7 6 5 4 3 2 1 Bit 0 0x002E Reserved 0 0 0 0 0 0 0 0 0x002F Reserved 0 0 0 0 0 0 0 0 0x0030 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0x0031 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x0032 TPM1CNTL Bit 7 6 5 4 3 2 1 Bit 0 0x0033 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8 0x0034 TPM1MODL Bit 7 6 5 4 3 2 1 Bit 0 0x0035 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0x0036 TPM1C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0037 TPM1C0VL Bit 7 6 5 4 3 2 1 Bit 0 0x0038 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 0x0039 TPM1C1VH Bit 15 14 13 12 11 10 9 Bit 8 0x003A TPM1C1VL Bit 7 6 5 4 3 2 1 Bit 0 0x003B TPM1C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0 0x003C TPM1C2VH Bit 15 14 13 12 11 10 9 Bit 8 0x003D TPM1C2VL Bit 7 6 5 4 3 2 1 Bit 0 0x003E– — — — — — — — — Reserved 0x0043 — — — — — — — — 0x0044 PTGD 0 0 0 0 PTGD3 PTGD2 PTGD1 PTGD0 0x0045 PTGPE 0 0 0 0 PTGPE3 PTGPE2 PTGPE1 PTGPE0 0x0046 PTGSE 0 0 0 0 PTGSE3 PTGSE2 PTGSE1 PTGSE0 0x0047 PTGDD 0 0 0 0 PTGDD3 PTGDD2 PTGDD1 PTGDD0 0x0048 ICGC1 HGO RANGE REFS CLKS OSCSTEN LOCD 0 0x0049 ICGC2 LOLRE MFD LOCRE RFD 0x004A ICGS1 CLKST REFST LOLS LOCK LOCS ERCS ICGIF 0x004B ICGS2 0 0 0 0 0 0 0 DCOS 0x004C ICGFLTU 0 0 0 0 FLT 0x004D ICGFLTL FLT 0x004E ICGTRM TRIM 0x004F Reserved 0 0 0 0 0 0 0 0 0x0050 ATDC ATDPU DJM RES8 SGN PRS 0x0051 ATDSC CCF ATDIE ATDCO ATDCH 0x0052 ATDRH Bit 7 6 5 4 3 2 1 Bit 0 0x0053 ATDRL Bit 7 6 5 4 3 2 1 Bit 0 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 45

Memory Table4-2. Direct-Page Register Summary (Sheet 3 of 3) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0054 ATDPE ATDPE7 ATDPE6 ATDPE5 ATDPE4 ATDPE3 ATDPE2 ATDPE1 ATDPE0 0x0055– — — — — — — — — Reserved 0x0057 — — — — — — — — 0x0058 IICA ADDR 0 0x0059 IICF MULT ICR 0x005A IICC IICEN IICIE MST TX TXAK RSTA 0 0 0x005B IICS TCF IAAS BUSY ARBL 0 SRW IICIF RXAK 0x005C IICD DATA 0x005D– — — — — — — — — Reserved 0x005F — — — — — — — — 0x0060 TPM2SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0x0061 TPM2CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x0062 TPM2CNTL Bit 7 6 5 4 3 2 1 Bit 0 0x0063 TPM2MODH Bit 15 14 13 12 11 10 9 Bit 8 0x0064 TPM2MODL Bit 7 6 5 4 3 2 1 Bit 0 0x0065 TPM2C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0x0066 TPM2C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0067 TPM2C0VL Bit 7 6 5 4 3 2 1 Bit 0 0x0068 TPM2C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 0x0069 TPM2C1VH Bit 15 14 13 12 11 10 9 Bit 8 0x006A TPM2C1VL Bit 7 6 5 4 3 2 1 Bit 0 0x006B– — — — — — — — — Reserved 0x007F — — — — — — — — High-pageregisters,showninTable4-3,areaccessedmuchlessoftenthanotherI/Oandcontrolregisters so they have been located outside the direct addressable memory space, starting at 0x1800. Table4-3. High-Page Register Summary Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x1800 SRS POR PIN COP ILOP ILAD ICG LVD 0 0x1801 SBDFR 0 0 0 0 0 0 0 BDFR 0x1802 SOPT COPE COPT STOPE — 0 0 BKGDPE — 0x1803– — — — — — — — — Reserved 0x1805 — — — — — — — — 0x1806 SDIDH ID11 ID10 ID9 ID8 0x1807 SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0x1808 SRTISC RTIF RTIACK RTICLKS RTIE 0 RTIS2 RTIS1 RTIS0 0x1809 SPMSC1 LVDF LVDACK LVDIE LVDRE LVDSE LVDE 0 0 0x180A SPMSC2 LVWF LVWACK LVDV LVWV PPDF PPDACK PDC PPDC 0x180B– — — — — — — — — Reserved 0x180F — — — — — — — — 0x1810 DBGCAH Bit 15 14 13 12 11 10 9 Bit 8 MC9S08GT16A/GT8A Data Sheet, Rev. 1 46 Freescale Semiconductor

Memory Table4-3. High-Page Register Summary (continued) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x1811 DBGCAL Bit 7 6 5 4 3 2 1 Bit 0 0x1812 DBGCBH Bit 15 14 13 12 11 10 9 Bit 8 0x1813 DBGCBL Bit 7 6 5 4 3 2 1 Bit 0 0x1814 DBGFH Bit 15 14 13 12 11 10 9 Bit 8 0x1815 DBGFL Bit 7 6 5 4 3 2 1 Bit 0 0x1816 DBGC DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0x1817 DBGT TRGSEL BEGIN 0 0 TRG3 TRG2 TRG1 TRG0 0x1818 DBGS AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0x1819– — — — — — — — — Reserved 0x181F — — — — — — — — 0x1820 FCDIV DIVLD PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 0x1821 FOPT KEYEN FNORED 0 0 0 0 SEC01 SEC00 0x1822 Reserved — — — — — — — — 0x1823 FCNFG 0 0 KEYACC 0 0 0 0 0 0x1824 FPROT FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS 0x1825 FSTAT FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0 0x1826 FCMD FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0 0x1827– — — — — — — — — Reserved 0x182B — — — — — — — — Nonvolatile FLASH registers, shown inTable 4-4, are located in the FLASH memory. These registers includean8-bytebackdoorkeywhichoptionallycanbeusedtogainaccesstosecurememoryresources. Duringresetevents,thecontentsofNVPROTandNVOPTinthenonvolatileregisterareaoftheFLASH memoryaretransferredintocorrespondingFPROTandFOPTworkingregistersinthehigh-pageregisters to control security and block protection options. Table4-4. Nonvolatile Register Summary Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0xFFB0 – NVBACKKEY 8-Byte Comparison Key 0xFFB7 0xFFB8 – Reserved — — — — — — — — 0xFFBC — — — — — — — — 0xFFBD NVPROT FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS 0xFFBE NVICGTRM1 NVTRIM 0xFFBF NVOPT KEYEN FNORED 0 0 0 0 SEC01 SEC00 1 NVICGTRM is the factory trim value. This value must be copied to ICGTRM in user code. Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengagememorysecurity.Thiskeymechanismcanbeaccessedonlythroughusercoderunninginsecure memory.(Asecuritykeycannotbeentereddirectlythroughbackgrounddebugcommands.)Thissecurity key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 47

Memory onlywaytodisengagesecurityisbymasserasingtheFLASHifneeded(normallythroughthebackground debuginterface)andverifyingthatFLASHisblank.Toavoidreturningtosecuremodeafterthenextreset, program the security bits (SEC01:SEC00) to the unsecured state (1:0). 4.3 RAM The MC9S08GT16A/GT8A includes static RAM. The locations in RAM below 0x0100 can be accessed usingthemoreefficientdirectaddressingmode,andanysinglebitinthisareacanbeaccessedwiththebit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after wakeupfromstop1,thecontentsofRAMareuninitialized.RAMdataisunaffectedbyanyresetprovided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08GT16A/GT8A, it is usually best to re-initialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.Includethefollowing2-instructionsequenceinyourresetinitializationroutine(whereRamLast is equated to the highest address of the RAM in the Freescale-provided equate file). LDHX #RamLast+1 ;point one past RAM TXS ;SP<-(H:X-1) Whensecurityisenabled,theRAMisconsideredasecurememoryresourceandisnotaccessiblethrough BDM or through code executing from non-secure memory. SeeSection4.5, “Security,” for a detailed description of the security feature. 4.4 FLASH The FLASH memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the FLASH memory after final assembly of the application product. Itispossibletoprogramtheentirearraythroughthesingle-wirebackgrounddebuginterface.Becauseno special voltages are needed for FLASH erase and programming operations, in-application programming isalsopossiblethroughothersoftware-controlledcommunicationpaths.Foramoredetaileddiscussionof in-circuit and in-application programming, refer to theHCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMV1/D. 4.4.1 Features Features of the FLASH memory include: • FLASH Size — MC9S08GT16A — 16384 bytes (32 pages of 512 bytes each) — MC9S08GT8A — 8192 bytes (16 pages of 512 bytes each) • Single power supply program and erase down to 1.8 V • Command interface for fast program and erase operation • Up to 100,000 program/erase cycles at typical voltage and temperature MC9S08GT16A/GT8A Data Sheet, Rev. 1 48 Freescale Semiconductor

Memory • Flexible block protection • Security feature for FLASH and RAM • Auto power-down for low-frequency read accesses 4.4.2 Program and Erase Times Beforeanyprogramorerasecommandcanbeaccepted,theFLASHclockdividerregister(FCDIV)must be written to set the internal clock for the FLASH module to a frequency (f ) between 150 kHz and FCLK 200kHz (seeTable 4.6.1). This register can be written only once, so normally this write is done during resetinitialization.FCDIVcannotbewritteniftheaccesserrorflag,FACCERRinFSTAT,isset.Theuser must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting clock (1/f ) is used by the command processor to time program and erase pulses. An integer number FCLK of these timing pulses is used by the command processor to complete a program or erase command. Table4-5showsprogramanderasetimes.ThebusclockfrequencyandFCDIVdeterminethefrequency ofFCLK(f ).ThetimeforonecycleofFCLKist = 1/f .Thetimesareshownasanumber FCLK FCLK FCLK of cycles of FCLK and as an absolute time for the case where t = 5µs. Program and erase times FCLK shownincludeoverheadforthecommandstatemachineandenablinganddisablingofprogramanderase voltages. Table4-5. Program and Erase Times Parameter Cycles of FCLK Time if FCLK=200kHz Byte program 9 45µs Byte program (burst) 4 20µs1 Page erase 4000 20ms Mass erase 20,000 100ms 1 Excluding start/end overhead 4.4.3 Program and Erase Command Execution Thestepsforexecutinganyofthecommandsarelistedbelow.TheFCDIVregistermustbeinitializedand any error flags cleared before beginning command execution. The command execution steps are: 1. Write a data value to an address in the FLASH array. The address and data information from this write is latched into the FLASH interface. This write is a required first step in any command sequence. For erase and blank check commands, the value of the data is not important. For page erasecommands,theaddressmaybeanyaddressinthe512-bytepageofFLASHtobeerased.For mass erase and blank check commands, the address can be any address in the FLASH memory. Whole pages of 512bytes are the smallest blocks of FLASH that may be erased. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 49

Memory NOTE Do not program any byte in the FLASH more than once after a successful erase operation. Reprogramming bits in a byte which is already programmedisnotallowedwithoutfirsterasingthepageinwhichthebyte resides or mass erasing the entire FLASH memory. Programming without first erasing may disturb data stored in the FLASH. 2. WritethecommandcodeforthedesiredcommandtoFCMD.Thefivevalidcommandsareblank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). The command code is latched into the command buffer. 3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its address and data information). Apartialcommandsequencecanbeabortedmanuallybywritinga0toFCBEFanytimeafterthewriteto the memory array and before writing the 1 that clears FCBEF and launches the complete command. Aborting a command in this way sets the FACCERR access error flag which must be cleared before starting a new command. Astrictlymonitoredproceduremustbeadheredto,orthecommandwillnotbeaccepted.Thisminimizes the possibility of any unintended change to the FLASH memory contents. The command complete flag (FCCF) indicates when a command is complete. The command sequence must be completed by clearing FCBEF to launch the command.Figure 4-2 is a flowchart for executing all of the commands except for burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset. MC9S08GT16A/GT8A Data Sheet, Rev. 1 50 Freescale Semiconductor

Memory WRITE TO FCDIV(Note 1) Note 1:Required only once after reset. START 0 FACCERR ? 1 CLEAR ERROR WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF Note 2:Wait at least four bus cycles TO LAUNCH COMMAND before checking FCBEF or FCCF. AND CLEAR FCBEF(Note 2) FPVIOL OR YES ERROR EXIT FACCERR ? NO 0 FCCF ? 1 DONE Figure4-2. FLASH Program and Erase Flowchart 4.4.4 Burst Program Execution The burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. This is possible because the high voltage to the FLASH array does not need to be disabled between program operations. Ordinarily, when a program or erase command is issued, an internal charge pump associated with the FLASH memory must be enabled to supplyhighvoltagetothearray.Uponcompletionofthecommand,thechargepumpisturnedoff.When aburstprogramcommandisissued,thechargepumpisenabledandthenremainsenabledaftercompletion of the burst program operation if the following two conditions are met: 1. The next burst program command has been queued before the current program operation has completed. 2. The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero. The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 51

Memory program time provided that the conditions above are met. In the case the next sequential address is the beginningofanewrow,theprogramtimeforthatbytewillbethestandardtimeinsteadofthebursttime. This is because the high voltage to the array must be disabled and then enabled again. If a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. WRITE TO FCDIV(Note 1) Note 1:Required only once after reset. START 0 FACCERR ? 1 CLEAR ERROR 0 FCBEF ? 1 WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND ($25) TO FCMD WRITE 1 TO FCBEF Note 2:Wait at least four bus cycles before TO LAUNCH COMMAND checking FCBEF or FCCF. AND CLEAR FCBEF(Note 2) FPVIO OR YES ERROR EXIT FACCERR ? NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE Figure4-3. FLASH Burst Program Flowchart MC9S08GT16A/GT8A Data Sheet, Rev. 1 52 Freescale Semiconductor

Memory 4.4.5 Access Errors An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERRmustbeclearedbywritinga1toFACCERRinFSTATbeforeanycommandcanbeprocessed. • Writing to a FLASH address before the internal FLASH clock frequency has been set by writing to the FCDIV register • WritingtoaFLASHaddresswhileFCBEFisnotset(Anewcommandcannotbestarteduntilthe command buffer is empty.) • WritingasecondtimetoaFLASHaddressbeforelaunchingthepreviouscommand(Thereisonly one write to FLASH for every command.) • WritingasecondtimetoFCMDbeforelaunchingthepreviouscommand(Thereisonlyonewrite to FCMD for every command.) • Writing to any FLASH control register other than FCMD after writing to a FLASH address • Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to FCMD • Accessing (read or write) any FLASH control register other than the write to FSTAT (to clear FCBEF and launch the command) after writing the command to FCMD • The MCU enters stop mode while a program or erase command is in progress (The command is aborted.) • Writingthebyteprogram,burstprogram,orpageerasecommandcode(0x20,0x25,or0x40)with a background debug command while the MCU is secured (The background debug controller can only do blank check and mass erase commands when the MCU is secure.) • Writing 0 to FCBEF to cancel a partial command 4.4.6 FLASH Block Protection The block protection feature prevents the protected region of FLASH from program or erase changes. Block protection is controlled through the FLASH Protection Register (FPROT). When enabled, block protection begins at any 512 byte boundary and continues through 0xFFFF. (seeSection4.6.4, “FLASH Protection Register (FPROT and NVPROT)”). After exit from reset, FPROT is loaded with the contents of the NVPROT location which is in the nonvolatile register block of the FLASH memory. FPROT cannot be changed directly from application softwaresoarunawayprogramcannotaltertheblockprotectionsettings.SinceNVPROTiswithinthelast 512 bytes of FLASH, if any amount of memory is protected, NVPROT is itself protected and cannot be altered (intentionally or unintentionally) by the application software. FPROT can be written through background debug commands which allows a way to erase and reprogram a protected FLASH memory. The block protection mechanism is illustrated below. The FPS bits are used as the upper bits of the last addressofunprotectedmemory.ThisaddressisformedbyconcatenatingFPS7:FPS1withlogic1bitsas shown. For example, in order to protect the last 8192 bytes of memory (addresses 0xE000 through 0xFFFF), the FPS bits must be set to 1101 111 which results in the value 0xDFFF as the last address of unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 53

Memory NVPROT)mustbeprogrammedtologic0toenableblockprotection.Thereforethevalue0xDEmustbe programmed into NVPROT to protect addresses 0xE000 through 0xFFFF. FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 1 1 1 1 1 1 1 1 1 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure4-4. Block Protection Mechanism OneuseforblockprotectionistoblockprotectanareaofFLASHmemoryforabootloaderprogram.This bootloader program then can be used to erase the rest of the FLASH memory and reprogram it. Because the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and reprogram operation. 4.4.7 Vector Redirection Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector redirectionallowsuserstomodifyinterruptvectorinformationwithoutunprotectingbootloaderandreset vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register locatedataddress0xFFBFtozero.Forredirectiontooccur,atleastsomeportionbutnotalloftheFLASH memorymustbeblockprotectedbyprogrammingtheNVPROTregisterlocatedataddress0xFFBD.All of the interrupt vectors (memory locations 0xFFC0–0xFFFD) are redirected, while the reset vector (0xFFFE:FFFF) is not. Forexample,if512bytesofFLASHareprotected,theprotectedaddressregionisfrom0xFE00through 0xFFFF.Theinterruptvectors(0xFFC0–0xFFFD)areredirectedtothelocations0xFDC0–0xFDFD.Now, ifanSPIinterruptistakenforinstance,thevaluesinthelocations0xFDE0:FDE1areusedforthevector instead of the values in the locations 0xFFE0:FFE1. This allows the user to reprogram the unprotected portion of the FLASH with new program code including new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged. 4.5 Security The MC9S08GT16A/GT8A includes circuitry to prevent unauthorized access to the contents of FLASH and RAM memory. When security is engaged, FLASH and RAM are considered secure resources. Direct-pageregisters,high-pageregisters,andthebackgrounddebugcontrollerareconsideredunsecured resources.ProgramsexecutingwithinsecurememoryhavenormalaccesstoanyMCUmemorylocations andresources.Attemptstoaccessasecurememorylocationwithaprogramexecutingfromanunsecured memoryspaceorthroughthebackgrounddebuginterfaceareblocked(writesareignoredandreadsreturn all 0s). Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in theFOPTregister.Duringreset,thecontentsofthenonvolatilelocationNVOPTarecopiedfromFLASH intotheworkingFOPTregisterinhigh-pageregisterspace.Auserengagessecuritybyprogrammingthe NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state disengages security while the other three combinations engage security. Notice the erased state (1:1) MC9S08GT16A/GT8A Data Sheet, Rev. 1 54 Freescale Semiconductor

Memory makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediatelyprogramtheSEC00bitto0inNVOPTsoSEC01:SEC00= 1:0.ThiswouldallowtheMCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug controller can still be used for background memory access commands, but the MCU cannot enter active background mode except by holding BKGD/MS low at the rising edge of reset. A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor securitykey.IfthenonvolatileKEYENbitinNVOPT/FOPTis0,thebackdoorkeyisdisabledandthere isnowaytodisengagesecuritywithoutcompletelyerasingallFLASHlocations.IfKEYENis1,asecure user program can temporarily disengage security by: 1. Writing1toKEYACCintheFCNFGregister.ThismakestheFLASHmoduleinterpretwritesto the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the first step in a FLASH program or erase command. 2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations. These writes must be done in order, starting with the value for NVBACKKEY and ending with NVBACKKEY+7.STHXshouldnotbeusedforthesewritesbecausethesewritescannotbedone on adjacent bus cycles. User software normally would get the key codes from outside the MCU system through a communication interface such as a serial I/O. 3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the key stored in the FLASH locations, SEC01:SEC00 are automatically changed to 1:0 and security will be disengaged until the next reset. The security key can be written only from RAM, so it cannot be entered through background commands without the cooperation of a secure user program. Thebackdoorcomparisonkey(NVBACKKEYthroughNVBACKKEY+7)islocatedinFLASHmemory locations in the nonvolatile register space so users can program these locations exactly as they would programanyotherFLASHmemorylocation.Thenonvolatileregistersareinthesame512-byteblockof FLASHastheresetandinterruptvectors,soblockprotectingthatspacealsoblockprotectsthebackdoor comparisonkey.Blockprotectscannotbechangedfromuserapplicationprograms,soifthevectorspace is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key. Security can always be disengaged through the background debug interface by performing these steps: 1. Disable any block protections by writing FPROT. FPROT can be written only with background debug commands, not from application software. 2. Mass erase FLASH, if necessary. 3. BlankcheckFLASH.ProvidedFLASHiscompletelyerased,securityisdisengageduntilthenext reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 =1:0. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 55

Memory 4.6 Register Definition TheFLASHmodulehasregistersinthehigh-pageregisterspace,threelocationsinthenonvolatileregister space in FLASH memory that are copied into three corresponding high-page control registers at reset. There is also an 8-byte comparison key in FLASH memory. Refer toTable 4-3 and Table4-4 for the absoluteaddressassignmentsforallFLASHregisters.Thissectionreferstoregistersandcontrolbitsonly bytheirnames.AFreescale-providedequateorheaderfilenormallyisusedtotranslatethesenamesinto the appropriate absolute addresses. 4.6.1 FLASH Clock Divider Register (FCDIV) Bit7ofthisregisterisaread-onlystatusflag.Bits6through0maybereadatanytimebutcanbewritten only one time. Before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. 7 6 5 4 3 2 1 0 R DIVLD PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure4-5. FLASH Clock Divider Register (FCDIV) Table4-6. FCDIV Field Descriptions Field Description 7 DivisorLoadedStatusFlag—Whenset,thisread-onlystatusflagindicatesthattheFCDIVregisterhasbeen DIVLD writtensincereset.Resetclearsthisbitandthefirstwritetothisregistercausesthisbittobecomesetregardless of the data written. 0 FCDIV has not been written since reset; erase and program operations disabled for FLASH. 1 FCDIV has been written since reset; erase and program operations enabled for FLASH. 6 Prescale (Divide) FLASH Clock by 8 PRDIV8 0 Clock input to the FLASH clock divider is the bus rate clock. 1 Clock input to the FLASH clock divider is the bus rate clock divided by8. 5 DivisorforFLASHClockDivider—TheFLASHclockdividerdividesthebusrateclock(orthebusrateclock DIV[5:0] divided by 8 if PRDIV8=1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the internal FLASH clock must fall within the range of 200kHz to 150kHz for proper FLASH operations. Program/erase timing pulses are one cycle of this internal FLASH clock, which corresponds to a range of 5µs to 6.7µs. The automated programming logic uses an integer number of these pulses to complete an erase or programoperation.SeeEquation4-1andEquation4-2.Table4-7showstheappropriatevaluesforPRDIV8and DIV5:DIV0 for selected bus frequencies. if PRDIV8=0 — f = f ÷ ([DIV5:DIV0] + 1) Eqn.4-1 FCLK Bus if PRDIV8=1 — f = f ÷ (8× ([DIV5:DIV0] + 1)) Eqn.4-2 FCLK Bus MC9S08GT16A/GT8A Data Sheet, Rev. 1 56 Freescale Semiconductor

Memory Table4-7. FLASH Clock Divider Settings PRDIV8 DIV5:DIV0 Program/Erase Timing Pulse f f Bus (Binary) (Decimal) FCLK (5µs Min, 6.7 µs Max) 20 MHz 1 12 192.3 kHz 5.2µs 10 MHz 0 49 200 kHz 5µs 8 MHz 0 39 200 kHz 5µs 4 MHz 0 19 200 kHz 5µs 2 MHz 0 9 200 kHz 5µs 1 MHz 0 4 200 kHz 5µs 200 kHz 0 0 200 kHz 5µs 150 kHz 0 0 150 kHz 6.7µs 4.6.2 FLASH Options Register (FOPT and NVOPT) Duringreset,thecontentsofthenonvolatilelocationNVOPTarecopiedfromFLASHintoFOPT.Bits5 through2arenotusedandalwaysread0.Thisregistermaybereadatanytime,butwriteshavenomeaning oreffect.Tochangethevalueinthisregister,eraseandreprogramtheNVOPTlocationinFLASHmemory as usual and then issue a new MCU reset. 7 6 5 4 3 2 1 0 R KEYEN FNORED 0 0 0 0 SEC01 SEC00 W Reset This register is loaded from nonvolatile location NVOPT during reset. = Unimplemented or Reserved Figure4-6. FLASH Options Register (FOPT) Table4-8. FOPT Field Descriptions Field Description 7 Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to KEYEN disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM commandscannotbeusedtowritekeycomparisonvaluesthatwouldunlockthebackdoorkey.Formoredetailed information about the backdoor key mechanism, refer toSection4.5, “Security.” 0 No backdoor key access allowed. 1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through NVBACKKEY+7, in that order), security is temporarily disengaged until the next MCU reset. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 57

Memory Table4-8. FOPT Field Descriptions (continued) Field Description 6 Vector Redirection Disable — When this bit is 1, vector redirection is disabled. FNORED 0 Vector redirection enabled. 1 Vector redirection disabled. 1:0 Security State Code — This 2-bit field determines the security state of the MCU as shown below. When the SEC0[1:0] MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecuredsourceincludingthebackgrounddebuginterface.Formoredetailedinformationaboutsecurity,refer toSection4.5, “Security.” 00 Secure 01 Secure 10 Unsecured 11 Secure SEC0[1:0] changes to 10 after successful backdoor key entry or a successful blank check of FLASH. 4.6.3 FLASH Configuration Register (FCNFG) Bits7through5maybereadorwrittenatanytime.Bits4through0alwaysread0andcannotbewritten. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 KEYACC W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure4-7. FLASH Configuration Register (FCNFG) Table4-9. FCNFG Field Descriptions Field Description 5 Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed KEYACC information about the backdoor key mechanism, refer toSection4.5, “Security.” 0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a FLASH programming or erase command. 1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes. Reads of the FLASH return invalid data. 4.6.4 FLASH Protection Register (FPROT and NVPROT) Duringreset,thecontentsofthenonvolatilelocationNVPROTarecopiedfromFLASHintoFPROT.This register may be read at any time, but user program writes have no meaning or effect. Background debug commands can write to FPROT. MC9S08GT16A/GT8A Data Sheet, Rev. 1 58 Freescale Semiconductor

Memory 7 6 5 4 3 2 1 0 R FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS W Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) Reset This register is loaded from nonvolatile location NVPROT during reset. Figure4-8. FLASH Protection Register (FPROT) 1 Background commands can be used to change the contents of these bits in FPROT. Table4-10. FPROT Field Descriptions Field Description 7:1 FLASHProtectSelectBits—WhenFPDIS=0,this7-bitfielddeterminestheendingaddressofunprotected FPS[7:1] FLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased or programmed. 0 FLASH Protection Disable FPDIS 0 FLASH block specified by FPS2:FPS0 is block protected (program and erase not allowed). 1 No FLASH block is protected. 4.6.5 FLASH Status Register (FSTAT) Bits3,1,and0alwaysread0andwriteshavenomeaningoreffect.Theremainingfivebitsarestatusbits that can be read at any time. Writes to these bits have special meanings that are discussed in the bit descriptions. 7 6 5 4 3 2 1 0 R FCCF 0 FBLANK 0 0 FCBEF FPVIOL FACCERR W Reset 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure4-9. FLASH Status Register (FSTAT) Table4-11. FSTAT Field Descriptions Field Description 7 FLASHCommandBufferEmptyFlag—TheFCBEFbitisusedtolaunchcommands.Italsoindicatesthatthe FCBEF command buffer is empty so that a new command sequence can be executed when performing burst programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. Only burst program commands can be buffered. 0 Command buffer is full (not ready for additional commands). 1 A new burst program command may be written to the command buffer. 6 FLASH Command Complete Flag — FCCF is set automatically when the command buffer is empty and no FCCF command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to register a command). Writing to FCCF has no meaning or effect. 0 Command in progress 1 All commands complete MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 59

Memory Table4-11. FSTAT Field Descriptions (continued) Field Description 5 Protection Violation Flag — FPVIOL is set automatically when FCBEF is cleared to register a command that FPVIOL attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing a 1 to FPVIOL. 0 No protection violation. 1 An attempt was made to erase or program a protected location. 4 Access Error Flag — FACCERR is set automatically when the proper command sequence is not followed FACCERR exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussionoftheexactactionsthatareconsideredaccesserrors,seeSection4.4.5,“AccessErrors.”FACCERR is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect. 0 No access error has occurred. 1 An access error has occurred. 2 FLASHVerifiedasAllBlank(Erased)Flag—FBLANKissetautomaticallyattheconclusionofablankcheck FBLANK commandiftheentireFLASHarraywasverifiedtobeerased.FBLANKisclearedbyclearingFCBEFtowritea new valid command. Writing to FBLANK has no meaning or effect. 0 After a blank check command is completed and FCCF=1, FBLANK=0 indicates the FLASH array is not completely erased. 1 After a blank check command is completed and FCCF=1, FBLANK=1 indicates the FLASH array is completely erased (all 0xFF). 4.6.6 FLASH Command Register (FCMD) Only five command codes are recognized in normal user modes as shown inTable4-13. Refer to Section4.4.3, “Program and Erase Command Execution” for a detailed discussion of FLASH programming and erase operations. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0 Reset 0 0 0 0 0 0 0 0 Figure4-10. FLASH Command Register (FCMD) Table4-12. FCMD Field Descriptions Field Description 7:0 FLASH Command Bits --SeeTable4-13 for a description of FCMD[7:0]. FCMD[7:0] MC9S08GT16A/GT8A Data Sheet, Rev. 1 60 Freescale Semiconductor

Memory Table4-13. FLASH Commands Command FCMD Equate File Label Blank check 0x05 mBlank Byte program 0x20 mByteProg Byte program — burst mode 0x25 mBurstProg Page erase (512 bytes/page) 0x40 mPageErase Mass erase (all FLASH) 0x41 mMassErase All other command codes are illegal and generate an access error. Itisnotnecessarytoperformablankcheckcommandafteramasseraseoperation.Blankcheckisrequired only as part of the security unlocking mechanism. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 61

Memory MC9S08GT16A/GT8A Data Sheet, Rev. 1 62 Freescale Semiconductor

Chapter 5 Resets, Interrupts, and System Configuration 5.1 Introduction Thissectiondiscussesbasicresetandinterruptmechanismsandthevarioussourcesofresetandinterrupts in the MC9S08GT16A/GT8A. Some interrupt sources from peripheral modules are discussed in greater detailwithinothersectionsofthisdatamanual.Thissectiongathersbasicinformationaboutallresetand interruptsourcesinoneplaceforeasyreference.Afewresetandinterruptsources,includingthecomputer operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral systems with their own sections but are part of the system control logic. 5.1.1 Features Reset and interrupt features include: • Multiple sources of reset for flexible system configuration and reliable operation: — Power-on detection (POR) — Low voltage detection (LVD) with enable — External RESET pin with enable — COP watchdog with enable and two timeout choices — Illegal opcode — Illegal address — Serial command from a background debug host • Reset status register (SRS) to indicate source of most recent reset • Separate interrupt vectors for each module (reduces polling overhead) (seeTable5-1) 5.2 MCU Reset ResettingtheMCUprovidesawaytostartprocessingfromaknownsetofinitialconditions.Duringreset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially configured as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the condition code register (CCR) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset. The MC9S08GT16A/GT8A has eight sources for reset: • Power-on reset (POR) • Low-voltage detect (LVD) MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 63

Resets, Interrupts, and System Configuration • Computer operating properly (COP) watchdog timer • Illegal opcode detect • Illegal address detect • Background debug forced reset • The reset pin (RESET) • Clock generator loss of lock and loss of clock reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in thesystemresetstatusregister.WhenevertheMCUentersreset,theinternalclockgenerator(ICG)module switchestoself-clockedmodewiththefrequencyoff selected.Theresetpinisdrivenlowfor34 Self_reset internal bus cycles where the internal bus frequency is half the ICG frequency. After the 34 cycles are completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low externally.Afterthepinisreleased,itissampledafteranother38cyclestodeterminewhethertheresetpin is the cause of the MCU reset. 5.3 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP timer periodically. If the application program gets lost and fails to reset the COP before it times out, a system reset is generated to force the system back to a known starting point. The COP watchdogisenabledbytheCOPEbitinSOPT(seeSection5.7.4,“SystemOptionsRegister(SOPT)”for additionalinformation).TheCOPtimerisresetbywritinganyvaluetotheaddressofSRS.Thiswritedoes notaffectthedataintheread-onlySRS.Instead,theactofwritingtothisaddressisdecodedandsendsa reset signal to the COP timer. Afteranyreset,theCOPtimerisenabled.Thisprovidesareliablewaytodetectcodethatisnotexecuting as intended. If the COP watchdog is not used in an application, it can be disabled by clearing the COPE bitinthewrite-onceSOPTregister.Also,theCOPTbitcanbeusedtochooseoneoftwotimeoutperiods (218or213cyclesofthebusrateclock).EveniftheapplicationwillusetheresetdefaultsettingsinCOPE andCOPT,theusershouldstillwritetowrite-onceSOPTduringresetinitializationtolockinthesettings. That way, they cannot be changed accidentally if the application program gets lost. ThewritetoSRSthatservices(clears)theCOPtimershouldnotbeplacedinaninterruptserviceroutine (ISR) because the ISR could continue to be executed periodically even if the main application program fails. When the MCU is in active background mode, the COP timer is temporarily disabled. 5.4 Interrupts InterruptsprovideawaytosavethecurrentCPUstatusandregisters,executeaninterruptserviceroutine (ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other thanthesoftwareinterrupt(SWI),whichisaprograminstruction,interruptsarecausedbyhardwareevents such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI under certain circumstances. MC9S08GT16A/GT8A Data Sheet, Rev. 1 64 Freescale Semiconductor

Resets, Interrupts, and System Configuration Ifaneventoccursinanenabledinterruptsource,anassociatedread-onlystatusflagwillbecomeset.The CPUwillnotresponduntilandunlessthelocalinterruptenableissetto1toenabletheinterrupt.TheIbit intheCCRis0toallowinterrupts.Theglobalinterruptmask(Ibit)intheCCRisinitiallysetafterreset, whichmasks(prevents)allmaskableinterruptsources.Theuserprograminitializesthestackpointerand performs other system setup before clearing the I bit to allow the CPU to respond to interrupts. WhentheCPUreceivesaqualifiedinterruptrequest,itcompletesthecurrentinstructionbeforeresponding totheinterrupt.Theinterruptsequencefollowsthesamecycle-by-cyclesequenceastheSWIinstruction and consists of: • Saving the CPU registers on the stack • Setting the I bit in the CCR to mask further interrupts • Fetching the interrupt vector for the highest-priority interrupt that is currently pending • Filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations WhiletheCPUisrespondingtotheinterrupt,theIbitisautomaticallysettoavoidthepossibilityofanother interruptinterruptingtheISRitself(thisiscallednestingofinterrupts).Normally,theIbitisrestoredto0 whentheCCRisrestoredfromthevaluestackedonentrytotheISR.Inrarecases,theIbitmaybecleared inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be servicedwithoutwaitingforthefirstserviceroutinetofinish.Thispracticeisnotrecommendedforanyone otherthanthemostexperiencedprogrammersbecauseitcanleadtosubtleprogramerrorsthataredifficult to debug. Theinterruptserviceroutineendswithareturn-from-interrupt(RTI)instructionwhichrestorestheCCR, A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the stack. NOTE For compatibility with the M68HC08, the H register is not automatically savedandrestored.ItisgoodprogrammingpracticetopushHontothestack atthestartoftheinterruptserviceroutine(ISR)andrestoreitjustbeforethe RTI that is used to return from the ISR. WhentwoormoreinterruptsarependingwhentheIbitiscleared,thehighestprioritysourceisserviced first (seeTable 5-1). 5.4.1 Interrupt Stack Frame Figure5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP)pointsatthenextavailablebytelocationonthestack.ThecurrentvaluesofCPUregistersarestored onthestackstartingwiththelow-orderbyteoftheprogramcounter(PCL)andendingwiththeCCR.After stacking,theSPpointsatthenextavailablelocationonthestackwhichistheaddressthatisonelessthan theaddresswheretheCCRwassaved.ThePCvaluethatisstackedistheaddressoftheinstructioninthe main program that would have executed next if the interrupt had not occurred. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 65

Resets, Interrupts, and System Configuration UNSTACKING TOWARD LOWER ADDRESSES ORDER 7 0 SP AFTER INTERRUPT STACKING 5 1 CONDITION CODE REGISTER 4 2 ACCUMULATOR 3 3 INDEX REGISTER (LOW BYTE X)* 2 4 PROGRAM COUNTER HIGH SP BEFORE 1 5 PROGRAM COUNTER LOW THE INTERRUPT STACKING TOWARD HIGHER ADDRESSES ORDER * High byte (H) of index register is not automatically stacked. Figure5-1. Interrupt Stack Frame WhenanRTIinstructionisexecuted,thesevaluesarerecoveredfromthestackinreverseorder.Aspartof the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information, starting from the PC address just recovered from the stack. The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR. Typically,theflagshouldbeclearedatthebeginningoftheISRsothatifanotherinterruptisgeneratedby this same source, it will be registered so it can be serviced after completion of the current ISR. 5.4.2 IRQ — External Interrupt Request Pin External interrupts are managed by the IRQSC status and control register. When the IRQ function is enabled,synchronouslogicmonitorsthepinforedge-onlyoredge-and-levelevents.WhentheMCUisin stopmodeandsystemclocksareshutdown,aseparateasynchronouspathisusedsotheIRQ(ifenabled) can wake the MCU. 5.4.2.1 Pin Configuration Options The IRQ pin enable (IRQPE) control bit in the IRQSC register must be 1 for the IRQ pin to act as the interruptrequest(IRQ)input.WhenthepinisconfiguredasanIRQinput,theusercanchoosethepolarity ofedgesorlevelsdetected(IRQEDG),whetherthepindetectsedges-onlyoredgesandlevels(IRQMOD), and whether an event causes an interrupt or only sets the IRQF flag (which can be polled by software). WhentheIRQpinisconfiguredtodetectrisingedges,anoptionalpulldownresistorisavailableratherthan apullupresistor.BIHandBILinstructionsmaybeusedtodetectthelevelontheIRQpinwhenthepinis configured to act as the IRQ input. NOTE The voltage measured on the pulled up IRQ pin may be as low as V – DD 0.7V.TheinternalgatesconnectedtothispinarepulledallthewaytoV . DD All other pins with enabled pullup resistors will have an unloaded measurement of V . DD MC9S08GT16A/GT8A Data Sheet, Rev. 1 66 Freescale Semiconductor

Resets, Interrupts, and System Configuration 5.4.2.2 Edge and Level Sensitivity TheIRQMODcontrolbitre-configuresthedetectionlogicsoitdetectsedgeeventsandpinlevels.Inthis edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin changesfromthedeassertedtotheassertedlevel),buttheflagiscontinuouslyset(andcannotbecleared) as long as the IRQ pin remains at the asserted level. 5.4.3 Interrupt Vectors, Sources, and Local Masks Table5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the bottom of the table. The high-order byte of the address for the interrupt service routine is located at the first address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address. When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 67

Resets, Interrupts, and System Configuration Table5-1. Vector Summary Vector Vector Address Vector Name Module Source Enable Description Priority Number (High/Low) 26 0xFFC0/FFC1 Unused Vector Space Lower through through (available for user program) 31 0xFFCA/FFCB 25 0xFFCC/FFCD Vrti System RTIF RTIE Real-time interrupt control 24 0xFFCE/FFCF Viic IIC IICIS IICIE IIC control 23 0xFFD0/FFD1 Vatd ATD COCO AIEN AD conversion complete 22 0xFFD2/FFD3 Vkeyboard KBI KBF KBIE Keyboard pins 21 0xFFD4/FFD5 Vsci2tx SCI2 TDRE TIE SCI2 transmit TC TCIE 20 0xFFD6/FFD7 Vsci2rx SCI2 IDLE ILIE SCI2 receive RDRF RIE 19 0xFFD8/FFD9 Vsci2err SCI2 OR ORIE SCI2 error NF NFIE FE FEIE PF PFIE 18 0xFFDA/FFDB Vsci1tx SCI1 TDRE TIE SCI1 transmit TC TCIE 17 0xFFDC/FFDD Vsci1rx SCI1 IDLE ILIE SCI1 receive RDRF RIE 16 0xFFDE/FFDF Vsci1err SCI1 OR ORIE SCI1 error NF NFIE FE FEIE PF PFIE 15 0xFFE0/FFE1 Vspi SPI SPIF SPIE SPI MODF SPIE SPTEF SPTIE 14 0xFFE2/FFE3 Vtpm2ovf TPM2 TOF TOIE TPM2 overflow 11 0xFFEC/FFED Unused Vector Space through through (available for user program) 13 0xFFE4/FFE5 10 0xFFEA/FFEB Vtpm2ch1 TPM2 CH1F CH1IE TPM2 channel 1 9 0xFFEC/FFED Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0 8 0xFFEE/FFEF Vtpm1ovf TPM1 TOF TOIE TPM1 overflow 7 0xFFF0/FFF1 Vtpm1ch2 TPM1 CH2F CH2IE TPM1 channel 2 6 0xFFF2/FFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1 5 0xFFF4/FFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0 4 0xFFF6/FFF7 Vicg ICG ICGIF LOLRE/LOCRE ICG (LOLS/LOCS) 3 0xFFF8/FFF9 Vlvd System LVDF LVDIE Low-voltage detect control 2 0xFFFA/FFFB Virq IRQ IRQF IRQIE IRQ pin 1 0xFFFC/FFFD Vswi Core SWI — Software interrupt Instruction 0 0xFFFE/FFFF Vreset System COP COPE Watchdog timer control LVD LVDRE Low-voltage detect Higher RESET pin — External pin Illegal opcode — Illegal opcode MC9S08GT16A/GT8A Data Sheet, Rev. 1 68 Freescale Semiconductor

Resets, Interrupts, and System Configuration 5.5 Low-Voltage Detect (LVD) System TheMC9S08GT16A/GT8Aincludesasystemtoprotectagainstlowvoltageconditionstoprotectmemory contents and control MCU system states during supply voltage variations. The system comprises a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (V ) LVDH orlow(V ).TheLVDcircuitisenabledwhenLVDEinSPMSC1ishighandthetripvoltageisselected LVDL byLVDVinSPMSC2.TheLVDisdisableduponenteringanyofthestopmodesunlesstheLVDSEbitis set. If LVDSE and LVDE are both set, then the MCU cannot enter stop1 or stop2, and the current consumption in stop3 with the LVD enabled will be greater. 5.5.1 Power-On Reset Operation WhenpowerisinitiallyappliedtotheMCU,orwhenthesupplyvoltagedropsbelowtheV level,the POR PORcircuitwillcausearesetcondition.Asthesupplyvoltagerises,theLVDcircuitwillholdthechipin reset until the supply has risen above the V level. Both the POR bit and the LVD bit in SRS are set LVDL following a POR. 5.5.2 LVD Reset Operation The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDREto1.AfteranLVDresethasoccurred,theLVDsystemwillholdtheMCUinresetuntilthesupply voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following either an LVD reset or POR. 5.5.3 LVD Interrupt Operation WhenalowvoltageconditionisdetectedandtheLVDcircuitisconfiguredforinterruptoperation(LVDE set, LVDIE set, and LVDRE clear), then LVDF will be set and an LVD interrupt will occur. 5.5.4 Low-Voltage Warning (LVW) The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is approaching, but is still above, the LVD voltage. The LVW does not have an interrupt associated with it. TherearetwouserselectabletripvoltagesfortheLVW,onehigh(V )andonelow(V ).Thetrip LVWH LVWL voltage is selected by LVWV in SPMSC2. 5.6 Real-Time Interrupt (RTI) The real-time interrupt function can be used to generate periodic interrupts based on a multiple of the sourceclock'speriod.TheRTIhastwosourceclockchoices,theexternalclockinput(ICGERCLK)tothe ICG or the RTI's own internal clock. The RTI can be used in run, wait, stop2 and stop3 modes. It is not available in stop1 mode. Inrunandwaitmodes,onlytheexternalclockcanbeusedastheRTI'sclocksource.Instop2mode,only the internal RTI clock can be used. In stop3, either the external clock or internal RTI clock can be used. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 69

Resets, Interrupts, and System Configuration When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and configured for low bandwidth operation (RANGE = 0). The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control value(RTIS2:RTIS1:RTIS0)usedtoselectoneofsevenRTIperiods.TheRTIhasalocalinterruptenable, RTIE, to allow masking of the real-time interrupt. The module can be disabled by writing 0:0:0 to RTIS2:RTIS1:RTIS0inwhichcasetheclocksourceinputisdisabledandnointerruptswillbegenerated. See Section5.7.6, “System Real-Time Interrupt Status and Control Register (SRTISC),” for detailed information about this register. 5.7 Register Definition One8-bitregisterinthedirectpageregisterspaceandeight8-bitregistersinthehigh-pageregisterspace are related to reset and interrupt systems. Refer to the direct-page register summary in Chapter4, “Memory” of this data sheet for the absolute addressassignmentsforallregisters.Thissectionreferstoregistersandcontrolbitsonlybytheirnames. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter3, “Modes of Operation.” MC9S08GT16A/GT8A Data Sheet, Rev. 1 70 Freescale Semiconductor

Resets, Interrupts, and System Configuration 5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) This direct page register includes two unimplemented bits which always read 0, four read/write bits, one read-onlystatusbit,andonewrite-onlybit.ThesebitsareusedtoconfiguretheIRQfunction,reportstatus, and acknowledge IRQ events. 7 6 5 4 3 2 1 0 R 0 0 IRQF 0 IRQEDG IRQPE IRQIE IRQMOD W IRQACK Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure5-2. Interrupt Request Status and Control Register (IRQSC) Table5-2. IRQSC Field Descriptions Field Description 5 Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or IRQEDG levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is sensitivetobothedgesandlevelsoronlyedges.WhentheIRQpinisenabledastheIRQinputandisconfigured to detect rising edges, the optional pullup resistor is re-configured as an optional pulldown resistor. 0 IRQ is falling edge or falling edge/low-level sensitive. 1 IRQ is rising edge or rising edge/high-level sensitive. 4 IRQPinEnable—Thisread/writecontrolbitenablestheIRQpinfunction.Whenthisbitisset,theIRQpincan IRQPE be used as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down resistor is enabled depending on the state of the IRQMOD bit. 0 IRQ pin function is disabled. 1 IRQ pin function is enabled. 3 IRQ Flag —This read-only status bit indicates when an interrupt request event has occurred. IRQF 0 No IRQ request. 1 IRQ event detected. 2 IRQAcknowledge—Thiswrite-onlybitisusedtoacknowledgeinterruptrequestevents(write1toclearIRQF). IRQACK Writing0hasnomeaningoreffect.Readsalwaysreturn0.Ifedge-and-leveldetectionisselected(IRQMOD=1), IRQF cannot be cleared while the IRQ pin remains at its asserted level. 1 IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate a hardware IRQIE interrupt request. 0 Hardware interrupt requests from IRQF disabled (use polling). 1 Hardware interrupt requested whenever IRQF=1. 0 IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level IRQMOD detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. SeeSection5.4.2.2, “Edge and Level Sensitivity” for more details. 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 71

Resets, Interrupts, and System Configuration 5.7.2 System Reset Status Register (SRS) This register includes six read-only status flags to indicate the source of the most recent reset. When a debughostforcesresetbywriting1toBDFRintheSBDFRregister,noneofthestatusbitsinSRSwillbe set.WritinganyvaluetothisregisteraddressclearstheCOPwatchdogtimerwithoutaffectingthecontents of this register. The reset state of these bits depends on what caused the MCU to reset. 7 6 5 4 3 2 1 0 R POR PIN COP ILOP ILAD ICG LVD 0 W Writing any value to SIMRS address clears COP watchdog timer. Power-on 1 0 0 0 0 0 1 0 reset: Low-voltage U 0 0 0 0 0 1 0 reset: Any other 0 Note (1) Note(1) Note(1) 0 Note(1) 0 0 reset: U = Unaffected by reset 1 Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset will be cleared. Figure5-3. System Reset Status (SRS) Table5-3. SRS Field Descriptions Field Description 7 Power-OnReset—Resetwascausedbythepower-ondetectionlogic.Becausetheinternalsupplyvoltagewas POR rampingupatthetime,thelow-voltagereset(LVD)statusbitisalsosettoindicatethattheresetoccurredwhile the internal supply was below the LVD threshold. 0 Reset not caused by POR. 1 POR caused reset. 6 External Reset Pin — Reset was caused by an active-low level on the external reset pin. PIN 0 Reset not caused by external reset pin. 1 Reset came from external reset pin. 5 ComputerOperatingProperly(COP)Watchdog—ResetwascausedbytheCOPwatchdogtimertimingout. COP This reset source may be blocked by COPE=0. 0 Reset not caused by COP timeout. 1 Reset caused by COP timeout. 4 IllegalOpcode—Resetwascausedbyanattempttoexecuteanunimplementedorillegalopcode.TheSTOP ILOP instructionisconsideredillegalifstopisdisabledbySTOPE=0intheSOPTregister.TheBGNDinstructionis considered illegal if active background mode is disabled by ENBDM=0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode. MC9S08GT16A/GT8A Data Sheet, Rev. 1 72 Freescale Semiconductor

Resets, Interrupts, and System Configuration Table5-3. SRS Field Descriptions (continued) Field Description 3 Illegal Address— Reset was caused by an attempt to access a designated illegal address. ILAD 0 Reset not caused by an illegal address access. 1 Reset caused by an illegal address access. Illegal address areas in the MC9S08GT16A are: • 0x0880 - 0x17FF— Gap from end of RAM to start of high page registers • 0x182C - 0xBFFF — Gap from end of high page registers to start of Flash memory Unused and reserved locations in register areas are not considered designated illegaladdresses and do not triggerillegal address resets. 2 Internal Clock Generation Module Reset — Reset was caused by an ICG module reset. ICG 0 Reset not caused by ICG module. 1 Reset caused by ICG module. 1 LowVoltageDetect—IftheLVDresetisenabled(LVDE=LVDRE=1)andthesupplydropsbelowtheLVDtrip LVD voltage,anLVDresetoccurs.TheLVDfunctionisdisabledwhentheMCUentersstop.TomaintainLVDoperation in stop, the LVDSE bit must be set. 0 Reset not caused by LVD trip or POR. 1 Reset caused by LVD trip or POR. 5.7.3 System Background Debug Force Reset Register (SBDFR) This register contains a single write-only control bit. A serial background command such as WRITE_BYTEmustbeusedtowritetoSBDFR.Attemptstowritethisregisterfromauserprogramare ignored. Reads always return 0x00. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W BDFR Note (1) Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background debug commands, not from user programs. Figure5-4. System Background Debug Force Reset Register (SBDFR) Table5-4. SBDFR Field Descriptions Field Description 0 Background Debug Force Reset — A serial background mode command such as WRITE_BYTE allows an BDFR external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 73

Resets, Interrupts, and System Configuration 5.7.4 System Options Register (SOPT) This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a write-onceregistersoonlythefirstwriteafterresetishonored.AnysubsequentattempttowritetoSOPT (intentionallyorunintentionally)isignoredtoavoidaccidentalchangestothesesensitivesettings.SOPT shouldbewrittenduringtheuser’sresetinitializationprogramtosetthedesiredcontrolsevenifthedesired settings are the same as the reset settings. 7 6 5 4 3 2 1 0 R 0 0 COPE COPT STOPE BKGDPE W Reset 1 1 0 1 0 0 1 1 = Unimplemented or Reserved Figure5-5. System Options Register (SOPT) Table5-5. SOPT Field Descriptions Field Description 7 COP Watchdog Enable — This write-once bit defaults to 1 after reset. COPE 0 COP watchdog timer disabled. 1 COP watchdog timer enabled (force reset on timeout). 6 COP Watchdog Timeout — This write-once bit defaults to 1 after reset. COPT 0 Short timeout period selected (213 cycles of BUSCLK). 1 Long timeout period selected (218 cycles of BUSCLK). 5 Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is STOPE disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced. 0 Stop mode disabled. 1 Stop mode enabled. 1 Background Debug Mode Pin Enable — The BKGDPE bit enables the PTG0/BKGD/MS pin to function as BKGDPE BKGD/MS.Whenthebitisclear,thepinwillfunctionasPTG0,whichisanoutput-onlygeneral-purposeI/O.This pin always defaults to BKGD/MS function after any reset. 0 BKGD pin disabled. 1 BKGD pin enabled. MC9S08GT16A/GT8A Data Sheet, Rev. 1 74 Freescale Semiconductor

Resets, Interrupts, and System Configuration 5.7.5 System Device Identification Register (SDIDH, SDIDL) This read-only register is included so host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU. 7 6 5 4 3 2 1 0 R ID11 ID10 ID9 ID8 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure5-6. System Device Identification Register High (SDIDH) Table5-6. SDIDH Field Descriptions Field Description 3:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[11:8] MC9S08GT16A/GT8A is hard coded to the value 0x00D. See also ID bits inTable5-7. 7 6 5 4 3 2 1 0 R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 W Reset 0 0 0 0 1 1 0 1 = Unimplemented or Reserved Figure5-7. System Device Identification Register Low (SDIDL) Table5-7. SDIDL Field Descriptions Field Description 7:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08GT16A/GT8A is hard coded to the value 0x00D. See also ID bits inTable5-6. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 75

Resets, Interrupts, and System Configuration 5.7.6 System Real-Time Interrupt Status and Control Register (SRTISC) This register contains one read-only status flag, one write-only acknowledge bit, three read/write delay selects, and three unimplemented bits, which always read 0. 7 6 5 4 3 2 1 0 R RTIF 0 0 RTICLKS RTIE RTIS2 RTIS1 RTIS0 W RTIACK Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure5-8. System RTI Status and Control Register (SRTISC) Table5-8. SRTISC Field Descriptions Field Description 7 Real-Time Interrupt Flag — This read-only status bit indicates the periodic wakeup timer has timed out. RTIF 0 Periodic wakeup timer not timed out. 1 Periodic wakeup timer timed out. 6 Real-Time Interrupt Acknowledge — This write-only bit is used to acknowledge real-time interrupt request RTIACK (write 1 to clear RTIF). Writing 0 has no meaning or effect. Reads always return 0. 5 Real-Time Interrupt Clock Select — This read/write bit selects the clock source for the real-time interrupt. RTICLKS 0 Real-time interrupt request clock source is internal oscillator. 1 Real-time interrupt request clock source is external clock. 4 Real-Time Interrupt Enable — This read-write bit enables real-time interrupts. RTIE 0 Real-time interrupts disabled. 1 Real-time interrupts enabled. 2:0 Real-Time Interrupt Period Selects — These read/write bits select the wakeup period for the RTI. One clock RTIS[2:0] sourceforthereal-timeinterruptisitsowninternalclocksource,whichoscillateswithaperiodofapproximately t and is independent of other MCU clock sources. Using an external clock source the delays will be crystal RTI frequency divided by value in RTIS2:RTIS1:RTIS0. SeeTable5-9. Table5-9. Real-Time Interrupt Period Internal Clock Source1 External Clock Source2 RTIS2:RTIS1:RTIS0 (t = 1.15 ms, Nominal) Period = t RTI ext 0:0:0 9.2 ms Disable periodic wakeup timer 0:0:1 18.4 ms text x 256 0:1:0 36.8 ms tex x 1024 0:1:1 73.6 ms tex x 2048 1:0:0 147.2 ms tex x 4096 1:0:1 294.4 ms text x 8192 1:1:0 588.8 ms text x 16384 1:1:1 1177.6 ms tex x 32768 1 SeeTableA-12 t inAppendixA, “Electrical Characteristics,” for the tolerance on these values. RTI 2 t is based on the external clock source, resonator, or crystal selected by the ICG configuration. SeeTableA-11 for details. ext MC9S08GT16A/GT8A Data Sheet, Rev. 1 76 Freescale Semiconductor

Resets, Interrupts, and System Configuration 5.7.7 System Power Management Status and Control 1 Register (SPMSC1) 7 6 5 4 3 2 1 0 R LVDF 0 0 0 LVDRE LVDSE LVDE LVDIE Note (1) Note(1) Note(1) W LVDACK Reset 0 0 0 1 1 1 0 0 = Unimplemented or Reserved 1 This bit can be written only one time after reset. Additional writes are ignored. Figure5-9. System Power Management Status and Control 1 Register (SPMSC1) Table5-10. SPMSC1 Field Descriptions Field Description 7 Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event. LVDF 6 Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors LVDACK (write 1 to clear LVDF). Reads always return 0. 5 Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF. LVDIE 0 Hardware interrupt disabled (use polling). 1 Request a hardware interrupt when LVDF = 1. 4 Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset LVDRE (provided LVDE = 1). 0 LVDF does not generate hardware resets. 1 Force an MCU reset when LVDF = 1. 3 Low-VoltageDetectStopEnable—ProvidedLVDE=1,thisread/writebitdetermineswhetherthelow-voltage LVDSE detect function operates when the MCU is in stop mode. 0 Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode. 2 Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation LVDE of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 77

Resets, Interrupts, and System Configuration 5.7.8 System Power Management Status and Control 2 Register (SPMSC2) Thisregisterisusedtoreportthestatusofthelowvoltagewarningfunction,andtoconfigurethestopmode behavior of the MCU. 7 6 5 4 3 2 1 0 R LVWF 0 PPDF 0 LVDV LVWV PDC PPDC W LVWACK PPDACK Power-on 0 0 0 0 0 0 0 0 reset: Note (1) LVD reset: 0 0 U U 0 0 0 0 Note(1) Any other 0 0 U U 0 0 0 0 reset: Note(1) = Unimplemented or Reserved U = Unaffected by reset 1 LVWF will be set in the case when V transitions below the trip point or after reset and V is already below V . Supply Supply LVW Figure5-10. System Power Management Status and Control 2 Register (SPMSC2) Table5-11. SPMSC2 Field Descriptions Field Description 7 Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status. LVWF 0 Low voltage warningnot present. 1 Low voltage warning is present or was present. 6 Low-VoltageWarningAcknowledge—TheLVWACKbitisthelow-voltagewarningacknowledge.Writinga1 LVWACK to LVWACK clears LVWF to 0 if a low voltage warning is not present. 5 Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V ). LVD LVDV 0 Low trip point selected (V = V ). LVD LVDL 1 High trip point selected (V = V ). LVD LVDH 4 Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V ). LVW LVWV 0 Low trip point selected (V = V ). LVW LVWL 1 High trip point selected (V = V ). LVW LVWH 3 Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode. PPDF 0 Not stop2 mode recovery. 1 Stop2 mode recovery. 2 Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit. PPDACK 1 Power Down Control — The write-once PDC bit controls entry into the power down (stop2 and stop1) modes. PDC 0 Power down modes are disabled. 1 Power down modes are enabled. 0 PartialPowerDownControl—Thewrite-oncePPDCbitcontrolswhichpowerdownmode,stop1orstop2,is PPDC selected. 0 Stop1, full power down, mode enabled if PDC set. 1 Stop2, partial power down, mode enabled if PDC set. MC9S08GT16A/GT8A Data Sheet, Rev. 1 78 Freescale Semiconductor

Chapter 6 Parallel Input/Output 6.1 Introduction Thissectionexplainssoftwarecontrolsrelatedtoparallelinput/output(I/O).TheMC9S08GT16A/GT8A hassixI/Oportswhichincludeatotalofupto39general-purposeI/Opins(onepin,PTG0,isoutputonly). SeeChapter2,“PinsandConnections,”formoreinformationaboutthelogicandhardwareaspectsofthese pins. Many of these pins are shared with on-chip peripherals such as timer systems, external interrupts, or keyboard interrupts. When these other modules are not controlling the port pins, they revert to general-purpose I/O control. For each I/O pin, a port data bit provides access to input (read) and output (write)data,adatadirectionbitcontrolsthedirectionofthepin,andapullupenablebitenablesaninternal pullupdevice(providedthepinisconfiguredasaninput),andaslewratecontrolbitcontrolstheriseand fall times of the pins. Pinsthatarenotusedintheapplicationmustbeterminated.Thispreventsexcesscurrentcausedbyfloating inputs and enhances immunity during noise or transient events. Termination methods include: • Configuring unused pins as outputs driving high or low • Configuring unused pins as inputs and using internal or external pullups Never connect unused pins to V or V . DD SS NOTE Not all general-purpose I/O pins are available on all packages. To avoid extra current drain from floating input pins, the user’s reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unconnected pins to outputs so the pins do not float. 6.1.1 Features Parallel I/O features, depending on package choice, include: • A total of 39 general-purpose I/O pins in six ports (PTG0 is output only) • High-current drivers on port C pins • Hysteresis input buffers • Software-controlled pullups on each input pin • Software-controlled slew rate output buffers • Eight port A pins shared with KBI MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 79

Parallel Input/Output • Eight port B pins shared with ATD • Eight high-current port C pins shared with SCI2 and IIC • Five port D pins shared with TPM1 and TPM2 • Six port E pins shared with SCI1 and SPI • Four port G pins shared with EXTAL, XTAL, and BKGD/MS MC9S08GT16A/GT8A Data Sheet, Rev. 1 80 Freescale Semiconductor

Parallel Input/Output 6.1.2 Block Diagram VREFLVREFHVSSADVDDAD 4 HCS08 CORE BKGD 8IN-BTIETR KREUYPBTO (AKRBDI) 8 PORT A 4 PPPTTTAAA347///KKKBBBIIIPPP347–– NOTE 6 PTA0/KBIP0 CPU BDC 4 10-BIT 8 T B PPTTBB74//AADDPP74– ANALOG-TO-DIGITAL OR 4 HCS08 SYSTEM CONTROL CONVERTER (ATD) P PTB3/ADP3– RESET PTB0/ADP0 NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION PTC7 POWER MANAGEMENT PTC6 PTC5 RTI COP INTER-IC (IIC) SSDCAL PORT C PPPTTTCCC432//SSCDAL NOTE 5 IRQ IRQ LVD RXD2 NOTES 2, 3 SERIAL COMMUNICATIONS PTC1/RxD2 TXD2 INTERFACE (SCI2) PTC0/TxD2 CH1 USER FLASH 2-CHANNEL TIMER/PWM PTD4/TPM2CH1 CH0 (GT16A = 16,384 BYTES) (TPM2) PTD3/TPM2CLK/TPM2CH0 (GT8A = 8192 BYTES) D CH0 RT O PTD2/TPM1CH2 3-CHANNEL TIMER/PWM CH1 P PTD1/TPM1CH1 (TPM1) CH2 PTD0/TPM1CLK/TPM1CH0 USER RAM (GT16A = 2048 BYTES) SPSCK (GT8A = 1024 BYTES) PTE5/SPSCK MOSI SERIAL PERIPHERAL PTE4/MOSI MISO ON-CHIP ICE INTERFACE (SPI) SS RT E PPTTEE32//SMSISO DEBUG O RXD1 P MODULE (DBG) SERIAL COMMUNICATIONS PTE1/RxD1 TXD1 INTERFACE (SCI1) PTE0/TxD1 INTERNAL CLOCK GENERATOR (ICG) PTG3 EXTAL G PTG2/EXTAL XTAL T LOW-POWER OSCILLATOR R PTG1/XTAL BKGD O P PTG0/BKGD/MS V DD VOLTAGE V SS REGULATOR = Pins not available in 44-, 42-, or 32-pin packages V SS = Pins not available in 42- or 32-pin packages = Pins not available in 32-pin packages NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE=1). 3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD. 4. Pin contains integrated pullup device. 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1). Figure6-1. Block Diagram Highlighting Parallel Input/Output Pins MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 81

Parallel Input/Output 6.2 External Signal Description The MC9S08GT16A/GT8A has a total of 39 parallel I/O pins (one is output only) in six 8-bit ports (PTA–PTE, PTG). Not all pins are bonded out in all packages. Consult the pin assignment inChapter 2, “PinsandConnections,”foravailableparallelI/Opins.Allofthesepinsareavailableforgeneral-purpose I/O when they are not used by other on-chip peripheral systems. Afterreset,BKGD/MSisenabledandthereforeisnotusableasanoutputpinuntilBKGDPEinSOPTis cleared.Therestoftheperipheralfunctionsaredisabled.Afterreset,alldatadirectionandpullupenable controls are set to 0s. These pins default to being high-impedance inputs with on-chip pullup devices disabled. The following paragraphs discuss each port and the software controls that determine each pin’s use. 6.2.1 Port A and Keyboard Interrupts Port A Bit 7 6 5 4 3 2 1 Bit 0 PTA7/ PTA6/ PTA5/ PTA4/ PTA3/ PTA2/ PTA1/ PTA0/ MCU Pin: KBIP7 KBIP6 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0 Figure6-2. Port A Pin Names PortAisan8-bitportsharedamongtheKBIkeyboardinterruptinputsandgeneral-purposeI/O.Anypins enabled as KBI inputs will be forced to act as inputs. PortApinsareavailableasgeneral-purposeI/OpinscontrolledbytheportAdata(PTAD),datadirection (PTADD),pullupenable(PTAPE),andslewratecontrol(PTASE)registers.RefertoSection6.3,“Parallel I/O Controls,” for more information about general-purpose I/O control. Port A can be configured to be keyboard interrupt input pins. Refer toChapter 7, “Keyboard Interrupt (S08KBIV1),” for more information about using port A pins as keyboard interrupts pins. 6.2.2 Port B and Analog to Digital Converter Inputs j Port B Bit 7 6 5 4 3 2 1 Bit 0 PTB7/ PTB6/ PTB5/ PTB4/ PTB3/ PTB2/ PTB1/ PTB0/ MCU Pin: ADP7 ADP6 ADP5 ADP4 ADP3 ADP2 ADP1 ADP0 Figure6-3. Port B Pin Names PortBisan8-bitportsharedamongtheATDinputsandgeneral-purposeI/O.AnypinenabledasanATD input will be forced to act as an input. PortBpinsareavailableasgeneral-purposeI/OpinscontrolledbytheportBdata(PTBD),datadirection (PTBDD),pullupenable(PTBPE),andslewratecontrol(PTBSE)registers.RefertoSection6.3,“Parallel I/O Controls,” for more information about general-purpose I/O control. WhentheATDmoduleisenabled,analogpinenablesareusedtospecifywhichpinsonportBwillbeused as ATD inputs. Refer toChapter14, “Analog-to-Digital Converter (S08ATDV3),” for more information about using port B pins as ATD pins. MC9S08GT16A/GT8A Data Sheet, Rev. 1 82 Freescale Semiconductor

Parallel Input/Output 6.2.3 Port C and SCI2, IIC, and High-Current Drivers Port C Bit 7 6 5 3 3 2 1 Bit 0 PTC7 PTC6 PTC5 PTC4 PTC3/ PTC2/ PTC1/ PTC0/ MCU Pin: SCL SDA RxD2 TxD2 Figure6-4. Port C Pin Names PortCisan8-bitportwhichissharedamongtheSCI2andIICmodules,andgeneral-purposeI/O.When SCI2 or IIC modules are enabled, the pin direction will be controlled by the module or function. Port C has high current output drivers. PortCpinsareavailableasgeneral-purposeI/OpinscontrolledbytheportCdata(PTCD),datadirection (PTCDD),pullupenable(PTCPE),andslewratecontrol(PTCSE)registers.RefertoSection6.3,“Parallel I/O Controls,” for more information about general-purpose I/O control. When the SCI2 module is enabled, PTC0 serves as the SCI2 module’s transmit pin (TxD2) and PTC1 serves as the receive pin (RxD2). Refer to Chapter11, “Serial Communications Interface (S08SCIV1),” for more information about using PTC0 and PTC1 as SCI pins WhentheIICmoduleisenabled,PTC2servesastheIICmodules’sserialdatainput/outputpin(SDA)and PTC3servesastheclockpin(SCL).RefertoChapter13,“Inter-IntegratedCircuit(S08IICV1),”formore information about using PTC2 and PTC3 as IIC pins. 6.2.4 Port D, TPM1 and TPM2 Port D Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 PTD4/ PTD3/ PTD2/ PTD1/ PTD0/ MCU Pin: TPM2CH1 TPM2CLK/ TPM1CH2 TPM1CH1 TPM1CLK/ TPM2CH0 TPM1CH0 Figure6-5. Port D Pin Names Port D is an 5-bit port shared with the two TPM modules, TPM1 and TPM2, and general-purpose I/O. When the TPM1 or TPM2 modules are enabled in output compare or input capture modes of operation, the pin direction will be controlled by the module function. PortDpinsareavailableasgeneral-purposeI/OpinscontrolledbytheportDdata(PTDD),datadirection (PTDDD),pullupenable(PTDPE),andslewratecontrol(PTDSE)registers.RefertoSection6.3,“Parallel I/O Controls,” for more information about general-purpose I/O control. TheTPM2modulecanbeconfiguredtousePTD4–PTD3aseitherinputcapture,outputcompare,PWM, or external clock input pins (PTD3 only). Refer to Chapter10, “Timer/PWM (S08TPMV2),” for more information about using PTD4–PTD3 as timer pins. TheTPM1modulecanbeconfiguredtousePTD2–PTD0aseitherinputcapture,outputcompare,PWM, or external clock input pins (PTD0 only). Refer to Chapter10, “Timer/PWM (S08TPMV2),” for more information about using PTD2–PTD0 as timer pins. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 83

Parallel Input/Output 6.2.5 Port E, SCI1, and SPI Port E Bit 7 6 5 4 3 2 1 Bit 0 0 0 PTE5/ PTE4/ PTE3/ PTE2/ PTE1/ PTE0/ MCU Pin: SPSCK MOSI MISO SS RxD1 TxD1 Figure6-6. Port E Pin Names PortEisan6-bitportsharedwiththeSCI1module,SPI1module,andgeneral-purposeI/O.WhentheSCI or SPI modules are enabled, the pin direction will be controlled by the module function. PortEpinsareavailableasgeneral-purposeI/OpinscontrolledbytheportEdata(PTED),datadirection (PTEDD),pullupenable(PTEPE),andslewratecontrol(PTESE)registers.RefertoSection6.3,“Parallel I/O Controls” for more information about general-purpose I/O control. When the SCI1 module is enabled, PTE0 serves as the SCI1 module’s transmit pin (TxD1) and PTE1 servesasthereceivepin(RxD1).RefertoChapter11,“SerialCommunicationsInterface(S08SCIV1)”for more information about using PTE0 and PTE1 as SCI pins. WhentheSPImoduleisenabled,PTE2servesastheSPImodule’sslaveselectpin(SS1),PTE3servesas the master-in slave-out pin (MISO1), PTE4 serves as the master-out slave-in pin (MOSI1), and PTE5 serves as the SPI clock pin (SPSCK1). Refer to Chapter12, “Serial Peripheral Interface (S08SPIV3) for more information about using PTE5–PTE2 as SPI pins. 6.2.6 Port G, BKGD/MS, and Oscillator Port G Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 PTG3 PTG2/ PTG1/ PTG0/ MCU Pin: EXTAL XTAL BKGD/MS Figure6-7. Port G Pin Names Port G is an 4-bit port which is shared among the background/mode select function, oscillator, and general-purposeI/O.Whenthebackground/modeselectfunctionoroscillatorisenabled,thepindirection will be controlled by the module function. PortGpinsareavailableasgeneral-purposeI/OpinscontrolledbytheportGdata(PTGD),datadirection (PTGDD),pullupenable(PTGPE),andslewratecontrol(PTGSE)registers.RefertoSection6.3,“Parallel I/O Controls,” for more information about general-purpose I/O control. TheinternalpullupforPTG0isenabledwhenthebackground/modeselectfunctionisenabled,regardless of the state of PTGPE0. During reset, the BKGD/MS pin functions as a mode select pin. After the MCU exitsreset,theBKGD/MSpinbecomesthebackgroundcommunicationsinput/outputpin.ThePTG0can be configured to be a general-purpose output pin. Refer toSection5.7.4, “System Options Register (SOPT),” for selecting BKGD or PTG0. Refer to Chapter3, “Modes of Operation,”, Chapter5, “Resets, Interrupts, and System Configuration,” and Chapter15, “Development Support,” for more information about using this pin. The ICG module can be configured to use PTG2–PTG1 ports as crystal oscillator or external clock pins. MC9S08GT16A/GT8A Data Sheet, Rev. 1 84 Freescale Semiconductor

Parallel Input/Output RefertoChapter9,“InternalClockGenerator(S08ICGV4),”formoreinformationaboutusingthesepins as oscillator pins. 6.3 Parallel I/O Controls Providednoon-chipperipheraliscontrollingaportpin,thepinsoperateasgeneral-purposeI/Opinsthat areaccessedandcontrolledbyadataregister(PTxD),adatadirectionregister(PTxDD),apullupenable register (PTxPE), and a slew rate control register (PTxSE) where x is A, B, C, D, E, or G. Readsofthedataregisterreturnthepinvalue(ifPTxDDn= 0)orthecontentsoftheportdataregister(if PTxDDn= 1).Writestotheportdataregisterarelatchedintotheportregisterwhetherthepiniscontrolled byanon-chipperipheralorthepinisconfiguredasaninput.Ifthecorrespondingpinisnotcontrolledby a peripheral and is configured as an output, this level will be driven out the port pin. 6.3.1 Data Direction Control The data direction control bits determine whether the pin output driver is enabled, and they control what is read for port data register reads. Each port pin has a data direction control bit. When PTxDDn = 0, the corresponding pin is an input and reads of PTxD return the pin value. When PTxDDn = 1, the corresponding pin is an output and reads of PTxD return the last value written to the port data register. When a peripheral module or system function is in control of a port pin, the data direction control still controls what is returned for reads of the port data register, even though the peripheral system has overriding control of the actual pin direction. For the MC9S08GT16A/GT8A MCU, reads of PTG0/BKGD/MS will return the value on the output pin. Itisagoodprogrammingpracticetowritetotheportdataregisterbeforechangingthedirectionofaport pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. 6.3.2 Internal Pullup Control An internal pullup device can be enabled for each port pin that is configured as an input (PTxDDn =0). Thepullupdeviceisavailableforaperipheralmoduletouse,providedtheperipheralisenabledandisan input function as long as the PTxDDn = 0. For the four configurable KBI module inputs on PTA7–PTA4, when a pin is configured to detect rising edges, the port pullup enable associated with the pin (PTAPEn) selects a pulldown rather than a pullup device. 6.3.3 Slew Rate Control Slew rate control can be enabled for each port pin that is configured as an output (PTxDDn= 1) or if a peripheralmoduleisenabledanditsfunctionisanoutput.Notallperipheralmodules’outputshaveslew ratecontrol;refertoChapter2,“PinsandConnections,”formoreinformationaboutwhichpinshaveslew rate control. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 85

Parallel Input/Output 6.4 Stop Modes Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An explanation of I/O behavior for the various stop modes follows: • WhentheMCUentersstop1mode,allinternalregistersincludinggeneral-purposeI/Ocontroland data registers are powered down. All of the general-purpose I/O pins assume their reset state: output buffers and pullups turned off. Upon exit from stop1, all I/O must be initialized as if the MCU had been reset. • WhentheMCUentersstop2mode,theinternalregistersarepowereddownasinstop1buttheI/O pin states are latched and held. For example, a port pin that is an output driving low continues to functionasanoutputdrivingloweventhoughitsassociateddatadirectionandoutputdataregisters arepowereddowninternally.Uponexitfromstop2,thepinscontinuetoholdtheirstatesuntila1 iswrittentothePPDACKbit.Toavoiddiscontinuityinthepinstatefollowingexitfromstop2,the user must restore the port control and data registers to the values they held before entering stop2. ThesevaluescanbestoredinRAMbeforeenteringstop2becausetheRAMismaintainedduring stop2. • In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon recovery, normal I/O function is available to the user. 6.5 Register Definition ThissectionprovidesinformationaboutallregistersandcontrolbitsassociatedwiththeparallelI/Oports. RefertotablesinChapter4,“Memory,”fortheabsoluteaddressassignmentsforallparallelI/Oregisters. Thissectionreferstoregistersandcontrolbitsonlybytheirnames.AFreescale-providedequateorheader file normally is used to translate these names into the appropriate absolute addresses. 6.5.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD) Port A includes eight pins shared between general-purpose I/O and the KBI module. Port A pins used as general-purposeI/OpinsarecontrolledbytheportAdata(PTAD),datadirection(PTADD),pullupenable (PTAPE), and slew rate control (PTASE) registers. IftheKBItakescontrolofaportApin,thecorrespondingPTASEbitisignoredsincethepinfunctionsas an input. As long as PTADD is 0, the PTAPE controls the pullup enable for the KBI function. Reads of PTAD will return the logic value of the corresponding pin, provided PTADD is 0. MC9S08GT16A/GT8A Data Sheet, Rev. 1 86 Freescale Semiconductor

Parallel Input/Output 7 6 5 4 3 2 1 0 R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 W Reset 0 0 0 0 0 0 0 0 Figure6-8. Port A Data Register (PTAD) Table6-1. PTAD Field Descriptions Field Description 7:0 Port A Data Register Bits— For port A pins that are inputs, reads return the logic level on the pin. For port A PTAD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. ResetforcesPTADtoall0s,butthese0sarenotdrivenoutthecorrespondingpinsbecauseresetalsoconfigures all port pins as high-impedance inputs with pullups disabled. 7 6 5 4 3 2 1 0 R PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-9. Pullup Enable for Port A (PTAPE) Table6-2. PTAPE Field Descriptions Field Description 7:0 PullupEnableforPortABits—ForportApinsthatareinputs,theseread/writecontrolbitsdeterminewhether PTAPE[7:0] internalpullupdevicesareenabledprovidedthecorrespondingPTADDnis0.ForportApinsthatareconfigured asoutputs,thesebitsareignoredandtheinternalpullupdevicesaredisabled.Whenanyofbits7through4of port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits enable pulldown rather than pullup devices. 0 Internal pullup device disabled. 1 Internal pullup device enabled. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 87

Parallel Input/Output 7 6 5 4 3 2 1 0 R PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 W Reset 0 0 0 0 0 0 0 0 Figure6-10. Slew Rate Control Enable for Port A (PTASE) Table6-3. PTASE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port A Bits — For port A pins that are outputs, these read/write control bits PTASE[7:0] determine whether the slew rate controlled outputs are enabled. For port A pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0 W Reset 0 0 0 0 0 0 0 0 Figure6-11. Data Direction for Port A (PTADD) Table6-4. PTADD Field Descriptions Field Description 7:0 DataDirectionforPortABits—Theseread/writebitscontrolthedirectionofportApinsandwhatisreadfor PTADD[7:0] PTAD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn. MC9S08GT16A/GT8A Data Sheet, Rev. 1 88 Freescale Semiconductor

Parallel Input/Output 6.5.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) Port B includes eight general-purpose I/O pins that share with the ATD function. Port B pins used as general-purposeI/OpinsarecontrolledbytheportBdata(PTBD),datadirection(PTBDD),pullupenable (PTBPE), and slew rate control (PTBSE) registers. IftheATDtakescontrolofaportBpin,thecorrespondingPTBDD,PTBSE,andPTBPEbitsareignored. When a port B pin is being used as an ATD pin, reads of PTBD will return a 0 of the corresponding pin, provided PTBDD is 0. 7 6 5 4 3 2 1 0 R PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 W Reset 0 0 0 0 0 0 0 0 Figure6-12. Port B Data Register (PTBD) Table6-5. PTBD Field Descriptions Field Description 7:0 Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B PTBD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTBD to all 0s, but these 0s are not driven out on the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7 6 5 4 3 2 1 0 R PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-13. Pullup Enable for Port B (PTBPE) Table6-6. PTBPE Field Descriptions Field Description 7:0 PullupEnableforPortBBits—ForportBpinsthatareinputs,theseread/writecontrolbitsdeterminewhether PTBPE[7:0] internal pullup devices are enabled. For port B pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 89

Parallel Input/Output 7 6 5 4 3 2 1 0 R PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 W Reset 0 0 0 0 0 0 0 0 Figure6-14. Data Direction for Port A (PTBSE) Table6-7. PTBSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port B Bits — For port B pins that are outputs, these read/write control bits PTBSE[7:0] determine whether the slew rate controlled outputs are enabled. For port B pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-15. Data Direction for Port B (PTBDD) Table6-8. PTBDD Field Descriptions Field Description 7:0 DataDirectionforPortBBits—Theseread/writebitscontrolthedirectionofportBpinsandwhatisreadfor PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. MC9S08GT16A/GT8A Data Sheet, Rev. 1 90 Freescale Semiconductor

Parallel Input/Output 6.5.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) PortCincludeseightgeneral-purposeI/OpinsthatsharewiththeSCI2andIICmodules.PortCpinsused as general-purpose I/O pins are controlled by the port C data (PTCD), data direction (PTCDD), pullup enable (PTCPE), and slew rate control (PTCSE) registers. IftheSCI2takescontrolofaportCpin,thecorrespondingPTCDDbitisignored.PTCSEcanbeusedto provide slew rate on the SCI2 transmit pin, TxD2. PTCPE can be used, provided the corresponding PTCDD bit is 0, to provide a pullup device on the SCI2 receive pin, RxD2. If the IIC takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to provide slew rate on the IIC serial data pin (SDA), when in output mode and the IIC clock pin (SCL). PTCPE can be used, provided the corresponding PTCDD bit is 0, to provide a pullup device on the IIC serial data pin, when in receive mode. Reads of PTCD will return the logic value of the corresponding pin, provided PTCDD is 0. 7 6 5 4 3 2 1 0 R PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 W Reset 0 0 0 0 0 0 0 0 Figure6-16. Port C Data Register (PTCD) Table6-9. PTCD Field Descriptions Field Description 7:0 Port C Data Register Bits— For port C pins that are inputs, reads return the logic level on the pin. For port C PTCD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 91

Parallel Input/Output 7 6 5 4 3 2 1 0 R PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-17. Pullup Enable for Port C (PTCPE) Table6-10. PTCPE Field Descriptions Field Description 7:0 PullupEnableforPortCBits—ForportCpinsthatareinputs,theseread/writecontrolbitsdeterminewhether PTCPE[7:0] internal pullup devices are enabled. For port C pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. 7 6 5 4 3 2 1 0 R PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0 W Reset 0 0 0 0 0 0 0 0 Figure6-18. Slew Rate Control Enable for Port C (PTCSE) Table6-11. PTCSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port C Bits — For port C pins that are outputs, these read/write control bits PTCSE[7:0] determine whether the slew rate controlled outputs are enabled. For port B pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-19. Data Direction for Port C (PTCDD) Table6-12. PTCDD Field Descriptions Field Description 7:0 DataDirectionforPortCBits—Theseread/writebitscontrolthedirectionofportCpinsandwhatisreadfor PTCDD[7:0] PTCD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn. MC9S08GT16A/GT8A Data Sheet, Rev. 1 92 Freescale Semiconductor

Parallel Input/Output 6.5.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) Port D includes five pins shared between general-purpose I/O, TPM1, and TPM2. Port D pins used as general-purposeI/OpinsarecontrolledbytheportDdata(PTDD),datadirection(PTDDD),pullupenable (PTDPE), and slew rate control (PTDSE) registers. If a TPM takes control of a port D pin, the corresponding PTDDD bit is ignored. When the TPM is in output compare mode, the corresponding PTDSE can be used to provide slew rate on the pin. When the TPM is in input capture mode, the corresponding PTDPE can be used, provided the corresponding PTDDD bit is 0, to provide a pullup device on the pin. Reads of PTDD will return the logic value of the corresponding pin, provided PTDDD is 0. 7 6 5 4 3 2 1 0 R 0 0 0 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-20. Port D Data Register (PTDD) Table6-13. PTDD Field Descriptions Field Description 4:0 Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D PTDD[4:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7 6 5 4 3 2 1 0 R 0 0 0 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-21. Pullup Enable for Port D (PTDPE) Table6-14. PTDPE Field Descriptions Field Description 4:0 PullupEnableforPortDBits—ForportDpinsthatareinputs,theseread/writecontrolbitsdeterminewhether PTDPE[4:0] internal pullup devices are enabled. For port D pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 93

Parallel Input/Output 7 6 5 4 3 2 1 0 R 0 0 0 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 W Reset 0 0 0 0 0 0 0 0 Figure6-22. Slew Rate Control Enable for Port D (PTDSE) Table6-15. PTDSE Field Descriptions Field Description 4:0 Slew Rate Control Enable for Port D Bits — For port D pins that are outputs, these read/write control bits PTDSE[4:0] determine whether the slew rate controlled outputs are enabled. For port D pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R 0 0 0 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-23. Data Direction for Port D (PTDDD) Table6-16. PTDDD Field Descriptions Field Description 4:0 DataDirectionforPortDBits—Theseread/writebitscontrolthedirectionofportDpinsandwhatisreadfor PTDDD[4:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn. MC9S08GT16A/GT8A Data Sheet, Rev. 1 94 Freescale Semiconductor

Parallel Input/Output 6.5.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) Port E includes six general-purpose I/O pins that share with the SCI1 and SPI modules. Port E pins used as general-purpose I/O pins are controlled by the port E data (PTED), data direction (PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers. IftheSCI1takescontrolofaportEpin,thecorrespondingPTEDDbitisignored.PTESEcanbeusedto provide slew rate on the SCI1 transmit pin, TxD1. PTEPE can be used, provided the corresponding PTEDD bit is 0, to provide a pullup device on the SCI1 receive pin, RxD1. If the SPI takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to provide slew rate on the SPI serial output pin (MOSI or MISO) and serial clock pin (SPSCK) depending ontheSPIoperationalmode.PTEPEcanbeused,providedthecorrespondingPTEDDbitis0,toprovide a pullup device on the SPI serial input pins (MOSI or MISO) and slave select pin (SS) depending on the SPI operational mode. Reads of PTED will return the logic value of the corresponding pin, provided PTEDD is 0. 7 6 5 4 3 2 1 0 R 0 0 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0 W Reset 0 0 0 0 0 0 0 0 Figure6-24. Port E Data Register (PTED) Table6-17. PTED Field Descriptions Field Description 5:0 Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E PTED[5:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits in this register. For port E pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. ResetforcesPTEDtoall0s,butthese0sarenotdrivenoutthecorrespondingpinsbecauseresetalsoconfigures all port pins as high-impedance inputs with pullups disabled. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 95

Parallel Input/Output 7 6 5 4 3 2 1 0 R 0 0 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-25. Pullup Enable for Port E (PTEPE) Table6-18. PTEPE Field Descriptions Field Description 5:0 PullupEnableforPortEBits—ForportEpinsthatareinputs,theseread/writecontrolbitsdeterminewhether PTEPE[5:0] internal pullup devices are enabled. For port E pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. 7 6 5 4 3 2 1 0 R 0 0 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0 W Reset 0 0 0 0 0 0 0 0 Figure6-26. Slew Rate Control Enable for Port E (PTESE) Table6-19. PTESE Field Descriptions Field Description 5:0 Slew Rate Control Enable for Port E Bits —For port E pins that are outputs, these read/write control bits PTESE[5:0] determinewhethertheslewratecontrolledoutputsareenabled.ForportEpinsthatareconfiguredasinputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R 0 0 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-27. Data Direction for Port E (PTEDD) Table6-20. PTEDD Field Descriptions Field Description 5:0 DataDirectionforPortEBits—Theseread/writebitscontrolthedirectionofportEpinsandwhatisreadfor PTEDD[5:0] PTED reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn. MC9S08GT16A/GT8A Data Sheet, Rev. 1 96 Freescale Semiconductor

Parallel Input/Output 6.5.6 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) PortGincludesfourgeneral-purposeI/OpinsthataresharedwithBKGD/MSfunctionandtheoscillator or external clock pins. Port G pins used as general-purpose I/O pins are controlled by the port G data (PTGD), data direction (PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers. Port pin PTG0, while in reset, defaults to the BKGD/MS pin. After the MCU is exits reset, PTG0 can be configuredtobeageneral-purposeoutputpin.WhenBKGD/MStakescontrolofPTG0,thecorresponding PTGDD, PTGPE, and PTGPSE bits are ignored. Port pins PTG1 and PTG2 can be configured to be oscillator or external clock pins. When the oscillator takes control of a port G pin, the corresponding PTGD, PTGDD, PTGSE, and PTGPE bits are ignored. Reads of PTGD will return the logic value of the corresponding pin, provided PTGDD is 0. 7 6 5 4 3 2 1 0 R 0 0 0 0 PTGD3 PTGD2 PTGD1 PTGD0 W Reset 0 0 0 0 0 0 0 0 Figure6-28. Port PTG Data Register (PTGD) Table6-21. PTGD Field Descriptions Field Description 3:0 PortPTGDataRegisterBits—ForportGpinsthatareinputs,readsreturnthelogiclevelonthepin.Forport PTGD[3:0] G pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7 6 5 4 3 2 1 0 R 0 0 0 0 PTGPE3 PTGPE2 PTGPE1 PTGPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-29. Pullup Enable for Port G (PTGPE) Table6-22. PTGPE Field Descriptions Field Description 3:0 PullupEnableforPortGBits—ForportGpinsthatareinputs,theseread/writecontrolbitsdeterminewhether PTGPE[3:0] internal pullup devices are enabled. For port G pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 97

Parallel Input/Output 7 6 5 4 3 2 1 0 R 0 0 0 0 PTGSE3 PTGSE2 PTGSE1 PTGSE0 W Reset 0 0 0 0 0 0 0 0 Figure6-30. Slew Rate Control Enable for Port G (PTGSE) Table6-23. PTGSE Field Descriptions Field Description 3:0 Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits PTGSE[3:0] determine whether the slew rate controlled outputs are enabled. For port G pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R 0 0 0 0 PTGDD0 PTGDD3 PTGDD2 PTGDD1 Note (1) W Reset 0 0 0 0 0 0 0 0 Figure6-31. Data Direction for Port G (PTGDD) 1 Although PTGDD0 is implemented, this bit actually has no effect on the operation of PTG0/BKGD. Table6-24. PTGDD Field Descriptions Field Description 3:0 DataDirectionforPortGBits—Theseread/writebitscontrolthedirectionofportGpinsandwhatisreadfor PTGDD[3:0] PTGD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn. MC9S08GT16A/GT8A Data Sheet, Rev. 1 98 Freescale Semiconductor

Chapter 7 Keyboard Interrupt (S08KBIV1) 7.1 Introduction The MC9S08GT16A/GT8A has one KBI module with eight keyboard interrupt inputs that share port A pins. SeeChapter2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins. 7.1.1 Port A and Keyboard Interrupt Pins PTA7/ PTA6/ PTA5/ PTA4/ PTA3/ PTA2/ PTA1/ PTA0/ MCU Pin: KBIP7 KBIP6 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0 Figure7-1. Port A Pin Names The following paragraphs discuss controlling the keyboard interrupt pins. PortAisan8-bitportwhichissharedamongtheKBIkeyboardinterruptinputsandgeneral-purposeI/O. TheeightKBIPEncontrolbitsintheKBIPEregisterallowselectionofanycombinationofportApinsto be assigned as KBI inputs. Any pins which are enabled as KBI inputs will be forced to act as inputs and theremainingportApinsareavailableasgeneral-purposeI/OpinscontrolledbytheportAdata(PTAD), data direction (PTADD), and pullup enable (PTAPE) registers. KBI inputs can be configured for edge-only sensitivity or edge-and-level sensitivity. Bits 3 through 0 of port A are falling-edge/low-level sensitive while bits 7 through 4 can be configured for rising-edge/high-level or for falling-edge/low-level sensitivity. TheeightPTAPEncontrolbitsinthePTAPEregisterallowyoutoselectwhetheraninternalpullupdevice is enabled on each port A pin that is configured as an input. When any of bits 7 through 4 of port A are enabledasKBIinputsandareconfiguredtodetectrisingedges/highlevels,thepullupenablebitsenable pulldown rather than pullup devices. An enabled keyboard interrupt can be used to wake the MCU from wait or standby (stop3). 7.1.2 Features The keyboard interrupt (KBI) module features include: • Keyboard interrupts selectable on eight port pins: — Four falling-edge/low-level sensitive — Four falling-edge/low-level or rising-edge/high-level sensitive — Choice of edge-only or edge-and-level sensitivity — Common interrupt flag and interrupt enable control — Capable of waking up the MCU from stop3 or wait mode MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 99

Keyboard Interrupt (S08KBIV1) VREFLVREFHVSSADVDDAD 4 HCS08 CORE BKGD 8IN-BTIETR KREUYPBTO (AKRBDI) 8 PORT A 4 PPPTTTAAA347///KKKBBBIIIPPP347–– NOTE 6 PTA0/KBIP0 CPU BDC 4 10-BIT 8 T B PPTTBB74//AADDPP74– ANALOG-TO-DIGITAL OR 4 HCS08 SYSTEM CONTROL CONVERTER (ATD) P PTB3/ADP3– RESET PTB0/ADP0 NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION PTC7 POWER MANAGEMENT PTC6 PTC5 RTI COP INTER-IC (IIC) SSDCAL PORT C PPPTTTCCC432//SSCDAL NOTE 5 IRQ IRQ LVD RXD2 NOTES 2, 3 SERIAL COMMUNICATIONS PTC1/RxD2 TXD2 INTERFACE (SCI2) PTC0/TxD2 CH1 USER FLASH 2-CHANNEL TIMER/PWM PTD4/TPM2CH1 CH0 (GT16A = 16,384 BYTES) (TPM2) PTD3/TPM2CLK/TPM2CH0 (GT8A = 8192 BYTES) D CH0 RT O PTD2/TPM1CH2 3-CHANNEL TIMER/PWM CH1 P PTD1/TPM1CH1 (TPM1) CH2 PTD0/TPM1CLK/TPM1CH0 USER RAM (GT16A = 2048 BYTES) SPSCK (GT8A = 1024 BYTES) PTE5/SPSCK MOSI SERIAL PERIPHERAL PTE4/MOSI MISO ON-CHIP ICE INTERFACE (SPI) SS RT E PPTTEE32//MSSISO DEBUG O RXD1 P MODULE (DBG) SERIAL COMMUNICATIONS PTE1/RxD1 TXD1 INTERFACE (SCI1) PTE0/TxD1 INTERNAL CLOCK GENERATOR (ICG) PTG3 EXTAL G PTG2/EXTAL XTAL T LOW-POWER OSCILLATOR R PTG1/XTAL BKGD O P PTG0/BKGD/MS V DD VOLTAGE V SS REGULATOR = Pins not available in 44-, 42-, or 32-pin packages V SS = Pins not available in 42- or 32-pin packages = Pins not available in 32-pin packages NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE=1). 3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD. 4. Pin contains integrated pullup device. 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1). Figure7-2. Block Diagram Highlighting the KBI Module MC9S08GT16A/GT8A Data Sheet, Rev. 1 100 Freescale Semiconductor

Keyboard Interrupt (S08KBIV1) 7.1.3 KBI Block Diagram Figure7-3 shows the block diagram for a KBI module. KBIP0 KBIPE0 KBIP3 KBACK BUSCLK KBIPE3 VDD RESET KBF DCLRQ 1 SYNCHRONIZER CK KBIP4 0 S KBIPE4 KEYBOARD STOP STOP BYPASS KEYBOARD KBEDG4 INTERRUPT FF INTERRUPT REQUEST KBIMOD 1 KBIE KBIPn 0 S KBIPEn KBEDGn Figure7-3. KBI Block Diagram 7.2 Register Definition This section provides information about all registers and control bits associated with the KBI module. Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignments for all KBI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 101

Keyboard Interrupt (S08KBIV1) 7.2.1 KBI Status and Control Register (KBISC) 7 6 5 4 3 2 1 0 R KBF 0 KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBIE KBIMOD W KBACK Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure7-4. KBI Status and Control Register (KBISC) Table7-1. KBISC Register Field Descriptions Field Description 7:4 KeyboardEdgeSelectforKBIPortBits—Eachoftheseread/writebitsselectsthepolarityoftheedgesand/or KBEDG[7:4] levelsthatarerecognizedastriggereventsonthecorrespondingKBIportpinwhenitisconfiguredasakeyboard interruptinput(KBIPEn=1).AlsoseetheKBIMODcontrolbit,whichdetermineswhetherthepinissensitiveto edges-only or edges and levels. 0 Falling edges/low levels 1 Rising edges/high levels 3 Keyboard Interrupt Flag — This read-only status flag is set whenever the selected edge event has been KBF detected on any of the enabled KBI port pins. This flag is cleared by writing a 1 to the KBACK control bit. The flag will remain set if KBIMOD=1 to select edge-and-level operation and any enabled KBI port pin remains at the asserted level. KBF can be used as a software pollable flag (KBIE=0) or it can generate a hardware interrupt request to the CPU (KBIE=1). 0 No KBI interrupt pending 1 KBI interrupt pending 2 KeyboardInterruptAcknowledge—Thiswrite-onlybit(readsalwaysreturn0)isusedtocleartheKBFstatus KBACK flag by writing a 1 to KBACK. When KBIMOD=1 to select edge-and-level operation and any enabled KBI port pinremains at the asserted level, KBF is being continuously set so writing 1 to KBACK does not clear the KBF flag. 1 KeyboardInterruptEnable—Thisread/writecontrolbitdetermineswhetherhardwareinterruptsaregenerated KBIE whentheKBFstatusflagequals1.WhenKBIE=0,nohardwareinterruptsaregenerated,butKBFcanstillbe used for software polling. 0 KBF does not generate hardware interrupts (use polling) 1 KBI hardware interrupt requested when KBF=1 KBIMOD Keyboard Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level detection.KBIportbits3through0candetectfallingedges-onlyorfallingedgesandlowlevels.KBIportbits7 through 4 can be configured to detect either: • Rising edges-only or rising edges and high levels (KBEDGn=1) • Falling edges-only or falling edges and low levels (KBEDGn=0) 0 Edge-only detection 1 Edge-and-level detection MC9S08GT16A/GT8A Data Sheet, Rev. 1 102 Freescale Semiconductor

Keyboard Interrupt (S08KBIV1) 7.2.2 KBI Pin Enable Register (KBIPE) 7 6 5 4 3 2 1 0 R KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure7-5. KBI Pin Enable Register (KBIPE) Table7-2. KBIPE Register Field Descriptions Field Description 7:0 Keyboard Pin Enable for KBI Port Bits — Each of these read/write bits selects whether the associated KBI KBIPE[7:0] port pin is enabled as a keyboard interrupt input or functions as a general-purpose I/O pin. 0 Bit n of KBI port is a general-purpose I/O pin not associated with the KBI 1 Bit n of KBI port enabled as a keyboard interrupt input 7.3 Functional Description 7.3.1 Pin Enables The KBIPEn control bits in the KBIPE register allow a user to enable (KBIPEn= 1) any combination of KBI-related port pins to be connected to the KBI module. Pins corresponding to 0s in KBIPE are general-purpose I/O pins that are not associated with the KBI module. 7.3.2 Edge and Level Sensitivity Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs in a KBI module must be at the deasserted logic level. Afallingedgeisdetectedwhenanenabledkeyboardinputsignalisseenasalogic1(thedeassertedlevel) during one bus cycle and then a logic0 (the asserted level) during the next cycle. Arisingedgeisdetectedwhentheinputsignalisseenasalogic0duringonebuscycleandthenalogic1 during the next cycle. The KBIMOD control bit can be set to reconfigure the detection logic so that it detects edges and levels. In KBIMOD =1 mode, the KBF status flag becomes set when an edge is detected (when one or more enabled pins change from the deasserted to the asserted level while all other enabled pins remain at their deassertedlevels),buttheflagiscontinuouslyset(andcannotbecleared)aslongasanyenabledkeyboard inputpinremainsattheassertedlevel.WhentheMCUentersstopmode,thesynchronousedge-detection logic is bypassed (because clocks are stopped). In stop mode, KBI inputs act as asynchronous level-sensitive inputs so they can wake the MCU from stop mode. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 103

Keyboard Interrupt (S08KBIV1) 7.3.3 KBI Interrupt Controls The KBF status flag becomes set (1) when an edge event has been detected on any KBI input pin. If KBIE =1intheKBISCregister,ahardwareinterruptwillberequestedwheneverKBF= 1.TheKBFflag is cleared by writing a 1 to the keyboard acknowledge (KBACK) bit. When KBIMOD =0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK. WhenKBIMOD = 1(selectingedge-and-leveloperation),KBFcannotbeclearedaslongasanykeyboard input is at its asserted level. MC9S08GT16A/GT8A Data Sheet, Rev. 1 104 Freescale Semiconductor

Chapter 8 Central Processor Unit (S08CPUV2) 8.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructionsandenhancedaddressingmodeswereaddedtoimproveCcompilerefficiencyandtosupport anewbackgrounddebugsystemwhichreplacesthemonitormodeofearlierM68HC08microcontrollers (MCU). 8.1.1 Features Features of the HCS08 CPU include: • Object code fully upward-compatible with M68HC05 and M68HC08 Families • All registers and memory are mapped to a single 64-Kbyte address space • 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space) • 16-bit index register (H:X) with powerful indexed addressing modes • 8-bit accumulator (A) • Many instructions treat X as a second general-purpose 8-bit register • Seven addressing modes: — Inherent — Operands in internal registers — Relative — 8-bit signed offset to branch destination — Immediate — Operand in next object code byte(s) — Direct — Operand in memory at 0x0000–0x00FF — Extended — Operand anywhere in 64-Kbyte address space — Indexed relative to H:X — Five submodes including auto increment — Indexed relative to SP — Improves C efficiency dramatically • Memory-to-memory data move instructions with four address mode combinations • Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (BCD) operations • Efficient bit manipulation instructions • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • STOP and WAIT instructions to invoke low-power operating modes MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 105

Central Processor Unit (S08CPUV2) 8.2 Programmer’s Model and CPU Registers Figure8-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) INDEX REGISTER (LOW) X 15 8 7 0 STACK POINTER SP 15 0 PROGRAM COUNTER PC 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure8-1. CPU Registers 8.2.1 Accumulator (A) The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit (ALU)isconnectedtotheaccumulatorandtheALUresultsareoftenstoredintotheAaccumulatorafter arithmeticandlogicaloperations.Theaccumulatorcanbeloadedfrommemoryusingvariousaddressing modes to specify the address where the loaded data comes from, or the contents of A can be stored to memory using various addressing modes to specify the address where data from A will be stored. Reset has no effect on the contents of the A accumulator. 8.2.2 Index Register (H:X) This16-bitregisterisactuallytwoseparate8-bitregisters(HandX),whichoftenworktogetherasa16-bit addresspointerwhereHholdstheupperbyteofanaddressandXholdsthelowerbyteoftheaddress.All indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer; however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the low-order 8-bit half (X). Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data values.Xcanbecleared,incremented,decremented,complemented,negated,shifted,orrotated.Transfer instructionsallowdatatobetransferredfromAortransferredtoAwherearithmeticandlogicaloperations can then be performed. ForcompatibilitywiththeearlierM68HC05Family,Hisforcedto0x00duringreset.Resethasnoeffect on the contents of X. MC9S08GT16A/GT8A Data Sheet, Rev. 1 106 Freescale Semiconductor

Central Processor Unit (S08CPUV2) 8.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can beanysizeuptotheamountofavailableRAM.Thestackisusedtoautomaticallysavethereturnaddress for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The AIS(addimmediatetostackpointer)instructionaddsan8-bitsignedimmediatevaluetoSP.Thisismost often used to allocate or deallocate space for local variables on the stack. SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs normally change the value in SP to the address of the last location (highest address) in on-chip RAM during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF). The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer. 8.2.4 Program Counter (PC) Theprogramcounterisa16-bitregisterthatcontainstheaddressofthenextinstructionoroperandtobe fetched. During normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location. This is called a change-of-flow. During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF. The vector stored there is the address of the first instruction that will be executed after exiting the reset state. 8.2.5 Condition Code Register (CCR) The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of theinstructionjustexecuted.Bits6and5aresetpermanentlyto1.Thefollowingparagraphsdescribethe functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 107

Central Processor Unit (S08CPUV2) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure8-2. Condition Code Register Table8-1. CCR Register Field Descriptions Field Description 7 Two’sComplementOverflowFlag—TheCPUsetstheoverflowflagwhenatwo’scomplementoverflowoccurs. V The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 0 No overflow 1 Overflow 4 Half-CarryFlag—TheCPUsetsthehalf-carryflagwhenacarryoccursbetweenaccumulatorbits3and4during H an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the result to a valid BCD value. 0 No carry between bits 3 and 4 1 Carry between bits 3 and 4 3 Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts I are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automaticallyaftertheCPUregistersaresavedonthestack,butbeforethefirstinstructionoftheinterruptservice routine is executed. Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This ensuresthatthenextinstructionafteraCLIorTAPwillalwaysbeexecutedwithoutthepossibilityofanintervening interrupt, provided I was set. 0 Interrupts enabled 1 Interrupts disabled 2 Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data N manipulationproducesanegativeresult,settingbit7oftheresult.Simplyloadingorstoringan8-bitor16-bitvalue causes N to be set if the most significant bit of the loaded or stored value was 1. 0 Non-negative result 1 Negative result 1 Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation Z produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the loaded or stored value was all 0s. 0 Non-zero result 1 Zero result 0 Carry/BorrowFlag—TheCPUsetsthecarry/borrowflagwhenanadditionoperationproducesacarryoutofbit C 7oftheaccumulatororwhenasubtractionoperationrequiresaborrow.Someinstructions—suchasbittestand branch, shift, and rotate — also clear or set the carry/borrow flag. 0 No carry out of bit 7 1 Carry out of bit 7 MC9S08GT16A/GT8A Data Sheet, Rev. 1 108 Freescale Semiconductor

Central Processor Unit (S08CPUV2) 8.3 Addressing Modes AddressingmodesdefinethewaytheCPUaccessesoperandsanddata.IntheHCS08,allmemory,status andcontrolregisters,andinput/output(I/O)portsshareasingle64-Kbytelinearaddressspacesoa16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructionsthataccessvariablesinRAMcanalsobeusedtoaccessI/Oandcontrolregistersornonvolatile program space. Someinstructionsusemorethanoneaddressingmode.Forinstance,moveinstructionsuseoneaddressing mode to specify the source operand and a second addressing mode to specify the destination address. InstructionssuchasBRCLR,BRSET,CBEQ,andDBNZuseoneaddressingmodetospecifythelocation of an operand for a test and then use relative addressing mode to specify the branch destination address whenthetestedconditionistrue.ForBRCLR,BRSET,CBEQ,andDBNZ,theaddressingmodelistedin the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 8.3.1 Inherent Addressing Mode (INH) In this addressing mode, operands needed to complete the instruction (if any) are located within CPU registers so the CPU does not need to access memory to get any operands. 8.3.2 Relative Addressing Mode (REL) Relativeaddressingmodeisusedtospecifythedestinationlocationforbranchinstructions.Asigned8-bit offsetvalueislocatedinthememorylocationimmediatelyfollowingtheopcode.Duringexecution,ifthe branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 8.3.3 Immediate Addressing Mode (IMM) In immediate addressing mode, the operand needed to complete the instruction is included in the object codeimmediatelyfollowingtheinstructionopcodeinmemory.Inthecaseofa16-bitimmediateoperand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that. 8.3.4 Direct Addressing Mode (DIR) Indirectaddressingmode,theinstructionincludesthelow-ordereightbitsofanaddressinthedirectpage (0x0000–0x00FF).Duringexecutiona16-bitaddressisformedbyconcatenatinganimplied0x00forthe high-order half of the address and the direct address from the instruction to get the 16-bit address where thedesiredoperandislocated.Thisisfasterandmorememoryefficientthanspecifyingacomplete16-bit address for the operand. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 109

Central Processor Unit (S08CPUV2) 8.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 8.3.6 Indexed Addressing Mode Indexedaddressingmodehassevenvariationsincludingfivethatusethe16-bitH:Xindexregisterpairand two that use the stack pointer as the base reference. 8.3.6.1 Indexed, No Offset (IX) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairastheaddressof the operand needed to complete the instruction. 8.3.6.2 Indexed, No Offset with Post Increment (IX+) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairastheaddressof the operand needed to complete the instruction. The index register pair is then incremented (H:X= H:X+ 0x0001) after the operand has been fetched. This addressing mode is only used for MOV and CBEQ instructions. 8.3.6.3 Indexed, 8-Bit Offset (IX1) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairplusanunsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairplusanunsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. Theindexregisterpairisthenincremented(H:X= H:X +0x0001)aftertheoperandhasbeenfetched.This addressing mode is used only for the CBEQ instruction. 8.3.6.5 Indexed, 16-Bit Offset (IX2) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairplusa16-bitoffset included in the instruction as the address of the operand needed to complete the instruction. 8.3.6.6 SP-Relative, 8-Bit Offset (SP1) Thisvariationofindexedaddressingusesthe16-bitvalueinthestackpointer(SP)plusanunsigned8-bit offset included in the instruction as the address of the operand needed to complete the instruction. MC9S08GT16A/GT8A Data Sheet, Rev. 1 110 Freescale Semiconductor

Central Processor Unit (S08CPUV2) 8.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like otherCPUinstructions.Inaddition,afewinstructionssuchasSTOPandWAITdirectlyaffectotherMCU circuitry. This section provides additional information about these operations. 8.4.1 Reset Sequence Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction boundary before responding to a reset event). For a more detailed discussion about how the MCU recognizes resets and determines the source, refer to the Resets, Interrupts, and System Configuration chapter. Thereseteventisconsideredconcludedwhenthesequencetodeterminewhethertheresetcamefroman internalsourceisdoneandwhentheresetpinisnolongerasserted.Attheconclusionofaresetevent,the CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for execution of the first program instruction. 8.4.2 Interrupt Sequence When an interrupt is requested, the CPU completes the current instruction before responding to the interrupt.Atthispoint,theprogramcounterispointingatthestartofthenextinstruction,whichiswhere the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the samesequenceofoperationsasforasoftwareinterrupt(SWI)instruction,excepttheaddressusedforthe vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. The CPU sequence for an interrupt is: 1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order. 2. Set the I bit in the CCR. 3. Fetch the high-order half of the interrupt vector. 4. Fetch the low-order half of the interrupt vector. 5. Delay for one free bus cycle. 6. Fetch three bytes of program information starting at the address indicated by the interrupt vector to fill the instruction queue in preparation for execution of the first instruction in the interrupt service routine. After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 111

Central Processor Unit (S08CPUV2) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). ForcompatibilitywiththeearlierM68HC05MCUs,thehigh-orderhalfoftheH:Xindexregisterpair(H) is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends theinterruptserviceroutine.ItisnotnecessarytosaveHifyouarecertainthattheinterruptserviceroutine does not use any instructions or auto-increment addressing modes that might change the value of H. The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 8.4.3 Wait Mode Operation The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that willwaketheCPUfromwaitmode.Whenaninterruptorreseteventoccurs,theCPUclockswillresume and the interrupt or reset event will be processed normally. IfaserialBACKGROUNDcommandisissuedtotheMCUthroughthebackgrounddebuginterfacewhile theCPUisinwaitmode,CPUclockswillresumeandtheCPUwillenteractivebackgroundmodewhere otherserialbackgroundcommandscanbeprocessed.Thisensuresthatahostdevelopmentsystemcanstill gain access to a target MCU even if it is in wait mode. 8.4.4 Stop Mode Operation Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to minimize power consumption. In such systems, external circuitry is needed to control the time spent in stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU from stop mode. When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control bithasbeensetbyaserialcommandthroughthebackgroundinterface(orbecausetheMCUwasresetinto activebackgroundmode),theoscillatorisforcedtoremainactivewhentheMCUentersstopmode.Inthis case,ifaserialBACKGROUNDcommandisissuedtotheMCUthroughthebackgrounddebuginterface whiletheCPUisinstopmode,CPUclockswillresumeandtheCPUwillenteractivebackgroundmode whereotherserialbackgroundcommandscanbeprocessed.Thisensuresthatahostdevelopmentsystem can still gain access to a target MCU even if it is in stop mode. RecoveryfromstopmodedependsontheparticularHCS08andwhethertheoscillatorwasstoppedinstop mode. Refer to the Modes of Operationchapter for more details. MC9S08GT16A/GT8A Data Sheet, Rev. 1 112 Freescale Semiconductor

Central Processor Unit (S08CPUV2) 8.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface. Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGNDopcode.Whentheprogramreachesthisbreakpointaddress,theCPUisforcedtoactivebackground mode rather than continuing the user program. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 113

Central Processor Unit (S08CPUV2) 8.5 HCS08 Instruction Set Summary Instruction Set Summary Nomenclature The nomenclature listed here is used in the instruction descriptions inTable8-2. Operators ( ) = Contents of register or memory location shown inside parentheses ← = Is loaded with (read: “gets”) & = Boolean AND | = Boolean OR ⊕ = Boolean exclusive-OR × = Multiply ÷ = Divide : = Concatenate + = Add – = Negate (two’s complement) CPU registers A = Accumulator CCR = Condition code register H = Index register, higher order (most significant) 8 bits X = Index register, lower order (least significant) 8 bits PC = Program counter PCH = Program counter, higher order (most significant) 8 bits PCL = Program counter, lower order (least significant) 8 bits SP = Stack pointer Memory and addressing M = A memory location or absolute data, depending on addressing mode M:M + 0x0001= A 16-bit value in two consecutive memory locations. The higher-order (most significant) 8 bits are located at the address of M, and the lower-order (least significant) 8 bits are located at the next higher sequential address. Condition code register (CCR) bits V = Two’s complement overflow indicator, bit 7 H = Half carry, bit 4 I = Interrupt mask, bit 3 N = Negative indicator, bit 2 Z = Zero indicator, bit 1 C = Carry/borrow, bit 0 (carry out of bit 7) CCR activity notation – = Bit not affected MC9S08GT16A/GT8A Data Sheet, Rev. 1 114 Freescale Semiconductor

Central Processor Unit (S08CPUV2) 0 = Bit forced to 0 1 = Bit forced to 1 = Bit set or cleared according to results of operation U = Undefined after the operation Machine coding notation dd = Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00) ee = Upper 8 bits of 16-bit offset ff = Lower 8 bits of 16-bit offset or 8-bit offset ii = One byte of immediate data jj = High-order byte of a 16-bit immediate data value kk = Low-order byte of a 16-bit immediate data value hh = High-order byte of 16-bit extended address ll = Low-order byte of 16-bit extended address rr = Relative offset Source form Everythinginthesourceformscolumns,exceptexpressionsinitaliccharacters,isliteralinformationthat must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a literal expression. All commas, pound signs (#), parentheses, and plus signs (+) are literal characters. n — Any label or expression that evaluates to a single integer in the range 0–7 opr8i — Any label or expression that evaluates to an 8-bit immediate value opr16i — Any label or expression that evaluates to a 16-bit immediate value opr8a — Anylabelorexpressionthatevaluatestoan8-bitvalue.Theinstructiontreatsthis8-bit value as the low order 8 bits of an address in the direct page of the 64-Kbyte address space (0x00xx). opr16a — Any label or expression that evaluates to a 16-bit value. The instruction treats this value as an address in the 64-Kbyte address space. oprx8 — Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing oprx16 — Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a 16-bit address bus, this can be either a signed or an unsigned value. rel — Any label or expression that refers to an address that is within –128 to +127 locations fromthe next addressafterthelastbyteof objectcodeforthecurrentinstruction.The assemblerwillcalculatethe8-bitsignedoffsetandincludeitintheobjectcodeforthis instruction. Address modes INH = Inherent (no operands) IMM = 8-bit or 16-bit immediate DIR = 8-bit direct EXT = 16-bit extended MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 115

Central Processor Unit (S08CPUV2) IX = 16-bit indexed no offset IX+ = 16-bit indexed no offset, post increment (CBEQ and MOV only) IX1 = 16-bit indexed with 8-bit offset from H:X IX1+ = 16-bit indexed with 8-bit offset, post increment (CBEQ only) IX2 = 16-bit indexed with 16-bit offset from H:X REL = 8-bit relative offset SP1 = Stack pointer with 8-bit offset SP2 = Stack pointer with 16-bit offset Table8-2. HCS08 Instruction Set Summary (Sheet 1 of 7) Effect 1s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B ADC #opr8i IMM A9 ii 2 ADC opr8a DIR B9 dd 3 ADC opr16a EXT C9 hh ll 4 ADC oprx16,X Add with Carry A← (A) + (M) + (C) ↕ ↕ – ↕ ↕ ↕ IX2 D9 ee ff 4 ADC oprx8,X IX1 E9 ff 3 ADC ,X IX F9 3 ADC oprx16,SP SP2 9ED9 ee ff 5 ADC oprx8,SP SP1 9EE9 ff 4 ADD #opr8i IMM AB ii 2 ADD opr8a DIR BB dd 3 ADD opr16a EXT CB hh ll 4 ADD oprx16,X Add without Carry A← (A) + (M) ↕ ↕ – ↕ ↕ ↕ IX2 DB ee ff 4 ADD oprx8,X IX1 EB ff 3 ADD ,X IX FB 3 ADD oprx16,SP SP2 9EDB ee ff 5 ADD oprx8,SP SP1 9EEB ff 4 Add Immediate Value SP← (SP) + (M) AIS #opr8i – – – – – – IMM A7 ii 2 (Signed) to Stack Pointer M is sign extended to a 16-bit value Add Immediate Value H:X← (H:X) + (M) AIX #opr8i (Signed) to Index – – – – – – IMM AF ii 2 M is sign extended to a 16-bit value Register (H:X) AND #opr8i IMM A4 ii 2 AND opr8a DIR B4 dd 3 AND opr16a EXT C4 hh ll 4 AND oprx16,X Logical AND A← (A) & (M) 0 – – ↕ ↕ – IX2 D4 ee ff 4 AND oprx8,X IX1 E4 ff 3 AND ,X IX F4 3 AND oprx16,SP SP2 9ED4 ee ff 5 AND oprx8,SP SP1 9EE4 ff 4 ASL opr8a DIR 38 dd 5 ASLA INH 48 1 AASSLLXoprx8,X A(Sriathmmee atisc LSShLif)t Left C 0 ↕ – – ↕ ↕ ↕ IINX1H 5688 ff 15 ASL ,X b7 b0 IX 78 4 ASL oprx8,SP SP1 9E68 ff 6 ASR opr8a DIR 37 dd 5 ASRA INH 47 1 ASRX Arithmetic Shift Right C ↕ – – ↕ ↕ ↕ INH 57 1 ASR oprx8,X IX1 67 ff 5 b7 b0 ASR ,X IX 77 4 ASR oprx8,SP SP1 9E67 ff 6 BCC rel Branch if Carry Bit Clear Branch if (C) = 0 – – – – – – REL 24 rr 3 MC9S08GT16A/GT8A Data Sheet, Rev. 1 116 Freescale Semiconductor

Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 2 of 7) Effect 1s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B DIR (b0) 11 dd 5 DIR (b1) 13 dd 5 DIR (b2) 15 dd 5 BCLR n,opr8a Clear Bit n in Memory Mn← 0 – – – – – – DIR (b3) 17 dd 5 DIR (b4) 19 dd 5 DIR (b5) 1B dd 5 DIR (b6) 1D dd 5 DIR (b7) 1F dd 5 Branch if Carry Bit Set BCS rel Branch if (C) = 1 – – – – – – REL 25 rr 3 (Same as BLO) BEQ rel Branch if Equal Branch if (Z) = 1 – – – – – – REL 27 rr 3 BranchifGreaterThanor BGE rel Equal To Branch if (N ⊕ V) = 0 – – – – – – REL 90 rr 3 (Signed Operands) Waits For and Processes BDM Enter Active Background BGND Commands Until GO, TRACE1, or – – – – – – INH 82 5+ if ENBDM = 1 TAGGO BGT rel Branch if Greater Than Branch if (Z)| (N ⊕ V) = 0 – – – – – – REL 92 rr 3 (Signed Operands) Branch if Half Carry Bit BHCC rel Branch if (H) = 0 – – – – – – REL 28 rr 3 Clear Branch if Half Carry Bit BHCS rel Branch if (H) = 1 – – – – – – REL 29 rr 3 Set BHI rel Branch if Higher Branch if (C) | (Z) = 0 – – – – – – REL 22 rr 3 BranchifHigherorSame BHS rel Branch if (C) = 0 – – – – – – REL 24 rr 3 (Same as BCC) BIHrel Branch if IRQ Pin High Branch if IRQ pin = 1 – – – – – – REL 2F rr 3 BIL rel Branch if IRQ Pin Low Branch if IRQ pin = 0 – – – – – – REL 2E rr 3 BIT #opr8i IMM A5 ii 2 BIT opr8a DIR B5 dd 3 BIT opr16a EXT C5 hh ll 4 (A) & (M) BIT oprx16,X Bit Test (CCR Updated but Operands 0 – – ↕ ↕ – IX2 D5 ee ff 4 BIT oprx8,X IX1 E5 ff 3 Not Changed) BIT ,X IX F5 3 BIT oprx16,SP SP2 9ED5 ee ff 5 BIT oprx8,SP SP1 9EE5 ff 4 Branch if Less Than BLE rel or Equal To Branch if (Z)| (N⊕V) = 1 – – – – – – REL 93 rr 3 (Signed Operands) Branch if Lower BLO rel Branch if (C) = 1 – – – – – – REL 25 rr 3 (Same as BCS) BLS rel Branch if Lower or Same Branch if (C) | (Z) = 1 – – – – – – REL 23 rr 3 BLTrel Branch if Less Than Branch if (N ⊕ V) =1 – – – – – – REL 91 rr 3 (Signed Operands) Branch if Interrupt Mask BMC rel Branch if (I) = 0 – – – – – – REL 2C rr 3 Clear BMI rel Branch if Minus Branch if (N) = 1 – – – – – – REL 2B rr 3 Branch if Interrupt Mask BMS rel Branch if (I) = 1 – – – – – – REL 2D rr 3 Set BNE rel Branch if Not Equal Branch if (Z) = 0 – – – – – – REL 26 rr 3 BPL rel Branch if Plus Branch if (N) = 0 – – – – – – REL 2A rr 3 BRA rel Branch Always No Test – – – – – – REL 20 rr 3 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 117

Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 3 of 7) Effect 1s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B DIR (b0) 01 dd rr 5 DIR (b1) 03 dd rr 5 DIR (b2) 05 dd rr 5 BRCLR n,opr8a,rel BranchifBitn inMemory Branch if (Mn) = 0 – – – – – ↕ DIR (b3) 07 dd rr 5 Clear DIR (b4) 09 dd rr 5 DIR (b5) 0B dd rr 5 DIR (b6) 0D dd rr 5 DIR (b7) 0F dd rr 5 BRN rel Branch Never Uses 3 Bus Cycles – – – – – – REL 21 rr 3 DIR (b0) 00 dd rr 5 DIR (b1) 02 dd rr 5 DIR (b2) 04 dd rr 5 BRSET n,opr8a,rel BranchifBitninMemory Branch if (Mn) = 1 – – – – – ↕ DIR (b3) 06 dd rr 5 Set DIR (b4) 08 dd rr 5 DIR (b5) 0A dd rr 5 DIR (b6) 0C dd rr 5 DIR (b7) 0E dd rr 5 DIR (b0) 10 dd 5 DIR (b1) 12 dd 5 DIR (b2) 14 dd 5 BSET n,opr8a Set Bitnin Memory Mn← 1 – – – – – – DIR (b3) 16 dd 5 DIR (b4) 18 dd 5 DIR (b5) 1A dd 5 DIR (b6) 1C dd 5 DIR (b7) 1E dd 5 PC←(PC) + 0x0002 push (PCL); SP← (SP) – 0x0001 BSR rel Branch to Subroutine push (PCH); SP← (SP) – 0x0001 – – – – – – REL AD rr 5 PC← (PC) +rel CBEQ opr8a,rel Branch if (A) = (M) DIR 31 dd rr 5 CBEQA #opr8i,rel Branch if (A) = (M) IMM 41 ii rr 4 CBEQX #opr8i,rel Compare and Branch if Branch if (X) = (M) IMM 51 ii rr 4 – – – – – – CBEQ oprx8,X+,rel Equal Branch if (A) = (M) IX1+ 61 ff rr 5 CBEQ ,X+,rel Branch if (A) = (M) IX+ 71 rr 5 CBEQoprx8,SP,rel Branch if (A) = (M) SP1 9E61 ff rr 6 CLC Clear Carry Bit C← 0 – – – – – 0 INH 98 1 CLI Clear Interrupt Mask Bit I← 0 – – 0 – – – INH 9A 1 CLR opr8a M← 0x00 DIR 3F dd 5 CLRA A← 0x00 INH 4F 1 CLRX X← 0x00 INH 5F 1 CLRH Clear H← 0x00 0 – – 0 1 – INH 8C 1 CLR oprx8,X M← 0x00 IX1 6F ff 5 CLR ,X M← 0x00 IX 7F 4 CLR oprx8,SP M← 0x00 SP1 9E6F ff 6 CMP #opr8i IMM A1 ii 2 CMP opr8a DIR B1 dd 3 CMP opr16a EXT C1 hh ll 4 (A) – (M) CMP oprx16,X Compare Accumulator (CCR Updated But Operands Not ↕ – – ↕ ↕ ↕ IX2 D1 ee ff 4 CMP oprx8,X with Memory IX1 E1 ff 3 Changed) CMP ,X IX F1 3 CMP oprx16,SP SP2 9ED1 ee ff 5 CMP oprx8,SP SP1 9EE1 ff 4 COM opr8a M← (M)= 0xFF – (M) DIR 33 dd 5 COMA A← (A) = 0xFF – (A) INH 43 1 CCOOMMXoprx8,X C(Oonmep’sle Cmoemnptlement) MX←← ((MX)) == 00xxFFFF –– ((XM)) 0 – – ↕ ↕ 1 IINX1H 5633 ff 15 COM ,X M← (M) = 0xFF – (M) IX 73 4 COM oprx8,SP M← (M) = 0xFF – (M) SP1 9E63 ff 6 CPHXopr16a EXT 3E hh ll 6 (H:X) – (M:M + 0x0001) CPHX #opr16i Compare IndexRegister (CCR Updated But Operands Not ↕ – – ↕ ↕ ↕ IMM 65 jj kk 3 CPHXopr8a (H:X) withMemory DIR 75 dd 5 Changed) CPHXoprx8,SP SP1 9EF3 ff 6 MC9S08GT16A/GT8A Data Sheet, Rev. 1 118 Freescale Semiconductor

Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 4 of 7) Effect 1s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B CPX #opr8i IMM A3 ii 2 CPX opr8a DIR B3 dd 3 CPX opr16a EXT C3 hh ll 4 Compare X (Index (X) – (M) CPX oprx16,X Register Low) with (CCR Updated But Operands Not ↕ – – ↕ ↕ ↕ IX2 D3 ee ff 4 CPX oprx8,X IX1 E3 ff 3 Memory Changed) CPX ,X IX F3 3 CPX oprx16,SP SP2 9ED3 ee ff 5 CPX oprx8,SP SP1 9EE3 ff 4 Decimal Adjust DAA AccumulatorAfterADDor (A) U – – ↕ ↕ ↕ INH 72 1 10 ADC of BCD Values DBNZ opr8a,rel DIR 3B dd rr 7 DBNZA rel INH 4B rr 4 Decrement A, X, or M DBNZX rel Decrement and Branch if Branch if (result)≠0 – – – – – – INH 5B rr 4 DBNZ oprx8,X,rel Not Zero IX1 6B ff rr 7 DBNZX Affects X Not H DBNZ ,X,rel IX 7B rr 6 DBNZ oprx8,SP,rel SP1 9E6B ff rr 8 DEC opr8a M← (M) – 0x01 DIR 3A dd 5 DECA A← (A) – 0x01 INH 4A 1 DDEECCXoprx8,X Decrement MX←← ((XM)) –– 00xx0011 ↕ – – ↕ ↕ – IINX1H 56AA ff 15 DEC ,X M← (M) – 0x01 IX 7A 4 DEC oprx8,SP M← (M) – 0x01 SP1 9E6A ff 6 DIV Divide HA←← R (Hem:Aa)÷in(dXe)r – – – – ↕ ↕ INH 52 6 EOR #opr8i IMM A8 ii 2 EOR opr8a DIR B8 dd 3 EOR opr16a EXT C8 hh ll 4 Exclusive OR EOR oprx16,X Memory with A← (A⊕ M) 0 – – ↕ ↕ – IX2 D8 ee ff 4 EOR oprx8,X IX1 E8 ff 3 Accumulator EOR ,X IX F8 3 EOR oprx16,SP SP2 9ED8 ee ff 5 EOR oprx8,SP SP1 9EE8 ff 4 INC opr8a M← (M) + 0x01 DIR 3C dd 5 INCA A← (A) + 0x01 INH 4C 1 IINNCCXoprx8,X Increment MX←← ((XM)) ++ 00xx0011 ↕ – – ↕ ↕ – IINX1H 56CC ff 15 INC ,X M← (M) + 0x01 IX 7C 4 INC oprx8,SP M← (M) + 0x01 SP1 9E6C ff 6 JMP opr8a DIR BC dd 3 JMP opr16a EXT CC hh ll 4 JMP oprx16,X Jump PC← Jump Address – – – – – – IX2 DC ee ff 4 JMP oprx8,X IX1 EC ff 3 JMP ,X IX FC 3 JSR opr8a PC← (PC) +n (n = 1, 2, or 3) DIR BD dd 5 JSR opr16a Push (PCL); SP← (SP) – 0x0001 EXT CD hh ll 6 JSR oprx16,X Jump to Subroutine Push (PCH); SP← (SP) – 0x0001 – – – – – – IX2 DD ee ff 6 JSR oprx8,X PC← Unconditional Address IX1 ED ff 5 JSR ,X IX FD 5 LDA #opr8i IMM A6 ii 2 LDA opr8a DIR B6 dd 3 LDA opr16a EXT C6 hh ll 4 LDA oprx16,X Load Accumulator from A← (M) 0 – – ↕ ↕ – IX2 D6 ee ff 4 LDA oprx8,X Memory IX1 E6 ff 3 LDA ,X IX F6 3 LDA oprx16,SP SP2 9ED6 ee ff 5 LDA oprx8,SP SP1 9EE6 ff 4 LDHX #opr16i IMM 45 jj kk 3 LDHX opr8a DIR 55 dd 4 LDHX opr16a EXT 32 hh ll 5 LDHX ,X LoadIndexRegister(H:X) H:X← (M:M+ 0x0001) 0 – – ↕ ↕ – IX 9EAE 5 from Memory LDHX oprx16,X IX2 9EBE ee ff 6 LDHX oprx8,X IX1 9ECE ff 5 LDHX oprx8,SP SP1 9EFE ff 5 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 119

Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 5 of 7) Effect 1s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B LDX #opr8i IMM AE ii 2 LDX opr8a DIR BE dd 3 LDX opr16a EXT CE hh ll 4 LDX oprx16,X Load X (Index Register X← (M) 0 – – ↕ ↕ – IX2 DE ee ff 4 LDX oprx8,X Low) from Memory IX1 EE ff 3 LDX ,X IX FE 3 LDX oprx16,SP SP2 9EDE ee ff 5 LDX oprx8,SP SP1 9EEE ff 4 LSL opr8a DIR 38 dd 5 LSLA INH 48 1 LSLX Logical Shift Left C 0 ↕ – – ↕ ↕ ↕ INH 58 1 LSL oprx8,X (Same as ASL) IX1 68 ff 5 b7 b0 LSL ,X IX 78 4 LSL oprx8,SP SP1 9E68 ff 6 LSR opr8a DIR 34 dd 5 LSRA INH 44 1 LSRX Logical Shift Right 0 C ↕ – – 0 ↕ ↕ INH 54 1 LSR oprx8,X IX1 64 ff 5 b7 b0 LSR ,X IX 74 4 LSR oprx8,SP SP1 9E64 ff 6 MOVopr8a,opr8a (M) ←(M) DIR/DIR 4E dd dd 5 destination source MMOOVV #ooppr8r8ai,,Xo+pr8a Move H:X← (H:X) + 0x0001 in 0 – – ↕ ↕ – DIMIRM//IDXI+R 56EE diid dd 54 MOV ,X+,opr8a IX+/DIR and DIR/IX+ Modes IX+/DIR 7E dd 5 MUL Unsigned multiply X:A← (X)× (A) – 0 – – – 0 INH 42 5 NEG opr8a M← – (M) = 0x00 – (M) DIR 30 dd 5 NEGA A← – (A) = 0x00 – (A) INH 40 1 NNEEGGXoprx8,X N(Tewgoa’tse Complement) MX←← –– ((MX)) == 00xx0000 –– ((XM)) – – ↕ ↕ ↕ IINX1H 5600 ff 15 NEG ,X M← – (M) = 0x00 – (M) IX 70 4 NEG oprx8,SP M← – (M) = 0x00 – (M) SP1 9E60 ff 6 NOP No Operation Uses 1 Bus Cycle – – – – – – INH 9D 1 NSA Nibble Swap A← (A[3:0]:A[7:4]) – – – – – – INH 62 1 Accumulator ORA #opr8i IMM AA ii 2 ORA opr8a DIR BA dd 3 ORA opr16a EXT CA hh ll 4 ORA oprx16,X InclusiveORAccumulator A← (A) | (M) 0 – – ↕ ↕ – IX2 DA ee ff 4 ORA oprx8,X andMemory IX1 EA ff 3 ORA ,X IX FA 3 ORA oprx16,SP SP2 9EDA ee ff 5 ORA oprx8,SP SP1 9EEA ff 4 PSHA Push Accumulator onto Push (A); SP←(SP) – 0x0001 – – – – – – INH 87 2 Stack PSHH Push H (Index Register Push (H); SP←(SP) –0x0001 – – – – – – INH 8B 2 High) onto Stack PSHX Push X (Index Register Push (X);SP←(SP) –0x0001 – – – – – – INH 89 2 Low) onto Stack PULA Pull Accumulator from SP←(SP +0x0001); Pull (A) – – – – – – INH 86 3 Stack PULH Pull H (Index Register SP←(SP +0x0001); Pull (H) – – – – – – INH 8A 3 High) from Stack PULX Pull X (Index Register SP←(SP +0x0001); Pull (X) – – – – – – INH 88 3 Low) from Stack ROL opr8a DIR 39 dd 5 ROLA INH 49 1 ROLX RotateLeftthroughCarry C ↕ – – ↕ ↕ ↕ INH 59 1 ROL oprx8,X IX1 69 ff 5 ROL ,X b7 b0 IX 79 4 ROL oprx8,SP SP1 9E69 ff 6 MC9S08GT16A/GT8A Data Sheet, Rev. 1 120 Freescale Semiconductor

Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 6 of 7) Effect 1s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B ROR opr8a DIR 36 dd 5 RORA INH 46 1 RORX Rotate Right through C ↕ – – ↕ ↕ ↕ INH 56 1 ROR oprx8,X Carry IX1 66 ff 5 ROR ,X b7 b0 IX 76 4 ROR oprx8,SP SP1 9E66 ff 6 SP← 0xFF RSP Reset Stack Pointer – – – – – – INH 9C 1 (High Byte Not Affected) SP← (SP) + 0x0001; Pull (CCR) SP← (SP) + 0x0001; Pull (A) RTI Return from Interrupt SP← (SP) + 0x0001; Pull (X) ↕ ↕ ↕ ↕ ↕ ↕ INH 80 9 SP← (SP) + 0x0001; Pull (PCH) SP← (SP) + 0x0001; Pull (PCL) SP← SP + 0x0001;Pull (PCH) RTS Return from Subroutine SP← SP + 0x0001; Pull (PCL) – – – – – – INH 81 6 SBC #opr8i IMM A2 ii 2 SBC opr8a DIR B2 dd 3 SBC opr16a EXT C2 hh ll 4 SBC oprx16,X Subtract with Carry A← (A) – (M) – (C) ↕ – – ↕ ↕ ↕ IX2 D2 ee ff 4 SBC oprx8,X IX1 E2 ff 3 SBC ,X IX F2 3 SBC oprx16,SP SP2 9ED2 ee ff 5 SBC oprx8,SP SP1 9EE2 ff 4 SEC Set Carry Bit C← 1 – – – – – 1 INH 99 1 SEI Set Interrupt Mask Bit I← 1 – – 1 – – – INH 9B 1 STA opr8a DIR B7 dd 3 STA opr16a EXT C7 hh ll 4 STA oprx16,X IX2 D7 ee ff 4 STA oprx8,X Store Accumulator in M←(A) 0 – – ↕ ↕ – IX1 E7 ff 3 Memory STA ,X IX F7 2 STA oprx16,SP SP2 9ED7 ee ff 5 STA oprx8,SP SP1 9EE7 ff 4 STHXopr8a DIR 35 dd 4 STHXopr16a Store H:X (Index Reg.) (M:M + 0x0001)← (H:X) 0 – – ↕ ↕ – EXT 96 hh ll 5 STHXoprx8,SP SP1 9EFF ff 5 Enable Interrupts: STOP Stop Processing I bit← 0; Stop Processing – – 0 – – – INH 8E 2+ Refer to MCU Documentation STX opr8a DIR BF dd 3 STX opr16a EXT CF hh ll 4 STX oprx16,X Store X (Low 8 Bits of IX2 DF ee ff 4 STX oprx8,X Index Register) M←(X) 0 – – ↕ ↕ – IX1 EF ff 3 STX ,X in Memory IX FF 2 STX oprx16,SP SP2 9EDF ee ff 5 STX oprx8,SP SP1 9EEF ff 4 SUB #opr8i IMM A0 ii 2 SUB opr8a DIR B0 dd 3 SUB opr16a EXT C0 hh ll 4 SUB oprx16,X Subtract A← (A)– (M) ↕ – – ↕ ↕ ↕ IX2 D0 ee ff 4 SUB oprx8,X IX1 E0 ff 3 SUB ,X IX F0 3 SUB oprx16,SP SP2 9ED0 ee ff 5 SUB oprx8,SP SP1 9EE0 ff 4 PC← (PC) + 0x0001 Push (PCL); SP← (SP) – 0x0001 Push (PCH); SP← (SP) – 0x0001 Push (X); SP← (SP) – 0x0001 SWI Software Interrupt Push (A); SP← (SP) – 0x0001 – – 1 – – – INH 83 11 Push (CCR); SP← (SP) – 0x0001 I← 1; PCH← Interrupt Vector High Byte PCL← Interrupt Vector Low Byte MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 121

Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 7 of 7) Effect 1s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B TAP Transfer Accumulator to CCR← (A) ↕ ↕ ↕ ↕ ↕ ↕ INH 84 1 CCR TAX Transfer Accumulator to X← (A) – – – – – – INH 97 1 X (Index Register Low) TPA Transfer CCR to A← (CCR) – – – – – – INH 85 1 Accumulator TST opr8a (M) – 0x00 DIR 3D dd 4 TSTA (A) – 0x00 INH 4D 1 TSTX Test for Negative or Zero (X) – 0x00 0 – – ↕ ↕ – INH 5D 1 TST oprx8,X (M) – 0x00 IX1 6D ff 4 TST ,X (M) – 0x00 IX 7D 3 TST oprx8,SP (M) – 0x00 SP1 9E6D ff 5 TSX TransferSPtoIndexReg. H:X← (SP) + 0x0001 – – – – – – INH 95 2 TXA Transfer X (Index Reg. A← (X) – – – – – – INH 9F 1 Low) to Accumulator TXS TransferIndexReg.toSP SP← (H:X) – 0x0001 – – – – – – INH 94 2 WAIT Enable Interrupts; Wait I bit← 0; Halt CPU – – 0 – – – INH 8F 2+ for Interrupt 1 Bus clock frequency is one-half of the CPU clock frequency. MC9S08GT16A/GT8A Data Sheet, Rev. 1 122 Freescale Semiconductor

Central Processor Unit (S08CPUV2) Table8-3. Opcode Map (Sheet 1 of 2) Bit-Manipulation Branch Read-Modify-Write Control Register/Memory 00 5 10 5 20 3 30 5 40 1 50 1 60 5 70 4 80 9 90 3 A0 2 B0 3 C0 4 D0 4 E0 3 F0 3 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI BGE SUB SUB SUB SUB SUB SUB 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 01 5 11 5 21 3 31 5 41 4 51 4 61 5 71 5 81 6 91 3 A1 2 B1 3 C1 4 D1 4 E1 3 F1 3 BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ RTS BLT CMP CMP CMP CMP CMP CMP 3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 02 5 12 5 22 3 32 5 42 5 52 6 62 1 72 1 82 5+ 92 3 A2 2 B2 3 C2 4 D2 4 E2 3 F2 3 BRSET1 BSET1 BHI LDHX MUL DIV NSA DAA BGND BGT SBC SBC SBC SBC SBC SBC 3 DIR 2 DIR 2 REL 3 EXT 1 INH 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 03 5 13 5 23 3 33 5 43 1 53 1 63 5 73 4 83 11 93 3 A3 2 B3 3 C3 4 D3 4 E3 3 F3 3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI BLE CPX CPX CPX CPX CPX CPX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 04 5 14 5 24 3 34 5 44 1 54 1 64 5 74 4 84 1 94 2 A4 2 B4 3 C4 4 D4 4 E4 3 F4 3 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR TAP TXS AND AND AND AND AND AND 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 05 5 15 5 25 3 35 4 45 3 55 4 65 3 75 5 85 1 95 2 A5 2 B5 3 C5 4 D5 4 E5 3 F5 3 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT 3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 06 5 16 5 26 3 36 5 46 1 56 1 66 5 76 4 86 3 96 5 A6 2 B6 3 C6 4 D6 4 E6 3 F6 3 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR PULA STHX LDA LDA LDA LDA LDA LDA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 3 EXT 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 07 5 17 5 27 3 37 5 47 1 57 1 67 5 77 4 87 2 97 1 A7 2 B7 3 C7 4 D7 4 E7 3 F7 2 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR PSHA TAX AIS STA STA STA STA STA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 08 5 18 5 28 3 38 5 48 1 58 1 68 5 78 4 88 3 98 1 A8 2 B8 3 C8 4 D8 4 E8 3 F8 3 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 09 5 19 5 29 3 39 5 49 1 59 1 69 5 79 4 89 2 99 1 A9 2 B9 3 C9 4 D9 4 E9 3 F9 3 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0A 5 1A 5 2A 3 3A 5 4A 1 5A 1 6A 5 7A 4 8A 3 9A 1 AA 2 BA 3 CA 4 DA 4 EA 3 FA 3 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC PULH CLI ORA ORA ORA ORA ORA ORA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0B 5 1B 5 2B 3 3B 7 4B 4 5B 4 6B 7 7B 6 8B 2 9B 1 AB 2 BB 3 CB 4 DB 4 EB 3 FB 3 BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD 3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 INH 3 IX1 2 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0C 5 1C 5 2C 3 3C 5 4C 1 5C 1 6C 5 7C 4 8C 1 9C 1 BC 3 CC 4 DC 4 EC 3 FC 3 BRSET6 BSET6 BMC INC INCA INCX INC INC CLRH RSP JMP JMP JMP JMP JMP 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0D 5 1D 5 2D 3 3D 4 4D 1 5D 1 6D 4 7D 3 9D 1 AD 5 BD 5 CD 6 DD 6 ED 5 FD 5 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0E 5 1E 5 2E 3 3E 6 4E 5 5E 5 6E 4 7E 5 8E 2+ 9E AE 2 BE 3 CE 4 DE 4 EE 3 FE 3 BRSET7 BSET7 BIL CPHX MOV MOV MOV MOV STOP Page 2 LDX LDX LDX LDX LDX LDX 3 DIR 2 DIR 2 REL 3 EXT 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0F 5 1F 5 2F 3 3F 5 4F 1 5F 1 6F 5 7F 4 8F 2+ 9F 1 AF 2 BF 3 CF 4 DF 4 EF 3 FF 2 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA AIX STX STX STX STX STX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Opcode in Hexadecimal F0 3 HCS08 Cycles SUB Instruction Mnemonic Number of Bytes 1 IX Addressing Mode MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 123

Central Processor Unit (S08CPUV2) Table8-3. Opcode Map (Sheet 2 of 2) Bit-Manipulation Branch Read-Modify-Write Control Register/Memory 9E60 6 9ED0 5 9EE0 4 NEG SUB SUB 3 SP1 4 SP2 3 SP1 9E61 6 9ED1 5 9EE1 4 CBEQ CMP CMP 4 SP1 4 SP2 3 SP1 9ED2 5 9EE2 4 SBC SBC 4 SP2 3 SP1 9E63 6 9ED3 5 9EE3 4 9EF3 6 COM CPX CPX CPHX 3 SP1 4 SP2 3 SP1 3 SP1 9E64 6 9ED4 5 9EE4 4 LSR AND AND 3 SP1 4 SP2 3 SP1 9ED5 5 9EE5 4 BIT BIT 4 SP2 3 SP1 9E66 6 9ED6 5 9EE6 4 ROR LDA LDA 3 SP1 4 SP2 3 SP1 9E67 6 9ED7 5 9EE7 4 ASR STA STA 3 SP1 4 SP2 3 SP1 9E68 6 9ED8 5 9EE8 4 LSL EOR EOR 3 SP1 4 SP2 3 SP1 9E69 6 9ED9 5 9EE9 4 ROL ADC ADC 3 SP1 4 SP2 3 SP1 9E6A 6 9EDA 5 9EEA 4 DEC ORA ORA 3 SP1 4 SP2 3 SP1 9E6B 8 9EDB 5 9EEB 4 DBNZ ADD ADD 4 SP1 4 SP2 3 SP1 9E6C 6 INC 3 SP1 9E6D 5 TST 3 SP1 9EAE 5 9EBE 6 9ECE 5 9EDE 5 9EEE 4 9EFE 5 LDHX LDHX LDHX LDX LDX LDHX 2 IX 4 IX2 3 IX1 4 SP2 3 SP1 3 SP1 9E6F 6 9EDF 5 9EEF 4 9EFF 5 CLR STX STX STHX 3 SP1 4 SP2 3 SP1 3 SP1 INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Prebyte (9E) and Opcode in Hexadecimal 9E60 6 HCS08 Cycles NEG Instruction Mnemonic Number of Bytes 3 SP1 Addressing Mode MC9S08GT16A/GT8A Data Sheet, Rev. 1 124 Freescale Semiconductor

Chapter 9 Internal Clock Generator (S08ICGV4) 9.1 Introduction The MC9S08GT16A/GT8A microcontroller provides one internal clock generation (ICG) module to create the system bus frequency. All functions described in this section are available on the MC9S08GT16A/GT8A microcontroller. The EXTAL and XTAL pins share port G bits 2 and 1, respectively. Analog supply lines V and V are internally derived from the MCU’s V and V DDA SSA DD SS pins. Electrical parametric data for the ICG may be found in AppendixA, “Electrical Characteristics.” SYSTEM CONTROL TPM1 TPM2 IIC1 SCI1 SCI2 SPI1 LOGIC ICGERCLK RTI FFE ÷ 2 ICG FIXED FREQ CLOCK (XCLK) ICGOUT ÷ BUSCLK 2 ICGLCLK* CPU BDC COP ATD1 RAM FLASH ATD has min and max FLASH has frequency frequency requirements. See requirements for program * ICGLCLK is the alternate BDC clock source for the MC9S08GT16A/GT8A. Chapter14,“Analog-to-DigitalConvert- and erase operation. er (S08ATDV3),” andAppendixA, SeeAppendixA, “Electrical “Electrical Characteristics.” Characteristics.” Figure9-1. System Clock Distribution Diagram NOTE Freescale Semiconductor programs a factory trim value for ICGTRM into the FLASH location $FFBE (NVICGTRM). Leaving this address for the ICGTRM value also allows debugger and programmer vendors to perform a manual trim operation and store the resultant ICGTRM value into NVICGTRM for users to access at a later time. The value in NVICGTRM isnotautomaticallyloadedandthereforemustbecopiedintoICGTTRMby user code. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 125

Internal Clock Generator (S08ICGV4) VREFLVREFHVSSADVDDAD 4 HCS08 CORE BKGD 8IN-BTIETR KREUYPBTO (AKRBDI) 8 PORT A 4 PPPTTTAAA347///KKKBBBIIIPPP347–– NOTE 6 PTA0/KBIP0 CPU BDC 4 10-BIT 8 T B PPTTBB74//AADDPP74– ANALOG-TO-DIGITAL OR 4 HCS08 SYSTEM CONTROL CONVERTER (ATD) P PTB3/ADP3– RESET PTB0/ADP0 NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION PTC7 POWER MANAGEMENT PTC6 PTC5 RTI COP INTER-IC (IIC) SSDCAL PORT C PPPTTTCCC432//SSCDAL NOTE 5 IRQ IRQ LVD RXD2 NOTES 2, 3 SERIAL COMMUNICATIONS PTC1/RxD2 TXD2 INTERFACE (SCI2) PTC0/TxD2 CH1 USER FLASH 2-CHANNEL TIMER/PWM PTD4/TPM2CH1 CH0 (GT16A = 16,384 BYTES) (TPM2) PTD3/TPM2CLK/TPM2CH0 (GT8A = 8192 BYTES) D CH0 RT O PTD2/TPM1CH2 3-CHANNEL TIMER/PWM CH1 P PTD1/TPM1CH1 (TPM1) CH2 PTD0/TPM1CLK/TPM1CH0 USER RAM (GT16A = 2048 BYTES) SPSCK (GT8A = 1024 BYTES) PTE5/SPSCK MOSI SERIAL PERIPHERAL PTE4/MOSI MISO ON-CHIP ICE INTERFACE (SPI) SS RT E PPTTEE32//SMSISO DEBUG O RXD1 P MODULE (DBG) SERIAL COMMUNICATIONS PTE1/RxD1 TXD1 INTERFACE (SCI1) PTE0/TxD1 INTERNAL CLOCK GENERATOR (ICG) PTG3 EXTAL G PTG2/EXTAL XTAL T LOW-POWER OSCILLATOR R PTG1/XTAL BKGD O P PTG0/BKGD/MS V DD VOLTAGE V SS REGULATOR = Pins not available in 44-, 42-, or 32-pin packages V SS = Pins not available in 42- or 32-pin packages = Pins not available in 32-pin packages NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE=1). 3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD. 4. Pin contains integrated pullup device. 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1). Figure9-2. Block Diagram Highlighting ICG Module MC9S08GT16A/GT8A Data Sheet, Rev. 1 126 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) The ICG provides multiple options for clock sources. This offers a user great flexibility when making choices between cost, precision, current draw, and performance. The ICG consists of four functional blocks. Each of these is briefly described here and then in more detail in a later section. • Oscillator block — The oscillator block provides means for connecting an external crystal or resonator. Two frequency ranges are software selectable to allow optimal startup and stability. Alternatively,theoscillatorblockcanbeusedtorouteanexternalsquarewavetothesystemclock. External sources can provide a very precise clock source. The oscillator is capable of being configured for low power mode or high amplitude mode as selected by HGO. • Internalreferencegenerator—Theinternalreferencegeneratorconsistsoftwocontrolledclock sources. One is designed to be approximately 8 MHz and can be selected as a local clock for the background debug controller. The other internal reference clock source is typically 243 kHz and can be trimmed for finer accuracy via software when a precise timed event is input to the MCU. This provides a highly reliable, low-cost clock source. • Frequency-locked loop — A frequency-locked loop (FLL) stage takes either the internal or externalclocksourceandmultipliesittoahigherfrequency.Statusbitsprovideinformationwhen thecircuithasachievedlockandwhenitfallsoutoflock.Additionally,thisblockcanmonitorthe external reference clock and signals whether the clock is valid or not. • Clock select block — The clock select block provides several switch options for connecting different clock sources to the system clock tree. ICGDCLK is the multiplied clock frequency out oftheFLL,ICGERCLKisthereferenceclockfrequencyfromthecrystalorexternalclocksource, and FFE (fixed frequency enable) is a control signal used to control the system fixed frequency clock (XCLK). ICGLCLK is the clock source for the background debug controller (BDC). 9.1.1 Features Themoduleisintendedtobeveryuserfriendlywithmanyofthefeaturesoccurringautomaticallywithout user intervention. To quickly configure the module, go toSection9.5, “Initialization/Application Information” and pick an example that best suits the application needs. Features of the ICG and clock distribution system: • Severaloptionsfortheprimaryclocksourceallowawiderangeofcost,frequency,andprecision choices: — 32kHz–100 kHz crystal or resonator — 1MHz–16MHz crystal or resonator — External clock — Internal reference generator • Defaults to self-clocked modeto minimize startup delays • Frequency-locked loop (FLL) generates 8 MHz to 40MHz (for bus rates up to 20 MHz) — Uses external or internal clock as reference frequency • Automatic lockout of non-running clock sources • Reset or interrupt on loss of clock or loss of FLL lock MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 127

Internal Clock Generator (S08ICGV4) • Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast frequency lock when recovering from stop3 mode • DCO will maintain operating frequency during a loss or removal of reference clock • Post-FLL divider selects 1 of 8 bus rate divisors (/1 through /128) • Separate self-clocked source for real-time interrupt • Trimmable internal clock source supports SCI communications without additional external components • Automatic FLL engagement after lock is acquired • External oscillator selectable for low power or high gain 9.1.2 Modes of Operation This is a high-level description only. Detailed descriptions of operating modes are contained in Section9.4, “Functional Description.” • Mode 1 — Off The output clock, ICGOUT, is static. This mode may be entered when the STOP instruction is executed. • Mode 2 — Self-clocked (SCM) Defaultmodeofoperationthatisenteredimmediatelyafterreset.TheICG’sFLLisopenloopand the digitally controlled oscillator (DCO) is free running at a frequency set by the filter bits. • Mode 3 — FLL engaged internal (FEI) In this mode, the ICG’s FLL is used to create frequencies that are programmable multiples of the internal reference clock. — FLLengagedinternalunlockedisatransitionstatethatoccurswhiletheFLLisattemptingto lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. — FLLengagedinternallockedisastatethatoccurswhentheFLLdetectsthattheDCOislocked to a multiple of the internal reference. • Mode 4 — FLL bypassed external (FBE) Inthismode,theICGisconfiguredtobypasstheFLLanduseanexternalclockastheclocksource. • Mode 5 — FLL engaged external (FEE) The ICG’s FLL is used to generate frequencies that are programmable multiples of the external clock reference. — FLLengagedexternalunlockedisatransitionstatethatoccurswhiletheFLLisattemptingto lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. — FLL engaged external locked is a state which occurs when the FLL detects that the DCO is locked to a multiple of the internal reference. MC9S08GT16A/GT8A Data Sheet, Rev. 1 128 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) 9.1.3 Block Diagram Figure9-3 is a top-level diagram that shows the functional organization of the internal clock generation (ICG) module. This section includes a general description and a feature list. EXTAL ICG OSCILLATOR (OSC) CLOCK WITH EXTERNAL REF SELECT SELECT ICGERCLK OUTPUT XTAL ICGDCLK CLOCK /R FREQUENCY DCO SELECT ICGOUT LOCKED REF LOOP (FLL) SELECT V DDA (SEE NOTE 2) LOSS OF LOCK AND CLOCK DETECTOR V SSA FIXED (SEE NOTE 2) CLOCK SELECT FFE IRG ICGIRCLK TYP 243 kHz INTERNAL REFERENCE 8 MHz GENERATORS RG LOCAL CLOCK FOR OPTIONAL USE WITH BDC ICGLCLK NOTES: 1. See chip level clock routing diagram for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK 2. Not all HCS08 microcontrollers have unique supply pins for the ICG. See the device pin assignments. Figure9-3. ICG Block Diagram 9.2 External Signal Description TheoscillatorpinsareusedtoprovideanexternalclocksourcefortheMCU.Theoscillatorpinsaregain controlled in low-power mode (default). Oscillator amplitudes in low-power mode are limited to approximately 1 V, peak-to-peak. 9.2.1 EXTAL — External Reference Clock / Oscillator Input IfuponthefirstwritetoICGC1,eithertheFEEmodeorFBEmodeisselected,thispinfunctionsaseither theexternalclockinputortheinputoftheoscillatorcircuitasdeterminedbyREFS.Ifuponthefirstwrite to ICGC1, either the FEI mode or SCM mode is selected, this pin is not used by the ICG. 9.2.2 XTAL — Oscillator Output If upon the first write to ICGC1, either the FEE mode or FBE mode is selected, this pin functions as the output of the oscillator circuit. If upon the first write to ICGC1, either the FEI mode or SCM mode is MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 129

Internal Clock Generator (S08ICGV4) selected,thispinisnotusedbytheICG.Theoscillatoriscapableofbeingconfiguredtoprovideahigher amplitude output for improved noise immunity. This mode of operation is selected by HGO = 1. 9.2.3 External Clock Connections If an external clock is used, then the pins are connected as shownFigure 9-4. ICG EXTAL V XTAL SS NOT CONNECTED CLOCK INPUT Figure9-4. External Clock Connections 9.2.4 External Crystal/Resonator Connections If an external crystal/resonator frequency reference is used, then the pins are connected as shown in Figure9-5. Recommended component values are listed in the Electrical Characteristics chapter. ICG EXTAL V XTAL SS R S C C 1 2 R F CRYSTAL OR RESONATOR Figure9-5. External Frequency Reference Connection MC9S08GT16A/GT8A Data Sheet, Rev. 1 130 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) 9.3 Register Definition Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignments for all ICG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 9.3.1 ICG Control Register 1 (ICGC1) 7 6 5 4 3 2 1 0 R 0 HGO1 RANGE REFS CLKS OSCSTEN LOCD W Reset 0 1 0 0 0 1 0 0 = Unimplemented or Reserved Figure9-6. ICG Control Register 1 (ICGC1) 1 This bit can be written only once after reset. Additional writes are ignored. Table9-1. ICGC1 Register Field Descriptions Field Description 7 High Gain Oscillator Select — The HGO bit is used to select between low power operation and high gain HGO operation for improved noise immunity. This bit is write-once after reset. 0 Oscillator configured for low power operation. 1 Oscillator configured for high gain operation. 6 Frequency Range Select — The RANGE bit controls the oscillator, reference divider, and FLL loop prescaler RANGE multiplication factor (P). It selects one of two reference frequency ranges for the ICG. The RANGE bit is write-onceafterareset.TheRANGEbitonlyhasaneffectinFLLengagedexternalandFLLbypassedexternal modes. 0 Oscillator configured for low frequency range. FLL loop prescale factor P is 64. 1 Oscillator configured for high frequency range. FLL loop prescale factor P is 1. 5 External Reference Select — The REFS bit controls the external reference clock source for ICGERCLK. The REFS REFS bit is write-once after a reset. 0 External clock requested. 1 Oscillator using crystal or resonator requested. 4:3 Clock Mode Select — The CLKS bits control the clock mode as described below. If FLL bypassed external is CLKS requested, it will not be selected until ERCS=1. If the ICG enters off mode, the CLKS bits will remain unchanged.Writes to the CLKS bits will not take effect if a previous write is not complete. 00 Self-clocked 01 FLL engaged, internal reference 10 FLL bypassed, external reference 11 FLL engaged, external reference TheCLKSbitsarewritableatanytime,unlessthefirstwriteafteraresetwasCLKS=0X,theCLKSbitscannot be written to 1X until after the next reset (because the EXTAL pin was not reserved). MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 131

Internal Clock Generator (S08ICGV4) Table9-1. ICGC1 Register Field Descriptions (continued) Field Description 2 Enable Oscillator in Off Mode — The OSCSTEN bit controls whether or not the oscillator circuit remains OSCSTEN enabled when the ICG enters off mode. This bit has no effect if HGO = 1 and RANGE = 1. 0 Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS=10, and REFST=1. 1 Oscillator enabled when ICG is in off mode, CLKS=1X and REFST=1. 1 Loss of Clock Disable LOCD 0 Loss of clock detection enabled. 1 Loss of clock detection disabled. MC9S08GT16A/GT8A Data Sheet, Rev. 1 132 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) 9.3.2 ICG Control Register 2 (ICGC2) 7 6 5 4 3 2 1 0 R LOLRE MFD LOCRE RFD W Reset 0 0 0 0 0 0 0 0 Figure9-7. ICG Control Register 2 (ICGC2) Table9-2. ICGC2 Register Field Descriptions Field Description 7 LossofLockResetEnable—TheLOLREbitdetermineswhattypeofrequestismadebytheICGfollowinga LOLRE loss of lock indication. The LOLRE bit only has an effect when LOLS is set. 0 Generate an interrupt request on loss of lock. 1 Generate a reset request on loss of lock. 6:4 MultiplicationFactor—TheMFDbitscontroltheprogrammablemultiplicationfactorintheFLLloop.Thevalue MFD specified by the MFD bits establishes the multiplication factor (N) applied to the reference frequency. Writes to the MFD bits will not take effect if a previous write is not complete. Select a low enough value for N such that f does not exceed its maximum specified value. ICGDCLK 000 Multiplication factor = 4 001 Multiplication factor = 6 010 Multiplication factor = 8 011 Multiplication factor = 10 100 Multiplication factor = 12 101 Multiplication factor = 14 110 Multiplication factor = 16 111 Multiplication factor = 18 3 LossofClockResetEnable—TheLOCREbitdetermineshowthesystemmanagesalossofclockcondition. LOCRE 0 Generate an interrupt request on loss of clock. 1 Generate a reset request on loss of clock. 2:0 ReducedFrequencyDivider—TheRFDbitscontrolthevalueofthedividerfollowingtheclockselectcircuitry. RFD ThevaluespecifiedbytheRFDbitsestablishesthedivisionfactor(R)appliedtotheselectedoutputclocksource. Writes to the RFD bits will not take effect if a previous write is not complete. 000 Division factor = 1 001 Division factor = 2 010 Division factor = 4 011 Division factor = 8 100 Division factor = 16 101 Division factor = 32 110 Division factor = 64 111 Division factor = 128 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 133

Internal Clock Generator (S08ICGV4) 9.3.3 ICG Status Register 1 (ICGS1) 7 6 5 4 3 2 1 0 R CLKST REFST LOLS LOCK LOCS ERCS ICGIF W 1 Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure9-8. ICG Status Register 1 (ICGS1) Table9-3. ICGS1 Register Field Descriptions Field Description 7:6 Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update CLKST immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Self-clocked 01 FLL engaged, internal reference 10 FLL bypassed, external reference 11 FLL engaged, external reference 5 Reference Clock Status — The REFST bit indicates which clock reference is currently selected by the REFST Reference Select circuit. 0 External Clock selected. 1 Crystal/Resonator selected. 4 FLL Loss of Lock Status — The LOLS bit is an indication of FLL lock status. LOLS 0 FLL has not unexpectedly lost lock since LOLS was last cleared. 1 FLL has unexpectedly lost lock since LOLS was last cleared, LOLRE determines action taken. 3 FLLLockStatus—TheLOCKbitindicateswhethertheFLLhasacquiredlock.TheLOCKbitisclearedinoff, LOCK self-clocked, and FLL bypassed modes. 0 FLL is currently unlocked. 1 FLL is currently locked. 2 Loss Of Clock Status — The LOCS bit is an indication of ICG loss of clock status. LOCS 0 ICG has not lost clock since LOCS was last cleared. 1 ICG has lost clock since LOCS was last cleared, LOCRE determines action taken. 1 External Reference Clock Status — The ERCS bit is an indication of whether or not the external reference ERCS clock (ICGERCLK) meets the minimum frequency requirement. 0 External reference clock is not stable, frequency requirement is not met. 1 External reference clock is stable, frequency requirement is met. 0 ICGInterruptFlag—TheICGIFread/writeflagissetwhenanICGinterruptrequestispending.Itisclearedby ICGIF aresetorbyreadingtheICGstatusregisterwhenICGIFissetandthenwritingalogic1toICGIF.IfanotherICG interruptoccursbeforetheclearingsequenceiscomplete,thesequenceisresetsoICGIFwouldremainsetafter the clear sequence was completed for the earlier interrupt. Writing a logic 0 to ICGIF has no effect. 0 No ICG interrupt request is pending. 1 An ICG interrupt request is pending. MC9S08GT16A/GT8A Data Sheet, Rev. 1 134 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) 9.3.4 ICG Status Register 2 (ICGS2) 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 DCOS W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure9-9. ICG Status Register 2 (ICGS2) Table9-4. ICGS2 Register Field Descriptions Field Description 0 DCOClockStable—TheDCOSbitissetwhentheDCOclock(ICG2DCLK)isstable,meaningthecounterror DCOS has not changed by more than n for two consecutive samples and the DCO clock is not static. This bit is unlock usedwhenexitingoffstateifCLKS=X1todeterminewhentoswitchtotherequestedclockmode.Itisalsoused inself-clockedmodetodeterminewhentostartmonitoringtheDCOclock.Thisbitiscleareduponenteringthe off state. 0 DCO clock is unstable. 1 DCO clock is stable. 9.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL) 7 6 5 4 3 2 1 0 R 0 0 0 0 FLT W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure9-10. ICG Upper Filter Register (ICGFLTU) Table9-5. ICGFLTU Register Field Descriptions Field Description 3:0 FilterValue—TheFLTbitsindicatethecurrentfiltervalue,whichcontrolstheDCOfrequency.TheFLTbitsare FLT readonlyexceptwhentheCLKSbitsareprogrammedtoself-clockedmode(CLKS=00).Inself-clockedmode, anywritetoICGFLTUupdatesthecurrent12-bitfiltervalue.WritestotheICGFLTUregisterwillnotaffectFLTif a previous latch sequence is not complete. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 135

Internal Clock Generator (S08ICGV4) 7 6 5 4 3 2 1 0 R FLT W Reset 1 1 0 0 0 0 0 0 Figure9-11. ICG Lower Filter Register (ICGFLTL) Table9-6. ICGFLTL Register Field Descriptions Field Description 7:0 FilterValue—TheFLTbitsindicatethecurrentfiltervalue,whichcontrolstheDCOfrequency.TheFLTbitsare FLT readonlyexceptwhentheCLKSbitsareprogrammedtoself-clockedmode(CLKS=00).Inself-clockedmode, anywritetoICGFLTUupdatesthecurrent12-bitfiltervalue.WritestotheICGFLTUregisterwillnotaffectFLTif a previous latch sequence is not complete. The filter registers show the filter value (FLT). 9.3.6 ICG Trim Register (ICGTRM) 7 6 5 4 3 2 1 0 R TRIM W POR 1 0 0 0 0 0 0 0 Reset: U U U U U U U U U = Unaffected by MCU reset Figure9-12. ICG Trim Register (ICGTRM) Table9-7. ICGTRM Register Field Descriptions Field Description 7 ICG Trim Setting — The TRIM bits control the internal reference generator frequency. They allow a±25% TRIM adjustmentofthenominal(POR)period.Thebit’seffectonperiodisbinaryweighted(i.e.,bit1willadjusttwice asmuchaschangingbit0).IncreasingthebinaryvalueinTRIMwillincreasetheperiodanddecreasingthevalue will decrease the period. 9.4 Functional Description This section provides a functional description of each of the five operating modes of the ICG. Also discussedarethelossofclockandlossoflockerrorsandrequirementsforentryintoeachmode.TheICG is very flexible, and in some configurations, it is possible to exceed certain clock specifications. When usingtheFLL,configuretheICGsothatthefrequencyofICGDCLKdoesnotexceeditsmaximumvalue to ensure proper MCU operation. MC9S08GT16A/GT8A Data Sheet, Rev. 1 136 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) 9.4.1 Off Mode (Off) Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state. However there are two cases to consider when clock activity continues while the CPU is in stop mode, 9.4.1.1 BDM Active When the BDM is enabled, the ICG continues activity as originally programmed. This allows access to memory and control registers via the BDC controller. 9.4.1.2 OSCSTEN Bit Set Whentheoscillatorisenabledinstopmode(OSCSTEN= 1),theindividualclockgeneratorsareenabled but the clock feed to the rest of the MCU is turned off. This option is provided to avoid long oscillator startup times if necessary, or to run the RTI from the oscillator during stop3. 9.4.1.3 Stop/Off Mode Recovery UpontheCPUexitingstopmodeduetoaninterrupt,thepreviouslysetcontrolbitsarevalidandthesystem clockfeedresumes.IfFEEisselected,theICGwillsourcetheinternalreferenceuntiltheexternalclock isstable.IfFBEisselected,theICGwillwaitfortheexternalclocktostabilizebeforeenablingICGOUT. Upon the CPU exiting stop mode due to a reset, the previously set ICG control bits are ignored and the default reset values applied. Therefore the ICG will exit stop in SCM mode configured for an approximately8MHzDCOoutput(4MHzbusclock)withtrimvaluemaintained.Ifusingacrystal,4096 clocks are detected prior to engaging ICGERCLK. This is incorporated in crystal start-up time. 9.4.2 Self-Clocked Mode (SCM) Self-clocked mode (SCM) is the default mode of operation and is entered when any of the following conditions occur: • After any reset. • Exiting from off mode when CLKS does not equal 10. If CLKS =X1, the ICG enters this state temporarily until the DCO is stable (DCOS =1). • CLKS bits are written from X1 to 00. • CLKS= 1X and ICGERCLK is not detected (both ERCS = 0 and LOCS = 1). Inthisstate,theFLLloopisopen.TheDCOison,andtheoutputclocksignalICGOUTfrequencyisgiven byf /R.TheICGDCLKfrequencycanbevariedfrom8MHzto40MHzbywritinganewvalue ICGDCLK into the filter registers (ICGFLTH and ICGFLTL). This is the only mode in which the filter registers can be written. Ifthismodeisenteredduetoareset,f willdefaulttof whichisnominally8MHz.Ifthis ICGDCLK Self_reset modeisenteredfromFLLengagedinternal,f willmaintainthepreviousfrequency.Ifthismode ICGDCLK isenteredfromFLLengagedexternal(eitherbyprogrammingCLKSorduetoalossofexternalreference clock),f willmaintainthepreviousfrequency,butICGOUTwilldoubleiftheFLLwasunlocked. ICGDCLK If this mode is entered from off mode, f will be equal to the frequency of ICGDCLK before ICGDCLK MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 137

Internal Clock Generator (S08ICGV4) enteringoffmode.IfCLKSbitsaresetto01or11comingoutoftheOffstate,theICGentersthismode untilICGDCLKisstableasdeterminedbytheDCOSbit.AfterICGDCLKisconsideredstable,theICG automaticallyclosestheloopbyswitchingtoFLLengaged(internalorexternal)asselectedbytheCLKS bits. CLKST CLKS RFD REFERENCE ICGIRCLK CLOCK REDUCED ICGOUT DIVIDER (/7) SELECT FREQUENCY CIRCUIT DIVIDER (R) RANGE ICGDCLK FLT MFD DIGITAL DIGITALLY 1x SUBTRACTOR LOOP CONTROLLED FILTER OSCILLATOR 2x FLL ANALOG K CLKST L RC FREQUENCY- GE LOCKED C LOOP (FLL) I OVERFLOW PULSE ICG2DCLK COUNTER COUNTER ENABLE RANGE IRQ LOCK AND RESET AND LOSS OF CLOCK INTERRUPT RESET DETECTOR CONTROL DCOS LOCK LOLS LOCS ERCS LOCD ICGIF LOLRELOCRE Figure9-13. Detailed Frequency-Locked Loop Block Diagram 9.4.3 FLL Engaged, Internal Clock (FEI) Mode FLL engaged internal (FEI) is entered when any of the following conditions occur: • CLKS bits are written to 01 • The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01 In FLL engaged internal mode, the reference clock is derived from the internal reference clock ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. MC9S08GT16A/GT8A Data Sheet, Rev. 1 138 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) 9.4.4 FLL Engaged Internal Unlocked FEIunlockedisatemporarystatethatisenteredwhenFEIisenteredandthecounterror(∆n)outputfrom the subtractor is greater than the maximum n or less than the minimum n , as required by the unlock unlock lock detector to detect the unlock condition. TheICGwillremaininthisstatewhilethecounterror(∆n)isgreaterthanthemaximumn orlessthan lock the minimum n , as required by the lock detector to detect the lock condition. lock In this state the output clock signal ICGOUT frequency is given by f / R. ICGDCLK 9.4.5 FLL Engaged Internal Locked FLLengagedinternallockedisenteredfromFEIunlockedwhenthecounterror(∆n),whichcomesfrom the subtractor, is less than n (max) and greater than n (min) for a given number of samples, as lock lock required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is givenbyf /R.InFEIlocked,thefiltervalueisupdatedonlyonceeveryfourcomparisoncycles. ICGDCLK The update made is an average of the error measurements taken in the four previous comparisons. 9.4.6 FLL Bypassed, External Clock (FBE) Mode FLL bypassed external (FBE) is entered when any of the following conditions occur: • From SCM when CLKS= 10 and ERCS is high • When CLKS = 10, ERCS= 1 upon entering off mode, and off is then exited • FromFLLengagedexternalmodeifalossofDCOclockoccursandtheexternalreferenceremains valid (both LOCS= 1 and ERCS = 1) Inthisstate,theDCOandIRGareoffandthereferenceclockisderivedfromtheexternalreferenceclock, ICGERCLK.TheoutputclocksignalICGOUTfrequencyisgivenbyf /R.Ifanexternalclock ICGERCLK source is used (REFS =0), then the input frequency on the EXTAL pin can be anywhere in the range 0MHz to 40 MHz. If a crystal or resonator is used (REFS= 1), then frequency range is either low for RANGE = 0 or high for RANGE= 1. 9.4.7 FLL Engaged, External Clock (FEE) Mode The FLL engaged external (FEE) mode is entered when any of the following conditions occur: • CLKS= 11 and ERCS and DCOS are both high. • The DCO stabilizes (DCOS =1) while in SCM upon exiting the off state with CLKS = 11. InFEEmode,thereferenceclockisderivedfromtheexternalreferenceclockICGERCLK,andtheFLL loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To runinFEEmode,theremustbeaworking32kHz–100kHzor2MHz–10MHzexternalclocksource.The maximumexternalclockfrequencyislimitedto10MHzinFEEmodetopreventover-clockingtheDCO. TheminimummultiplierfortheFLL,fromTable9-12is4.Because4X10MHzis40MHz,whichisthe operational limit of the DCO, the reference clock cannot be any faster than 10 MHz. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 139

Internal Clock Generator (S08ICGV4) 9.4.7.1 FLL Engaged External Unlocked FEEunlockedisenteredwhenFEEisenteredandthecounterror(∆n)outputfromthesubtractorisgreater thanthemaximumn orlessthantheminimumn ,asrequiredbythelockdetectortodetectthe unlock unlock unlock condition. TheICGwillremaininthisstatewhilethecounterror(∆n)isgreaterthanthemaximumn orlessthan lock the minimum n , as required by the lock detector to detect the lock condition. lock In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to lock it according to their operational descriptions later in this section. Upon entering this state and until the FLL becomes locked, the output clock signal ICGOUT frequency is given by f / (2×R) This ICGDCLK extra divide by two prevents frequency overshoots during the initial locking process from exceeding chip-level maximum frequency specifications. After the FLL has locked, if an unexpected loss of lock causes it to re-enter the unlocked state while the ICG remains in FEE mode, the output clock signal ICGOUT frequency is given by f / R. ICGDCLK 9.4.7.2 FLL Engaged External Locked FEE locked is entered from FEE unlocked when the count error (∆n) is less than n (max) and greater lock than n (min) for a given number of samples, as required by the lock detector to detect the lock lock condition.TheoutputclocksignalICGOUTfrequencyisgivenbyf /R.InFLLengagedexternal ICGDCLK locked,thefiltervalueisupdatedonlyonceeveryfourcomparisoncycles.Theupdatemadeisanaverage of the error measurements taken in the four previous comparisons. 9.4.8 FLL Lock and Loss-of-Lock Detection TodeterminetheFLLlockedandloss-of-lockconditions,thepulsecountercountsthepulsesoftheDCO foronecomparisoncycle(seeTable 9-9forexplanationofacomparisoncycle)andpassesthisnumberto thesubtractor.ThesubtractorcomparesthisvaluetothevalueinMFDandproducesacounterror,∆n.To achievelockedstatus,∆nmustbebetweenn (min)andn (max).AftertheFLLhaslocked,∆nmust lock lock staybetweenn (min)andn (max)toremainlocked.If∆ngoesoutsidethisrangeunexpectedly, unlock unlock the LOLS status bit is set and remains set until cleared by software or until the MCU is reset. LOLS is cleared by reading ICGS1 then writing 1 to ICGIF (LOLRE = 0), or by a loss-of-lock induced reset (LOLRE = 1), or by any MCU reset. If the ICG enters the off state due to stop mode when ENBDM= OSCSTEN = 0, the FLL loses locked status (LOCK is cleared), but LOLS remains unchanged because this is not an unexpected loss-of-lock condition.Thoughitwouldbeunusual,ifENBDMisclearedto0whiletheMCUisinstop,theICGenters theoffstate.Becausethisisanunexpectedstoppingofclocks,LOLSwillbesetwhentheMCUwakesup from stop. Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the LOLS will not be set. MC9S08GT16A/GT8A Data Sheet, Rev. 1 140 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) 9.4.9 FLL Loss-of-Clock Detection ThereferenceclockandtheDCOclockaremonitoredunderdifferentconditions(seeTable9-8).Provided thereferencefrequencyisbeingmonitored,ERCS= 1indicatesthatthereferenceclockmeetsminimum frequencyrequirements.Whenthereferenceand/orDCOclock(s)arebeingmonitored,ifeitheronefalls belowacertainfrequency,f andf ,respectively,theLOCSstatusbitwillbesettoindicatetheerror. LOR LOD LOCS will remain set until it is acknowledged or until the MCU is reset. LOCS is cleared by reading ICGS1thenwriting1toICGIF(LOCRE=0),orbyaloss-of-clockinducedreset(LOCRE=1),orbyany MCU reset. IftheICGisinFEE,alossofreferenceclockcausestheICGtoenterSCM,andalossofDCOclockcauses the ICG to enter FBE mode. If the ICG is in FBE mode, a loss of reference clock will cause the ICG to enterSCM.Ineachcase,theCLKSTandCLKSbitswillbeautomaticallychangedtoreflectthenewstate. IftheICGisinFEEmodewhenalossofclockoccursandtheERCSisstillsetto1,thentheCLKSTbits are set to 10 and the ICG reverts to FBE mode. AlossofclockwillalsocausealossoflockwheninFEEorFEImodes.Becausethemethodofclearing theLOCSandLOLSbitsisthesame,thiswouldonlybeanissueintheunlikelycasethatLOLRE =1and LOCRE =0. In this case, the interrupt would be overridden by the reset for the loss of lock. Table9-8. Clock Monitoring (When LOCD = 0) ExternalReference DCO Clock Mode CLKS REFST ERCS Clock Monitored? Monitored? Off 0X or 11 X Forced Low No No 10 0 Forced Low No No 10 1 Real-Time1 Yes(1) No SCM 0X X Forced Low No Yes2 (CLKST=00) 10 0 Forced High No Yes(2) 10 1 Real-Time Yes Yes(2) 11 X Real-Time Yes Yes(2) FEI 0X X Forced Low No Yes (CLKST=01) 11 X Real-Time Yes Yes FBE 10 0 Forced High No No (CLKST=10) 10 1 Real-Time Yes No FEE 11 X Real-Time Yes Yes (CLKST=11) 1 If ENABLE is high (waiting for external crystal start-up after exiting stop). 2 DCO clock will not be monitored until DCOS=1 upon entering SCM from off or FLL bypassed external mode. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 141

Internal Clock Generator (S08ICGV4) 9.4.10 Clock Mode Requirements A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by CLKST1:CLKST0.Providedminimumconditionsaremet,thestatusshowninCLKST1:CLKST0should be the same as the requested mode in CLKS1:CLKS0. Table9-9 shows the relationship between CLKS, CLKST, and ICGOUT. It also shows the conditions for CLKS =CLKST or the reason CLKS≠ CLKST. NOTE If a crystal will be used before the next reset, then be sure to set REFS= 1 andCLKS =1xonthefirstwritetotheICGC1register.Failuretodosowill result in “locking” REFS =0 which will prevent the oscillator amplifier from being enabled until the next reset occurs. Table9-9. ICG State Table Actual Desired Reference Reason Comparison Conditions1for Mode Mode Range Frequency ICGOUT CLKS1≠ Cycle Time CLKS = CLKST (CLKST) (CLKS) (f ) CLKST REFERENCE Off X 0 — 0 — — Off (XX) (XX) FBE X 0 — 0 — ERCS = 0 (10) Not switching SCM (00) X fICGIRCLK/72 8/fICGIRCLK ICGDCLK/R from FBE to — SCM FEI SCM (01) 0 fICGIRCLK/7(1) 8/fICGIRCLK ICGDCLK/R — DCOS=0 (00) FBE (10) X fICGIRCLK/7(1) 8/fICGIRCLK ICGDCLK/R — ERCS=0 FEE DCOS=0or (11) X fICGIRCLK/7(1) 8/fICGIRCLK ICGDCLK/R — ERCS=0 FEI FEI (01) 0 fICGIRCLK/7 8/fICGIRCLK ICGDCLK/R DCOS=1 — (01) FEE (11) X fICGIRCLK/7 8/fICGIRCLK ICGDCLK/R — ERCS=0 FBE X 0 — ICGERCLK/R ERCS=1 — FBE (10) (10) FEE LOCS=1& X 0 — ICGERCLK/R — (11) ERCS=1 ERCS=1 and FEE FEE 0 fICGERCLK 2/fICGERCLK ICGDCLK/R3 DCOS=1 — (11) (11) ERCS=1 and 1 fICGERCLK 128/fICGERCLK ICGDCLK/R(2) DCOS=1 — 1 CLKST will not update immediately after a write to CLKS. Several bus cycles are required before CLKST updates to the new value. 2 ThereferencefrequencyhasnoeffectonICGOUTinSCM,butthereferencefrequencyisstillusedinmakingthecomparisons that determine the DCOS bit 3 AfterinitialLOCK;willbeICGDCLK/2RduringinitiallockingprocessandwhileFLLisre-lockingaftertheMFDbitsarechanged. MC9S08GT16A/GT8A Data Sheet, Rev. 1 142 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) 9.4.11 Fixed Frequency Clock The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is equal to the internal bus clock, BUSCLK, in all modes except FEE. In FEE mode, XCLK is equal to ICGERCLK÷ 2 when the following conditions are met: • (P × N)÷R ≥ 4 where P is determined by RANGE (seeTable9-11), N and R are determined by MFD and RFD respectively (see Table9-12). • LOCK = 1. If the above conditions are not true, then XCLK is equal to BUSCLK. WhentheICGisineitherFEIorSCMmode,XCLKisturnedoff.AnyperipheralswhichcanuseXCLK as a clock source must not do so when the ICG is in FEI or SCM mode. 9.4.12 High Gain Oscillator The oscillator has the option of running in a high gain oscillator (HGO) mode, which improves the oscillator'sresistancetoEMCnoisewhenrunninginFBEorFEEmodes.Thisoptionisselectedbywriting a1totheHGObitintheICGC1register.HGOisusedwithboththehighandlowrangeoscillatorsbutis only valid when REFS = 1 in the ICGC1 register. When HGO = 0, the standard low-power oscillator is selected. This bit is writable only once after any reset. 9.5 Initialization/Application Information 9.5.1 Introduction The section is intended to give some basic direction on which configuration a user would want to select wheninitializingtheICG.Forsomeapplications,theserialcommunicationlinkmaydictatetheaccuracy of the clock reference. For other applications, lowest power consumption may be the chief clock consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in choosing which is best for any application. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 143

Internal Clock Generator (S08ICGV4) Table9-10. ICG Configuration Consideration Clock Reference Source = Internal Clock Reference Source = External FEI FEE 4 MHz < fBus< 20 MHz. 4 MHz < fBus< 20 MHz Medium power (will be less than FEE if oscillator Medium power (will be less than FEI if oscillator FLL range = high) range = low) Engaged Good clock accuracy (After IRG is trimmed) High clock accuracy Lowest system cost(no external components Medium/High system cost (crystal, resonator or required) external clock source required) IRG is on. DCO is on.1 IRG is off. DCO is on. SCM FBE This mode is mainly provided for quick and reliable f range≤8 MHz when crystal or resonator is Bus system startup. used. FLL 3 MHz < fBus< 5 MHz (default). Lowest power Bypassed 3 MHz < fBus< 20 MHz (via filter bits). Highest clock accuracy Medium power Medium/High system cost (Crystal, resonator or Poor accuracy. external clock source required) IRG is off. DCO is on and open loop. IRG is off. DCO is off. 1 TheIRGtypicallyconsumes100µA.TheFLLandDCOtypicallyconsumes0.5to2.5mA,dependinguponoutputfrequency. For minimum power consumption and minimum jitter, choose N and R to be as small as possible. The following sections contain initialization examples for various configurations. NOTE Hexadecimalvaluesdesignatedbyapreceding$,binaryvaluesdesignated by a preceding %, and decimal values have no preceding character. Important configuration information is repeated here for reference. Table9-11. ICGOUT Frequency Calculation Options Clock Scheme f 1 P Note ICGOUT SCM — self-clocked mode (FLL bypassed f / R NA Typical f = 8MHz ICGDCLK ICGOUT internal) immediately after reset FBE — FLL bypassed external f / R NA ext FEI — FLL engaged internal (f / 7)* 64 * N / R 64 Typical f = 243 kHz IRG IRG FEE — FLL engaged external f * P * N / R Range =0 ; P = 64 ext Range =1; P = 1 1 Ensure thatf , which is equal tof * R, does not exceed f . ICGDCLK ICGOUT ICGDCLKmax Table9-12. MFD and RFD Decode Table MFD Value Multiplication Factor (N) RFD Division Factor (R) 000 4 000 ÷1 001 6 001 ÷2 010 8 010 ÷4 011 10 011 ÷8 100 12 100 ÷16 MC9S08GT16A/GT8A Data Sheet, Rev. 1 144 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) Table9-12. MFD and RFD Decode Table 101 14 101 ÷32 110 16 110 ÷64 111 18 111 ÷128 9.5.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to 8.38MHz to achieve 4.19 MHz bus frequency. AftertheMCUisreleasedfromreset,theICGisinself-clockedmode(SCM)andsuppliesapproximately 8 MHz on ICGOUT, which corresponds to a 4 MHz bus frequency (f ). Bus The clock scheme will be FLL engaged, external (FEE). So f = f * P * N / R ; P =64, f = 32 kHz Eqn.9-1 ICGOUT ext ext Solving for N / R gives: N / R = 8.38 MHz /(32 kHz * 64) = 4 ; we can choose N = 4 and R =1 Eqn.9-2 The values needed in each register to set up the desired operation are: ICGC1 = $38 (%00111000) Bit 7 HGO 0 Configures oscillator for low power Bit 6 RANGE 0 Configures oscillator for low-frequency range; FLL prescale factor is 64 Bit 5 REFS 1 Oscillator using crystal or resonator is requested Bits 4:3 CLKS 11 FLL engaged, external reference clock mode Bit 2 OSCSTEN 0 Oscillator disabled Bit 1 LOCD 0 Loss-of-clock detection enabled Bit 0 0 Unimplemented or reserved, always reads zero ICGC2 = $00 (%00000000) Bit 7 LOLRE 0 Generates an interrupt request on loss of lock Bits 6:4 MFD 000 Sets the MFD multiplication factor to 4 Bit 3 LOCRE 0 Generates an interrupt request on loss of clock Bits 2:0 RFD 000 Sets the RFD division factor to÷1 ICGS1 = $xx This is read only except for clearing interrupt flag ICGS2 = $xx This is read only; should read DCOS= 1 before performing any time critical tasks ICGFLTLU/L = $xx Only needed in self-clocked mode; FLT will be adjusted by loop to give 8.38 MHz DCO clock Bits 15:12 unused 0000 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 145

Internal Clock Generator (S08ICGV4) Bits 11:0 FLT No need for user initialization ICGTRM = $xx Bits 7:0 TRIM Only need to write when trimming internal oscillator; not used when external crystal is clock source Figure9-14 shows flow charts for three conditions requiring ICG initialization. RESET QUICK RECOVERY FROM STOP MINIMUM CURRENT DRAW IN STOP RECOVERY FROM STOP RECOVERY FROM STOP OSCSTEN =1 OSCSTEN =0 INITIALIZE ICG ICGC1 = $38 ICGC2=$00 CHECK CHECK NO NO FLL LOCK STATUS. FLL LOCK STATUS. LOCK=1? LOCK=1? YES YES CHECK NO FLL LOCK STATUS. LOCK=1? CONTINUE CONTINUE YES CONTINUE NOTE: THIS WILL REQUIRE THE OSCILLATOR TO START AND STABILIZE. ACTUAL TIME IS DEPENDENT ON CRYSTAL /RESONATOR AND EXTERNAL CIRCUITRY. Figure9-14. ICG Initialization for FEE in Example #1 MC9S08GT16A/GT8A Data Sheet, Rev. 1 146 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) 9.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 4 MHz oscillator up to 40-MHz to achieve 20 MHz bus frequency. AftertheMCUisreleasedfromreset,theICGisinself-clockedmode(SCM)andsuppliesapproximately 8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (f ). Bus During reset initialization software, the clock scheme will be set to FLL engaged, external (FEE). So f = f * P * N / R ; P =1, f = 4.00 MHz Eqn.9-3 ICGOUT ext ext Solving for N / R gives: N / R = 40 MHz /(4 MHz * 1) = 10 ; We can choose N = 10 and R =1 Eqn.9-4 The values needed in each register to set up the desired operation are: ICGC1 = $78 (%01111000) Bit 7 HGO 0 Configures oscillator for low power Bit 6 RANGE 1 Configures oscillator for high-frequency range; FLL prescale factor is 1 Bit 5 REFS 1 Requests an oscillator Bits 4:3 CLKS 11 FLL engaged, external reference clock mode Bit 2 OSCSTEN 0 Disables the oscillator Bit 1 LOCD 0 Loss-of-clock detection enabled Bit 0 0 Unimplemented or reserved, always reads zero ICGC2 = $30 (%00110000) Bit 7 LOLRE 0 Generates an interrupt request on loss of lock Bit 6:4 MFD 011 Sets the MFD multiplication factor to 10 Bit 3 LOCRE 0 Generates an interrupt request on loss of clock Bit 2:0 RFD 000 Sets the RFD division factor to÷1 ICGS1 = $xx This is read only except for clearing interrupt flag ICGS2 = $xx This is read only. Should read DCOS before performing any time critical tasks ICGFLTLU/L = $xx Not used in this example ICGTRM Not used in this example MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 147

Internal Clock Generator (S08ICGV4) RECOVERY RESET FROM STOP INITIALIZE ICG ICGC1 = $7A SERVICE INTERRUPT ICGC2 = $30 SOURCE (f = 4 MHz) Bus CHECK NO FLL LOCK STATUS CHECK NO LOCK=1? FLL LOCK STATUS LOCK=1? YES YES CONTINUE CONTINUE Figure9-15. ICG Initialization and Stop Recovery for Example #2 MC9S08GT16A/GT8A Data Sheet, Rev. 1 148 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) 9.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency In this example, the FLL will be used (in FEI mode) to multiply the internal 243 kHz (approximate) reference clock up to 10.8 MHz to achieve 5.4 MHz bus frequency. This system will also use the trim function to fine tune the frequency based on an external reference signal. AftertheMCUisreleasedfromreset,theICGisinself-clockedmode(SCM)andsuppliesapproximately 8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (f ). Bus The clock scheme will be FLL engaged, internal (FEI). So f = (f / 7) * P * N / R ; P = 64, f = 243 kHz Eqn.9-5 ICGOUT IRG IRG Solving for N / R gives: N / R = 10.8 MHz /(243/7 kHz * 64) = 4.86 ; We can choose N = 10 and R = 2. Eqn.9-6 A trim procedure will be required to hone the frequency to exactly 5.4 MHz. An example of the trim procedure is shown in example #4. The values needed in each register to set up the desired operation are: ICGC1 = $28 (%00101000) Bit 7 HGO 0 Configures oscillator for low power Bit 6 RANGE 0 Configures oscillator for low-frequency range; FLL prescale factor is 64 Bit 5 REFS 1 Oscillator using crystal or resonator requested (bit is really a don’t care) Bits 4:3 CLKS 01 FLL engaged, internal reference clock mode Bit 2 OSCSTEN 0 Disables the oscillator Bit 1 LOCD 0 Loss-of-clock enabled Bit 0 0 Unimplemented or reserved, always reads zero ICGC2 = $31 (%00110001) Bit 7 LOLRE 0 Generates an interrupt request on loss of lock Bit 6:4 MFD 011 Sets the MFD multiplication factor to 10 Bit 3 LOCRE 0 Generates an interrupt request on loss of clock Bit 2:0 RFD 001 Sets the RFD division factor to÷2 ICGS1 = $xx This is read only except for clearing interrupt flag ICGS2 = $xx This is read only; good idea to read this before performing time critical operations ICGFLTLU/L = $xx Not used in this example MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 149

Internal Clock Generator (S08ICGV4) ICGTRM = $xx Bit 7:0 TRIM Only need to write when trimming internal oscillator; done in separate operation (see example #4) RECOVERY RESET FROM STOP INITIALIZE ICG ICGC1 =$28 CHECK NO ICGC2 = $31 FLL LOCK STATUS. LOCK=1? YES CHECK NO FLL LOCK STATUS. LOCK=1? CONTINUE YES CONTINUE NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. Figure9-16. ICG Initialization and Stop Recovery for Example #3 MC9S08GT16A/GT8A Data Sheet, Rev. 1 150 Freescale Semiconductor

Internal Clock Generator (S08ICGV4) 9.5.5 Example #4: Internal Clock Generator Trim Theinternallygeneratedclocksourceisguaranteedtohaveaperiod±25%ofthenominalvalue.Insome cases, this may be sufficient accuracy. For other applications that require a tight frequency tolerance, a trimmingprocedureisprovidedthatwillallowaveryaccuratesource.Thissectionoutlinesoneexample of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used. Initial conditions: 1) Clock supplied from ATE has 500µsec duty period 2) ICG configured for internal reference with 4 MHz bus START TRIM PROCEDURE ICGTRM = $80, n=1 MEASURE INCOMING CLOCK WIDTH (COUNT = # OF BUS CLOCKS / 4) COUNT < EXPECTED =500 (RUNNING TOO SLOW) . COUNT = EXPECTED = 500 CASE STATEMENT COUNT > EXPECTED = 500 (RUNNING TOO FAST) ICGTRM = ICGTRM = ICGTRM - 128 / (2**n) ICGTRM + 128 / (2**n) STORE ICGTRM VALUE (DECREASING ICGTRM (INCREASING ICGTRM IN NON-VOLATILE INCREASES THE FREQUENCY) DECREASES THE FREQUENCY) MEMORY CONTINUE n = n + 1 YES IS n > 8? NO Figure9-17. Trim Procedure In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final testwithautomatedtestequipment.AseparatesignalormessageisprovidedtotheMCUoperatingunder user provided software control. The MCU initiates a trim procedure as outlined inFigure9-17 while the tester supplies a precision reference signal. Iftheintendedbusfrequencyisnearthemaximumallowedforthedevice,itisrecommendedtotrimusing a reduction divisor (R) twice the final value. After the trim procedure is complete, the reduction divisor can be restored. This will prevent accidental overshoot of the maximum clock frequency. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 151

Internal Clock Generator (S08ICGV4) MC9S08GT16A/GT8A Data Sheet, Rev. 1 152 Freescale Semiconductor

Chapter 10 Timer/PWM (S08TPMV2) 10.1 Introduction The MC9S08GT16A/GT8A includes two independent timer/PWM (TPM) modules which support traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on eachchannel.AcontrolbitineachTPMconfiguresallchannelsinthattimertooperateascenter-aligned PWMfunctions.IneachofthesetwoTPMs,timingfunctionsarebasedonaseparate16-bitcounterwith prescaler and modulo features to control frequency and range (period between overflows) of the time reference. This timing system is ideally suited for a wide range of control applications, and the center-alignedPWMcapabilityonthe3-channelTPMextendsthefieldofapplicationstomotorcontrolin small appliances. The use of the fixed system clock, XCLK, as the clock source for either of the TPM modules allows the TPMprescalertorunusingtheoscillatorratedividedbytwo(ICGERCLK/2).Thisclocksourcemustbe selectedonlyiftheICGisconfiguredineitherFBEorFEEmode.InFBEmode,thisselectionisredundant becausetheBUSCLKfrequencyisthesameasXCLK.InFEEmode,theproperconditionsmustbemet forXCLKtoequalICGERCLK/2.SelectingXCLKastheclocksourcewiththeICGineitherFEIorSCM mode will result in the TPM being non-functional. 10.1.1 Features ThetimersystemintheMC9S08GT16Aincludesa3-channelTPM1andaseparate5-channelTPM2;the timer system in the MC9S08GT8A includes two 2-channel modules, TPM1 and TPM2. Timer system features include: • A total of eight channels: — Each channel may be input capture, output compare, or buffered edge-aligned PWM — Rising-edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs • EachTPMmaybeconfiguredforbuffered,center-alignedpulse-widthmodulation(CPWM)onall channels • Clock source to prescaler for each TPM is independently selectable as bus clock, fixed system clock, or an external pin • Prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 • 16-bit free-running or up/down (CPWM) count operation • 16-bit modulus register to control counter range • Timer system enable • One interrupt per channel plus terminal count interrupt MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 153

Timer/PWM (S08TPMV2) VREFLVREFHVSSADVDDAD 4 HCS08 CORE BKGD 8IN-BTIETR KREUYPBTO (AKRBDI) 8 PORT A 4 PPPTTTAAA347///KKKBBBIIIPPP347–– NOTE 6 PTA0/KBIP0 CPU BDC 4 10-BIT 8 T B PPTTBB74//AADDPP74– ANALOG-TO-DIGITAL OR 4 HCS08 SYSTEM CONTROL CONVERTER (ATD) P PTB3/ADP3– RESET PTB0/ADP0 NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION PTC7 POWER MANAGEMENT PTC6 PTC5 RTI COP INTER-IC (IIC) SSDCAL PORT C PPPTTTCCC432//SSCDAL NOTE 5 IRQ IRQ LVD RXD2 NOTES 2, 3 SERIAL COMMUNICATIONS PTC1/RxD2 TXD2 INTERFACE (SCI2) PTC0/TxD2 CH1 USER FLASH 2-CHANNEL TIMER/PWM PTD4/TPM2CH1 CH0 (GT16A = 16,384 BYTES) (TPM2) PTD3/TPM2CLK/TPM2CH0 (GT8A = 8192 BYTES) D CH0 RT O PTD2/TPM1CH2 3-CHANNEL TIMER/PWM CH1 P PTD1/TPM1CH1 (TPM1) CH2 PTD0/TPM1CLK/TPM1CH0 USER RAM (GT16A = 2048 BYTES) SPSCK (GT8A = 1024 BYTES) PTE5/SPSCK MOSI SERIAL PERIPHERAL PTE4/MOSI MISO ON-CHIP ICE INTERFACE (SPI) SS RT E PPTTEE32//MSSISO DEBUG O RXD1 P MODULE (DBG) SERIAL COMMUNICATIONS PTE1/RxD1 TXD1 INTERFACE (SCI1) PTE0/TxD1 INTERNAL CLOCK GENERATOR (ICG) PTG3 EXTAL G PTG2/EXTAL XTAL T LOW-POWER OSCILLATOR R PTG1/XTAL BKGD O P PTG0/BKGD/MS V DD VOLTAGE V SS REGULATOR = Pins not available in 44-, 42-, or 32-pin packages V SS = Pins not available in 42- or 32-pin packages = Pins not available in 32-pin packages NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE=1). 3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD. 4. Pin contains integrated pullup device. 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1). Figure10-1. Block Diagram Highlighting the TPM Modules MC9S08GT16A/GT8A Data Sheet, Rev. 1 154 Freescale Semiconductor

Timer/Pulse-Width Modulator (S08TPMV2) 10.1.2 Features The TPM has the following features: • EachTPMmaybeconfiguredforbuffered,center-alignedpulse-widthmodulation(CPWM)onall channels • Clock sources independently selectable per TPM (multiple TPMs device) • Selectable clock sources (device dependent): bus clock, fixed system clock, external pin • Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 • 16-bit free-running or up/down (CPWM) count operation • 16-bit modulus register to control counter range • Timer system enable • One interrupt per channel plus a terminal count interrupt for each TPM module (multiple TPMs device) • Channel features: — Each channel may be input capture, output compare, or buffered edge-aligned PWM — Rising-edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs 10.1.3 Block Diagram Figure10-2 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers of channels. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 155

Timer/Pulse-Width Modulator (S08TPMV2) BUSCLK CLOCK SOURCE PRESCALE AND SELECT SELECT DIVIDE BY XCLK SYNC OFF, BUS, XCLK, EXT 1, 2, 4, 8, 16, 32, 64, or 128 TPMxCLK CLKSB CLKSA PS2 PS1 PS0 CPWMS MAIN 16-BIT COUNTER TOF COUNTER RESET INTERRUPT TOIE LOGIC 16-BIT COMPARATOR TPMxMODH:TPMxMODL ELS0B ELS0A CHANNEL 0 PORT TPMxCH0 16-BIT COMPARATOR LOGIC TPMxC0VH:TPMxC0VL CH0F 16-BIT LATCH INTERRUPT LOGIC MS0B MS0A CH0IE S CHANNEL 1 ELS1B ELS1A PORT TPMxCH1 BU 16-BIT COMPARATOR LOGIC L NA TPMxC1VH:TPMxC1VL CH1F R E T 16-BIT LATCH INTERRUPT N I LOGIC MS1B MS1A CH1IE . . . . . . . . . ELSnB ELSnA CHANNEL n PORT TPMxCHn 16-BIT COMPARATOR LOGIC TPMxCnVH:TPMxCnVL CHnF 16-BIT LATCH INTERRUPT LOGIC CHnIE MSnB MSnA Figure10-2. TPM Block Diagram The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a modulocounter,oranup-/down-counterwhentheTPMisconfiguredforcenter-alignedPWM.TheTPM counter(whenoperatinginnormalup-countingmode)providesthetimingreferencefortheinputcapture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control the modulo value of the counter. (The values 0x0000 or 0xFFFF effectively make the counter free running.) Software can read the counter value at any time without affecting the counting sequence. Any write to either byte of the TPMxCNT counter resets the counter regardless of the data value written. MC9S08GT16A/GT8A Data Sheet, Rev. 1 156 Freescale Semiconductor

Timer/Pulse-Width Modulator (S08TPMV2) All TPM channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels. 10.2 External Signal Description When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled. Afterreset,theTPMmodulesaredisabledandallpinsdefaulttogeneral-purposeinputswiththepassive pullups disabled. 10.2.1 External TPM Clock Sources WhencontrolbitsCLKSB:CLKSAinthetimerstatusandcontrolregisteraresetto1:1,theprescalerand consequentlythe16-bitcounterforTPMxaredrivenbyanexternalclocksource,TPMxCLK,connected to an I/O pin. A synchronizer is needed between the external clock and the rest of the TPM. This synchronizerisclockedbythebusclocksothefrequencyoftheexternalsourcemustbelessthanone-half thefrequencyofthebusrateclock.Theupperfrequencylimitforthisexternalclocksourceisspecifiedto beone-fourththebusfrequencytoconservativelyaccommodatedutycycleandphase-lockedloop(PLL) or frequency-locked loop (FLL) frequency jitter effects. OnsomedevicestheexternalclockinputissharedwithoneoftheTPMchannels.WhenaTPMchannel issharedastheexternalclockinput,theassociatedTPMchannelcannotusethepin.(Thechannelcanstill be used in output compare mode as a software timer.) Also, if one of the TPM channels is used as the externalclockinput,thecorrespondingELSnB:ELSnAcontrolbitsmustbesetto0:0sothechannelisnot trying to use the same pin. 10.2.2 TPMxCHn — TPMx Channel n I/O Pins Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the configurationofthechannel.Insomecases,nopinfunctionisneededsothepinrevertstobeingcontrolled by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction registersdonotaffecttherelatedpin(s).SeethePinsandConnectionschapterforadditionalinformation about shared pin functions. 10.3 Register Definition The TPM includes: • An 8-bit status and control register (TPMxSC) • A 16-bit counter (TPMxCNTH:TPMxCNTL) • A 16-bit modulo register (TPMxMODH:TPMxMODL) Each timer channel has: • An 8-bit status and control register (TPMxCnSC) • A 16-bit channel value register (TPMxCnVH:TPMxCnVL) Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignmentsforallTPMregisters.Thissectionreferstoregistersandcontrolbitsonlybytheirnames.A MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 157

Timer/Pulse-Width Modulator (S08TPMV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. SomeMCUsystemshavemorethanoneTPM,soregisternamesincludeplaceholdercharacterstoidentify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n and TPM1C2SC is the status and control register for timer 1, channel 2. 10.3.1 Timer x Status and Control Register (TPMxSC) TPMxSCcontainstheoverflowstatusflagandcontrolbitsthatareusedtoconfiguretheinterruptenable, TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this timer module. 7 6 5 4 3 2 1 0 R TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure10-3. Timer x Status and Control Register (TPMxSC) Table10-1. TPMxSC Register Field Descriptions Field Description 7 Timer Overflow Flag — This flag is set when the TPM counter changes to 0x0000 after reaching the modulo TOF value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set after the counter has reached the value in the modulo register, at the transition to the next lower count value. ClearTOFbyreadingtheTPMstatusandcontrolregisterwhenTOFissetandthenwritinga0toTOF.Ifanother TPMoverflowoccursbeforetheclearingsequenceiscomplete,thesequenceisresetsoTOFwouldremainset aftertheclearsequencewascompletedfortheearlierTOF.ResetclearsTOF.Writinga1toTOFhasnoeffect. 0 TPM counter has not reached modulo value or overflow 1 TPM counter has overflowed 6 Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an TOIE interrupt is generated when TOF equals 1. Reset clears TOIE. 0 TOF interrupts inhibited (use software polling) 1 TOF interrupts enabled 5 Center-AlignedPWMSelect—Thisread/writebitselectsCPWMoperatingmode.Resetclearsthisbitsothe CPWMS TPMoperatesinup-countingmodeforinputcapture,outputcompare,andedge-alignedPWMfunctions.Setting CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears CPWMS. 0 AllTPMxchannelsoperateasinputcapture,outputcompare,oredge-alignedPWMmodeasselectedbythe MSnB:MSnA control bits in each channel’s status and control register 1 All TPMx channels operate in center-aligned PWM mode 4:3 ClockSourceSelect—AsshowninTable10-2,this2-bitfieldisusedtodisabletheTPMsystemorselectone CLKS[B:A] ofthreeclocksourcestodrivethecounterprescaler.TheexternalsourceandtheXCLKaresynchronizedtothe bus clock by an on-chip synchronization circuit. 2:0 Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in PS[2:0] Table10-3.Thisprescalerislocatedafteranyclocksourcesynchronizationorclocksourceselection,soitaffects whatever clock source is selected to drive the TPM system. MC9S08GT16A/GT8A Data Sheet, Rev. 1 158 Freescale Semiconductor

Timer/Pulse-Width Modulator (S08TPMV2) Table10-2. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 0:0 No clock selected (TPMx disabled) 0:1 Bus rate clock (BUSCLK) 1:0 Fixed system clock (XCLK) 1:1 External source (TPMxCLK)1,2 1 The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency. 2 If the external clock input is shared with channel n and is selected as the TPM clock source, the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try to use the same pin for a conflicting function. Table10-3. Prescale Divisor Selection PS2:PS1:PS0 TPM Clock Source Divided-By 0:0:0 1 0:0:1 2 0:1:0 4 0:1:1 8 1:0:0 16 1:0:1 32 1:1:0 64 1:1:1 128 10.3.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) Thetworead-onlyTPMcounterregisterscontainthehighandlowbytesofthevalueintheTPMcounter. Readingeitherbyte(TPMxCNTHorTPMxCNTL)latchesthecontentsofbothbytesintoabufferwhere they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The coherencymechanismisautomaticallyrestartedbyanMCUreset,awriteofanyvaluetoTPMxCNTHor TPMxCNTL, or any write to the timer status/control register (TPMxSC). Reset clears the TPM counter registers. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Any write to TPMxCNTH clears the 16-bit counter. Reset 0 0 0 0 0 0 0 0 Figure10-4. Timer x Counter Register High (TPMxCNTH) MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 159

Timer/Pulse-Width Modulator (S08TPMV2) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Any write to TPMxCNTL clears the 16-bit counter. Reset 0 0 0 0 0 0 0 0 Figure10-5. Timer x Counter Register Low (TPMxCNTL) Whenbackgroundmodeisactive,thetimercounterandthecoherencymechanismarefrozensuchthatthe buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. 10.3.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock (CPWMS = 0)orstartscountingdown(CPWMS = 1),andtheoverflowflag(TOF)becomesset.Writing toTPMxMODHorTPMxMODLinhibitsTOFandoverflowinterruptsuntiltheotherbyteiswritten.Reset setstheTPMcountermoduloregistersto0x0000,whichresultsinafree-runningtimercounter(modulo disabled). 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure10-6. Timer x Counter Modulo Register High (TPMxMODH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure10-7. Timer x Counter Modulo Register Low (TPMxMODL) Itisgoodpracticetowaitforanoverflowinterruptsobothbytesofthemoduloregistercanbewrittenwell before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. MC9S08GT16A/GT8A Data Sheet, Rev. 1 160 Freescale Semiconductor

Timer/Pulse-Width Modulator (S08TPMV2) 10.3.4 Timer x Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 1 0 R 0 0 CHnF CHnIE MSnB MSnA ELSnB ELSnA W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure10-8. Timer x Channel n Status and Control Register (TPMxCnSC) Table10-4. TPMxCnSC Register Field Descriptions Field Description 7 ChannelnFlag—Whenchannelnisconfiguredforinputcapture,thisflagbitissetwhenanactiveedgeoccurs CHnF on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag is seldom used with center-aligned PWMs because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF byreadingTPMxCnSCwhileCHnFissetandthenwritinga0toCHnF.Ifanotherinterruptrequestoccursbefore the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect. 0 No input capture or output compare event occurred on channeln 1 Input capture or output compare event occurred on channeln 6 Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE. CHnIE 0 Channel n interrupt requests disabled (use software polling) 1 Channel n interrupt requests enabled 5 Mode Select B for TPM Channel n — When CPWMS=0, MSnB=1 configures TPM channel n for MSnB edge-aligned PWM mode. For a summary of channel mode and setup controls, refer toTable10-5. 4 ModeSelectAforTPMChanneln—WhenCPWMS=0andMSnB=0,MSnAconfiguresTPMchannelnfor MSnA input capture mode or output compare mode. Refer toTable10-5 for a summary of channel mode and setup controls. 3:2 Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by ELSn[B:A] CPWMS:MSnB:MSnA and shown inTable10-5, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. SettingELSnB:ELSnAto0:0configurestherelatedtimerpinasageneral-purposeI/Opinunrelatedtoanytimer channelfunctions.Thisfunctionistypicallyusedtotemporarilydisableaninputcapturechannelortomakethe timerpinavailableasageneral-purposeI/Opinwhentheassociatedtimerchannelissetupasasoftwaretimer that does not require the use of a pin. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 161

Timer/Pulse-Width Modulator (S08TPMV2) Table10-5. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration X XX 00 PinnotusedforTPMchannel;useasanexternalclockfortheTPMor revert to general-purpose I/O 0 00 01 Input capture Capture onrising edge only 10 Capture onfalling edge only 11 Capture on rising or falling edge 01 00 Output Software compare only compare 01 Toggle output on compare 10 Clearoutput on compare 11 Setoutput on compare 1X 10 Edge-aligned High-true pulses (clearoutput on compare) PWM X1 Low-true pulses (setoutput on compare) 1 XX 10 Center-aligned High-true pulses (clearoutput on compare-up) PWM X1 Low-true pulses (setoutput on compare-up) If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior. 10.3.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) These read/write registers contain the captured TPM counter value of the input capture function or the outputcomparevaluefortheoutputcompareorPWMfunctions.Thechannelvalueregistersarecleared by reset. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure10-9. Timerx Channel Value Register High (TPMxCnVH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure10-10. TimerChannel Value Register Low (TPMxCnVL) Ininputcapturemode,readingeitherbyte(TPMxCnVHorTPMxCnVL)latchesthecontentsofbothbytes into a buffer where they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPMxCnSC register is written. MC9S08GT16A/GT8A Data Sheet, Rev. 1 162 Freescale Semiconductor

Timer/Pulse-Width Modulator (S08TPMV2) InoutputcompareorPWMmodes,writingtoeitherbyte(TPMxCnVHorTPMxCnVL)latchesthevalue into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 10.4 Functional Description All TPM functions are associated with a main 16-bit counter that allows flexible selection of the clock sourceandprescaledivisor.A16-bitmoduloregisteralsoisassociatedwiththemain16-bitcounterinthe TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function. TheTPMhascenter-alignedPWMcapabilitiescontrolledbytheCPWMScontrolbitinTPMxSC.When CPWMS is set to 1, timer counter TPMxCNT changes to an up-/down-counter and all channels in the associated TPM act as center-aligned PWM channels. When CPWMS =0, each channel can independentlybeconfiguredtooperateininputcapture,outputcompare,orbufferededge-alignedPWM mode. The following sections describe the main 16-bit counter and each of the timer operating modes (input capture,outputcompare,edge-alignedPWM,andcenter-alignedPWM).Becausedetailsofpinoperation and interrupt activity depend on the operating mode, these topics are covered in the associated mode sections. 10.4.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overflow, and manual counter reset. After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive. Normally,CLKSB:CLKSAwouldbesetto0:1sothebusclockdrivesthetimercounter.Theclocksource for each of the TPM can be independently selected to be off, the bus clock (BUSCLK), the fixed system clock (XCLK), or an external input. The maximum frequency allowed for the external clock option is one-fourth the bus rate. Refer toSection10.3.1, “Timer x Status and Control Register (TPMxSC)” and Table10-2 for more information about clock source selection. Whenthemicrocontrollerisinactivebackgroundmode,theTPMtemporarilysuspendsallcountinguntil themicrocontrollerreturnstonormaluseroperatingmode.Duringstopmode,allTPMclocksarestopped; therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to operate normally. Themain16-bitcounterhastwocountingmodes.Whencenter-alignedPWMisselected(CPWMS = 1), thecounteroperatesinup-/down-countingmode.Otherwise,thecounteroperatesasasimpleup-counter. As an up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then continueswith0x0000.Theterminalcountis0xFFFForamodulusvalueinTPMxMODH:TPMxMODL. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 163

Timer/Pulse-Width Modulator (S08TPMV2) When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminalcountandthencountsdownwardto0x0000whereitreturnstoup-counting.Both0x0000andthe terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock period long). Aninterruptflagandenableareassociatedwiththemain16-bitcounter.Thetimeroverflowflag(TOF)is asoftware-accessibleindicationthatthetimercounterhasoverflowed.Theenablesignalselectsbetween software polling (TOIE= 0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE= 1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1. The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-countingmode,themain16-bitcountercountsfrom0x0000through0xFFFFandoverflowsto0x0000 onthenextcountingclock.TOFbecomessetatthetransitionfrom0xFFFFto0x0000.Whenamodulus limitisset,TOFbecomessetatthetransitionfromthevaluesetinthemodulusregisterto0x0000.When the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changesdirectionatthetransitionfromthevaluesetinthemodulusregisterandthenextlowercountvalue. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter forreadoperations.Whenevereitherbyteofthecounterisread(TPMxCNTHorTPMxCNTL),bothbytes arecapturedintoabuffersowhentheotherbyteisread,thevaluewillrepresenttheotherbyteofthecount atthetimethefirstbytewasread.Thecountercontinuestocountnormally,butnonewvaluecanberead from either byte until both bytes of the old count have been read. Themaintimercountercanberesetmanuallyatanytimebywritinganyvaluetoeitherbyteofthetimer count TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was read before resetting the count. 10.4.2 Channel Mode Selection ProvidedCPWMS= 0(center-alignedPWMoperationisnotspecified),theMSnBandMSnAcontrolbits inthechannelnstatusandcontrol registersdeterminethebasicmodeofoperationforthecorresponding channel. Choices include input capture, output compare, and buffered edge-aligned PWM. 10.4.2.1 Input Capture Mode Withtheinputcapturefunction,theTPMcancapturethetimeatwhichanexternaleventoccurs.Whenan activeedgeoccursonthepinofaninputcapturechannel,theTPMlatchesthecontentsoftheTPMcounter intothechannelvalueregisters(TPMxCnVH:TPMxCnVL).Risingedges,fallingedges,oranyedgemay be chosen as the active edge that triggers an input capture. When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent16-bitaccessesregardlessoforder.Thecoherencysequencecanbemanuallyresetbywritingto the channel status/control register (TPMxCnSC). An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. MC9S08GT16A/GT8A Data Sheet, Rev. 1 164 Freescale Semiconductor

Timer/Pulse-Width Modulator (S08TPMV2) 10.4.2.2 Output Compare Mode With the output compare function, the TPM can generate timed pulses with programmable position, polarity,duration,andfrequency.Whenthecounterreachesthevalueinthechannelvalueregistersofan output compare channel, the TPM can set, clear, or toggle the channel pin. In output compare mode, values are transferred to the corresponding timer channel value registers only afterboth8-bitbytesofa16-bitregisterhavebeenwritten.Thiscoherencysequencecanbemanuallyreset by writing to the channel status/control register (TPMxCnSC). An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. 10.4.2.3 Edge-Aligned PWM Mode ThistypeofPWMoutputusesthenormalup-countingmodeofthetimercounter(CPWMS = 0)andcan be used when other channels in the same TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the setting in the modulus register (TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. Duty cycle cases of 0percent and 100 percent are possible. AsFigure 10-11shows,theoutputcomparevalueintheTPMchannelregistersdeterminesthepulsewidth (duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the pulse width. If ELSnA = 0, the counter overflow forces the PWM signal high and the output compare forcesthePWMsignallow.IfELSnA= 1,thecounteroverflowforcesthePWMsignallowandtheoutput compare forces the PWM signal high. OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TPMxC OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE Figure10-11. PWM Period and Pulse Width (ELSnA=0) Whenthechannelvalueregisterissetto0x0000,thedutycycleis0percent.Bysettingthetimerchannel value register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting, 100% duty cycle can be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register, TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the correspondingtimerchannelregistersonlyafterboth8-bitbytesofa16-bitregisterhavebeenwrittenand the value in the TPMxCNTH:TPMxCNTL counter is 0x0000. (The new duty cycle does not take effect until the next full period.) MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 165

Timer/Pulse-Width Modulator (S08TPMV2) 10.4.3 Center-Aligned PWM Mode This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS= 1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODLshouldbekeptintherangeof0x0001to0x7FFFbecausevaluesoutsidethis range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output. pulse width=2 x (TPMxCnVH:TPMxCnVL) Eqn.10-1 period = 2 x (TPMxMODH:TPMxMODL); for TPMxMODH:TPMxMODL=0x0001–0x7FFF Eqn.10-2 IfthechannelvalueregisterTPMxCnVH:TPMxCnVLiszeroornegative(bit15set),thedutycyclewill be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if generationof100%dutycycleisnotnecessary).Thisisnotasignificantlimitationbecausetheresulting period is much longer than required for normal applications. TPMxMODH:TPMxMODL = 0x0000isaspecialcasethatshouldnotbeusedwithcenter-alignedPWM mode. When CPWMS= 0, this case corresponds to the counter running free from 0x0000 through 0xFFFF,butwhenCPWMS= 1thecounterneedsavalidmatchtothemodulusregistersomewhereother than at 0x0000 in order to change directions from up-counting to down-counting. Figure10-12 shows the output compare value in the TPM channel registers (multiplied by 2), which determines the pulse width (duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while counting up forces the CPWM output signal low and a compare match while counting down forces the outputhigh.ThecountercountsupuntilitreachesthemodulosettinginTPMxMODH:TPMxMODL,then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL. COUNT=0 OUTPUT OUTPUT COUNT= COMPARE COMPARE COUNT= TPMxMODH:TPMx (COUNT DOWN) (COUNT UP) TPMxMODH:TPMx TPM1C PULSE WIDTH 2 x PERIOD 2 x Figure10-12. CPWM Period and Pulse Width (ELSnA=0) Center-alignedPWMoutputstypicallyproducelessnoisethanedge-alignedPWMsbecausefewerI/Opin transitionsarelinedupatthesamesystemclockedge.ThistypeofPWMisalsorequiredforsometypes of motor drives. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensurecoherent16-bitupdatesandtoavoidunexpectedPWMpulsewidths.Writestoanyoftheregisters, TPMxMODH,TPMxMODL,TPMxCnVH,andTPMxCnVL,actuallywritetobufferregisters.Valuesare MC9S08GT16A/GT8A Data Sheet, Rev. 1 166 Freescale Semiconductor

Timer/Pulse-Width Modulator (S08TPMV2) transferredtothecorrespondingtimerchannelregistersonlyafterboth8-bitbytesofa16-bitregisterhave beenwrittenandthetimercounteroverflows(reversesdirectionfromup-countingtodown-countingatthe endoftheterminalcountinthemodulusregister).ThisTPMxCNToverflowrequirementonlyappliesto PWM channels, not output compares. Optionally,whenTPMxCNTH:TPMxCNTL = TPMxMODH:TPMxMODL,theTPMcangenerateaTOF interruptattheendofthiscount.TheusercanchoosetoreloadanynumberofthePWMbuffers,andthey will all update simultaneously at the start of a new period. Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the coherencymechanismforthemoduloregisters.WritingtoTPMxCnSCcancelsanyvalueswrittentothe channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. 10.5 TPM Interrupts TheTPMgeneratesanoptionalinterruptforthemaincounteroverflowandaninterruptforeachchannel. The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized.IfthechannelisconfiguredforoutputcompareorPWMmodes,theinterruptflagisseteach time the main timer counter matches the value in the 16-bit channel value register. See theResets, Interrupts, and System Configuration chapter for absolute interrupt vector addresses, priority, and local interrupt mask control bits. ForeachinterruptsourceintheTPM,aflagbitissetonrecognitionoftheinterruptconditionsuchastimer overflow, channel input capture, or output compare events. This flag may be read (polled) by software to verify that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated whenever the associated interrupt flag equals 1. It is the responsibility of user software to perform a sequence of steps to clear the interrupt flag before returning from the interrupt service routine. 10.5.1 Clearing Timer Interrupt Flags TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1) followedbyawriteof0tothebit.Ifaneweventisdetectedbetweenthesetwosteps,thesequenceisreset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. 10.5.2 Timer Overflow Interrupt Description The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-countingmode,the16-bittimercountercountsfrom0x0000through0xFFFFandoverflowsto0x0000 onthenextcountingclock.TOFbecomessetatthetransitionfrom0xFFFFto0x0000.Whenamodulus limitisset,TOFbecomessetatthetransitionfromthevaluesetinthemodulusregisterto0x0000.When thecounterisoperatinginup-/down-countingmode,theTOFflaggetssetasthecounterchangesdirection atthetransitionfromthevaluesetinthemodulusregisterandthenextlowercountvalue.Thiscorresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 167

Timer/Pulse-Width Modulator (S08TPMV2) 10.5.3 Channel Event Interrupt Description The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges,fallingedges,anyedge,ornoedge(off)astheedgethattriggersaninputcaptureevent.Whenthe selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in Section10.5.1, “Clearing Timer Interrupt Flags.” When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step sequence described inSection10.5.1, “Clearing Timer Interrupt Flags.” 10.5.4 PWM End-of-Duty-Cycle Events For channels that are configured for PWM operation, there are two possibilities: • When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter matches the channel value register that marks the end of the active duty cycle period. • When the channel is configured for center-aligned PWM, the timer count matches the channel valueregistertwiceduringeachPWMcycle.InthisCPWMcase,thechannelflagissetatthestart and at the end of the active duty cycle, which are the times when the timer counter matches the channel value register. The flag is cleared by the 2-step sequence described inSection10.5.1, “Clearing Timer Interrupt Flags.” MC9S08GT16A/GT8A Data Sheet, Rev. 1 168 Freescale Semiconductor

Chapter 11 Serial Communications Interface (S08SCIV1) 11.1 Introduction TheMC9S08GT16A/GT8Aincludestwoindependentserialcommunicationsinterface(SCI)modules— sometimescalleduniversalasynchronousreceiver/transmitters(UARTs).Typically,thesesystemsareused toconnecttotheRS232serialinput/output(I/O)portofapersonalcomputerorworkstation,andtheycan also be used to communicate with other embedded controllers. Aflexible,13-bit,modulo-basedbaudrategeneratorsupportsabroadrangeofstandardbaudratesbeyond 115.2 kbaud. Transmit and receive within the same SCI use a common baud rate, and each SCI module has a separate baud rate generator. This SCI system offers many advanced features not commonly found on other asynchronous serial I/O peripherals on other embedded controllers. The receiver employs an advanced data sampling technique that ensures reliable communication and noise detection. Hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 169

Serial Communications Interface (S08SCIV1) VREFLVREFHVSSADVDDAD 4 HCS08 CORE BKGD 8IN-BTIETR KREUYPBTO (AKRBDI) 8 PORT A 4 PPPTTTAAA347///KKKBBBIIIPPP347–– NOTE 6 PTA0/KBIP0 CPU BDC 4 10-BIT 8 T B PPTTBB74//AADDPP74– ANALOG-TO-DIGITAL OR 4 HCS08 SYSTEM CONTROL CONVERTER (ATD) P PTB3/ADP3– RESET PTB0/ADP0 NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION PTC7 POWER MANAGEMENT PTC6 PTC5 RTI COP INTER-IC (IIC) SSDCAL PORT C PPPTTTCCC432//SSCDAL NOTE 5 IRQ IRQ LVD RXD2 NOTES 2, 3 SERIAL COMMUNICATIONS PTC1/RxD2 TXD2 INTERFACE (SCI2) PTC0/TxD2 CH1 USER FLASH 2-CHANNEL TIMER/PWM PTD4/TPM2CH1 CH0 (GT16A = 16,384 BYTES) (TPM2) PTD3/TPM2CLK/TPM2CH0 (GT8A = 8192 BYTES) D CH0 RT O PTD2/TPM1CH2 3-CHANNEL TIMER/PWM CH1 P PTD1/TPM1CH1 (TPM1) CH2 PTD0/TPM1CLK/TPM1CH0 USER RAM (GT16A = 2048 BYTES) SPSCK (GT8A = 1024 BYTES) PTE5/SPSCK MOSI SERIAL PERIPHERAL PTE4/MOSI MISO ON-CHIP ICE INTERFACE (SPI) SS RT E PPTTEE32//MSSISO DEBUG O RXD1 P MODULE (DBG) SERIAL COMMUNICATIONS PTE1/RxD1 TXD1 INTERFACE (SCI1) PTE0/TxD1 INTERNAL CLOCK GENERATOR (ICG) PTG3 EXTAL G PTG2/EXTAL XTAL T LOW-POWER OSCILLATOR R PTG1/XTAL BKGD O P PTG0/BKGD/MS V DD VOLTAGE V SS REGULATOR = Pins not available in 44-, 42-, or 32-pin packages V SS = Pins not available in 42- or 32-pin packages = Pins not available in 32-pin packages NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE=1). 3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD. 4. Pin contains integrated pullup device. 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1). Figure11-1. Block Diagram Highlighting the SCI Modules MC9S08GT16A/GT8A Data Sheet, Rev. 1 170 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) 11.1.1 Features Features of SCI module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Interrupt-driven or polled operation: — Transmit data register empty and transmission complete — Receive data register full — Receive overrun, parity error, framing error, and noise error — Idle receiver detect • Hardware parity generation and checking • Programmable 8-bit or 9-bit character length • Receiver wakeup by idle-line or address-mark 11.1.2 Modes of Operation See Section11.3, “Functional Description,” for a detailed description of SCI operation in the different modes. • 8- and 9- bit data modes • Stop modes — SCI is halted during all stop modes • Loop modes MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 171

Serial Communications Interface (S08SCIV1) 11.1.3 Block Diagram Figure11-2showsthetransmitterportionoftheSCI.(Figure 11-3showsthereceiverportionoftheSCI.) INTERNAL BUS (WRITE-ONLY) LOOPS SCID – Tx BUFFER RSRC LOOP TO RECEIVE M P RT CONTROL DATA IN O A ST 11-BIT TRANSMIT SHIFT REGISTER ST 1× BAUD H 8 7 6 5 4 3 2 1 0 L TO TxD PIN RATE CLOCK B SHIFT DIRECTION S L PPET GENPTAE8RRIATTYION OAD FROM SCIxD HIFT ENABLE REAMBLE (ALL 1s) REAK (ALL 0s) L S P B SCI CONTROLS TxD ENABLE TE TO TxD TRANSMIT CONTROL SBK TxD DIRECTION PIN LOGIC TXDIR TDRE TIE Tx INTERRUPT TC REQUEST TCIE Figure11-2. SCI Transmitter Block Diagram MC9S08GT16A/GT8A Data Sheet, Rev. 1 172 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) Figure11-3 shows the receiver portion of the SCI. INTERNAL BUS (READ-ONLY) SCID – Rx BUFFER 16× BAUD DIVIDE RATE CLOCK BY 16 T P R M TO 11-BIT RECEIVE SHIFT REGISTER SB TA S L S H 8 7 6 5 4 3 2 1 0 L FROM RxD PIN DATA RECOVERY s ALL 1 MSB SHIFT DIRECTION LOOPS SINGLE-WIRE WAKE WAKEUP RWU LOOP CONTROL LOGIC RSRC ILT FROM TRANSMITTER RDRF RIE Rx INTERRUPT IDLE REQUEST ILIE OR ORIE FE FEIE ERROR INTERRUPT REQUEST NF NEIE PE PARITY PF CHECKING PT PEIE Figure11-3. SCI Receiver Block Diagram MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 173

Serial Communications Interface (S08SCIV1) 11.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignments for all SCI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) ThispairofregisterscontrolstheprescaledivisorforSCIbaudrategeneration.Toupdatethe13-bitbaud ratesetting[SBR12:SBR0],firstwritetoSCIxBDHtobufferthehighhalfofthenewvalueandthenwrite to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written. SCIxBDLisresettoanon-zerovalue,soafterresetthebaudrategeneratorremainsdisableduntilthefirst time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1). 7 6 5 4 3 2 1 0 R 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-4. SCI Baud Rate Register (SCIxBDH) Table11-1. SCIxBDH Register Field Descriptions Field Description 4:0 BaudRateModuloDivisor—These13bitsarereferredtocollectivelyasBR,andtheysetthemodulodivide SBR[12:8] rate for the SCI baud rate generator. When BR=0, the SCI baud rate generator is disabled to reduce supply current. When BR=1 to 8191, the SCI baud rate=BUSCLK/(16×BR). See also BR bits inTable11-2. 7 6 5 4 3 2 1 0 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W Reset 0 0 0 0 0 1 0 0 Figure11-5. SCI Baud Rate Register (SCIxBDL) Table11-2. SCIxBDL Register Field Descriptions Field Description 7:0 BaudRateModuloDivisor—These13bitsarereferredtocollectivelyasBR,andtheysetthemodulodivide SBR[7:0] rate for the SCI baud rate generator. When BR=0, the SCI baud rate generator is disabled to reduce supply current. When BR=1 to 8191, the SCI baud rate=BUSCLK/(16×BR). See also BR bits inTable11-1. MC9S08GT16A/GT8A Data Sheet, Rev. 1 174 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) 11.2.2 SCI Control Register 1 (SCIxC1) This read/write register is used to control various optional features of the SCI system. 7 6 5 4 3 2 1 0 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W Reset 0 0 0 0 0 0 0 0 Figure11-6. SCI Control Register 1 (SCIxC1) Table11-3. SCIxC1 Register Field Descriptions Field Description 7 Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS LOOPS=1, the transmitter output is internally connected to the receiver input. 0 Normal operation — RxD and TxD use separate pins. 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by SCI. 6 SCI Stops in Wait Mode SCISWAI 0 SCIclockscontinuetoruninwaitmodesotheSCIcanbethesourceofaninterruptthatwakesuptheCPU. 1 SCI clocks freeze while CPU is in wait mode. 5 Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When RSRC LOOPS=1, the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output. 0 Provided LOOPS=1, RSRC=0 selects internal loop back mode and the SCI does not use the RxD pins. 1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input. 4 9-Bit or 8-Bit Mode Select M 0 Normal — start + 8 data bits (LSB first) + stop. 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (LSB first) + 9th data bit + stop. 3 Receiver Wakeup Method Select — Refer toSection11.3.3.2, “Receiver Wakeup Operation” for more WAKE information. 0 Idle-line wakeup. 1 Address-mark wakeup. 2 Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic1 bits at the end of a character ILT do not count toward the 10 or 11 bit times of the logic high level by the idle line detection logic. Refer to Section11.3.3.2.1, “Idle-Line Wakeup” for more information. 0 Idle character bit count starts after start bit. 1 Idle character bit count starts after stop bit. 1 ParityEnable—Enableshardwareparitygenerationandchecking.Whenparityisenabled,themostsignificant PE bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking. 1 Parity enabled. 0 ParityType—Providedparityisenabled(PE=1),thisbitselectsevenoroddparity.Oddparitymeansthetotal PT number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 175

Serial Communications Interface (S08SCIV1) 11.2.3 SCI Control Register 2 (SCIxC2) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R TIE TCIE RIE ILIE TE RE RWU SBK W Reset 0 0 0 0 0 0 0 0 Figure11-7. SCI Control Register 2 (SCIxC2) Table11-4. SCIxC2 Register Field Descriptions Field Description 7 Transmit Interrupt Enable (for TDRE) TIE 0 Hardware interrupts from TDRE disabled (use polling). 1 Hardware interrupt requested when TDRE flag is 1. 6 Transmission Complete Interrupt Enable (for TC) TCIE 0 Hardware interrupt requested when TC flag is 1. 1 Hardware interrupts from TC disabled (use polling). 5 Receiver Interrupt Enable (for RDRF) RIE 0 Hardware interrupts from RDRF disabled (use polling). 1 Hardware interrupt requested when RDRF flag is 1. 4 Idle Line Interrupt Enable (for IDLE) ILIE 0 Hardware interrupts from IDLE disabled (use polling). 1 Hardware interrupt requested when IDLE flag is 1. 3 Transmitter Enable TE 0 Transmitter off. 1 Transmitter on. TEmustbe1inordertousetheSCItransmitter.Normally,whenTE=1,theSCIforcestheTxDpintoactasan outputfortheSCIsystem.IfLOOPS=1andRSRC=0,theTxDpinrevertstobeingaportBgeneral-purpose I/O pin even if TE=1. When the SCI is configured for single-wire operation (LOOPS=RSRC=1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin). TEalsocanbeusedtoqueueanidlecharacterbywritingTE=0thenTE=1whileatransmissionisinprogress. Refer toSection11.3.2.1, “Send Break and Queued Idle,” for more details. WhenTEiswrittento0,thetransmitterkeepscontroloftheportTxDpinuntilanydata,queuedidle,orqueued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin. 2 Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. RE 0 Receiver off. 1 Receiver on. MC9S08GT16A/GT8A Data Sheet, Rev. 1 176 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) Table11-4. SCIxC2 Register Field Descriptions (continued) Field Description 1 Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it RWU waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle linebetweenmessages(WAKE=0,idle-linewakeup),oralogic1inthemostsignificantdatabitinacharacter (WAKE=1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware condition automatically clears RWU. Refer toSection11.3.3.2, “Receiver Wakeup Operation,” for more details. 0 Normal SCI receiver operation. 1 SCI receiver in standby waiting for wakeup condition. 0 SendBreak—Writinga1andthena0toSBKqueuesabreakcharacterinthetransmitdatastream.Additional SBK breakcharactersof10or11bittimesoflogic0arequeuedaslongasSBK=1.Dependingonthetimingofthe set and clear of SBK relative to the information currently being transmitted, a second break character may be queuedbeforesoftwareclearsSBK.RefertoSection11.3.2.1,“SendBreakandQueuedIdle,”formoredetails. 0 Normal transmitter operation. 1 Queue break character(s) to be sent. 11.2.4 SCI Status Register 1 (SCIxS1) Thisregisterhaseightread-onlystatusflags.Writeshavenoeffect.Specialsoftwaresequences(whichdo not involve writing to this register) are used to clear these status flags. 7 6 5 4 3 2 1 0 R TDRE TC RDRF IDLE OR NF FE PF W Reset 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-8. SCI Status Register 1 (SCIxS1) Table11-5. SCIxS1 Register Field Descriptions Field Description 7 Transmit Data Register Empty Flag — TDRE is set immediately after reset and when a transmit data value TDRE transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIxS1 with TDRE=1 and then write to the SCI data register (SCIxD). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty. 6 TransmissionCompleteFlag—TCissetimmediatelyafterresetandwhenTDRE=1andnodata,preamble, TC or break character is being transmitted. 0 Transmitter active (sending data, a preamble, or a break). 1 Transmitter idle (transmission activity complete). TC is cleared automatically by reading SCIxS1 with TC=1 and then doing one of the following three things: • Write to the SCI data register (SCIxD) to transmit new data • Queue a preamble by changing TE from 0 to 1 • Queue a break character by writing 1 to SBK in SCIxC2 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 177

Serial Communications Interface (S08SCIV1) Table11-5. SCIxS1 Register Field Descriptions (continued) Field Description 5 ReceiveDataRegisterFullFlag—RDRFbecomessetwhenacharactertransfersfromthereceiveshifterinto RDRF the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data register (SCIxD). 0 Receive data register empty. 1 Receive data register full. 4 Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of IDLE activity. When ILT=0, the receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times dependingontheMcontrolbit)neededforthereceivertodetectanidleline.WhenILT=1,thereceiverdoesn’t start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the previouscharacterdonotcounttowardthefullcharactertimeoflogichighneededforthereceivertodetectan idle line. To clear IDLE, read SCIxS1 with IDLE=1 and then read the SCI data register (SCIxD). After IDLE has been cleared,itcannotbecomesetagainuntilafteranewcharacterhasbeenreceivedandRDRFhasbeenset.IDLE will get set only once even if the receive line remains idle for an extended period. 0 No idle line detected. 1 Idle line was detected. 3 ReceiverOverrunFlag—ORissetwhenanewserialcharacterisreadytobetransferredtothereceivedata OR register (buffer), but the previously received character has not been read from SCIxD yet. In this case, the new character(andallassociatederrorinformation)islostbecausethereisnoroomtomoveitintoSCIxD.Toclear OR, read SCIxS1 with OR=1 and then read the SCI data register (SCIxD). 0 No overrun. 1 Receive overrun (new SCI data lost). 2 NoiseFlag—Theadvancedsamplingtechniqueusedinthereceivertakessevensamplesduringthestartbit NF andthreesamplesineachdatabitandthestopbit.Ifanyofthesesamplesdisagreeswiththerestofthesamples within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No noise detected. 1 Noise detected in the received character in SCIxD. 1 FramingErrorFlag—FEissetatthesametimeasRDRFwhenthereceiverdetectsalogic0wherethestop FE bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE=1 and then read the SCI data register (SCIxD). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error. 0 Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE=1) and the parity bit in PF the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No parity error. 1 Parity error. MC9S08GT16A/GT8A Data Sheet, Rev. 1 178 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) 11.2.5 SCI Status Register 2 (SCIxS2) This register has one read-only status flag. Writes have no effect. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 RAF W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-9. SCI Status Register 2 (SCIxS2) Table11-6. SCIxS2 Register Field Descriptions Field Description 0 ReceiverActiveFlag—RAFissetwhentheSCIreceiverdetectsthebeginningofavalidstartbit,andRAFis RAF cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an SCI character is being received before instructing the MCU to go to stop mode. 0 SCI receiver idle waiting for a start bit. 1 SCI receiver active (RxD input not idle). 11.2.6 SCI Control Register 3 (SCIxC3) 7 6 5 4 3 2 1 0 R R8 0 T8 TXDIR ORIE NEIE FEIE PEIE W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-10. SCI Control Register 3 (SCIxC3) Table11-7. SCIxC3 Register Field Descriptions Field Description 7 Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M=1), R8 can be thought of as a R8 ninthreceivedatabittotheleftoftheMSBofthebuffereddataintheSCIxDregister.Whenreading9-bitdata, read R8 before reading SCIxD because reading SCIxD completes automatic flag clearing sequences which could allow R8 and SCIxD to be overwritten with new data. 6 NinthDataBitforTransmitter—WhentheSCIisconfiguredfor9-bitdata(M=1),T8maybethoughtofasa T8 ninthtransmitdatabittotheleftoftheMSBofthedataintheSCIxDregister.Whenwriting9-bitdata,theentire 9-bit value is transferred to the SCI shift register after SCIxD is written so T8 should be written (if it needs to change from its previous value) before SCIxD is written. If T8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time SCIxD is written. 5 TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation TXDIR (LOOPS=RSRC=1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 179

Serial Communications Interface (S08SCIV1) Table11-7. SCIxC3 Register Field Descriptions (continued) Field Description 3 Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. ORIE 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR=1. 2 Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests. NEIE 0 NF interrupts disabled (use polling). 1 Hardware interrupt requested when NF=1. 1 Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt FEIE requests. 0 FE interrupts disabled (use polling). 1 Hardware interrupt requested when FE=1. 0 Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt PEIE requests. 0 PF interrupts disabled (use polling). 1 Hardware interrupt requested when PF=1. 11.2.7 SCI Data Register (SCIxD) This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags. 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 0 0 0 0 0 Figure11-11. SCI Data Register (SCIxD) MC9S08GT16A/GT8A Data Sheet, Rev. 1 180 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) 11.3 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices,includingotherMCUs.TheSCIcomprisesabaudrategenerator,transmitter,andreceiverblock. Thetransmitterandreceiveroperateindependently,althoughtheyusethesamebaudrategenerator.During normaloperation,theMCUmonitorsthestatusoftheSCI,writesthedatatobetransmitted,andprocesses received data. The following describes each of the blocks of the SCI. 11.3.1 Baud Rate Generation As shown inFigure11-12, the clock source for the SCI baud rate generator is the bus-rate clock. MODULO DIVIDE BY (1 THROUGH 8191) DIVIDE BY BUSCLK SBR12:SBR0 16 Tx BAUD RATE Rx SAMPLING CLOCK BAUD RATE GENERATOR (16× BAUD RATE) OFF IF [SBR12:SBR0] =0 BUSCLK BAUD RATE = [SBR12:SBR0]× 16 Figure11-12. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independentclocksources)tousethesamebaudrate.Allowedtoleranceonthisbaudfrequencydepends onthedetailsofhowthereceiversynchronizestotheleadingedgeofthestartbitandhowbitsamplingis performed. TheMCUresynchronizestobitboundariesoneveryhigh-to-lowtransition,butintheworstcase,thereare no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus frequencyisdrivenbyacrystal,theallowedbaudratemismatchisabout±4.5percentfor8-bitdataformat and about±4 percent for 9-bit data format. Although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 11.3.2 Transmitter Functional Description This section describes the overall block diagram for the SCI transmitter (Figure11-2), as well as specialized functions for sending break and idle characters. The transmitter is enabled by setting the TE bit in SCIxC2. This queues a preamble character that is one fullcharacterframeoftheidlestate.Thetransmitterthenremainsidleuntildataisavailableinthetransmit data buffer. Programs store data into the transmit data buffer by writing to the SCI data register (SCIxD). The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the M control bit. For the remainder of this section, we will assume M = 0, selectingthenormal8-bitdatamode.In8-bitdatamode,theshiftregisterholdsastartbit,eightdatabits, and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 181

Serial Communications Interface (S08SCIV1) thetransmitdataregisteristransferredtotheshiftregister(synchronizedwiththebaudrateclock)andthe transmit data register empty (TDRE) status flag is set to indicate another character may be written to the transmit data buffer at SCIxD. If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD1 pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD1 high, waiting for more characters to transmit. Writing0toTEdoesnotimmediatelyreleasethepintobeageneral-purposeI/Opin.Anytransmitactivity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 11.3.2.1 Send Break and Queued Idle The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times includingthestartandstopbits).Normally,aprogramwouldwaitforTDREtobecomesettoindicatethe lastcharacterofamessagehasmovedtothetransmitshifter,thenwrite1andthenwrite0totheSBKbit. Thisactionqueuesabreakcharactertobesentassoonastheshifterisavailable.IfSBKisstill1whenthe queuedbreakmovesintotheshifter(synchronizedtothebaudrateclock),anadditionalbreakcharacteris queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data bits and a framing error (FE= 1) occurs. Whenidle-linewakeupisused,afullcharactertimeofidle(logic1)isneededbetweenmessagestowake up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last characterofamessagehasmovedtothetransmitshifter,thenwrite0andthenwrite1totheTEbit.This actionqueuesanidlecharactertobesentassoonastheshifterisavailable.Aslongasthecharacterinthe shifterdoesnotfinishwhileTE= 0,theSCItransmitterneveractuallyreleasescontroloftheTxD1pin.If there is a possibility of the shifter finishing while TE =0, set the general-purpose I/O controls so the pin that is shared with TxD1 is an output driving a logic 1. This ensures that the TxD1 line will look like a normal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE. 11.3.3 Receiver Functional Description In this section, the data sampling technique used to reconstruct receiver data is described in more detail; two variations of the receiver wakeup function are explained. (The receiver block diagram is shown in Figure11-3.) ThereceiverisenabledbysettingtheREbitinSCIxC2.Characterframesconsistofastartbitoflogic0, eight(ornine)databits(LSBfirst),andastopbitoflogic1.Forinformationabout9-bitdatamode,refer toSection11.3.5.1,“8-and9-BitDataModes.”Fortheremainderofthisdiscussion,weassumetheSCI is configured for normal 8-bit data mode. Afterreceivingthestopbitintothereceiveshifter,andprovidedthereceivedataregisterisnotalreadyfull, thedatacharacteristransferredtothereceivedataregisterandthereceivedataregisterfull(RDRF)status flagisset.IfRDRFwasalreadysetindicatingthereceivedataregister(buffer)wasalreadyfull,theoverrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program MC9S08GT16A/GT8A Data Sheet, Rev. 1 182 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) hasonefullcharactertimeafterRDRFissetbeforethedatainthereceivedatabuffermustbereadtoavoid a receiver overrun. Whenaprogramdetectsthatthereceivedataregisterisfull(RDRF= 1),itgetsthedatafromthereceive data register by reading SCIxD. The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s program that handles receive data. Refer toSection11.3.4, “Interrupts and Status Flags,” for more details about flag clearing. 11.3.3.1 Data Sampling Technique TheSCIreceiverusesa16×baudrateclockforsampling.Thereceiverstartsbytakinglogiclevelsamples at 16 times the baud rate to search for a falling edge on the RxD1 serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock is used to dividethebittimeinto16segmentslabeledRT1throughRT16.Whenafallingedgeislocated,threemore samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determinethelogiclevelforthatbit.Thelogiclevelisinterpretedtobethatofthemajorityofthesamples takenduringthebittime.Inthecaseofthestartbit,thebitisassumedtobe0ifatleasttwoofthesamples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive data buffer. Thefallingedgedetectionlogiccontinuouslylooksforfallingedges,andifanedgeisdetected,thesample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. Inthecaseofaframingerror,providedthereceivedcharacterwasnotabreakcharacter,thesamplinglogic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. Inthecaseofaframingerror,thereceiverisinhibitedfromreceivinganynewcharactersuntiltheframing error flag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set. 11.3.3.2 Receiver Wakeup Operation Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU= 1, it inhibitssettingofthestatusflagsassociatedwiththereceiver,thuseliminatingthesoftwareoverheadfor handling the unimportant message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 183

Serial Communications Interface (S08SCIV1) 11.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automaticallywhenthereceiverdetectsafullcharactertimeoftheidle-linelevel.TheMcontrolbitselects 8-bitor9-bitdatamodethatdetermineshowmanybittimesofidleareneededtoconstituteafullcharacter time (10 or 11 bit times because of the start and stop bits). WhentheRWUbitisset,theidlecharacterthatwakesareceiverdoesnotsetthereceiveridlebit,IDLE, or the receive data register full flag, RDRF. It therefore will not generate an interrupt when this idle characteroccurs.ThereceiverwillwakeupandwaitforthenextdatatransmissionwhichwillsetRDRF and generate an interrupt if enabled. The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward thefullcharactertimeofidle.WhenILT=1,theidlebitcounterdoesnotstartuntilafterastopbittime, so the idle detection is not affected by the data in the last character of the previous message. 11.3.3.2.2 Address-Mark Wakeup When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared automaticallywhenthereceiverdetectsalogic1inthemostsignificantbitofareceivedcharacter(eighth bit in M = 0 mode and ninth bit in M = 1 mode). Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. The logic 1 MSB of an address frame clears the receivers RWU bit before the stop bit is received and sets the RDRF flag. 11.3.4 Interrupts and Status Flags TheSCIsystemhasthreeseparateinterruptvectorstoreducetheamountofsoftwareneededtoisolatethe cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events. Another interrupt vector is associated with the receiver for RDRF and IDLE events, and a third vector is used for OR, NF, FE, and PF error conditions. Each of these eight interrupt sources can be separately maskedbylocalinterruptenablemasks.Theflagscanstillbepolledbysoftwarewhenthelocalmasksare cleared to disable generation of hardware interrupt requests. TheSCItransmitterhastwostatusflagsthatoptionallycangeneratehardwareinterruptrequests.Transmit data register empty (TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished transmittingalldata,preamble,andbreakcharactersandisidlewithTxD1high.Thisflagisoftenusedin systemswithmodemstodeterminewhenitissafetoturnoffthemodem.Ifthetransmitcompleteinterrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC= 1. Instead of hardware interrupts,softwarepollingmaybeusedtomonitortheTDREandTCstatusflagsifthecorrespondingTIE or TCIE local interrupt masks are 0s. Whenaprogramdetectsthatthereceivedataregisterisfull(RDRF= 1),itgetsthedatafromthereceive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF =1 and then reading SCIxD. MC9S08GT16A/GT8A Data Sheet, Rev. 1 184 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardwareinterruptsareused,SCIxS1mustbereadintheinterruptserviceroutine(ISR).Normally,thisis done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied. TheIDLEstatusflagincludeslogicthatpreventsitfromgettingsetrepeatedlywhentheRxD1lineremains idleforanextendedperiodoftime.IDLEisclearedbyreadingSCIxS1whileIDLE = 1andthenreading SCIxD.AfterIDLEhasbeencleared,itcannotbecomesetagainuntilthereceiverhasreceivedatleastone new character and has set RDRF. IftheassociatederrorwasdetectedinthereceivedcharacterthatcausedRDRFtobeset,theerrorflags— noiseflag(NF),framingerror(FE),andparityerrorflag(PF)—getsetatthesametimeasRDRF.These flags are not set in overrun cases. If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (OR) flag gets set instead and the data and any associated NF, FE, or PF condition is lost. 11.3.5 Additional SCI Functions The following sections describe additional SCI functions. 11.3.5.1 8- and 9-Bit Data Modes The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the M control bit in SCIxC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data register. For the transmit data buffer, this bit is stored in T8 in SCIxC3. For the receiver, the ninth bit is held in R8 in SCIxC3. For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCIxD. Ifthebitvaluetobetransmittedastheninthbitofanewcharacteristhesameasforthepreviouscharacter, it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data is transferred from SCIxD to the shifter. 9-bitdatamodetypicallyisusedinconjunctionwithparitytoalloweightbitsofdataplustheparityinthe ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker. 11.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. Instop1andstop2modes,allSCIregisterdataislostandmustbere-initializeduponrecoveryfromthese two stop modes. No SCI module registers are affected in stop3 mode. Because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode).Softwareshouldensurestopmodeisnotenteredwhilethereisacharacterbeingtransmittedoutof or received into the SCI module. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 185

Serial Communications Interface (S08SCIV1) 11.3.5.3 Loop Mode When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC= 1). Loop mode is sometimes used to check software, independent of connectionsintheexternalsystem,tohelpisolatesystemproblems.Inthismode,thetransmitteroutputis internally connected to the receiver input and the RxD1 pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. 11.3.5.4 Single-Wire Operation When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC= 1). Single-wire mode is used to implement a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the TxD1 pin. The RxD1 pin is not used and reverts to a general-purpose port I/O pin. Insingle-wiremode,theTXDIRbitinSCIxC3controlsthedirectionofserialdataontheTxD1pin.When TXDIR= 0, the TxD1 pin is an input to the SCI receiver and the transmitter is temporarily disconnected fromtheTxD1pinsoanexternaldevicecansendserialdatatothereceiver.WhenTXDIR= 1,theTxD1 pinisanoutputdrivenbythetransmitter.Insingle-wiremode,theinternalloopbackconnectionfromthe transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. MC9S08GT16A/GT8A Data Sheet, Rev. 1 186 Freescale Semiconductor

Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.1 Introduction The MC9S08GT16A/GT8A provides one serial peripheral interface (SPI) module. The four pins associated with SPI functionality are shared with port E pins 2–5. See the AppendixA, “Electrical Characteristics,” appendix for SPI electrical parametric information. When the SPI is enabled, the directionofpinsiscontrolledbymoduleconfiguration.IftheSPIisdisabled,allfourpinscanbeusedas general-purpose I/O. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 187

Serial Peripheral Interface (S08SPIV3) VREFLVREFHVSSADVDDAD 4 HCS08 CORE BKGD 8IN-BTIETR KREUYPBTO (AKRBDI) 8 PORT A 4 PPPTTTAAA347///KKKBBBIIIPPP347–– NOTE 6 PTA0/KBIP0 CPU BDC 4 10-BIT 8 T B PPTTBB74//AADDPP74– ANALOG-TO-DIGITAL OR 4 HCS08 SYSTEM CONTROL CONVERTER (ATD) P PTB3/ADP3– RESET PTB0/ADP0 NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION PTC7 POWER MANAGEMENT PTC6 PTC5 RTI COP INTER-IC (IIC) SSDCAL PORT C PPPTTTCCC432//SSCDAL NOTE 5 IRQ IRQ LVD RXD2 NOTES 2, 3 SERIAL COMMUNICATIONS PTC1/RxD2 TXD2 INTERFACE (SCI2) PTC0/TxD2 CH1 USER FLASH 2-CHANNEL TIMER/PWM PTD4/TPM2CH1 CH0 (GT16A = 16,384 BYTES) (TPM2) PTD3/TPM2CLK/TPM2CH0 (GT8A = 8192 BYTES) D CH0 RT O PTD2/TPM1CH2 3-CHANNEL TIMER/PWM CH1 P PTD1/TPM1CH1 (TPM1) CH2 PTD0/TPM1CLK/TPM1CH0 USER RAM (GT16A = 2048 BYTES) SPSCK (GT8A = 1024 BYTES) PTE5/SPSCK MOSI SERIAL PERIPHERAL PTE4/MOSI MISO ON-CHIP ICE INTERFACE (SPI) SS RT E PPTTEE32//SMSISO DEBUG O RXD1 P MODULE (DBG) SERIAL COMMUNICATIONS PTE1/RxD1 TXD1 INTERFACE (SCI1) PTE0/TxD1 INTERNAL CLOCK GENERATOR (ICG) PTG3 EXTAL G PTG2/EXTAL XTAL T LOW-POWER OSCILLATOR R PTG1/XTAL BKGD O P PTG0/BKGD/MS V DD VOLTAGE V SS REGULATOR = Pins not available in 44-, 42-, or 32-pin packages V SS = Pins not available in 42- or 32-pin packages = Pins not available in 32-pin packages NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE=1). 3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD. 4. Pin contains integrated pullup device. 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1). Figure12-1. Block Diagram Highlighting the SPI Module MC9S08GT16A/GT8A Data Sheet, Rev. 1 188 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) Module Initialization (Slave): Write: SPIC1 to configure interrupts,setprimarySPIoptions,slavemodeselect,and system enable. Write: SPIC2 to configure optional SPI features Module Initialization (Master): Write: SPIC1 to configure interrupts, set primary SPI options, master mode select, and system enable. Write: SPIC2 to configure optional SPI features Write: SPIBR to set baud rate Module Use: After SPI master initiates transfer by checking that SPTEF = 1 and then writing data to SPID: Wait for SPTEF, then write to SPID Wait for SPRF, then read from SPID ModefaultdetectioncanbeenabledformastermodeincaseswheremorethanoneSPIdevicemightbecomeamaster at the same time. SPIC1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE Module/interrupt enables and configuration SPIC2 MODFEN BIDIROE SPISWAI SPC0 Additional configuration options. SPIBR SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud rate = (BUSCLK/SPPR[2:0])/SPR2[2:0] SPID Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIS SPRF SPTEF MODF Figure12-2. SPI Module Quick Start 12.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 189

Serial Peripheral Interface (S08SPIV3) 12.1.2 Block Diagrams ThissectionincludesblockdiagramsshowingSPIsystemconnections,theinternalorganizationoftheSPI module, and the SPI clock dividers that control the master mode bit rate. 12.1.2.1 SPI System Block Diagram Figure12-3 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master deviceinitiatesallSPIdatatransfers.Duringatransfer,themastershiftsdataout(ontheMOSIpin)tothe slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively exchangesthedatathatwasintheSPIshiftregistersofthetwoSPIsystems.TheSPSCKsignalisaclock output from the master and an input to the slave. The slave device must be selected by a low level on the slaveselectinput(SSpin).Inthissystem,themasterdevicehasconfigureditsSSpinasanoptionalslave select output. MASTER SLAVE MOSI MOSI SPI SHIFTER SPI SHIFTER 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MISO MISO SPSCK SPSCK CLOCK GENERATOR SS SS Figure12-3. SPI System Connections The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure12-3showsasystemwheredataisexchangedbetweentwoMCUs,manypracticalsystemsinvolve simplerconnectionswheredataisunidirectionallytransferredfromthemasterMCUtoaslaveorfroma slave to the master MCU. 12.1.2.2 SPI Module Block Diagram Figure12-4isablockdiagramoftheSPImodule.ThecentralelementoftheSPIistheSPIshiftregister. Data is written to the double-buffered transmitter (write to SPID) and gets transferred to the SPI shift register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from SPID). Pin multiplexing logic controls connections between MCU pins and the SPI module. MC9S08GT16A/GT8A Data Sheet, Rev. 1 190 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) WhentheSPIisconfiguredasamaster,theclockoutputisroutedtotheSPSCKpin,theshifteroutputis routed to MOSI, and the shifter input is routed from the MISO pin. When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin. IntheexternalSPIsystem,simplyconnectallSPSCKpinstoeachother,allMISOpinstogether,andall MOSI pins together. Peripheral devices often use slightly different names for these pins. PIN CONTROL M MOSI SPE S (MOMI) Tx BUFFER (WRITE SPID) ENABLE SPI SYSTEM M MISO SHIFT SPI SHIFT REGISTER SHIFT S (SISO) OUT IN SPC0 Rx BUFFER (READ SPID) BIDIROE SHIFT SHIFT Rx BUFFER Tx BUFFER LSBFE DIRECTION CLOCK FULL EMPTY MASTER CLOCK M BUS RATE SPIBR CLOCK SPSCK CLOCK CLOCK GENERATOR LOGIC SLAVE CLOCK S MASTER/SLAVE MASTER/ MSTR MODE SELECT SLAVE MODFEN SSOE MODE FAULT SS DETECTION SPRF SPTEF SPTIE SPI INTERRUPT MODF REQUEST SPIE Figure12-4. SPI Module Block Diagram 12.1.3 SPI Baud Rate Generation As shown inFigure12-5, the clock source for the SPI baud rate generator is the bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal SPI master mode bit-rate clock. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 191

Serial Peripheral Interface (S08SPIV3) PRESCALER CLOCK RATE DIVIDER DIVIDE BY DIVIDE BY MASTER BUS CLOCK SPI 1, 2, 3, 4, 5, 6, 7, or 8 2, 4, 8, 16, 32, 64, 128, or 256 BIT RATE SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 Figure12-5. SPI Baud Rate Generation 12.2 External Signal Description TheSPIoptionallysharesfourportpins.ThefunctionofthesepinsdependsonthesettingsofSPIcontrol bits.WhentheSPIisdisabled(SPE=0),thesefourpinsreverttobeinggeneral-purposeportI/Opinsthat are not controlled by the SPI. 12.2.1 SPSCK — SPI Serial Clock WhentheSPIisenabledasaslave,thispinistheserialclockinput.WhentheSPIisenabledasamaster, this pin is the serial clock output. 12.2.2 MOSI — Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0= 0, this pin is the serial data input.IfSPC0 = 1toselectsingle-wirebidirectionalmode,andmastermodeisselected,thispinbecomes thebidirectionaldataI/Opin(MOMI).Also,thebidirectionalmodeoutputenablebitdetermineswhether the pin acts as an input (BIDIROE= 0) or an output (BIDIROE = 1). If SPC0= 1 and slave mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 12.2.3 MISO — Master Data In, Slave Data Out When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data input. When the SPI is enabled as a slave and SPC0= 0, this pin is the serial data output.IfSPC0 = 1toselectsingle-wirebidirectionalmode,andslavemodeisselected,thispinbecomes thebidirectionaldataI/Opin(SISO)andthebidirectionalmodeoutputenablebitdetermineswhetherthe pinactsasaninput(BIDIROE= 0)oranoutput(BIDIROE= 1).IfSPC0 = 1andmastermodeisselected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 12.2.4 SS — Slave Select WhentheSPIisenabledasaslave,thispinisthelow-trueslaveselectinput.WhentheSPIisenabledas amasterandmodefaultenableisoff(MODFEN =0),thispinisnotusedbytheSPIandrevertstobeing a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select outputenablebitdetermineswhetherthispinactsasthemodefaultinput(SSOE= 0)orastheslaveselect output (SSOE = 1). MC9S08GT16A/GT8A Data Sheet, Rev. 1 192 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) 12.3 Modes of Operation 12.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. Duringeitherstop1orstop2mode,theSPImodulewillbefullypowereddown.Uponwake-upfromstop1 orstop2mode,theSPImodulewillbeintheresetstate.Duringstop3mode,clockstotheSPImoduleare halted. No registers are affected. If stop3 is exited with a reset, the SPI will be put into its reset state. If stop3 is exited with an interrupt, the SPI continues from the state it was in when stop3 was entered. 12.4 Register Definition The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for transmit/receive data. Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignmentsforallSPIregisters.Thissectionreferstoregistersandcontrolbitsonlybytheirnames,and a Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 12.4.1 SPI Control Register 1 (SPIC1) This read/write register includes the SPI enable control, interrupt enables, and configuration options. 7 6 5 4 3 2 1 0 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W Reset 0 0 0 0 0 1 0 0 Figure12-6. SPI Control Register 1 (SPIC1) Table12-1. SPIC1 Field Descriptions Field Description 7 SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF) SPIE and mode fault (MODF) events. 0 Interrupts from SPRF and MODF inhibited (use polling) 1 When SPRF or MODF is 1, request a hardware interrupt 6 SPI System Enable — Disabling the SPI halts any transfer that is in progress and initializes internal state SPE machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty. 0 SPI system inactive 1 SPI system enabled 5 SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). SPTIE 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 193

Serial Peripheral Interface (S08SPIV3) Table12-1. SPIC1 Field Descriptions (continued) Field Description 4 Master/Slave Mode Select MSTR 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 ClockPolarity—ThisbiteffectivelyplacesaninverterinserieswiththeclocksignalfromamasterSPIortoa CPOL slave SPI device. Refer toSection12.5.1, “SPI Clock Formats” for more details. 0 Active-high SPI clock (idles low) 1 Active-low SPI clock (idles high) 2 Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral CPHA devices. Refer toSection12.5.1, “SPI Clock Formats” for more details. 0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer 1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer 1 Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in SSOE SPIC2 and the master/slave (MSTR) control bit to determine the function of theSS pin as shown inTable12-2. 0 LSB First (Shifter Direction) LSBFE 0 SPI serial data transfers start with most significant bit 1 SPI serial data transfers start with least significant bit Table12-2.SS Pin Function MODFEN SSOE Master Mode Slave Mode 0 0 General-purpose I/O (not SPI) Slave select input 0 1 General-purpose I/O (not SPI) Slave select input 1 0 SS input for mode fault Slave select input 1 1 AutomaticSS output Slave select input 12.4.2 SPI Control Register 2 (SPIC2) This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not implemented and always read 0. 7 6 5 4 3 2 1 0 R 0 0 0 0 MODFEN BIDIROE SPISWAI SPC0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure12-7. SPI Control Register 2 (SPIC2) MC9S08GT16A/GT8A Data Sheet, Rev. 1 194 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) Table12-3. SPIC2 Register Field Descriptions Field Description 4 MasterMode-FaultFunctionEnable—WhentheSPIisconfiguredforslavemode,thisbithasnomeaningor MODFEN effect. (TheSS pin is the slave select input.) In master mode, this bit determines how theSS pin is used (refer toTable12-2 for more details). 0 Mode fault function disabled, masterSS pin reverts to general-purpose I/O not controlled by SPI 1 Mode fault function enabled, masterSS pin acts as the mode fault input or the slave select output 3 Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0)=1, BIDIROE BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO (SISO) pin, respectively, as the single SPI data I/O pin. When SPC0=0, BIDIROE has no meaning or effect. 0 Output driver disabled so SPI data I/O pin acts as an input 1 SPI I/O pin enabled as an output 1 SPI Stop in Wait Mode SPISWAI 0 SPI clocks continue to operate in wait mode 1 SPI clocks stop when the MCU enters wait mode 0 SPIPinControl0—TheSPC0bitchoosessingle-wirebidirectionalmode.IfMSTR=0(slavemode),theSPI SPC0 uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR=1 (master mode), the SPI uses the MOSI(MOMI)pinforbidirectionalSPIdatatransfers.WhenSPC0=1,BIDIROEisusedtoenableordisablethe output driver for the single bidirectional SPI I/O pin. 0 SPI uses separate pins for data input and data output 1 SPI configured for single-wire bidirectional operation 12.4.3 SPI Baud Rate Register (SPIBR) ThisregisterisusedtosettheprescalerandbitratedivisorforanSPImaster.Thisregistermaybereador written at any time. 7 6 5 4 3 2 1 0 R 0 0 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure12-8. SPI Baud Rate Register (SPIBR) Table12-4. SPIBR Register Field Descriptions Field Description 6:4 SPIBaudRatePrescaleDivisor—This3-bitfieldselectsoneofeightdivisorsfortheSPIbaudrateprescaler SPPR[2:0] asshowninTable12-5.Theinputtothisprescaleristhebusrateclock(BUSCLK).Theoutputofthisprescaler drives the input of the SPI baud rate divider (seeFigure12-5). 2:0 SPIBaudRateDivisor—This3-bitfieldselectsoneofeightdivisorsfortheSPIbaudratedividerasshownin SPR[2:0] Table12-6.TheinputtothisdividercomesfromtheSPIbaudrateprescaler(seeFigure12-5).Theoutputofthis divider is the SPI bit rate clock for master mode. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 195

Serial Peripheral Interface (S08SPIV3) Table12-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table12-6. SPI Baud Rate Divisor SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 12.4.4 SPI Status Register (SPIS) Thisregisterhasthreeread-onlystatusbits.Bits6,3,2,1,and0arenotimplementedandalwaysread0. Writes have no meaning or effect. 7 6 5 4 3 2 1 0 R SPRF 0 SPTEF MODF 0 0 0 0 W Reset 0 0 1 0 0 0 0 0 = Unimplemented or Reserved Figure12-9. SPI Status Register (SPIS) MC9S08GT16A/GT8A Data Sheet, Rev. 1 196 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) Table12-7. SPIS Register Field Descriptions Field Description 7 SPIReadBufferFullFlag—SPRFissetatthecompletionofanSPItransfertoindicatethatreceiveddatamay SPRF bereadfromtheSPIdataregister(SPID).SPRFisclearedbyreadingSPRFwhileitisset,thenreadingtheSPI data register. 0 No data available in the receive data buffer 1 Data available in the receive data buffer 5 SPITransmitBufferEmptyFlag—Thisbitissetwhenthereisroominthetransmitdatabuffer.Itisclearedby SPTEF readingSPISwithSPTEFset,followedbywritingadatavaluetothetransmitbufferatSPID.SPISmustberead withSPTEF=1beforewritingdatatoSPIDortheSPIDwritewillbeignored.SPTEFgeneratesanSPTEFCPU interruptrequestiftheSPTIEbitintheSPIC1isalsoset.SPTEFisautomaticallysetwhenadatabytetransfers fromthetransmitbufferintothetransmitshiftregister.ForanidleSPI(nodatainthetransmitbufferortheshift register and no transfer in progress), data written to SPID is transferred to the shifter almost immediately so SPTEFissetwithintwobuscyclesallowingasecond8-bitdatavaluetobequeuedintothetransmitbuffer.After completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and SPTEF will be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter. 0 SPI transmit buffer not empty 1 SPI transmit buffer empty 4 Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes MODF low,indicatingsomeotherSPIdeviceisalsoconfiguredasamaster.TheSSpinactsasamodefaulterrorinput only when MSTR=1, MODFEN=1, and SSOE=0; otherwise, MODF will never be set. MODF is cleared by reading MODF while it is 1, then writing to SPI control register 1 (SPIC1). 0 No mode fault error 1 Mode fault error detected 12.4.5 SPI Data Register (SPID) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure12-10. SPI Data Register (SPID) Readsofthisregisterreturnthedatareadfromthereceivedatabuffer.Writestothisregisterwritedatato the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data buffer initiates an SPI transfer. Data should not be written to the transmit data buffer unless the SPI transmit buffer empty flag (SPTEF) is set, indicating there is room in the transmit buffer to queue a new transmit byte. DatamaybereadfromSPIDanytimeafterSPRFissetandbeforeanothertransferisfinished.Failureto read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 197

Serial Peripheral Interface (S08SPIV3) 12.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF =1) and then writingabyteofdatatotheSPIdataregister(SPID)inthemasterSPIdevice.WhentheSPIshiftregister isavailable,thisbyteofdataismovedfromthetransmitdatabuffertotheshifter,SPTEFissettoindicate thereisroominthebuffertoqueueanothertransmitcharacterifdesired,andtheSPIserialtransferstarts. DuringtheSPItransfer,dataissampled(read)ontheMISOpinatoneSPSCKedgeandshifted,changing thebitvalueontheMOSIpin,one-halfSPSCKcyclelater.AftereightSPSCKcycles,thedatathatwasin theshiftregisterofthemasterhasbeenshiftedouttheMOSIpintotheslavewhileeightbitsofdatawere shiftedintheMISOpinintothemaster’sshiftregister.Attheendofthistransfer,thereceiveddatabyteis moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read by reading SPID. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved into the shifter, SPTEF is set, and a new transfer is started. Normally, SPI data is transferred most significant bit (MSB) first. If the least significant bit first enable (LSBFE) bit is set, SPI data is shifted LSB first. When the SPI is configured as a slave, itsSS pin must be driven low before a transfer starts andSS must stay low throughout the transfer. If a clock format where CPHA =0 is selected,SS must be driven to a logic1betweensuccessivetransfers.IfCPHA =1,SSmayremainlowbetweensuccessivetransfers.See Section12.5.1, “SPI Clock Formats” for more details. Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffer, and a previously received character can be in the receive data buffer while a new character is being shifted in. The SPTEF flag indicates when the transmit buffer has room for a new character. The SPRF flag indicates when a received character is available in the receive data buffer. The received character must be read out of the receive buffer (read SPID) before the next transfer is finished or a receive overrun error results. In the case of a receive overrun, the new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. There is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 12.5.1 SPI Clock Formats To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses between two different clock phase relationships between the clock and data. Figure12-11 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are shownforreferencewithbit1startingatthefirstSPSCKedgeandbit8endingone-halfSPSCKcycleafter the sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending onthesettinginLSBFE.BothvariationsofSPSCKpolarityareshown,butonlyoneofthesewaveforms appliesforaspecifictransfer,dependingonthevalueinCPOL.TheSAMPLEINwaveformappliestothe MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output MC9S08GT16A/GT8A Data Sheet, Rev. 1 198 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) pin from a master and the MISO waveform applies to the MISO output from a slave. TheSS OUT waveformappliestotheslaveselectoutputfromamaster(providedMODFENandSSOE= 1).Themaster SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. TheSSIN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL=0) SPSCK (CPOL=1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 BIT 6 ... BIT 2 BIT 1 BIT 0 LSB FIRST BIT 0 BIT 1 ... BIT 5 BIT 6 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure12-11. SPI Clock Formats (CPHA = 1) WhenCPHA = 1,theslavebeginstodriveitsMISOoutputwhenSSgoestoactivelow,butthedataisnot defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the thirdSPSCKedge,theSPIshiftershiftsonebitpositionwhichshiftsinthebitvaluethatwasjustsampled, andshiftstheseconddatabitvalueouttheotherendoftheshiftertotheMOSIandMISOoutputsofthe master and slave, respectively. When CHPA= 1, the slave’sSS input is not required to go to its inactive high level between transfers. Figure12-12 shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are shownforreferencewithbit1startingastheslaveisselected(SSINgoeslow),andbit8endsatthelast SPSCKedge. TheMSB firstandLSB firstlines show theorderofSPIdatabitsdependingonthesetting MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 199

Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specifictransfer,dependingonthevalueinCPOL.TheSAMPLEINwaveformappliestotheMOSIinput of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a masterandtheMISOwaveformappliestotheMISOoutputfromaslave.TheSSOUTwaveformapplies totheslaveselectoutputfromamaster(providedMODFENandSSOE= 1).ThemasterSSoutputgoes toactivelowatthestartofthefirstbittimeofthetransferandgoesbackhighone-halfSPSCKcycleafter the end of the eighth bit time of the transfer. TheSSIN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL=0) SPSCK (CPOL=1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 BIT 6 ... BIT 2 BIT 1 BIT 0 LSB FIRST BIT 0 BIT 1 ... BIT 5 BIT 6 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure12-12. SPI Clock Formats (CPHA = 0) When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB dependingonLSBFE)whenSSgoestoactivelow.ThefirstSPSCKedgecausesboththemasterandthe slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK edge,theSPIshiftershiftsonebitpositionwhichshiftsinthebitvaluethatwasjustsampledandshiftsthe second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CPHA = 0, the slave’sSS input must go to its inactive high level between transfers. MC9S08GT16A/GT8A Data Sheet, Rev. 1 200 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) 12.5.2 SPI Interrupts Therearethreeflagbits,twointerruptmaskbits,andoneinterruptvectorassociatedwiththeSPIsystem. TheSPIinterruptenablemask(SPIE)enablesinterruptsfromtheSPIreceiverfullflag(SPRF)andmode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmitbufferemptyflag(SPTEF).Whenoneoftheflagbitsisset,andtheassociatedinterruptmaskbit isset,ahardwareinterruptrequestissenttotheCPU.Iftheinterruptmaskbitsarecleared,softwarecan poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should checktheflagbitstodeterminewhateventcausedtheinterrupt.Theserviceroutineshouldalsoclearthe flag bit(s) before returning from the ISR (usually near the beginning of the ISR). 12.5.3 Mode Fault Detection A mode fault occurs and the mode fault flag (MODF) becomes set when a master SPI device detects an error on theSS pin (provided theSS pin is configured as the mode fault input signal). TheSS pin is configured to be the mode fault input signal when MSTR = 1, mode fault enable is set (MODFEN= 1), and slave select output enable is clear (SSOE = 0). ThemodefaultdetectionfeaturecanbeusedinasystemwheremorethanoneSPIdevicemightbecome amasteratthesametime.Theerrorisdetectedwhenamaster’sSSpinislow,indicatingthatsomeother SPIdeviceistryingtoaddressthismasterasifitwereaslave.Thiscouldindicateaharmfuloutputdriver conflict,sothemodefaultlogicisdesignedtodisableallSPIoutputdriverswhensuchanerrorisdetected. When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are disabled. MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIC1). User software should verify the error condition has been corrected before changing the SPI back to master mode. 12.6 Initialization/Application Information 12.6.1 SPI Module Initialization Example 12.6.1.1 Initialization Sequence BeforetheSPImodulecanbeusedforcommunication,aninitializationproceduremustbecarriedout,as follows: 1. Updatecontrolregister1(SPIC1)toenabletheSPIandtocontrolinterruptenables.Thisregister alsosetstheSPIasmasterorslave,determinesclockphaseandpolarity,andconfiguresthemain SPI options. 2. Updatecontrolregister2(SPIC2)toenableadditionalSPIfunctionssuchasthemastermode-fault function and bidirectional mode output. Other optional SPI functions are configured here as well. 3. Update the baud rate register (SPIBR) to set the prescaler and bit rate divisor for an SPI master. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 201

Serial Peripheral Interface (S08SPIV3) 12.6.1.2 Pseudo—Code Example In this example, the SPI module will be set up for master mode with only transmit interrupts enabled to run at a maximum baud rate of bus clock divided by 2. Clock phase and polarity will be set for an active-highSPIclockwherethefirstedgeonSPSCKoccursatthestartofthefirstcycleofadatatransfer. SPIC1 = 0x74(%01110100) Bit 7 SPIE = 0 Disables receive and mode fault interrupts Bit 6 SPE = 1 Enables the SPI system Bit 5 SPTIE = 1 Enables SPI transmit interrupts Bit 4 MSTR = 1 Sets the SPI module as a master SPI device Bit 3 CPOL = 0 Configures SPI clock as active-high Bit 2 CPHA = 1 First edge on SPSCK at start of first data transfer cycle Bit 1 SSOE = 0 DeterminesSS pin function when mode fault enabled Bit 0 LSBFE = 0 SPI serial data transfers start with most significant bit SPIC2 = 0x00(%00000000) Bit 7:5 = 000 Unimplemented Bit 4 MODFEN = 0 Disables mode fault function Bit 3 BIDIROE = 0 SPI data I/O pin acts as input Bit 2 = 0 Unimplemented Bit 1 SPISWAI = 0 SPI clocks operate in wait mode Bit 0 SPC0 = 0 SPI uses separate pins for data input and output SPIBR = 0x00(%00000000) Bit 7 = 0 Unimplemented Bit 6:4 = 000 Sets prescale divisor to 1 Bit 3 = 0 Unimplemented Bit 2:0 = 000 Sets baud rate divisor to 2 SPIS = 0x00(%00000000) Bit 7 SPRF = 0 Flag is set when receive data buffer is full Bit 6 = 0 Unimplemented Bit 5 SPTEF = 0 Flag is set when transmit data buffer is empty Bit 4 MODF = 0 Mode fault flag for master mode Bit 3:0 = 0 Unimplemented SPID = 0xxx Holds data to be transmitted by transmit buffer and data received by receive buffer. MC9S08GT16A/GT8A Data Sheet, Rev. 1 202 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) RESET INITIALIZE SPI SPIC1 = 0x74 SPIC2 = 0x00 SPIBR = 0x00 NO SPTEF = 1 ? YES READSPISWITHSPTEF SET TO CLEAR FLAG, THEN WRITE DATA TO SPID CONTINUE Figure12-13. Initialization Flowchart Example for SPI Master Device MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 203

Serial Peripheral Interface (S08SPIV3) MC9S08GT16A/GT8A Data Sheet, Rev. 1 204 Freescale Semiconductor

Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.1 Introduction TheMC9S08GT16A/GT8Aseriesofmicrocontrollersprovidesoneinter-integratedcircuit(IIC)module forcommunicationwithotherintegratedcircuits.Thetwopinsassociatedwiththismodule,SDAandSCL share port C pins 2 and 3, respectively. All functionality as described in this section is available on MC9S08GT16A/GT8A. When the IIC is enabled, the direction of pins is controlled by module configuration. If the IIC is disabled, both pins can be used as general-purpose I/O. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 205

Inter-Integrated Circuit (S08IICV1) VREFLVREFHVSSADVDDAD 4 HCS08 CORE BKGD 8IN-BTIETR KREUYPBTO (AKRBDI) 8 PORT A 4 PPPTTTAAA347///KKKBBBIIIPPP347–– NOTE 6 PTA0/KBIP0 CPU BDC 4 10-BIT 8 T B PPTTBB74//AADDPP74– ANALOG-TO-DIGITAL OR 4 HCS08 SYSTEM CONTROL CONVERTER (ATD) P PTB3/ADP3– RESET PTB0/ADP0 NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION PTC7 POWER MANAGEMENT PTC6 PTC5 RTI COP INTER-IC (IIC) SSDCAL PORT C PPPTTTCCC432//SSCDAL NOTE 5 IRQ IRQ LVD RXD2 NOTES 2, 3 SERIAL COMMUNICATIONS PTC1/RxD2 TXD2 INTERFACE (SCI2) PTC0/TxD2 CH1 USER FLASH 2-CHANNEL TIMER/PWM PTD4/TPM2CH1 CH0 (GT16A = 16,384 BYTES) (TPM2) PTD3/TPM2CLK/TPM2CH0 (GT8A = 8192 BYTES) D CH0 RT O PTD2/TPM1CH2 3-CHANNEL TIMER/PWM CH1 P PTD1/TPM1CH1 (TPM1) CH2 PTD0/TPM1CLK/TPM1CH0 USER RAM (GT16A = 2048 BYTES) SPSCK (GT8A = 1024 BYTES) PTE5/SPSCK MOSI SERIAL PERIPHERAL PTE4/MOSI MISO ON-CHIP ICE INTERFACE (SPI) SS RT E PPTTEE32//MSSISO DEBUG O RXD1 P MODULE (DBG) SERIAL COMMUNICATIONS PTE1/RxD1 TXD1 INTERFACE (SCI1) PTE0/TxD1 INTERNAL CLOCK GENERATOR (ICG) PTG3 EXTAL G PTG2/EXTAL XTAL T LOW-POWER OSCILLATOR R PTG1/XTAL BKGD O P PTG0/BKGD/MS V DD VOLTAGE V SS REGULATOR = Pins not available in 44-, 42-, or 32-pin packages V SS = Pins not available in 42- or 32-pin packages = Pins not available in 32-pin packages NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE=1). 3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD. 4. Pin contains integrated pullup device. 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1). Figure13-1. Block Diagram Highlighting the IIC Module MC9S08GT16A/GT8A Data Sheet, Rev. 1 206 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) 13.1.1 Features The IIC includes these distinctive features: • Compatible with IIC bus standard • Multi-master operation • Software programmable for one of 64 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation/detection • Repeated START signal generation • Acknowledge bit generation/detection • Bus busy detection 13.1.2 Modes of Operation The IIC functions the same in normal and monitor modes. A brief description of the IIC in the various MCU modes is given here. • Run mode — This is the basic mode of operation. To conserve power in this mode, disable the module. • Waitmode—ThemodulewillcontinuetooperatewhiletheMCUisinwaitmodeandcanprovide a wake-up interrupt. • Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The STOP instruction does not affect IIC register states. Stop1 and stop2 will reset the register contents. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 207

Inter-Integrated Circuit (S08IICV1) 13.1.3 Block Diagram Figure13-2 is a block diagram of the IIC. ADDRESS DATA BUS INTERRUPT ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG INPUT SYNC IN/OUT START DATA STOP SHIFT ARBITRATION REGISTER CONTROL CLOCK CONTROL ADDRESS COMPARE SCL SDA Figure13-2. IIC Functional Block Diagram 13.2 External Signal Description This section describes each user-accessible pin signal. 13.2.1 SCL — Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system. 13.2.2 SDA — Serial Data Line The bidirectional SDA is the serial data line of the IIC system. 13.3 Register Definition This section consists of the IIC register descriptions in address order. MC9S08GT16A/GT8A Data Sheet, Rev. 1 208 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.3.1 IIC Address Register (IICA) 7 6 5 4 3 2 1 0 R 0 ADDR W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure13-3. IIC Address Register (IICA) Table13-1. IICA Register Field Descriptions Field Description 7:1 IIC Address Register — The ADDR contains the specific slave address to be used by the IIC module. This is ADDR[7:1] the address the module will respond to when addressed as a slave. 13.3.2 IIC Frequency Divider Register (IICF) 7 6 5 4 3 2 1 0 R MULT ICR W Reset 0 0 0 0 0 0 0 0 Figure13-4. IIC Frequency Divider Register (IICF) MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 209

Inter-Integrated Circuit (S08IICV1) Table13-2. IICA Register Field Descriptions Field Description 7:6 IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL MULT divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved 5:0 IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection. These bits are used to ICR define the SCL divider and the SDA hold value. The SCL divider multiplied by the value provided by the MULT register (multiplier factor mul) is used to generate IIC baud rate. IIC baud rate = bus speed (Hz)/(mul * SCL divider) SDA hold time is the delay from the falling edge of the SCL (IIC clock) to the changing of SDA (IIC data). The ICR is used to determine the SDA hold value. SDA hold time = bus period (s) * SDA hold value Table13-3providestheSCLdividerandSDAholdvaluesforcorrespondingvaluesoftheICR.Thesevaluescan be used to set IIC baud rate and SDA hold time. For example: Bus speed = 8MHz MULT is set to 01 (mul = 2) Desired IIC baud rate = 100kbps IIC baud rate = bus speed (Hz)/(mul * SCL divider) 100000 = 8000000/(2*SCL divider) SCL divider = 40 Table13-3 shows that ICR must be set to 0B to provide an SCL divider of 40 and that this will result in an SDA hold value of 9. SDA hold time = bus period (s) * SDA hold value * mul SDA hold time = 1/8000000 * 9 * mul = 1.125µs * mul IfthegeneratedSDAholdvalueisnotacceptable,theMULTbitscanbeusedtochangetheICR.Thiswillresult in a different SDA hold value. MC9S08GT16A/GT8A Data Sheet, Rev. 1 210 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) Table13-3. IIC Divider and Hold Values ICR SDA Hold ICR SDA Hold SCL Divider SCL Divider (hex) Value (hex) Value 00 20 7 20 160 17 01 22 7 21 192 17 02 24 8 22 224 33 03 26 8 23 256 33 04 28 9 24 288 49 05 30 9 25 320 49 06 34 10 26 384 65 07 40 10 27 480 65 08 28 7 28 320 33 09 32 7 29 384 33 0A 36 9 2A 448 65 0B 40 9 2B 512 65 0C 44 11 2C 576 97 0D 48 11 2D 640 97 0E 56 13 2E 768 129 0F 68 13 2F 960 129 10 48 9 30 640 65 11 56 9 31 768 65 12 64 13 32 896 129 13 72 13 33 1024 129 14 80 17 34 1152 193 15 88 17 35 1280 193 16 104 21 36 1536 257 17 128 21 37 1920 257 18 80 9 38 1280 129 19 96 9 39 1536 129 1A 112 17 3A 1792 257 1B 128 17 3B 2048 257 1C 144 25 3C 2304 385 1D 160 25 3D 2560 385 1E 192 33 3E 3072 513 1F 240 33 3F 3840 513 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 211

Inter-Integrated Circuit (S08IICV1) 13.3.3 IIC Control Register (IICC) 7 6 5 4 3 2 1 0 R 0 0 0 IICEN IICIE MST TX TXAK W RSTA Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure13-5. IIC Control Register (IICC) Table13-4. IICC Register Field Descriptions Field Description 7 IIC Enable — The IICEN bit determines whether the IIC module is enabled. IICEN 0 IIC is not enabled. 1 IIC is enabled. 6 IIC Interrupt Enable — The IICIE bit determines whether an IIC interrupt is requested. IICIE 0 IIC interrupt request not enabled. 1 IIC interrupt request enabled. 5 MasterModeSelect—TheMSTbitischangedfroma0toa1whenaSTARTsignalisgeneratedonthebus MST andmastermodeisselected.Whenthisbitchangesfroma1toa0aSTOPsignalisgeneratedandthemode of operation changes from master to slave. 0 Slave Mode. 1 Master Mode. 4 TransmitModeSelect—TheTXbitselectsthedirectionofmasterandslavetransfers.Inmastermodethisbit TX shouldbesetaccordingtothetypeoftransferrequired.Therefore,foraddresscycles,thisbitwillalwaysbehigh. When addressed as a slave this bit should be set by software according to the SRW bit in the status register. 0 Receive. 1 Transmit. 3 Transmit Acknowledge Enable — This bit specifies the value driven onto the SDA during data acknowledge TXAK cycles for both master and slave receivers. 0 An acknowledge signal will be sent out to the bus after receiving one data byte. 1 No acknowledge signal response is sent. 2 Repeat START — Writing a one to this bit will generate a repeated START condition provided it is the current RSTA master.Thisbitwillalwaysbereadasalow.Attemptingarepeatatthewrongtimewillresultinlossofarbitration. MC9S08GT16A/GT8A Data Sheet, Rev. 1 212 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) 13.3.4 IIC Status Register (IICS) 7 6 5 4 3 2 1 0 R TCF BUSY 0 SRW RXAK IAAS ARBL IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure13-6. IIC Status Register (IICS) Table13-5. IICS Register Field Descriptions Field Description 7 Transfer Complete Flag — This bit is set on the completion of a byte transfer. Note that this bit is only valid TCF during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the IICD register in receive mode or writing to the IICD in transmit mode. 0 Transfer in progress. 1 Transfer complete. 6 AddressedasaSlave—TheIAASbitissetwhenthecallingaddressmatchestheprogrammedslaveaddress. IAAS Writing the IICC register clears this bit. 0 Not addressed. 1 Addressed as a slave. 5 BusBusy—TheBUSYbitindicatesthestatusofthebusregardlessofslaveormastermode.TheBUSYbitis BUSY set when a START signal is detected and cleared when a STOP signal is detected. 0 Bus is idle. 1 Bus is busy. 4 Arbitration Lost — This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be ARBL cleared by software, by writing a one to it. 0 Standard bus operation. 1 Loss of arbitration. 2 Slave Read/Write — When addressed as a slave the SRW bit indicates the value of the R/W command bit of SRW the calling address sent to the master. 0 Slave receive, master writing to slave. 1 Slave transmit, master reading from slave. 1 IIC Interrupt Flag — The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by IICIF writing a one to it in the interrupt routine. One of the following events can set the IICIF bit: • One byte transfer completes • Match of slave address to calling address • Arbitration lost 0 No interrupt pending. 1 Interrupt pending. 0 ReceiveAcknowledge—WhentheRXAKbitislow,itindicatesanacknowledgesignalhasbeenreceivedafter RXAK thecompletionofonebyteofdatatransmissiononthebus.IftheRXAKbitishighitmeansthatnoacknowledge signal is detected. 0 Acknowledge received. 1 No acknowledge received. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 213

Inter-Integrated Circuit (S08IICV1) 13.3.5 IIC Data I/O Register (IICD) 7 6 5 4 3 2 1 0 R DATA W Reset 0 0 0 0 0 0 0 0 Figure13-7. IIC Data I/O Register (IICD) Table13-6. IICD Register Field Descriptions Field Description 7:0 Data—Inmastertransmitmode,whendataiswrittentotheIICD,adatatransferisinitiated.Themostsignificant DATA bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data. NOTE When transmitting out of master receive mode, the IIC mode should be switched before reading the IICD register to prevent an inadvertent initiation of a master receive data transfer. In slave mode, the same functions are available after an address match has occurred. Note that the TX bit in IICC must correctly reflect the desired direction of transfer in master and slave modesforthetransmissiontobegin.Forinstance,iftheIICisconfiguredformastertransmitbutamaster receive is desired, then reading the IICD will not initiate the receive. ReadingtheIICDwillreturnthelastbytereceivedwhiletheIICisconfiguredineithermasterreceiveor slave receive modes. The IICD does not reflect every byte that is transmitted on the IIC bus, nor can software verify that a byte has been written to the IICD correctly by reading it back. Inmastertransmitmode,thefirstbyteofdatawrittentoIICDfollowingassertionofMSTisusedforthe addresstransferandshouldcompriseofthecallingaddress(inbit7–bit1)concatenatedwiththerequired R/W bit (in position bit 0). MC9S08GT16A/GT8A Data Sheet, Rev. 1 214 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) 13.4 Functional Description This section provides a complete functional description of the IIC module. 13.4.1 IIC Protocol TheIICbussystemusesaserialdataline(SDA)andaserialclockline(SCL)fordatatransfer.Alldevices connectedtoitmusthaveopendrainoropencollectoroutputs.AlogicANDfunctionisexercisedonboth lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: • START signal • Slave address transmission • Data transfer • STOP signal The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system communication is described briefly in the following sections and illustrated inFigure13-8. MSB LSB MSB LSB SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 START CALLING ADDRESS READ/ ACK DATA BYTE NO STOP SIGNAL WRITE BIT ACK SIGNAL BIT MSB LSB MSB LSB SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W START CALLING ADDRESS READ/ ACK REPEATED NEW CALLING ADDRESS READ/ NO STOP SIGNAL WRITE BIT START WRITE ACK SIGNAL SIGNAL BIT Figure13-8. IIC Bus Transmission Signals MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 215

Inter-Integrated Circuit (S08IICV1) 13.4.1.1 START Signal When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown inFigure13-8, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginningofanewdatatransfer(eachdatatransfermaycontainseveralbytesofdata)andbringsallslaves out of their idle states. 13.4.1.2 Slave Address Transmission The first byte of data transferred immediately after the START signal is the slave address transmitted by themaster.Thisisaseven-bitcallingaddressfollowedbyaR/Wbit.TheR/Wbittellstheslavethedesired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Only the slave with a calling address that matches the one transmitted by the master will respond by sendingbackanacknowledgebit.ThisisdonebypullingtheSDAlowatthe9thclock(seeFigure13-8). Notwoslavesinthesystemmayhavethesameaddress.IftheIICmoduleisthemaster,itmustnottransmit an address that is equal to its own slave address. The IIC cannot be master and slave at the same time. However, if arbitration is lost during an address cycle, the IIC will revert to slave mode and operate correctly even if it is being addressed by another master. 13.4.1.3 Data Transfer Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. Alltransfersthatcomeafteranaddresscyclearereferredtoasdatatransfers,eveniftheycarrysub-address information for the slave device Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown inFigure13-8. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receivingdevice.AnacknowledgeissignalledbypullingtheSDAlowattheninthclock.Insummary,one complete data transfer needs nine clock pulses. If the slave receiver does not acknowledge the master in the 9th bit time, the SDA line must be left high by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer. Ifthemasterreceiverdoesnotacknowledgetheslavetransmitterafteradatabytetransmission,theslave interprets this as an end of data transfer and releases the SDA line. In either case, the data transfer is aborted and the master does one of two things: • Relinquishes the bus by generating a STOP signal. • Commences a new calling by generating a repeated START signal. MC9S08GT16A/GT8A Data Sheet, Rev. 1 216 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) 13.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure13-8). ThemastercangenerateaSTOPeveniftheslavehasgeneratedanacknowledgeatwhichpointtheslave must release the bus. 13.4.1.5 Repeated START Signal AsshowninFigure13-8,arepeatedSTARTsignalisaSTARTsignalgeneratedwithoutfirstgeneratinga STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 13.4.1.6 Arbitration Procedure The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or moremasterstrytocontrolthebusatthesametime,aclocksynchronizationproceduredeterminesthebus clock,forwhichthelowperiodisequaltothelongestclocklowperiodandthehighisequaltotheshortest oneamongthemasters.Therelativepriorityofthecontendingmastersisdeterminedbyadataarbitration procedure,abusmasterlosesarbitrationifittransmitslogic1whileanothermastertransmitslogic0.The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 13.4.1.7 Clock Synchronization Becausewire-ANDlogicisperformedontheSCLline,ahigh-to-lowtransitionontheSCLlineaffectsall thedevicesconnectedonthebus.Thedevicesstartcountingtheirlowperiodandafteradevice’sclockhas gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to highinthisdeviceclockmaynotchangethestateoftheSCLlineifanotherdeviceclockisstillwithinits low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (seeFigure13-9). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulledhigh.ThereisthennodifferencebetweenthedeviceclocksandthestateoftheSCLlineandallthe devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 217

Inter-Integrated Circuit (S08IICV1) DELAY START COUNTING HIGH PERIOD SCL1 SCL2 SCL INTERNAL COUNTER RESET Figure13-9. IIC Clock Synchronization 13.4.1.8 Handshaking Theclocksynchronizationmechanismcanbeusedasahandshakeindatatransfer.Slavedevicesmayhold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 13.4.1.9 Clock Stretching Theclocksynchronizationmechanismcanbeusedbyslavestoslowdownthebitrateofatransfer.After the master has driven SCL low the slave can drive SCL low for the required period and then release it. If theslaveSCLlowperiodisgreaterthanthemasterSCLlowperiodthentheresultingSCLbussignallow period is stretched. 13.5 Resets The IIC is disabled after reset. The IIC cannot cause an MCU reset. 13.6 Interrupts The IIC generates a single interrupt. AninterruptfromtheIIC isgeneratedwhenanyoftheeventsinTable13-7occurprovidedtheIICIEbit isset.TheinterruptisdrivenbybitIICIF(oftheIICstatusregister)andmaskedwithbitIICIE(oftheIIC controlregister).TheIICIFbitmustbeclearedbysoftwarebywritingaonetoitintheinterruptroutine. The user can determine the interrupt type by reading the status register. Table13-7. Interrupt Summary Interrupt Source Status Flag Local Enable Complete 1-byte transfer TCF IICIF IICIE Match of received calling address IAAS IICIF IICIE Arbitration Lost ARBL IICIF IICIE MC9S08GT16A/GT8A Data Sheet, Rev. 1 218 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) 13.6.1 Byte Transfer Interrupt TheTCF(transfercompleteflag)bitissetatthefallingedgeofthe9thclocktoindicatethecompletionof byte transfer. 13.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register), the IAAS bit in thestatusregisterisset.TheCPUisinterruptedprovidedtheIICIEisset.TheCPUmustchecktheSRW bit and set its Tx mode accordingly. 13.6.3 Arbitration Lost Interrupt TheIICisatruemulti-masterbusthatallowsmorethanonemastertobeconnectedonit.Iftwoormore masterstrytocontrolthebusatthesametime,therelativepriorityofthecontendingmastersisdetermined by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration process and the ARBL bit in the status register is set. Arbitration is lost in the following circumstances: • SDA sampled as a low when the master drives a high during an address or data transmit cycle. • SDAsampledasalowwhenthemasterdrivesahighduringtheacknowledgebitofadatareceive cycle. • A START cycle is attempted when the bus is busy. • A repeated START cycle is requested in slave mode. • A STOP condition is detected when the master did not request it. This bit must be cleared by software by writing a one to it. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 219

Inter-Integrated Circuit (S08IICV1) MC9S08GT16A/GT8A Data Sheet, Rev. 1 220 Freescale Semiconductor

Chapter 14 Analog-to-Digital Converter (S08ATDV3) The MC9S08GT16A/GT8A provides one 8-channel analog-to-digital (ATD) module. The eight ATD channels share port B. Each channel individually can be configured for general-purpose I/O or for ATD functionality. All features of the ATD module as described in this section are available on the MC9S08GT16A/GT8A. Electrical parametric information for the ATD may be found inAppendix A, “Electrical Characteristics.” MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 221

Analog-to-Digital Converter (S08ATDV3) VREFLVREFHVSSADVDDAD 4 HCS08 CORE BKGD 8IN-BTIETR KREUYPBTO (AKRBDI) 8 PORT A 4 PPPTTTAAA347///KKKBBBIIIPPP347–– NOTE 6 PTA0/KBIP0 CPU BDC 4 10-BIT 8 T B PPTTBB74//AADDPP74– ANALOG-TO-DIGITAL OR 4 HCS08 SYSTEM CONTROL CONVERTER (ATD) P PTB3/ADP3– RESET PTB0/ADP0 NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION PTC7 POWER MANAGEMENT PTC6 PTC5 RTI COP INTER-IC (IIC) SSDCAL PORT C PPPTTTCCC432//SSCDAL NOTE 5 IRQ IRQ LVD RXD2 NOTES 2, 3 SERIAL COMMUNICATIONS PTC1/RxD2 TXD2 INTERFACE (SCI2) PTC0/TxD2 CH1 USER FLASH 2-CHANNEL TIMER/PWM PTD4/TPM2CH1 CH0 (GT16A = 16,384 BYTES) (TPM2) PTD3/TPM2CLK/TPM2CH0 (GT8A = 8192 BYTES) D CH0 RT O PTD2/TPM1CH2 3-CHANNEL TIMER/PWM CH1 P PTD1/TPM1CH1 (TPM1) CH2 PTD0/TPM1CLK/TPM1CH0 USER RAM (GT16A = 2048 BYTES) SPSCK (GT8A = 1024 BYTES) PTE5/SPSCK MOSI SERIAL PERIPHERAL PTE4/MOSI MISO ON-CHIP ICE INTERFACE (SPI) SS RT E PPTTEE32//SMSISO DEBUG O RXD1 P MODULE (DBG) SERIAL COMMUNICATIONS PTE1/RxD1 TXD1 INTERFACE (SCI1) PTE0/TxD1 INTERNAL CLOCK GENERATOR (ICG) PTG3 EXTAL G PTG2/EXTAL XTAL T LOW-POWER OSCILLATOR R PTG1/XTAL BKGD O P PTG0/BKGD/MS V DD VOLTAGE V SS REGULATOR = Pins not available in 44-, 42-, or 32-pin packages V SS = Pins not available in 42- or 32-pin packages = Pins not available in 32-pin packages NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE=1). 3. IRQ does not have a clamp diode to V . IRQ should not be driven above V . DD DD 4. Pin contains integrated pullup device. 5. High current drive. 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1). Figure14-1. MC9S08GT16A Block Diagram Highlighting ATD Block and Pins MC9S08GT16A/GT8A Data Sheet, Rev. 1 222 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) 14.1 Introduction The ATD module is an analog-to-digital converter with a successive approximation register (SAR) architecture with sample and hold. 14.1.1 Features • 8-/10-bit resolution • 14.0µsec, 10-bit single conversion time at a conversion frequency of 2MHz • Left-/right-justified result data • Left-justified signed data mode • Conversion complete flag or conversion complete interrupt generation • Analog input multiplexer for up to eight analog input channels • Single or continuous conversion mode 14.1.2 Modes of Operation The ATD has two modes for low power • Stop mode • Power-down mode 14.1.2.1 Stop Mode WhentheMCUgoesintostopmode,theMCUstopstheclocksandtheATDanalogcircuitryisturnedoff, placing the module into a low-power state. Once in stop mode, the ATD module aborts any single or continuous conversion in progress. Upon exiting stop mode, no conversions occur and the registers have theirpreviousvalues.AslongastheATDPUbitissetpriortoenteringstopmode,themoduleisreactivated coming out of stop. 14.1.2.2 Power Down Mode Clearing the ATDPU bit in register ATDC also places the ATD module in a low-power state. The ATD conversion clock is disabled and the analog circuitry is turned off, placing the module in power-down mode. (This mode does not remove power to the ATD module.) Once in power-down mode, the ATD moduleabortsanyconversioninprogress.UponsettingtheATDPUbit,themoduleisreactivated.During power-down mode, the ATD registers are still accessible. NotethattheresetstateoftheATDPUbitiszero.Therefore,themoduleisresetintothepower-downstate. 14.1.3 Block Diagram Figure14-2 illustrates the functional structure of the ATD module. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 223

Analog-to-Digital Converter (S08ATDV3) CONTROL SAR_REG INTERRUPT DATA <9:0> ADDRESS CONTROL AND JUSTIFICATION RESULT REGISTERS STATUS R/W DATA REGISTERS V CTL DD PRESCALER STATUS V SS CTL BUSCLK CLOCK CONVERSION MODE STATE PRESCALER CONTROL BLOCK MACHINE CONVERSION CLOCK DIGITAL ANALOG POWERDOWN CTL V REFH V REFL V DDAD R E VSSAD ST SUCCESSIVE APPROXIMATION REGISTER GI E ANALOG-TO-DIGITAL CONVERTER (ATD) BLOCK R ADP0 N O SI ADP1 R E V ADP2 N O C ADP3 INPUT ADP4 MUX ADP5 ADP6 ADP7 = INTERNAL PINS = CHIP PADS Figure14-2. ATD Block Diagram 14.2 External Signal Description The ATD supports eight input channels and requires four supply/reference/ground pins. These pins are listed inTable14-1. MC9S08GT16A/GT8A Data Sheet, Rev. 1 224 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) Table14-1. Signal Properties Name Function AD7–AD0 Channel input pins VREFH High reference voltage for ATD converter VREFL Low reference voltage for ATD converter VDDAD ATD power supply voltage VSSAD ATD ground supply voltage 14.2.1 ADP7–ADP0 — Channel Input Pins ThechannelpinsareusedastheanaloginputpinsoftheATD.Eachpinisconnectedtoananalogswitch which serves as the signal gate into the sample submodule. 14.2.2 V , V — ATD Reference Pins REFH REFL Thesepinsserveasthesourceforthehighandlowreferencepotentialsfortheconverter.Separationfrom thepowersupplypinsaccommodatesthefilteringnecessarytoachievetheaccuracyofwhichthesystem is capable. 14.2.3 V , V — ATD Supply Pins DDAD SSAD These two pins are used to supply power and ground to the analog section of the ATD. Dedicated power isrequiredtoisolatethesensitiveanalogcircuitryfromthenormallevelsofnoisepresentondigitalpower supplies. NOTE V andV mustbeatthesamepotential.Likewise,V andV DDAD1 DD SSAD1 SS must be at the same potential. 14.3 Register Definition The ATD has seven registers that control ATD functions. Refertothedirect-pageregistersummaryinthememorychapterofthisdatasheetfortheabsoluteaddress assignmentsforallATDregisters.Thissectionreferstoregistersandcontrolbitsonlybytheirnames.A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 14.3.1 ATD Control (ATDC) Writes to the ATD control register will abort the current conversion, but will not start a new conversion. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 225

Analog-to-Digital Converter (S08ATDV3) 7 6 5 4 3 2 1 0 R ATDPU DJM RES8 SGN PRS W Reset 0 0 0 0 0 0 0 0 Figure14-3. ATD Control Register (ATDC) Table14-2. ATDC Field Descriptions Field Description 7 ATDPowerUp—Thisbitprovidesprogramon/offcontrolovertheATD,reducingpowerconsumptionwhenthe ATDPU ATD is not being used. When cleared, the ATDPU bit aborts any conversion in progress. 0 Disable the ATD and enter a low-power state. 1 ATD functionality. 6 DataJustificationMode—Thisbitdetermineshowthe10-bitconversionresultdatamapsontotheATDresult DJM register bits. When RES8 is set, bit DJM has no effect and the 8-bit result is always located in ATDRH. Forleft-justifiedmode,resultdatabits9–2mapontobits7–0ofATDRH,resultdatabits1and0mapontoATDRL bits 7 and 6, where bit 7 of ATDRH is the most significant bit (MSB). Forright-justifiedmode,resultdatabits9and8mapontobits1and0ofATDRH,resultdatabits7–0maponto ATDRL bits 7–0, where bit 1 of ATDRH is the most significant bit (MSB). The effect of the DJM bit on the result is shown inTable14-3. 0 Result register data is left justified. SeeFigure14-4. 1 Result register data is right justified. SeeFigure14-5. 5 ATD Resolution Select— This bit determines the resolution of the ATD converter, 8-bits or 10-bits. The ATD RES8 converter has the accuracy of a 10-bit converter. However, if 8-bit compatibility is required, selecting 8-bit resolution will map result data bits 9-2 onto ATDRH bits 7-0. The effect of the RES8 bit on the result is shown inTable14-3. 0 10-bit resolution selected. 1 8-bit resolution selected. 4 SignedResultSelect—Thisbitdetermineswhethertheresultwillbesignedorunsigneddata.Signeddatais SGN representedas2’scomplementdataandisachievedbycomplementingtheMSBoftheresult.Signeddatamode canbeusedonlywhentheresultisleftjustified(DJM=0)andisnotavailableforright-justifiedmode(DJM=1). When a signed result is selected, the range for conversions becomes –512 ($200) to 511 ($1FF) for 10-bit resolution and –128 ($80) to 127 ($7F) for 8-bit resolution. The effect of the SGN bit on the result is shown inTable14-3. 0 Left justified result data is unsigned. 1 Left justified result data is signed. 3:0 Prescaler Rate Select — This field of bits determines the prescaled factor for the ATD conversion clock. PRS Table14-4 illustrates the divide-by operation and the appropriate range of bus clock frequencies. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 RESULT 0 ATDRH ATDRL Figure14-4. Left-Justified Mode 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 RESULT 0 ATDRH ATDRL Figure14-5. Right-Justified Mode MC9S08GT16A/GT8A Data Sheet, Rev. 1 226 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) Table14-3. Available Result Data Formats Analog Input V =V , V =V REFH DDA REFL SSA RES8 DJM SGN Data Formats of Result ATDRH:ATDRL V V DDA SSA 1 0 0 8-bit : left justified : unsigned $FF:$00 $00:$00 1 0 1 8-bit : left justified : signed $7F:$00 $80:$00 1 1 X1 8-bit : left justified2 : unsigned $FF:$00 $00:$00 0 0 0 10-bit : left justified : unsigned $FF:$C0 $00:$00 0 0 1 10-bit : left justified : signed $7F:$C0 $80:$00 0 1 X1 10-bit : right justified : unsigned $03:$FF $00:$00 1 The SGN bit is only effective when DJM=0. When DJM = 1, SGN is ignored. 2 8-bit results are always in ATDRH. Table14-4. Clock Prescaler Values Max Bus Clock Max Bus Clock Min Bus Clock3 PRS Factor = (PRS +1)× 2 MHz MHz MHz (2MHz max ATD Clock)1 (1MHz max ATD Clock)2 (500kHzminATDClock) 0000 2 4 2 1 0001 4 8 4 2 0010 6 12 6 3 0011 8 16 8 4 0100 10 20 10 5 0101 12 20 12 6 0110 14 20 14 7 0111 16 20 16 8 1000 18 20 18 9 1001 20 20 20 10 1010 22 20 20 11 1011 24 20 20 12 1100 26 20 20 13 1101 28 20 20 14 1110 30 20 20 15 1111 32 20 20 16 1 MaximumATDconversionclockfrequencyis2MHz.ThemaxbusclockfrequencyiscomputedfromthemaxATDconversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus clock = 2 (max ATD conversion clock frequency)× 2 (Factor) = 4MHz. 2 Use these settings if the maximum desired ATD conversion clock frequency is 1MHz. The max bus clock frequency is computedfromthemaxATDconversionclockfrequencytimestheindicatedprescalersetting;i.e.,foraPRSof0,maxbus clock = 1 (max ATD conversion clock frequency)× 2 (Factor) = 2 MHz. 3 MinimumATDconversionclockfrequencyis500kHz.TheminbusclockfrequencyiscomputedfromtheminATDconversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 1, min bus clock = 0.5 (min ATD conversion clock frequency)× 2 (Factor) = 1 MHz. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 227

Analog-to-Digital Converter (S08ATDV3) 14.3.2 ATD Status and Control (ATDSC) Writes to the ATD status and control register clears the CCF flag, cancels any pending interrupts, and initiates a new conversion. 7 6 5 4 3 2 1 0 R CCF ATDIE ATDCO ATDCH W Reset 0 0 0 0 0 0 0 1 = Unimplemented or Reserved Figure14-6. ATD Status and Control Register (ATDSC) Table14-5. ATDSC Register Field Descriptions Field Description 7 ConversionCompleteFlag—TheCCFisaread-onlybitwhichisseteachtimeaconversioniscomplete.The CCF CCF bit is cleared whenever the ATDSC register is written. It is also cleared whenever the result registers, ATDRH or ATDRL, are read. 0 Current conversion is not complete. 1 Current conversion is complete. 6 ATDInterruptEnabled—Whenthisbitisset,aninterruptisgenerateduponcompletionofanATDconversion. ATDIE At this time, the result registers contain the result data generated by the conversion. The interrupt will remain pending as long as the conversion complete flag CCF is set. If the ATDIE bit is cleared, then the CCF bit must be polled to determine when the conversion is complete. Note that system reset clears pending interrupts. 0 ATD interrupt disabled. 1 ATD interrupt enabled. 5 ATDContinuousConversion—Whenthisbitisset,theATDwillconvertsamplescontinuouslyandupdatethe ATDCO resultregistersattheendofeachconversion.Whenthisbitiscleared,onlyoneconversioniscompletedbetween writes to the ATDSC register. 0 Single conversion mode. 1 Continuous conversion mode. 4:0 AnalogInputChannelSelect—Thisfieldofbitsselectstheanaloginputchannelwhosesignalissampledand ATDCH converted to digital codes.Table14-6lists the coding used to select the various analog input channels. Table14-6. Analog Input Channel Select Coding ATDCH Analog Input Channel 00 AD0 01 AD1 02 AD2 03 AD3 04 AD4 05 AD5 06 AD6 07 AD7 08–1D Reserved (default to VREFL) 1E VREFH 1F VREFL MC9S08GT16A/GT8A Data Sheet, Rev. 1 228 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) 14.3.3 ATD Result Data (ATDRH, ATDRL) Forleft-justifiedmode,resultdatabits9–2mapontobits7–0ofATDRH,resultdatabits1and0maponto ATDRL bits 7 and 6, where bit 7 of ATDRH is the most significant bit (MSB). 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 RESULT 0 ATD1RH ATD1RL Figure14-7. Left-Justified Mode Forright-justifiedmode,resultdatabits9and8mapontobits1and0ofATDRH,resultdatabits7–0map onto ATDRL bits 7–0, where bit 1 of ATDRH is the most significant bit (MSB). 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 RESULT 0 ATD1RH ATD1RL Figure14-8. Right-Justified Mode TheATD10-bitconversionresultsarestoredintwo8-bitresultregisters,ATDRHandATDRL.Theresult dataisformattedeitherleftorrightjustifiedwheretheformatisselectedusingtheDJMcontrolbitinthe ATDCregister.The10-bitresultdataismappedeitherbetweenATDRHbits7–0andATDRLbits7–6(left justified), or ATDRH bits 1–0 and ATDRL bits 7–0 (right justified). For 8-bit conversions, the 8-bit result is always located in ATDRH bits 7–0, and the ATDRL bits read 0. For 10-bit conversions, the six unused bits always read 0. The ATDRH and ATDRL registers are read-only. 14.3.4 ATD Pin Enable (ATDPE) 7 6 5 4 3 2 1 0 R ATDPE7 ATDPE6 ATDPE5 ATDPE4 ATDPE3 ATDPE2 ATDPE1 ATDPE0 W Reset 0 0 0 0 0 0 0 0 Figure14-9. ATD Pin Enable Register (ATDPE) Table14-7. ATDSC Register Field Descriptions Field Description 7:0 ATD Pin 7–0 Enables— The ATD pin enable register allows the pins dedicated to the ATD module to be ATDPE[7:0] configured for ATD usage. A write to this register will abort the current conversion but will not initiate a new conversion. If the ATDPEx bit is 0 (disabled for ATD usage) but the corresponding analog input channel is selected via the ATDCH bits, the ATD will not convert the analog input but will instead convert V placing REFL zeroes in the ATD result registers. 0 Pin disabled for ATD usage. 1 Pin enabled for ATD usage. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 229

Analog-to-Digital Converter (S08ATDV3) 14.4 Functional Description TheATDusesasuccessiveapproximationregister(SAR)architecture.TheATDcontainsallthenecessary elements to perform a single analog-to-digital conversion. AwritetotheATDSCregisterinitiatesanewconversion.AwritetotheATDCregisterwillinterruptthe currentconversionbutitwillnotinitiateanewconversion.AwritetotheATDPEregisterwillalsoabort the current conversion but will not initiate a new conversion. If a conversion is already running when a write to the ATDSC register is made, it will be aborted and a new one will be started. 14.4.1 Mode Control TheATDhasamodecontrolunittocommunicatewiththesampleandhold(S/H)machineandtheSAR machine when necessary to collect samples and perform conversions. The mode control unit signals the S/H machine to begin collecting a sample and for the SAR machine to begin receiving a sample. At the end of the sample period, the S/H machine signals the SAR machine to begin the analog-to-digital conversion process. The conversion process is terminated when the SAR machine signals the end of conversiontothemodecontrolunit.ForV andV ,theSARmachineusesthereferencepotentials REFL REFH to set the sampled signal level within itself without relying on the S/H machine to deliver them. Themodecontrolunitorganizestheconversion,specifiestheinputsamplechannel,andmovesthedigital outputdatafromtheSARregistertotheresultregister.Theresultregisterconsistsofadual-portregister. The SAR register writes data into the register through one port while the module data bus reads data out of the register through the other port. 14.4.2 Sample and Hold TheS/Hmachineacceptsanalogsignalsandstoresthemascapacitorchargeonastoragenodelocatedin the SAR machine. Only one sample can be held at a time so the S/H machine and the SAR machine can notrunconcurrentlyeventhoughtheyareindependentmachines.Figure14-10showstheplacementofthe various resistors and capacitors. ATD SAR R INPUT PIN R ENGINE AS AIN1 V AIN + CHANNEL SELECT 0 – CAS INPUT PIN R AIN2 CHANNEL SELECT 1 INPUT PIN R AIN3 . CHANNEL . SELECT 2 . INPUT PIN R AINn CHANNEL SELECT n C AIN Figure14-10. Resistor and Capacitor Placement MC9S08GT16A/GT8A Data Sheet, Rev. 1 230 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) When the S/H machine is not sampling, it disables its own internal clocks.The input analog signals are unipolar. The signals must fall within the potential range of V to V . The S/H machine is not SSAD DDAD required to perform special conversions (i.e., convert V and V ). REFL REFH Proper sampling is dependent on the following factors: • Analog source impedance (the real portion, R – see the electricals characteristics at the end of AS this data sheet) — This is the resistive (or real, in the case of high frequencies) portion of the network driving the analog input voltage V . AIN • Analogsourcecapacitance(C )—Thisisthefilteringcapacitanceontheanaloginput,which(if AS large enough) may help the analog source network charge the ATD input in the case of high R . AS • ATDinputresistance(R –maximumvalue7kΩ)—ThisistheinternalresistanceoftheATD AIN circuit in the path between the external ATD input and the ATD sample and hold circuit. This resistance varies with temperature, voltage, and process variation but a worst case number is necessary to compute worst case sample error. • ATD input capacitance (C – maximum value 25pF) — This is the internal capacitance of the AIN ATD sample and hold circuit. This capacitance varies with temperature, voltage, and process variation but a worst case number is necessary to compute worst case sample error. • ATDconversionclockfrequency(f –maximumvalue2MHz)—Thisisthefrequencyof ATDCLK the clock input to the ATD and is dependent on the bus clock frequency and the ATD prescaler. This frequency determines the width of the sample window, which is 14 ATDCLK cycles. • Inputsamplefrequency(f –seetheelectricalcharacteristicsattheendofthisdatasheet)— SAMP This is the frequency that a given input is sampled. • Delta-inputsamplevoltage(∆V )—Thisisthedifferencebetweenthecurrentinputvoltage SAMP (intended for conversion) and the previously sampled voltage (which may be from a different channel).Innon-continuousconvertmode,thisisassumedtobethegreaterof(V –V )and REFH AIN (V – V ). In continuous convert mode, 5 LSB should be added to the known difference to AIN REFL account for leakage and other losses. • Delta-analoginputvoltage(∆V )—Thisisthedifferencebetweenthecurrentinputvoltageand AIN the input voltage during the last conversion on a given channel. This is based on the slew rate of the input. In cases where there is no external filtering capacitance, the sampling error is determined by the number of time constants of charging and the change in input voltage relative to the resolution of the ATD: # of time constants (τ) = (14 / f ) / ((R + R ) * C ) Eqn.14-1 ATDCLK AS AIN AIN sampling error in LSB (E ) = 2N * (∆V / (V - V )) * e−τ S SAMP REFH REFL The maximum sampling error (assuming maximum change on the input voltage) will be: E = (3.6/3.6) * e–(14/((7 k + 10 k) * 50 p * 2 M)) * 1024 = 0.271 LSB Eqn.14-2 S Inthecasewhereanexternalfilteringcapacitanceisapplied,thesamplingerrorcanbereducedbasedon thesizeofthesourcecapacitor(C )relativetotheanaloginputcapacitance(C ).Ignoringtheanalog AS AIN source impedance (R ), C will charge C to a value of: AS AS AIN MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 231

Analog-to-Digital Converter (S08ATDV3) E = 2N * (∆V / (V – V )) * (C / (C + C )) Eqn.14-3 S SAMP REFH REFL AIN AIN AS In the case of a 0.1 µF C , a worst case sampling error of 0.5 LSB is achieved regardless of R . AS AS However,inthecaseofrepeatedconversionsatarateoff ,R mustre-chargeC .Thisrechargeis SAMP AS AS continuous and controlled only by R (not R ), and reduces the overall sampling error to: AS AIN ES = 2N * {(∆VAIN / (VREFH – VREFL)) * e−(1 / (fSAMP * RAS * CAS ) + (∆VSAMP / (VREFH - VREFL)) * Min[(CAIN / (CAIN + CAS)), e−(1 / (fATDCLK * (RAS+ RAIN) * CAIN )]} Eqn.14-4 This is a worst case sampling error which does not account for R recharging the combination of C AS AS and C during the sample window. It does illustrate that high values of R (>10kΩ) are possible if a AIN AS large C is used and sufficient time to recharge C is provided between samples. In order to achieve AS AS accuracy specified under the worst case conditions of maximum∆V and minimum C , R must SAMP AS AS belessthanthemaximumvalueof10kΩ.Themaximumvalueof10kΩforR istoensurelowsampling AS error in the worst case condition of maximum ∆V and minimum C . SAMP AS 14.4.3 Analog Input Multiplexer Theanaloginputmultiplexerselectsoneoftheeightexternalanaloginputchannelstogenerateananalog sample. The analog input multiplexer includes negative stress protection circuitry which prevents cross-talkbetweenchannelswhentheappliedinputpotentialsarewithinspecification.Onlyanaloginput signalswithinthepotentialrangeofV toV (ATDreferencepotentials)willresultinvalidATD REFL REFH conversions. 14.4.4 ATD Module Accuracy Definitions Figure14-11 illustrates an ideal ATD transfer function. The horizontal axis represents the ATD input voltageinmillivolts.Theverticalaxistheconversionresultcode.TheATDisspecifiedwiththefollowing figures of merit: • Number of bits (N) — The number of bits in the digitized output • Resolution(LSB)—TheresolutionoftheATDisthestepsizeoftheidealtransferfunction.This is also referred to as the ideal code width, or the difference between the transition voltages to a given code and to the next code. This unit, known as 1LSB, is equal to 1LSB = (V – V ) / 2N Eqn.14-5 REFH REFL • Inherent quantization error (E ) — This is the error caused by the division of the perfect ideal Q straight-linetransferfunctionintothequantizedidealtransferfunctionwith2Nsteps.Thiserroris ± 1/2LSB. • Differentialnon-linearity(DNL)—Thisisthedifferencebetweenthecurrentcodewidthandthe idealcodewidth(1LSB).Thecurrentcodewidthisthedifferenceinthetransitionvoltagestothe currentcodeandtothenextcode.AnegativeDNLmeansthetransferfunctionspendslesstimeat the current code than ideal; a positive DNL, more. The DNL cannot be less than –1.0; a DNL of greater than 1.0 reduces the effective number of bits by 1. • Integralnon-linearity(INL)—Thisisthedifferencebetweenthetransitionvoltagetothecurrent codeandthetransitiontothecorrespondingcodeontheadjustedtransfercurve.INLisameasure MC9S08GT16A/GT8A Data Sheet, Rev. 1 232 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) of how straight the line is (how far it deviates from a straight line). The adjusted ideal transition voltage is: Eqn.14-6 (Current Code - 1/2) Adjusted Ideal Trans. V = * ((V + E ) - (V + E )) REFH FS REFL ZS 2N • Zeroscaleerror(E )—Thisisthedifferencebetweenthetransitionvoltagetothefirstvalidcode ZS andtheidealtransitiontothatcode.Normally,itisdefinedasthedifferencebetweentheactualand ideal transition to code $001, but in some cases the first transition may be to a higher code. The ideal transition to any code is: Eqn.14-7 (Current Code - 1/2) Ideal Transition V = *(V – V ) 2N REFH REFL • Fullscaleerror(E )—Thisisthedifferencebetweenthetransitionvoltagetothelastvalidcode FS andtheidealtransitiontothatcode.Normally,itisdefinedasthedifferencebetweentheactualand idealtransitiontocode$3FF,butinsomecasesthelasttransitionmaybetoalowercode.Theideal transition to any code is: Eqn.14-8 (Current Code - 1/2) Ideal Transition V = *(V – V ) 2N REFH REFL • Totalunadjustederror(E )—Thisisthedifferencebetweenthetransitionvoltagetoagivencode TU and the ideal straight-line transfer function. An alternate definition (with the same result) is the difference between the actual transfer function and the ideal straight-line transfer function. This measure of error includes inherent quantization error and all forms of circuit error (INL, DNL, zero-scale, and full-scale) except input leakage error, which is not due to the ATD. • Inputleakageerror(E )—Thisistheerrorbetweenthetransitionvoltagetothecurrentcodeand IL the ideal transition to that code that is the result of input leakage across the real portion of the impedance of the network that drives the analog input. This error is a system-observable error which is not inherent to the ATD, so it is not added to total error. This error is: E (in V) = input leakage * R Eqn.14-9 IL AS TherearetwootherformsoferrorwhicharenotspecifiedwhichcanalsoaffectATDaccuracy.Theseare: • Sampling error (E ) — The error due to inadequate time to charge the ATD circuitry S • Noiseerror(E )—TheerrorduetonoiseonV ,V ,orV duetoeitherdirectcoupling N AIN REFH REFL (noisesourcecapacitivelycoupleddirectlyonthesignal)orpowersupply(V ,V ,V , DDAD SSAD DD andV )noiseinterferingwiththeATD’sabilitytoresolvetheinputaccurately.Theerrordueto SS internal sources can be reduced (and specified operation achieved) by operating the ATD conversioninwaitmodeandceasingallIOactivity.Reducingtheerrorduetoexternalsourcesis dependent on system activity and board layout. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 233

Analog-to-Digital Converter (S08ATDV3) CODE D C TOTAL UNADJUSTED ERROR BOUNDARY B A IDEAL TRANSFER FUNCTION 9 NEGATIVE DNL (CODE WIDTH <1LSB) 8 IDEAL STRAIGHT-LINE TRANSFER FUNCTION 7 QUANTIZATION 6 ERROR INL (ASSUMES E =E =0) ZS FS 5 1 LSB 4 TOTAL UNADJUSTED 3 ERROR AT THIS CODE 2 POSITIVE DNL 1 (CODE WIDTH >1LSB) 0 1 2 3 4 8 12 LSB NOTES: Graph is for example only and may not represent actual performance Figure14-11. ATD Accuracy Definitions MC9S08GT16A/GT8A Data Sheet, Rev. 1 234 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) 14.5 Resets The ATD module is reset on system reset. If the system reset signal is activated, the ATD registers are initializedbacktotheirresetstateandtheATDmoduleispowereddown.Thisoccursasafunctionofthe register file initialization; the reset definition of the ATDPU bit (power down bit) is zero or disabled. The MCU places the module back into an initialized state. If the module is performing a conversion, the current conversion is terminated, the conversion complete flag is cleared, and the SAR register bits are cleared. Any pending interrupts are also cancelled. Note that the control, test, and status registers are initialized on reset; the initialized register state is defined in the register description section of this specification. Enablingthemodule(usingtheATDPUbit)doesnotcausethemoduletoresetsincetheregisterfileisnot initialized. Finally, writing to control register ATDC doesnot cause the module to reset; the current conversion will be terminated. 14.6 Interrupts TheATDmoduleoriginatesinterruptrequestsandtheMCUhandlesorservicestheserequests.Detailson how the ATD interrupt requests are handled can be found in the resets and interrupts chapter of this data sheet. TheATDinterruptfunctionisenabledbysettingtheATDIEbitintheATDSCregister.WhentheATDIE bitisset,aninterruptisgeneratedattheendofanATDconversionandtheATDresultregisters(ATDRH and ATDRL) contain the result data generated by the conversion. If the interrupt function is disabled (ATDIE= 0), then the CCF flag must be polled to determine when a conversion is complete. TheinterruptwillremainpendingaslongastheCCFflagisset.TheCCFbitisclearedwhenevertheATD status and control (ATDSC) register is written. The CCF bit is also cleared whenever the ATD result registers (ATDRH or ATDRL) are read. Table14-8. Interrupt Summary Local Interrupt Description Enable CCF ATDIE Conversion complete MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 235

Analog-to-Digital Converter (S08ATDV3) MC9S08GT16A/GT8A Data Sheet, Rev. 1 236 Freescale Semiconductor

Chapter 15 Development Support 15.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that providesaconvenientinterfaceforprogrammingtheon-chipFLASHandothernonvolatilememories.The BDCisalsotheprimarydebuginterfacefordevelopmentandallowsnon-intrusiveaccesstomemorydata and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. In the HCS08 Family, address and data bus signals are not available on external pins (not even in test modes).DebugisdonethroughcommandsfedintothetargetMCUviathesingle-wirebackgrounddebug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals. ThealternateBDCclocksourceforMC9S08GT16A/GT8AistheICGLCLK.SeetheChapter 9,“Internal Clock Generator (S08ICGV4),” for more information about ICGCLK and how to select clock sources. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 237

Development Support 15.1.1 Features Features of the BDC module include: • Single pin for mode selection and background communications • BDC registers are not located in the memory map • SYNC command to determine target communications rate • Non-intrusive commands for memory access • Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from stop or wait modes • One hardware address breakpoint built into BDC • Oscillator runs in stop mode, if BDC enabled • COP watchdog disabled while in active background mode Features of the ICE system include: • Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W • Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information: — Change-of-flow addresses or — Event-only data • Two types of breakpoints: — Tag breakpoints for instruction opcodes — Force breakpoints for any address access • Nine trigger modes: — Basic: A-only, A OR B — Sequence: A then B — Full: A AND B data, A AND NOT B data — Event (store data): Event-only B, A then event-only B — Range: Inside range (A ≤ address ≤ B), outside range (address < A or address > B) 15.2 Background Debug Controller (BDC) AllMCUsintheHCS08Familycontainasingle-wirebackgrounddebuginterfacethatsupportsin-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debuginterfacesonearlier8-bitMCUs,thissystemdoesnotinterferewithnormalapplicationresources. It does not use any user memory or locations in the memory map and does not share any on-chip peripherals. BDC commands are divided into two groups: • ActivebackgroundmodecommandsrequirethatthetargetMCUisinactivebackgroundmode(the user program is not running). Active background mode commands allow the CPU registers to be readorwritten,andallowtheusertotraceoneuserinstructionatatime,orGOtotheuserprogram from active background mode. MC9S08GT16A/GT8A Data Sheet, Rev. 1 238 Freescale Semiconductor

Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusivecommandsallowausertoreadorwriteMCUmemorylocationsoraccessstatusand control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commandsforthecustomserialinterfacetothesingle-wirebackgrounddebugsystem.Dependingonthe developmenttoolvendor,thisinterfacepodmayuseastandardRS-232serialport,aparallelprinterport, orsomeothertypeofcommunicationssuchasauniversalserialbus(USB)tocommunicatebetweenthe hostPCandthepod.Thepodtypicallyconnectstothetargetsystemwithground,theBKGDpin,RESET, and sometimes V . An open-drain connection to reset allows the host to force a target system reset, DD which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. Sometimes V can be used to allow the pod to use DD powerfromthetargetsystemtoavoidtheneedforaseparatepowersupply.However,ifthepodispowered separately,itcanbeconnectedtoarunningtargetsystemwithoutforcingatargetsystemresetorotherwise disturbing the running application program. BKGD 1 2 GND NO CONNECT 3 4 RESET NO CONNECT 5 6 V DD Figure15-1. BDM Tool Connector 15.2.1 BKGD Pin Description BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectionalserialcommunicationofactivebackgroundmodecommandsanddata.Duringreset,thispin is used to select between starting in active background mode or starting the user’s application program. Thispinisalsousedtorequestatimedsyncresponsepulsetoallowahostdevelopmenttooltodetermine the correct clock frequency for background debug serial communications. BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers.Thisprotocolassumesthehostknowsthecommunicationclockratethatisdetermined by the target BDC clock rate. All communication is initiated and controlled by the host that drives a high-to-lowedgetosignalthebeginningofeachbittime.Commandsanddataaresentmostsignificantbit first (MSB first). For a detailed description of the communications protocol, refer toSection15.2.2, “Communication Details.” IfahostisattemptingtocommunicatewithatargetMCUthathasanunknownBDCclockrate,aSYNC commandmaybesenttothetargetMCUtorequestatimedsyncresponsesignalfromwhichthehostcan determine the correct communication speed. BKGDisapseudo-open-drainpinandthereisanon-chippullupsonoexternalpullupresistorisrequired. Unliketypicalopen-drainpins,theexternalRCtimeconstantonthispin,whichisinfluencedbyexternal capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Section15.2.2, “Communication Details,” for more detail. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 239

Development Support Whennodebuggerpodisconnectedtothe6-pinBDMinterfaceconnector,theinternalpulluponBKGD chooses normal operating mode. When a development system is connected, it can pull both BKGD and RESET low, releaseRESET to select active background mode rather than normal operating mode, then releaseBKGD.ItisnotnecessarytoresetthetargetMCUtocommunicatewithitthroughthebackground debug interface. 15.2.2 Communication Details The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGDisapseudo-open-drainpinthatcanbedriveneitherbyanexternalcontrollerorbytheMCU.Data is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512BDCclockcyclesoccurbetweenfallingedgesfromthehost.AnyBDCcommandthatwasinprogress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. Theclockswitch(CLKSW)controlbitintheBDCstatusandcontrolregisterallowstheusertoselectthe BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source. The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronoustotheexternalhost.TheinternalBDCclocksignalisshownforreferenceincountingcycles. MC9S08GT16A/GT8A Data Sheet, Rev. 1 240 Freescale Semiconductor

Development Support Figure15-2showsanexternalhosttransmittingalogic1or0totheBKGDpinofatargetHCS08MCU. Thehostisasynchronoustothetargetsothereisa0-to-1cycledelayfromthehost-generatedfallingedge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target sensesthebitlevelontheBKGDpin.Typically,thehostactivelydrivesthepseudo-open-drainBKGDpin duringhost-to-targettransmissionstospeeduprisingedges.BecausethetargetdoesnotdrivetheBKGD pinduringthehost-to-targettransmissionperiod,thereisnoneedtotreatthelineasanopen-drainsignal during this period. BDC CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES EARLIEST START OF NEXT BIT SYNCHRONIZATION TARGET SENSES BIT LEVEL UNCERTAINTY PERCEIVED START OF BIT TIME Figure15-2. BDC Host-to-Target Serial Bit Timing MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 241

Development Support Figure15-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enoughforthetargettorecognizeit(atleasttwotargetBDCcycles).Thehostmustreleasethelowdrive beforethetargetMCUdrivesabriefactive-highspeeduppulsesevencyclesaftertheperceivedstartofthe bit time. The host should sample the bit level about 10 cycles after it started the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure15-3. BDC Target-to-Host Serial Bit Timing (Logic 1) MC9S08GT16A/GT8A Data Sheet, Rev. 1 242 Freescale Semiconductor

Development Support Figure15-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the targetHCS08finishesit.Becausethetargetwantsthehosttoreceivealogic0,itdrivestheBKGDpinlow for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE HIGH-IMPEDANCE TO BKGD PIN SPEEDUP TARGET MCU PULSE DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure15-4. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 243

Development Support 15.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commandsanddataaresentMSB-firstusingacustomBDCcommunicationsprotocol.Activebackground mode commands require that the target MCU is currently in the active background mode while non-intrusivecommandsmaybeissuedatanytimewhetherthetargetMCUisinactivebackgroundmode or running a user application program. Table15-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in Table15-1 to describe the coding structure of the BDC commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) / = separates parts of the command d = delay 16 target BDC clock cycles AAAA = a 16-bit address in the host-to-target direction RD = 8 bits of read data in the target-to-host direction WD = 8 bits of write data in the host-to-target direction RD16 = 16 bits of read data in the target-to-host direction WD16 = 16 bits of write data in the host-to-target direction SS = the contents of BDCSCR in the target-to-host direction (STATUS) CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP = 16bitsofwritedatainthehost-to-targetdirection(forBDCBKPTbreakpointregister) MC9S08GT16A/GT8A Data Sheet, Rev. 1 244 Freescale Semiconductor

Development Support Table15-1. BDC Command Summary Command Active BDM/ Coding Description Mnemonic Non-intrusive Structure Request a timed reference pulse to determine SYNC Non-intrusive n/a1 target BDC communication speed Enable acknowledge protocol. Refer to ACK_ENABLE Non-intrusive D5/d Freescale document order no. HCS08RMv1/D. Disable acknowledge protocol. Refer to ACK_DISABLE Non-intrusive D6/d Freescale document order no. HCS08RMv1/D. Enter active background mode if enabled BACKGROUND Non-intrusive 90/d (ignore if ENBDM bit equals 0) READ_STATUS Non-intrusive E4/SS Read BDC status from BDCSCR WRITE_CONTROL Non-intrusive C4/CC Write BDC controls in BDCSCR READ_BYTE Non-intrusive E0/AAAA/d/RD Read a byte from target memory READ_BYTE_WS Non-intrusive E1/AAAA/d/SS/RD Read a byte and report status Re-read byte from address just read and READ_LAST Non-intrusive E8/SS/RD report status WRITE_BYTE Non-intrusive C0/AAAA/WD/d Write a byte to target memory WRITE_BYTE_WS Non-intrusive C1/AAAA/WD/d/SS Write a byte and report status READ_BKPT Non-intrusive E2/RBKP Read BDCBKPT breakpoint register WRITE_BKPT Non-intrusive C2/WBKP Write BDCBKPT breakpoint register Go to execute the user application program GO Active BDM 08/d starting at the address currently in the PC Trace 1 user instruction at the address in the TRACE1 Active BDM 10/d PC, then return to active background mode Same as GO but enable external tagging TAGGO Active BDM 18/d (HCS08 devices have no external tagging pin) READ_A Active BDM 68/d/RD Read accumulator (A) READ_CCR Active BDM 69/d/RD Read condition code register (CCR) READ_PC Active BDM 6B/d/RD16 Read program counter (PC) READ_HX Active BDM 6C/d/RD16 Read H and X register pair (H:X) READ_SP Active BDM 6F/d/RD16 Read stack pointer (SP) Increment H:X by one then read memory byte READ_NEXT Active BDM 70/d/RD located at H:X Increment H:X by one then read memory byte READ_NEXT_WS Active BDM 71/d/SS/RD located at H:X. Report status and data. WRITE_A Active BDM 48/WD/d Write accumulator (A) WRITE_CCR Active BDM 49/WD/d Write condition code register (CCR) WRITE_PC Active BDM 4B/WD16/d Write program counter (PC) WRITE_HX Active BDM 4C/WD16/d Write H and X register pair (H:X) WRITE_SP Active BDM 4F/WD16/d Write stack pointer (SP) IncrementH:Xbyone,thenwritememorybyte WRITE_NEXT Active BDM 50/WD/d located at H:X IncrementH:Xbyone,thenwritememorybyte WRITE_NEXT_WS Active BDM 51/WD/d/SS located at H:X. Also report status. 1 The SYNC command is a special operation that does not have a command code. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 245

Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correctcommunicationsspeedtouseforBDCcommunicationsuntilafterithasanalyzedtheresponseto the SYNC command. To issue a SYNC command, the host: • DrivestheBKGDpinlowforatleast128cyclesoftheslowestpossibleBDCclock(Theslowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) • DrivesBKGDhighforabriefspeeduppulsetogetafastrisetime(Thisspeeduppulseistypically one cycle of the fastest clock in the system.) • Removes all drive to the BKGD pin so it reverts to high impedance • Monitors the BKGD pin for the sync response pulse Thetarget,upondetectingtheSYNCrequestfromthehost(whichisamuchlongerlowtimethanwould ever occur during normal BDC communications): • Waits for BKGD to return to a logic high • Delays 16cycles to allow the host to stop driving the high speedup pulse • Drives BKGD low for 128 BDC clock cycles • Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD • Removes all drive to the BKGD pin so it reverts to high impedance Thehostmeasuresthelowtimeofthis128-cyclesyncresponsepulseanddeterminesthecorrectspeedfor subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 15.2.4 BDC Hardware Breakpoint The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bitmatchvalueintheBDCBKPTregister.Thisbreakpointcangenerateaforcedbreakpointoratagged breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies that taggedbreakpointscanonlybeplacedattheaddressofaninstructionopcodewhileforcedbreakpointscan be set at any address. Thebreakpointenable(BKPTEN)controlbitintheBDCstatusandcontrolregister(BDCSCR)isusedto enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the breakpointlogicisdisabledandnoBDCbreakpointsarerequestedregardlessofthevaluesinotherBDC breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS= 0) type breakpoints. Theon-chipdebugmodule(DBG)includescircuitryfortwoadditionalhardwarebreakpointsthataremore flexible than the simple breakpoint in the BDC module. MC9S08GT16A/GT8A Data Sheet, Rev. 1 246 Freescale Semiconductor

Development Support 15.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuitemulatorhavebeenbuiltontothechipwiththeMCU.Thedebugsystemconsistsofan8-stage FIFOthatcanstoreaddressordatabusinformation,andaflexibletriggersystemtodecidewhentocapture businformationandwhatinformationtocapture.Thesystemreliesonthesingle-wirebackgrounddebug system to access debug control registers and to read results out of the eight stage FIFO. The debug module includes control and status registers that are accessible in the user’s memory map. These registers are located in the high register space to avoid using valuable direct page memory space. Mostofthedebugmodule’sfunctionsareusedduringdevelopment,anduserprogramsrarelyaccessany of the control and status registers for the debug module. The one exception is that the debug system can provide the means to implement a form of ROM patching. This topic is discussed in greater detail in Section15.3.6, “Hardware Breakpoints.” 15.3.1 Comparators A and B Two16-bitcomparators(AandB)canoptionallybequalifiedwiththeR/Wsignalandanopcodetracking circuit.SeparatecontrolbitsallowyoutoignoreR/Wforeachcomparator.Theopcodetrackingcircuitry optionally allows you to specify that a trigger will occur only if the opcode at the specified address is actuallyexecutedasopposedtoonlybeingreadfrommemoryintotheinstructionqueue.Thecomparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. Comparators are disabled temporarily during all BDC accesses. The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an additional purpose, in full address plus data comparisons they are used to decide which of these buses to useinthecomparatorBdatabuscomparisons.IfRWAEN= 1(enabled)andRWA = 0(write),theCPU’s write data bus is used. Otherwise, the CPU’s read data bus is used. Thecurrentlyselectedtriggermodedetermineswhatthedebuggerlogicdoeswhenacomparatordetects a qualified match condition. A match can cause: • Generation of a breakpoint to the CPU • Storage of data bus values into the FIFO • Starting to store change-of-flow addresses into the FIFO (begin type trace) • Stopping the storage of change-of-flow addresses into the FIFO (end type trace) 15.3.2 Bus Capture Information and FIFO Operation The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of wordsofvalidinformationthatareintheFIFOasdataisstoredintoit.Ifatracerunismanuallyhaltedby writing0toARMbeforetheFIFOisfull(CNT=1:0:0:0),theinformationisshiftedbyonepositionand MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 247

Development Support thehostmustperform((8–CNT)–1)dummyreadsoftheFIFOtoadvanceittothefirstsignificantentry in the FIFO. Inmosttriggermodes,theinformationstoredintheFIFOconsistsof16-bitchange-of-flowaddresses.In thesecases,readDBGFHthenDBGFLtogetonecoherentwordofinformationoutoftheFIFO.Reading DBGFL(thelow-orderbyteoftheFIFOdataport)causestheFIFOtoshiftsothenextwordofinformation isavailableattheFIFOdataport.Intheevent-onlytriggermodes(seeSection15.3.5,“TriggerModes”), 8-bitdatainformationisstoredintotheFIFO.Inthesecases,thehigh-orderhalfoftheFIFO(DBGFH)is notusedanddataisreadoutoftheFIFObysimplyreadingDBGFL.EachtimeDBGFLisread,theFIFO is shifted so the next data value is available through the FIFO data port at DBGFL. In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU addressesandtheinputsideoftheFIFO.Becauseofthisdelay,ifthetriggereventitselfisachange-of-flow addressorachange-of-flowaddressappearsduringthenexttwobuscyclesafteratriggereventstartsthe FIFO,itwillnotbesavedintotheFIFO.Inthecaseofanend-trace,ifthetriggereventisachange-of-flow, it will be saved as the last change-of-flow entry for that debug run. TheFIFOcanalsobeusedtogenerateaprofileofexecutedinstructionaddresseswhenthedebuggerisnot armed. When ARM = 0, reading DBGFL causes the address of the most-recently fetched opcode to be savedintheFIFO.Tousetheprofilingfeature,ahostdebuggerwouldreadaddressesoutoftheFIFOby reading DBGFH then DBGFL at regular periodic intervals. The first eight values would be discarded because they correspond to the eight DBGFL reads needed to initially fill the FIFO. Additional periodic readsofDBGFHandDBGFLreturndelayedinformationaboutexecutedinstructionssothehostdebugger can develop a profile of executed instruction addresses. 15.3.3 Change-of-Flow Information To minimize the amount of information stored in the FIFO, only information related to instructions that causeachangetothenormalsequentialexecutionofinstructionsisstored.Withknowledgeofthesource andobjectcodeprogramstoredinthetargetsystem,anexternaldebuggersystemcanreconstructthepath of execution through many instructions from the change-of-flow information stored in the FIFO. For conditional branch instructions where the branch is taken (branch condition was true), the source addressisstored(theaddressoftheconditionalbranchopcode).BecauseBRAandBRNinstructionsare not conditional, these events do not cause change-of-flow information to be stored in the FIFO. IndirectJMPandJSRinstructionsusethecurrentcontentsoftheH:Xindexregisterpairtodeterminethe destination address, so the debug system stores the run-time destination address for any indirect JMP or JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-flow information. 15.3.4 Tag vs. Force Breakpoints and Triggers Taggingisatermthatreferstoidentifyinganinstructionopcodeasitisfetchedintotheinstructionqueue, but not taking any other action until and unless that instruction is actually executed by the CPU. This distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt causessomeinstructionsthathavebeenfetchedintotheinstructionqueuetobethrownawaywithoutbeing executed. MC9S08GT16A/GT8A Data Sheet, Rev. 1 248 Freescale Semiconductor

Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. Thetagvs.forceterminologyisusedintwocontextswithinthedebugmodule.Thefirstcontextrefersto breakpoint requests from the debug module to the CPU. The second refers to match signals from the comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is enteredintotheinstructionqueuealongwiththeopcodesothatif/whenthisopcodeeverexecutes,theCPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active background moderatherthanexecutingthetaggedinstruction.WhentheTRGSELcontrolbitintheDBGTregisteris set to select tag-type operation, the output from comparator A or B is qualified by a block of logic in the debugmodulethattracksopcodesandonlyproducesatriggertothedebuggeriftheopcodeatthecompare addressisactuallyexecuted.Thereisseparateopcodetrackinglogicforeachcomparatorsomorethanone compare event can be tracked through the instruction queue at a time. 15.3.5 Trigger Modes Thetriggermodecontrolstheoverallbehaviorofadebugrun.The4-bitTRGfieldintheDBGTregister selectsoneofninetriggermodes.WhenTRGSEL = 1intheDBGTregister,theoutputofthecomparator must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in DBGTchooseswhethertheFIFObeginsstoringdatawhenthequalifiedtriggerisdetected(begintrace), ortheFIFOstoresdatainacircularfashionfromthetimeitisarmeduntilthequalifiedtriggerisdetected (end trigger). Adebugrunisstartedbywritinga1totheARMbitintheDBGCregister,whichsetstheARMFflagand clearstheAFandBFflagsandtheCNTbitsinDBGS.Abegin-tracedebugrunendswhentheFIFOgets full.Anend-tracerunendswhentheselectedtriggereventoccurs.Anydebugruncanbestoppedmanually by writing a 0 to ARM or DBGEN in DBGC. In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only trigger modes, the FIFO stores data in the low-order eight bits of the FIFO. The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type traces.WhenTRGSEL= 1toselectopcodefetchtriggers,itisnotnecessarytouseR/Wincomparisons because opcode tags would only apply to opcode fetches that are always read cycles. It would also be unusual to specify TRGSEL = 1 while using a full mode trigger because the opcode value is normally known at a particular address. Thefollowingtriggermodedescriptionsonlystatetheprimarycomparatorconditionsthatleadtoatrigger. Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and the corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1 and TAG determines whether the CPU request will be a tag request or a force request. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 249

Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally) mustmatchwithinthesamebuscycletocauseatriggerevent.ComparatorAchecksaddress,thelowbyte of comparator B checks data, and R/W is checked against RWA if RWAEN= 1. The high-order half of comparator B is not used. Infulltriggermodesitisnotusefultospecifyatag-typeCPUbreakpoint(BRKEN = TAG= 1),butifyou do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low halfofcomparatorB,andR/WmustmatchRWAifRWAEN= 1.Allthreeconditionsmustbemetwithin the same bus cycle to cause a trigger. Infulltriggermodesitisnotusefultospecifyatag-typeCPUbreakpoint(BRKEN = TAG= 1),butifyou do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. Event-Only B (Store Data) — Trigger events occur each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. AThenEvent-OnlyB(StoreData)—AftertheaddresshasmatchedthevalueincomparatorA,atrigger eventoccurseachtimetheaddressmatchesthevalueincomparatorB.Triggereventscausethedatatobe captured into the FIFO. The debug run ends when the FIFO becomes full. InsideRange(A≤Address≤B)—Atriggeroccurswhentheaddressisgreaterthanorequaltothevalue in comparator A and less than or equal to the value in comparator B at the same time. Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than the value in comparator A or greater than the value in comparator B. MC9S08GT16A/GT8A Data Sheet, Rev. 1 250 Freescale Semiconductor

Development Support 15.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions describedinSection15.3.5,“TriggerModes,”tobeusedtogenerateahardwarebreakpointrequesttothe CPU.TAGinDBGCcontrolswhetherthebreakpointrequestwillbetreatedasatag-typebreakpointora force-typebreakpoint.Atagbreakpointcausesthecurrentopcodetobemarkedasitenterstheinstruction queue.Ifataggedopcodereachestheendofthepipe,theCPUexecutesaBGNDinstructiontogotoactive background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to finish the current instruction and then go to active background mode. If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background mode. 15.4 Register Definition This section contains the descriptions of the BDC and DBG registers and control bits. Refertothehigh-pageregistersummaryinthedeviceoverviewchapterofthisdatasheetfortheabsolute address assignments for all DBG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 15.4.1 BDC Registers and Control Bits The BDC has two registers: • The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller. • The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address. These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU (so they do not have addresses and cannot be accessed by user programs). SomeofthebitsintheBDCSCRhavewritelimitations;otherwise,theseregistersmaybereadorwritten at any time. For example, the ENBDM control bit may not be written while the MCU is in active backgroundmode.(Thispreventstheambiguousconditionofthecontrolbitforbiddingactivebackground mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS, WSF,andDVF)areread-onlystatusindicatorsandcanneverbewrittenbytheWRITE_CONTROLserial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 251

Development Support 15.4.1.1 BDC Status and Control Register (BDCSCR) ThisregistercanbereadorwrittenbyserialBDCcommands(READ_STATUSandWRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 6 5 4 3 2 1 0 R BDMACT WS WSF DVF ENBDM BKPTEN FTS CLKSW W Normal 0 0 0 0 0 0 0 0 Reset Reset in 1 1 0 0 1 0 0 0 Active BDM: = Unimplemented or Reserved Figure15-5. BDC Status and Control Register (BDCSCR) Table15-2. BDCSCR Register Field Descriptions Field Description 7 Enable BDM (Permit Active Background Mode)— Typically, this bit is written to 1 by the debug host shortly ENBDM afterthebeginningofadebugsessionorwheneverthedebughostresetsthetargetandremains1untilanormal reset clears it. 0 BDM cannot be made active (non-intrusive commands still allowed) 1 BDM can be made active to allow active background mode commands 6 Background Mode Active Status — This is a read-only status bit. BDMACT 0 BDM not active (user application program running) 1 BDM active and waiting for serial commands 5 BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) BKPTEN control bit and BDCBKPT match register are ignored. 0 BDC breakpoint disabled 1 BDC breakpoint enabled 4 Force/Tag Select — When FTS=1, a breakpoint is requested whenever the CPU address bus matches the FTS BDCBKPT match register. When FTS=0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters active background mode rather than executing the tagged opcode. 0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that instruction 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC CLKSW clock source. 0 Alternate BDC clock source 1 MCU bus clock MC9S08GT16A/GT8A Data Sheet, Rev. 1 252 Freescale Semiconductor

Development Support Table15-2. BDCSCR Register Field Descriptions (continued) Field Description 2 Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. WS However,theBACKGROUNDcommandcanbeusedtoforcethetargetCPUoutofwaitorstopandintoactive background mode where all BDC commands work. Whenever the host forces the target MCU into active background mode, the host should issue a READ_STATUS command to check that BDMACT=1 before attempting other BDC commands. 0 TargetCPUisrunninguserapplicationcodeorinactivebackgroundmode(wasnotinwaitorstopmodewhen background became active) 1 TargetCPUisinwaitorstopmode,oraBACKGROUNDcommandwasusedtochangefromwaitorstopto active background mode 1 WaitorStopFailureStatus—ThisstatusbitissetifamemoryaccesscommandfailedduetothetargetCPU WSF executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command thatfailed,thenreturntotheuserprogram.(Typically,thehostwouldrestoreCPUregistersandstackvaluesand re-execute the wait or stop instruction.) 0 Memory access did not conflict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode 0 DataValidFailureStatus—ThisstatusbitisnotusedintheMC9S08GT16A/GT8Abecauseitdoesnothave DVF any slow access memory. 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a slow memory access 15.4.1.2 BDC Breakpoint Match Register (BDCBKPT) This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal memory map of the MCU. BreakpointsarenormallysetwhilethetargetMCUisinactivebackgroundmodebeforerunningtheuser application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer to Section15.2.4, “BDC Hardware Breakpoint.” 15.4.2 System Background Debug Force Reset Register (SBDFR) This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTEmustbeusedtowritetoSBDFR.Attemptstowritethisregisterfromauserprogramare ignored. Reads always return 0x00. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 253

Development Support 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W BDFR1 Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure15-6. System Background Debug Force Reset Register (SBDFR) Table15-3. SBDFR Register Field Description Field Description 0 BackgroundDebugForceReset—AserialactivebackgroundmodecommandsuchasWRITE_BYTEallows BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. 15.4.3 DBG Registers and Control Bits The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers. These registers are located in the high register space of the normal memory map so theyareaccessible to normalapplication programs.These registersarerarely ifeveraccessed bynormal user application programs with the possible exception of a ROM patching mechanism that uses the breakpoint logic. 15.4.3.1 Debug Comparator A High Register (DBGCAH) This register contains compare value bits for the high-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 15.4.3.2 Debug Comparator A Low Register (DBGCAL) This register contains compare value bits for the low-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 15.4.3.3 Debug Comparator B High Register (DBGCBH) This register contains compare value bits for the high-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 15.4.3.4 Debug Comparator B Low Register (DBGCBL) This register contains compare value bits for the low-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. MC9S08GT16A/GT8A Data Sheet, Rev. 1 254 Freescale Semiconductor

Development Support 15.4.3.5 Debug FIFO High Register (DBGFH) Thisregisterprovidesread-onlyaccesstothehigh-ordereightbitsoftheFIFO.Writestothisregisterhave nomeaningoreffect.Intheevent-onlytriggermodes,theFIFOonlystoresdataintothelow-orderbyteof each FIFO word, so this register is not used and will read 0x00. ReadingDBGFHdoesnotcausetheFIFOtoshifttothenextword.Whenreading16-bitwordsoutofthe FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the next word of information. 15.4.3.6 Debug FIFO Low Register (DBGFL) Thisregisterprovidesread-onlyaccesstothelow-ordereightbitsoftheFIFO.Writestothisregisterhave no meaning or effect. Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each FIFOwordisunused).Whenreading8-bitwordsoutoftheFIFO,simplyreadDBGFLrepeatedlytoget successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case. DonotattempttoreaddatafromtheFIFOwhileitisstillarmed(afterarmingbutbeforetheFIFOisfilled or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can interfere with normal sequencing of reads from the FIFO. ReadingDBGFLwhilethedebuggerisnotarmedcausestheaddressofthemost-recentlyfetchedopcode tobestoredtothelastlocationintheFIFO.ByreadingDBGFHthenDBGFLperiodically,externalhost softwarecandevelopaprofileofprogramexecution.AftereightreadsfromtheFIFO,theninthreadwill returntheinformationthatwasstoredasaresultofthefirstread.Tousetheprofilingfeature,readtheFIFO eight times without using the data to prime the sequence and then begin using the data to get a delayed pictureofwhataddresseswerebeingexecuted.TheinformationstoredintotheFIFOonreadsofDBGFL (while the FIFO is not armed) is the address of the most-recently fetched opcode. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 255

Development Support 15.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN W Reset 0 0 0 0 0 0 0 0 Figure15-7. Debug Control Register (DBGC) Table15-4. DBGC Register Field Descriptions Field Description 7 Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure. DBGEN 0 DBG disabled 1 DBG enabled 6 ArmControl—ControlswhetherthedebuggeriscomparingandstoringinformationintheFIFO.Awriteisused ARM tosetthisbit(andARMF)andcompletionofadebugrunautomaticallyclearsit.Anydebugruncanbemanually stopped by writing 0 to ARM or to DBGEN. 0 Debugger not armed 1 Debugger armed 5 Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If TAG BRKEN=0, this bit has no meaning or effect. 0 CPU breaks requested as force type requests 1 CPU breaks requested as tag type requests 4 BreakEnable—ControlswhetheratriggereventwillgenerateabreakrequesttotheCPU.Triggereventscan BRKEN causeinformationtobestoredintheFIFOwithoutgeneratingabreakrequesttotheCPU.Foranendtrace,CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a begintrace,CPUbreakrequestsareissuedwhentheFIFObecomesfull.TRGSELdoesnotaffectthetimingof CPU break requests. 0 CPU break requests not enabled 1 Triggers cause a break request to the CPU 3 R/WComparisonValueforComparatorA—WhenRWAEN=1,thisbitdetermineswhetherareadorawrite RWA access qualifies comparator A. When RWAEN=0, RWA and the R/W signal do not affect comparator A. 0 Comparator A can only match on a write cycle 1 Comparator A can only match on a read cycle 2 Enable R/W for Comparator A— Controls whether the level of R/W is considered for a comparator A match. RWAEN 0 R/W is not used in comparison A 1 R/W is used in comparison A 1 R/WComparisonValueforComparatorB—WhenRWBEN=1,thisbitdetermineswhetherareadorawrite RWB access qualifies comparator B. When RWBEN=0, RWB and the R/W signal do not affect comparator B. 0 Comparator B can match only on a write cycle 1 Comparator B can match only on a read cycle 0 Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match. RWBEN 0 R/W is not used in comparison B 1 R/W is used in comparison B MC9S08GT16A/GT8A Data Sheet, Rev. 1 256 Freescale Semiconductor

Development Support 15.4.3.8 Debug Trigger Register (DBGT) Thisregistercanbereadanytime,butmaybewrittenonlyifARM= 0,exceptbits4and5arehard-wired to 0s. 7 6 5 4 3 2 1 0 R 0 0 TRGSEL BEGIN TRG3 TRG2 TRG1 TRG0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure15-8. Debug Trigger Register (DBGT) Table15-5. DBGT Register Field Descriptions Field Description 7 Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode TRGSEL tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate throughtheopcodetrackinglogicandatriggereventisonlysignalledtotheFIFOlogiciftheopcodeatthematch address is actually executed. 0 Trigger on access to compare address (force) 1 Trigger if opcode at compare address is executed (tag) 6 Begin/EndTriggerSelect—ControlswhethertheFIFOstartsfillingatatriggerorfillsinacircularmanneruntil BEGIN a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 Data stored in FIFO until trigger (end trace) 1 Trigger initiates data storage (begin trace) 3:0 Select Trigger Mode — Selects one of nine triggering modes, as described below. TRG[3:0] 0000 A-only 0001 A OR B 0010 A Then B 0011 Event-only B (store data) 0100 A then event-only B (store data) 0101 A AND B data (full mode) 0110 A AND NOT B data (full mode) 0111 Inside range: A≤ address≤ B 1000 Outside range: address < A or address > B 1001 – 1111 (No trigger) MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 257

Development Support 15.4.3.9 Debug Status Register (DBGS) This is a read-only status register. 7 6 5 4 3 2 1 0 R AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure15-9. Debug Status Register (DBGS) Table15-6. DBGS Register Field Descriptions Field Description 7 Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A AF condition was met since arming. 0 Comparator A has not matched 1 Comparator A match 6 Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B BF condition was met since arming. 0 Comparator B has not matched 1 Comparator B match 5 ArmFlag—WhileDBGEN=1,thisstatusbitisaread-onlyimageofARMinDBGC.Thisbitissetbywriting1 ARMF to the ARM control bit in DBGC (while DBGEN=1) and is automatically cleared at the end of a debug run. A debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC. 0 Debugger not armed 1 Debugger armed 3:0 FIFOValidCount—Thesebitsareclearedatthestartofadebugrunandindicatethenumberofwordsofvalid CNT[3:0] dataintheFIFOattheendofadebugrun.ThevalueinCNTdoesnotdecrementasdataisreadoutoftheFIFO. The external debug host is responsible for keeping track of the count as information is read out of the FIFO. 0000 Number of valid words in FIFO = No valid data 0001 Number of valid words in FIFO = 1 0010 Number of valid words in FIFO = 2 0011 Number of valid words in FIFO = 3 0100 Number of valid words in FIFO = 4 0101 Number of valid words in FIFO = 5 0110 Number of valid words in FIFO = 6 0111 Number of valid words in FIFO = 7 1000 Number of valid words in FIFO = 8 MC9S08GT16A/GT8A Data Sheet, Rev. 1 258 Freescale Semiconductor

Appendix A Electrical Characteristics A.1 Introduction This section contains electrical and timing specifications. A.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: TableA-1. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant C sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices T under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. A.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in TableA-2 may affect device reliability or cause permanentdamagetothedevice.Forfunctionaloperatingconditions,refertotheremainingtablesinthis section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputsaretiedtoanappropriatelogicvoltagelevel(forinstance,eitherV orV )ortheprogrammable SS DD pull-up resistor associated with the pin is enabled. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 259

Electrical Characteristics TableA-2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to +3.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD+0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1,2,3 ID ± 25 mA Storage temperature range Tstg –55 to 150 °C Maximum junction temperature T 150 °C J 1 Input must be current limited to the value specified. To determine the value of the required current-limitingresistor,calculateresistancevaluesforpositive(V )andnegative(V )clamp DD SS voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V and V . SS DD 3 Power supply must maintain regulation within operating V range during instantaneous and DD operating maximum current conditions. If positive injection current (V > V ) is greater than In DD I , the injection current may flow out of V and could result in external power supply going DD DD out of regulation. Ensure external V load will shunt current greater than maximum injection DD current.ThiswillbethegreatestriskwhentheMCUisnotconsumingpower.Examplesare:if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. A.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the MCU design. In order to take P into account in power calculations, determine the difference between I/O actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of SS DD unusuallyhighpincurrent(heavyloads),thedifferencebetweenpinvoltageandV orV willbevery SS DD small. MC9S08GT16A/GT8A Data Sheet, Rev. 1 260 Freescale Semiconductor

Electrical Characteristics TableA-3. Thermal Characteristics Rating Symbol Value Unit Operating temperature range T to T T L H °C (packaged) A –40 to 125 Thermal resistance 1s board type 48-pin QFN 84 44-pin QFP θ 1, 2 72 °C/W JA 42-pin SDIP 62 32-pin QFN 99 Thermal resistance 2s2p board type 48-pin QFN 26 44-pin QFP θ 1,2 54 °C/W JA 42-pin SDIP 51 32-pin QFN 33 1 Junction temperature is a function of die size, on-chip power dissipation, package thermalresistance,mountingsite(board)temperature,ambienttemperature,airflow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Single layer board is designed per JEDEC JESD51-3. The average chip-junction temperature (T ) in°C can be obtained from: J T = T + (P ×θ ) Eqn.A-1 J A D JA where: T = Ambient temperature,°C A θ = Package thermal resistance, junction-to-ambient,°C/W JA P = P + P D int I/O P = I × V , Watts — chip internal power int DD DD P = Power dissipation on input and output pins — user determined I/O Formostapplications,P <<P andcanbeneglected.AnapproximaterelationshipbetweenP andT I/O int D J (if P is neglected) is: I/O P = K÷ (T + 273°C) Eqn.A-2 D J Solving equations 1 and 2 for K gives: K = P × (T + 273°C) +θ × (P )2 Eqn.A-3 D A JA D whereKisaconstantpertainingtotheparticularpart.Kcanbedeterminedfromequation3bymeasuring P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by D A D J solving equations 1 and 2 iteratively for any value of T . A MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 261

Electrical Characteristics A.5 Electrostatic Discharge (ESD) Protection Characteristics Althoughdamagefromelectrostaticdischarge(ESD)ismuchlesscommononthesedevicesthanonearly CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualificationtestsareperformedtoensurethatthesedevicescanwithstandexposuretoreasonablelevels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification TableA-4. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Human Body Series Resistance R1 1500 Ω Storage Capacitance C 100 pF Number of Pulse per pin — 3 Machine Series Resistance R1 0 Ω Storage Capacitance C 200 pF Number of Pulse per pin — 3 Charge Device Series Resistance R1 Ω Model Storage Capacitance C pF Number of Pulse per pin — Latch-Up Minimum input voltage limit –2.5 V Maximum input voltage limit 7.5 V A.6 DC Characteristics This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. TableA-5. MCU Operating Conditions Characteristic Min Typ Max Unit Supply Voltage 1.8 — 3.6 V Temperature °C M –40 — 125 C –40 — 85 MC9S08GT16A/GT8A Data Sheet, Rev. 1 262 Freescale Semiconductor

Electrical Characteristics TableA-6. DC Characteristics (Sheet 1 of 2) (Temperature Range = –40 to 125°C Ambient) C Parameter Symbol Min Typical1 Max Unit Minimum RAM retention supply voltageapplied to V 1.02 — V RAM V DD P Low-voltage detection threshold — high range V V LVDH (V falling) 2.08 2.1 2.2 DD (V rising) 2.16 2.19 2.27 DD P Low-voltage detection threshold — low range V V LVDL (V falling) 1.80 1.82 1.91 DD (V rising) 1.88 1.90 1.99 DD P Low-voltage warning threshold — high range V V LVWH (V falling) 2.35 2.40 2.5 DD (V rising) 2.35 2.40 2.5 DD P Low-voltage warning threshold — low range V (VDD falling) VLVWL 2.08 2.1 2.2 (V rising) 2.16 2.19 2.27 DD P Power on reset (POR) re-arm voltage(2) V Mode = stop VRearm 0.20 0.30 0.40 Mode = run and Wait 0.50 0.80 1.2 P Input high voltage (VDD > 2.3 V) (all digital inputs) VIH 0.70× VDD — V P Inp(aultl hdiigghit avlo ilntapguets ()1.8 V≤ VDD≤2.3 V) VIH 0.85× VDD — V P Input low voltage (VDD > 2.3 V) (all digital inputs) VIL — 0.35× VDD V P Inp(aultl ldoiwgi tvaol litnapguet s(1).8 V≤ VDD≤2.3 V) VIL — 0.30× VDD V Y Input hysteresis (all digital inputs) Vhys 0.06× VDD — V P Input leakage current (per pin) µA V = V or V all input only pins |IIn| — 0.025 1.0 In DD SS, P Highimpedance(off-state)leakagecurrent(perpin) µA V = V or V , all input/output |IOZ| — 0.025 1.0 In DD SS P Internal pullup and pulldown resistors3 kΩ (all port pins and IRQ) RPU 17.5 52.5 p Internal pulldown resistors (Port A4–A7 and IRQ) RPD 17.5 52.5 kΩ P Output high voltage (V ≥ 1.8 V) DD IOH= –2 mA (ports A, B, D, E, and G) VDD – 0.5 — V V P Output high voltage (port C) OH IOH= –10 mA (VDD≥ 2.7 V) V – 0.5 — IOH= –6 mA (VDD≥ 2.3 V) DD — IOH= –3 mA (VDD≥ 1.8 V) — D Maximum total IOH for all port pins |IOHT| — 60 mA MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 263

Electrical Characteristics TableA-6. DC Characteristics (Sheet 2 of 2) (Temperature Range = –40 to 125°C Ambient) C Parameter Symbol Min Typical1 Max Unit D Output low voltage (V ≥ 1.8 V) DD IOL= 2.0 mA (ports A, B, D, E, and G) — 0.5 V D Output low voltage (port C) V OL IOL= 10.0 mA (VDD≥ 2.7 V) — 0.5 IOL= 6 mA (VDD≥ 2.3 V) — 0.5 IOL= 3 mA (VDD≥ 1.8 V) — 0.5 D Maximum total IOL for all port pins IOLT — 60 mA dc injection current 4,5,6,7 DC Injection Current A, B, C, D Single pin limit V > V 0 - 2 mA IN DD |I | V < V IC 0 - –0.2 mA IN SS Total MCU limit, includes sum of all stressed pins V > V 0 - 25 mA IN DD V < V 0 - –5 mA IN SS C Input capacitance (all non-supply pins)(2) CIn — 7 pF 1 Typicals are measured at 25°C. 2 This parameter is characterized and not tested on each device. 3 Measurement condition for pull resistors: V = V for pullup and V = V for pulldown. In SS In DD 4 Power supply must maintain regulation within operating V range during instantaneous and operating maximum current DD conditions.Ifpositiveinjectioncurrent(V >V )isgreaterthanI ,theinjectioncurrentmayflowoutofV andcouldresult In DD DD DD in external power supply going out of regulation. Ensure external V load will shunt current greater than maximum injection DD current.ThiswillbethegreatestriskwhentheMCUisnotconsumingpower.Examplesare:ifnosystemclockispresent,or if clock rate is very low which (would reduce overall power consumption). 5 All functional non-supply pins are internally clamped to V and V . SS DD 6 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 7 IRQ does not have a clamp diode to V . Do not drive IRQ above V . DD DD PULLUP RESISTOR TYPICALS 40 PULLDOWN RESISTOR TYPICALS 85°C 40 – 2450°°CC Ωk) 8255°°CC Ω)35 E ( –40°C UP RESISTOR (k2350 WN RESISTANC 3305 PULL- ULLDO 25 20 P 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 20 V (V) 1.8 2.3 2.8 3.3 3.6 DD V (V) DD FigureA-1. Pullup and Pulldown Typical Resistor Values (V = 3.0 V) DD MC9S08GT16A/GT8A Data Sheet, Rev. 1 264 Freescale Semiconductor

Electrical Characteristics TYPICAL VOL VS IOL AT VDD= 3.0 V TYPICAL VOL VS VDD 1 85°C 0.4 85°C 25°C 25°C 0.8 –40°C –40°C 0.3 0.6 V (V)OL 0.4 V (V)OL 0.2 IOL = 6 mA IOL= 10 mA 0.1 0.2 I = 3 mA OL 0 0 0 10 20 30 1 2 3 4 V (V) I (mA) DD OL FigureA-2. Typical Low-Side Driver (Sink) Characteristics (Port C) TYPICAL V VS I AT V = 3.0 V TYPICAL V VS V OL OL DD OL DD 1.2 85°C 0.2 25°C 1 –40°C 0.15 0.8 V) 0.6 V) 0.1 V (OL 0.4 V (OL 0.05 85°C,IOL= 2 mA 0.2 25°C,IOL= 2 mA –40°C,IOL= 2 mA 0 0 0 5 10 15 20 1 2 3 4 V (V) I (mA) DD OL FigureA-3. Typical Low-Side Driver (Sink) Characteristics (Ports A, B, D, E, and G) TYPICAL V – V VS V AT SPEC I DD OH DD OH 0.4 TYPICAL V – V VS I AT V = 3.0 V 85°C 0.8 85°C DD OH OH DD – 2450°°CC 25°C 0.3 V) 0.6 –40°C (H V) V – VDDO 00..24 – V (DOH 00..12 IOH= –6 mA IOH= –10 mA 0 VD IOH= –3 mA 0 –5 –10 –15 –20 –25 –30 0 I (mA) OH 1 2 3 4 V (V) DD FigureA-4. Typical High-Side Driver (Source) Characteristics (Port C) MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 265

Electrical Characteristics TYPICAL VDD– VOH VS IOH AT VDD= 3.0 V TYPICAL VDD– VOH VS VDD AT SPEC IOH (V)H 01..821 – 824550°°°CCC (V)H 00..012.552 – 824550°°°CCC,,,IIIOOOHHH=== 222 mmmAAA O O V 0.6 V – – D D 0.1 D 0.4 D V V 0.2 0.05 0 0 0 –5 –10 –15 –20 1 2 3 4 IOH (mA) VDD (V) FigureA-5. Typical High-Side (Source) Characteristics (Ports A, B, D, E, and G) A.7 Supply Current Characteristics TableA-7. Supply Current Characteristics Parameter Symbol V (V) Typical1 Max2 Temp. (°C) DD 3 3 0.8 mA 1.3 mA4 125 Run supply current measured at RI DD (CPU clock = 2MHz, fBus = 1 MHz) 2 0.66 mA 1.0 mA(4) 125 Run supply current (3) measured at 3 4.3 mA 7.0 mA5 125 RI DD (CPU clock = 16MHz, fBus = 8 MHz) 2 3.3 mA 4.5 mA(4) 125 0.6µA(4) 55 1.8µA(4) 70 3 25 nA 4.0µA(5) 85 13µA(5) 125 Stop1 mode supply current S1I DD 500 nA(4) 55 1.5µA(4) 70 2 20 nA 3.3µA(4) 85 10µA(4) 125 3.0µA(4) 55 5.5µA(4) 70 3 550 nA 11µA(5) 85 20µA(5) 125 Stop2 mode supply current S2I DD 2.4µA(4) 55 5.0µA(4) 70 2 400 nA 9.5µA(4) 85 17µA(4) 125 MC9S08GT16A/GT8A Data Sheet, Rev. 1 266 Freescale Semiconductor

Electrical Characteristics TableA-7. Supply Current Characteristics (continued) Parameter Symbol V (V) Typical1 Max2 Temp. (°C) DD 4.3µA(4) 55 7.2µA(4) 70 3 675 nA 17.0µA(5) 85 45µA(5) 125 Stop3 mode supply current S3I DD 3.5µA(4) 55 6.2µA(4) 70 2 500 nA 15.0µA(4) 85 40µA(4) 125 3 300 nA RTI adder to stop2 or stop36 2 300 nA LVI adder to stop3 3 70µA (LVDSE = LVDE = 1) 2 60µA Adder to stop3 for oscillator enabled7 3 5µA (OSCSTEN =1) 2 5µA Adder for loss-of-clock enabled 3 9µA (LOCD=0) 2 9µA Adder for high gain oscillator enabled 3 28µA (HGO=1) 2 2µA 1 Typicals are measured at 25°C. SeeTableA-6 throughTableA-9 for typical curves across voltage/temperature. 2 Values given here are preliminary estimates prior to completing characterization. 3 All modules except ATD active, ICG configured for FBE, and does not include any dc loads on port pins 4 Values are characterized but not tested on every part. 5 Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization. 6 Mostcustomersareexpectedtofindthatauto-wakeupfromstop2orstop3canbeusedinsteadofthehighercurrentwaitmode. Wait mode typical is 560µA at 3 V and 422µA at 2V with f = 1 MHz. Bus 7 Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0), clock monitor disabled (LOCD = 1). MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 267

Electrical Characteristics 14 = FEI mode, ATD off, 20 MHz 12 = FBE mode, ATD off, 20 MHz 10 = FEI mode, ATD off, 16 MHz 8 I (mA) DD = FBE mode, all modules enabled, 8 MHz 6 = FEI mode, ATD off, 8 MHz 4 2 = FEI mode, ATD off, 1 MHz = FBE mode, ATD off, 1 MHz 0 1.801.902.002.102.202.302.402.502.602.702.802.903.003.103.203.303.403.503.60 V (Vdc) DD FigureA-6. Typical Run I for FBE and FEE Modes, I vs V DD DD DD MC9S08GT16A/GT8A Data Sheet, Rev. 1 268 Freescale Semiconductor

Electrical Characteristics 1.4 1.2 1 0.8 µD (A) 0.6 728555°°°CCC D 105°C I 125°C 0.4 0.2 0 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VDD (Vdc) FigureA-7. Typical Stop1 I DD MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 269

Electrical Characteristics FigureA-8. Typical Stop 2 I DD MC9S08GT16A/GT8A Data Sheet, Rev. 1 270 Freescale Semiconductor

Electrical Characteristics FigureA-9. Typical Stop3 I DD MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 271

Electrical Characteristics A.8 ATD Characteristics TableA-8. ATD Electrical Characteristics (Operating) No. Characteristic Condition Symbol Min Typ Max Unit 1 ATD supply1 V 1.80 — 3.6 V DDAD 2 ATD supply current Enabled I — 0.7 1.2 mA DDADrun Disabled I — 0.02 0.6 µA DDADstop (ATDPU = 0 or STOP) 3 Differential supply voltage V –V |V | — — 100 mV DD DDAD DDLT 4 Differential ground voltage V –V |V | — — 100 mV SS SSAD SDLT 5 Reference potential, low |V | — — V V REFL SSAD Reference potential, high 2.08V< V < 3.6V V 2.08 — V V DDAD REFH DDAD 1.80V< V < 2.08V V — V DDAD DDAD DDAD 6 Reference supply current Enabled I — 200 300 µA REF (V to V ) REFH REFL Disabled I — <0.01 0.02 REF (ATDPU = 0 or STOP) 7 Analog input voltage2 V V – 0.3 — V + 0.3 V INDC SSAD DDAD 1 V must be at same potential as V . DDAD DD 2 Maximum electrical operating range, not valid conversion range. TableA-9. ATD Timing/Performance Characteristics1 No. Characteristic Condition Symbol Min Typ Max Unit 1 ATD conversion clock 2.08V< V < 3.6V f 0.5 — 2.0 MHz DDAD ATDCLK frequency 1.80V< V < 2.08V 0.5 — 1.0 DDAD 2 Conversion cycles CC 28 28 <30 ATDCLK (continuous convert)2 cycles 3 Conversion time 2.08V< V < 3.6V T 14.0 — 60.0 µs DDAD conv (Including sample time) 1.80V< V < 2.08V 28.0 — 60.0 DDAD 4 ATD sample time t t — 14 — ATDCLK ADS ADS cycles 5 Sourceimpedanceatinput3 R — — 10 kΩ AS 6 Analog Input Voltage4 V V V V AIN REFL REFH MC9S08GT16A/GT8A Data Sheet, Rev. 1 272 Freescale Semiconductor

Electrical Characteristics TableA-9. ATD Timing/Performance Characteristics1 (continued) No. Characteristic Condition Symbol Min Typ Max Unit Ideal resolution (1 LSB)5 2.08V< V < 3.6V RES 2.031 — 3.516 mV DDAD 7 1.80V< V < 2.08V 1.758 — 2.031 DDAD 8 Differential non-linearity6 1.80V< VDDAD< 3.6V DNL — +0.5 +1.0 LSB 9 Integral non-linearity7 1.80 V< VDDAD< 3.6V INL — +0.5 +1.0 LSB 10 Zero-scale error8 1.80V< VDDAD< 3.6V EZS — +0.4 +1.0 LSB 11 Full-scale error9 1.80V< VDDAD< 3.6V EFS — +0.4 +1.0 LSB 12 Input leakage error 10 1.80V< VDDAD< 3.6V EIL — +0.05 +5 LSB Total unadjusted 13 error11 1.80V< VDDAD< 3.6V ETU — +1.1 +2.5 LSB 14 Input resistance R — 5 7 kΩ AIN 15 Input capacitance C — — 25 pF AIN 1 AllACCURACYnumbersarebasedonprocessorandsystembeinginWAITstate(verylittleactivityandnoIOswitching)andthat adequatelow-passfilteringispresentonanaloginputpins(filterwith0.01µFto0.1µFcapacitorbetweenanaloginputandV ). REFL Failure to observe these guidelines may result in system or microcontroller noise causing accuracy errors which will vary based on board layout and the type and magnitude of the activity. 2 Thisistheconversiontimeforsubsequentconversionsincontinuousconvertmode.Actualconversiontimeforsingleconversions orthefirstconversionincontinuousmodeisextendedbyoneATDclockcycleand2buscyclesduetostartingtheconversionand setting the CCF flag. The total conversion time in Bus Cycles for a conversion is: SC Bus Cycles = ((PRS+1)*2) * (28+1) + 2 CC Bus Cycles = ((PRS+1)*2) * (28) 3 R istherealportionoftheimpedanceofthenetworkdrivingtheanaloginputpin.Valuesgreaterthanthisamountmaynotfully AS charge the input circuitry of the ATD resulting in accuracy error. 4 AnaloginputmustbebetweenV andV forvalidconversion.ValuesgreaterthanV willconvertto$3FFlessthefull REFL REFH REFH scale error (E ). FS 5 The resolution is the ideal step size or 1LSB = (V –V )/1024 REFH REFL 6 Differentialnon-linearityisthedifferencebetweenthecurrentcodewidthandtheidealcodewidth(1LSB).Thecurrentcodewidth is the difference in the transition voltages to and from the current code. 7 Integralnon-linearityisthedifferencebetweenthetransitionvoltagetothecurrentcodeandtheadjustedidealtransitionvoltage for the current code. The adjusted ideal transition voltage is (Current Code–1/2)*(1/((V +E )–(V +E ))). REFH FS REFL ZS 8 Zero-scale error is the difference between the transition to the first valid code and the ideal transition to that code. The Ideal transition voltage to a given code is (Code–1/2)*(1/(V –V )). REFH REFL 9 Full-scale error is the difference between the transition to the last valid code and the ideal transition to that code. The ideal transition voltage to a given code is (Code–1/2)*(1/(V –V )). REFH REFL 10Input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pin. Reducing the impedance of the network reduces this error. 11Total unadjusted error is the difference between the transition voltage to the current code and the ideal straight-line transfer function.Thismeasureoferrorincludesinherentquantizationerror(1/2LSB)andcircuiterror(differential,integral,zero-scale,and full-scale) error. The specified value of E assumes zero E (no leakage or zero real source impedance). T IL MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 273

Electrical Characteristics A.9 Internal Clock Generation Module Characteristics ICG EXTAL XTAL RF RS Crystal or Resonator (See Note) C 1 C 2 NOTE: Use fundamental mode crystal or ceramic resonator only. TableA-10. ICG DC Electrical Specifications (Temperature Range = –40 to 125°C Ambient) Characteristic Symbol Min Typ1 Max Unit Load capacitors C 1 See Note2 C 2 Feedback resistor Low range (32k to 100 kHz) R 10 MΩ F High range (1M – 16 MHz) 1 MΩ Series resistor Low range Low Gain (HGO = 0) — 0 — High Gain (HGO = 1) — 100 — High range R kΩ Low Gain (HGO = 0) S — 0 — High Gain (HGO = 1) ≥ 8 MHz — 0 — 4 MHz — 10 — 1MHz — 20 — 1 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. 2 See crystal or resonator manufacturer’s recommendation. MC9S08GT16A/GT8A Data Sheet, Rev. 1 274 Freescale Semiconductor

Electrical Characteristics A.9.1 ICG Frequency Specifications TableA-11. ICG Frequency Specifications (V = V (min) to V (max), Temperature Range = –40 to 125°C Ambient) DDA DDA DDA Characteristic Symbol Min Typical Max Unit Oscillator crystal or resonator (REFS = 1) (Fundamental mode crystal or ceramic resonator) Low range flo 32 — 100 kHz High range High Gain, FBE (HGO=1,CLKS = 10) fhi_byp 1 — 16 MHz High Gain, FEE (HGO=1,CLKS = 11) fhi_eng 2 — 10 MHz Low Power, FBE (HGO=0, CLKS=10) flp_byp 1 — 8 MHz Low Power, FEE (HGO=0, CLKS=11) flp_eng 2 — 8 MHz Input clock frequency (CLKS=11, REFS=0) Low range flo 32 — 100 kHz High range fhi_eng 2 — 10 MHz Input clock frequency (CLKS=10, REFS=0) fExtal 0 — 40 MHz Internal reference frequency (untrimmed) fICGIRCLK 182.25 243 303.75 kHz Duty cycle of input clock4 (REFS=0) tdc 40 — 60 % Output clock ICGOUT frequency CLKS=10, REFS=0 f (max) All other cases fICGOUT fExtal(min) fExtal MHz f (min) ICGDCLKmax lo (max) Minimum DCO clock (ICGDCLK) frequency fICGDCLKmin 8 — MHz Maximum DCO clock (ICGDCLK) frequency fICGDCLKmax — 40 MHz Self-clock mode (ICGOUT) frequency1 fSelf fICGDCLKmin fICGDCLKmax MHz Self-clock mode reset (ICGOUT) frequency fSelf_reset 5.5 8 10.5 MHz Loss of reference frequency2 Low range fLOR 5 25 kHz High range 50 500 Loss of DCO frequency3 fLOD 0.5 1.5 MHz Crystalstart-uptime4,5 Low range t CSTL — 430 — High range ms t — 4 — CSTH FLL lock time4, 6 Low range tLockl — 5 ms High range t — 5 Lockh FLL frequency unlock range nUnlock –4*N 4*N counts FLL frequency lock range nLock –2*N 2*N counts ICGOUT period jitter,4, 7measured at f Max ICGOUT C Long term jitter (averaged over 2 ms interval) Jitter — 0.2 % fICG Internal oscillator deviation from trimmed frequency8 V = 1.8 – 3.6 V, (constant temperature) — ±0.5 ±2 VDD = 3.0 V±10%, –40° C to 125° C ACCint — ±0.5 ±2 % DD Oscillator Amplitude (peak-to-peak) HGO = 0 Voscamp — 1 — V HGO = 1 — V — DD MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 275

Electrical Characteristics 1 Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop. 2 Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it is not in the desired range. 3 Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode (if an external reference exists) if it is not in the desired range. 4 This parameter is characterized before qualification rather than 100% tested. 5 Proper PC board layout procedures must be followed to achieve specifications. 6 ThisspecificationappliestotheperiodoftimerequiredfortheFLLtolockafterenteringFLLengagedinternalorexternal modes. If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7 Jitteristheaveragedeviationfromtheprogrammedfrequencymeasuredoverthespecifiedintervalatmaximumf . ICGOUT Measurementsaremadewiththedevicepoweredbyfilteredsuppliesandclockedbyastableexternalclocksignal.Noise injected into the FLL circuitry via V and V and variation in crystal oscillator frequency increase the C DDA SSA Jitter percentage for a given interval. 8 SeeFigureA-10 0.1 80 100 120 –60 –40 –20 0 20 40 60 –0.1 %) T ( N –0.2 E C R E P –0.3 –0.4 2 V –0.5 3 V –0.6 TEMPERATURE (°C) FigureA-10. Internal Oscillator Deviation from Trimmed Frequency A.10 AC Characteristics Thissectiondescribesactimingcharacteristicsforeachperipheralsystem.Fordetailedinformationabout how clocks for the bus are generated, see Chapter9, “Internal Clock Generator (S08ICGV4).” MC9S08GT16A/GT8A Data Sheet, Rev. 1 276 Freescale Semiconductor

Electrical Characteristics A.10.1 Control Timing TableA-12. Control Timing Parameter Symbol Min Typical Max Unit Bus frequency (t = 1/f ) cyc Bus VDD≥2.1 V fBus 0 — 20 MHz V < 2.1 V 0 8 DD Real-time interrupt internal oscillator period tRTI 750 1150 1550 µs 1.5 x External reset pulse width1 textrst f — ns Self_reset 34 x Reset low drive2 trstdrv f — ns Self_reset Active background debug mode latch setup time tMSSU 25 — ns Active background debug mode latch hold time tMSH 25 — ns IRQ pulse width3 tILIH 1.5 x tcyc — ns Port rise and fall time (load = 50 pF)4 Slew rate control disabled tRise, tFall — 3 ns Slew rate control enabled — 30 1 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 2 Whenanyresetisinitiated,internalcircuitrydrivestheresetpinlowforabout34cyclesoff andthensamplesthelevel Self_reset on the reset pin about 38cycles later to distinguish external reset requests from internal requests. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V and 80% V levels. Temperature range –40°C to 125°C. DD DD 1600 1400 1200 1000 Period (µs) = +3 Sigma 800 = Mean = –3 Sigma 600 400 200 0 –40 –20 0 20 40 60 80 100 120 140 Temperature (°C) FigureA-11. Typical RTI Clock Period vs. Temperature MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 277

Electrical Characteristics t extrst RESET PIN FigureA-12. Reset Timing BKGD/MS RESET t MSH t MSSU FigureA-13. Active Background Debug Mode Latch Timing t ILIH IRQ FigureA-14. IRQ Timing A.10.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. TableA-13. TPM Input Timing Function Symbol Min Max Unit External clock frequency fTPMext dc fBus/4 MHz External clock period tTPMext 4 — tcyc External clock high time tclkh 1.5 — tcyc External clock low time tclkl 1.5 — tcyc Input capture pulse width tICPW 1.5 — tcyc MC9S08GT16A/GT8A Data Sheet, Rev. 1 278 Freescale Semiconductor

Electrical Characteristics t Text t clkh TPMxCHn t clkl FigureA-15. Timer External Clock t ICPW TPMxCHn TPMxCHn t ICPW FigureA-16. Timer Input Capture Pulse MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 279

Electrical Characteristics A.10.3 SPI Timing TableA-14 and FigureA-17 through FigureA-20 describe the timing requirements for the SPI system. TableA-14. SPI Timing No. Function Symbol Min Max Unit Operating frequency Master f f /2048 f /2 Hz op Bus Bus Slave dc f /4 Bus SCK period 1 Master t 2 2048 t SCK cyc Slave 4 — t cyc Enable lead time 2 Master t 1/2 — t Lead SCK Slave 1 — t cyc Enable lag time 3 Master t 1/2 — t Lag SCK Slave 1 — t cyc Clock (SCK) high or low time 4 Master t t – 30 1024 t ns WSCK cyc cyc Slave t – 30 — ns cyc Data setup time (inputs) 5 Master t 15 — ns SU Slave 15 — ns Data hold time (inputs) 6 Master t 0 — ns HI Slave 25 — ns 7 Slave access time t — 1 t a cyc 8 Slave MISO disable time t — 1 t dis cyc Data valid (after SCK edge) 9 Master t — 25 ns v Slave — 25 ns Data hold time (outputs) 10 Master t 0 — ns HO Slave 0 — ns Rise time 11 Input t — t – 25 ns RI cyc Output t — 25 ns RO Fall time 12 Input t — t – 25 ns FI cyc Output t — 25 ns FO MC9S08GT16A/GT8A Data Sheet, Rev. 1 280 Freescale Semiconductor

Electrical Characteristics SS1 (OUTPUT) 2 1 11 3 SCK 4 (CPOL = 0) (OUTPUT) 4 12 SCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 9 9 10 MOSI (OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT NOTES: 1.SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. FigureA-17. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 12 11 3 SCK (CPOL = 0) (OUTPUT) 4 4 11 12 SCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MSB IN(2) BIT 6 . . . 1 LSB IN 9 10 MOSI PORT DATA MASTER MSB OUT(2) BIT 6 . . . 1 MASTER LSB OUT PORT DATA (OUTPUT) NOTES: 1.SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. FigureA-18. SPI Master Timing (CPHA = 1) MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 281

Electrical Characteristics SS (INPUT) 1 12 11 3 SCK (CPOL = 0) (INPUT) 2 4 4 11 12 SCK (CPOL = 1) (INPUT) 8 7 9 10 10 MISO SEE (OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE 5 6 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally MSB of character just received FigureA-19. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 12 11 SCK (CPOL = 0) (INPUT) 4 4 11 12 SCK (CPOL = 1) (INPUT) 9 10 8 MISO SEE (OUTPUT) NOTE SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT 7 5 6 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received FigureA-20. SPI Slave Timing (CPHA = 1) MC9S08GT16A/GT8A Data Sheet, Rev. 1 282 Freescale Semiconductor

Electrical Characteristics A.11 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the FLASH memory. ProgramanderaseoperationsdonotrequireanyspecialpowersourcesotherthanthenormalV supply. DD For more detailed information about program/erase operations, seeChapter 4, “Memory.” TableA-15. FLASH Characteristics Characteristic Symbol Min Typical Max Unit Supply voltage for program/erase T≤ 85°C Vprog/erase 1.8 3.6 V T> 85°C 2.1 3.6 V Supply voltage for read operation 0 < fBus < 8 MHz VRead 1.8 3.6 V 0 < f < 20 MHz 2.08 3.6 Bus Internal FCLK frequency1 fFCLK 150 200 kHz Internal FCLK period (1/FCLK) tFcyc 5 6.67 µs Byte program time (random location)(2) tprog 9 tFcyc Byte program time (burst mode)(2) tBurst 4 tFcyc Page erase time2 tPage 4000 tFcyc Mass erase time(2) tMass 20,000 tFcyc Byte program current3 RIDDBP — 4 — mA Page erase current3 RIDDPE — 6 — mA Program/erase endurance4 T to T = –40°C to +125°C 10,000 — cycles L H T = 25°C 100,000 — Data retention5 tD_ret 15 100 — years 1 The frequency of this clock is controlled by a software setting. 2 Thesevaluesarehardwarestatemachinecontrolled.Usercodedoesnotneedtocountcycles.Thisinformation supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run I . These values were measured at room DD temperatures with V = 3.0 V, bus frequency = 4.0 MHz. DD 4 Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D,Typical Endurance for Nonvolatile Memory. 5 Typicaldataretentionvaluesarebasedonintrinsiccapabilityofthetechnologymeasuredathightemperature andde-ratedto25°CusingtheArrheniusequation.ForadditionalinformationonhowFreescaleSemiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D,Typical Data Retention for Nonvolatile Memory. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 283

Electrical Characteristics MC9S08GT16A/GT8A Data Sheet, Rev. 1 284 Freescale Semiconductor

Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering information for MC9S08GT16A and MC9S08GT8A devices. Table15-7. Devices in the MC9S08GT16A/GT8A Series Device FLASH RAM Packages1 MC9S08GT16A 16K 2K 48 QFN 44 QFP 42 SDIP 32 QFN MC9S08GT8A 8K 1K 1 SeeTableB-1 for package information. B.1.1 Device Numbering Scheme MC9 S08GT16A C XX E Status RoHS compliance indicator (E = yes) (MC = Fully Qualified) Package designator (seeTableB-1) Memory (9 = FLASH-based) Temperature range(C = –40°C to +85°C) (M = –40°C to +125°C) Core Family/memory size B.2 Mechanical Drawings The following pages are mechanical specifications for MC9S08GT16A/GT8A package options. See TableB-1 for the document number for each package type. TableB-1. Package Information PinCount Type Designator Document No. 48 QFN Quad flat no-lead FD 98ARH99048A 44 QFP Quad flat package FB 98ASB42839B 42 PSDIP Plastic shrink dual inline package B 98ASB42767B 32 QFN Quad flat no-lead FC 98ARH99035A MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor 285

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