Freescale Semiconductor Document Number: QFN_Addendum Rev. 0, 07/2014 Addendum Addendum for New QFN Package Migration This addendum provides the changes to the 98A case outline numbers for products covered in this book. Case outlines were changed because of the migration from gold wire to copper wire in some packages. See the table below for the old (gold wire) package versus the new (copper wire) package. To view the new drawing, go to Freescale.com and search on the new 98A package number for your device. For more information about QFN package use, see EB806: Electrical Connection Recommendations for the Exposed Pad on QFN and DFN Packages. ©Freescale Semiconductor, Inc., 2014. All rights reserved.

Original (gold wire) Current (copper wire) Part Number Package Description package document number package document number MC68HC908JW32 48 QFN 98ARH99048A 98ASA00466D MC9S08AC16 MC9S908AC60 MC9S08AC128 MC9S08AW60 MC9S08GB60A MC9S08GT16A MC9S08JM16 MC9S08JM60 MC9S08LL16 MC9S08QE128 MC9S08QE32 MC9S08RG60 MCF51CN128 MC9RS08LA8 48 QFN 98ARL10606D 98ASA00466D MC9S08GT16A 32 QFN 98ARH99035A 98ASA00473D MC9S908QE32 32 QFN 98ARE10566D 98ASA00473D MC9S908QE8 32 QFN 98ASA00071D 98ASA00736D MC9S08JS16 24 QFN 98ARL10608D 98ASA00734D MC9S08QB8 MC9S08QG8 24 QFN 98ARL10605D 98ASA00474D MC9S08SH8 24 QFN 98ARE10714D 98ASA00474D MC9RS08KB12 24 QFN 98ASA00087D 98ASA00602D MC9S08QG8 16 QFN 98ARE10614D 98ASA00671D MC9RS08KB12 8 DFN 98ARL10557D 98ASA00672D MC9S08QG8 MC9RS08KA2 6 DFN 98ARL10602D 98ASA00735D Addendum for New QFN Package Migration, Rev. 0 2 Freescale Semiconductor

MC9S08GB60A MC9S08GB32A MC9S08GT60A MC9S08GT32A Data Sheet HCS08 Microcontrollers MC9S08GB60A Rev. 2 07/2008 freescale.com

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MC9S08GB60A Data Sheet Covers: MC9S08GB60A MC9S08GB32A MC9S08GT60A MC9S08GT32A MC9S08GB60A Rev. 2 07/2008

Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. Revision Revision Description of Changes Number Date 1.00 07/14/2005 Initial public release. Added a footnote to RTI of Table 3.2; Added RTI description to Section 3.5.6; 1.01 09/04/2007 Added a sentence "If active BDM mode is enabled in stop3, the internal RTI clock is not available." to the Section 5.7 Real Time Interrupt. Changed the Maximun Low Power of FBE and FEE in TableA-9 to 10 MHz. 1.02 02/25/2008 Changed the Title of Table13-2 from “IIC1A Register Field Descriptions” to “IIC1F Register Field Descriptions” Added 42-pin SDIP information. Changed “However, when HGO=0, the maximum frequency is 8 MHz in FEE 2 7/30/2008 and FBE modes.” to “However, when HGO=0, the maximum frequency is 10 MHz in FEE and FBE modes.” in Appendix B5. Updated the “How to reach us” at backpage. This product incorporates SuperFlash® technology licensed from SST. Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005-2008. All rights reserved. MC9S08GB60A Data Sheet, Rev. 2 6 Freescale Semiconductor

List of Chapters Chapter Number Title Page Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Chapter 2 Pins and Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Chapter 3 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Chapter 4 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Chapter 5 Resets, Interrupts, and System Configuration . . . . . . . . . . . . . . .65 Chapter 6 Parallel Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Chapter 7 Internal Clock Generator (S08ICGV2) . . . . . . . . . . . . . . . . . . . . .103 Chapter 8 Central Processor Unit (S08CPUV2) . . . . . . . . . . . . . . . . . . . . . .129 Chapter 9 Keyboard Interrupt (S08KBIV1) . . . . . . . . . . . . . . . . . . . . . . . . . .149 Chapter 10 Timer/PWM (S08TPMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Chapter 11 Serial Communications Interface (S08SCIV1). . . . . . . . . . . . . .171 Chapter 12 Serial Peripheral Interface (S08SPIV3). . . . . . . . . . . . . . . . . . . .189 Chapter 13 Inter-Integrated Circuit (S08IICV1) . . . . . . . . . . . . . . . . . . . . . . .205 Chapter 14 Analog-to-Digital Converter (S08ATDV3) . . . . . . . . . . . . . . . . .223 Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 Appendix B EB652: Migrating from the GB60 Series to the GB60A Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 Appendix C Ordering Information and Mechanical Drawings. . . . . . . . . .287 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 3

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Contents Section Number Title Page Chapter 1 Device Overview 1.1 Overview .........................................................................................................................................17 1.2 Features ...........................................................................................................................................17 1.2.1 Standard Features of the HCS08 Family .........................................................................17 1.2.2 Features of MC9S08GBxxA/GTxxA Series of MCUs ....................................................18 1.2.3 Devices in the MC9S08GBxxA/GTxxA Series ...............................................................19 1.3 MCU Block Diagrams .....................................................................................................................19 1.4 System Clock Distribution ..............................................................................................................21 Chapter 2 Pins and Connections 2.1 Introduction .....................................................................................................................................23 2.2 Device Pin Assignment ...................................................................................................................24 2.3 Recommended System Connections ...............................................................................................27 2.3.1 Power ...............................................................................................................................29 2.3.2 Oscillator ..........................................................................................................................29 2.3.3 Reset ................................................................................................................................29 2.3.4 Background / Mode Select (PTG0/BKGD/MS) ..............................................................30 2.3.5 General-Purpose I/O and Peripheral Ports .......................................................................30 2.3.6 Signal Properties Summary .............................................................................................32 Chapter 3 Modes of Operation 3.1 Introduction .....................................................................................................................................35 3.2 Features ...........................................................................................................................................35 3.3 Run Mode ........................................................................................................................................35 3.4 Active Background Mode ...............................................................................................................35 3.5 Wait Mode .......................................................................................................................................36 3.6 Stop Modes ......................................................................................................................................36 3.6.1 Stop1 Mode ......................................................................................................................37 3.6.2 Stop2 Mode ......................................................................................................................37 3.6.3 Stop3 Mode ......................................................................................................................38 3.6.4 Active BDM Enabled in Stop Mode ................................................................................38 3.6.5 LVD Enabled in Stop Mode .............................................................................................39 3.6.6 On-Chip Peripheral Modules in Stop Modes ...................................................................39 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 7

Section Number Title Page Chapter 4 Memory 4.1 MC9S08GBxxA/GTxxA Memory Map ..........................................................................................43 4.1.1 Reset and Interrupt Vector Assignments ..........................................................................43 4.2 Register Addresses and Bit Assignments ........................................................................................45 4.3 RAM ................................................................................................................................................50 4.4 Flash ................................................................................................................................................50 4.4.1 Features ............................................................................................................................51 4.4.2 Program and Erase Times ................................................................................................51 4.4.3 Program and Erase Command Execution ........................................................................52 4.4.4 Burst Program Execution .................................................................................................53 4.4.5 Access Errors ...................................................................................................................55 4.4.6 Flash Block Protection .....................................................................................................55 4.4.7 Vector Redirection ...........................................................................................................56 4.5 Security ............................................................................................................................................56 4.6 Flash Registers and Control Bits .....................................................................................................57 4.6.1 Flash Clock Divider Register (FCDIV) ...........................................................................57 4.6.2 Flash Options Register (FOPT and NVOPT) ...................................................................59 4.6.3 Flash Configuration Register (FCNFG) ..........................................................................60 4.6.4 Flash Protection Register (FPROT and NVPROT) .........................................................60 4.6.5 Flash Status Register (FSTAT) ........................................................................................62 4.6.6 Flash Command Register (FCMD) ..................................................................................63 Chapter 5 Resets, Interrupts, and System Configuration 5.1 Introduction .....................................................................................................................................65 5.2 Features ...........................................................................................................................................65 5.3 MCU Reset ......................................................................................................................................65 5.4 Computer Operating Properly (COP) Watchdog .............................................................................66 5.5 Interrupts .........................................................................................................................................66 5.5.1 Interrupt Stack Frame ......................................................................................................67 5.5.2 External Interrupt Request (IRQ) Pin ..............................................................................68 5.5.2.1 Pin Configuration Options ..............................................................................68 5.5.2.2 Edge and Level Sensitivity .............................................................................69 5.5.3 Interrupt Vectors, Sources, and Local Masks ..................................................................69 5.6 Low-Voltage Detect (LVD) System ................................................................................................71 5.6.1 Power-On Reset Operation ..............................................................................................71 5.6.2 LVD Reset Operation .......................................................................................................71 5.6.3 LVD Interrupt Operation .................................................................................................71 5.6.4 Low-Voltage Warning (LVW) .........................................................................................71 5.7 Real-Time Interrupt (RTI) ...............................................................................................................71 5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................72 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ...........................................73 MC9S08GB60A Data Sheet, Rev. 2 8 Freescale Semiconductor

Section Number Title Page 5.8.2 System Reset Status Register (SRS) ................................................................................74 5.8.3 System Background Debug Force Reset Register (SBDFR) ...........................................75 5.8.4 System Options Register (SOPT) ....................................................................................76 5.8.5 System Device Identification Register (SDIDH, SDIDL) ...............................................77 5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC) ...............................78 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ..........................79 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ..........................80 Chapter 6 Parallel Input/Output 6.1 Introduction .....................................................................................................................................81 6.2 Features ...........................................................................................................................................83 6.3 Pin Descriptions ..............................................................................................................................83 6.3.1 Port A and Keyboard Interrupts .......................................................................................83 6.3.2 Port B and Analog to Digital Converter Inputs ...............................................................84 6.3.3 Port C and SCI2, IIC, and High-Current Drivers ............................................................84 6.3.4 Port D, TPM1 and TPM2 ................................................................................................85 6.3.5 Port E, SCI1, and SPI ......................................................................................................85 6.3.6 Port F and High-Current Drivers .....................................................................................86 6.3.7 Port G, BKGD/MS, and Oscillator ..................................................................................86 6.4 Parallel I/O Controls ........................................................................................................................87 6.4.1 Data Direction Control ....................................................................................................87 6.4.2 Internal Pullup Control ....................................................................................................87 6.4.3 Slew Rate Control ............................................................................................................87 6.5 Stop Modes ......................................................................................................................................88 6.6 Parallel I/O Registers and Control Bits ...........................................................................................88 6.6.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD) ................................................88 6.6.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) ................................................91 6.6.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) ................................................93 6.6.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) ...............................................95 6.6.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) .................................................97 6.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD) ..................................................99 6.6.7 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) .............................................100 Chapter 7 Internal Clock Generator (S08ICGV2) 7.1 Introduction ...................................................................................................................................105 7.1.1 Features ..........................................................................................................................106 7.1.2 Modes of Operation .......................................................................................................107 7.2 Oscillator Pins ...............................................................................................................................107 7.2.1 EXTAL— External Reference Clock / Oscillator Input ................................................107 7.2.2 XTAL— Oscillator Output ............................................................................................107 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 9

Section Number Title Page 7.2.3 External Clock Connections ..........................................................................................108 7.2.4 External Crystal/Resonator Connections .......................................................................108 7.3 Functional Description ..................................................................................................................109 7.3.1 Off Mode (Off) ..............................................................................................................109 7.3.1.1 BDM Active .................................................................................................109 7.3.1.2 OSCSTEN Bit Set .........................................................................................109 7.3.1.3 Stop/Off Mode Recovery ..............................................................................109 7.3.2 Self-Clocked Mode (SCM) ............................................................................................109 7.3.3 FLL Engaged, Internal Clock (FEI) Mode ....................................................................111 7.3.3.1 FLL Engaged Internal Unlocked ..................................................................111 7.3.3.2 FLL Engaged Internal Locked ......................................................................111 7.3.4 FLL Bypassed, External Clock (FBE) Mode ................................................................111 7.3.5 FLL Engaged, External Clock (FEE) Mode ..................................................................111 7.3.5.1 FLL Engaged External Unlocked .................................................................112 7.3.5.2 FLL Engaged External Locked .....................................................................112 7.3.6 FLL Lock and Loss-of-Lock Detection .........................................................................112 7.3.7 FLL Loss-of-Clock Detection ........................................................................................113 7.3.8 Clock Mode Requirements ............................................................................................114 7.3.9 Fixed Frequency Clock ..................................................................................................115 7.3.10 High Gain Oscillator ......................................................................................................115 7.4 Initialization/Application Information ..........................................................................................115 7.4.1 Introduction ....................................................................................................................115 7.4.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz .........................118 7.4.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz .............................119 7.4.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency .....................121 7.4.5 Example #4: Internal Clock Generator Trim .................................................................122 7.5 ICG Registers and Control Bits .....................................................................................................123 7.5.1 ICG Control Register 1 (ICGC1) ...................................................................................124 7.5.2 ICG Control Register 2 (ICGC2) ...................................................................................125 7.5.3 ICG Status Register 1 (ICGS1) ........................................................................126 7.5.4 ICG Status Register 2 (ICGS2) ......................................................................................127 7.5.5 ICG Filter Registers (ICGFLTU, ICGFLTL) .................................................................127 7.5.6 ICG Trim Register (ICGTRM) ......................................................................................128 Chapter 8 Central Processor Unit (S08CPUV2) 8.1 Introduction ...................................................................................................................................129 8.1.1 Features ..........................................................................................................................129 8.2 Programmer’s Model and CPU Registers .....................................................................................130 8.2.1 Accumulator (A) ............................................................................................................130 8.2.2 Index Register (H:X) .....................................................................................................130 8.2.3 Stack Pointer (SP) ..........................................................................................................131 8.2.4 Program Counter (PC) ...................................................................................................131 8.2.5 Condition Code Register (CCR) ....................................................................................131 MC9S08GB60A Data Sheet, Rev. 2 10 Freescale Semiconductor

Section Number Title Page 8.3 Addressing Modes .........................................................................................................................133 8.3.1 Inherent Addressing Mode (INH) ..................................................................................133 8.3.2 Relative Addressing Mode (REL) .................................................................................133 8.3.3 Immediate Addressing Mode (IMM) .............................................................................133 8.3.4 Direct Addressing Mode (DIR) .....................................................................................133 8.3.5 Extended Addressing Mode (EXT) ...............................................................................134 8.3.6 Indexed Addressing Mode .............................................................................................134 8.3.6.1 Indexed, No Offset (IX) ................................................................................134 8.3.6.2 Indexed, No Offset with Post Increment (IX+) ............................................134 8.3.6.3 Indexed, 8-Bit Offset (IX1) ...........................................................................134 8.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) .......................................134 8.3.6.5 Indexed, 16-Bit Offset (IX2) .........................................................................134 8.3.6.6 SP-Relative, 8-Bit Offset (SP1) ....................................................................134 8.3.6.7 SP-Relative, 16-Bit Offset (SP2) ..................................................................135 8.4 Special Operations .........................................................................................................................135 8.4.1 Reset Sequence ..............................................................................................................135 8.4.2 Interrupt Sequence .........................................................................................................135 8.4.3 Wait Mode Operation ....................................................................................................136 8.4.4 Stop Mode Operation .....................................................................................................136 8.4.5 BGND Instruction ..........................................................................................................137 8.5 HCS08 Instruction Set Summary ..................................................................................................138 Chapter 9 Keyboard Interrupt (S08KBIV1) 9.1 Introduction ...................................................................................................................................149 9.1.1 Port A and Keyboard Interrupt Pins ..............................................................................149 9.2 Features .........................................................................................................................................149 9.2.1 KBI Block Diagram .......................................................................................................151 9.3 Register Definition ........................................................................................................................151 9.3.1 KBI Status and Control Register (KBI1SC) ..................................................................152 9.3.2 KBI Pin Enable Register (KBI1PE) ..............................................................................153 9.4 Functional Description ..................................................................................................................153 9.4.1 Pin Enables ....................................................................................................................153 9.4.2 Edge and Level Sensitivity ............................................................................................153 9.4.3 KBI Interrupt Controls ...................................................................................................154 Chapter 10 Timer/PWM (S08TPMV1) 10.1 Introduction ...................................................................................................................................155 10.2 Features .........................................................................................................................................155 10.3 TPM Block Diagram .....................................................................................................................157 10.4 Pin Descriptions ............................................................................................................................158 10.4.1 External TPM Clock Sources ........................................................................................158 10.4.2 TPMxCHn — TPMx Channel n I/O Pins ......................................................................158 10.5 Functional Description ..................................................................................................................158 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 11

Section Number Title Page 10.5.1 Counter ..........................................................................................................................159 10.5.2 Channel Mode Selection ................................................................................................160 10.5.2.1 Input Capture Mode ......................................................................................160 10.5.2.2 Output Compare Mode .................................................................................160 10.5.2.3 Edge-Aligned PWM Mode ...........................................................................160 10.5.3 Center-Aligned PWM Mode ..........................................................................................161 10.6 TPM Interrupts ..............................................................................................................................163 10.6.1 Clearing Timer Interrupt Flags ......................................................................................163 10.6.2 Timer Overflow Interrupt Description ...........................................................................163 10.6.3 Channel Event Interrupt Description .............................................................................163 10.6.4 PWM End-of-Duty-Cycle Events ..................................................................................164 10.7 TPM Registers and Control Bits ...................................................................................................164 10.7.1 Timer x Status and Control Register (TPMxSC) ...........................................................165 10.7.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) ..............................................166 10.7.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) ..............................167 10.7.4 Timer x Channel n Status and Control Register (TPMxCnSC) .....................................168 10.7.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) .....................................169 Chapter 11 Serial Communications Interface (S08SCIV1) 11.1 Introduction ...................................................................................................................................171 11.1.1 Features ..........................................................................................................................173 11.1.2 Modes of Operation .......................................................................................................173 11.1.3 Block Diagram ...............................................................................................................174 11.2 Register Definition ........................................................................................................................176 11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) .........................................................176 11.2.2 SCI Control Register 1 (SCIxC1) ..................................................................................177 11.2.3 SCI Control Register 2 (SCIxC2) ..................................................................................178 11.2.4 SCI Status Register 1 (SCIxS1) .....................................................................................179 11.2.5 SCI Status Register 2 (SCIxS2) .....................................................................................181 11.2.6 SCI Control Register 3 (SCIxC3) ..................................................................................181 11.2.7 SCI Data Register (SCIxD) ...........................................................................................182 11.3 Functional Description ..................................................................................................................183 11.3.1 Baud Rate Generation ....................................................................................................183 11.3.2 Transmitter Functional Description ...............................................................................183 11.3.2.1 Send Break and Queued Idle ........................................................................184 11.3.3 Receiver Functional Description ...................................................................................184 11.3.3.1 Data Sampling Technique .............................................................................185 11.3.3.2 Receiver Wakeup Operation .........................................................................185 11.3.4 Interrupts and Status Flags .............................................................................................186 11.3.5 Additional SCI Functions ..............................................................................................187 11.3.5.1 8- and 9-Bit Data Modes ...............................................................................187 11.3.5.2 Stop Mode Operation ....................................................................................187 11.3.5.3 Loop Mode ....................................................................................................188 MC9S08GB60A Data Sheet, Rev. 2 12 Freescale Semiconductor

Section Number Title Page 11.3.5.4 Single-Wire Operation ..................................................................................188 Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.1 Introduction ...................................................................................................................................189 12.1.1 Features ..........................................................................................................................191 12.1.2 Block Diagrams .............................................................................................................191 12.1.2.1 SPI System Block Diagram ..........................................................................191 12.1.2.2 SPI Module Block Diagram ..........................................................................192 12.1.3 SPI Baud Rate Generation .............................................................................................193 12.2 External Signal Description ..........................................................................................................194 12.2.1 SPSCK — SPI Serial Clock ..........................................................................................194 12.2.2 MOSI — Master Data Out, Slave Data In .....................................................................194 12.2.3 MISO — Master Data In, Slave Data Out .....................................................................194 12.2.4 SS — Slave Select .........................................................................................................194 12.3 Modes of Operation .......................................................................................................................195 12.3.1 SPI in Stop Modes .........................................................................................................195 12.4 Register Definition ........................................................................................................................195 12.4.1 SPI Control Register 1 (SPI1C1) ...................................................................................195 12.4.2 SPI Control Register 2 (SPI1C2) ...................................................................................196 12.4.3 SPI Baud Rate Register (SPI1BR) .................................................................................197 12.4.4 SPI Status Register (SPI1S) ...........................................................................................198 12.4.5 SPI Data Register (SPI1D) ............................................................................................199 12.5 Functional Description ..................................................................................................................200 12.5.1 SPI Clock Formats .........................................................................................................200 12.5.2 SPI Interrupts .................................................................................................................203 12.5.3 Mode Fault Detection ....................................................................................................203 Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.1 Introduction ...................................................................................................................................205 13.1.1 Features ..........................................................................................................................207 13.1.2 Modes of Operation .......................................................................................................207 13.1.3 Block Diagram ...............................................................................................................208 13.2 External Signal Description ..........................................................................................................208 13.2.1 SCL — Serial Clock Line ..............................................................................................208 13.2.2 SDA — Serial Data Line ...............................................................................................208 13.3 Register Definition ........................................................................................................................208 13.3.1 IIC Address Register (IIC1A) ........................................................................................209 13.3.2 IIC Frequency Divider Register (IIC1F) .......................................................................209 13.3.3 IIC Control Register (IIC1C) .........................................................................................212 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 13

Section Number Title Page 13.3.4 IIC Status Register (IIC1S) ............................................................................................213 13.3.5 IIC Data I/O Register (IIC1D) .......................................................................................214 13.4 Functional Description ..................................................................................................................215 13.4.1 IIC Protocol ...................................................................................................................215 13.4.1.1 START Signal ...............................................................................................216 13.4.1.2 Slave Address Transmission .........................................................................216 13.4.1.3 Data Transfer .................................................................................................216 13.4.1.4 STOP Signal ..................................................................................................217 13.4.1.5 Repeated START Signal ...............................................................................217 13.4.1.6 Arbitration Procedure ...................................................................................217 13.4.1.7 Clock Synchronization ..................................................................................217 13.4.1.8 Handshaking .................................................................................................218 13.4.1.9 Clock Stretching ............................................................................................218 13.5 Resets ............................................................................................................................................218 13.6 Interrupts .......................................................................................................................................218 13.6.1 Byte Transfer Interrupt ..................................................................................................219 13.6.2 Address Detect Interrupt ................................................................................................219 13.6.3 Arbitration Lost Interrupt ..............................................................................................219 13.7 Initialization/Application Information ..........................................................................................220 Chapter 14 Analog-to-Digital Converter (S08ATDV3) 14.1 Introduction ...................................................................................................................................225 14.1.1 Features ..........................................................................................................................225 14.1.2 Modes of Operation .......................................................................................................225 14.1.2.1 Stop Mode .....................................................................................................225 14.1.2.2 Power Down Mode .......................................................................................225 14.1.3 Block Diagram ...............................................................................................................225 14.2 Signal Description .........................................................................................................................226 14.2.1 Overview ........................................................................................................................226 14.2.1.1 Channel Input Pins — AD1P7–AD1P0 ........................................................227 14.2.1.2 ATD Reference Pins — V , V REFH REFL .......................................................................227 14.2.1.3 ATD Supply Pins — V , V DDAD SSAD ...........................................................................227 14.3 Functional Description ..................................................................................................................227 14.3.1 Mode Control .................................................................................................................227 14.3.2 Sample and Hold ............................................................................................................228 14.3.3 Analog Input Multiplexer ..............................................................................................230 14.3.4 ATD Module Accuracy Definitions ...............................................................................230 14.4 Resets ............................................................................................................................................233 14.5 Interrupts .......................................................................................................................................233 14.6 ATD Registers and Control Bits ....................................................................................................233 14.6.1 ATD Control (ATDC) ....................................................................................................234 14.6.2 ATD Status and Control (ATD1SC) ..............................................................................236 14.6.3 ATD Result Data (ATD1RH, ATD1RL) ........................................................................237 MC9S08GB60A Data Sheet, Rev. 2 14 Freescale Semiconductor

Section Number Title Page 14.6.4 ATD Pin Enable (ATD1PE) ...........................................................................................238 Chapter 15 Development Support 15.1 Introduction ...................................................................................................................................239 15.1.1 Features ..........................................................................................................................240 15.2 Background Debug Controller (BDC) ..........................................................................................240 15.2.1 BKGD Pin Description ..................................................................................................241 15.2.2 Communication Details .................................................................................................242 15.2.3 BDC Commands ............................................................................................................246 15.2.4 BDC Hardware Breakpoint ............................................................................................248 15.3 On-Chip Debug System (DBG) ....................................................................................................249 15.3.1 Comparators A and B ....................................................................................................249 15.3.2 Bus Capture Information and FIFO Operation ..............................................................249 15.3.3 Change-of-Flow Information .........................................................................................250 15.3.4 Tag vs. Force Breakpoints and Triggers ........................................................................250 15.3.5 Trigger Modes ................................................................................................................251 15.3.6 Hardware Breakpoints ...................................................................................................253 15.4 Register Definition ........................................................................................................................253 15.4.1 BDC Registers and Control Bits ....................................................................................253 15.4.1.1 BDC Status and Control Register (BDCSCR) ..............................................254 15.4.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................255 15.4.2 System Background Debug Force Reset Register (SBDFR) .........................................255 15.4.3 DBG Registers and Control Bits ...................................................................................256 15.4.3.1 Debug Comparator A High Register (DBGCAH) ........................................256 15.4.3.2 Debug Comparator A Low Register (DBGCAL) .........................................256 15.4.3.3 Debug Comparator B High Register (DBGCBH) ........................................256 15.4.3.4 Debug Comparator B Low Register (DBGCBL) .........................................256 15.4.3.5 Debug FIFO High Register (DBGFH) ..........................................................257 15.4.3.6 Debug FIFO Low Register (DBGFL) ...........................................................257 15.4.3.7 Debug Control Register (DBGC) .................................................................258 15.4.3.8 Debug Trigger Register (DBGT) ..................................................................259 15.4.3.9 Debug Status Register (DBGS) ....................................................................260 Appendix A Electrical Characteristics A.1 Introduction ...................................................................................................................................261 A.2 Absolute Maximum Ratings ..........................................................................................................261 A.3 Thermal Characteristics .................................................................................................................262 A.4 Electrostatic Discharge (ESD) Protection Characteristics ............................................................263 A.5 DC Characteristics .........................................................................................................................263 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 15

Section Number Title Page A.6 Supply Current Characteristics ......................................................................................................267 A.7 ATD Characteristics ......................................................................................................................271 A.8 Internal Clock Generation Module Characteristics .......................................................................273 A.8.1 ICG Frequency Specifications ........................................................................................274 A.9 AC Characteristics .........................................................................................................................275 A.9.1 Control Timing ...............................................................................................................276 A.9.2 Timer/PWM (TPM) Module Timing ..............................................................................277 A.9.3 SPI Timing ......................................................................................................................278 A.10 Flash Specifications .......................................................................................................................281 Appendix B EB652: Migrating from the GB60 Series to the GB60A Series B.1 Overview .......................................................................................................................................283 B.2 Flash Programming Voltage ..........................................................................................................283 B.3 Flash Block Protection: 60K Devices Only ..................................................................................283 B.4 Internal Clock Generator: High Gain Oscillator Option ...............................................................283 B.5 Internal Clock Generator: Low-Power Oscillator Maximum Frequency ......................................284 B.6 Internal Clock Generator: Loss-of-Clock Disable Option ............................................................284 B.7 System Device Identification Register ..........................................................................................285 Appendix C Ordering Information and Mechanical Drawings C.1 Ordering Information ....................................................................................................................287 C.2 Mechanical Drawings ....................................................................................................................288 MC9S08GB60A Data Sheet, Rev. 2 16 Freescale Semiconductor

Chapter 1 Device Overview 1.1 Overview The MC9S08GBxxA/GTxxA are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.2 Features Features have been organized to reflect: • Standard features of the HCS08 Family • Features of the MC9S08GBxxA/GTxxA MCU 1.2.1 Standard Features of the HCS08 Family • 40-MHz HCS08 CPU (central processor unit) • HC08 instruction set with added BGND instruction • Background debugging system (see also Chapter 15, “Development Support”) • Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) • Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints. • Support for up to 32 interrupt/reset sources • Power-saving modes: wait plus three stops • System protection features: — Optional computer operating properly (COP) reset — Low-voltage detection with reset or interrupt — Illegal opcode detection with reset — Illegal address detection with reset (some devices don’t have illegal addresses) MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 17

Chapter1 Device Overview 1.2.2 Features of MC9S08GBxxA/GTxxA Series of MCUs • On-chip in-circuit programmable flash memory: — Fully read/write functional across voltage and temperature ranges — Block protection and security options — (see Table 1-1 for device-specific information) • On-chip random-access memory (RAM) (see Table1-1 for device specific information) • 8-channel, 10-bit analog-to-digital converter (ATD) • Two serial communications interface modules (SCI) • Serial peripheral interface module (SPI) • Multiple clock source options: — Internally generated clock with ±0.2% trimming resolution and ±0.5% deviation across voltage — Crystal — Resonator — External clock • Inter-integrated circuit bus module to operate up to 100 kbps (IIC) • One 3-channel and one 5-channel 16-bit timer/pulse width modulator (TPM) modules with selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each timer module may be configured for buffered, centered PWM (CPWM) on all channels (TPMx). • 8-pin keyboard interrupt module (KBI) • 16 high-current pins (limited by package dissipation) • Software selectable pullups on ports when used as input. Selection is on an individual port bit basis. During output mode, pullups are disengaged. • Internal pullup on RESET and IRQ pin to reduce customer system cost • Up to 56 general-purpose input/output (I/O) pins, depending on package selection • 64-pin low-profile quad flat package (LQFP) — MC9S08GBxxA • 48-pin quad flat package, no lead (QFN) — MC9S08GTxxA • 44-pin quad flat package (QFP) — MC9S08GTxxA • 42-pin skinny dual in-line package (SDIP) — MC9S08GTxxA MC9S08GB60A Data Sheet, Rev. 2 18 Freescale Semiconductor

Chapter1 Device Overview 1.2.3 Devices in the MC9S08GBxxA/GTxxA Series Table 1-1 lists the devices available in the MC9S08GBxxA/GTxxA series and summarizes the differences among them. Table1-1. Devices in the MC9S08GBxxA/GTxxA Series Device Flash RAM TPM I/O Packages MC9S08GB60A 60K 4K One 3-channel and one 56 64 LQFP 5-channel, 16-bit timer MC9S08GB32A 32K 2K One 3-channel and one 56 64 LQFP 5-channel, 16-bit timer MC9S08GT60A 60K 4K Two 2-channel, 39 48 QFN1 16-bit timers 36 44 QFP 33 42 SDIP MC9S08GT32A 32K 2K Two 2-channel, 39 48 QFN(1) 16-bit timers 36 44 QFP 33 42 SDIP 1 The 48-pin QFN package has one 3-channel and one 2-channel 16-bit TPM. 1.3 MCU Block Diagrams These block diagrams show the structure of the MC9S08GBxxA/GTxxA MCUs. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 19

Chapter1 Device Overview HCS08 CORE DEBUG MODULE (DBG) A CPU BDC 8 RT 8 PTA7/KBI1P7– 8-BIT KEYBOARD PO PTA0/KBI1P0 INTERRUPT MODULE (KBI1) HCS08 SYSTEM CONTROL B RESET CANOANLVOEGR-TTEOR-D (1IG0-ITBAITL) 8 ORT 8 PTB7/AD1P7– RESETS AND INTERRUPTS (ATD1) P PTB0/AD1P0 MODES OF OPERATION POWER MANAGEMENT PTC7 PTC6 RTI COP PTC5 C IRQ IRQ LVD IIC MODULE SCL1 RT PTC4 (IIC1) O PTC3/SCL1 SDA1 P PTC2/SDA1 SCL1 PTC1/RxD2 SERIAL COMMUNICATIONS SCL1 PTC0/TxD2 INTERFACE MODULE USER FLASH (SCI2) PTD7/TPM2CH4 (Gx60A = 61,268 BYTES) PTD6/TPM2CH3 (Gx32A = 32,768 BYTES) 5-CHANNMEOLD TUILMEER/PWM 5 T D PPTTDD45//TTPPMM22CCHH12 R PTD3/TPM2CH0 (TPM2) O 3 P PTD2/TPM1CH2 USER RAM PTD1/TPM1CH1 3-CHANNEL TIMER/PWM (Gx60A = 4096 BYTES) PTD0/TPM1CH0 MODULE (Gx32A = 2048 BYTES) (TPM1) PTE7 PTE6 SPSCK1 VVDDAD SERIAL PERIPHERAL MOSI1 T E PPTTEE54//SMPOSSCI1K1 VSRSEAFDH INTERF(ASCPEI1 M)ODULE MSSIS1O1 POR PTE3/MISO1 V PTE2/SS1 REFL RxD1 PTE1/RxD1 SERIAL COMMUNICATIONS TxD1 VDD VOLTAGE INTERFACE MODULE PTE0/TxD1 (SCI1) V REGULATOR SS T F 8 R PTF7–PTF0 O P 4 PTG7–PTG4 INTERNAL CLOCK PTG3 GENERATOR EXTAL G PTG2/EXTAL (ICG) XTAL T R PTG1/XTAL BKGD O P PTG0/BKGD/MS LOW-POWER OSCILLATOR Note: Not all pins are bonded out in all packages. See Table2-2 for complete details. Block Diagram Symbol Key: = Not connected in 48-, 44-, and 42-pin packages = Not connected in 44- and 42-pin packages = Not connected in 42-pin packages Figure1-1. MC9S08GBxxA/GTxxA Block Diagram MC9S08GB60A Data Sheet, Rev. 2 20 Freescale Semiconductor

Chapter1 Device Overview Table 1-2 lists the functional versions of the on-chip modules. Table1-2. Block Versions Module Version Analog-to-Digital Converter (ATD) 3 Internal Clock Generator (ICG) 2 Inter-Integrated Circuit (IIC) 1 Keyboard Interrupt (KBI) 1 Serial Communications Interface (SCI) 1 Serial Peripheral Interface (SPI) 3 Timer Pulse-Width Modulator (TPM) 1 Central Processing Unit (CPU) 2 1.4 System Clock Distribution SYSTEM CONTROL TPM1 TPM2 IIC1 SCI1 SCI2 SPI1 LOGIC ICGERCLK RTI FFE ÷2 ICG FIXED FREQ CLOCK (XCLK) ICGOUT BUSCLK ÷2 ICGLCLK* CPU BDC ATD1 RAM FLASH ATD has min and max Flash has frequency frequency requirements. See requirements for program * ICGLCLK is the alternate BDC clock source for the MC9S08GBxxA/GTxxA. Chapter1, “Device Overview” and and erase operation. AppendixA, “Electrical Characteristics. See AppendixA, “Electrical Characteristics. Figure1-2. System Clock Distribution Diagram Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock connection diagram. The ICG supplies the clock sources: • ICGOUT is an output of the ICG module. It is one of the following: — The external crystal oscillator — An external clock source — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop sub-module Control bits inside the ICG determine which source is connected. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 21

Chapter1 Device Overview • FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be the ICGERCLK. Otherwise the fixed-frequency clock will be BUSCLK. • ICGLCLK — Development tools can select this internal self-clocked source (~ 8MHz) to speed up BDC communications in systems where the bus clock is slow. • ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. MC9S08GB60A Data Sheet, Rev. 2 22 Freescale Semiconductor

Chapter 2 Pins and Connections 2.1 Introduction This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 23

Chapter2 Pins and Connections 2.2 Device Pin Assignment S M TAL AL GD/ 1P7 1P6 1P5 1P4 1P3 X T K BI BI BI BI BI G6 G5 G4 G3 G2/E G1/X G0/B SAD DAD F1 F0 A7/K A6/K A5/K A4/K A3/K T T T T T T T S D T T T T T T T P P P P P P P V V P P P P P P P 64 49 63 62 61 60 59 58 57 56 55 54 53 52 51 50 RESET 1 48 PTA2/KBI1P2 PTG7 2 47 PTA1/KBI1P1 PTC0/TxD2 3 46 PTA0/KBI1P0 PTC1/RxD2 4 45 PTF7 PTC2/SDA1 5 44 PTF6 PTC3/SCL1 6 43 PTF5 PTC4 7 42 V REFL PTC5 8 41 V REFH PTC6 9 40 PTB7/AD1P7 PTC7 10 39 PTB6/AD1P6 PTF2 11 38 PTB5/AD1P5 PTF3 12 37 PTB4/AD1P4 PTF4 13 36 PTB3/AD1P3 PTE0/TxD1 14 35 PTB2/AD1P2 PTE1/RxD1 15 34 PTB1/AD1P1 IRQ 16 33 PTB0/AD1P0 18 19 20 21 22 23 24 25 26 27 28 29 30 31 17 32 E2/SS1 MISO1 MOSI1 PSCK1 PTE6 PTE7 VSS VDD M1CH0 M1CH1 M1CH2 M2CH0 M2CH1 M2CH2 M2CH3 M2CH4 T 3/ 4/ S P P P P P P P P P PTE PTE TE5/ D0/T D1/T D2/T D3/T D4/T D5/T D6/T D7/T P T T T T T T T T P P P P P P P P Figure2-1. MC9S08GBxxA in 64-Pin LQFP Package MC9S08GB60A Data Sheet, Rev. 2 24 Freescale Semiconductor

Chapter2 Pins and Connections S M AL L D/ P7 P6 P5 P4 P3 P2 T A G 1 1 1 1 1 1 X T K BI BI BI BI BI BI E X B K K K K K K G3 G2/ G1/ G0/ SAD DAD A7/ A6/ A5/ A4/ A3/ A2/ T T T T S D T T T T T T P P P P V V P P P P P P RESET 1 48 47 46 45 44 43 42 41 40 39 38 3736 PTA1/KBI1P1 PTC0/TxD2 2 35 PTA0/KBI1P0 PTC1/RxD2 3 34 VREFL PTC2/SDA1 4 33 VREFH PTC3/SCL1 5 32 PTB7/AD1P7 PTC4 6 31 PTB6/AD1P6 PTC5 7 30 PTB5/AD1P5 PTC6 8 29 PTB4/AD1P4 PTC7 9 28 PTB3/AD1P3 PTE0/TxD1 10 27 PTB2/AD1P2 PTE1/RxD1 11 26 PTB1/AD1P1 IRQ 12 25 PTB0/AD1P0 13 14 15 16 17 18 19 20 21 22 23 24 1 1 1 1 2 D 0 1 2 0 1 S O K S S D H H H H H E2/S MIS OSI1 PSC VS VS V M1C M1C M1C M2C M2C T 3/ M S P P P P P P PTE PTE4/ PTE5/ TD0/T TD1/T TD2/T TD3/T TD4/T P P P P P Figure2-2. MC9S08GTxxA in 48-Pin QFN Package MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 25

Chapter2 Pins and Connections S M AL L D/ P7 P6 P5 P4 P3 P2 T A G 1 1 1 1 1 1 X T K BI BI BI BI BI BI E X B K K K K K K G2/ G1/ G0/ SAD DAD A7/ A6/ A5/ A4/ A3/ A2/ T T T S D T T T T T T P P P V V P P P P P P 44 34 RESET 1 43 42 41 40 39 38 37 36 35 33 PTA1/KBI1P1 PTC0/TxD2 2 32 PTA0/KBI1P0 PTC1/RxD2 3 31 VREFL PTC2/SDA1 4 30 VREFH PTC3/SCL1 5 29 PTB7/AD1P7 PTC4 6 28 PTB6/AD1P6 PTC5 7 27 PTB5/AD1P5 PTC6 8 26 PTB4/AD1P4 PTE0/TxD1 9 25 PTB3/AD1P3 PTE1/RxD1 10 24 PTB2/AD1P2 IRQ 11 23 PTB1/AD1P1 3 4 5 6 7 8 9 0 1 1 1 1 1 1 1 1 2 2 12 22 1 1 1 1 S D 0 1 0 1 0 E2/SS MISO MOSI PSCK VS VD M1CH M1CH M2CH M2CH AD1P T 3/ 4/ S P P P P 0/ P E E 5/ T T T T B PT PT TE D0/ D1/ D3/ D4/ PT P T T T T P P P P Figure2-3. MC9S08GTxxA in 44-Pin QFP Package MC9S08GB60A Data Sheet, Rev. 2 26 Freescale Semiconductor

Chapter2 Pins and Connections VDDAD 1 42 PTA7/KBI1P7 VSSAD 2 41 PTA6/KBI1P6 PTG0/BKGD/MS 3 40 PTA5/KBI1P5 PTG1/XTAL 4 39 PTA4/KBI1P4 PTG2/EXTAL 5 38 PTA3/KBI1P3 RESET 6 37 PTA2/KBI1P2 PTC0/TxD2 7 36 PTA1/KBI1P1 PTC1/RXD2 8 35 PTA0/KBI1P0 PTC2/SDA1 9 34 VREFL PTC3/SCL1 10 33 V REFH PTC4 11 32 PTB7/AD1P7 PTE0/TxD1 12 31 PTB6/AD1P6 PTE1/RxD1 13 30 PTB5/AD1P5 IRQ 14 29 PTB4/AD1P4 PTE2/SS1 15 28 PTB3/AD1P3 PTE3/MISO1 16 27 PTB2/AD1P2 PTE4/MOSI1 17 26 PTB1/AD1P1 PTE5/SPSCK1 18 25 PTB0/AD1P0 VSS 19 24 PTD4/TPM2CH1 VDD 20 23 PTD3/TPM2CH0 PTD0/TPM1CH0 21 22 PTD1/TPM1CH1 Figure2-4. . MC9S08GTxxA in 42-Pin SDIP Package 2.3 Recommended System Connections Figure 2-4 shows pin connections that are common to almost all MC9S08GBxxA application systems. MC9S08GTxxA connections will be similar except for the number of I/O pins available. A more detailed discussion of system connections follows. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 27

Chapter2 Pins and Connections V REFH V DDAD C BYAD MC9S08GBxxA/GTxxA 0.1 μF V PTA0/KBI1P0 SYSTEM VDD VSSAD PTA1/KBI1P1 POWER REFL VDD PTA2/KBI1P2 + 3 V CBLK + CBY PORT PTA3/KBI1P3 10 μF 0.1 μF A PTA4/KBI1P4 VSS PTA5/KBI1P5 NOTE 4 PTA6/KBI1P6 PTA7/KBI1P7 NOTE 1 R F R S PTB0/AD1P0 XTAL NOTE 2 PTB1/AD1P1 C1 X1 C2 PTB2/AD1P2 EXTAL PORT PTB3/AD1P3 NOTE 2 B PTB4/AD1P4 BACKGROUND HEADER PTB5/AD1P5 PTB6/AD1P6 I/O AND V PTB7/AD1P7 PERIPHERAL DD BKGD/MS NOTE 3 V PTC0/TxD2 INTERFACE TO DD PTC1/RxD2 APPLICATION 4.7 kΩ–10 kΩ PTC2/SDA1 SYSTEM RESET PORT PTC3/SCL1 0.1 μF NOTE 5 C PTC4 OPTIONAL VDD PTC5 MANUAL PTC6 RESET 4.7 kΩ–10 kΩ ASYNCHRONOUS PTC7 INTERRUPT IRQ INPUT 0.1 μF NOTE 5 PTG0/BKDG/MS PTD0/TPM1CH0 PTG1/XTAL PTD1/TPM1CH1 PTG2/EXTAL PTD2/TPM1CH2 PTG3 PORT PORT PTD3/TPM2CH0 NOTES: 1. Not required if using the PTG4 G D PTD4/TPM2CH1 internal oscillator option. PTG5 PTD5/TPM2CH2 2. These are the same pins as PTG6 PTD6/TPM2CH3 PTG1 and PTG2. PTG7 PTD7/TPM2CH4 3. BKGD/MS is the same pin as PTG0. PTF0 PTE0/TxD1 4. The 48-pin QFN has 2 VSS PTF1 PTE1/RxD1 pins (V and V ), both SS1 SS2 PTF2 PTE2/SS1 of which must be connected to GND. PTF3 PORT PORT PTE3/MISO1 5. RC filters on RESET and PTF4 F E PTE4/MOSI1 IRQ are recommended for PTF5 PTE5/SPSCK1 EMC-sensitive applications PTF6 PTE6 PTF7 PTE7 Figure2-5. Basic System Connections MC9S08GB60A Data Sheet, Rev. 2 28 Freescale Semiconductor

Chapter2 Pins and Connections 2.3.1 Power V and V are the primary power supply pins for the MCU. This voltage source supplies power to all DD SS I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1-μF ceramic bypass capacitor located as close to the MCU power pins as practical to suppress high-frequency noise. V and V are the analog power supply pins for the MCU. This voltage source supplies power to DDAD SSAD the ATD. A 0.1-μF ceramic bypass capacitor should be located as close to the MCU power pins as practical to suppress high-frequency noise. 2.3.2 Oscillator Out of reset, the MCU uses an internally generated clock (self-clocked mode — f ), that is Self_reset approximately equivalent to an 8-MHz crystal rate. This frequency source is used during reset startup and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. This MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the MCU. For more information on the ICG, see Chapter7, “Internal Clock Generator (S08ICGV2).” The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL input pin, and the XTAL output pin can be used as general I/O. Refer to Figure 2-4 for the following discussion. R (when used) and R should be low-inductance S F resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically designed for high-frequency applications. R is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its F value is not generally critical. Typical systems use 1MΩ to 10MΩ. Higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup. C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 which are usually the same size. As a first-order approximation, use 10pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). 2.3.3 Reset RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 29

Chapter2 Pins and Connections debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for approximately 34cycles of f , released, and sampled again approximately 38 Self_reset cycles of f later. If reset was caused by an internal source such as low-voltage reset or watchdog Self_reset timeout, the circuitry expects the reset pin sample to return a logic 1. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system control reset status register (SRS). In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure2-4 for an example. 2.3.4 Background / Mode Select (PTG0/BKGD/MS) The background/mode select (BKGD/MS) shares its function with an I/O port pin. While in reset, the pin functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and can be used for background debug communication. While functioning as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew rate control. When used as an I/O port (PTG0) the pin is limited to output only. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during the rising edge of reset which forces the MCU to active background mode. The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. 2.3.5 General-Purpose I/O and Peripheral Ports The remaining 55 pins are shared among general-purpose I/O and on-chip peripheral functions such as timers and serial I/O systems. (17 of these pins are not bonded out on the 48-pin package, 20 of these pins are not bonded out on the 44-pin package and 22 of hese pins are not bonded out on the 42-pin package.) Immediately after reset, all 55 of these pins are configured as high-impedance general-purpose inputs with internal pullup devices disabled. NOTE To prevent extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float. MC9S08GB60A Data Sheet, Rev. 2 30 Freescale Semiconductor

Chapter2 Pins and Connections For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the appropriate section from Table 2-1. Table2-1. Pin Sharing References Alternate Port Pins Reference1 Function PTA7–PTA0 KBI1P7–KBI1P0 Chapter2, “Pins and Connections” PTB7–PTB0 AD1P7–AD1P0 Chapter14, “Analog-to-Digital Converter (S08ATDV3)” PTC7–PTC4 — Chapter6, “Parallel Input/Output” PTC3–PTC2 SCL1–SDA1 Chapter13, “Inter-Integrated Circuit (S08IICV1)” PTC1–PTC0 RxD2–TxD2 Chapter11, “Serial Communications Interface (S08SCIV1)” TPM2CH4– PTD7–PTD3 Chapter10, “Timer/PWM (S08TPMV1)” TPM2CH0 TPM1CH2– PTD2–PTD0 Chapter10, “Timer/PWM (S08TPMV1)” TPM1CH0 PTE7–PTE6 — Chapter6, “Parallel Input/Output” PTE5 SPSCK1 PTE4 MISO1 Chapter12, “Serial Peripheral Interface (S08SPIV3)” PTE3 MOSI1 PTE2 SS1 PTE1–PTE0 RxD1–TxD1 Chapter11, “Serial Communications Interface (S08SCIV1)” PTF7–PTF0 — Chapter6, “Parallel Input/Output” PTG7–PTG3 — Chapter6, “Parallel Input/Output” PTG2–PTG1 EXTAL–XTAL Chapter7, “Internal Clock Generator (S08ICGV2)” PTG0 BKGD/MS Chapter15, “Development Support” 1 See this section for information about modules that share these pins. When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin’s output buffer. See Chapter 6, “Parallel Input/Output” for details. Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTA7–PTA4 pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices. Similarly, when IRQ is configured as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device rather than a pullup device. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 31

Chapter2 Pins and Connections 2.3.6 Signal Properties Summary Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the common pin interfaces are hardwired to internal circuits. Table2-2. Signal Properties Pin High Current Output Dir Pull-Up2 Comments Name Pin Slew 1 VDD — — — The 48-pin QFN package has two V pins — V VSS — — — and V . SS SS1 SS2 VDDAD — — — VSSAD — — — VREFH — — — VREFL — — — RESET I/O Y N Y Pin contains integrated pullup. IRQPE must be set to enable IRQ function. IRQ does not have a clamp diode to V . IRQ should DD not be driven above V . DD IRQ I — — Y Pullup/pulldown active when IRQ pin function enabled. Pullup forced on when IRQ enabled for falling edges; pulldown forced on when IRQ enabled for rising edges. PTA0/KBI1P0 I/O N SWC SWC PTA1/KBI1P1 I/O N SWC SWC PTA2/KBI1P2 I/O N SWC SWC PTA3/KBI1P3 I/O N SWC SWC PTA4/KBI1P4 I/O N SWC SWC Pullup/pulldown active when KBI pin function PTA5/KBI1P5 I/O N SWC SWC enabled. Pullup forced on when KBI1Px enabled for PTA6/KBI1P6 I/O N SWC SWC falling edges; pulldown forced on when KBI1Px enabled for rising edges. PTA7/KBI1P7 I/O N SWC SWC PTB0/AD1P0 I/O N SWC SWC PTB1/AD1P1 I/O N SWC SWC PTB2/AD1P2 I/O N SWC SWC PTB3/AD1P3 I/O N SWC SWC PTB4/AD1P4 I/O N SWC SWC PTB5/AD1P5 I/O N SWC SWC PTB6/AD1P6 I/O N SWC SWC PTB7/AD1P7 I/O N SWC SWC PTC0/TxD2 I/O Y SWC SWC When pin is configured for SCI function, pin is PTC1/RxD2 I/O Y SWC SWC configured for partial output drive. PTC2/SDA1 I/O Y SWC SWC PTC3/SCL1 I/O Y SWC SWC PTC4 I/O Y SWC SWC PTC5 I/O Y SWC SWC Not available on 42-pin package PTC6 I/O Y SWC SWC Not available on 42-pin package MC9S08GB60A Data Sheet, Rev. 2 32 Freescale Semiconductor

Chapter2 Pins and Connections Table2-2. Signal Properties (continued) Pin High Current Output Dir Pull-Up2 Comments Name Pin Slew 1 PTC7 I/O Y SWC SWC Not available on 42-pin package PTD0/TPM1CH0 I/O N SWC SWC PTD1/TPM1CH1 I/O N SWC SWC PTD2/TPM1CH2 I/O N SWC SWC Not available on 42-pin , or 44-pin package PTD3/TPM2CH0 I/O N SWC SWC PTD4/TPM2CH1 I/O N SWC SWC PTD5/TPM2CH2 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package PTD6/TPM2CH3 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package PTD7/TPM2CH4 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package PTE0/TxD1 I/O N SWC SWC PTE1/RxD1 I/O N SWC SWC PTE2/SS1 I/O N SWC SWC PTE3/MISO1 I/O N SWC SWC PTE4/MOSI1 I/O N SWC SWC PTE5/SPSCK1 I/O N SWC SWC PTE6 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package PTE7 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package PTF0 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package PTF1 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package PTF2 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package PTF3 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package PTF4 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package PTF5 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package PTF6 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package PTF7 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package Pullup enabled and slew rate disabled when BDM PTG0/BKGD/MS O N SWC SWC function enabled. Pullup and slew rate disabled when XTAL pin PTG1/XTAL I/O N SWC SWC function. Pullup and slew rate disabled when EXTAL pin PTG2/EXTAL I/O N SWC SWC function. PTG3 I/O N SWC SWC Not available on 42- or 44-pin package PTG4 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package PTG5 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package PTG6 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package PTG7 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package 1 SWC is software controlled slew rate, the register is associated with the respective port. 2 SWC is software controlled pullup resistor, the register is associated with the respective port. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 33

Chapter2 Pins and Connections MC9S08GB60A Data Sheet, Rev. 2 34 Freescale Semiconductor

Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08GBxxA/GTxxA are described in this section. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 Features • Active background mode for code development • Wait mode: — CPU shuts down to conserve power — System clocks running — Full voltage regulation maintained • Stop modes: — System clocks stopped; voltage regulator in standby — Stop1 — Full power down of internal circuits for maximum power savings — Stop2 — Partial power down of internal circuits, RAM contents retained — Stop3 — All internal circuits powered for fast recovery 3.3 Run Mode This is the normal operating mode for the MC9S08GBxxA/GTxxA. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset. 3.4 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for analyzing MCU operation during software development. Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 35

Chapter3 Modes of Operation • When encountering a DBG breakpoint After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run mode; non-intrusive commands can also be executed while the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command • Active background commands, which can be executed only while the MCU is in active background mode. Active background commands include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user’s application program (GO) The active background mode is used to program a bootloader or user application program into the flash program memory before the MCU is operated in run mode for the first time. When the MC9S08GBxxA/GTxxA is shipped from the Freescale Semiconductor factory, the flash program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the flash memory is initially programmed. The active background mode can also be used to erase and reprogram the flash memory after it has been previously programmed. For additional information about the active background mode, refer to Chapter 15, “Development Support. 3.5 Wait Mode Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. 3.6 Stop Modes One of three stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In all stop modes, all internal clocks are halted. If the STOPE bit is not set MC9S08GB60A Data Sheet, Rev. 2 36 Freescale Semiconductor

Chapter3 Modes of Operation when the CPU executes a STOP instruction, the MCU will not enter any of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2. Table 3-1 summarizes the behavior of the MCU in each of the stop modes. Table3-1. Stop Mode Behavior CPU, Digital Mode PDC PPDC Peripherals, RAM ICG ATD Regulator I/O Pins RTI Flash Stop1 1 0 Off Off Off Disabled1 Off Reset Off Stop2 1 1 Off Standby Off Disabled Standby States held Optionally on Stop3 0 Don’t Standby Standby Off2 Disabled Standby States held Optionally on care 1 Either ATD stop mode or power-down mode depending on the state of ATDPU. 2 Crystal oscillator can be configured to run in stop3. Please see the ICG registers. 3.6.1 Stop1 Mode The stop1 mode provides the lowest possible standby power consumption by causing the internal circuitry of the MCU to be powered down. Stop1 can be entered only if the LVD circuit is not enabled in stop modes (either LVDE or LVDSE not set). When the MCU is in stop1 mode, all internal circuits that are powered from the voltage regulator are turned off. The voltage regulator is in a low-power standby state, as is the ATD. Exit from stop1 is performed by asserting either of the wake-up pins on the MCU: RESET or IRQ. IRQ is always an active low input when the MCU is in stop1, regardless of how it was configured before entering stop1. Entering stop1 mode automatically asserts LVD. Stop1 cannot be exited until V > V rising (V DD LVDH/L DD must rise above the LVI rearm voltage). Upon wake-up from stop1 mode, the MCU will start up as from a power-on reset (POR). The CPU will take the reset vector. 3.6.2 Stop2 Mode The stop2 mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I/O pins. Stop2 can be entered only if the LVD circuit is not enabled in stop modes (either LVDE or LVDSE not set). Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other memory-mapped registers they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2, these values can be restored by user software before pin latches are opened. When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ATD. Upon entry MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 37

Chapter3 Modes of Operation into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting stop2 mode until a 1 is written to PPDACK in SPMSC2. Exit from stop2 is performed by asserting either of the wake-up pins: RESET or IRQ, or by an RTI interrupt. IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured before entering stop2. Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default reset states and must be initialized. After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written to PPDACK in SPMSC2. To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.3 Stop3 Mode Upon entering the stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The ICG is turned off, the ATD is disabled, and the voltage regulator is put in standby. The states of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained. Exit from stop3 is performed by asserting RESET, an asynchronous interrupt pin, or through the real-time interrupt. The asynchronous interrupt pins are the IRQ or KBI pins. If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in the MCU taking the appropriate interrupt vector. A separate self-clocked source (≈1kHz) for the real-time interrupt allows a wakeup from stop2 or stop3 mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop. MC9S08GB60A Data Sheet, Rev. 2 38 Freescale Semiconductor

Chapter3 Modes of Operation 3.6.4 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in the Chapter 15, “Development Support,” section of this data sheet. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode so background debug communication is still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the user attempts to enter either stop1 or stop2 with ENBDM set, the MCU will instead enter stop3. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After the device enters background debug mode, all background commands are available. The table below summarizes the behavior of the MCU in stop when entry into the background debug mode is enabled. Table3-2. BDM Enabled Stop Mode Behavior CPU, Digital Mode PDC PPDC Peripherals, RAM ICG ATD Regulator I/O Pins RTI1 Flash Stop3 Don’t Don’t Standby Standby Active Disabled2 Active States held Optionally on care care 1 The 1 kHz internal RTI clock is not available in stop3 with active BDM enabled. 2 Either ATD stop mode or power-down mode depending on the state of ATDPU. 3.6.5 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits in SPMSC1 when the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the user attempts to enter either stop1 or stop2 with the LVD enabled for stop (LVDSE= 1), the MCU will instead enter stop3. The table below summarizes the behavior of the MCU in stop when the LVD is enabled. Table3-3. LVD Enabled Stop Mode Behavior CPU, Digital Mode PDC PPDC Peripherals, RAM ICG ATD Regulator I/O Pins RTI Flash Stop3 Don’t Don’t Standby Standby Standby Disabled1 Active States held Optionally on care care 1 Either ATD stop mode or power-down mode depending on the state of ATDPU. 3.6.6 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 39

Chapter3 Modes of Operation clocks to the peripheral systems are halted to reduce power consumption. Refer to Section3.6.1, “Stop1 Mode,” Section3.6.2, “Stop2 Mode,” and Section3.6.3, “Stop3 Mode,” for specific information on system behavior in stop modes. I/O Pins • All I/O pin states remain unchanged when the MCU enters stop3 mode. • If the MCU is configured to go into stop2 mode, all I/O pins states are latched before entering stop. • If the MCU is configured to go into stop1 mode, all I/O pins are forced to their default reset state upon entry into stop. Memory • All RAM and register contents are preserved while the MCU is in stop3 mode. • All registers will be reset upon wake-up from stop2, but the contents of RAM are preserved and pin states remain latched until the PPDACK bit is written. The user may save any memory-mapped register data into RAM before entering stop2 and restore the data upon exit from stop2. • All registers will be reset upon wake-up from stop1 and the contents of RAM are not preserved. The MCU must be initialized as upon reset. The contents of the flash memory are nonvolatile and are preserved in any of the stop modes. ICG — In stop3 mode, the ICG enters its low-power standby state. Either the oscillator or the internal reference may be kept running when the ICG is in standby by setting the appropriate control bit. In both stop2 and stop1 modes, the ICG is turned off. Neither the oscillator nor the internal reference can be kept running in stop2 or stop1, even if enabled within the ICG module. TPM — When the MCU enters stop mode, the clock to the TPM1 and TPM2 modules stop. The modules halt operation. If the MCU is configured to go into stop2 or stop1 mode, the TPM modules will be reset upon wake-up from stop and must be reinitialized. ATD — When the MCU enters stop mode, the ATD will enter a low-power standby state. No conversion operation will occur while in stop. If the MCU is configured to go into stop2 or stop1 mode, the ATD will be reset upon wake-up from stop and must be reinitialized. KBI — During stop3, the KBI pins that are enabled continue to function as interrupt sources that are capable of waking the MCU from stop3. The KBI is disabled in stop1 and stop2 and must be reinitialized after waking up from either of these modes. RTI — During stop2 and stop3, the RTI continues to operate as an interrupt wakeup source. During stop1, the RTI is disabled. In stop2, the RTI uses the internal 1 kHz RTI clock, but in stop3 mode, the RTI uses either the external clock or the internal RTI clock. When the active BDM mode is enabled though, the internal RTI clock is not operational. SCI — When the MCU enters stop mode, the clocks to the SCI1 and SCI2 modules stop. The modules halt operation. If the MCU is configured to go into stop2 or stop1 mode, the SCI modules will be reset upon wake-up from stop and must be reinitialized. SPI — When the MCU enters stop mode, the clocks to the SPI module stop. The module halts operation. If the MCU is configured to go into stop2 or stop1 mode, the SPI module will be reset upon wake-up from stop and must be reinitialized. MC9S08GB60A Data Sheet, Rev. 2 40 Freescale Semiconductor

Chapter3 Modes of Operation IIC — When the MCU enters stop mode, the clocks to the IIC module stops. The module halts operation. If the MCU is configured to go into stop2 or stop1 mode, the IIC module will be reset upon wake-up from stop and must be reinitialized. Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any of the stop modes unless the LVD is enabled in stop mode or BDM is enabled. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 41

Chapter3 Modes of Operation MC9S08GB60A Data Sheet, Rev. 2 42 Freescale Semiconductor

Chapter 4 Memory 4.1 MC9S08GBxxA/GTxxA Memory Map As shown in Figure 4-1, on-chip memory in the MC9S08GBxxA/GTxxA series of MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x007F) • High-page registers (0x1800 through 0x182B) • Nonvolatile registers (0xFFB0 through 0xFFBF) 0x0000 0x0000 DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS 0x007F 0x007F 0x0080 0x0080 RAM RAM 2048 BYTES 0x087F 0x0880 4096 BYTES UNIMPLEMENTED 0x107F 0x1080 3968 BYTES FLASH 1920 BYTES 0x17FF 0x17FF 0x1800 0x1800 HIGH PAGE REGISTERS HIGH PAGE REGISTERS 0x182B 0x182B 0x182C 0x182C UNIMPLEMENTED 26580 BYTES 0x7FFF 0x8000 FLASH 59348 BYTES FLASH 32768 BYTES 0xFFFF 0xFFFF MC9S08GB60A/MC9S08GT60A MC9S08GB32A/MC9S08GT32A Figure4-1. MC9S08GBxxA/GTxxA Memory Map MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 43

Chapter4 Memory 4.1.1 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08GBxxA/GTxxA. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter5, “Resets, Interrupts, and System Configuration.” Table4-1. Reset and Interrupt Vectors Address Vector Vector Name (High/Low) 0xFFC0:FFC1 Unused Vector Space (available for user program) 0xFFCA:FFCB 0xFFCC:FFCD RTI Vrti 0xFFCE:FFCF IIC Viic1 0xFFD0:FFD1 ATD Conversion Vatd1 0xFFD2:FFD3 Keyboard Vkeyboard1 0xFFD4:FFD5 SCI2 Transmit Vsci2tx 0xFFD6:FFD7 SCI2 Receive Vsci2rx 0xFFD8:FFD9 SCI2 Error Vsci2err 0xFFDA:FFDB SCI1 Transmit Vsci1tx 0xFFDC:FFDD SCI1 Receive Vsci1rx 0xFFDE:FFDF SCI1 Error Vsci1err 0xFFE0:FFE1 SPI Vspi1 0xFFE2:FFE3 TPM2 Overflow Vtpm2ovf 0xFFE4:FFE5 TPM2 Channel 4 Vtpm2ch4 0xFFE6:FFE7 TPM2 Channel 3 Vtpm2ch3 0xFFE8:FFE9 TPM2 Channel 2 Vtpm2ch2 0xFFEA:FFEB TPM2 Channel 1 Vtpm2ch1 0xFFEC:FFED TPM2 Channel 0 Vtpm2ch0 0xFFEE:FFEF TPM1 Overflow Vtpm1ovf 0xFFF0:FFF1 TPM1 Channel 2 Vtpm1ch2 0xFFF2:FFF3 TPM1 Channel 1 Vtpm1ch1 0xFFF4:FFF5 TPM1 Channel 0 Vtpm1ch0 0xFFF6:FFF7 ICG Vicg 0xFFF8:FFF9 Low Voltage Detect Vlvd 0xFFFA:FFFB IRQ Virq 0xFFFC:FFFD SWI Vswi 0xFFFE:FFFF Reset Vreset MC9S08GB60A Data Sheet, Rev. 2 44 Freescale Semiconductor

Chapter4 Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08GBxxA/GTxxA are divided into these three groups: • Direct-page registers are located in the first 128 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables. • The nonvolatile register area consists of a block of 16locations in flash memory at 0xFFB0–0xFFBF. Nonvolatile register locations include: — Three values which are loaded into working registers at reset — An 8-byte backdoor comparison key which optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are flash memory, they must be erased and programmed like other flash memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efficient direct addressing mode which only requires the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-3 and Table4-4 the whole address in column one is shown in bold. In Table 4-2, Table4-3, and Table4-4, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 45

Chapter4 Memory Table4-2. Direct-Page Register Summary (Sheet 1 of 3) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 PTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 0x0001 PTAPE PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 0x0002 PTASE PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 0x0003 PTADD PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0 0x0004 PTBD PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 0x0005 PTBPE PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0x0006 PTBSE PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 0x0007 PTBDD PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0 0x0008 PTCD PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 0x0009 PTCPE PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0x000A PTCSE PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0 0x000B PTCDD PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0 0x000C PTDD PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0 0x000D PTDPE PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 0x000E PTDSE PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 0x000F PTDDD PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0 0x0010 PTED PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0 0x0011 PTEPE PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 0x0012 PTESE PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0 0x0013 PTEDD PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0 0x0014 IRQSC 0 0 IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD 0x0015 Reserved — — — — — — — — 0x0016 KBI1SC KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBF KBACK KBIE KBIMOD 0x0017 KBI1PE KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 0x0018 SCI1BDH 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 0x0019 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x001A SCI1C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0x001B SCI1C2 TIE TCIE RIE ILIE TE RE RWU SBK 0x001C SCI1S1 TDRE TC RDRF IDLE OR NF FE PF 0x001D SCI1S2 0 0 0 0 0 0 0 RAF 0x001E SCI1C3 R8 T8 TXDIR 0 ORIE NEIE FEIE PEIE 0x001F SCI1D Bit 7 6 5 4 3 2 1 Bit 0 0x0020 SCI2BDH 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 0x0021 SCI2BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x0022 SCI2C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0x0023 SCI2C2 TIE TCIE RIE ILIE TE RE RWU SBK 0x0024 SCI2S1 TDRE TC RDRF IDLE OR NF FE PF 0x0025 SCI2S2 0 0 0 0 0 0 0 RAF 0x0026 SCI2C3 R8 T8 TXDIR 0 ORIE NEIE FEIE PEIE 0x0027 SCI2D Bit 7 6 5 4 3 2 1 Bit 0 MC9S08GB60A Data Sheet, Rev. 2 46 Freescale Semiconductor

Chapter4 Memory Table4-2. Direct-Page Register Summary (Sheet 2 of 3) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0028 SPI1C1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0x0029 SPI1C2 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0 0x002A SPI1BR 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0 0x002B SPI1S SPRF 0 SPTEF MODF 0 0 0 0 0x002C Reserved 0 0 0 0 0 0 0 0 0x002D SPI1D Bit 7 6 5 4 3 2 1 Bit 0 0x002E Reserved 0 0 0 0 0 0 0 0 0x002F Reserved 0 0 0 0 0 0 0 0 0x0030 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0x0031 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x0032 TPM1CNTL Bit 7 6 5 4 3 2 1 Bit 0 0x0033 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8 0x0034 TPM1MODL Bit 7 6 5 4 3 2 1 Bit 0 0x0035 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0x0036 TPM1C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0037 TPM1C0VL Bit 7 6 5 4 3 2 1 Bit 0 0x0038 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 0x0039 TPM1C1VH Bit 15 14 13 12 11 10 9 Bit 8 0x003A TPM1C1VL Bit 7 6 5 4 3 2 1 Bit 0 0x003B TPM1C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0 0x003C TPM1C2VH Bit 15 14 13 12 11 10 9 Bit 8 0x003D TPM1C2VL Bit 7 6 5 4 3 2 1 Bit 0 0x003E– — — — — — — — — Reserved 0x003F — — — — — — — — 0x0040 PTFD PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0 0x0041 PTFPE PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 0x0042 PTFSE PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0 0x0043 PTFDD PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0 0x0044 PTGD PTGD7 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0 0x0045 PTGPE PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0 0x0046 PTGSE PTGSE7 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0 0x0047 PTGDD PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0 0x0048 ICGC1 HGO RANGE REFS CLKS OSCSTEN LOCD 0 0x0049 ICGC2 LOLRE MFD LOCRE RFD 0x004A ICGS1 CLKST REFST LOLS LOCK LOCS ERCS ICGIF 0x004B ICGS2 0 0 0 0 0 0 0 DCOS 0x004C ICGFLTU 0 0 0 0 FLT 0x004D ICGFLTL FLT 0x004E ICGTRM TRIM 0x004F Reserved 0 0 0 0 0 0 0 0 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 47

Chapter4 Memory Table4-2. Direct-Page Register Summary (Sheet 3 of 3) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0050 ATD1C ATDPU DJM RES8 SGN PRS 0x0051 ATD1SC CCF ATDIE ATDCO ATDCH 0x0052 ATD1RH Bit 7 6 5 4 3 2 1 Bit 0 0x0053 ATD1RL Bit 7 6 5 4 3 2 1 Bit 0 0x0054 ATD1PE ATDPE7 ATDPE6 ATDPE5 ATDPE4 ATDPE3 ATDPE2 ATDPE1 ATDPE0 0x0055– — — — — — — — — Reserved 0x0057 — — — — — — — — 0x0058 IIC1A ADDR 0 0x0059 IIC1F MULT ICR 0x005A IIC1C IICEN IICIE MST TX TXAK RSTA 0 0 0x005B IIC1S TCF IAAS BUSY ARBL 0 SRW IICIF RXAK 0x005C IIC1D DATA 0x005D– — — — — — — — — Reserved 0x005F — — — — — — — — 0x0060 TPM2SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0x0061 TPM2CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x0062 TPM2CNTL Bit 7 6 5 4 3 2 1 Bit 0 0x0063 TPM2MODH Bit 15 14 13 12 11 10 9 Bit 8 0x0064 TPM2MODL Bit 7 6 5 4 3 2 1 Bit 0 0x0065 TPM2C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0x0066 TPM2C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0067 TPM2C0VL Bit 7 6 5 4 3 2 1 Bit 0 0x0068 TPM2C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 0x0069 TPM2C1VH Bit 15 14 13 12 11 10 9 Bit 8 0x006A TPM2C1VL Bit 7 6 5 4 3 2 1 Bit 0 0x006B TPM2C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0 0x006C TPM2C2VH Bit 15 14 13 12 11 10 9 Bit 8 0x006D TPM2C2VL Bit 7 6 5 4 3 2 1 Bit 0 0x006E TPM2C3SC CH3F CH3IE MS3B MS3A ELS3B ELS3A 0 0 0x006F TPM2C3VH Bit 15 14 13 12 11 10 9 Bit 8 0x0070 TPM2C3VL Bit 7 6 5 4 3 2 1 Bit 0 0x0071 TPM2C4SC CH4F CH4IE MS4B MS4A ELS4B ELS4A 0 0 0x0072 TPM2C4VH Bit 15 14 13 12 11 10 9 Bit 8 0x0073 TPM2C4VL Bit 7 6 5 4 3 2 1 Bit 0 0x0074– — — — — — — — — Reserved 0x007F — — — — — — — — MC9S08GB60A Data Sheet, Rev. 2 48 Freescale Semiconductor

Chapter4 Memory High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. Table4-3. High-Page Register Summary Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x1800 SRS POR PIN COP ILOP 0 ICG LVD 0 0x1801 SBDFR 0 0 0 0 0 0 0 BDFR 0x1802 SOPT COPE COPT STOPE — 0 0 BKGDPE — 0x1803 – — — — — — — — — Reserved 0x1805 — — — — — — — — 0x1806 SDIDH REV3 REV2 REV1 REV0 ID11 ID10 ID9 ID8 0x1807 SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0x1808 SRTISC RTIF RTIACK RTICLKS RTIE 0 RTIS2 RTIS1 RTIS0 0x1809 SPMSC1 LVDF LVDACK LVDIE LVDRE LVDSE LVDE 0 0 0x180A SPMSC2 LVWF LVWACK LVDV LVWV PPDF PPDACK PDC PPDC 0x180B– — — — — — — — — Reserved 0x180F — — — — — — — — 0x1810 DBGCAH Bit 15 14 13 12 11 10 9 Bit 8 0x1811 DBGCAL Bit 7 6 5 4 3 2 1 Bit 0 0x1812 DBGCBH Bit 15 14 13 12 11 10 9 Bit 8 0x1813 DBGCBL Bit 7 6 5 4 3 2 1 Bit 0 0x1814 DBGFH Bit 15 14 13 12 11 10 9 Bit 8 0x1815 DBGFL Bit 7 6 5 4 3 2 1 Bit 0 0x1816 DBGC DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0x1817 DBGT TRGSEL BEGIN 0 0 TRG3 TRG2 TRG1 TRG0 0x1818 DBGS AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0x1819– — — — — — — — — Reserved 0x181F — — — — — — — — 0x1820 FCDIV DIVLD PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 0x1821 FOPT KEYEN FNORED 0 0 0 0 SEC01 SEC00 0x1822 Reserved — — — — — — — — 0x1823 FCNFG 0 0 KEYACC 0 0 0 0 0 0x1824 FPROT FPOPEN FPDIS FPS2 FPS1 FPS0 0 0 0 0x1825 FSTAT FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0 0x1826 FCMD FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0 0x1827– — — — — — — — — Reserved 0x182B — — — — — — — — Nonvolatile flash registers, shown in Table 4-4, are located in the flash memory. These registers include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the flash memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 49

Chapter4 Memory Table4-4. Nonvolatile Register Summary Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0xFFB0 – NVBACKKEY 8-Byte Comparison Key 0xFFB7 0xFFB8 – Reserved — — — — — — — — 0xFFBC — — — — — — — — 0xFFBD NVPROT FPOPEN FPDIS FPS2 FPS1 FPS0 0 0 0 0xFFBE Reserved1 — — — — — — — — 0xFFBF NVOPT KEYEN FNORED 0 0 0 0 SEC01 SEC00 1 This location is used to store the factory trim value for the ICG. Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the flash if needed (normally through the background debug interface) and verifying that flash is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC01:SEC00) to the unsecured state (1:0). 4.3 RAM The MC9S08GBxxA/GTxxA includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08GBxxA/GTxxA, it is usually best to re-initialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale-provided equate file). LDHX #RamLast+1 ;point one past RAM TXS ;SP<-(H:X-1) When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or through code executing from non-secure memory. See Section4.5, “Security” for a detailed description of the security feature. 4.4 Flash The flash memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the flash memory after final assembly of the application product. It is possible MC9S08GB60A Data Sheet, Rev. 2 50 Freescale Semiconductor

Chapter4 Memory to program the entire array through the single-wire background debug interface. Because no special voltages are needed for flash erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1/D. 4.4.1 Features Features of the flash memory include: • Flash Size — MC9S08GB60A/MC9S08GT60A — 61268 bytes (120 pages of 512 bytes each) — MC9S08GB32A/MC9S08GT32A— 32768 bytes (64 pages of 512 bytes each) • Single power supply program and erase • Command interface for fast program and erase operation • Up to 100,000 program/erase cycles at typical voltage and temperature • Flexible block protection • Security feature for flash and RAM • Auto power-down for low-frequency read accesses 4.4.2 Program and Erase Times Before any program or erase command can be accepted, the flash clock divider register (FCDIV) must be written to set the internal clock for the flash module to a frequency (f ) between 150 kHz and 200 kHz FCLK (see Table 4.6.1). This register can be written only once, so normally this write is done during reset initialization. FCDIV cannot be written if the access error flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting clock (1/f ) is used by the command processor to time program and erase pulses. An integer number of these FCLK timing pulses is used by the command processor to complete a program or erase command. Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency of FCLK (f ). The time for one cycle of FCLK is t = 1/f . The times are shown as a number FCLK FCLK FCLK of cycles of FCLK and as an absolute time for the case where t =5μs. Program and erase times FCLK shown include overhead for the command state machine and enabling and disabling of program and erase voltages. Table4-5. Program and Erase Times Parameter Cycles of FCLK Time if FCLK=200kHz Byte program 9 45μs Byte program (burst) 4 20μs1 Page erase 4000 20ms Mass erase 20,000 100ms 1 Excluding start/end overhead MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 51

Chapter4 Memory 4.4.3 Program and Erase Command Execution The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared before beginning command execution. The command execution steps are: 1. Write a data value to an address in the flash array. The address and data information from this write is latched into the flash interface. This write is a required first step in any command sequence. For erase and blank check commands, the value of the data is not important. For page erase commands, the address may be any address in the 512-byte page of flash to be erased. For mass erase and blank check commands, the address can be any address in the flash memory. Whole pages of 512bytes are the smallest blocks of flash that may be erased. In the 60K version, there are two instances where the size of a block that is accessible to the user is less than 512 bytes: the first page following RAM, and the first page following the high page registers. These pages are overlapped by the RAM and high page registers, respectively. NOTE Do not program any byte in the flash more than once after a successful erase operation. Reprogramming bits in a byte which is already programmed is not allowed without first erasing the page in which the byte resides or mass erasing the entire flash memory. Programming without first erasing may disturb data stored in the flash. 2. Write the command code for the desired command to FCMD. The five valid commands are blank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). The command code is latched into the command buffer. 3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its address and data information). A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to the memory array and before writing the 1 that clears FCBEF and launches the complete command. Aborting a command in this way sets the FACCERR access error flag which must be cleared before starting a new command. A strictly monitored procedure must be adhered to, or the command will not be accepted. This minimizes the possibility of any unintended change to the flash memory contents. The command complete flag (FCCF) indicates when a command is complete. The command sequence must be completed by clearing FCBEF to launch the command. Figure 4-2 is a flowchart for executing all of the commands except for burst programming. The FCDIV register must be initialized before using any flash commands. This must be done only once following a reset. MC9S08GB60A Data Sheet, Rev. 2 52 Freescale Semiconductor

Chapter4 Memory START 0 FACCERR ? CLEAR ERROR WRITE TO FCDIV(1) (1) Only required once after reset. WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF (2) Wait at least four bus cycles before TO LAUNCH COMMAND checking FCBEF or FCCF. AND CLEAR FCBEF (2) YES FPVIO OR ERROR EXIT FACCERR ? NO 0 FCCF ? 1 DONE Figure4-2. Flash Program and Erase Flowchart 4.4.4 Burst Program Execution The burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. This is possible because the high voltage to the flash array does not need to be disabled between program operations. Ordinarily, when a program or erase command is issued, an internal charge pump associated with the flash memory must be enabled to supply high voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst program command is issued, the charge pump is enabled and then remains enabled after completion of the burst program operation if the following two conditions are met: 1. The next burst program command has been queued before the current program operation has completed. 2. The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of flash memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero. The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 53

Chapter4 Memory program time provided that the conditions above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. This is because the high voltage to the array must be disabled and then enabled again. If a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. START 0 FACCERR ? 1 CLEAR ERROR WRITE TO FCDIV(1) (1) Only required once after reset. 0 FCBEF ? 1 WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF (2) Wait at least four bus cycles before TO LAUNCH COMMAND checking FCBEF or FCCF. AND CLEAR FCBEF (2) YES FPVIO OR ERROR EXIT FACCERR ? NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE Figure4-3. Flash Burst Program Flowchart MC9S08GB60A Data Sheet, Rev. 2 54 Freescale Semiconductor

Chapter4 Memory 4.4.5 Access Errors An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed. • Writing to a flash address before the internal flash clock frequency has been set by writing to the FCDIV register • Writing to a flash address while FCBEF is not set (A new command cannot be started until the command buffer is empty.) • Writing a second time to a flash address before launching the previous command (There is only one write to flash for every command.) • Writing a second time to FCMD before launching the previous command (There is only one write to FCMD for every command.) • Writing to any flash control register other than FCMD after writing to a flash address • Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to FCMD • Accessing (read or write) any flash control register other than the write to FSTAT (to clear FCBEF and launch the command) after writing the command to FCMD • The MCU enters stop mode while a program or erase command is in progress (The command is aborted.) • Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with a background debug command while the MCU is secured (The background debug controller can only do blank check and mass erase commands when the MCU is secure.) • Writing 0 to FCBEF to cancel a partial command 4.4.6 Flash Block Protection Block protection prevents program or erase changes for flash memory locations in a designated address range. Mass erase is disabled when any block of flash is protected. The MC9S08GBxxA/GTxxA allows a block of memory at the end of flash, and/or the entire flash memory to be block protected. A disable control bit and a 3-bit control field, allows the user to set the size of this block. A separate control bit allows block protection of the entire flash memory array. All seven of these control bits are located in the FPROT register (see Section4.6.4, “Flash Protection Register (FPROT and NVPROT)”). At reset, the high-page register (FPROT) is loaded with the contents of the NVPROT location which is in the nonvolatile register block of the flash memory. The value in FPROT cannot be changed directly from application software so a runaway program cannot alter the block protection settings. If the last 512 bytes of flash which includes the NVPROT register is protected, the application program cannot alter the block protection settings (intentionally or unintentionally). The FPROT control bits can be written by background debug commands to allow a way to erase a protected flash memory. One use for block protection is to block protect an area of flash memory for a bootloader program. This bootloader program then can be used to erase the rest of the flash memory and reprogram it. Because the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and reprogram operation. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 55

Chapter4 Memory 4.4.7 Vector Redirection Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register located at address 0xFFBF to zero. For redirection to occur, at least some portion but not all of the flash memory must be block protected by programming the NVPROT register located at address 0xFFBD. All of the interrupt vectors (memory locations 0xFFC0–0xFFFD) are redirected, while the reset vector (0xFFFE:FFFF) is not. When more than 32K is protected, vector redirection must not be enabled. For example, if 512 bytes of flash are protected, the protected address region is from 0xFE00 through 0xFFFF. The interrupt vectors (0xFFC0–0xFFFD) are redirected to the locations 0xFDC0–0xFDFD. Now, if an SPI interrupt is taken for instance, the values in the locations 0xFDE0:FDE1 are used for the vector instead of the values in the locations 0xFFE0:FFE1. This allows the user to reprogram the unprotected portion of the flash with new program code including new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged. 4.5 Security The MC9S08GBxxA/GTxxA includes circuitry to prevent unauthorized access to the contents of flash and RAM memory. When security is engaged, flash and RAM are considered secure resources. Direct-page registers, high-page registers, and the background debug controller are considered unsecured resources. Programs executing within secure memory have normal access to any MCU memory locations and resources. Attempts to access a secure memory location with a program executing from an unsecured memory space or through the background debug interface are blocked (writes are ignored and reads return all 0s). Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from flash into the working FOPT register in high-page register space. A user engages security by programming the NVOPT location which can be done at the same time the flash memory is programmed. The 1:0 state disengages security while the other three combinations engage security. Notice the erased state (1:1) makes the MCU secure. During development, whenever the flash is erased, it is good practice to immediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00= 1:0. This would allow the MCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug controller can still be used for background memory access commands, but the MCU cannot enter active background mode except by holding BKGD/MS low at the rising edge of reset. A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there is no way to disengage security without completely erasing all flash locations. If KEYEN is 1, a secure user program can temporarily disengage security by: 1. Writing 1 to KEYACC in the FCNFG register. This makes the flash module interpret writes to the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the first step in a flash program or erase command. MC9S08GB60A Data Sheet, Rev. 2 56 Freescale Semiconductor

Chapter4 Memory 2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations. These writes must be done in order, starting with the value for NVBACKKEY and ending with NVBACKKEY+7. STHX should not be used for these writes because these writes cannot be done on adjacent bus cycles. User software normally would get the key codes from outside the MCU system through a communication interface such as a serial I/O. 3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the key stored in the flash locations, SEC01:SEC00 are automatically changed to 1:0 and security will be disengaged until the next reset. The security key can be written only from RAM, so it cannot be entered through background commands without the cooperation of a secure user program. The flash memory cannot be accessed by read operations while KEYACC is set. The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in flash memory locations in the nonvolatile register space so users can program these locations just as they would program any other flash memory location. The nonvolatile registers are in the same 512-byte block of flash as the reset and interrupt vectors, so block protecting that space also block protects the backdoor comparison key. Block protects cannot be changed from user application programs, so if the vector space is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key. Security can always be disengaged through the background debug interface by performing these steps: 1. Disable any block protections by writing FPROT. FPROT can be written only with background debug commands, not from application software. 2. Mass erase flash, if necessary. 3. Blank check flash. Provided flash is completely erased, security is disengaged until the next reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00=1:0. 4.6 Flash Registers and Control Bits The flash module has nine 8-bit registers in the high-page register space, three locations in the nonvolatile register space in flash memory that are copied into three corresponding high-page control registers at reset. There is also an 8-byte comparison key in flash memory. Refer to Table4-3 and Table4-4 for the absolute address assignments for all flash registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 4.6.1 Flash Clock Divider Register (FCDIV) Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written only one time. Before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 57

Chapter4 Memory 7 6 5 4 3 2 1 0 R DIVLD PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure4-4. Flash Clock Divider Register (FCDIV) Table4-6. FCDIV Field Descriptions Field Description 7 Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been DIVLD written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless of the data written. 0 FCDIV has not been written since reset; erase and program operations disabled for flash. 1 FCDIV has been written since reset; erase and program operations enabled for flash. 6 Prescale (Divide) Flash Clock by 8 PRDIV8 0 Clock input to the flash clock divider is the bus rate clock. 1 Clock input to the flash clock divider is the bus rate clock divided by8. 5 Divisor for Flash Clock Divider — The flash clock divider divides the bus rate clock (or the bus rate clock DIV[5:0] divided by 8 if PRDIV8=1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the internal flash clock must fall within the range of 200kHz to 150kHz for proper flash operations. Program/erase timing pulses are one cycle of this internal flash clock, which corresponds to a range of 5μs to 6.7μs. The automated programming logic uses an integer number of these pulses to complete an erase or program operation. See Equation4-1 and Equation4-2. Table4-7 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies. if PRDIV8=0 — f = f ÷ ([DIV5:DIV0] + 1) Eqn.4-1 FCLK Bus if PRDIV8=1 — f = f ÷ (8 × ([DIV5:DIV0] + 1)) Eqn.4-2 FCLK Bus Table4-7. Flash Clock Divider Settings PRDIV8 DIV5:DIV0 Program/Erase Timing Pulse f f Bus (Binary) (Decimal) FCLK (5μs Min, 6.7 μs Max) 20 MHz 1 12 192.3 kHz 5.2μs 10 MHz 0 49 200 kHz 5μs 8 MHz 0 39 200 kHz 5μs 4 MHz 0 19 200 kHz 5μs 2 MHz 0 9 200 kHz 5μs 1 MHz 0 4 200 kHz 5μs 200 kHz 0 0 200 kHz 5μs 150 kHz 0 0 150 kHz 6.7μs MC9S08GB60A Data Sheet, Rev. 2 58 Freescale Semiconductor

Chapter4 Memory 4.6.2 Flash Options Register (FOPT and NVOPT) During reset, the contents of the nonvolatile location NVOPT are copied from flash into FOPT. Bits 5 through 2 are not used and always read 0. This register may be read at any time, but writes have no meaning or effect. To change the value in this register, erase and reprogram the NVOPT location in flash memory as usual and then issue a new MCU reset. 7 6 5 4 3 2 1 0 R KEYEN FNORED 0 0 0 0 SEC01 SEC00 W Reset This register is loaded from nonvolatile location NVOPT during reset. = Unimplemented or Reserved Figure4-5. Flash Options Register (FOPT) Table4-8. FOPT Field Descriptions Field Description 7 Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to KEYEN disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed information about the backdoor key mechanism, refer to Section4.5, “Security.” 0 No backdoor key access allowed. 1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through NVBACKKEY+7, in that order), security is temporarily disengaged until the next MCU reset. 6 Vector Redirection Disable — When this bit is 1, vector redirection is disabled. FNORED 0 Vector redirection enabled. 1 Vector redirection disabled. 1:0 Security State Code — This 2-bit field determines the security state of the MCU as shown below. When the SEC0[1:0] MCU is secure, the contents of RAM and flash memory cannot be accessed by instructions from any unsecured source including the background debug interface. For more detailed information about security, refer to Section4.5, “Security.” 00 Secure 01 Secure 10 Unsecured 11 Secure SEC0[1:0] changes to 10 after successful backdoor key entry or a successful blank check of flash. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 59

Chapter4 Memory 4.6.3 Flash Configuration Register (FCNFG) Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 KEYACC W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure4-6. Flash Configuration Register (FCNFG) Table4-9. FCNFG Field Descriptions Field Description 5 Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed KEYACC information about the backdoor key mechanism, refer to Section4.5, “Security.” 0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a flash programming or erase command. 1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes. Reads of the flash return invalid data. 4.6.4 Flash Protection Register (FPROT and NVPROT) During reset, the contents of the nonvolatile location NVPROT is copied from flash into FPROT. Bits 0, 1, and 2 are not used and each always reads as 0. This register may be read at any time, but user program writes have no meaning or effect. Background debug commands can write to FPROT. 7 6 5 4 3 2 1 0 R FPOPEN FPDIS FPS2 FPS1 FPS0 0 0 0 W (1) (1) (1) (1) (1) Reset This register is loaded from nonvolatile location NVPROT during reset. = Unimplemented or Reserved Figure4-7. Flash Protection Register (FPROT) 1 Background commands can be used to change the contents of these bits in FPROT. Table4-10. FPROT Field Descriptions Field Description 7 Open Unprotected Flash for Program/Erase FPOPEN 0 Entire flash memory is block protected (no program or erase allowed). 1 Any flash location, not otherwise block protected or secured, may be erased or programmed. MC9S08GB60A Data Sheet, Rev. 2 60 Freescale Semiconductor

Chapter4 Memory Table4-10. FPROT Field Descriptions (continued) Field Description 6 Flash Protection Disable FPDIS 0 Flash block specified by FPS2:FPS0 is block protected (program and erase not allowed). 1 No flash block is protected. 5:3 Flash Protect Size Selects — When FPDIS=0, this 3-bit field determines the size of a protected block of flash FPS[2:0] locations at the high address end of the flash (see Table4-11). Protected flash locations cannot be erased or programmed. Table4-11. High Address Protected Block FPS2:FPS1:FPS0 Protected Address Range Protected Block Size Redirected Vectors1,2 0:0:0 0xFE00–0xFFFF 512 bytes 0xFDC0–0xFDFD 0:0:1 0xFC00–0xFFFF 1024 bytes 0xFBC0–0xFBFD 0:1:0 0xF800–0xFFFF 2048 bytes 0xF7C0–0xF7FD 0:1:1 0xF000–0xFFFF 4096 bytes 0xEFC0–0xEFFD 1:0:0 0xE000–0xFFFF 8192 bytes 0xDFC0–0xDFFD 1:0:1 0xC000–0xFFFF 16384 bytes 0xBFC0–0xBFFD3 1:1:0 0x8000–0xFFFF 32768 bytes 0x7FC0–0x7FFD4 1:1:1 0x182C–0xFFFF 59,348 bytes No redirection allowed 1 No redirection if FPOPEN=0, or FNORED=1. 2 Reset vector is not redirected. 3 32K and 60K devices only. 4 60K devices only. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 61

Chapter4 Memory 4.6.5 Flash Status Register (FSTAT) Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits that can be read at any time. Writes to these bits have special meanings that are discussed in the bit descriptions. 7 6 5 4 3 2 1 0 R FCCF 0 FBLANK 0 0 FCBEF FPVIOL FACCERR W Reset 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure4-8. Flash Status Register (FSTAT) Table4-12. FSTAT Field Descriptions Field Description 7 Flash Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the FCBEF command buffer is empty so that a new command sequence can be executed when performing burst programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. Only burst program commands can be buffered. 0 Command buffer is full (not ready for additional commands). 1 A new burst program command may be written to the command buffer. 6 Flash Command Complete Flag — FCCF is set automatically when the command buffer is empty and no FCCF command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to register a command). Writing to FCCF has no meaning or effect. 0 Command in progress 1 All commands complete 5 Protection Violation Flag — FPVIOL is set automatically when FCBEF is cleared to register a command that FPVIOL attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing a 1 to FPVIOL. 0 No protection violation. 1 An attempt was made to erase or program a protected location. 4 Access Error Flag — FACCERR is set automatically when the proper command sequence is not followed FACCERR exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussion of the exact actions that are considered access errors, see Section4.4.5, “Access Errors.” FACCERR is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect. 0 No access error has occurred. 1 An access error has occurred. 2 Flash Verified as All Blank (Erased) Flag — FBLANK is set automatically at the conclusion of a blank check FBLANK command if the entire flash array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a new valid command. Writing to FBLANK has no meaning or effect. 0 After a blank check command is completed and FCCF=1, FBLANK=0 indicates the flash array is not completely erased. 1 After a blank check command is completed and FCCF=1, FBLANK=1 indicates the flash array is completely erased (all 0xFF). MC9S08GB60A Data Sheet, Rev. 2 62 Freescale Semiconductor

Chapter4 Memory 4.6.6 Flash Command Register (FCMD) Only five command codes are recognized in normal user modes as shown in Table 4-14. Refer to Section4.4.3, “Program and Erase Command Execution” for a detailed discussion of flash programming and erase operations. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0 Reset 0 0 0 0 0 0 0 0 Figure4-9. Flash Command Register (FCMD) Table4-13. FCMD Field Descriptions Field Description 7:0 See Table4-14 for a description of FCMD[7:0]. FCMD[7:0] Table4-14. Flash Commands Command FCMD Equate File Label Blank check 0x05 mBlank Byte program 0x20 mByteProg Byte program — burst mode 0x25 mBurstProg Page erase (512 bytes/page) 0x40 mPageErase Mass erase (all flash) 0x41 mMassErase All other command codes are illegal and generate an access error. It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 63

Chapter4 Memory MC9S08GB60A Data Sheet, Rev. 2 64 Freescale Semiconductor

Chapter 5 Resets, Interrupts, and System Configuration 5.1 Introduction This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08GBxxA/GTxxA. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data manual. This section gathers basic information about all reset and interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral systems with their own sections but are part of the system control logic. 5.2 Features Reset and interrupt features include: • Multiple sources of reset for flexible system configuration and reliable operation: — Power-on detection (POR) — Low voltage detection (LVD) with enable — External RESET pin with enable — COP watchdog with enable and two timeout choices — Illegal opcode — Serial command from a background debug host • Reset status register (SRS) to indicate source of most recent reset • Separate interrupt vectors for each module (reduces polling overhead) (see Table5-1) 5.3 MCU Reset Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially configured as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the condition code register (CCR) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset. The MC9S08GBxxA/GTxxA has seven sources for reset: • Power-on reset (POR) • Low-voltage detect (LVD) • Computer operating properly (COP) timer MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 65

Chapter5 Resets, Interrupts, and System Configuration • Illegal opcode detect • Background debug forced reset • The reset pin (RESET) • Clock generator loss of lock and loss of clock reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register. Whenever the MCU enters reset, the internal clock generator (ICG) module switches to self-clocked mode with the frequency of f selected. The reset pin is driven low for 34 Self_reset internal bus cycles where the internal bus frequency is half the ICG frequency. After the 34 cycles are completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low externally. After the pin is released, it is sampled after another 38 cycles to determine whether the reset pin is the cause of the MCU reset. 5.4 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP timer periodically. If the application program gets lost and fails to reset the COP before it times out, a system reset is generated to force the system back to a known starting point. The COP watchdog is enabled by the COPE bit in SOPT (see Section 5.8.4, “System Options Register (SOPT)” for additional information). The COP timer is reset by writing any value to the address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a reset signal to the COP timer. After any reset, the COP timer is enabled. This provides a reliable way to detect code that is not executing as intended. If the COP watchdog is not used in an application, it can be disabled by clearing the COPE bit in the write-once SOPT register. Also, the COPT bit can be used to choose one of two timeout periods (218 or 213 cycles of the bus rate clock). Even if the application will use the reset default settings in COPE and COPT, the user should still write to write-once SOPT during reset initialization to lock in the settings. That way, they cannot be changed accidentally if the application program gets lost. The write to SRS that services (clears) the COP timer should not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails. When the MCU is in active background mode, the COP timer is temporarily disabled. 5.5 Interrupts Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI under certain circumstances. If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The CPU will not respond until and unless the local interrupt enable is set to 1 to enable the interrupt. The I bit MC9S08GB60A Data Sheet, Rev. 2 66 Freescale Semiconductor

Chapter5 Resets, Interrupts, and System Configuration in the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and performs other system setup before clearing the I bit to allow the CPU to respond to interrupts. When the CPU receives a qualified interrupt request, it completes the current instruction before responding to the interrupt. The interrupt sequence follows the same cycle-by-cycle sequence as the SWI instruction and consists of: • Saving the CPU registers on the stack • Setting the I bit in the CCR to mask further interrupts • Fetching the interrupt vector for the highest-priority interrupt that is currently pending • Filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0 when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit may be cleared inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difficult to debug. The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR, A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the stack. NOTE For compatibility with the M68HC08, the H register is not automatically saved and restored. It is good programming practice to push H onto the stack at the start of the interrupt service routine (ISR) and restore it just before the RTI that is used to return from the ISR. When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced first (see Table 5-1). 5.5.1 Interrupt Stack Frame Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP) points at the next available byte location on the stack. The current values of CPU registers are stored on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After stacking, the SP points at the next available location on the stack which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 67

Chapter5 Resets, Interrupts, and System Configuration UNSTACKING TOWARD LOWER ADDRESSES ORDER ² 7 0 SP AFTER INTERRUPT STACKING 5 1 CONDITION CODE REGISTER 4 2 ACCUMULATOR 3 3 INDEX REGISTER (LOW BYTE X)* 2 4 PROGRAM COUNTER HIGH SP BEFORE 1 5 PROGRAM COUNTER LOW THE INTERRUPT ² ² STACKING TOWARD HIGHER ADDRESSES ORDER ² * High byte (H) of index register is not automatically stacked. Figure5-1. Interrupt Stack Frame When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information, starting from the PC address just recovered from the stack. The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR. Typically, the flag should be cleared at the beginning of the ISR so that if another interrupt is generated by this same source, it will be registered so it can be serviced after completion of the current ISR. 5.5.2 External Interrupt Request (IRQ) Pin External interrupts are managed by the IRQSC status and control register. When the IRQ function is enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled) can wake the MCU. 5.5.2.1 Pin Configuration Options The IRQ pin enable (IRQPE) control bit in the IRQSC register must be 1 for the IRQ pin to act as the interrupt request (IRQ) input. When the pin is configured as an IRQ input, the user can choose the polarity of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event causes an interrupt or only sets the IRQF flag (which can be polled by software). When the IRQ pin is configured to detect rising edges, an optional pulldown resistor is available rather than a pullup resistor. BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act as the IRQ input. NOTE The voltage measured on the pulled up IRQ pin may be as low as V – 0.7 DD V. The internal gates connected to this pin are pulled all the way to V . All DD other pins with enabled pullup resistors will have an unloaded measurement of V . DD MC9S08GB60A Data Sheet, Rev. 2 68 Freescale Semiconductor

Chapter5 Resets, Interrupts, and System Configuration 5.5.2.2 Edge and Level Sensitivity The IRQMOD control bit re-configures the detection logic so it detects edge events and pin levels. In this edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the IRQ pin remains at the asserted level. 5.5.3 Interrupt Vectors, Sources, and Local Masks Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the bottom of the table. The high-order byte of the address for the interrupt service routine is located at the first address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address. When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 69

Chapter5 Resets, Interrupts, and System Configuration Table5-1. Vector Summary Vector Vector Address Vector Name Module Source Enable Description Priority Number (High/Low) 26 0xFFC0/FFC1 Unused Vector Space through through (available for user program) Lower 31 0xFFCA/FFCB 25 0xFFCC/FFCD Vrti System RTIF RTIE Real-time interrupt control 24 0xFFCE/FFCF Viic1 IIC IICIS IICIE IIC control 23 0xFFD0/FFD1 Vatd1 ATD COCO AIEN AD conversion complete 22 0xFFD2/FFD3 Vkeyboard1 KBI KBF KBIE Keyboard pins 21 0xFFD4/FFD5 Vsci2tx SCI2 TDRE TIE SCI2 transmit TC TCIE 20 0xFFD6/FFD7 Vsci2rx SCI2 IDLE ILIE SCI2 receive RDRF RIE 19 0xFFD8/FFD9 Vsci2err SCI2 OR ORIE SCI2 error NF NFIE FE FEIE PF PFIE 18 0xFFDA/FFDB Vsci1tx SCI1 TDRE TIE SCI1 transmit TC TCIE 17 0xFFDC/FFDD Vsci1rx SCI1 IDLE ILIE SCI1 receive RDRF RIE 16 0xFFDE/FFDF Vsci1err SCI1 OR ORIE SCI1 error NF NFIE FE FEIE PF PFIE 15 0xFFE0/FFE1 Vspi1 SPI SPIF SPIE SPI MODF SPIE SPTEF SPTIE 14 0xFFE2/FFE3 Vtpm2ovf TPM2 TOF TOIE TPM2 overflow 13 0xFFE4/FFE5 Vtpm2ch4 TPM2 CH4F CH4IE TPM2 channel 4 12 0xFFE6/FFE7 Vtpm2ch3 TPM2 CH3F CH3IE TPM2 channel 3 11 0xFFE8/FFE9 Vtpm2ch2 TPM2 CH2F CH2IE TPM2 channel 2 10 0xFFEA/FFEB Vtpm2ch1 TPM2 CH1F CH1IE TPM2 channel 1 9 0xFFEC/FFED Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0 8 0xFFEE/FFEF Vtpm1ovf TPM1 TOF TOIE TPM1 overflow 7 0xFFF0/FFF1 Vtpm1ch2 TPM1 CH2F CH2IE TPM1 channel 2 6 0xFFF2/FFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1 5 0xFFF4/FFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0 4 0xFFF6/FFF7 Vicg ICG ICGIF LOLRE/LOCRE ICG (LOLS/LOCS) 3 0xFFF8/FFF9 Vlvd System LVDF LVDIE Low-voltage detect control 2 0xFFFA/FFFB Virq IRQ IRQF IRQIE IRQ pin 1 0xFFFC/FFFD Vswi Core SWI — Software interrupt Instruction 0 0xFFFE/FFFF Vreset System COP COPE Watchdog timer control LVD LVDRE Low-voltage detect Higher RESET pin — External pin Illegal opcode — Illegal opcode MC9S08GB60A Data Sheet, Rev. 2 70 Freescale Semiconductor

Chapter5 Resets, Interrupts, and System Configuration 5.6 Low-Voltage Detect (LVD) System The MC9S08GBxxA/GTxxA includes a system to protect against low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system comprises a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (V ) LVDH or low (V ). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip voltage is selected LVDL by LVDV in SPMSC2. The LVD is disabled upon entering any of the stop modes unless the LVDSE bit is set. If LVDSE and LVDE are both set, then the MCU cannot enter stop1 or stop2, and the current consumption in stop3 with the LVD enabled will be greater. 5.6.1 Power-On Reset Operation When power is initially applied to the MCU, or when the supply voltage drops below the V level, the POR POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in reset until the supply has risen above the V level. Both the POR bit and the LVD bit in SRS are set LVDL following a POR. 5.6.2 LVD Reset Operation The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following either an LVD reset or POR. 5.6.3 LVD Interrupt Operation When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE set, LVDIE set, and LVDRE clear), then LVDF will be set and an LVD interrupt will occur. 5.6.4 Low-Voltage Warning (LVW) The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is approaching, but is still above, the LVD voltage. The LVW does not have an interrupt associated with it. There are two user selectable trip voltages for the LVW, one high (V ) and one low (V ). The trip LVWH LVWL voltage is selected by LVWV in SPMSC2. 5.7 Real-Time Interrupt (RTI) The real-time interrupt function can be used to generate periodic interrupts based on a multiple of the source clock's period. The RTI has two source clock choices, the external clock input (ICGERCLK) to the ICG or the RTI's own internal clock. The RTI can be used in run, wait, stop2 and stop3 modes. It is not available in stop1 mode. In run and wait modes, only the external clock can be used as the RTI's clock source. In stop2 mode, only the internal RTI clock can be used. In stop3, either the external clock or internal RTI clock can be used. When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 71

Chapter5 Resets, Interrupts, and System Configuration configured for low bandwidth operation (RANGE = 0). If active BDM mode is enabled in stop3, the internal RTI clock is not available. The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control value (RTIS2:RTIS1:RTIS0) used to select one of seven RTI periods. The RTI has a local interrupt enable, RTIE, to allow masking of the real-time interrupt. The module can be disabled by writing 0:0:0 to RTIS2:RTIS1:RTIS0 in which case the clock source input is disabled and no interrupts will be generated. See Section5.8.6, “System Real-Time Interrupt Status and Control Register (SRTISC),” for detailed information about this register. 5.8 Reset, Interrupt, and System Control Registers and Control Bits One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems. Refer to the direct-page register summary in Chapter4, “Memory” of this data sheet for the absolute address assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of Operation.” MC9S08GB60A Data Sheet, Rev. 2 72 Freescale Semiconductor

Chapter5 Resets, Interrupts, and System Configuration 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) This direct page register includes two unimplemented bits which always read 0, four read/write bits, one read-only status bit, and one write-only bit. These bits are used to configure the IRQ function, report status, and acknowledge IRQ events. 7 6 5 4 3 2 1 0 R 0 0 IRQF 0 IRQEDG IRQPE IRQIE IRQMOD W IRQACK Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure5-2. Interrupt Request Status and Control Register (IRQSC) Table5-2. IRQSC Field Descriptions Field Description 5 Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or IRQEDG levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured to detect rising edges, the optional pullup resistor is re-configured as an optional pulldown resistor. 0 IRQ is falling edge or falling edge/low-level sensitive. 1 IRQ is rising edge or rising edge/high-level sensitive. 4 IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can IRQPE be used as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down resistor is enabled depending on the state of the IRQMOD bit. 0 IRQ pin function is disabled. 1 IRQ pin function is enabled. 3 IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred. IRQF 0 No IRQ request. 1 IRQ event detected. 2 IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF). IRQACK Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD=1), IRQF cannot be cleared while the IRQ pin remains at its asserted level. 1 IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate a hardware IRQIE interrupt request. 0 Hardware interrupt requests from IRQF disabled (use polling). 1 Hardware interrupt requested whenever IRQF=1. 0 IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level IRQMOD detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. See Section5.5.2.2, “Edge and Level Sensitivity” for more details. 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 73

Chapter5 Resets, Interrupts, and System Configuration 5.8.2 System Reset Status Register (SRS) This register includes six read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset. 7 6 5 4 3 2 1 0 R POR PIN COP ILOP 0 ICG LVD 0 W Writing any value to SIMRS address clears COP watchdog timer. Power-on 1 0 0 0 0 0 1 0 reset: Low-voltage U 0 0 0 0 0 1 0 reset: Any other 0 Note(1) Note(1) Note(1) 0 Note(1) 0 0 reset: U = Unaffected by reset 1 Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset will be cleared. Figure5-3. System Reset Status (SRS) Table5-3. SRS Field Descriptions Field Description 7 Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was POR ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. 0 Reset not caused by POR. 1 POR caused reset. 6 External Reset Pin — Reset was caused by an active-low level on the external reset pin. PIN 0 Reset not caused by external reset pin. 1 Reset came from external reset pin. 5 Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out. COP This reset source may be blocked by COPE=0. 0 Reset not caused by COP timeout. 1 Reset caused by COP timeout. 4 Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP ILOP instruction is considered illegal if stop is disabled by STOPE=0 in the SOPT register. The BGND instruction is considered illegal if active background mode is disabled by ENBDM=0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode. MC9S08GB60A Data Sheet, Rev. 2 74 Freescale Semiconductor

Chapter5 Resets, Interrupts, and System Configuration Table5-3. SRS Field Descriptions (continued) Field Description 2 Internal Clock Generation Module Reset — Reset was caused by an ICG module reset. ICG 0 Reset not caused by ICG module. 1 Reset caused by ICG module. 1 Low Voltage Detect — If the LVD reset is enabled (LVDE = LVDRE = 1) and the supply drops below the LVD trip LVD voltage, an LVD reset occurs. The LVD function is disabled when the MCU enters stop. To maintain LVD operation in stop, the LVDSE bit must be set. 0 Reset not caused by LVD trip or POR. 1 Reset caused by LVD trip or POR. 5.8.3 System Background Debug Force Reset Register (SBDFR) This register contains a single write-only control bit. A serial background command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W BDFR1 Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background debug commands, not from user programs. Figure5-4. System Background Debug Force Reset Register (SBDFR) Table5-4. SBDFR Field Descriptions Field Description 0 Background Debug Force Reset — A serial background mode command such as WRITE_BYTE allows an BDFR external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 75

Chapter5 Resets, Interrupts, and System Configuration 5.8.4 System Options Register (SOPT) This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT should be written during the user’s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. 7 6 5 4 3 2 1 0 R 0 0 COPE COPT STOPE BKGDPE W Reset 1 1 0 1 0 0 1 1 = Unimplemented or Reserved Figure5-5. System Options Register (SOPT) Table5-5. SOPT Field Descriptions Field Description 7 COP Watchdog Enable — This write-once bit defaults to 1 after reset. COPE 0 COP watchdog timer disabled. 1 COP watchdog timer enabled (force reset on timeout). 6 COP Watchdog Timeout — This write-once bit defaults to 1 after reset. COPT 0 Short timeout period selected (213 cycles of BUSCLK). 1 Long timeout period selected (218 cycles of BUSCLK). 5 Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is STOPE disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced. 0 Stop mode disabled. 1 Stop mode enabled. 1 Background Debug Mode Pin Enable — The BKGDPE bit enables the PTG0/BKGD/MS pin to function as BKGDPE BKGD/MS. When the bit is clear, the pin will function as PTG0, which is an output-only general-purpose I/O. This pin always defaults to BKGD/MS function after any reset. 0 BKGD pin disabled. 1 BKGD pin enabled. MC9S08GB60A Data Sheet, Rev. 2 76 Freescale Semiconductor

Chapter5 Resets, Interrupts, and System Configuration 5.8.5 System Device Identification Register (SDIDH, SDIDL) This read-only register is included so host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU. 7 6 5 4 3 2 1 0 R REV3 REV2 REV1 REV0 ID11 ID10 ID9 ID8 W Reset 01 0(1) 0(1) 0(1) 0 0 0 0 = Unimplemented or Reserved 1 The revision number that is hard coded into these bits reflects the current silicon revision level. Figure5-6. System Device Identification Register High (SDIDH) Table5-6. SDIDH Field Descriptions Field Description 7:4 Revision Number — The high-order 4 bits of address 0x1806 are hard coded to reflect the current mask set REV[3:0] revision number (0–F). 3:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[11:8] MC9S08GBxxA/GTxxA is hard coded to the value 0x002. See also ID bits in Table5-7. 7 6 5 4 3 2 1 0 R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 W Reset 0 0 0 0 0 0 1 0 = Unimplemented or Reserved Figure5-7. System Device Identification Register Low (SDIDL) Table5-7. SDIDL Field Descriptions Field Description 3:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08GBxxA/GTxxA is hard coded to the value 0x002. See also ID bits in Table5-6. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 77

Chapter5 Resets, Interrupts, and System Configuration 5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC) This register contains one read-only status flag, one write-only acknowledge bit, three read/write delay selects, and three unimplemented bits, which always read 0. 7 6 5 4 3 2 1 0 R RTIF 0 0 RTICLKS RTIE RTIS2 RTIS1 RTIS0 W RTIACK Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure5-8. System RTI Status and Control Register (SRTISC) Table5-8. SRTISC Field Descriptions Field Description 7 Real-Time Interrupt Flag — This read-only status bit indicates the periodic wakeup timer has timed out. RTIF 0 Periodic wakeup timer not timed out. 1 Periodic wakeup timer timed out. 6 Real-Time Interrupt Acknowledge — This write-only bit is used to acknowledge real-time interrupt request RTIACK (write 1 to clear RTIF). Writing 0 has no meaning or effect. Reads always return 0. 5 Real-Time Interrupt Clock Select — This read/write bit selects the clock source for the real-time interrupt. RTICLKS 0 Real-time interrupt request clock source is internal oscillator. 1 Real-time interrupt request clock source is external clock. 4 Real-Time Interrupt Enable — This read-write bit enables real-time interrupts. RTIE 0 Real-time interrupts disabled. 1 Real-time interrupts enabled. 2:0 Real-Time Interrupt Period Selects — These read/write bits select the wakeup period for the RTI. One clock RTIS[2:0] source for the real-time interrupt is its own internal clock source, which oscillates with a period of approximately t and is independent of other MCU clock sources. Using an external clock source the delays will be crystal RTI frequency divided by value in RTIS2:RTIS1:RTIS0. See Table5-9. Table5-9. Real-Time Interrupt Period Internal Clock Source 1 External Clock Source 2 RTIS2:RTIS1:RTIS0 (t = 1 ms, Nominal) Period = t RTI ext 0:0:0 Disable periodic wakeup timer Disable periodic wakeup timer 0:0:1 8 ms text x 256 0:1:0 32 ms tex x 1024 0:1:1 64 ms tex x 2048 1:0:0 128 ms tex x 4096 1:0:1 256 ms text x 8192 1:1:0 512 ms text x 16384 1:1:1 1.024 s tex x 32768 1 See TableA-10t in AppendixA, “Electrical Characteristics,” for the tolerance on these values. RTI 2 t is based on the external clock source, resonator, or crystal selected by the ICG configuration. See TableA-9 for details. ext MC9S08GB60A Data Sheet, Rev. 2 78 Freescale Semiconductor

Chapter5 Resets, Interrupts, and System Configuration 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) 7 6 5 4 3 2 1 0 R LVDF 0 0 0 LVDIE LVDRE1 LVDSE(1) LVDE(1) W LVDACK Reset 0 0 0 1 1 1 0 0 = Unimplemented or Reserved 1 This bit can be written only one time after reset. Additional writes are ignored. Figure5-9. System Power Management Status and Control 1 Register (SPMSC1) Table5-10. SPMSC1 Field Descriptions Field Description 7 Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event. LVDF 6 Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors LVDACK (write 1 to clear LVDF). Reads always return 0. 5 Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF. LVDIE 0 Hardware interrupt disabled (use polling). 1 Request a hardware interrupt when LVDF = 1. 4 Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset LVDRE (provided LVDE = 1). 0 LVDF does not generate hardware resets. 1 Force an MCU reset when LVDF = 1. 3 Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage LVDSE detect function operates when the MCU is in stop mode. 0 Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode. 2 Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation LVDE of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 79

Chapter5 Resets, Interrupts, and System Configuration 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) This register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the MCU. 7 6 5 4 3 2 1 0 R LVWF 0 PPDF 0 LVDV LVWV PDC PPDC W LVWACK PPDACK Power-on 0(1) 0 0 0 0 0 0 0 reset: LVD reset: 0(1) 0 U U 0 0 0 0 Any other 0(1) 0 U U 0 0 0 0 reset: = Unimplemented or Reserved U = Unaffected by reset 1 LVWF will be set in the case when V transitions below the trip point or after reset and V is already below V . Supply Supply LVW Figure5-10. System Power Management Status and Control 2 Register (SPMSC2) Table5-11. SPMSC2 Field Descriptions Field Description 7 Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status. LVWF 0 Low voltage warning not present. 1 Low voltage warning is present or was present. 6 Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge. Writing a 1 LVWACK to LVWACK clears LVWF to 0 if a low voltage warning is not present. 5 Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V ). LVD LVDV 0 Low trip point selected (V = V ). LVD LVDL 1 High trip point selected (V = V ). LVD LVDH 4 Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V ). LVW LVWV 0 Low trip point selected (V = V ). LVW LVWL 1 High trip point selected (V = V ). LVW LVWH 3 Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode. PPDF 0 Not stop2 mode recovery. 1 Stop2 mode recovery. 2 Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit. PPDACK 1 Power Down Control — The write-once PDC bit controls entry into the power down (stop2 and stop1) modes. PDC 0 Power down modes are disabled. 1 Power down modes are enabled. 0 Partial Power Down Control — The write-once PPDC bit controls which power down mode, stop1 or stop2, is PPDC selected. 0 Stop1, full power down, mode enabled if PDC set. 1 Stop2, partial power down, mode enabled if PDC set. MC9S08GB60A Data Sheet, Rev. 2 80 Freescale Semiconductor

Chapter 6 Parallel Input/Output 6.1 Introduction This section explains software controls related to parallel input/output (I/O). The MC9S08GBxxA has seven I/O ports which include a total of 56 general-purpose I/O pins (one of these pins is output only). The MC9S08GTxxA has six I/O ports which include a total of up to 39 general-purpose I/O pins (one pin, PTG0, is output only). See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins. Many of these pins are shared with on-chip peripherals such as timer systems, external interrupts, or keyboard interrupts. When these other modules are not controlling the port pins, they revert to general-purpose I/O control. For each I/O pin, a port data bit provides access to input (read) and output (write) data, a data direction bit controls the direction of the pin, and a pullup enable bit enables an internal pullup device (provided the pin is configured as an input), and a slew rate control bit controls the rise and fall times of the pins. NOTE Not all general-purpose I/O pins are available on all packages. To avoid extra current drain from floating input pins, the user’s reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unconnected pins to outputs so the pins do not float. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 81

Chapter6 Parallel Input/Output HCS08 CORE DEBUG MODULE (DBG) A CPU BDC 8 RT 8 PTA7/KBI1P7– 8-BIT KEYBOARD PO PTA0/KBI1P0 INTERRUPT MODULE (KBI1) HCS08 SYSTEM CONTROL B RESET RESETS AND INTERRUPTS CANOANLVOEG(RA-TTTEDOR1-D )(1IG0-ITBAITL) 8 PORT 8 PPTTBB07//AADD11PP07– MODES OF OPERATION POWER MANAGEMENT PTC7 PTC6 RTI COP PTC5 C IRQ IRQ LVD IIC MODULE SCL1 RT PTC4 (IIC1) O PTC3/SCL1 SDA1 P PTC2/SDA1 SCL1 PTC1/RxD2 SERIAL COMMUNICATIONS SCL1 PTC0/TxD2 INTERFACE MODULE USER FLASH (SCI2) PTD7/TPM2CH4 (Gx60A = 61,268 BYTES) PTD6/TPM2CH3 (Gx32A = 32,768 BYTES) 5-CHANNMEOLD TUILMEER/PWM 5 T D PPTTDD45//TTPPMM22CCHH12 R PTD3/TPM2CH0 (TPM2) O 3 P PTD2/TPM1CH2 USER RAM PTD1/TPM1CH1 3-CHANNEL TIMER/PWM (Gx60A = 4096 BYTES) PTD0/TPM1CH0 MODULE (Gx32A = 2048 BYTES) (TPM1) PTE7 PTE6 SPSCK1 VVDDAD SERIAL PERIPHERAL MOSI1 T E PPTTEE45//MSPOSSCI1K1 VSRSEAFDH INTERF(ASCPEI1 M)ODULE MSSIS1O1 POR PTE3/MISO1 V PTE2/SS1 REFL RxD1 PTE1/RxD1 SERIAL COMMUNICATIONS TxD1 VDD VOLTAGE INTERFACE MODULE PTE0/TxD1 (SCI1) V REGULATOR SS T F 8 R PTF7–PTF0 O P 4 PTG7–PTG4 INTERNAL CLOCK PTG3 GENERATOR EXTAL G PTG2/EXTAL (ICG) XTAL T R PTG1/XTAL BKGD O P PTG0/BKGD/MS LOW-POWER OSCILLATOR Note: Not all pins are bonded out in all packages. See Table2-2 for complete details. Block Diagram Symbol Key: = Not connected in 48-, 44-, and 42-pin packages = Not connected in 44- and 42-pin packages = Not connected in 42-pin packages Figure6-1. Block Diagram Highlighting Parallel Input/Output Pins MC9S08GB60A Data Sheet, Rev. 2 82 Freescale Semiconductor

Chapter6 Parallel Input/Output 6.2 Features Parallel I/O features, depending on package choice, include: • A total of 56 general-purpose I/O pins in seven ports (PTG0 is output only) • High-current drivers on port C and port F pins • Hysteresis input buffers • Software-controlled pullups on each input pin • Software-controlled slew rate output buffers • Eight port A pins shared with KBI1 • Eight port B pins shared with ATD1 • Eight high-current port C pins shared with SCI2 and IIC1 • Eight port D pins shared with TPM1 and TPM2 • Eight port E pins shared with SCI1 and SPI1 • Eight high-current port F pins • Eight port G pins shared with EXTAL, XTAL, and BKGD/MS 6.3 Pin Descriptions The MC9S08GBxxA/GTxxA has a total of 56 parallel I/O pins (one is output only) in seven 8-bit ports (PTA–PTG). Not all pins are bonded out in all packages. Consult the pin assignment in Chapter2, “Pins and Connections,” for available parallel I/O pins. All of these pins are available for general-purpose I/O when they are not used by other on-chip peripheral systems. After reset, BKGD/MS is enabled and therefore is not usable as an output pin until BKGDPE in SOPT is cleared. The rest of the peripheral functions are disabled. After reset, all data direction and pullup enable controls are set to 0s. These pins default to being high-impedance inputs with on-chip pullup devices disabled. The following paragraphs discuss each port and the software controls that determine each pin’s use. 6.3.1 Port A and Keyboard Interrupts Port A Bit 7 6 5 4 3 2 1 Bit 0 PTA7/ PTA6/ PTA5/ PTA4/ PTA3/ PTA2/ PTA1/ PTA0/ MCU Pin: KBI1P7 KBI1P6 KBI1P5 KBI1P4 KBI1P3 KBI1P2 KBI1P1 KBI1P0 Figure6-2. Port A Pin Names Port A is an 8-bit port shared among the KBI keyboard interrupt inputs and general-purpose I/O. Any pins enabled as KBI inputs will be forced to act as inputs. Port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD), data direction (PTADD), pullup enable (PTAPE), and slew rate control (PTASE) registers. Refer to Section 6.4, “Parallel I/O Controls,” for more information about general-purpose I/O control. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 83

Chapter6 Parallel Input/Output Port A can be configured to be keyboard interrupt input pins. Refer to Chapter9, “Keyboard Interrupt (S08KBIV1),” for more information about using portA pins as keyboard interrupts pins. 6.3.2 Port B and Analog to Digital Converter Inputs j Port B Bit 7 6 5 4 3 2 1 Bit 0 PTB7/ PTB6/ PTB5/ PTB4/ PTB3/ PTB2/ PTB1/ PTB0/ MCU Pin: AD1P7 AD1P6 AD1P5 AD1P4 AD1P3 AD1P2 AD1P1 AD1P0 Figure6-3. Port B Pin Names Port B is an 8-bit port shared among the ATD inputs and general-purpose I/O. Any pin enabled as an ATD input will be forced to act as an input. Port B pins are available as general-purpose I/O pins controlled by the port B data (PTBD), data direction (PTBDD), pullup enable (PTBPE), and slew rate control (PTBSE) registers. Refer to Section 6.4, “Parallel I/O Controls,” for more information about general-purpose I/O control. When the ATD module is enabled, analog pin enables are used to specify which pins on port B will be used as ATD inputs. Refer to Chapter 14, “Analog-to-Digital Converter (S08ATDV3),” for more information about using port B pins as ATD pins. 6.3.3 Port C and SCI2, IIC, and High-Current Drivers Port C Bit 7 6 5 3 3 2 1 Bit 0 PTC3/ PTC2/ PTC1/ PTC0/ MCU Pin: PTC7 PTC6 PTC5 PTC4 SCL1 SDA1 RxD2 TxD2 Figure6-4. Port C Pin Names Port C is an 8-bit port which is shared among the SCI2 and IIC1 modules, and general-purpose I/O. When SCI2 or IIC1 modules are enabled, the pin direction will be controlled by the module or function. Port C has high current output drivers. Port C pins are available as general-purpose I/O pins controlled by the port C data (PTCD), data direction (PTCDD), pullup enable (PTCPE), and slew rate control (PTCSE) registers. Refer to Section 6.4, “Parallel I/O Controls,” for more information about general-purpose I/O control. When the SCI2 module is enabled, PTC0 serves as the SCI2 module’s transmit pin (TxD2) and PTC1 serves as the receive pin (RxD2). Refer to Chapter 11, “Serial Communications Interface (S08SCIV1),” for more information about using PTC0 and PTC1 as SCI pins When the IIC module is enabled, PTC2 serves as the IIC modules’s serial data input/output pin (SDA1) and PTC3 serves as the clock pin (SCL1). Refer to Chapter 13, “Inter-Integrated Circuit (S08IICV1),” for more information about using PTC2 and PTC3 as IIC pins. MC9S08GB60A Data Sheet, Rev. 2 84 Freescale Semiconductor

Chapter6 Parallel Input/Output 6.3.4 Port D, TPM1 and TPM2 Port D Bit 7 6 5 4 3 2 1 Bit 0 PTD7/ PTD6/ PTD5/ PTD4/ PTD3/ PTD2/ PTD1/ PTD0/ MCU Pin: TPM2CH4 TPM2CH3 TPM2CH2 TPM2CH1 TPM2CH0 TPM1CH2 TPM1CH1 TPM1CH0 Figure6-5. Port D Pin Names Port D is an 8-bit port shared with the two TPM modules, TPM1 and TPM2, and general-purpose I/O. When the TPM1 or TPM2 modules are enabled in output compare or input capture modes of operation, the pin direction will be controlled by the module function. Port D pins are available as general-purpose I/O pins controlled by the port D data (PTDD), data direction (PTDDD), pullup enable (PTDPE), and slew rate control (PTDSE) registers. Refer to Section6.4, “Parallel I/O Controls” for more information about general-purpose I/O control. The TPM2 module can be configured to use PTD7–PTD3 as either input capture, output compare, PWM, or external clock input pins (PTD3 only). Refer to Chapter 10, “Timer/PWM (S08TPMV1)” for more information about using PTD7–PTD3 as timer pins. The TPM1 module can be configured to use PTD2–PTD0 as either input capture, output compare, PWM, or external clock input pins (PTD0 only). Refer to Chapter 10, “Timer/PWM (S08TPMV1)” for more information about using PTD2–PTD0 as timer pins. 6.3.5 Port E, SCI1, and SPI Port E Bit 7 6 5 4 3 2 1 Bit 0 PTE5/ PTE4/ PTE3/ PTE2/ PTE1/ PTE0/ MCU Pin: PTE7 PTE6 SPSCK1 MOSI1 MISO1 SS1 RxD1 TxD1 Figure6-6. Port E Pin Names Port E is an 8-bit port shared with the SCI1 module, SPI1 module, and general-purpose I/O. When the SCI or SPI modules are enabled, the pin direction will be controlled by the module function. Port E pins are available as general-purpose I/O pins controlled by the port E data (PTED), data direction (PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers. Refer to Section6.4, “Parallel I/O Controls” for more information about general-purpose I/O control. When the SCI1 module is enabled, PTE0 serves as the SCI1 module’s transmit pin (TxD1) and PTE1 serves as the receive pin (RxD1). Refer to Chapter11, “Serial Communications Interface (S08SCIV1)” for more information about using PTE0 and PTE1 as SCI pins. When the SPI module is enabled, PTE2 serves as the SPI module’s slave select pin (SS1), PTE3 serves as the master-in slave-out pin (MISO1), PTE4 serves as the master-out slave-in pin (MOSI1), and PTE5 serves as the SPI clock pin (SPSCK1). Refer to Chapter 12, “Serial Peripheral Interface (S08SPIV3) for more information about using PTE5–PTE2 as SPI pins. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 85

Chapter6 Parallel Input/Output 6.3.6 Port F and High-Current Drivers Port F Bit 7 6 5 4 3 2 1 Bit 0 MCU Pin: PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 Figure6-7. Port F Pin Names Port F is an 8-bit port general-purpose I/O that is not shared with any peripheral module. Port F has high current output drivers. Port F pins are available as general-purpose I/O pins controlled by the port F data (PTFD), data direction (PTFDD), pullup enable (PTFPE), and slew rate control (PTFSE) registers. Refer to Section6.4, “Parallel I/O Controls” for more information about general-purpose I/O control. 6.3.7 Port G, BKGD/MS, and Oscillator Port G Bit 7 6 5 4 3 2 1 Bit 0 PTG2/ PTG1/ PTG0/ MCU Pin: PTG7 PTG6 PTG5 PTG4 PTG3 EXTAL XTAL BKGD/MS Figure6-8. Port G Pin Names Port G is an 8-bit port which is shared among the background/mode select function, oscillator, and general-purpose I/O. When the background/mode select function or oscillator is enabled, the pin direction will be controlled by the module function. Port G pins are available as general-purpose I/O pins controlled by the port G data (PTGD), data direction (PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers. Refer to Section6.4, “Parallel I/O Controls” for more information about general-purpose I/O control. The internal pullup for PTG0 is enabled when the background/mode select function is enabled, regardless of the state of PTGPE0. During reset, the BKGD/MS pin functions as a mode select pin. After the MCU is out of reset, the BKGD/MS pin becomes the background communications input/output pin. The PTG0 can be configured to be a general-purpose output pin. Refer to Chapter3, “Modes of Operation”, Chapter 5, “Resets, Interrupts, and System Configuration”, and Chapter15, “Development Support” for more information about using this pin. The ICG module can be configured to use PTG2–PTG1 ports as crystal oscillator or external clock pins. Refer to Chapter13, “Inter-Integrated Circuit (S08IICV1)” for more information about using these pins as oscillator pins. MC9S08GB60A Data Sheet, Rev. 2 86 Freescale Semiconductor

Chapter6 Parallel Input/Output 6.4 Parallel I/O Controls Provided no on-chip peripheral is controlling a port pin, the pins operate as general-purpose I/O pins that are accessed and controlled by a data register (PTxD), a data direction register (PTxDD), a pullup enable register (PTxPE), and a slew rate control register (PTxSE) where x is A, B, C, D, E, F, or G. Reads of the data register return the pin value (if PTxDDn= 0) or the contents of the port data register (if PTxDDn=1). Writes to the port data register are latched into the port register whether the pin is controlled by an on-chip peripheral or the pin is configured as an input. If the corresponding pin is not controlled by a peripheral and is configured as an output, this level will be driven out the port pin. 6.4.1 Data Direction Control The data direction control bits determine whether the pin output driver is enabled, and they control what is read for port data register reads. Each port pin has a data direction control bit. When PTxDDn =0, the corresponding pin is an input and reads of PTxD return the pin value. When PTxDDn= 1, the corresponding pin is an output and reads of PTxD return the last value written to the port data register. When a peripheral module or system function is in control of a port pin, the data direction control still controls what is returned for reads of the port data register, even though the peripheral system has overriding control of the actual pin direction. For the MC9S08GBxxA/GTxxA MCU, reads of PTG0/BKGD/MS will return the value on the output pin. It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. 6.4.2 Internal Pullup Control An internal pullup device can be enabled for each port pin that is configured as an input (PTxDDn= 0). The pullup device is available for a peripheral module to use, provided the peripheral is enabled and is an input function as long as the PTxDDn= 0. For the four configurable KBI module inputs on PTA7–PTA4, when a pin is configured to detect rising edges, the port pullup enable associated with the pin (PTAPEn) selects a pulldown rather than a pullup device. 6.4.3 Slew Rate Control Slew rate control can be enabled for each port pin that is configured as an output (PTxDDn= 1) or if a peripheral module is enabled and its function is an output. Not all peripheral modules’ outputs have slew rate control; refer to Chapter2, “Pins and Connections” for more information about which pins have slew rate control. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 87

Chapter6 Parallel Input/Output 6.5 Stop Modes Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An explanation of I/O behavior for the various stop modes follows: • When the MCU enters stop1 mode, all internal registers including general-purpose I/O control and data registers are powered down. All of the general-purpose I/O pins assume their reset state: output buffers and pullups turned off. Upon exit from stop1, all I/O must be initialized as if the MCU had been reset. • When the MCU enters stop2 mode, the internal registers are powered down as in stop1 but the I/O pin states are latched and held. For example, a port pin that is an output driving low continues to function as an output driving low even though its associated data direction and output data registers are powered down internally. Upon exit from stop2, the pins continue to hold their states until a 1 is written to the PPDACK bit. To avoid discontinuity in the pin state following exit from stop2, the user must restore the port control and data registers to the values they held before entering stop2. These values can be stored in RAM before entering stop2 because the RAM is maintained during stop2. • In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon recovery, normal I/O function is available to the user. 6.6 Parallel I/O Registers and Control Bits This section provides information about all registers and control bits associated with the parallel I/O ports. Refer to tables in Chapter4, “Memory” for the absolute address assignments for all parallel I/O registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 6.6.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD) Port A includes eight pins shared between general-purpose I/O and the KBI module. Port A pins used as general-purpose I/O pins are controlled by the port A data (PTAD), data direction (PTADD), pullup enable (PTAPE), and slew rate control (PTASE) registers. If the KBI takes control of a port A pin, the corresponding PTASE bit is ignored since the pin functions as an input. As long as PTADD is 0, the PTAPE controls the pullup enable for the KBI function. Reads of PTAD will return the logic value of the corresponding pin, provided PTADD is 0. MC9S08GB60A Data Sheet, Rev. 2 88 Freescale Semiconductor

Chapter6 Parallel Input/Output 7 6 5 4 3 2 1 0 R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 W Reset 0 0 0 0 0 0 0 0 Figure6-9. Port A Data Register (PTAD) Table6-1. PTAD Field Descriptions Field Description 7:0 Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A PTAD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7 6 5 4 3 2 1 0 R PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-10. Pullup Enable for Port A (PTAPE) Table6-2. PTAPE Field Descriptions Field Description 7:0 Pullup Enable for Port A Bits — For port A pins that are inputs, these read/write control bits determine whether PTAPE[7:0] internal pullup devices are enabled provided the corresponding PTADDn is 0. For port A pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. When any of bits 7 through 4 of port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits enable pulldown rather than pullup devices. 0 Internal pullup device disabled. 1 Internal pullup device enabled. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 89

Chapter6 Parallel Input/Output 7 6 5 4 3 2 1 0 R PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 W Reset 0 0 0 0 0 0 0 0 Figure6-11. Slew Rate Control Enable for Port A (PTASE) Table6-3. PTASE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port A Bits — For port A pins that are outputs, these read/write control bits PTASE[7:0] determine whether the slew rate controlled outputs are enabled. For port A pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0 W Reset 0 0 0 0 0 0 0 0 Figure6-12. Data Direction for Port A (PTADD) Table6-4. PTADD Field Descriptions Field Description 7:0 Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for PTADD[7:0] PTAD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn. MC9S08GB60A Data Sheet, Rev. 2 90 Freescale Semiconductor

Chapter6 Parallel Input/Output 6.6.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) Port B includes eight general-purpose I/O pins that share with the ATD function. Port B pins used as general-purpose I/O pins are controlled by the port B data (PTBD), data direction (PTBDD), pullup enable (PTBPE), and slew rate control (PTBSE) registers. If the ATD takes control of a port B pin, the corresponding PTBDD, PTBSE, and PTBPE bits are ignored. When a port B pin is being used as an ATD pin, reads of PTBD will return a 0 of the corresponding pin, provided PTBDD is 0. 7 6 5 4 3 2 1 0 R PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 W Reset 0 0 0 0 0 0 0 0 Figure6-13. Port B Data Register (PTBD) Table6-5. PTBD Field Descriptions Field Description 7:0 Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B PTBD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTBD to all 0s, but these 0s are not driven out on the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7 6 5 4 3 2 1 0 R PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-14. Pullup Enable for Port B (PTBPE) Table6-6. PTBPE Field Descriptions Field Description 7:0 Pullup Enable for Port B Bits — For port B pins that are inputs, these read/write control bits determine whether PTBPE[7:0] internal pullup devices are enabled. For port B pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 91

Chapter6 Parallel Input/Output 7 6 5 4 3 2 1 0 R PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 W Reset 0 0 0 0 0 0 0 0 Figure6-15. Data Direction for Port A (PTBSE) Table6-7. PTBSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port B Bits — For port B pins that are outputs, these read/write control bits PTBSE[7:0] determine whether the slew rate controlled outputs are enabled. For port B pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-16. Data Direction for Port B (PTBDD) Table6-8. PTBDD Field Descriptions Field Description 7:0 Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. MC9S08GB60A Data Sheet, Rev. 2 92 Freescale Semiconductor

Chapter6 Parallel Input/Output 6.6.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) Port C includes eight general-purpose I/O pins that share with the SCI2 and IIC modules. Port C pins used as general-purpose I/O pins are controlled by the port C data (PTCD), data direction (PTCDD), pullup enable (PTCPE), and slew rate control (PTCSE) registers. If the SCI2 takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to provide slew rate on the SCI2 transmit pin, TxD2. PTCPE can be used, provided the corresponding PTCDD bit is 0, to provide a pullup device on the SCI2 receive pin, RxD2. If the IIC takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to provide slew rate on the IIC serial data pin (SDA1), when in output mode and the IIC clock pin (SCL1). PTCPE can be used, provided the corresponding PTCDD bit is 0, to provide a pullup device on the IIC serial data pin, when in receive mode. Reads of PTCD will return the logic value of the corresponding pin, provided PTCDD is 0. 7 6 5 4 3 2 1 0 R PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 W Reset 0 0 0 0 0 0 0 0 Figure6-17. Port C Data Register (PTCD) Table6-9. PTCD Field Descriptions Field Description 7:0 Port C Data Register Bits— For port C pins that are inputs, reads return the logic level on the pin. For port C PTCD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 93

Chapter6 Parallel Input/Output 7 6 5 4 3 2 1 0 R PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-18. Pullup Enable for Port C (PTCPE) Table6-10. PTCPE Field Descriptions Field Description 7:0 Pullup Enable for Port C Bits — For port C pins that are inputs, these read/write control bits determine whether PTCPE[7:0] internal pullup devices are enabled. For port C pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. 7 6 5 4 3 2 1 0 R PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0 W Reset 0 0 0 0 0 0 0 0 Figure6-19. Slew Rate Control Enable for Port C (PTCSE) Table6-11. PTCSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port C Bits — For port C pins that are outputs, these read/write control bits PTCSE[7:0] determine whether the slew rate controlled outputs are enabled. For port B pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-20. Data Direction for Port C (PTCDD) Table6-12. PTCDD Field Descriptions Field Description 7:0 Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for PTCDD[7:0] PTCD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn. MC9S08GB60A Data Sheet, Rev. 2 94 Freescale Semiconductor

Chapter6 Parallel Input/Output 6.6.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) Port D includes eight pins shared between general-purpose I/O, TPM1, and TPM2. Port D pins used as general-purpose I/O pins are controlled by the port D data (PTDD), data direction (PTDDD), pullup enable (PTDPE), and slew rate control (PTDSE) registers. If a TPM takes control of a port D pin, the corresponding PTDDD bit is ignored. When the TPM is in output compare mode, the corresponding PTDSE can be used to provide slew rate on the pin. When the TPM is in input capture mode, the corresponding PTDPE can be used, provided the corresponding PTDDD bit is 0, to provide a pullup device on the pin. Reads of PTDD will return the logic value of the corresponding pin, provided PTDDD is 0. 7 6 5 4 3 2 1 0 R PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-21. Port D Data Register (PTDD) Table6-13. PTDD Field Descriptions Field Description 7:0 Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D PTDD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7 6 5 4 3 2 1 0 R PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-22. Pullup Enable for Port D (PTDPE) Table6-14. PTDPE Field Descriptions Field Description 7:0 Pullup Enable for Port D Bits — For port D pins that are inputs, these read/write control bits determine whether PTDPE[7:0] internal pullup devices are enabled. For port D pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 95

Chapter6 Parallel Input/Output 7 6 5 4 3 2 1 0 R PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 W Reset 0 0 0 0 0 0 0 0 Figure6-23. Slew Rate Control Enable for Port D (PTDSE) Table6-15. PTDSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port D Bits — For port D pins that are outputs, these read/write control bits PTDSE[7:0] determine whether the slew rate controlled outputs are enabled. For port D pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-24. Data Direction for Port D (PTDDD) Table6-16. PTDDD Field Descriptions Field Description 7:0 Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for PTDDD[7:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn. MC9S08GB60A Data Sheet, Rev. 2 96 Freescale Semiconductor

Chapter6 Parallel Input/Output 6.6.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) Port E includes eight general-purpose I/O pins that share with the SCI1 and SPI modules. Port E pins used as general-purpose I/O pins are controlled by the port E data (PTED), data direction (PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers. If the SCI1 takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to provide slew rate on the SCI1 transmit pin, TxD1. PTEPE can be used, provided the corresponding PTEDD bit is 0, to provide a pullup device on the SCI1 receive pin, RxD1. If the SPI takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to provide slew rate on the SPI serial output pin (MOSI1 or MISO1) and serial clock pin (SPSCK1) depending on the SPI operational mode. PTEPE can be used, provided the corresponding PTEDD bit is 0, to provide a pullup device on the SPI serial input pins (MOSI1 or MISO1) and slave select pin (SS1) depending on the SPI operational mode. Reads of PTED will return the logic value of the corresponding pin, provided PTEDD is 0. 7 6 5 4 3 2 1 0 R PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0 W Reset 0 0 0 0 0 0 0 0 Figure6-25. Port E Data Register (PTED) Table6-17. PTED Field Descriptions Field Description 7:0 Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E PTED[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits in this register. For port E pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 97

Chapter6 Parallel Input/Output 7 6 5 4 3 2 1 0 R PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-26. Pullup Enable for Port E (PTEPE) Table6-18. PTEPE Field Descriptions Field Description 7:0 Pullup Enable for Port E Bits — For port E pins that are inputs, these read/write control bits determine whether PTEPE[7:0] internal pullup devices are enabled. For port E pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. 7 6 5 4 3 2 1 0 R PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0 W Reset 0 0 0 0 0 0 0 0 Figure6-27. Slew Rate Control Enable for Port E (PTESE) Table6-19. PTESE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port E Bits — For port E pins that are outputs, these read/write control bits PTESE[7:0] determine whether the slew rate controlled outputs are enabled. For port E pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-28. Data Direction for Port E (PTEDD) Table6-20. PTEDD Field Descriptions Field Description 7:0 Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for PTEDD[7:0] PTED reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn. MC9S08GB60A Data Sheet, Rev. 2 98 Freescale Semiconductor

Chapter6 Parallel Input/Output 6.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD) Port F includes eight general-purpose I/O pins that are not shared with any peripheral module. Port F pins used as general-purpose I/O pins are controlled by the port F data (PTFD), data direction (PTFDD), pullup enable (PTFPE), and slew rate control (PTFSE) registers. 7 6 5 4 3 2 1 0 R PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0 W Reset 0 0 0 0 0 0 0 0 Figure6-29. Port PTF Data Register (PTFD) Table6-21. PTFD Field Descriptions Field Description 7:0 Port PTF Data Register Bits — For port F pins that are inputs, reads return the logic level on the pin. For port PTFD[7:0] F pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7 6 5 4 3 2 1 0 R PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-30. Pullup Enable for Port F (PTFPE) Table6-22. PTFPE Field Descriptions Field Description 7:0 Pullup Enable for Port F Bits — For port F pins that are inputs, these read/write control bits determine whether PTFPE[7:0] internal pullup devices are enabled. For port F pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 99

Chapter6 Parallel Input/Output 7 6 5 4 3 2 1 0 R PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0 W Reset 0 0 0 0 0 0 0 0 Figure6-31. Slew Rate Control Enable for Port F (PTFSE) Table6-23. PTFSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port F Bits — For port F pins that are outputs, these read/write control bits PTFSE[7:0] determine whether the slew rate controlled outputs are enabled. For port F pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-32. Data Direction for Port F (PTFDD) Table6-24. PTFDD Field Descriptions Field Description 7:0 Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for PTFDD[7:0] PTFD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn. 6.6.7 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) Port G includes eight general-purpose I/O pins that are shared with BKGD/MS function and the oscillator or external clock pins. Port G pins used as general-purpose I/O pins are controlled by the port G data (PTGD), data direction (PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers. Port pin PTG0, while in reset, defaults to the BKGD/MS pin. After the MCU is out of reset, PTG0 can be configured to be a general-purpose output pin. When BKGD/MS takes control of PTG0, the corresponding PTGDD, PTGPE, and PTGPSE bits are ignored. Port pins PTG1 and PTG2 can be configured to be oscillator or external clock pins. When the oscillator takes control of a port G pin, the corresponding PTGD, PTGDD, PTGSE, and PTGPE bits are ignored. Reads of PTGD will return the logic value of the corresponding pin, provided PTGDD is 0. MC9S08GB60A Data Sheet, Rev. 2 100 Freescale Semiconductor

Chapter6 Parallel Input/Output 7 6 5 4 3 2 1 0 R PTGD7 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0 W Reset 0 0 0 0 0 0 0 0 Figure6-33. Port PTG Data Register (PTGD) Table6-25. PTGD Field Descriptions Field Description 7:0 Port PTG Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port PTGD[7:0] G pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7 6 5 4 3 2 1 0 R PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0 W Reset 0 0 0 0 0 0 0 0 Figure6-34. Pullup Enable for Port G (PTGPE) Table6-26. PTGPE Field Descriptions Field Description 7:0 Pullup Enable for Port G Bits — For port G pins that are inputs, these read/write control bits determine whether PTGPE[7:0] internal pullup devices are enabled. For port G pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 101

Chapter6 Parallel Input/Output 7 6 5 4 3 2 1 0 R PTGSE7 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0 W Reset 0 0 0 0 0 0 0 0 Figure6-35. Slew Rate Control Enable for Port G (PTGSE) Table6-27. PTGSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits PTGSE[7:0] determine whether the slew rate controlled outputs are enabled. For port G pins that are configured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled. 7 6 5 4 3 2 1 0 R PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0 W Reset 0 0 0 0 0 0 0 0 Figure6-36. Data Direction for Port G (PTGDD) Table6-28. PTGDD Field Descriptions Field Description 7:0 Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for PTGDD[7:0] PTGD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn. MC9S08GB60A Data Sheet, Rev. 2 102 Freescale Semiconductor

Chapter 7 Internal Clock Generator (S08ICGV2) The MC9S08GBxxA/GTxxA microcontroller provides one internal clock generation (ICG) module to create the system bus frequency. All functions described in this section are available on the MC9S08GBxxA/GTxxA microcontroller. The EXTAL and XTAL pins share port G bits 2 and 1, respectively. Analog supply lines V and V are internally derived from the MCU’s V and V DDA SSA DD SS pins. Electrical parametric data for the ICG may be found in AppendixA, “Electrical Characteristics.” SYSTEM CONTROL TPM1 TPM2 IIC1 SCI1 SCI2 SPI1 LOGIC ICGERCLK RTI FFE ÷2 ICG FIXED FREQ CLOCK (XCLK) ICGOUT BUSCLK ÷2 ICGLCLK* CPU BDC ATD1 RAM FLASH ATD has min and max Flash has frequency frequency requirements. See requirements for program * ICGLCLK is the alternate BDC clock source for the MC9S08GBxxA/GTxxA. Chapter1, “Device Overview” and and erase operation. AppendixA, “Electrical Characteristics. See AppendixA, “Electrical Characteristics. Figure7-1. System Clock Distribution Diagram NOTE Freescale Semiconductor recommends that flash location $FFBE be reserved to store a nonvolatile version of ICGTRM. This will allow debugger and programmer vendors to perform a manual trim operation and store the resultant ICGTRM value for users to access at a later time. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 103

Chapter7 Internal Clock Generator (S08ICGV2) HCS08 CORE DEBUG MODULE (DBG) A CPU BDC 8 RT 8 PTA7/KBI1P7– 8-BIT KEYBOARD PO PTA0/KBI1P0 INTERRUPT MODULE (KBI1) HCS08 SYSTEM CONTROL B RESET RESETS AND INTERRUPTS CANOANLVOEG(RA-TTTEDOR1-D )(1IG0-ITBAITL) 8 PORT 8 PPTTBB07//AADD11PP07– MODES OF OPERATION POWER MANAGEMENT PTC7 PTC6 RTI COP PTC5 C IRQ IRQ LVD IIC MODULE SCL1 RT PTC4 (IIC1) O PTC3/SCL1 SDA1 P PTC2/SDA1 SCL1 PTC1/RxD2 SERIAL COMMUNICATIONS SCL1 PTC0/TxD2 INTERFACE MODULE USER FLASH (SCI2) PTD7/TPM2CH4 (Gx60A = 61,268 BYTES) PTD6/TPM2CH3 (Gx32A = 32,768 BYTES) 5-CHANNMEOLD TUILMEER/PWM 5 T D PPTTDD45//TTPPMM22CCHH12 R PTD3/TPM2CH0 (TPM2) O 3 P PTD2/TPM1CH2 USER RAM PTD1/TPM1CH1 3-CHANNEL TIMER/PWM (Gx60A = 4096 BYTES) PTD0/TPM1CH0 MODULE (Gx32A = 2048 BYTES) (TPM1) PTE7 PTE6 SPSCK1 VVDDAD SERIAL PERIPHERAL MOSI1 T E PPTTEE45//MSPOSSCI1K1 VSRSEAFDH INTERF(ASCPEI1 M)ODULE MSSIS1O1 POR PTE3/MISO1 V PTE2/SS1 REFL RxD1 PTE1/RxD1 SERIAL COMMUNICATIONS TxD1 VDD VOLTAGE INTERFACE MODULE PTE0/TxD1 (SCI1) V REGULATOR SS T F 8 R PTF7–PTF0 O P 4 PTG7–PTG4 INTERNAL CLOCK PTG3 GENERATOR EXTAL G PTG2/EXTAL (ICG) XTAL T R PTG1/XTAL BKGD O P PTG0/BKGD/MS LOW-POWER OSCILLATOR Note: Not all pins are bonded out in all packages. See Table2-2 for complete details. Block Diagram Symbol Key: = Not connected in 48-, 44-, and 42-pin packages = Not connected in 44- and 42-pin packages = Not connected in 42-pin packages Figure7-2. Block Diagram Highlighting ICG Module MC9S08GB60A Data Sheet, Rev. 2 104 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) 7.1 Introduction Figure 7-3 is a top-level diagram that shows the functional organization of the internal clock generation (ICG) module. This section includes a general description and a feature list. EXTAL ICG OSCILLATOR (OSC) CLOCK WITH EXTERNAL REF SELECT SELECT ICGERCLK XTAL OUTPUT ICGDCLK CLOCK /R FREQUENCY DCO SELECT ICGOUT LOCKED REF LOOP (FLL) SELECT V DDA (SEE NOTE 2) LOSS OF LOCK AND CLOCK DETECTOR V SSA FIXED (SEE NOTE 2) CLOCK SELECT FFE IRG ICGIRCLK TYP 243 kHz INTERNAL REFERENCE 8 MHz GENERATORS RG LOCAL CLOCK FOR OPTIONAL USE WITH BDC ICGLCLK NOTES: 1. See Table7-1 for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK 2. Not all HCS08 microcontrollers have unique supply pins for the ICG. See the device pin assignments in Chapter2, “Pins and Connections for specifics. Figure7-3. ICG Block Diagram The ICG provides multiple options for clock sources. This offers a user great flexibility when making choices between cost, precision, current draw, and performance. As seen in Figure 7-3, the ICG consists of four functional blocks. Each of these is briefly described here and then in more detail in a later section. • Oscillator block — The oscillator block provides means for connecting an external crystal or resonator. Two frequency ranges are software selectable to allow optimal startup and stability. Alternatively, the oscillator block can be used to route an external square wave to the system clock. External sources can provide a very precise clock source. The oscillator is capable of being configured for low power mode or high amplitude mode as selected by HGO. • Internal reference generator — The internal reference generator consists of two controlled clock sources. One is designed to be approximately 8 MHz and can be selected as a local clock for the background debug controller. The other internal reference clock source is typically 243 kHz and can be trimmed for finer accuracy via software when a precise timed event is input to the MCU. This provides a highly reliable, low-cost clock source. • Frequency-locked loop — A frequency-locked loop (FLL) stage takes either the internal or external clock source and multiplies it to a higher frequency. Status bits provide information when the circuit has achieved lock and when it falls out of lock. Additionally, this block can monitor the external reference clock and signals whether the clock is valid or not. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 105

Internal Clock Generator (S08ICGV2) • Clock select block — The clock select block provides several switch options for connecting different clock sources to the system clock tree. ICGDCLK is the multiplied clock frequency out of the FLL, ICGERCLK is the reference clock frequency from the crystal or external clock source, and FFE (fixed frequency enable) is a control signal used to control the system fixed frequency clock (XCLK). ICGLCLK is the clock source for the background debug controller (BDC). The module is intended to be very user friendly with many of the features occurring automatically without user intervention. To quickly configure the module, go to Section 7.4, “Initialization/Application Information” and pick an example that best suits the application needs. 7.1.1 Features Features of the ICG and clock distribution system: • Several options for the primary clock source allow a wide range of cost, frequency, and precision choices: — 32kHz–100 kHz crystal or resonator — 1MHz–16MHz crystal or resonator — External clock — Internal reference generator • Defaults to self-clocked mode to minimize startup delays • Frequency-locked loop (FLL) generates 8MHz to 40MHz (for bus rates up to 20MHz) — Uses external or internal clock as reference frequency • Automatic lockout of non-running clock sources • Reset or interrupt on loss of clock or loss of FLL lock • Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast frequency lock when recovering from stop3 mode • DCO will maintain operating frequency during a loss or removal of reference clock • Post-FLL divider selects 1 of 8 bus rate divisors (/1 through /128) • Separate self-clocked source for real-time interrupt • Trimmable internal clock source supports SCI communications without additional external components • Automatic FLL engagement after lock is acquired • Selectable low-power/high-gain oscillator modes MC9S08GB60A Data Sheet, Rev. 2 106 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) 7.1.2 Modes of Operation This is a high-level description only. Detailed descriptions of operating modes are contained in Section7.3, “Functional Description.” • Mode 1 — Off The output clock, ICGOUT, is static. This mode may be entered when the STOP instruction is executed. • Mode 2 — Self-clocked (SCM) Default mode of operation that is entered out of reset. The ICG’s FLL is open loop and the digitally controlled oscillator (DCO) is free running at a frequency set by the filter bits. • Mode 3 — FLL engaged internal (FEI) In this mode, the ICG’s FLL is used to create frequencies that are programmable multiples of the internal reference clock. — FLL engaged internal unlocked is a transition state which occurs while the FLL is attempting to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. — FLL engaged internal locked is a state which occurs when the FLL detects that the DCO is locked to a multiple of the internal reference. • Mode 4 — FLL bypassed external (FBE) In this mode, the ICG is configured to bypass the FLL and use an external clock as the clock source. • Mode 5 — FLL engaged external (FEE) The ICG’s FLL is used to generate frequencies that are programmable multiples of the external clock reference. — FLL engaged external unlocked is a transition state which occurs while the FLL is attempting to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. — FLL engaged external locked is a state which occurs when the FLL detects that the DCO is locked to a multiple of the internal reference. 7.2 Oscillator Pins The oscillator pins are used to provide an external clock source for the MCU. 7.2.1 EXTAL— External Reference Clock / Oscillator Input If upon the first write to ICGC1, either FEE mode or FBE mode is selected, this pin functions as either the external clock input or the input of the oscillator circuit as determined by REFS. If upon the first write to ICGC1, either FEI mode or SCM mode is selected, this pin is not used by the ICG. 7.2.2 XTAL— Oscillator Output If upon the first write to ICGC1, either FEE mode or FBE mode is selected, this pin functions as the output of the oscillator circuit. If upon the first write to ICGC1, either FEI mode or SCM mode is selected, this MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 107

Internal Clock Generator (S08ICGV2) pin is not used by the ICG. The oscillator is capable of being configured to provide a higher amplitude output for improved noise immunity. This mode of operation is selected by HGO = 1. 7.2.3 External Clock Connections If an external clock is used, then the pins are connected as shown in Figure 7-4. ICG EXTAL V XTAL SS NOT CONNECTED CLOCK INPUT Figure7-4. External Clock Connections 7.2.4 External Crystal/Resonator Connections If an external crystal/resonator frequency reference is used, then the pins are connected as shown in Figure 7-5. Recommended component values are listed in AppendixA, “Electrical Characteristics.” ICG EXTAL V XTAL SS R S C C 1 2 R F CRYSTAL OR RESONATOR Figure7-5. External Frequency Reference Connection MC9S08GB60A Data Sheet, Rev. 2 108 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) 7.3 Functional Description This section provides a functional description of each of the five operating modes of the ICG. Also covered are the loss of clock and loss of lock errors and requirements for entry into each mode. The ICG is very flexible, and in some configurations, it is possible to exceed certain clock specifications. When using the FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value to ensure proper MCU operation. 7.3.1 Off Mode (Off) Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state. However there are two cases to consider when clock activity continues while the CPU is in stop mode. 7.3.1.1 BDM Active When the BDM is enabled (ENBDM = 1), the ICG continues activity as originally programmed. This allows access to memory and control registers via the BDC. 7.3.1.2 OSCSTEN Bit Set When the oscillator is enabled in stop mode (OSCSTEN= 1), the individual clock generators are enabled but the clock feed to the rest of the MCU is turned off. This option is provided to avoid long oscillator startup times if necessary, or to run the RTI from the oscillator during stop3. 7.3.1.3 Stop/Off Mode Recovery Upon the CPU exiting stop mode due to an interrupt, the previously set control bits are valid and the system clock feed resumes. If FEE is selected, the ICG will source the internal reference until the external clock is stable. If FBE is selected, the ICG will wait for the external clock to stabilize before enabling ICGOUT. Upon the CPU exiting stop mode due to a reset, the previously set ICG control bits are ignored and the default reset values applied. Therefore the ICG will exit stop in SCM mode configured for an approximately 8 MHz DCO output (4 MHz bus clock) with trim value maintained. If using a crystal, 4096 clocks are detected prior to engaging ICGERCLK. This is incorporated in crystal start-up time. 7.3.2 Self-Clocked Mode (SCM) Self-clocked mode (SCM) is the default mode of operation and is entered when any of the following conditions occur: • After any reset. • Exiting from off mode when CLKS does not equal 10. If CLKS= X1, the ICG enters this state temporarily until the DCO is stable (DCOS=1). • CLKS bits are written from X1 to 00. • CLKS=1X and ICGERCLK is not detected (both ERCS= 0 and LOCS=1). MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 109

Internal Clock Generator (S08ICGV2) In this state, the FLL loop is open. The DCO is on, and the output clock signal ICGOUT frequency is given by f / R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value ICGDCLK into the filter registers (ICGFLTU and ICGFLTL). This is the only mode in which the filter registers can be written. If this mode is entered due to a reset, f will default to f which is nominally 8 MHz. If this ICGDCLK Self_reset mode is entered from FLL engaged internal, f will maintain the previous frequency. If this mode ICGDCLK is entered from FLL engaged external (either by programming CLKS or due to a loss of external reference clock), f will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked. ICGDCLK If this mode is entered from off mode, f will be equal to the frequency of ICGDCLK before ICGDCLK entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode until ICGDCLK is stable as determined by the DCOS bit. Once ICGDCLK is considered stable, the ICG automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS bits. CLKST CLKS RFD REFERENCE ICGIRCLK CLOCK REDUCED ICGOUT DIVIDER (/7) SELECT FREQUENCY CIRCUIT DIVIDER (R) RANGE ICGDCLK FLT MFD DIGITAL DIGITALLY 1x SUBTRACTOR LOOP CONTROLLED FILTER OSCILLATOR 2x FLL ANALOG K CLKST L C R FREQUENCY- GE LOCKED C LOOP (FLL) I OVERFLOW PULSE ICG2DCLK COUNTER COUNTER ENABLE RANGE IRQ LOCK AND RESET AND LOSS OF CLOCK INTERRUPT RESET DETECTOR CONTROL DCOS LOCK LOLS LOCS ERCS LOCD ICGIF LOLRE LOCRE Figure7-6. Detailed Frequency-Locked Loop Block Diagram MC9S08GB60A Data Sheet, Rev. 2 110 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) 7.3.3 FLL Engaged, Internal Clock (FEI) Mode FLL engaged internal (FEI) is entered when any of the following conditions occur: • CLKS bits are written to 01 • The DCO clock stabilizes (DCOS= 1) while in SCM upon exiting the off state with CLKS=01 In FLL engaged internal mode, the reference clock is derived from the internal reference clock ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. 7.3.3.1 FLL Engaged Internal Unlocked FEI unlocked is a temporary state that is entered when FEI is entered and the count error (Δn) output from the subtractor is greater than the maximum n or less than the minimum n , as required by the unlock unlock lock detector to detect the unlock condition. The ICG will remain in this state while the count error (Δn) is greater than the maximum n or less than lock the minimum n , as required by the lock detector to detect the lock condition. lock In this state the output clock signal ICGOUT frequency is given by f / R. ICGDCLK 7.3.3.2 FLL Engaged Internal Locked FLL engaged internal locked is entered from FEI unlocked when the count error (Δn), which comes from the subtractor, is less than n (max) and greater than nlock (min) for a given number of samples, as lock required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is given by f / R. In FEI locked, the filter value is only updated once every four comparison cycles. ICGDCLK The update made is an average of the error measurements taken in the four previous comparisons. 7.3.4 FLL Bypassed, External Clock (FBE) Mode FLL bypassed external (FBE) is entered when any of the following conditions occur: • From SCM when CLKS= 10 and ERCS is high • When CLKS= 10, ERCS =1 upon entering off mode, and off is then exited • From FLL engaged external mode if a loss of DCO clock occurs and the external reference is still valid (both LOCS= 1 and ERCS=1) In this state, the DCO and IRG are off and the reference clock is derived from the external reference clock, ICGERCLK. The output clock signal ICGOUT frequency is given by f / R. If an external clock ICGERCLK source is used (REFS= 0), then the input frequency on the EXTAL pin can be anywhere in the range 0MHz to 40MHz. If a crystal or resonator is used (REFS =1), then frequency range is either low for RANGE= 0 or high for RANGE= 1. 7.3.5 FLL Engaged, External Clock (FEE) Mode The FLL engaged external (FEE) mode is entered when any of the following conditions occur: • CLKS=11 and ERCS and DCOS are both high. • The DCO stabilizes (DCOS= 1) while in SCM upon exiting the off state with CLKS=11. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 111

Internal Clock Generator (S08ICGV2) In FEE mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To run in FEE mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source. The maximum external clock frequency is limited to 10 MHz in FEE mode to prevent over-clocking the DCO. The minimum multiplier for the FLL, from Table 7-7, is 4. Because 4 X 10 MHz is 40 MHz, which is the operational limit of the DCO, the reference clock cannot be any faster than 10 MHz. 7.3.5.1 FLL Engaged External Unlocked FEE unlocked is entered when FEE is entered and the count error (Δn) output from the subtractor is greater than the maximum n or less than the minimum n , as required by the lock detector to detect the unlock unlock unlock condition. The ICG will remain in this state while the count error (Δn) is greater than the maximum n or less than lock the minimum n , as required by the lock detector to detect the lock condition. lock In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to lock it according to their operational descriptions later in this section. Upon entering this state and until the FLL becomes locked, the output clock signal ICGOUT frequency is given by f / (2×R). This ICGDCLK extra divide by two prevents frequency overshoots during the initial locking process from exceeding chip-level maximum frequency specifications. As soon as the FLL has locked, if an unexpected loss of lock causes it to re-enter the unlocked state while the ICG remains in FEE mode, the output clock signal ICGOUT frequency is given by f / R. ICGDCLK 7.3.5.2 FLL Engaged External Locked FEE locked is entered from FEE unlocked when the count error (Δn) is less than n (max) and greater lock than n (min) for a given number of samples, as required by the lock detector to detect the lock lock condition. The output clock signal ICGOUT frequency is given by f /R. In FLL engaged external ICGDCLK locked, the filter value is only updated once every four comparison cycles. The update made is an average of the error measurements taken in the four previous comparisons. 7.3.6 FLL Lock and Loss-of-Lock Detection To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO for one comparison cycle (see Table 7-2 for explanation of a comparison cycle) and passes this number to the subtractor. The subtractor compares this value to the value in MFD and produces a count error, Δn. To achieve locked status, Δn must be between n (min) and n (max). As soon as the FLL has locked, Δn lock lock must stay between n (min) and n (max) to remain locked. If Δn goes outside this range unlock unlock unexpectedly, the LOLS status bit is set and remains set until acknowledged or until the MCU is reset. LOLS is cleared by reading ICGS1 then writing 1 to ICGIF (LOLRE = 0), or by a loss-of-lock induced reset (LOLRE = 1), or by any MCU reset. If the ICG enters the off state due to stop mode when ENBDM = OSCSTEN= 0, the FLL loses locked status (LOCK is cleared), but LOLS remains unchanged because this is not an unexpected loss-of-lock condition. Though it would be unusual, if ENBDM is cleared to 0 while the MCU is in stop, the ICG enters MC9S08GB60A Data Sheet, Rev. 2 112 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) the off state. Because this is an unexpected stopping of clocks, LOLS will be set when the MCU wakes up from stop. Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the LOLS will not be set. 7.3.7 FLL Loss-of-Clock Detection The reference clock and the DCO clock are monitored under different conditions (see Table7-1). Provided the reference frequency is being monitored, ERCS=1 indicates that the reference clock meets minimum frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either one falls below a certain frequency, f and f , respectively, the LOCS status bit will be set to indicate the error. LOR LOD LOCS will remain set until it is cleared by software or until the MCU is reset. LOCS is cleared by reading ICGS1 then writing 1 to ICGIF (LOCRE = 0), or by a loss-of-clock induced reset (LOCRE = 1), or by any MCU reset. If the ICG is in FEE, a loss of reference clock causes the ICG to enter SCM, and a loss of DCO clock causes the ICG to enter FBE mode. If the ICG is in FBE mode, a loss of reference clock will cause the ICG to enter SCM. In each case, the CLKST and CLKS bits will be automatically changed to reflect the new state. A loss of clock will also cause a loss of lock when in FEE or FEI modes. Because the method of clearing the LOCS and LOLS bits is the same, this would only be an issue in the unlikely case that LOLRE =1 and LOCRE= 0. In this case, the interrupt would be overridden by the reset for the loss of lock. Table7-1. Clock Monitoring (When LOCD = 0) External Reference DCO Clock Mode CLKS REFST ERCS Clock Monitored? Monitored? 0X or 11 X Forced Low No No Off 10 0 Forced Low No No 10 1 Real-Time1 Yes(1) No 0X X Forced Low No Yes2 SCM 10 0 Forced High No Yes(2) (CLKST=00) 10 1 Real-Time Yes Yes(2) 11 X Real-Time Yes Yes(2) FEI 0X X Forced Low No Yes (CLKST=01) 11 X Real-Time Yes Yes FBE 10 0 Forced High No No (CLKST=10) 10 1 Real-Time Yes No FEE 11 X Real-Time Yes Yes (CLKST=11) 1 If ENABLE is high (waiting for external crystal start-up after exiting stop). 2 DCO clock will not be monitored until DCOS=1 upon entering SCM from off or FLL bypassed external mode. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 113

Internal Clock Generator (S08ICGV2) 7.3.8 Clock Mode Requirements A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by CLKST1:CLKST0. Provided minimum conditions are met, the status shown in CLKST1:CLKST0 should be the same as the requested mode in CLKS1:CLKS0. Table7-2 shows the relationship between CLKS, CLKST, and ICGOUT. It also shows the conditions for CLKS= CLKST or the reason CLKS ≠ CLKST. NOTE If a crystal will be used before the next reset, then be sure to set REFS= 1 and CLKS= 1x on the first write to the ICGC1 register. Failure to do so will result in “locking” REFS= 0, which will prevent the oscillator amplifier from being enabled until the next reset occurs. Table7-2. ICG State Table Actual Desired Reference Reason Comparison Conditions1 for Mode Mode Range Frequency ICGOUT CLKS1 = Cycle Time CLKS=CLKST (CLKST) (CLKS) (f ) CLKST REFERENCE Off X 0 — 0 — — Off (XX) (XX) FBE X 0 — 0 — ERCS = 0 (10) SCM Not switching from (00) X fICGIRCLK/72 8/fICGIRCLK ICGDCLK/R FBE to SCM — FEI SCM (01) 0 fICGIRCLK/7(1) 8/fICGIRCLK ICGDCLK/R — DCOS=0 (00) FBE (10) X fICGIRCLK/7(1) 8/fICGIRCLK ICGDCLK/R — ERCS=0 FEE DCOS=0 or (11) X fICGIRCLK/7(1) 8/fICGIRCLK ICGDCLK/R — ERCS=0 FEI FEI (01) 0 fICGIRCLK/7 8/fICGIRCLK ICGDCLK/R DCOS=1 — (01) FEE (11) X fICGIRCLK/7 8/fICGIRCLK ICGDCLK/R — ERCS=0 FBE X 0 — ICGERCLK/R ERCS=1 — FBE (10) (10) FEE LOCS=1 & X 0 — ICGERCLK/R — (11) ERCS=1 ERCS=1 and FEE FEE 0 fICGERCLK 2/fICGERCLK ICGDCLK/R3 DCOS=1 — (11) (11) ERCS=1 and 1 fICGERCLK 128/fICGERCLK ICGDCLK/R(2) DCOS=1 — 1 CLKST will not update immediately after a write to CLKS. Several bus cycles are required before CLKST updates to the new value. 2 The reference frequency has no effect on ICGOUT in SCM, but the reference frequency is still used in making the comparisons that determine the DCOS bit. 3 After initial LOCK; will be ICGDCLK/2R during initial locking process and while FLL is re-locking after the MFD bits are changed. MC9S08GB60A Data Sheet, Rev. 2 114 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) 7.3.9 Fixed Frequency Clock The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is equal to the internal bus clock, BUSCLK, in FBE mode. In FEE mode, XCLK is equal to ICGERCLK ÷ 2 when the following conditions are met: • (P × N) ÷ R ≥ 4 where P is determined by RANGE (see Table 7-4), N and R are determined by MFD and RFD, respectively (see Table 7-5). • LOCK = 1. If the above conditions are not true, then XCLK is equal to BUSCLK. When the ICG is in either FEI or SCM mode, XCLK is turned off. Any peripherals which can use XCLK as a clock source must not do so when the ICG is in FEI or SCM mode. 7.3.10 High Gain Oscillator The oscillator has the option of running in a high gain oscillator (HGO) mode, which improves the oscillator's resistance to EMC noise when running in FBE or FEE modes. This option is selected by writing a 1 to the HGO bit in the ICGC1 register. HGO is used with both the high and low range oscillators but is only valid when REFS = 1 in the ICGC1 register. When HGO = 0, the standard low-power oscillator is selected. If the high gain option is to be switched after the initial write to the ICGC1 register, then the ICG should first be changed to SCM or FEI mode to stop the external oscillator. Then the HGO bit can be modified and FEE or FBE mode can be re-selected in the same write to ICGC1. The oscillator will go through the standard start-up delay before the ICG switches to the external oscillator 7.4 Initialization/Application Information 7.4.1 Introduction This section is intended to give some basic direction on which configuration a user would want to select when initializing the ICG. For some applications, the serial communication link may dictate the accuracy of the clock reference. For other applications, lowest power consumption may be the chief clock consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in choosing which is best for any application. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 115

Internal Clock Generator (S08ICGV2) Table7-3. ICG Configuration Consideration Clock Reference Source = Internal Clock Reference Source = External FEI FEE 4 MHz < fBus < 20 MHz. 4 MHz < fBus < 20 MHz Medium power (will be less than FEE if oscillator Medium power (will be less than FEI if oscillator FLL range = high) range = low) Engaged Medium clock accuracy (After IRG is trimmed) Good clock accuracy Lowest system cost (no external components Medium/High system cost (crystal, resonator or required) external clock source required) IRG is on. DCO is on. 1 IRG is off. DCO is on. SCM FBE This mode is mainly provided for quick and reliable f range <= 8 MHz when crystal or resonator is Bus system startup. used. FLL 3 MHz < fBus < 5 MHz (default). Lowest power Bypassed 3 MHz < fBus < 20 MHz (via filter bits). Highest clock accuracy Medium power Medium/High system cost (Crystal, resonator or Poor accuracy. external clock source required) IRG is off. DCO is on and open loop. IRG is off. DCO is off. 1 The IRG typically consumes 100 μA. The FLL and DCO typically consumes 0.5 to 2.5 mA, depending upon output frequency. For minimum power consumption and minimum jitter, choose N and R to be as small as possible. The following sections contain initialization examples for various configurations. NOTE Hexadecimal values designated by a preceding $, binary values designated by a preceding %, and decimal values have no preceding character. Important configuration information is repeated here for reference. Table7-4. ICGOUT Frequen cy Calculation Options Clock Scheme f 1 P Note ICGOUT SCM — self-clocked mode (FLL bypassed f / R NA Typical fICGOUT = internal) ICGDCLK 8MHz out of reset FBE — FLL bypassed external fext / R NA FEI — FLL engaged internal (fIRG / 7)* 64*N / R 64 Typical fIRG = 243 kHz Range =0 ; P = 64 FEE — FLL engaged external fext * P * N / R Range =1; P = 1 1 Ensure that f , which is equal to f * R, does not exceed f ICGDCLK ICGOUT ICGDCLKmax. MC9S08GB60A Data Sheet, Rev. 2 116 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) Table7-5. MFD and RFD Decode Table MFD Value Multiplication Factor (N) RFD Division Factor (R) 000 4 000 ÷1 001 6 001 ÷2 010 8 010 ÷4 011 10 011 ÷8 100 12 100 ÷16 101 14 101 ÷32 110 16 110 ÷64 111 18 111 ÷128 Register Bit 7 6 5 4 3 2 1 Bit 0 ICGC1 HGO RANGE REFS CLKS OSCSTEN LOCD 0 ICGC2 LOLRE MFD LOCRE RFD ICGS1 CLKST REFST LOLS LOCK LOCS ERCS ICGIF ICGS2 0 0 0 0 0 0 0 DCOS ICGFLTU 0 0 0 0 FLT ICGFLTL FLT ICGTRM TRIM = Unimplemented or Reserved Figure7-7. ICG Register Set MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 117

Internal Clock Generator (S08ICGV2) 7.4.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to 8.38MHz to achieve 4.19 MHz bus frequency. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT, which corresponds to a 4 MHz bus frequency (f ). Bus The clock scheme will be FLL engaged, external (FEE). So f = f * P * N / R ; P =64, f = 32 kHz Eqn.7-1 ICGOUT ext ext Solving for N / R gives: N / R = 8.38 MHz /(32 kHz * 64) = 4 ; we can choose N = 4 and R =1 Eqn.7-2 The values needed in each register to set up the desired operation are: ICGC1 = $38 (%00111000) Bit 7 HGO 0 Configures oscillator for low-power operation Bit 6 RANGE 0 Configures oscillator for low-frequency range; FLL prescale factor is 64 Bit 5 REFS 1 Oscillator using crystal or resonator is requested Bits 4:3 CLKS 11 FLL engaged, external reference clock mode Bit 2 OSCSTEN 0 Oscillator disabled in stop modes Bit 1 LOCD 0 Loss-of-clock detection enabled Bit 0 0 Unimplemented or reserved, always reads zero ICGC2 = $00 (%00000000) Bit 7 LOLRE 0 Generates an interrupt request on loss of lock Bits 6:4 MFD 000 Sets the MFD multiplication factor to 4 Bit 3 LOCRE 0 Generates an interrupt request on loss of clock Bits 2:0 RFD 000 Sets the RFD division factor to ÷1 ICGS1 = $xx This is read only except for clearing interrupt flag ICGS2 = $xx This is read only; should read DCOS=1 before performing any time critical tasks ICGFLTLU/L = $xx Only needed in self-clocked mode; FLT will be adjusted by loop to give 8.38 MHz DCO clock Bits 15:12 unused 0000 Bits 11:0 FLT No need for user initialization ICGTRM = $xx Bits 7:0 TRIM Only need to write when trimming internal oscillator; not used when external crystal is clock source MC9S08GB60A Data Sheet, Rev. 2 118 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) Figure 7-8 shows flow charts for three conditions requiring ICG initialization. RECOVERY FROM QUICK RECOVERY FROM STOP MINIMUM CURRENT DRAW IN STOP RESET, STIO1, STOP2 RECOVERY FROM STOP3 RECOVERY FROM STOP3 OSCSTEN =1 OSCSTEN =0 INITIALIZE ICG ICG1 = $38 ICG2=$00 CHECK CHECK NO NO FLL LOCK STATUS. FLL LOCK STATUS. LOCK=1? LOCK=1? YES YES CHECK NO FLL LOCK STATUS. LOCK=1? CONTINUE CONTINUE YES CONTINUE NOTE: THIS WILL REQUIRE THE OSCILLATOR TO START AND STABILIZE. ACTUAL TIME IS DEPENDENT ON CRYSTAL /RESONATOR AND EXTERNAL CIRCUITRY. Figure7-8. ICG Initialization for FEE in Example #1 7.4.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 4 MHz oscillator up to 40-MHz to achieve 20 MHz bus frequency. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (f ). Bus During reset initialization software, the clock scheme will be set to FLL engaged, external (FEE). So f = f * P * N / R ; P =1, f = 4.00 MHz Eqn.7-3 ICGOUT ext ext Solving for N / R gives: N / R = 40 MHz /(4 MHz * 1) = 10 ; We can choose N = 10 and R =1 Eqn.7-4 The values needed in each register to set up the desired operation are: ICGC1 = $78 (%01111000) Bit 7 HGO 0 Configures oscillator for low-power operation Bit 6 RANGE 1 Configures oscillator for high-frequency range; FLL prescale factor is 1 Bit 5 REFS 1 Requests an oscillator Bits 4:3 CLKS 11 FLL engaged, external reference clock mode Bit 2 OSCSTEN 0 Disables the oscillator in stop modes Bit 1 LOCD 0 Loss-of-clock detection enabled Bit 0 0 Unimplemented or reserved, always reads zero MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 119

Internal Clock Generator (S08ICGV2) ICGC2 = $30 (%00110000) Bit 7 LOLRE 0 Generates an interrupt request on loss of lock Bit 6:4 MFD 011 Sets the MFD multiplication factor to 10 Bit 3 LOCRE 0 Generates an interrupt request on loss of clock Bit 2:0 RFD 000 Sets the RFD division factor to ÷1 ICGS1 = $xx This is read only except for clearing interrupt flag ICGS2 = $xx This is read only. Should read DCOS before performing any time critical tasks ICGFLTLU/L = $xx Not used in this example ICGTRM Not used in this example RECOVERY FROM RECOVERY RESET, STOP1, STOP2 FROM STOP3 INITIALIZE ICG ICG1 = $7A SERVICE INTERRUPT ICG2=$30 SOURCE (f = 4 MHz) Bus CHECK NO FLL LOCK STATUS CHECK NO LOCK=1? FLL LOCK STATUS LOCK=1? YES YES CONTINUE CONTINUE Figure7-9. ICG Initialization and Stop Recovery for Example #2 MC9S08GB60A Data Sheet, Rev. 2 120 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) 7.4.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency In this example, the FLL will be used (in FEI mode) to multiply the internal 243 kHz (approximate) reference clock up to 10.8 MHz to achieve 5.4 MHz bus frequency. This system will also use the trim function to fine tune the frequency based on an external reference signal. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (f ). Bus The clock scheme will be FLL engaged, internal (FEI). So f = (f / 7) * P * N / R ; P = 64, f = 243 kHz Eqn.7-5 ICGOUT IRG IRG Solving for N / R gives: N / R = 10.8 MHz /(243/7 kHz * 64) = 4.86 ; We can choose N = 10 and R = 2. Eqn.7-6 A trim procedure will be required to hone the frequency to exactly 5.4 MHz. An example of the trim procedure is shown in example #4. The values needed in each register to set up the desired operation are: ICGC1 = $28 (%00101000) Bit 7 HGO 0 Configures oscillator for low-power operation Bit 6 RANGE 0 Configures oscillator for low-frequency range; FLL prescale factor is 64 Bit 5 REFS 1 Oscillator using crystal or resonator requested (bit is really a don’t care) Bits 4:3 CLKS 01 FLL engaged, internal reference clock mode Bit 2 OSCSTEN 0 Disables the oscillator in stop modes Bit 1 LOCD 0 Loss-of-clock detection enabled Bit 0 0 Unimplemented or reserved, always reads zero ICGC2 = $31 (%00110001) Bit 7 LOLRE 0 Generates an interrupt request on loss of lock Bit 6:4 MFD 011 Sets the MFD multiplication factor to 10 Bit 3 LOCRE 0 Generates an interrupt request on loss of clock Bit 2:0 RFD 001 Sets the RFD division factor to ÷2 ICGS1 = $xx This is read only except for clearing interrupt flag ICGS2 = $xx This is read only; good idea to read this before performing time critical operations ICGFLTLU/L = $xx Not used in this example ICGTRM = $xx Bit 7:0 TRIM Only need to write when trimming internal oscillator; done in separate operation (see example #4) MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 121

Internal Clock Generator (S08ICGV2) RECOVERY FROM RECOVERY RESET, STOP1, STOP2 FROM STOP3 INITIALIZE ICG ICG1 = $28 CHECK NO ICG2=$31 FLL LOCK STATUS. LOCK=1? YES CHECK NO FLL LOCK STATUS. LOCK=1? CONTINUE YES CONTINUE NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. Figure7-10. ICG Initialization and Stop Recovery for Example #3 7.4.5 Example #4: Internal Clock Generator Trim The internally generated clock source is guaranteed to have a period ± 25% of the nominal value. In some case this may be sufficient accuracy. For other applications that require a tight frequency tolerance, a trimming procedure is provided that will allow a very accurate source. This section outlines one example of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used. MC9S08GB60A Data Sheet, Rev. 2 122 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) Initial conditions: START TRIM PROCEDURE 1) Clock supplied from ATE has 500 μs duty period ICGTRM = $80, n=1 2) ICG configured for internal reference with 4 MHz bus MEASURE INCOMING CLOCK WIDTH (COUNT = # OF BUS CLOCKS / 4) COUNT < EXPECTED =500 (RUNNING TOO SLOW) . COUNT = EXPECTED = 500 CASE STATEMENT COUNT > SZZEXPECTED = 500 (RUNNING TOO FAST) ICGTRM = ICGTRM = ICGTRM - 128 / (2**n) ICGTRM + 128 / (2**n) STORE ICGTRM VALUE (DECREASI NG ICGTRM (INCREASIN G ICGTRM IN NON-V OLATILE INCREASES THE FREQUENCY) DECREASES THE FREQUENCY) MEMORY CONTINUE n = n + 1 YES IS n > 8? NO Figure7-11. Trim Procedure In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final test with automated test equipment. A separate signal or message is provided to the MCU operating under user provided software control. The MCU initiates a trim procedure as outlined in Figure7-11 while the tester supplies a precision reference signal. If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using a reduction divisor (R) twice the final value. Once the trim procedure is complete, the reduction divisor can be restored. This will prevent accidental overshoot of the maximum clock frequency. 7.5 ICG Registers and Control Bits Refer to the direct-page register summary in Chapter4, “Memory” of this data sheet for the absolute address assignments for all ICG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 123

Internal Clock Generator (S08ICGV2) 7.5.1 ICG Control Register 1 (ICGC1) 7 6 5 4 3 2 1 0 R 0 HGO RANGE REFS CLKS OSCSTEN LOCD W Reset 0 1 0 0 0 1 0 0 = Unimplemented or Reserved Figure7-12. ICG Control Register 1 (ICGC1) Table7-6. ICGC1 Field Descriptions Field Description 7 High Gain Oscillator Select — The HGO bit is used to select between low-power operation and high-amplitude HGO operation. 0 Oscillator configured for low power operation. 1 Oscillator configured for high amplitude operation. 6 Frequency Range Select — The RANGE bit controls the oscillator, reference divider, and FLL loop prescaler RANGE multiplication factor (P). It selects one of two reference frequency ranges for the ICG. The RANGE bit is write-once after a reset. The RANGE bit only has an effect in FLL engaged external and FLL bypassed external modes. 0 Oscillator configured for low frequency range. FLL loop prescale factor P is 64. 1 Oscillator configured for high frequency range. FLL loop prescale factor P is 1. 5 External Reference Select — The REFS bit controls the external reference clock source for ICGERCLK. The REFS REFS bit is write-once after a reset. 0 External clock requested. 1 Oscillator using crystal or resonator requested. 4:3 Clock Mode Select — The CLKS bits control the clock mode. If FLL bypassed external is requested, it will not CLKS be selected until ERCS=1. If the ICG enters off mode, the CLKS bits will remain unchanged. Writes to the CLKS bits will not take effect if a previous write is not complete. The CLKS bits are writable at any time, unless the first write after a reset was CLKS=0X, the CLKS bits cannot be written to 1X until after the next reset (because the EXTAL pin was not reserved). 00 Self-clocked 01 FLL engaged, internal reference 10 FLL bypassed, external reference 11 FLL engaged, external reference 2 Enable Oscillator in Off Mode — The OSCTEN bit controls whether or not the oscillator circuit remains enabled OSCSTEN when the ICG enters off mode. 0 Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS=10, and REFST=1. 1 Oscillator enabled when ICG is in off mode, CLKS=1X and REFST=1. 1 Loss of Clock Disable LOCD 0 Loss of clock detection enabled. 1 Loss of clock detection disabled. MC9S08GB60A Data Sheet, Rev. 2 124 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) 7.5.2 ICG Control Register 2 (ICGC2) 7 6 5 4 3 2 1 0 R LOLRE MFD LOCRE RFD W Reset 0 0 0 0 0 0 0 0 Figure7-13. ICG Control Register 2 (ICGC2) Table7-7. ICGC2 Field Descriptions Field Description 7 Loss of Lock Reset Enable — The LOLRE bit determines what type of request is made by the ICG following a LOLRE loss of lock indication. The LOLRE bit only has an effect when LOLS is set. 0 Generate an interrupt request on loss of lock. 1 Generate a reset request on loss of lock. 6:4 Multiplication Factor — The MFD bits control the programmable multiplication factor in the FLL loop. The value MFD specified by the MFD bits establishes the multiplication factor (N) applied to the reference frequency. Writes to the MFD bits will not take effect if a previous write is not complete. Select a low enough value for N such that f does not exceed its maximum specified rating. ICGDCLK 000 Multiplication Factor (N) = 4 001 Multiplication Factor (N) = 6 010 Multiplication Factor (N) = 8 011 Multiplication Factor (N) = 10 100 Multiplication Factor (N) = 12 101 Multiplication Factor (N) = 14 110 Multiplication Factor (N) = 16 111 Multiplication Factor (N) = 18 3 Loss of Clock Reset Enable — The LOCRE bit determines how the system handles a loss of clock condition. LOCRE 0 Generate an interrupt request on loss of clock. 1 Generate a reset request on loss of clock. 2:0 Reduced Frequency Divider — The RFD bits control the value of the divider following the clock select circuitry. RFD The value specified by the RFD bits establishes the division factor (R) applied to the selected output clock source. Writes to the RFD bits will not take effect if a previous write is not complete. 000 Division Factor (R) = 1 001 Division Factor (R) = 2 010 Division Factor (R) = 4 011 Division Factor (R) = 8 100 Division Factor (R) = 16 101 Division Factor (R) = 32 110 Division Factor (R) = 64 111 Division Factor (R) = 128 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 125

Internal Clock Generator (S08ICGV2) 7.5.3 ICG Status Register 1 (ICGS1) 7 6 5 4 3 2 1 0 R CLKST REFST LOLS LOCK LOCS ERCS ICGIF W 1 Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure7-14. ICG Status Register 1 (ICGS1) Table7-8. ICGS1 Field Descriptions Field Description 7:6 Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update CLKST immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Self-clocked 01 FLL engaged, internal reference 10 FLL bypassed, external reference 11 FLL engaged, external reference 5 Reference Clock Status — The REFST bit indicates which clock reference is currently selected by the REFST Reference Select circuit. 0 External Clock selected. 1 Crystal/Resonator selected. 4 FLL Loss of Lock Status — The LOLS bit is an indication of FLL-lock status. If LOLS is set, it remains set until LOLS cleared by clearing the ICGIF flag or an MCU reset. 0 FLL has not unexpectedly lost lock since LOLS was last cleared. 1 FLL has unexpectedly lost lock since LOLS was last cleared, LOLRE determines action taken. 3 FLL Lock Status — The LOCK bit indicates whether the FLL has acquired lock. The LOCK bit is cleared in off, LOCK self-clocked, and FLL bypassed modes. 0 FLL is currently unlocked. 1 FLL is currently locked. 2 Loss Of Clock Status — The LOCS bit is an indication of ICG loss-of-clock status. If LOCS is set, it remains set LOCS until cleared by clearing the ICGIF flag or an MCU reset. 0 ICG has not lost clock since LOCS was last cleared. 1 ICG has lost clock since LOCS was last cleared, LOCRE determines action taken. 1 External Reference Clock Status — The ERCS bit is an indication of whether or not the external reference clock ERCS (ICGERCLK) meets the minimum frequency requirement. 0 External reference clock is not stable, frequency requirement is not met. 1 External reference clock is stable, frequency requirement is met. 0 ICG Interrupt Flag — The ICGIF read/write flag is set when an ICG interrupt request is pending. It is cleared by ICGIF a reset or by reading the ICG status register when ICGIF is set and then writing a 1 to ICGIF. If another ICG interrupt occurs before the clearing sequence is complete, the sequence is reset so ICGIF would remain set after the clear sequence was completed for the earlier interrupt. Writing a 0 to ICGIF has no effect. 0 No ICG interrupt request is pending. 1 An ICG interrupt request is pending. MC9S08GB60A Data Sheet, Rev. 2 126 Freescale Semiconductor

Internal Clock Generator (S08ICGV2) 7.5.4 ICG Status Register 2 (ICGS2) 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 DCOS W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure7-15. ICG Status Register 2 (ICGS2) Table7-9. ICGS2 Field Descriptions Field Description 0 DCO Clock Stable — The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error DCOS has not changed by more than n for two consecutive samples and the DCO clock is not static. This bit is unlock used when exiting off state if CLKS=X1 to determine when to switch to the requested clock mode. It is also used in self-clocked mode to determine when to start monitoring the DCO clock. This bit is cleared upon entering the off state. 0 DCO clock is unstable. 1 DCO clock is stable. 7.5.5 ICG Filter Registers (ICGFLTU, ICGFLTL) The filter registers show the filter value (FLT). 7 6 5 4 3 2 1 0 R 0 0 0 0 FLT W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure7-16. ICG Upper Filter Register (ICGFLTU) Table7-10. ICGFLTU Field Descriptions Field Description 3:0 Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are FLT read only except when the CLKS bits are programmed to self-clocked mode (CLKS=00). In self-clocked mode, any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if a previous latch sequence is not complete. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 127

Internal Clock Generator (S08ICGV2) 7 6 5 4 3 2 1 0 R FLT W Reset 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure7-17. ICG Upper Filter Register (ICGFLTL) Table7-11. ICGFLTL Field Descriptions Field Description 7:0 Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are FLT read only except when the CLKS bits are programmed to self-clocked mode (CLKS=00). In self-clocked mode, any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if a previous latch sequence is not complete. 7.5.6 ICG Trim Register (ICGTRM) 7 6 5 4 3 2 1 0 R TRIM W POR: 1 0 0 0 0 0 0 0 Reset: u u u u u u u u = Unimplemented or Reserved u = Unaffected by MCU reset Figure7-18. ICG Trim Register (ICGTRM) Table7-12. ICGTRM Field Descriptions Field Description 7:0 ICG Trim Setting — The TRIM bits control the internal reference generator frequency. They allow a ± 25% TRIM adjustment of the nominal (POR) period. The bit’s effect on period is binary weighted (i.e., bit 1 will adjust twice as much as changing bit 0). Increasing the binary value in TRIM will increase the period and decreasing the value will decrease the period. MC9S08GB60A Data Sheet, Rev. 2 128 Freescale Semiconductor

Chapter 8 Central Processor Unit (S08CPUV2) 8.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler efficiency and to support a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers (MCU). 8.1.1 Features Features of the HCS08 CPU include: • Object code fully upward-compatible with M68HC05 and M68HC08 Families • All registers and memory are mapped to a single 64-Kbyte address space • 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space) • 16-bit index register (H:X) with powerful indexed addressing modes • 8-bit accumulator (A) • Many instructions treat X as a second general-purpose 8-bit register • Seven addressing modes: — Inherent — Operands in internal registers — Relative — 8-bit signed offset to branch destination — Immediate — Operand in next object code byte(s) — Direct — Operand in memory at 0x0000–0x00FF — Extended — Operand anywhere in 64-Kbyte address space — Indexed relative to H:X — Five submodes including auto increment — Indexed relative to SP — Improves C efficiency dramatically • Memory-to-memory data move instructions with four address mode combinations • Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (BCD) operations • Efficient bit manipulation instructions • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • STOP and WAIT instructions to invoke low-power operating modes MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 129

Chapter8 Central Processor Unit (S08CPUV2) 8.2 Programmer’s Model and CPU Registers Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) INDEX REGISTER (LOW) X 15 8 7 0 STACK POINTER SP 15 0 PROGRAM COUNTER PC 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure8-1. CPU Registers 8.2.1 Accumulator (A) The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit (ALU) is connected to the accumulator and the ALU results are often stored into the A accumulator after arithmetic and logical operations. The accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data comes from, or the contents of A can be stored to memory using various addressing modes to specify the address where data from A will be stored. Reset has no effect on the contents of the A accumulator. 8.2.2 Index Register (H:X) This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit address pointer where H holds the upper byte of an address and X holds the lower byte of the address. All indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer; however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the low-order 8-bit half (X). Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data values. X can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. Transfer instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations can then be performed. For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect on the contents of X. MC9S08GB60A Data Sheet, Rev. 2 130 Freescale Semiconductor

Chapter8 Central Processor Unit (S08CPUV2) 8.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most often used to allocate or deallocate space for local variables on the stack. SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs normally change the value in SP to the address of the last location (highest address) in on-chip RAM during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF). The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer. 8.2.4 Program Counter (PC) The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. During normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location. This is called a change-of-flow. During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF. The vector stored there is the address of the first instruction that will be executed after exiting the reset state. 8.2.5 Condition Code Register (CCR) The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 131

Chapter8 Central Processor Unit (S08CPUV2) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure8-2. Condition Code Register Table8-1. CCR Register Field Descriptions Field Description 7 Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. V The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 0 No overflow 1 Overflow 4 Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during H an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the result to a valid BCD value. 0 No carry between bits 3 and 4 1 Carry between bits 3 and 4 3 Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts I are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the first instruction of the interrupt service routine is executed. Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening interrupt, provided I was set. 0 Interrupts enabled 1 Interrupts disabled 2 Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data N manipulation produces a negative result, setting bit7 of the result. Simply loading or storing an 8-bit or 16-bit value causes N to be set if the most significant bit of the loaded or stored value was 1. 0 Non-negative result 1 Negative result 1 Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation Z produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the loaded or stored value was all 0s. 0 Non-zero result 1 Zero result 0 Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit C 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 0 No carry out of bit 7 1 Carry out of bit 7 MC9S08GB60A Data Sheet, Rev. 2 132 Freescale Semiconductor

Chapter8 Central Processor Unit (S08CPUV2) 8.3 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space. Some instructions use more than one addressing mode. For instance, move instructions use one addressing mode to specify the source operand and a second addressing mode to specify the destination address. Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to specify the branch destination address when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 8.3.1 Inherent Addressing Mode (INH) In this addressing mode, operands needed to complete the instruction (if any) are located within CPU registers so the CPU does not need to access memory to get any operands. 8.3.2 Relative Addressing Mode (REL) Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit offset value is located in the memory location immediately following the opcode. During execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 8.3.3 Immediate Addressing Mode (IMM) In immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that. 8.3.4 Direct Addressing Mode (DIR) In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x0000–0x00FF). During execution a 16-bit address is formed by concatenating an implied 0x00 for the high-order half of the address and the direct address from the instruction to get the 16-bit address where the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit address for the operand. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 133

Chapter8 Central Processor Unit (S08CPUV2) 8.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 8.3.6 Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. 8.3.6.1 Indexed, No Offset (IX) This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed to complete the instruction. 8.3.6.2 Indexed, No Offset with Post Increment (IX+) This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed to complete the instruction. The index register pair is then incremented (H:X =H:X+ 0x0001) after the operand has been fetched. This addressing mode is only used for MOV and CBEQ instructions. 8.3.6.3 Indexed, 8-Bit Offset (IX1) This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. The index register pair is then incremented (H:X= H:X+ 0x0001) after the operand has been fetched. This addressing mode is used only for the CBEQ instruction. 8.3.6.5 Indexed, 16-Bit Offset (IX2) This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.3.6.6 SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. MC9S08GB60A Data Sheet, Rev. 2 134 Freescale Semiconductor

Chapter8 Central Processor Unit (S08CPUV2) 8.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU circuitry. This section provides additional information about these operations. 8.4.1 Reset Sequence Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction boundary before responding to a reset event). For a more detailed discussion about how the MCU recognizes resets and determines the source, refer to the Resets, Interrupts, and System Configuration chapter. The reset event is considered concluded when the sequence to determine whether the reset came from an internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for execution of the first program instruction. 8.4.2 Interrupt Sequence When an interrupt is requested, the CPU completes the current instruction before responding to the interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. The CPU sequence for an interrupt is: 1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order. 2. Set the I bit in the CCR. 3. Fetch the high-order half of the interrupt vector. 4. Fetch the low-order half of the interrupt vector. 5. Delay for one free bus cycle. 6. Fetch three bytes of program information starting at the address indicated by the interrupt vector to fill the instruction queue in preparation for execution of the first instruction in the interrupt service routine. After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 135

Chapter8 Central Processor Unit (S08CPUV2) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends the interrupt service routine. It is not necessary to save H if you are certain that the interrupt service routine does not use any instructions or auto-increment addressing modes that might change the value of H. The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 8.4.3 Wait Mode Operation The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume and the interrupt or reset event will be processed normally. If a serial BACKGROUND command is issued to the MCU through the background debug interface while the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in wait mode. 8.4.4 Stop Mode Operation Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to minimize power consumption. In such systems, external circuitry is needed to control the time spent in stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU fromstop mode. When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control bit has been set by a serial command through the background interface (or because the MCU was reset into active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this case, if a serial BACKGROUND command is issued to the MCU through the background debug interface while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation chapter for more details. MC9S08GB60A Data Sheet, Rev. 2 136 Freescale Semiconductor

Chapter8 Central Processor Unit (S08CPUV2) 8.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface. Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 137

Chapter8 Central Processor Unit (S08CPUV2) 8.5 HCS08 Instruction Set Summary Instruction Set Summary Nomenclature The nomenclature listed here is used in the instruction descriptions in Table 8-2. Operators ( ) = Contents of register or memory location shown inside parentheses ← = Is loaded with (read: “gets”) & = Boolean AND | = Boolean OR ⊕ = Boolean exclusive-OR × = Multiply ÷ = Divide : = Concatenate + = Add – = Negate (two’s complement) CPU registers A = Accumulator CCR = Condition code register H = Index register, higher order (most significant) 8 bits X = Index register, lower order (least significant) 8 bits PC = Program counter PCH = Program counter, higher order (most significant) 8 bits PCL = Program counter, lower order (least significant) 8 bits SP = Stack pointer Memory and addressing M = A memory location or absolute data, depending on addressing mode M:M + 0x0001= A 16-bit value in two consecutive memory locations. The higher-order (most significant) 8 bits are located at the address of M, and the lower-order (least significant) 8 bits are located at the next higher sequential address. Condition code register (CCR) bits V = Two’s complement overflow indicator, bit 7 H = Half carry, bit 4 I = Interrupt mask, bit 3 N = Negative indicator, bit 2 Z = Zero indicator, bit 1 C = Carry/borrow, bit 0 (carry out of bit 7) CCR activity notation – = Bit not affected MC9S08GB60A Data Sheet, Rev. 2 138 Freescale Semiconductor

Chapter8 Central Processor Unit (S08CPUV2) 0 = Bit forced to 0 1 = Bit forced to 1 Þ = Bit set or cleared according to results of operation U = Undefined after the operation Machine coding notation dd = Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00) ee = Upper 8 bits of 16-bit offset ff = Lower 8 bits of 16-bit offset or 8-bit offset ii = One byte of immediate data jj = High-order byte of a 16-bit immediate data value kk = Low-order byte of a 16-bit immediate data value hh = High-order byte of 16-bit extended address ll = Low-order byte of 16-bit extended address rr = Relative offset Source form Everything in the source forms columns, except expressions in italic characters, is literal information that must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a literal expression. All commas, pound signs (#), parentheses, and plus signs (+) are literal characters. n — Any label or expression that evaluates to a single integer in the range 0–7 opr8i — Any label or expression that evaluates to an 8-bit immediate value opr16i — Any label or expression that evaluates to a 16-bit immediate value opr8a — Any label or expression that evaluates to an 8-bit value. The instruction treats this 8-bit value as the low order 8 bits of an address in the direct page of the 64-Kbyte address space (0x00xx). opr16a — Any label or expression that evaluates to a 16-bit value. The instruction treats this value as an address in the 64-Kbyte address space. oprx8 — Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing oprx16 — Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a 16-bit address bus, this can be either a signed or an unsigned value. rel — Any label or expression that refers to an address that is within –128 to +127 locations from the next address after the last byte of object code for the current instruction. The assembler will calculate the 8-bit signed offset and include it in the object code for this instruction. Address modes INH = Inherent (no operands) IMM = 8-bit or 16-bit immediate DIR = 8-bit direct EXT = 16-bit extended MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 139

Chapter8 Central Processor Unit (S08CPUV2) IX = 16-bit indexed no offset IX+ = 16-bit indexed no offset, post increment (CBEQ and MOV only) IX1 = 16-bit indexed with 8-bit offset from H:X IX1+ = 16-bit indexed with 8-bit offset, post increment (CBEQ only) IX2 = 16-bit indexed with 16-bit offset from H:X REL = 8-bit relative offset SP1 = Stack pointer with 8-bit offset SP2 = Stack pointer with 16-bit offset Table8-2. HCS08 Instruction Set Summary (Sheet 1 of 7) Effect 1s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B ADC #opr8i IMM A9 ii 2 ADC opr8a DIR B9 dd 3 ADC opr16a EXT C9 hh ll 4 ADC oprx16,X IX2 D9 ee ff 4 Add with Carry A ← (A) + (M) + (C) (cid:166) (cid:166) – (cid:166) (cid:166) (cid:166) ADC oprx8,X IX1 E9 ff 3 ADC ,X IX F9 3 ADC oprx16,SP SP2 9ED9 ee ff 5 ADC oprx8,SP SP1 9EE9 ff 4 ADD #opr8i IMM AB ii 2 ADD opr8a DIR BB dd 3 ADD opr16a EXT CB hh ll 4 ADD oprx16,X IX2 DB ee ff 4 Add without Carry A ← (A) + (M) (cid:166) (cid:166) – (cid:166) (cid:166) (cid:166) ADD oprx8,X IX1 EB ff 3 ADD ,X IX FB 3 ADD oprx16,SP SP2 9EDB ee ff 5 ADD oprx8,SP SP1 9EEB ff 4 Add Immediate Value SP ← (SP) + (M) AIS #opr8i – – – – – – IMM A7 ii 2 (Signed) to Stack Pointer M is sign extended to a 16-bit value Add Immediate Value H:X ← (H:X) + (M) AIX #opr8i (Signed) to Index – – – – – – IMM AF ii 2 M is sign extended to a 16-bit value Register (H:X) AND #opr8i IMM A4 ii 2 AND opr8a DIR B4 dd 3 AND opr16a EXT C4 hh ll 4 AND oprx16,X IX2 D4 ee ff 4 Logical AND A ← (A) & (M) 0 – – (cid:166) (cid:166) – AND oprx8,X IX1 E4 ff 3 AND ,X IX F4 3 AND oprx16,SP SP2 9ED4 ee ff 5 AND oprx8,SP SP1 9EE4 ff 4 ASL opr8a DIR 38 dd 5 ASLA INH 48 1 ASLX Arithmetic Shift Left INH 58 1 ASL oprx8,X (Same as LSL) C 0 (cid:166) – – (cid:166) (cid:166) (cid:166) IX1 68 ff 5 ASL ,X b7 b0 IX 78 4 ASL oprx8,SP SP1 9E68 ff 6 ASR opr8a DIR 37 dd 5 ASRA INH 47 1 ASRX Arithmetic Shift Right C (cid:166) – – (cid:166) (cid:166) (cid:166) INH 57 1 ASR oprx8,X IX1 67 ff 5 b7 b0 ASR ,X IX 77 4 ASR oprx8,SP SP1 9E67 ff 6 BCC rel Branch if Carry Bit Clear Branch if (C) = 0 – – – – – – REL 24 rr 3 MC9S08GB60A Data Sheet, Rev. 2 140 Freescale Semiconductor

Chapter8 Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 2 of 7) Effect 1 s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B DIR (b0) 11 dd 5 DIR (b1) 13 dd 5 DIR (b2) 15 dd 5 DIR (b3) 17 dd 5 BCLR n,opr8a Clear Bit n in Memory Mn ← 0 – – – – – – DIR (b4) 19 dd 5 DIR (b5) 1B dd 5 DIR (b6) 1D dd 5 DIR (b7) 1F dd 5 Branch if Carry Bit Set BCS rel Branch if (C) = 1 – – – – – – REL 25 rr 3 (Same as BLO) BEQ rel Branch if Equal Branch if (Z) = 1 – – – – – – REL 27 rr 3 Branch if Greater Than or BGE rel Equal To Branch if (N ⊕ V) = 0 – – – – – – REL 90 rr 3 (Signed Operands) Waits For and Processes BDM Enter Active Background BGND Commands Until GO, TRACE1, or – – – – – – INH 82 5+ if ENBDM = 1 TAGGO Branch if Greater Than BGT rel Branch if (Z) | (N ⊕ V) = 0 – – – – – – REL 92 rr 3 (Signed Operands) Branch if Half Carry Bit BHCC rel Branch if (H) = 0 – – – – – – REL 28 rr 3 Clear Branch if Half Carry Bit BHCS rel Branch if (H) = 1 – – – – – – REL 29 rr 3 Set BHI rel Branch if Higher Branch if (C) | (Z) = 0 – – – – – – REL 22 rr 3 Branch if Higher or Same BHS rel Branch if (C) = 0 – – – – – – REL 24 rr 3 (Same as BCC) BIH rel Branch if IRQ Pin High Branch if IRQ pin = 1 – – – – – – REL 2F rr 3 BIL rel Branch if IRQ Pin Low Branch if IRQ pin = 0 – – – – – – REL 2E rr 3 BIT #opr8i IMM A5 ii 2 BIT opr8a DIR B5 dd 3 BIT opr16a EXT C5 hh ll 4 (A) & (M) BIT oprx16,X IX2 D5 ee ff 4 Bit Test (CCR Updated but Operands 0 – – (cid:166) (cid:166) – BIT oprx8,X IX1 E5 ff 3 Not Changed) BIT ,X IX F5 3 BIT oprx16,SP SP2 9ED5 ee ff 5 BIT oprx8,SP SP1 9EE5 ff 4 Branch if Less Than BLE rel or Equal To Branch if (Z) | (N ⊕ V) = 1 – – – – – – REL 93 rr 3 (Signed Operands) Branch if Lower BLO rel Branch if (C) = 1 – – – – – – REL 25 rr 3 (Same as BCS) BLS rel Branch if Lower or Same Branch if (C) | (Z) = 1 – – – – – – REL 23 rr 3 Branch if Less Than BLT rel Branch if (N ⊕ V ) = 1 – – – – – – REL 91 rr 3 (Signed Operands) Branch if Interrupt Mask BMC rel Branch if (I) = 0 – – – – – – REL 2C rr 3 Clear BMI rel Branch if Minus Branch if (N) = 1 – – – – – – REL 2B rr 3 Branch if Interrupt Mask BMS rel Branch if (I) = 1 – – – – – – REL 2D rr 3 Set BNE rel Branch if Not Equal Branch if (Z) = 0 – – – – – – REL 26 rr 3 BPL rel Branch if Plus Branch if (N) = 0 – – – – – – REL 2A rr 3 BRA rel Branch Always No Test – – – – – – REL 20 rr 3 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 141

Chapter8 Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 3 of 7) Effect 1 s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B DIR (b0) 01 dd rr 5 DIR (b1) 03 dd rr 5 DIR (b2) 05 dd rr 5 Branch if Bit n in Memory DIR (b3) 07 dd rr 5 BRCLR n,opr8a,rel Branch if (Mn) = 0 – – – – – (cid:166) Clear DIR (b4) 09 dd rr 5 DIR (b5) 0B dd rr 5 DIR (b6) 0D dd rr 5 DIR (b7) 0F dd rr 5 BRN rel Branch Never Uses 3 Bus Cycles – – – – – – REL 21 rr 3 DIR (b0) 00 dd rr 5 DIR (b1) 02 dd rr 5 DIR (b2) 04 dd rr 5 Branch if Bit n in Memory DIR (b3) 06 dd rr 5 BRSET n,opr8a,rel Branch if (Mn) = 1 – – – – – (cid:166) Set DIR (b4) 08 dd rr 5 DIR (b5) 0A dd rr 5 DIR (b6) 0C dd rr 5 DIR (b7) 0E dd rr 5 DIR (b0) 10 dd 5 DIR (b1) 12 dd 5 DIR (b2) 14 dd 5 DIR (b3) 16 dd 5 BSET n,opr8a Set Bit n in Memory Mn ← 1 – – – – – – DIR (b4) 18 dd 5 DIR (b5) 1A dd 5 DIR (b6) 1C dd 5 DIR (b7) 1E dd 5 PC ← (PC) + 0x0002 push (PCL); SP ← (SP) – 0x0001 BSR rel Branch to Subroutine – – – – – – REL AD rr 5 push (PCH); SP ← (SP) – 0x0001 PC ← (PC) + rel CBEQ opr8a,rel Branch if (A) = (M) DIR 31 dd rr 5 CBEQA #opr8i,rel Branch if (A) = (M) IMM 41 ii rr 4 CBEQX #opr8i,rel Compare and Branch if Branch if (X) = (M) IMM 51 ii rr 4 – – – – – – CBEQ oprx8,X+,rel Equal Branch if (A) = (M) IX1+ 61 ff rr 5 CBEQ ,X+,rel Branch if (A) = (M) IX+ 71 rr 5 CBEQ oprx8,SP,rel Branch if (A) = (M) SP1 9E61 ff rr 6 CLC Clear Carry Bit C ← 0 – – – – – 0 INH 98 1 CLI Clear Interrupt Mask Bit I ← 0 – – 0 – – – INH 9A 1 CLR opr8a M ← 0x00 DIR 3F dd 5 CLRA A ← 0x00 INH 4F 1 CLRX X ← 0x00 INH 5F 1 CLRH Clear H ← 0x00 0 – – 0 1 – INH 8C 1 CLR oprx8,X M ← 0x00 IX1 6F ff 5 CLR ,X M ← 0x00 IX 7F 4 CLR oprx8,SP M ← 0x00 SP1 9E6F ff 6 CMP #opr8i IMM A1 ii 2 CMP opr8a DIR B1 dd 3 CMP opr16a EXT C1 hh ll 4 (A) – (M) CMP oprx16,X Compare Accumulator IX2 D1 ee ff 4 (CCR Updated But Operands Not (cid:166) – – (cid:166) (cid:166) (cid:166) CMP oprx8,X with Memory IX1 E1 ff 3 Changed) CMP ,X IX F1 3 CMP oprx16,SP SP2 9ED1 ee ff 5 CMP oprx8,SP SP1 9EE1 ff 4 COM opr8a M ← (M)= 0xFF – (M) DIR 33 dd 5 COMA A ← (A) = 0xFF – (A) INH 43 1 COMX Complement X ← (X) = 0xFF – (X) INH 53 1 0 – – (cid:166) (cid:166) 1 COM oprx8,X (One’s Complement) M ← (M) = 0xFF – (M) IX1 63 ff 5 COM ,X M ← (M) = 0xFF – (M) IX 73 4 COM oprx8,SP M ← (M) = 0xFF – (M) SP1 9E63 ff 6 CPHX opr16a EXT 3E hh ll 6 (H:X) – (M:M + 0x0001) CPHX #opr16i Compare Index Register IMM 65 jj kk 3 (CCR Updated But Operands Not (cid:166) – – (cid:166) (cid:166) (cid:166) CPHX opr8a (H:X) with Memory DIR 75 dd 5 Changed) CPHX oprx8,SP SP1 9EF3 ff 6 MC9S08GB60A Data Sheet, Rev. 2 142 Freescale Semiconductor

Chapter8 Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 4 of 7) Effect 1 s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B CPX #opr8i IMM A3 ii 2 CPX opr8a DIR B3 dd 3 CPX opr16a EXT C3 hh ll 4 Compare X (Index (X) – (M) CPX oprx16,X IX2 D3 ee ff 4 Register Low) with (CCR Updated But Operands Not (cid:166) – – (cid:166) (cid:166) (cid:166) CPX oprx8,X IX1 E3 ff 3 Memory Changed) CPX ,X IX F3 3 CPX oprx16,SP SP2 9ED3 ee ff 5 CPX oprx8,SP SP1 9EE3 ff 4 Decimal Adjust DAA Accumulator After ADD or (A) U – – (cid:166) (cid:166) (cid:166) INH 72 1 10 ADC of BCD Values DBNZ opr8a,rel DIR 3B dd rr 7 DBNZA rel INH 4B rr 4 Decrement A, X, or M DBNZX rel Decrement and Branch if INH 5B rr 4 Branch if (result) ≠ 0 – – – – – – DBNZ oprx8,X,rel Not Zero IX1 6B ff rr 7 DBNZX Affects X Not H DBNZ ,X,rel IX 7B rr 6 DBNZ oprx8,SP,rel SP1 9E6B ff rr 8 DEC opr8a M ← (M) – 0x01 DIR 3A dd 5 DECA A ← (A) – 0x01 INH 4A 1 DECX X ← (X) – 0x01 INH 5A 1 Decrement (cid:166) – – (cid:166) (cid:166) – DEC oprx8,X M ← (M) – 0x01 IX1 6A ff 5 DEC ,X M ← (M) – 0x01 IX 7A 4 DEC oprx8,SP M ← (M) – 0x01 SP1 9E6A ff 6 A ← (H:A)÷(X) DIV Divide – – – – (cid:166) (cid:166) INH 52 6 H ← Remainder EOR #opr8i IMM A8 ii 2 EOR opr8a DIR B8 dd 3 EOR opr16a EXT C8 hh ll 4 Exclusive OR EOR oprx16,X IX2 D8 ee ff 4 Memory with A ← (A ⊕ M) 0 – – (cid:166) (cid:166) – EOR oprx8,X IX1 E8 ff 3 Accumulator EOR ,X IX F8 3 EOR oprx16,SP SP2 9ED8 ee ff 5 EOR oprx8,SP SP1 9EE8 ff 4 INC opr8a M ← (M) + 0x01 DIR 3C dd 5 INCA A ← (A) + 0x01 INH 4C 1 INCX X ← (X) + 0x01 INH 5C 1 Increment (cid:166) – – (cid:166) (cid:166) – INC oprx8,X M ← (M) + 0x01 IX1 6C ff 5 INC ,X M ← (M) + 0x01 IX 7C 4 INC oprx8,SP M ← (M) + 0x01 SP1 9E6C ff 6 JMP opr8a DIR BC dd 3 JMP opr16a EXT CC hh ll 4 JMP oprx16,X Jump PC ← Jump Address – – – – – – IX2 DC ee ff 4 JMP oprx8,X IX1 EC ff 3 JMP ,X IX FC 3 JSR opr8a DIR BD dd 5 PC ← (PC) + n (n = 1, 2, or 3) JSR opr16a EXT CD hh ll 6 Push (PCL); SP ← (SP) – 0x0001 JSR oprx16,X Jump to Subroutine – – – – – – IX2 DD ee ff 6 Push (PCH); SP ← (SP) – 0x0001 JSR oprx8,X IX1 ED ff 5 PC ← Unconditional Address JSR ,X IX FD 5 LDA #opr8i IMM A6 ii 2 LDA opr8a DIR B6 dd 3 LDA opr16a EXT C6 hh ll 4 LDA oprx16,X Load Accumulator from IX2 D6 ee ff 4 A ← (M) 0 – – (cid:166) (cid:166) – LDA oprx8,X Memory IX1 E6 ff 3 LDA ,X IX F6 3 LDA oprx16,SP SP2 9ED6 ee ff 5 LDA oprx8,SP SP1 9EE6 ff 4 LDHX #opr16i IMM 45 jj kk 3 LDHX opr8a DIR 55 dd 4 LDHX opr16a EXT 32 hh ll 5 Load Index Register (H:X) LDHX ,X H:X ← (M:M + 0x0001) 0 – – (cid:166) (cid:166) – IX 9EAE 5 from Memory LDHX oprx16,X IX2 9EBE ee ff 6 LDHX oprx8,X IX1 9ECE ff 5 LDHX oprx8,SP SP1 9EFE ff 5 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 143

Chapter8 Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 5 of 7) Effect 1 s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B LDX #opr8i IMM AE ii 2 LDX opr8a DIR BE dd 3 LDX opr16a EXT CE hh ll 4 LDX oprx16,X Load X (Index Register IX2 DE ee ff 4 X ← (M) 0 – – (cid:166) (cid:166) – LDX oprx8,X Low) from Memory IX1 EE ff 3 LDX ,X IX FE 3 LDX oprx16,SP SP2 9EDE ee ff 5 LDX oprx8,SP SP1 9EEE ff 4 LSL opr8a DIR 38 dd 5 LSLA INH 48 1 LSLX Logical Shift Left C 0 (cid:166) – – (cid:166) (cid:166) (cid:166) INH 58 1 LSL oprx8,X (Same as ASL) IX1 68 ff 5 b7 b0 LSL ,X IX 78 4 LSL oprx8,SP SP1 9E68 ff 6 LSR opr8a DIR 34 dd 5 LSRA INH 44 1 LSRX Logical Shift Right 0 C (cid:166) – – 0 (cid:166) (cid:166) INH 54 1 LSR oprx8,X IX1 64 ff 5 b7 b0 LSR ,X IX 74 4 LSR oprx8,SP SP1 9E64 ff 6 MOV opr8a,opr8a (M) ← (M) DIR/DIR 4E dd dd 5 destination source MOV opr8a,X+ DIR/IX+ 5E dd 5 Move 0 – – (cid:166) (cid:166) – MOV #opr8i,opr8a H:X ← (H:X) + 0x0001 in IMM/DIR 6E ii dd 4 MOV ,X+,opr8a IX+/DIR and DIR/IX+ Modes IX+/DIR 7E dd 5 MUL Unsigned multiply X:A ← (X) × (A) – 0 – – – 0 INH 42 5 NEG opr8a M ← – (M) = 0x00 – (M) DIR 30 dd 5 NEGA A ← – (A) = 0x00 – (A) INH 40 1 NEGX Negate X ← – (X) = 0x00 – (X) INH 50 1 (cid:166) – – (cid:166) (cid:166) (cid:166) NEG oprx8,X (Two’s Complement) M ← – (M) = 0x00 – (M) IX1 60 ff 5 NEG ,X M ← – (M) = 0x00 – (M) IX 70 4 NEG oprx8,SP M ← – (M) = 0x00 – (M) SP1 9E60 ff 6 NOP No Operation Uses 1 Bus Cycle – – – – – – INH 9D 1 Nibble Swap NSA A ← (A[3:0]:A[7:4]) – – – – – – INH 62 1 Accumulator ORA #opr8i IMM AA ii 2 ORA opr8a DIR BA dd 3 ORA opr16a EXT CA hh ll 4 ORA oprx16,X Inclusive OR Accumulator IX2 DA ee ff 4 A ← (A) | (M) 0 – – (cid:166) (cid:166) – ORA oprx8,X and Memory IX1 EA ff 3 ORA ,X IX FA 3 ORA oprx16,SP SP2 9EDA ee ff 5 ORA oprx8,SP SP1 9EEA ff 4 Push Accumulator onto PSHA Push (A); SP ← (SP) – 0x0001 – – – – – – INH 87 2 Stack Push H (Index Register PSHH Push (H); SP ← (SP) – 0x0001 – – – – – – INH 8B 2 High) onto Stack Push X (Index Register PSHX Push (X); SP ← (SP) – 0x0001 – – – – – – INH 89 2 Low) onto Stack Pull Accumulator from PULA SP ← (SP + 0x0001); Pull (A) – – – – – – INH 86 3 Stack Pull H (Index Register PULH SP ← (SP + 0x0001); Pull (H) – – – – – – INH 8A 3 High) from Stack Pull X (Index Register PULX SP ← (SP + 0x0001); Pull (X) – – – – – – INH 88 3 Low) from Stack ROL opr8a DIR 39 dd 5 ROLA INH 49 1 ROLX Rotate Left through Carry C (cid:166) – – (cid:166) (cid:166) (cid:166) INH 59 1 ROL oprx8,X IX1 69 ff 5 ROL ,X b7 b0 IX 79 4 ROL oprx8,SP SP1 9E69 ff 6 MC9S08GB60A Data Sheet, Rev. 2 144 Freescale Semiconductor

Chapter8 Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 6 of 7) Effect 1 s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B ROR opr8a DIR 36 dd 5 RORA INH 46 1 RORX Rotate Right through C (cid:166) – – (cid:166) (cid:166) (cid:166) INH 56 1 ROR oprx8,X Carry IX1 66 ff 5 ROR ,X b7 b0 IX 76 4 ROR oprx8,SP SP1 9E66 ff 6 SP ← 0xFF RSP Reset Stack Pointer – – – – – – INH 9C 1 (High Byte Not Affected) SP ← (SP) + 0x0001; Pull (CCR) SP ← (SP) + 0x0001; Pull (A) RTI Return from Interrupt SP ← (SP) + 0x0001; Pull (X) (cid:166) (cid:166) (cid:166) (cid:166) (cid:166) (cid:166) INH 80 9 SP ← (SP) + 0x0001; Pull (PCH) SP ← (SP) + 0x0001; Pull (PCL) SP ← SP + 0x0001; Pull (PCH) RTS Return from Subroutine – – – – – – INH 81 6 SP ← SP + 0x0001; Pull (PCL) SBC #opr8i IMM A2 ii 2 SBC opr8a DIR B2 dd 3 SBC opr16a EXT C2 hh ll 4 SBC oprx16,X IX2 D2 ee ff 4 Subtract with Carry A ← (A) – (M) – (C) (cid:166) – – (cid:166) (cid:166) (cid:166) SBC oprx8,X IX1 E2 ff 3 SBC ,X IX F2 3 SBC oprx16,SP SP2 9ED2 ee ff 5 SBC oprx8,SP SP1 9EE2 ff 4 SEC Set Carry Bit C ← 1 – – – – – 1 INH 99 1 SEI Set Interrupt Mask Bit I ← 1 – – 1 – – – INH 9B 1 STA opr8a DIR B7 dd 3 STA opr16a EXT C7 hh ll 4 STA oprx16,X IX2 D7 ee ff 4 Store Accumulator in STA oprx8,X M ← (A) 0 – – (cid:166) (cid:166) – IX1 E7 ff 3 Memory STA ,X IX F7 2 STA oprx16,SP SP2 9ED7 ee ff 5 STA oprx8,SP SP1 9EE7 ff 4 STHX opr8a DIR 35 dd 4 STHX opr16a Store H:X (Index Reg.) (M:M + 0x0001) ← (H:X) 0 – – (cid:166) (cid:166) – EXT 96 hh ll 5 STHX oprx8,SP SP1 9EFF ff 5 Enable Interrupts: Stop Processing STOP I bit ← 0; Stop Processing – – 0 – – – INH 8E 2+ Refer to MCU Documentation STX opr8a DIR BF dd 3 STX opr16a EXT CF hh ll 4 STX oprx16,X Store X (Low 8 Bits of IX2 DF ee ff 4 STX oprx8,X Index Register) M ← (X) 0 – – (cid:166) (cid:166) – IX1 EF ff 3 STX ,X in Memory IX FF 2 STX oprx16,SP SP2 9EDF ee ff 5 STX oprx8,SP SP1 9EEF ff 4 SUB #opr8i IMM A0 ii 2 SUB opr8a DIR B0 dd 3 SUB opr16a EXT C0 hh ll 4 SUB oprx16,X IX2 D0 ee ff 4 Subtract A ← (A) – (M) (cid:166) – – (cid:166) (cid:166) (cid:166) SUB oprx8,X IX1 E0 ff 3 SUB ,X IX F0 3 SUB oprx16,SP SP2 9ED0 ee ff 5 SUB oprx8,SP SP1 9EE0 ff 4 PC ← (PC) + 0x0001 Push (PCL); SP ← (SP) – 0x0001 Push (PCH); SP ← (SP) – 0x0001 Push (X); SP ← (SP) – 0x0001 SWI Software Interrupt Push (A); SP ← (SP) – 0x0001 – – 1 – – – INH 83 11 Push (CCR); SP ← (SP) – 0x0001 I ← 1; PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 145

Chapter8 Central Processor Unit (S08CPUV2) Table8-2. HCS08 Instruction Set Summary (Sheet 7 of 7) Effect 1 s SFoourrmce Operation Description on CCR dressode code erand Cycle V H I N Z C AdM Op Op us B Transfer Accumulator to TAP CCR ← (A) (cid:166) (cid:166) (cid:166) (cid:166) (cid:166) (cid:166) INH 84 1 CCR Transfer Accumulator to TAX X ← (A) – – – – – – INH 97 1 X (Index Register Low) Transfer CCR to TPA A ← (CCR) – – – – – – INH 85 1 Accumulator TST opr8a (M) – 0x00 DIR 3D dd 4 TSTA (A) – 0x00 INH 4D 1 TSTX (X) – 0x00 INH 5D 1 Test for Negative or Zero 0 – – (cid:166) (cid:166) – TST oprx8,X (M) – 0x00 IX1 6D ff 4 TST ,X (M) – 0x00 IX 7D 3 TST oprx8,SP (M) – 0x00 SP1 9E6D ff 5 TSX Transfer SP to Index Reg. H:X ← (SP) + 0x0001 – – – – – – INH 95 2 Transfer X (Index Reg. TXA A ← (X) – – – – – – INH 9F 1 Low) to Accumulator TXS Transfer Index Reg. to SP SP ← (H:X) – 0x0001 – – – – – – INH 94 2 Enable Interrupts; Wait WAIT I bit ← 0; Halt CPU – – 0 – – – INH 8F 2+ for Interrupt 1 Bus clock frequency is one-half of the CPU clock frequency. MC9S08GB60A Data Sheet, Rev. 2 146 Freescale Semiconductor

Chapter8 Central Processor Unit (S08CPUV2) Table8-3. Opcode Map (Sheet 1 of 2) Bit-Manipulation Branch Read-Modify-Write Control Register/Memory 00 5 10 5 20 3 30 5 40 1 50 1 60 5 70 4 80 9 90 3 A0 2 B0 3 C0 4 D0 4 E0 3 F0 3 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI BGE SUB SUB SUB SUB SUB SUB 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 01 5 11 5 21 3 31 5 41 4 51 4 61 5 71 5 81 6 91 3 A1 2 B1 3 C1 4 D1 4 E1 3 F1 3 BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ RTS BLT CMP CMP CMP CMP CMP CMP 3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 02 5 12 5 22 3 32 5 42 5 52 6 62 1 72 1 82 5+ 92 3 A2 2 B2 3 C2 4 D2 4 E2 3 F2 3 BRSET1 BSET1 BHI LDHX MUL DIV NSA DAA BGND BGT SBC SBC SBC SBC SBC SBC 3 DIR 2 DIR 2 REL 3 EXT 1 INH 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 03 5 13 5 23 3 33 5 43 1 53 1 63 5 73 4 83 11 93 3 A3 2 B3 3 C3 4 D3 4 E3 3 F3 3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI BLE CPX CPX CPX CPX CPX CPX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 04 5 14 5 24 3 34 5 44 1 54 1 64 5 74 4 84 1 94 2 A4 2 B4 3 C4 4 D4 4 E4 3 F4 3 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR TAP TXS AND AND AND AND AND AND 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 05 5 15 5 25 3 35 4 45 3 55 4 65 3 75 5 85 1 95 2 A5 2 B5 3 C5 4 D5 4 E5 3 F5 3 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT 3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 06 5 16 5 26 3 36 5 46 1 56 1 66 5 76 4 86 3 96 5 A6 2 B6 3 C6 4 D6 4 E6 3 F6 3 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR PULA STHX LDA LDA LDA LDA LDA LDA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 3 EXT 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 07 5 17 5 27 3 37 5 47 1 57 1 67 5 77 4 87 2 97 1 A7 2 B7 3 C7 4 D7 4 E7 3 F7 2 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR PSHA TAX AIS STA STA STA STA STA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 08 5 18 5 28 3 38 5 48 1 58 1 68 5 78 4 88 3 98 1 A8 2 B8 3 C8 4 D8 4 E8 3 F8 3 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 09 5 19 5 29 3 39 5 49 1 59 1 69 5 79 4 89 2 99 1 A9 2 B9 3 C9 4 D9 4 E9 3 F9 3 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0A 5 1A 5 2A 3 3A 5 4A 1 5A 1 6A 5 7A 4 8A 3 9A 1 AA 2 BA 3 CA 4 DA 4 EA 3 FA 3 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC PULH CLI ORA ORA ORA ORA ORA ORA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0B 5 1B 5 2B 3 3B 7 4B 4 5B 4 6B 7 7B 6 8B 2 9B 1 AB 2 BB 3 CB 4 DB 4 EB 3 FB 3 BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD 3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 INH 3 IX1 2 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0C 5 1C 5 2C 3 3C 5 4C 1 5C 1 6C 5 7C 4 8C 1 9C 1 BC 3 CC 4 DC 4 EC 3 FC 3 BRSET6 BSET6 BMC INC INCA INCX INC INC CLRH RSP JMP JMP JMP JMP JMP 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0D 5 1D 5 2D 3 3D 4 4D 1 5D 1 6D 4 7D 3 9D 1 AD 5 BD 5 CD 6 DD 6 ED 5 FD 5 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0E 5 1E 5 2E 3 3E 6 4E 5 5E 5 6E 4 7E 5 8E 2+ 9E AE 2 BE 3 CE 4 DE 4 EE 3 FE 3 BRSET7 BSET7 BIL CPHX MOV MOV MOV MOV STOP Page 2 LDX LDX LDX LDX LDX LDX 3 DIR 2 DIR 2 REL 3 EXT 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0F 5 1F 5 2F 3 3F 5 4F 1 5F 1 6F 5 7F 4 8F 2+ 9F 1 AF 2 BF 3 CF 4 DF 4 EF 3 FF 2 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA AIX STX STX STX STX STX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Opcode in Hexadecimal F0 3 HCS08 Cycles SUB Instruction Mnemonic Number of Bytes 1 IX Addressing Mode MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 147

Chapter8 Central Processor Unit (S08CPUV2) Table8-3. Opcode Map (Sheet 2 of 2) Bit-Manipulation Branch Read-Modify-Write Control Register/Memory 9E60 6 9ED0 5 9EE0 4 NEG SUB SUB 3 SP1 4 SP2 3 SP1 9E61 6 9ED1 5 9EE1 4 CBEQ CMP CMP 4 SP1 4 SP2 3 SP1 9ED2 5 9EE2 4 SBC SBC 4 SP2 3 SP1 9E63 6 9ED3 5 9EE3 4 9EF3 6 COM CPX CPX CPHX 3 SP1 4 SP2 3 SP1 3 SP1 9E64 6 9ED4 5 9EE4 4 LSR AND AND 3 SP1 4 SP2 3 SP1 9ED5 5 9EE5 4 BIT BIT 4 SP2 3 SP1 9E66 6 9ED6 5 9EE6 4 ROR LDA LDA 3 SP1 4 SP2 3 SP1 9E67 6 9ED7 5 9EE7 4 ASR STA STA 3 SP1 4 SP2 3 SP1 9E68 6 9ED8 5 9EE8 4 LSL EOR EOR 3 SP1 4 SP2 3 SP1 9E69 6 9ED9 5 9EE9 4 ROL ADC ADC 3 SP1 4 SP2 3 SP1 9E6A 6 9EDA 5 9EEA 4 DEC ORA ORA 3 SP1 4 SP2 3 SP1 9E6B 8 9EDB 5 9EEB 4 DBNZ ADD ADD 4 SP1 4 SP2 3 SP1 9E6C 6 INC 3 SP1 9E6D 5 TST 3 SP1 9EAE 5 9EBE 6 9ECE 5 9EDE 5 9EEE 4 9EFE 5 LDHX LDHX LDHX LDX LDX LDHX 2 IX 4 IX2 3 IX1 4 SP2 3 SP1 3 SP1 9E6F 6 9EDF 5 9EEF 4 9EFF 5 CLR STX STX STHX 3 SP1 4 SP2 3 SP1 3 SP1 INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Prebyte (9E) and Opcode in Hexadecimal 9E60 6 HCS08 Cycles NEG Instruction Mnemonic Number of Bytes 3 SP1 Addressing Mode MC9S08GB60A Data Sheet, Rev. 2 148 Freescale Semiconductor

Chapter 9 Keyboard Interrupt (S08KBIV1) 9.1 Introduction The MC9S08GBxxA/GTxxA has one KBI module with eight keyboard interrupt inputs that share port A pins. See Chapter2, “Pins and Connections” for more information about the logic and hardware aspects of these pins. 9.1.1 Port A and Keyboard Interrupt Pins PTA7/ PTA6/ PTA5/ PTA4/ PTA3/ PTA2/ PTA1/ PTA0/ MCU Pin: KBI1P7 KBI1P6 KBI1P5 KBI1P4 KBI1P3 KBI1P2 KBI1P1 KBI1P0 Figure9-1. Port A Pin Names The following paragraphs discuss controlling the keyboard interrupt pins. Port A is an 8-bit port which is shared among the KBI keyboard interrupt inputs and general-purpose I/O. The eight KBIPEn control bits in the KBIPE register allow selection of any combination of port A pins to be assigned as KBI inputs. Any pins which are enabled as KBI inputs will be forced to act as inputs and the remaining port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD), data direction (PTADD), and pullup enable (PTAPE) registers. KBI inputs can be configured for edge-only sensitivity or edge-and-level sensitivity. Bits 3 through 0 of port A are falling-edge/low-level sensitive while bits 7 through 4 can be configured for rising-edge/high-level or for falling-edge/low-level sensitivity. The eight PTAPEn control bits in the PTAPE register allow you to select whether an internal pullup device is enabled on each port A pin that is configured as an input. When any of bits 7 through 4 of port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits enable pulldown rather than pullup devices. An enabled keyboard interrupt can be used to wake the MCU from wait or standby (stop3). 9.2 Features The keyboard interrupt (KBI) module features include: • Keyboard interrupts selectable on eight port pins: — Four falling-edge/low-level sensitive — Four falling-edge/low-level or rising-edge/high-level sensitive — Choice of edge-only or edge-and-level sensitivity — Common interrupt flag and interrupt enable control — Capable of waking up the MCU from stop3 or wait mode MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 149

Chapter9 Keyboard Interrupt (S08KBIV1) HCS08 CORE DEBUG MODULE (DBG) A CPU BDC 8 RT 8 PTA7/KBI1P7– 8-BIT KEYBOARD PO PTA0/KBI1P0 INTERRUPT MODULE (KBI1) HCS08 SYSTEM CONTROL B RESET RESETS AND INTERRUPTS CANOANLVOEG(RA-TTTEDOR1-D )(1IG0-ITBAITL) 8 PORT 8 PPTTBB07//AADD11PP07– MODES OF OPERATION POWER MANAGEMENT PTC7 PTC6 RTI COP PTC5 C IRQ IRQ LVD IIC MODULE SCL1 RT PTC4 (IIC1) O PTC3/SCL1 SDA1 P PTC2/SDA1 SCL1 PTC1/RxD2 SERIAL COMMUNICATIONS SCL1 PTC0/TxD2 INTERFACE MODULE USER FLASH (SCI2) PTD7/TPM2CH4 (Gx60A = 61,268 BYTES) PTD6/TPM2CH3 (Gx32A = 32,768 BYTES) 5-CHANNMEOLD TUILMEER/PWM 5 T D PPTTDD45//TTPPMM22CCHH12 R PTD3/TPM2CH0 (TPM2) O 3 P PTD2/TPM1CH2 USER RAM PTD1/TPM1CH1 3-CHANNEL TIMER/PWM (Gx60A = 4096 BYTES) PTD0/TPM1CH0 MODULE (Gx32A = 2048 BYTES) (TPM1) PTE7 PTE6 SPSCK1 VVDDAD SERIAL PERIPHERAL MOSI1 T E PPTTEE45//MSPOSSCI1K1 VSRSEAFDH INTERF(ASCPEI1 M)ODULE MSSIS1O1 POR PTE3/MISO1 V PTE2/SS1 REFL RxD1 PTE1/RxD1 SERIAL COMMUNICATIONS TxD1 VDD VOLTAGE INTERFACE MODULE PTE0/TxD1 (SCI1) V REGULATOR SS T F 8 R PTF7–PTF0 O P 4 PTG7–PTG4 INTERNAL CLOCK PTG3 GENERATOR EXTAL G PTG2/EXTAL (ICG) XTAL T R PTG1/XTAL BKGD O P PTG0/BKGD/MS LOW-POWER OSCILLATOR Note: Not all pins are bonded out in all packages. See Table2-2 for complete details. Block Diagram Symbol Key: = Not connected in 48-, 44-, and 42-pin packages = Not connected in 44- and 42-pin packages = Not connected in 42-pin packages Figure9-2. Block Diagram Highlighting KBI Module MC9S08GB60A Data Sheet, Rev. 2 150 Freescale Semiconductor

Keyboard Interrupt (S08KBIV1) 9.2.1 KBI Block Diagram Figure 9-3 shows the block diagram for a KBI module. KBI1P0 KBIPE0 KBI1P3 KBACK BUSCLK KBIPE3 VDD RESET KBF DCLRQ 1 SYNCHRONIZER CK KBI1P4 0 S KBIPE4 KEYBOARD STOP STOP BYPASS KEYBOARD KBEDG4 INTERRUPT FF INTERRUPT REQUEST KBIMOD 1 KBIE KBI1Pn 0 S KBIPEn KBEDGn Figure9-3. KBI Block Diagram 9.3 Register Definition This section provides information about all registers and control bits associated with the KBI module. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 151

Keyboard Interrupt (S08KBIV1) 9.3.1 KBI Status and Control Register (KBI1SC) 7 6 5 4 3 2 1 0 R KBF 0 KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBIE KBIMOD W KBACK Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure9-4. KBI Status and Control Register (KBI1SC) Table9-1. KBI1SC Register Field Descriptions Field Description 7:4 Keyboard Edge Select for KBI Port Bits — Each of these read/write bits selects the polarity of the edges and/or KBEDG[7:4] levels that are recognized as trigger events on the corresponding KBI port pin when it is configured as a keyboard interrupt input (KBIPEn=1). Also see the KBIMOD control bit, which determines whether the pin is sensitive to edges-only or edges and levels. 0 Falling edges/low levels 1 Rising edges/high levels 3 Keyboard Interrupt Flag — This read-only status flag is set whenever the selected edge event has been KBF detected on any of the enabled KBI port pins. This flag is cleared by writing a 1 to the KBACK control bit. The flag will remain set if KBIMOD=1 to select edge-and-level operation and any enabled KBI port pin remains at the asserted level. KBF can be used as a software pollable flag (KBIE=0) or it can generate a hardware interrupt request to the CPU (KBIE=1). 0 No KBI interrupt pending 1 KBI interrupt pending 2 Keyboard Interrupt Acknowledge — This write-only bit (reads always return 0) is used to clear the KBF status KBACK flag by writing a 1 to KBACK. When KBIMOD=1 to select edge-and-level operation and any enabled KBI port pin remains at the asserted level, KBF is being continuously set so writing 1 to KBACK does not clear the KBF flag. 1 Keyboard Interrupt Enable — This read/write control bit determines whether hardware interrupts are generated KBIE when the KBF status flag equals 1. When KBIE=0, no hardware interrupts are generated, but KBF can still be used for software polling. 0 KBF does not generate hardware interrupts (use polling) 1 KBI hardware interrupt requested when KBF=1 KBIMOD Keyboard Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level detection. KBI port bits 3 through 0 can detect falling edges-only or falling edges and low levels. KBI port bits 7 through 4 can be configured to detect either: (cid:129) Rising edges-only or rising edges and high levels (KBEDGn=1) (cid:129) Falling edges-only or falling edges and low levels (KBEDGn=0) 0 Edge-only detection 1 Edge-and-level detection MC9S08GB60A Data Sheet, Rev. 2 152 Freescale Semiconductor

Keyboard Interrupt (S08KBIV1) 9.3.2 KBI Pin Enable Register (KBI1PE) 7 6 5 4 3 2 1 0 R KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure9-5. KBI Pin Enable Register (KBI1PE) Table9-2. KBI1PE Register Field Descriptions Field Description 7:0 Keyboard Pin Enable for KBI Port Bits — Each of these read/write bits selects whether the associated KBI KBIPE[7:0] port pin is enabled as a keyboard interrupt input or functions as a general-purpose I/O pin. 0 Bit n of KBI port is a general-purpose I/O pin not associated with the KBI 1 Bit n of KBI port enabled as a keyboard interrupt input 9.4 Functional Description 9.4.1 Pin Enables The KBIPEn control bits in the KBI1PE register allow a user to enable (KBIPEn=1) any combination of KBI-related port pins to be connected to the KBI module. Pins corresponding to 0s in KBI1PE are general-purpose I/O pins that are not associated with the KBI module. 9.4.2 Edge and Level Sensitivity Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs in a KBI module must be at the deasserted logic level. A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle. The KBIMOD control bit can be set to reconfigure the detection logic so that it detects edges and levels. In KBIMOD= 1 mode, the KBF status flag becomes set when an edge is detected (when one or more enabled pins change from the deasserted to the asserted level while all other enabled pins remain at their deasserted levels), but the flag is continuously set (and cannot be cleared) as long as any enabled keyboard input pin remains at the asserted level. When the MCU enters stop mode, the synchronous edge-detection logic is bypassed (because clocks are stopped). In stop mode, KBI inputs act as asynchronous level-sensitive inputs so they can wake the MCU from stop mode. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 153

Keyboard Interrupt (S08KBIV1) 9.4.3 KBI Interrupt Controls The KBF status flag becomes set (1) when an edge event has been detected on any KBI input pin. If KBIE= 1 in the KBI1SC register, a hardware interrupt will be requested whenever KBF =1. The KBF flag is cleared by writing a 1 to the keyboard acknowledge (KBACK) bit. When KBIMOD =0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK. When KBIMOD= 1 (selecting edge-and-level operation), KBF cannot be cleared as long as any keyboard input is at its asserted level. MC9S08GB60A Data Sheet, Rev. 2 154 Freescale Semiconductor

Chapter 10 Timer/PWM (S08TPMV1) 10.1 Introduction The MC9S08GBxxA/GTxxA includes two independent timer/PWM (TPM) modules which support traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on each channel. A control bit in each TPM configures all channels in that timer to operate as center-aligned PWM functions. In each of these two TPMs, timing functions are based on a separate 16-bit counter with prescaler and modulo features to control frequency and range (period between overflows) of the time reference. This timing system is ideally suited for a wide range of control applications, and the center-aligned PWM capability on the 3-channel TPM extends the field of applications to motor control in small appliances. The use of the fixed system clock, XCLK, as the clock source for either of the TPM modules allows the TPM prescaler to run using the oscillator rate divided by two (ICGERCLK/2). This clock source must be selected only if the ICG is configured in either FBE or FEE mode. In FBE mode, this selection is redundant because the BUSCLK frequency is the same as XCLK. In FEE mode, the proper conditions must be met for XCLK to equal ICGERCLK/2 (Section7.3.9, “Fixed Frequency Clock”). Selecting XCLK as the clock source with the ICG in either FEI or SCM mode will result in the TPM being non-functional. 10.2 Features The timer system in the MC9S08GBxxA includes a 3-channel TPM1 and a separate 5-channel TPM2; the timer system in the MC9S08GTxxA includes two 2-channel modules, TPM1 and TPM2. Timer system features include: • A total of eight channels: — Each channel may be input capture, output compare, or buffered edge-aligned PWM — Rising-edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs • Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all channels • Clock source to prescaler for each TPM is independently selectable as bus clock, fixed system clock, or an external pin • Prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 • 16-bit free-running or up/down (CPWM) count operation • 16-bit modulus register to control counter range • Timer system enable • One interrupt per channel plus terminal count interrupt MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 155

Chapter10 Timer/PWM (S08TPMV1) HCS08 CORE DEBUG MODULE (DBG) A CPU BDC 8 RT 8 PTA7/KBI1P7– 8-BIT KEYBOARD PO PTA0/KBI1P0 INTERRUPT MODULE (KBI1) HCS08 SYSTEM CONTROL B RESET RESETS AND INTERRUPTS CANOANLVOEG(RA-TTTEDOR1-D )(1IG0-ITBAITL) 8 PORT 8 PPTTBB07//AADD11PP07– MODES OF OPERATION POWER MANAGEMENT PTC7 PTC6 RTI COP PTC5 C IRQ IRQ LVD IIC MODULE SCL1 RT PTC4 (IIC1) O PTC3/SCL1 SDA1 P PTC2/SDA1 SCL1 PTC1/RxD2 SERIAL COMMUNICATIONS SCL1 PTC0/TxD2 INTERFACE MODULE USER FLASH (SCI2) PTD7/TPM2CH4 (Gx60A = 61,268 BYTES) PTD6/TPM2CH3 (Gx32A = 32,768 BYTES) 5-CHANNMEOLD TUILMEER/PWM 5 T D PPTTDD45//TTPPMM22CCHH12 R PTD3/TPM2CH0 (TPM2) O 3 P PTD2/TPM1CH2 USER RAM PTD1/TPM1CH1 3-CHANNEL TIMER/PWM (Gx60A = 4096 BYTES) PTD0/TPM1CH0 MODULE (Gx32A = 2048 BYTES) (TPM1) PTE7 PTE6 SPSCK1 VVDDAD SERIAL PERIPHERAL MOSI1 T E PPTTEE45//MSPOSSCI1K1 VSRSEAFDH INTERF(ASCPEI1 M)ODULE MSSIS1O1 POR PTE3/MISO1 V PTE2/SS1 REFL RxD1 PTE1/RxD1 SERIAL COMMUNICATIONS TxD1 VDD VOLTAGE INTERFACE MODULE PTE0/TxD1 (SCI1) V REGULATOR SS T F 8 R PTF7–PTF0 O P 4 PTG7–PTG4 INTERNAL CLOCK PTG3 GENERATOR EXTAL G PTG2/EXTAL (ICG) XTAL T R PTG1/XTAL BKGD O P PTG0/BKGD/MS LOW-POWER OSCILLATOR Note: Not all pins are bonded out in all packages. See Table2-2 for complete details. Block Diagram Symbol Key: = Not connected in 48-, 44-, and 42-pin packages = Not connected in 44- and 42-pin packages = Not connected in 42-pin packages Figure10-1. Block Diagram Highlighting the TPM Modules MC9S08GB60A Data Sheet, Rev. 2 156 Freescale Semiconductor

Timer/PWM (TPM) 10.3 TPM Block Diagram The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 0–4). The TPM shares its I/O pins with general-purpose I/O port pins (refer to the Pins and Connections chapter for more information). Figure 10-2 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers of channels. BUSCLK CLOCK SOURCE PRESCALE AND SELECT SELECT DIVIDE BY XCLK SYNC OFF, BUS, XCLK, EXT 1, 2, 4, 8, 16, 32, 64, or 128 TPMx) EXT CLK <st-blue> <st-blue> <st-blue> <st-blue> <st-blue> <st-blue> MAIN 16-BIT COUNTER <st-blue> COUNTER RESET INTERRUPT <st-blue> LOGIC 16-BIT COMPARATOR TPMxMODH:TPMx ELS0B ELS0A CHANNEL 0 PORT TPMxCH0 16-BIT COMPARATOR LOGIC TPMxC0VH:TPMxC0VL CH0F 16-BIT LATCH INTERRUPT LOGIC MS0B MS0A CH0IE S CHANNEL 1 ELS1B ELS1A PORT TPMxCH1 BU 16-BIT COMPARATOR LOGIC L NA TPMxC1VH:TPMxC1VL CH1F R E T 16-BIT LATCH INTERRUPT N I LOGIC MS1B MS1A CH1IE . . . . . . . . . ELSnB ELSnA CHANNEL n PORT TPMxCHn 16-BIT COMPARATOR LOGIC TPMxCnVH:TPMxCnVL CHnF 16-BIT LATCH INTERRUPT LOGIC CHnIE MSnB MSnA Figure10-2. TPM Block Diagram The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a modulo counter, or an up-/down-counter when the TPM is configured for center-aligned PWM. The TPM MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 157

Timer/PWM (TPM) counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control the modulo value of the counter. (The values $0000 or $FFFF effectively make the counter free running.) Software can read the counter value at any time without affecting the counting sequence. Any write to either byte of the TPMxCNT counter resets the counter regardless of the data value written. All TPM channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels. 10.4 Pin Descriptions Table 10-2 shows the MCU pins related to the TPM modules. When TPMxCH0 is used as an external clock input, the associated TPM channel 0 can not use the pin. (Channel 0 can still be used in output compare mode as a software timer.) When any of the pins associated with the timer is configured as a timer input, a passive pullup can be enabled. After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. 10.4.1 External TPM Clock Sources When control bits CLKSB:CLKSA in the timer status and control register are set to 1:1, the prescaler and consequently the 16-bit counter for TPMx are driven by an external clock source connected to the TPMxCH0 pin. A synchronizer is needed between the external clock and the rest of the TPM. This synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half the frequency of the bus rate clock. The upper frequency limit for this external clock source is specified to be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (PLL) or frequency-locked loop (FLL) frequency jitter effects. When the TPM is using the channel 0 pin for an external clock, the corresponding ELS0B:ELS0A control bits should be set to 0:0 so channel 0 is not trying to use the same pin. 10.4.2 TPMxCHn — TPMx Channel n I/O Pins Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the configuration of the channel. In some cases, no pin function is needed so the pin reverts to being controlled by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction registers do not affect the related pin(s). See the Pins and Connections chapter for additional information about shared pin functions. 10.5 Functional Description All TPM functions are associated with a main 16-bit counter that allows flexible selection of the clock source and prescale divisor. A 16-bit modulo register also is associated with the main 16-bit counter in the TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function. The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPMxSC. When CPWMS is set to 1, timer counter TPMxCNT changes to an up-/down-counter and all channels in the MC9S08GB60A Data Sheet, Rev. 2 158 Freescale Semiconductor

Timer/PWM (TPM) associated TPM act as center-aligned PWM channels. When CPWMS =0, each channel can independently be configured to operate in input capture, output compare, or buffered edge-aligned PWM mode. The following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend on the operating mode, these topics are covered in the associated mode sections. 10.5.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overflow, and manual counter reset. After any MCU reset, CLKSB:CLKSA= 0:0 so no clock source is selected and the TPM is inactive. Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the timer counter. The clock source for each of the TPM can be independently selected to be off, the bus clock (BUSCLK), the fixed system clock (XCLK), or an external input through the TPMxCH0 pin. The maximum frequency allowed for the external clock option is one-fourth the bus rate. Refer to Section10.7.1, “Timer x Status and Control Register (TPMxSC),” and Table 10-2 for more information about clock source selection. When the microcontroller is in active background mode, the TPM temporarily suspends all counting until the microcontroller returns to normal user operating mode. During stop mode, all TPM clocks are stopped; therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to operate normally. The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS= 1), the counter operates in up-/down-counting mode. Otherwise, the counter operates as a simple up-counter. As an up-counter, the main 16-bit counter counts from $0000 through its terminal count and then continues with $0000. The terminal count is $FFFF or a modulus value in TPMxMODH:TPMxMODL. When center-aligned PWM operation is specified, the counter counts upward from $0000 through its terminal count and then counts downward to $0000 where it returns to up-counting. Both $0000 and the terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock period long). An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is a software-accessible indication that the timer counter has overflowed. The enable signal selects between software polling (TOIE =0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE= 1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1. The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the main 16-bit counter counts from $0000 through $FFFF and overflows to $0000 on the next counting clock. TOF becomes set at the transition from $FFFF to $0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to $0000. When the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. This corresponds to the end of a PWM period. (The $0000 count value corresponds to the center of a period.) MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 159

Timer/PWM (TPM) Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations. Whenever either byte of the counter is read (TPMxCNTH or TPMxCNTL), both bytes are captured into a buffer so when the other byte is read, the value will represent the other byte of the count at the time the first byte was read. The counter continues to count normally, but no new value can be read from either byte until both bytes of the old count have been read. The main timer counter can be reset manually at any time by writing any value to either byte of the timer count TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was read before resetting the count. 10.5.2 Channel Mode Selection Provided CPWMS= 0 (center-aligned PWM operation is not specified), the MSnB and MSnA control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output compare, and buffered edge-aligned PWM. 10.5.2.1 Input Capture Mode With the input capture function, the TPM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TPM latches the contents of the TPM counter into the channel value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. 10.5.2.2 Output Compare Mode With the output compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM can set, clear, or toggle the channel pin. In output compare mode, values are transferred to the corresponding timer channel value registers only after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. 10.5.2.3 Edge-Aligned PWM Mode This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS= 0) and can be used when other channels in the same TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the setting in the modulus register (TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value MC9S08GB60A Data Sheet, Rev. 2 160 Freescale Semiconductor

Timer/PWM (TPM) register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. Duty cycle cases of 0percent and 100percent are possible. As Figure 10-3 shows, the output compare value in the TPM channel registers determines the pulse width (duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the pulse width. If ELSnA= 0, the counter overflow forces the PWM signal high and the output compare forces the PWM signal low. If ELSnA= 1, the counter overflow forces the PWM signal low and the output compare forces the PWM signal high. OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TPMxC OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE Figure10-3. PWM Period and Pulse Width (ELSnA=0) When the channel value register is set to $0000, the duty cycle is 0percent. By setting the timer channel value register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting, 100percent duty cycle can be achieved. This implies that the modulus setting must be less than $FFFF to get 100percent duty cycle. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register, TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the value in the TPMxCNTH:TPMxCNTL counter is $0000. (The new duty cycle does not take effect until the next full period.) 10.5.3 Center-Aligned PWM Mode This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS= 1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL should be kept in the range of $0001 to $7FFF because values outside this range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output. pulse width=2 x (TPMxCnVH:TPMxCnVL) Eqn.10-1 period = 2 x (TPMxMODH:TPMxMODL); for TPMxMODH:TPMxMODL=$0001–$7FFF Eqn.10-2 If the channel value register TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle will be 0 percent. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100 percent because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is $0001 through $7FFE ($7FFF if MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 161

Timer/PWM (TPM) generation of 100 percent duty cycle is not necessary). This is not a significant limitation because the resulting period is much longer than required for normal applications. TPMxMODH:TPMxMODL= $0000 is a special case that should not be used with center-aligned PWM mode. When CPWMS= 0, this case corresponds to the counter running free from $0000 through $FFFF, but when CPWMS= 1 the counter needs a valid match to the modulus register somewhere other than at $0000 in order to change directions from up-counting to down-counting. Figure 10-4 shows the output compare value in the TPM channel registers (multiplied by 2), which determines the pulse width (duty cycle) of the CPWM signal. If ELSnA =0, the compare match while counting up forces the CPWM output signal low and a compare match while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL. COUNT=0 OUTPUT OUTPUT COUNT= COMPARE COMPARE COUNT= TPMxMODH:TPMx (COUNT DOWN) (COUNT UP) TPMxMODH:TPMx TPM1C PULSE WIDTH 2 x PERIOD 2 x Figure10-4. CPWM Period and Pulse Width (ELSnA=0) Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined up at the same system clock edge. This type of PWM is also required for some types of motor drives. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers, TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). This TPMxCNT overflow requirement only applies to PWM channels, not output compares. Optionally, when TPMxCNTH:TPMxCNTL= TPMxMODH:TPMxMODL, the TPM can generate a TOF interrupt at the end of this count. The user can choose to reload any number of the PWM buffers, and they will all update simultaneously at the start of a new period. Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. MC9S08GB60A Data Sheet, Rev. 2 162 Freescale Semiconductor

Timer/PWM (TPM) 10.6 TPM Interrupts The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel. The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each time the main timer counter matches the value in the 16-bit channel value register. See the Resets, Interrupts, and System Configuration chapter for absolute interrupt vector addresses, priority, and local interrupt mask control bits. For each interrupt source in the TPM, a flag bit is set on recognition of the interrupt condition such as timer overflow, channel input capture, or output compare events. This flag may be read (polled) by software to verify that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated whenever the associated interrupt flag equals 1. It is the responsibility of user software to perform a sequence of steps to clear the interrupt flag before returning from the interrupt service routine. 10.6.1 Clearing Timer Interrupt Flags TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1) followed by a write of 0 to the bit. If a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. 10.6.2 Timer Overflow Interrupt Description The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the 16-bit timer counter counts from $0000 through $FFFF and overflows to $0000 on the next counting clock. TOF becomes set at the transition from $FFFF to $0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to $0000. When the counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. This corresponds to the end of a PWM period. (The $0000 count value corresponds to the center of a period.) 10.6.3 Channel Event Interrupt Description The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in Section10.6.1, “Clearing Timer Interrupt Flags.” When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step sequence described in Section10.6.1, “Clearing Timer Interrupt Flags.” MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 163

Timer/PWM (TPM) 10.6.4 PWM End-of-Duty-Cycle Events For channels that are configured for PWM operation, there are two possibilities: • When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter matches the channel value register that marks the end of the active duty cycle period. • When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle, which are the times when the timer counter matches the channel value register. The flag is cleared by the 2-step sequence described in Section10.6.1, “Clearing Timer Interrupt Flags.” 10.7 TPM Registers and Control Bits The TPM includes: • An 8-bit status and control register (TPMxSC) • A 16-bit counter (TPMxCNTH:TPMxCNTL) • A 16-bit modulo register (TPMxMODH:TPMxMODL) Each timer channel has: • An 8-bit status and control register (TPMxCnSC) • A 16-bit channel value register (TPMxCnVH:TPMxCnVL) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all TPM registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some MCU systems have more than one TPM, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n and TPM1C2SC is the status and control register for timer 1, channel 2. MC9S08GB60A Data Sheet, Rev. 2 164 Freescale Semiconductor

Timer/PWM (TPM) 10.7.1 Timer x Status and Control Register (TPMxSC) TPMxSC contains the overflow status flag and control bits that are used to configure the interrupt enable, TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this timer module. 7 6 5 4 3 2 1 0 R TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure10-5. Timer x Status and Control Register (TPMxSC) Table10-1. TPMxSC Register Field Descriptions Field Description 7 Timer Overflow Flag — This flag is set when the TPM counter changes to $0000 after reaching the modulo TOF value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set after the counter has reached the value in the modulo register, at the transition to the next lower count value. Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If another TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect. 0 TPM counter has not reached modulo value or overflow 1 TPM counter has overflowed 6 Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an TOIE interrupt is generated when TOF equals 1. Reset clears TOIE. 0 TOF interrupts inhibited (use software polling) 1 TOF interrupts enabled 5 Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the CPWMS TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears CPWMS. 0 All TPMx channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channel’s status and control register 1 All TPMx channels operate in center-aligned PWM mode 4:3 Clock Source Select — As shown in Table10-2, this 2-bit field is used to disable the TPM system or select one CLKS[B:A] of three clock sources to drive the counter prescaler. The external source and the XCLK are synchronized to the bus clock by an on-chip synchronization circuit. 2:0 Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in PS[2:0] Table10-3. This prescaler is located after any clock source synchronization or clock source selection, so it affects whatever clock source is selected to drive the TPM system. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 165

Timer/PWM (TPM) Table10-2. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 0:0 No clock selected (TPM disabled) 0:1 Bus rate clock (BUSCLK) 1:0 Fixed system clock (XCLK) 1:1 External source (TPMx Ext Clk)1,2 1.The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency. 2.When the TPMxCH0 pin is selected as the TPM clock source, the corresponding ELS0B:ELS0A control bits should be set to 0:0 so channel 0 does not try to use the same pin for a conflicting function. Table10-3. Prescale Divisor Selection PS2:PS1:PS0 TPM Clock Source Divided-By 0:0:0 1 0:0:1 2 0:1:0 4 0:1:1 8 1:0:0 16 1:0:1 32 1:1:0 64 1:1:1 128 10.7.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter. Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or TPMxCNTL, or any write to the timer status/control register (TPMxSC). Reset clears the TPM counter registers. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Any write to TPMxCNTH clears the 16-bit counter. Reset 0 0 0 0 0 0 0 0 Figure10-6. Timer x Counter Register High (TPMxCNTH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Any write to TPMxCNTL clears the 16-bit counter. Reset 0 0 0 0 0 0 0 0 Figure10-7. Timer x Counter Register Low (TPMxCNTL) MC9S08GB60A Data Sheet, Rev. 2 166 Freescale Semiconductor

Timer/PWM (TPM) When background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. 10.7.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counter reaches the modulo value, the TPM counter resumes counting from $0000 at the next clock (CPWMS= 0) or starts counting down (CPWMS =1), and the overflow flag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits the TOF bit and overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to $0000, which results in a free-running timer counter (modulo disabled). 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure10-8. Timer x Counter Modulo Register High (TPMxMODH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure10-9. Timer x Counter Modulo Register Low (TPMxMODL) It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 167

Timer/PWM (TPM) 10.7.4 Timer x Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 1 0 R 0 0 CHnF CHnIE MSnB MSnA ELSnB ELSnA W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure10-10. Timer x Channel n Status and Control Register (TPMxCnSC) Table10-4. TPMxCnSC Register Field Descriptions Field Description 7 Channel n Flag — When channel n is configured for input capture, this flag bit is set when an active edge occurs CHnF on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag is seldom used with center-aligned PWMs because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by reading TPMxCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect. 0 No input capture or output compare event occurred on channeln 1 Input capture or output compare event occurred on channeln 6 Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE. CHnIE 0 Channel n interrupt requests disabled (use software polling) 1 Channel n interrupt requests enabled 5 Mode Select B for TPM Channel n — When CPWMS=0, MSnB=1 configures TPM channel n for MSnB edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table10-5. 4 Mode Select A for TPM Channel n — When CPWMS=0 and MSnB=0, MSnA configures TPM channel n for MSnA input capture mode or output compare mode. Refer to Table10-5 for a summary of channel mode and setup controls. 3:2 Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by ELSn[B:A] CPWMS:MSnB:MSnA and shown in Table10-5, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer channel functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin. This is also the setting required for channel 0 when the TPMxCH0 pin is used as an external clock input. MC9S08GB60A Data Sheet, Rev. 2 168 Freescale Semiconductor

Timer/PWM (TPM) Table10-5. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration Pin not used for TPM channel; use as an external clock for the TPM or X XX 00 revert to general-purpose I/O 01 Capture on rising edge only 00 10 Input capture Capture on falling edge only 11 Capture on rising or falling edge 00 Software compare only 0 01 Toggle output on compare 01 Output compare 10 Clear output on compare 11 Set output on compare 10 Edge-aligned High-true pulses (clear output on compare) 1X X1 PWM Low-true pulses (set output on compare) 10 Center-aligned High-true pulses (clear output on compare-up) 1 XX X1 PWM Low-true pulses (set output on compare-up) If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior. 10.7.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel value registers are cleared by reset. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure10-11. Timer x Channel Value Register High (TPMxCnVH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure10-12. Timer Channel Value Register Low (TPMxCnVL) MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 169

Timer/PWM (TPM) In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPMxCnSC register is written. In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. MC9S08GB60A Data Sheet, Rev. 2 170 Freescale Semiconductor

Chapter 11 Serial Communications Interface (S08SCIV1) 11.1 Introduction The MC9S08GBxxA/GTxxA includes two independent serial communications interface (SCI) modules — sometimes called universal asynchronous receiver/transmitters (UARTs). Typically, these systems are used to connect to the RS232 serial input/output (I/O) port of a personal computer or workstation, and they can also be used to communicate with other embedded controllers. A flexible, 13-bit, modulo-based baud rate generator supports a broad range of standard baud rates beyond 115.2 kbaud. Transmit and receive within the same SCI use a common baud rate, and each SCI module has a separate baud rate generator. This SCI system offers many advanced features not commonly found on other asynchronous serial I/O peripherals on other embedded controllers. The receiver employs an advanced data sampling technique that ensures reliable communication and noise detection. Hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 171

Chapter11 Serial Communications Interface (S08SCIV1) HCS08 CORE DEBUG MODULE (DBG) A CPU BDC 8 RT 8 PTA7/KBI1P7– 8-BIT KEYBOARD PO PTA0/KBI1P0 INTERRUPT MODULE (KBI1) HCS08 SYSTEM CONTROL B RESET RESETS AND INTERRUPTS CANOANLVOEG(RA-TTTEDOR1-D )(1IG0-ITBAITL) 8 PORT 8 PPTTBB07//AADD11PP07– MODES OF OPERATION POWER MANAGEMENT PTC7 PTC6 RTI COP PTC5 C IRQ IRQ LVD IIC MODULE SCL1 RT PTC4 (IIC1) O PTC3/SCL1 SDA1 P PTC2/SDA1 SCL1 PTC1/RxD2 SERIAL COMMUNICATIONS SCL1 PTC0/TxD2 INTERFACE MODULE USER FLASH (SCI2) PTD7/TPM2CH4 (Gx60A = 61,268 BYTES) PTD6/TPM2CH3 (Gx32A = 32,768 BYTES) 5-CHANNMEOLD TUILMEER/PWM 5 T D PPTTDD45//TTPPMM22CCHH12 R PTD3/TPM2CH0 (TPM2) O 3 P PTD2/TPM1CH2 USER RAM PTD1/TPM1CH1 3-CHANNEL TIMER/PWM (Gx60A = 4096 BYTES) PTD0/TPM1CH0 MODULE (Gx32A = 2048 BYTES) (TPM1) PTE7 PTE6 SPSCK1 VVDDAD SERIAL PERIPHERAL MOSI1 T E PPTTEE45//MSPOSSCI1K1 VSRSEAFDH INTERF(ASCPEI1 M)ODULE MSSIS1O1 POR PTE3/MISO1 V PTE2/SS1 REFL RxD1 PTE1/RxD1 SERIAL COMMUNICATIONS TxD1 VDD VOLTAGE INTERFACE MODULE PTE0/TxD1 (SCI1) V REGULATOR SS T F 8 R PTF7–PTF0 O P 4 PTG7–PTG4 INTERNAL CLOCK PTG3 GENERATOR EXTAL G PTG2/EXTAL (ICG) XTAL T R PTG1/XTAL BKGD O P PTG0/BKGD/MS LOW-POWER OSCILLATOR Note: Not all pins are bonded out in all packages. See Table2-2 for complete details. Block Diagram Symbol Key: = Not connected in 48-, 44-, and 42-pin packages = Not connected in 44- and 42-pin packages = Not connected in 42-pin packages Figure11-1. Block Diagram Highlighting the SCI Modules MC9S08GB60A Data Sheet, Rev. 2 172 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) 11.1.1 Features Features of SCI module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Interrupt-driven or polled operation: — Transmit data register empty and transmission complete — Receive data register full — Receive overrun, parity error, framing error, and noise error — Idle receiver detect • Hardware parity generation and checking • Programmable 8-bit or 9-bit character length • Receiver wakeup by idle-line or address-mark 11.1.2 Modes of Operation See Section11.3, “Functional Description,” for a detailed description of SCI operation in the different modes. • 8- and 9- bit data modes • Stop modes — SCI is halted during all stop modes • Loop modes MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 173

Serial Communications Interface (S08SCIV1) 11.1.3 Block Diagram Figure 11-2 shows the transmitter portion of the SCI. (Figure 11-3 shows the receiver portion of the SCI.) INTERNAL BUS (WRITE-ONLY) LOOPS SCID – Tx BUFFER RSRC LOOP TO RECEIVE CONTROL M P RT DATA IN O A ST 11-BIT TRANSMIT SHIFT REGISTER ST H 8 7 6 5 4 3 2 1 0 L TO TxD PIN 1 × BAUD RATE CLOCK B SHIFT DIRECTION S L PPET GENPTEA8RRAITTYION OAD FROM SCIxD HIFT ENABLE REAMBLE (ALL 1s) REAK (ALL 0s) L S P B SCI CONTROLS TxD ENABLE TE TO TxD TRANSMIT CONTROL SBK TxD DIRECTION PIN LOGIC TXDIR TDRE TIE Tx INTERRUPT TC REQUEST TCIE Figure11-2. SCI Transmitter Block Diagram MC9S08GB60A Data Sheet, Rev. 2 174 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) Figure 11-3 shows the receiver portion of the SCI. INTERNAL BUS (READ-ONLY) SCID – Rx BUFFER 16 × BAUD DIVIDE RATE CLOCK BY 16 T P R M TO 11-BIT RECEIVE SHIFT REGISTER SB TA S L S H 8 7 6 5 4 3 2 1 0 L FROM RxD PIN DATA RECOVERY s ALL 1 MSB SHIFT DIRECTION LOOPS SINGLE-WIRE WAKE WAKEUP RWU LOOP CONTROL LOGIC RSRC ILT FROM TRANSMITTER RDRF RIE Rx INTERRUPT IDLE REQUEST ILIE OR ORIE FE FEIE ERROR INTERRUPT REQUEST NF NEIE PE PARITY PF CHECKING PT PEIE Figure11-3. SCI Receiver Block Diagram MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 175

Serial Communications Interface (S08SCIV1) 11.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud rate setting [SBR12:SBR0], first write to SCIxBDH to buffer the high half of the new value and then write to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written. SCIxBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1). 7 6 5 4 3 2 1 0 R 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-4. SCI Baud Rate Register (SCIxBDH) Table11-1. SCIxBDH Register Field Descriptions Field Description 4:0 Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide SBR[12:8] rate for the SCI baud rate generator. When BR=0, the SCI baud rate generator is disabled to reduce supply current. When BR=1 to 8191, the SCI baud rate=BUSCLK/(16×BR). See also BR bits in Table11-2. 7 6 5 4 3 2 1 0 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W Reset 0 0 0 0 0 1 0 0 Figure11-5. SCI Baud Rate Register (SCIxBDL) Table11-2. SCIxBDL Register Field Descriptions Field Description 7:0 Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide SBR[7:0] rate for the SCI baud rate generator. When BR=0, the SCI baud rate generator is disabled to reduce supply current. When BR=1 to 8191, the SCI baud rate=BUSCLK/(16×BR). See also BR bits in Table11-1. MC9S08GB60A Data Sheet, Rev. 2 176 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) 11.2.2 SCI Control Register 1 (SCIxC1) This read/write register is used to control various optional features of the SCI system. 7 6 5 4 3 2 1 0 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W Reset 0 0 0 0 0 0 0 0 Figure11-6. SCI Control Register 1 (SCIxC1) Table11-3. SCIxC1 Register Field Descriptions Field Description 7 Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS=1, LOOPS the transmitter output is internally connected to the receiver input. 0 Normal operation — RxD and TxD use separate pins. 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by SCI. 6 SCI Stops in Wait Mode SCISWAI 0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU. 1 SCI clocks freeze while CPU is in wait mode. 5 Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When RSRC LOOPS=1, the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output. 0 Provided LOOPS=1, RSRC=0 selects internal loop back mode and the SCI does not use the RxD pins. 1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input. 4 9-Bit or 8-Bit Mode Select M 0 Normal — start + 8 data bits (LSB first) + stop. 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (LSB first) + 9th data bit + stop. 3 Receiver Wakeup Method Select — Refer to Section11.3.3.2, “Receiver Wakeup Operation” for more WAKE information. 0 Idle-line wakeup. 1 Address-mark wakeup. 2 Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic1 bits at the end of a character ILT do not count toward the 10 or 11 bit times of the logic high level by the idle line detection logic. Refer to Section11.3.3.2.1, “Idle-Line Wakeup” for more information. 0 Idle character bit count starts after start bit. 1 Idle character bit count starts after stop bit. 1 Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant PE bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking. 1 Parity enabled. 0 Parity Type — Provided parity is enabled (PE=1), this bit selects even or odd parity. Odd parity means the total PT number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 177

Serial Communications Interface (S08SCIV1) 11.2.3 SCI Control Register 2 (SCIxC2) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R TIE TCIE RIE ILIE TE RE RWU SBK W Reset 0 0 0 0 0 0 0 0 Figure11-7. SCI Control Register 2 (SCIxC2) Table11-4. SCIxC2 Register Field Descriptions Field Description 7 Transmit Interrupt Enable (for TDRE) TIE 0 Hardware interrupts from TDRE disabled (use polling). 1 Hardware interrupt requested when TDRE flag is 1. 6 Transmission Complete Interrupt Enable (for TC) TCIE 0 Hardware interrupts from TC disabled (use polling). 1 Hardware interrupt requested when TC flag is 1. 5 Receiver Interrupt Enable (for RDRF) RIE 0 Hardware interrupts from RDRF disabled (use polling). 1 Hardware interrupt requested when RDRF flag is 1. 4 Idle Line Interrupt Enable (for IDLE) ILIE 0 Hardware interrupts from IDLE disabled (use polling). 1 Hardware interrupt requested when IDLE flag is 1. 3 Transmitter Enable TE 0 Transmitter off. 1 Transmitter on. TE must be 1 in order to use the SCI transmitter. When TE=1, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is configured for single-wire operation (LOOPS=RSRC=1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin). TE also can be used to queue an idle character by writing TE=0 then TE=1 while a transmission is in progress. Refer to Section11.3.2.1, “Send Break and Queued Idle,” for more details. When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin. 2 Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If RE LOOPS=1 , the RxD pin reverts to being a general-purpose I/O pin even if RE=1. 0 Receiver off. 1 Receiver on. MC9S08GB60A Data Sheet, Rev. 2 178 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) Table11-4. SCIxC2 Register Field Descriptions (continued) Field Description 1 Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it RWU waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle line between messages (WAKE=0, idle-line wakeup), or a logic 1 in the most significant data bit in a character (WAKE=1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware condition automatically clears RWU. Refer to Section11.3.3.2, “Receiver Wakeup Operation,” for more details. 0 Normal SCI receiver operation. 1 SCI receiver in standby waiting for wakeup condition. 0 Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional SBK break characters of 10 or 11bit times of logic 0 are queued as long as SBK=1. Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued before software clears SBK. Refer to Section11.3.2.1, “Send Break and Queued Idle,” for more details. 0 Normal transmitter operation. 1 Queue break character(s) to be sent. 11.2.4 SCI Status Register 1 (SCIxS1) This register has eight read-only status flags. Writes have no effect. Special software sequences (which do not involve writing to this register) are used to clear these status flags. 7 6 5 4 3 2 1 0 R TDRE TC RDRF IDLE OR NF FE PF W Reset 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-8. SCI Status Register 1 (SCIxS1) Table11-5. SCIxS1 Register Field Descriptions Field Description 7 Transmit Data Register Empty Flag — TDRE is set immediately after reset and when a transmit data value TDRE transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIxS1 with TDRE=1 and then write to the SCI data register (SCIxD). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty. 6 Transmission Complete Flag — TC is set immediately after reset and when TDRE=1 and no data, preamble, TC or break character is being transmitted. 0 Transmitter active (sending data, a preamble, or a break). 1 Transmitter idle (transmission activity complete). TC is cleared automatically by reading SCIxS1 with TC=1 and then doing one of the following three things: (cid:129) Write to the SCI data register (SCIxD) to transmit new data (cid:129) Queue a preamble by changing TE from 0 to 1 (cid:129) Queue a break character by writing 1 to SBK in SCIxC2 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 179

Serial Communications Interface (S08SCIV1) Table11-5. SCIxS1 Register Field Descriptions (continued) Field Description 5 Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into RDRF the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data register (SCIxD). 0 Receive data register empty. 1 Receive data register full. 4 Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of IDLE activity. When ILT=0, the receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the M control bit) needed for the receiver to detect an idle line. When ILT=1, the receiver doesn’t start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. To clear IDLE, read SCIxS1 with IDLE=1 and then read the SCI data register (SCIxD). After IDLE has been cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE will get set only once even if the receive line remains idle for an extended period. 0 No idle line detected. 1 Idle line was detected. 3 Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data OR register (buffer), but the previously received character has not been read from SCIxD yet. In this case, the new character (and all associated error information) is lost because there is no room to move it into SCIxD. To clear OR, read SCIxS1 with OR=1 and then read the SCI data register (SCIxD). 0 No overrun. 1 Receive overrun (new SCI data lost). 2 Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit NF and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No noise detected. 1 Noise detected in the received character in SCIxD. 1 Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic0 where the stop FE bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE=1 and then read the SCI data register (SCIxD). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error. 0 Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE=1) and the parity bit in PF the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No parity error. 1 Parity error. MC9S08GB60A Data Sheet, Rev. 2 180 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) 11.2.5 SCI Status Register 2 (SCIxS2) This register has one read-only status flag. Writes have no effect. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 RAF W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-9. SCI Status Register 2 (SCIxS2) Table11-6. SCIxS2 Register Field Descriptions Field Description 0 Receiver Active Flag — RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is RAF cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an SCI character is being received before instructing the MCU to go to stop mode. 0 SCI receiver idle waiting for a start bit. 1 SCI receiver active (RxD input not idle). 11.2.6 SCI Control Register 3 (SCIxC3) 7 6 5 4 3 2 1 0 R R8 0 T8 TXDIR ORIE NEIE FEIE PEIE W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-10. SCI Control Register 3 (SCIxC3) Table11-7. SCIxC3 Register Field Descriptions Field Description 7 Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M=1), R8 can be thought of as a ninth R8 receive data bit to the left of the MSB of the buffered data in the SCIxD register. When reading 9-bit data, read R8 before reading SCIxD because reading SCIxD completes automatic flag clearing sequences which could allow R8 and SCIxD to be overwritten with new data. 6 Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M=1), T8 may be thought of as a T8 ninth transmit data bit to the left of the MSB of the data in the SCIxD register. When writing 9-bit data, the entire 9-bit value is transferred to the SCI shift register after SCIxD is written so T8 should be written (if it needs to change from its previous value) before SCIxD is written. If T8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time SCIxD is written. 5 TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation TXDIR (LOOPS=RSRC=1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 181

Serial Communications Interface (S08SCIV1) Table11-7. SCIxC3 Register Field Descriptions (continued) Field Description 3 Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. ORIE 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR=1. 2 Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests. NEIE 0 NF interrupts disabled (use polling). 1 Hardware interrupt requested when NF=1. 1 Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt FEIE requests. 0 FE interrupts disabled (use polling). 1 Hardware interrupt requested when FE=1. 0 Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt PEIE requests. 0 PF interrupts disabled (use polling). 1 Hardware interrupt requested when PF=1. 11.2.7 SCI Data Register (SCIxD) This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags. 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 0 0 0 0 0 Figure11-11. SCI Data Register (SCIxD) MC9S08GB60A Data Sheet, Rev. 2 182 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) 11.3 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data. The following describes each of the blocks of the SCI. 11.3.1 Baud Rate Generation As shown in Figure 11-12, the clock source for the SCI baud rate generator is the bus-rate clock. MODULO DIVIDE BY (1 THROUGH 8191) DIVIDE BY BUSCLK SBR12:SBR0 16 Tx BAUD RATE Rx SAMPLING CLOCK BAUD RATE GENERATOR (16 × BAUD RATE) OFF IF [SBR12:SBR0] =0 BUSCLK BAUD RATE = [SBR12:SBR0] × 16 Figure11-12. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ±4 percent for 9-bit data format. Although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 11.3.2 Transmitter Functional Description This section describes the overall block diagram for the SCI transmitter (Figure 11-2), as well as specialized functions for sending break and idle characters. The transmitter is enabled by setting the TE bit in SCIxC2. This queues a preamble character that is one full character frame of the idle state. The transmitter then remains idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by writing to the SCI data register (SCIxD). The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the M control bit. For the remainder of this section, we will assume M =0, selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 183

Serial Communications Interface (S08SCIV1) the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register empty (TDRE) status flag is set to indicate another character may be written to the transmit data buffer at SCIxD. If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD1 pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD1 high, waiting for more characters to transmit. Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 11.3.2.1 Send Break and Queued Idle The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times including the start and stop bits). Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data bits and a framing error (FE= 1) occurs. When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This action queues an idle character to be sent as soon as the shifter is available. As long as the character in the shifter does not finish while TE=0, the SCI transmitter never actually releases control of the TxD1 pin. If there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin that is shared with TxD1 is an output driving a logic 1. This ensures that the TxD1 line will look like a normal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE. 11.3.3 Receiver Functional Description In this section, the data sampling technique used to reconstruct receiver data is described in more detail; two variations of the receiver wakeup function are explained. (The receiver block diagram is shown in Figure 11-3.) The receiver is enabled by setting the RE bit in SCIxC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer to Section 11.3.5.1, “8- and 9-Bit Data Modes.” For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode. After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (RDRF) status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the MC9S08GB60A Data Sheet, Rev. 2 184 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun. When a program detects that the receive data register is full (RDRF= 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s program that handles receive data. Refer to Section11.3.4, “Interrupts and Status Flags,” for more details about flag clearing. 11.3.3.1 Data Sampling Technique The SCI receiver uses a 16× baud rate clock for sampling. The receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the RxD1 serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock is used to divide the bit time into 16segments labeled RT1 through RT16. When a falling edge is located, three more samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive data buffer. The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set. 11.3.3.2 Receiver Wakeup Operation Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU= 1, it inhibits setting of the status flags associated with the receiver, thus eliminating the software overhead for handling the unimportant message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 185

Serial Communications Interface (S08SCIV1) 11.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level. The M control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits). When the RWU bit is set, the idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF. It therefore will not generate an interrupt when this idle character occurs. The receiver will wake up and wait for the next data transmission which will set RDRF and generate an interrupt if enabled. The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 11.3.3.2.2 Address-Mark Wakeup When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth bit in M = 0 mode and ninth bit in M = 1 mode). Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. The logic 1 MSB of an address frame clears the receivers RWU bit before the stop bit is received and sets the RDRF flag. 11.3.4 Interrupts and Status Flags The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events. Another interrupt vector is associated with the receiver for RDRF and IDLE events, and a third vector is used for OR, NF, FE, and PF error conditions. Each of these eight interrupt sources can be separately masked by local interrupt enable masks. The flags can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit data register empty (TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be requested whenever TDRE=1. Transmit complete (TC) indicates that the transmitter is finished transmitting all data, preamble, and break characters and is idle with TxD1 high. This flag is often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC= 1. Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF= 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF=1 and then reading SCIxD. MC9S08GB60A Data Sheet, Rev. 2 186 Freescale Semiconductor

Serial Communications Interface (S08SCIV1) When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardware interrupts are used, SCIxS1 must be read in the interrupt service routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied. The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD1 line remains idle for an extended period of time. IDLE is cleared by reading SCIxS1 while IDLE=1 and then reading SCIxD. After IDLE has been cleared, it cannot become set again until the receiver has received at least one new character and has set RDRF. If the associated error was detected in the received character that caused RDRF to be set, the error flags — noise flag (NF), framing error (FE), and parity error flag (PF) — get set at the same time as RDRF. These flags are not set in overrun cases. If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (OR) flag gets set instead and the data and any associated NF, FE, or PF condition is lost. 11.3.5 Additional SCI Functions The following sections describe additional SCI functions. 11.3.5.1 8- and 9-Bit Data Modes The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the M control bit in SCIxC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data register. For the transmit data buffer, this bit is stored in T8 in SCIxC3. For the receiver, the ninth bit is held in R8 in SCIxC3. For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCIxD. If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data is transferred from SCIxD to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker. 11.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. Because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted out of or received into the SCI module. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 187

Serial Communications Interface (S08SCIV1) 11.3.5.3 Loop Mode When LOOPS= 1, the RSRC bit in the same register chooses between loop mode (RSRC= 0) or single-wire mode (RSRC= 1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input and the RxD1 pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. 11.3.5.4 Single-Wire Operation When LOOPS= 1, the RSRC bit in the same register chooses between loop mode (RSRC= 0) or single-wire mode (RSRC= 1). Single-wire mode is used to implement a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the TxD1 pin. The RxD1 pin is not used and reverts to a general-purpose port I/O pin. In single-wire mode, the TXDIR bit in SCIxC3 controls the direction of serial data on the TxD1 pin. When TXDIR= 0, the TxD1 pin is an input to the SCI receiver and the transmitter is temporarily disconnected from the TxD1 pin so an external device can send serial data to the receiver. When TXDIR= 1, the TxD1 pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. MC9S08GB60A Data Sheet, Rev. 2 188 Freescale Semiconductor

Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.1 Introduction The MC9S08GBxxA/GTxxA provides one serial peripheral interface (SPI) module. The four pins associated with SPI functionality are shared with port E pins 2–5. See the Appendix A, “Electrical Characteristics,” appendix for SPI electrical parametric information. When the SPI is enabled, the direction of pins is controlled by module configuration. If the SPI is disabled, all four pins can be used as general-purpose I/O. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 189

Chapter12 Serial Peripheral Interface (S08SPIV3) HCS08 CORE DEBUG MODULE (DBG) A CPU BDC 8 RT 8 PTA7/KBI1P7– 8-BIT KEYBOARD PO PTA0/KBI1P0 INTERRUPT MODULE (KBI1) HCS08 SYSTEM CONTROL B RESET RESETS AND INTERRUPTS CANOANLVOEG(RA-TTTEDOR1-D )(1IG0-ITBAITL) 8 PORT 8 PPTTBB07//AADD11PP07– MODES OF OPERATION POWER MANAGEMENT PTC7 PTC6 RTI COP PTC5 C IRQ IRQ LVD IIC MODULE SCL1 RT PTC4 (IIC1) O PTC3/SCL1 SDA1 P PTC2/SDA1 SCL1 PTC1/RxD2 SERIAL COMMUNICATIONS SCL1 PTC0/TxD2 INTERFACE MODULE USER FLASH (SCI2) PTD7/TPM2CH4 (Gx60A = 61,268 BYTES) PTD6/TPM2CH3 (Gx32A = 32,768 BYTES) 5-CHANNMEOLD TUILMEER/PWM 5 T D PPTTDD45//TTPPMM22CCHH12 R PTD3/TPM2CH0 (TPM2) O 3 P PTD2/TPM1CH2 USER RAM PTD1/TPM1CH1 3-CHANNEL TIMER/PWM (Gx60A = 4096 BYTES) PTD0/TPM1CH0 MODULE (Gx32A = 2048 BYTES) (TPM1) PTE7 PTE6 SPSCK1 VVDDAD SERIAL PERIPHERAL MOSI1 T E PPTTEE45//MSPOSSCI1K1 VSRSEAFDH INTERF(ASCPEI1 M)ODULE MSSIS1O1 POR PTE3/MISO1 V PTE2/SS1 REFL RxD1 PTE1/RxD1 SERIAL COMMUNICATIONS TxD1 VDD VOLTAGE INTERFACE MODULE PTE0/TxD1 (SCI1) V REGULATOR SS T F 8 R PTF7–PTF0 O P 4 PTG7–PTG4 INTERNAL CLOCK PTG3 GENERATOR EXTAL G PTG2/EXTAL (ICG) XTAL T R PTG1/XTAL BKGD O P PTG0/BKGD/MS LOW-POWER OSCILLATOR Note: Not all pins are bonded out in all packages. See Table2-2 for complete details. Block Diagram Symbol Key: = Not connected in 48-, 44-, and 42-pin packages = Not connected in 44- and 42-pin packages = Not connected in 42-pin packages Figure12-1. Block Diagram Highlighting the SPI Module MC9S08GB60A Data Sheet, Rev. 2 190 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) 12.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 12.1.2 Block Diagrams This section includes block diagrams showing SPI system connections, the internal organization of the SPI module, and the SPI clock dividers that control the master mode bit rate. 12.1.2.1 SPI System Block Diagram Figure 12-2 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock output from the master and an input to the slave. The slave device must be selected by a low level on the slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave select output. MASTER SLAVE MOSI MOSI SPI SHIFTER SPI SHIFTER 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MISO MISO SPSCK SPSCK CLOCK GENERATOR SS SS Figure12-2. SPI System Connections MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 191

Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 12-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 12.1.2.2 SPI Module Block Diagram Figure 12-3 is a block diagram of the SPI module. The central element of the SPI is the SPI shift register. Data is written to the double-buffered transmitter (write to SPI1D) and gets transferred to the SPI shift register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from SPI1D). Pin multiplexing logic controls connections between MCU pins and the SPI module. When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is routed to MOSI, and the shifter input is routed from the MISO pin. When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin. In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. MC9S08GB60A Data Sheet, Rev. 2 192 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) PIN CONTROL M MOSI SPE S (MOMI) Tx BUFFER (WRITE SPI1D) ENABLE SPI SYSTEM M MISO SHIFT SPI SHIFT REGISTER SHIFT S (SISO) OUT IN SPC0 Rx BUFFER (READ SPI1D) BIDIROE SHIFT SHIFT Rx BUFFER Tx BUFFER LSBFE DIRECTION CLOCK FULL EMPTY MASTER CLOCK M BUS RATE SPIBR CLOCK SPSCK CLOCK CLOCK GENERATOR LOGIC SLAVE CLOCK S MASTER/SLAVE MASTER/ MSTR MODE SELECT SLAVE MODFEN SSOE MODE FAULT SS DETECTION SPRF SPTEF SPTIE SPI INTERRUPT MODF REQUEST SPIE Figure12-3. SPI Module Block Diagram 12.1.3 SPI Baud Rate Generation As shown in Figure 12-4, the clock source for the SPI baud rate generator is the bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal SPI master mode bit-rate clock. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 193

Serial Peripheral Interface (S08SPIV3) PRESCALER CLOCK RATE DIVIDER DIVIDE BY DIVIDE BY MASTER BUS CLOCK SPI 1, 2, 3, 4, 5, 6, 7, or 8 2, 4, 8, 16, 32, 64, 128, or 256 BIT RATE SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 Figure12-4. SPI Baud Rate Generation 12.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that are not controlled by the SPI. 12.2.1 SPSCK — SPI Serial Clock When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master, this pin is the serial clock output. 12.2.2 MOSI — Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0= 0, this pin is the serial data input. If SPC0= 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE =0) or an output (BIDIROE= 1). If SPC0= 1 and slave mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 12.2.3 MISO — Master Data In, Slave Data Out When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data input. When the SPI is enabled as a slave and SPC0= 0, this pin is the serial data output. If SPC0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE= 0) or an output (BIDIROE= 1). If SPC0= 1 and master mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 12.2.4 SS — Slave Select When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as a master and mode fault enable is off (MODFEN= 0), this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN= 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE= 0) or as the slave select output (SSOE= 1). MC9S08GB60A Data Sheet, Rev. 2 194 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) 12.3 Modes of Operation 12.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected. If stop3 is exited with a reset, the SPI will be put into its reset state. If stop3 is exited with an interrupt, the SPI continues from the state it was in when stop3 was entered. 12.4 Register Definition The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SPI registers. This section refers to registers and control bits only by their names, and a Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 12.4.1 SPI Control Register 1 (SPI1C1) This read/write register includes the SPI enable control, interrupt enables, and configuration options. 7 6 5 4 3 2 1 0 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W Reset 0 0 0 0 0 1 0 0 Figure12-5. SPI Control Register 1 (SPI1C1) Table12-1. SPI1C1 Field Descriptions Field Description 7 SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF) SPIE and mode fault (MODF) events. 0 Interrupts from SPRF and MODF inhibited (use polling) 1 When SPRF or MODF is 1, request a hardware interrupt 6 SPI System Enable — Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes SPE internal state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty. 0 SPI system inactive 1 SPI system enabled 5 SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). SPTIE 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 195

Serial Peripheral Interface (S08SPIV3) Table12-1. SPI1C1 Field Descriptions (continued) Field Description 4 Master/Slave Mode Select MSTR 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a CPOL slave SPI device. Refer to Section12.5.1, “SPI Clock Formats” for more details. 0 Active-high SPI clock (idles low) 1 Active-low SPI clock (idles high) 2 Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral CPHA devices. Refer to Section12.5.1, “SPI Clock Formats” for more details. 0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer 1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer 1 Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in SSOE SPCR2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table12-2. 0 LSB First (Shifter Direction) LSBFE 0 SPI serial data transfers start with most significant bit 1 SPI serial data transfers start with least significant bit Table12-2. SS Pin Function MODFEN SSOE Master Mode Slave Mode 0 0 General-purpose I/O (not SPI) Slave select input 0 1 General-purpose I/O (not SPI) Slave select input 1 0 SS input for mode fault Slave select input 1 1 Automatic SS output Slave select input NOTE Ensure that the SPI should not be disabled (SPE=0) at the same time as a bit change to the CPHA bit. These changes should be performed as separate operations or unexpected behavior may occur. 12.4.2 SPI Control Register 2 (SPI1C2) This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not implemented and always read 0. 7 6 5 4 3 2 1 0 R 0 0 0 0 MODFEN BIDIROE SPISWAI SPC0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure12-6. SPI Control Register 2 (SPI1C2) MC9S08GB60A Data Sheet, Rev. 2 196 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) Table12-3. SPI1C2 Register Field Descriptions Field Description 4 Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or MODFEN effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table12-2 for more details). 0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI 1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output 3 Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0)=1, BIDIROE BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO (SISO) pin, respectively, as the single SPI data I/O pin. When SPC0=0, BIDIROE has no meaning or effect. 0 Output driver disabled so SPI data I/O pin acts as an input 1 SPI I/O pin enabled as an output 1 SPI Stop in Wait Mode SPISWAI 0 SPI clocks continue to operate in wait mode 1 SPI clocks stop when the MCU enters wait mode 0 SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR=0 (slave mode), the SPI SPC0 uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR=1 (master mode), the SPI uses the MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0=1, BIDIROE is used to enable or disable the output driver for the single bidirectional SPI I/O pin. 0 SPI uses separate pins for data input and data output 1 SPI configured for single-wire bidirectional operation 12.4.3 SPI Baud Rate Register (SPI1BR) This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or written at any time. 7 6 5 4 3 2 1 0 R 0 0 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure12-7. SPI Baud Rate Register (SPI1BR) Table12-4. SPI1BR Register Field Descriptions Field Description 6:4 SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler SPPR[2:0] as shown in Table12-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler drives the input of the SPI baud rate divider (see Figure12-4). 2:0 SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in SPR[2:0] Table12-6. The input to this divider comes from the SPI baud rate prescaler (see Figure12-4). The output of this divider is the SPI bit rate clock for master mode. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 197

Serial Peripheral Interface (S08SPIV3) Table12-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table12-6. SPI Baud Rate Divisor SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 12.4.4 SPI Status Register (SPI1S) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0. Writes have no meaning or effect. 7 6 5 4 3 2 1 0 R SPRF 0 SPTEF MODF 0 0 0 0 W Reset 0 0 1 0 0 0 0 0 = Unimplemented or Reserved Figure12-8. SPI Status Register (SPI1S) MC9S08GB60A Data Sheet, Rev. 2 198 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) Table12-7. SPI1S Register Field Descriptions Field Description 7 SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may SPRF be read from the SPI data register (SPI1D). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register. 0 No data available in the receive data buffer 1 Data available in the receive data buffer 5 SPI Transmit Buffer Empty Flag — This bit is set when there is room in the transmit data buffer. It is cleared by SPTEF reading SPI1S with SPTEF set, followed by writing a data value to the transmit buffer at SPI1D. SPI1S must be read with SPTEF=1 before writing data to SPI1D or the SPI1D write will be ignored. SPTEF generates an SPTEF CPU interrupt request if the SPTIE bit in the SPI1C1 is also set. SPTEF is automatically set when a data byte transfers from the transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit buffer or the shift register and no transfer in progress), data written to SPI1D is transferred to the shifter almost immediately so SPTEF is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. After completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and SPTEF will be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter. 0 SPI transmit buffer not empty 1 SPI transmit buffer empty 4 Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes low, MODF indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only when MSTR=1, MODFEN=1, and SSOE=0; otherwise, MODF will never be set. MODF is cleared by reading MODF while it is 1, then writing to SPI control register 1 (SPI1C1). 0 No mode fault error 1 Mode fault error detected 12.4.5 SPI Data Register (SPI1D) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure12-9. SPI Data Register (SPI1D) Reads of this register return the data read from the receive data buffer. Writes to this register write data to the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data buffer initiates an SPI transfer. Data should not be written to the transmit data buffer unless the SPI transmit buffer empty flag (SPTEF) is set, indicating there is room in the transmit buffer to queue a new transmit byte. Data may be read from SPI1D any time after SPRF is set and before another transfer is finished. Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 199

Serial Peripheral Interface (S08SPIV3) 12.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF= 1) and then writing a byte of data to the SPI data register (SPI1D) in the master SPI device. When the SPI shift register is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts. During the SPI transfer, data is sampled (read) on the MISO pin at one SPSCK edge and shifted, changing the bit value on the MOSI pin, one-half SPSCK cycle later. After eight SPSCK cycles, the data that was in the shift register of the master has been shifted out the MOSI pin to the slave while eight bits of data were shifted in the MISO pin into the master’s shift register. At the end of this transfer, the received data byte is moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read by reading SPI1D. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved into the shifter, SPTEF is set, and a new transfer is started. Normally, SPI data is transferred most significant bit (MSB) first. If the least significant bit first enable (LSBFE) bit is set, SPI data is shifted LSB first. When the SPI is configured as a slave, its SS pin must be driven low before a transfer starts and SS must stay low throughout the transfer. If a clock format where CPHA =0 is selected, SS must be driven to a logic 1 between successive transfers. If CPHA =1, SS may remain low between successive transfers. See Section12.5.1, “SPI Clock Formats” for more details. Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffer, and a previously received character can be in the receive data buffer while a new character is being shifted in. The SPTEF flag indicates when the transmit buffer has room for a new character. The SPRF flag indicates when a received character is available in the receive data buffer. The received character must be read out of the receive buffer (read SPI1D) before the next transfer is finished or a receive overrun error results. In the case of a receive overrun, the new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. There is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 12.5.1 SPI Clock Formats To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses between two different clock phase relationships between the clock and data. Figure 12-10 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are shown for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after the sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MC9S08GB60A Data Sheet, Rev. 2 200 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE= 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SSIN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL=0) SPSCK (CPOL=1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 BIT 6 ... BIT 2 BIT 1 BIT 0 LSB FIRST BIT 0 BIT 1 ... BIT 5 BIT 6 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure12-10. SPI Clock Formats (CPHA = 1) When CPHA =1, the slave begins to drive its MISO output when SS goes to active low, but the data is not defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CHPA= 1, the slave’s SS input is not required to go to its inactive high level between transfers. Figure 12-11 shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 201

Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE= 1). The master SS output goes to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after the end of the eighth bit time of the transfer. The SSIN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL=0) SPSCK (CPOL=1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 BIT 6 ... BIT 2 BIT 1 BIT 0 LSB FIRST BIT 0 BIT 1 ... BIT 5 BIT 6 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure12-11. SPI Clock Formats (CPHA = 0) When CPHA= 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CPHA= 0, the slave’s SS input must go to its inactive high level between transfers. MC9S08GB60A Data Sheet, Rev. 2 202 Freescale Semiconductor

Serial Peripheral Interface (S08SPIV3) 12.5.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF). When one of the flag bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should check the flag bits to determine what event caused the interrupt. The service routine should also clear the flag bit(s) before returning from the ISR (usually near the beginning of the ISR). 12.5.3 Mode Fault Detection A mode fault occurs and the mode fault flag (MODF) becomes set when a master SPI device detects an error on the SS pin (provided the SS pin is configured as the mode fault input signal). The SS pin is configured to be the mode fault input signal when MSTR= 1, mode fault enable is set (MODFEN= 1), and slave select output enable is clear (SSOE= 0). The mode fault detection feature can be used in a system where more than one SPI device might become a master at the same time. The error is detected when a master’s SS pin is low, indicating that some other SPI device is trying to address this master as if it were a slave. This could indicate a harmful output driver conflict, so the mode fault logic is designed to disable all SPI output drivers when such an error is detected. When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are disabled. MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPI1C1). User software should verify the error condition has been corrected before changing the SPI back to master mode. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 203

Serial Peripheral Interface (S08SPIV3) MC9S08GB60A Data Sheet, Rev. 2 204 Freescale Semiconductor

Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.1 Introduction The MC9S08GBxxA/GTxxA series of microcontrollers provides one inter-integrated circuit (IIC) module for communication with other integrated circuits. The two pins associated with this module, SDA1 and SCL1 share port C pins 2 and 3, respectively. All functionality as described in this section is available on MC9S08GBxxA/GTxxA. When the IIC is enabled, the direction of pins is controlled by module configuration. If the IIC is disabled, both pins can be used as general-purpose I/O. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 205

Chapter13 Inter-Integrated Circuit (S08IICV1) HCS08 CORE DEBUG MODULE (DBG) A CPU BDC 8 RT 8 PTA7/KBI1P7– 8-BIT KEYBOARD PO PTA0/KBI1P0 INTERRUPT MODULE (KBI1) HCS08 SYSTEM CONTROL B RESET RESETS AND INTERRUPTS CANOANLVOEG(RA-TTTEDOR1-D )(1IG0-ITBAITL) 8 PORT 8 PPTTBB07//AADD11PP07– MODES OF OPERATION POWER MANAGEMENT PTC7 PTC6 RTI COP PTC5 C IRQ IRQ LVD IIC MODULE SCL1 RT PTC4 (IIC1) O PTC3/SCL1 SDA1 P PTC2/SDA1 SCL1 PTC1/RxD2 SERIAL COMMUNICATIONS SCL1 PTC0/TxD2 INTERFACE MODULE USER FLASH (SCI2) PTD7/TPM2CH4 (Gx60A = 61,268 BYTES) PTD6/TPM2CH3 (Gx32A = 32,768 BYTES) 5-CHANNMEOLD TUILMEER/PWM 5 T D PPTTDD45//TTPPMM22CCHH12 R PTD3/TPM2CH0 (TPM2) O 3 P PTD2/TPM1CH2 USER RAM PTD1/TPM1CH1 3-CHANNEL TIMER/PWM (Gx60A = 4096 BYTES) PTD0/TPM1CH0 MODULE (Gx32A = 2048 BYTES) (TPM1) PTE7 PTE6 SPSCK1 VVDDAD SERIAL PERIPHERAL MOSI1 T E PPTTEE45//MSPOSSCI1K1 VSRSEAFDH INTERF(ASCPEI1 M)ODULE MSSIS1O1 POR PTE3/MISO1 V PTE2/SS1 REFL RxD1 PTE1/RxD1 SERIAL COMMUNICATIONS TxD1 VDD VOLTAGE INTERFACE MODULE PTE0/TxD1 (SCI1) V REGULATOR SS T F 8 R PTF7–PTF0 O P 4 PTG7–PTG4 INTERNAL CLOCK PTG3 GENERATOR EXTAL G PTG2/EXTAL (ICG) XTAL T R PTG1/XTAL BKGD O P PTG0/BKGD/MS LOW-POWER OSCILLATOR Note: Not all pins are bonded out in all packages. See Table2-2 for complete details. Block Diagram Symbol Key: = Not connected in 48-, 44-, and 42-pin packages = Not connected in 44- and 42-pin packages = Not connected in 42-pin packages Figure13-1. Block Diagram Highlighting the IIC Module MC9S08GB60A Data Sheet, Rev. 2 206 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) 13.1.1 Features The IIC includes these distinctive features: • Compatible with IIC bus standard • Multi-master operation • Software programmable for one of 64 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation/detection • Repeated START signal generation • Acknowledge bit generation/detection • Bus busy detection 13.1.2 Modes of Operation The IIC functions the same in normal and monitor modes. A brief description of the IIC in the various MCU modes is given here. • Run mode — This is the basic mode of operation. To conserve power in this mode, disable the module. • Wait mode — The module will continue to operate while the MCU is in wait mode and can provide a wake-up interrupt. • Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The STOP instruction does not affect IIC register states. Stop2 and stop1 will reset the register contents. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 207

Inter-Integrated Circuit (S08IICV1) 13.1.3 Block Diagram Figure 13-2 is a block diagram of the IIC. ADDRESS DATA BUS INTERRUPT ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG INPUT SYNC IN/OUT START DATA STOP SHIFT ARBITRATION REGISTER CONTROL CLOCK CONTROL ADDRESS COMPARE SCL SDA Figure13-2. IIC Functional Block Diagram 13.2 External Signal Description This section describes each user-accessible pin signal. 13.2.1 SCL — Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system. 13.2.2 SDA — Serial Data Line The bidirectional SDA is the serial data line of the IIC system. 13.3 Register Definition This section consists of the IIC register descriptions in address order. MC9S08GB60A Data Sheet, Rev. 2 208 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.3.1 IIC Address Register (IIC1A) 7 6 5 4 3 2 1 0 R 0 ADDR W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure13-3. IIC Address Register (IIC1A) Table13-1. IIC1A Register Field Descriptions Field Description 7:1 IIC Address Register — The ADDR contains the specific slave address to be used by the IIC module. This is ADDR[7:1] the address the module will respond to when addressed as a slave. 13.3.2 IIC Frequency Divider Register (IIC1F) 7 6 5 4 3 2 1 0 R MULT ICR W Reset 0 0 0 0 0 0 0 0 Figure13-4. IIC Frequency Divider Register (IIC1F) MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 209

Inter-Integrated Circuit (S08IICV1) Table13-2. IIC1F Register Field Descriptions Field Description 7:6 IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL MULT divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved 5:0 IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection. These bits are used to ICR define the SCL divider and the SDA hold value. The SCL divider multiplied by the value provided by the MULT register (multiplier factor mul) is used to generate IIC baud rate. IIC baud rate = bus speed (Hz)/(mul * SCL divider) SDA hold time is the delay from the falling edge of the SCL (IIC clock) to the changing of SDA (IIC data). The ICR is used to determine the SDA hold value. SDA hold time = bus period (s) * SDA hold value Table13-3 provides the SCL divider and SDA hold values for corresponding values of the ICR. These values can be used to set IIC baud rate and SDA hold time. For example: Bus speed = 8MHz MULT is set to 01 (mul = 2) Desired IIC baud rate = 100kbps IIC baud rate = bus speed (Hz)/(mul * SCL divider) 100000 = 8000000/(2*SCL divider) SCL divider = 40 Table13-3 shows that ICR must be set to 0B to provide an SCL divider of 40 and that this will result in an SDA hold value of 9. SDA hold time = bus period (s) * SDA hold value SDA hold time = 1/8000000 * 9 = 1.125μs If the generated SDA hold value is not acceptable, the MULT bits can be used to change the ICR. This will result in a different SDA hold value. MC9S08GB60A Data Sheet, Rev. 2 210 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) Table13-3. IIC Divider and Hold Values ICR SDA Hold ICR SDA Hold SCL Divider SCL Divider (hex) Value (hex) Value 00 20 7 20 160 17 01 22 7 21 192 17 02 24 8 22 224 33 03 26 8 23 256 33 04 28 9 24 288 49 05 30 9 25 320 49 06 34 10 26 384 65 07 40 10 27 480 65 08 28 7 28 320 33 09 32 7 29 384 33 0A 36 9 2A 448 65 0B 40 9 2B 512 65 0C 44 11 2C 576 97 0D 48 11 2D 640 97 0E 56 13 2E 768 129 0F 68 13 2F 960 129 10 48 9 30 640 65 11 56 9 31 768 65 12 64 13 32 896 129 13 72 13 33 1024 129 14 80 17 34 1152 193 15 88 17 35 1280 193 16 104 21 36 1536 257 17 128 21 37 1920 257 18 80 9 38 1280 129 19 96 9 39 1536 129 1A 112 17 3A 1792 257 1B 128 17 3B 2048 257 1C 144 25 3C 2304 385 1D 160 25 3D 2560 385 1E 192 33 3E 3072 513 1F 240 33 3F 3840 513 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 211

Inter-Integrated Circuit (S08IICV1) 13.3.3 IIC Control Register (IIC1C) 7 6 5 4 3 2 1 0 R 0 0 0 IICEN IICIE MST TX TXAK W RSTA Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure13-5. IIC Control Register (IIC1C) Table13-4. IIC1C Register Field Descriptions Field Description 7 IIC Enable — The IICEN bit determines whether the IIC module is enabled. IICEN 0 IIC is not enabled. 1 IIC is enabled. 6 IIC Interrupt Enable — The IICIE bit determines whether an IIC interrupt is requested. IICIE 0 IIC interrupt request not enabled. 1 IIC interrupt request enabled. 5 Master Mode Select — The MST bit is changed from a 0 to a 1 when a START signal is generated on the bus MST and master mode is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode of operation changes from master to slave. 0 Slave Mode. 1 Master Mode. 4 Transmit Mode Select — The TX bit selects the direction of master and slave transfers. In master mode this bit TX should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high. When addressed as a slave this bit should be set by software according to the SRW bit in the status register. 0 Receive. 1 Transmit. 3 Transmit Acknowledge Enable — This bit specifies the value driven onto the SDA during data acknowledge TXAK cycles for both master and slave receivers. 0 An acknowledge signal will be sent out to the bus after receiving one data byte. 1 No acknowledge signal response is sent. 2 Repeat START — Writing a one to this bit will generate a repeated START condition provided it is the current RSTA master. This bit will always be read as a low. Attempting a repeat at the wrong time will result in loss of arbitration. MC9S08GB60A Data Sheet, Rev. 2 212 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) 13.3.4 IIC Status Register (IIC1S) 7 6 5 4 3 2 1 0 R TCF BUSY 0 SRW RXAK IAAS ARBL IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure13-6. IIC Status Register (IIC1S) Table13-5. IIC1S Register Field Descriptions Field Description 7 Transfer Complete Flag — This bit is set on the completion of a byte transfer. Note that this bit is only valid TCF during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the IIC1D register in receive mode or writing to the IIC1D in transmit mode. 0 Transfer in progress. 1 Transfer complete. 6 Addressed as a Slave — The IAAS bit is set when the calling address matches the programmed slave address. IAAS Writing the IIC1C register clears this bit. 0 Not addressed. 1 Addressed as a slave. 5 Bus Busy — The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is BUSY set when a START signal is detected and cleared when a STOP signal is detected. 0 Bus is idle. 1 Bus is busy. 4 Arbitration Lost — This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be ARBL cleared by software, by writing a one to it. 0 Standard bus operation. 1 Loss of arbitration. 2 Slave Read/Write — When addressed as a slave the SRW bit indicates the value of the R/W command bit of SRW the calling address sent to the master. 0 Slave receive, master writing to slave. 1 Slave transmit, master reading from slave. 1 IIC Interrupt Flag — The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by IICIF writing a one to it in the interrupt routine. One of the following events can set the IICIF bit: (cid:129) One byte transfer completes (cid:129) Match of slave address to calling address (cid:129) Arbitration lost 0 No interrupt pending. 1 Interrupt pending. 0 Receive Acknowledge — When the RXAK bit is low, it indicates an acknowledge signal has been received after RXAK the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received. 1 No acknowledge received. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 213

Inter-Integrated Circuit (S08IICV1) 13.3.5 IIC Data I/O Register (IIC1D) 7 6 5 4 3 2 1 0 R DATA W Reset 0 0 0 0 0 0 0 0 Figure13-7. IIC Data I/O Register (IIC1D) Table13-6. IIC1D Register Field Descriptions Field Description 7:0 Data — In master transmit mode, when data is written to the IIC1D, a data transfer is initiated. The most DATA significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data. NOTE When transmitting out of master receive mode, the IIC mode should be switched before reading the IIC1D register to prevent an inadvertent initiation of a master receive data transfer. In slave mode, the same functions are available after an address match has occurred. Note that the TX bit in IIC1C must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, then reading the IIC1D will not initiate the receive. Reading the IIC1D will return the last byte received while the IIC is configured in either master receive or slave receive modes. The IIC1D does not reflect every byte that is transmitted on the IIC bus, nor can software verify that a byte has been written to the IIC1D correctly by reading it back. In master transmit mode, the first byte of data written to IIC1D following assertion of MST is used for the address transfer and should comprise of the calling address (in bit 7–bit 1) concatenated with the required R/W bit (in position bit 0). MC9S08GB60A Data Sheet, Rev. 2 214 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) 13.4 Functional Description This section provides a complete functional description of the IIC module. 13.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: • START signal • Slave address transmission • Data transfer • STOP signal The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system communication is described briefly in the following sections and illustrated in Figure13-8. MSB LSB MSB LSB SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 START CALLING ADDRESS READ/ ACK DATA BYTE NO STOP SIGNAL WRITE BIT ACK SIGNAL BIT MSB LSB MSB LSB SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W START CALLING ADDRESS READ/ ACK REPEATED NEW CALLING ADDRESS READ/ NO STOP SIGNAL WRITE BIT START WRITE ACK SIGNAL SIGNAL BIT Figure13-8. IIC Bus Transmission Signals MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 215

Inter-Integrated Circuit (S08IICV1) 13.4.1.1 START Signal When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 13-8, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. 13.4.1.2 Slave Address Transmission The first byte of data transferred immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 13-8). No two slaves in the system may have the same address. If the IIC module is the master, it must not transmit an address that is equal to its own slave address. The IIC cannot be master and slave at the same time. However, if arbitration is lost during an address cycle, the IIC will revert to slave mode and operate correctly even if it is being addressed by another master. 13.4.1.3 Data Transfer Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 13-8. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one complete data transfer needs nine clock pulses. If the slave receiver does not acknowledge the master in the 9th bit time, the SDA line must be left high by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer. If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the SDA line. In either case, the data transfer is aborted and the master does one of two things: • Relinquishes the bus by generating a STOP signal. • Commences a new calling by generating a repeated START signal. MC9S08GB60A Data Sheet, Rev. 2 216 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) 13.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure13-8). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus. 13.4.1.5 Repeated START Signal As shown in Figure 13-8, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 13.4.1.6 Arbitration Procedure The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 13.4.1.7 Clock Synchronization Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all the devices connected on the bus. The devices start counting their low period and after a device’s clock has gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is still within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 13-9). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 217

Inter-Integrated Circuit (S08IICV1) START COUNTING HIGH PERIOD DELAY SCL1 SCL2 SCL INTERNAL COUNTER RESET Figure13-9. IIC Clock Synchronization 13.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 13.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it. If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. 13.5 Resets The IIC is disabled after reset. The IIC cannot cause an MCU reset. 13.6 Interrupts The IIC generates a single interrupt. An interrupt from the IIC is generated when any of the events in Table 13-7 occur provided the IICIE bit is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC control register). The IICIF bit must be cleared by software by writing a one to it in the interrupt routine. The user can determine the interrupt type by reading the status register. Table13-7. Interrupt Summary Interrupt Source Status Flag Local Enable Complete 1-byte transfer TCF IICIF IICIE Match of received calling address IAAS IICIF IICIE Arbitration Lost ARBL IICIF IICIE MC9S08GB60A Data Sheet, Rev. 2 218 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) 13.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of byte transfer. 13.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register), the IAAS bit in the status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 13.6.3 Arbitration Lost Interrupt The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration process and the ARBL bit in the status register is set. Arbitration is lost in the following circumstances: • SDA sampled as a low when the master drives a high during an address or data transmit cycle. • SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. • A START cycle is attempted when the bus is busy. • A repeated START cycle is requested in slave mode. • A STOP condition is detected when the master did not request it. This bit must be cleared by software by writing a one to it. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 219

Inter-Integrated Circuit (S08IICV1) 13.7 Initialization/Application Information Module Initialization (Slave) 1. Write: IICA — to set the slave address 2. Write: IICC — to enable IIC and interrupts 3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 4. Initialize RAM variables used to achieve the routine shown in Figure13-11 Module Initialization (Master) 1. Write: IICF — to set the IIC baud rate (example provided in this chapter) 2. Write: IICC — to enable IIC and interrupts 3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 4. Initialize RAM variables used to achieve the routine shown in Figure13-11 5. Write: IICC — to enable TX 6. Write: IICC — to enable MST (master mode) 7. Write: IICD — with the address of the target slave. (The LSB of this byte will determine whether the communication is master receive or transmit.) Module Use The routine shown in Figure13-11 can handle both master and slave IIC operations. For slave operation, an incoming IIC message that contains the proper address will begin IIC communication. For master operation, communication must be initiated by writing to the IICD register. Register Model IICA ADDR 0 Address to which the module will respond when addressed as a slave (in slave mode) IICF MULT ICR Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER)) IICC IICEN IICIE MST TX TXAK RSTA 0 0 Module configuration IICS TCF IAAS BUSY ARBL 0 SRW IICIF RXAK Module status flags IICD DATA Data register; Write to transmit IIC data read to read IIC data Figure13-10. IIC Module Quick Start MC9S08GB60A Data Sheet, Rev. 2 220 Freescale Semiconductor

Inter-Integrated Circuit (S08IICV1) Clear IICIF Y Master N Mode ? TX Tx/Rx RX Y Arbitration Lost ? ? N Last Byte Transmitted Y Clear ARBL ? N RXAK=0 N Byte tLoa Bset Read Y N IAAS=1 Y IAAS=1 ? ? ? ? Y N Y N Address Transfer Data Transfer Y Y AdEdnr dC oyfc le Y Byte2 tnod B Lea sRt ead (Read) SRW=1 TX/RX RX (Mast?er Rx) ? ? ? N N N(Write) TX Write Next Generate Set TX Y ACK from Set TXACK =1 Stop Signal Receiver Byte to IICD Mode (MST = 0) ? N Read Data Write Data Tx Next from IICD to IICD Byte and Store Switch to Set RX Switch to Rx Mode Mode Rx Mode Generate Read Data Dummy Read Dummy Read Dummy Read Stop Signal from IICD from IICD from IICD from IICD (MST = 0) and Store RTI Figure13-11. Typical IIC Interrupt Routine MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 221

Inter-Integrated Circuit (S08IICV1) MC9S08GB60A Data Sheet, Rev. 2 222 Freescale Semiconductor

Chapter 14 Analog-to-Digital Converter (S08ATDV3) The MC9S08GBxxA/GTxxA provides one 8-channel analog-to-digital (ATD) module. The eight ATD channels share port B. Each channel individually can be configured for general-purpose I/O or for ATD functionality. All features of the ATD module as described in this section are available on the MC9S08GBxxA/GTxxA. Electrical parametric information for the ATD may be found in AppendixA, “Electrical Characteristics.” MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 223

Chapter14 Analog-to-Digital Converter (S08ATDV3) HCS08 CORE DEBUG MODULE (DBG) A CPU BDC 8 RT 8 PTA7/KBI1P7– 8-BIT KEYBOARD PO PTA0/KBI1P0 INTERRUPT MODULE (KBI1) HCS08 SYSTEM CONTROL B RESET RESETS AND INTERRUPTS CANOANLVOEG(RA-TTTEDOR1-D )(1IG0-ITBAITL) 8 PORT 8 PPTTBB07//AADD11PP07– MODES OF OPERATION POWER MANAGEMENT PTC7 PTC6 RTI COP PTC5 C IRQ IRQ LVD IIC MODULE SCL1 RT PTC4 (IIC1) O PTC3/SCL1 SDA1 P PTC2/SDA1 SCL1 PTC1/RxD2 SERIAL COMMUNICATIONS SCL1 PTC0/TxD2 INTERFACE MODULE USER FLASH (SCI2) PTD7/TPM2CH4 (Gx60A = 61,268 BYTES) PTD6/TPM2CH3 (Gx32A = 32,768 BYTES) 5-CHANNMEOLD TUILMEER/PWM 5 T D PPTTDD45//TTPPMM22CCHH12 R PTD3/TPM2CH0 (TPM2) O 3 P PTD2/TPM1CH2 USER RAM PTD1/TPM1CH1 3-CHANNEL TIMER/PWM (Gx60A = 4096 BYTES) PTD0/TPM1CH0 MODULE (Gx32A = 2048 BYTES) (TPM1) PTE7 PTE6 SPSCK1 VVDDAD SERIAL PERIPHERAL MOSI1 T E PPTTEE45//MSPOSSCI1K1 VSRSEAFDH INTERF(ASCPEI1 M)ODULE MSSIS1O1 POR PTE3/MISO1 V PTE2/SS1 REFL RxD1 PTE1/RxD1 SERIAL COMMUNICATIONS TxD1 VDD VOLTAGE INTERFACE MODULE PTE0/TxD1 (SCI1) V REGULATOR SS T F 8 R PTF7–PTF0 O P 4 PTG7–PTG4 INTERNAL CLOCK PTG3 GENERATOR EXTAL G PTG2/EXTAL (ICG) XTAL T R PTG1/XTAL BKGD O P PTG0/BKGD/MS LOW-POWER OSCILLATOR Note: Not all pins are bonded out in all packages. See Table2-2 for complete details. Block Diagram Symbol Key: = Not connected in 48-, 44-, and 42-pin packages = Not connected in 44- and 42-pin packages = Not connected in 42-pin packages Figure14-1. MC9S08GB60A Block Diagram Highlighting ATD Block and Pins MC9S08GB60A Data Sheet, Rev. 2 224 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) 14.1 Introduction The ATD module is an analog-to-digital converter with a successive approximation register (SAR) architecture with sample and hold. 14.1.1 Features • 8-/10-bit resolution • 14.0 μsec, 10-bit single conversion time at a conversion frequency of 2MHz • Left-/right-justified result data • Left-justified signed data mode • Conversion complete flag or conversion complete interrupt generation • Analog input multiplexer for up to eight analog input channels • Single or continuous conversion mode 14.1.2 Modes of Operation The ATD has two modes for low power • Stop mode • Power-down mode 14.1.2.1 Stop Mode When the MCU goes into stop mode, the MCU stops the clocks and the ATD analog circuitry is turned off, placing the module into a low-power state. Once in stop mode, the ATD module aborts any single or continuous conversion in progress. Upon exiting stop mode, no conversions occur and the registers have their previous values. As long as the ATDPU bit is set prior to entering stop mode, the module is reactivated coming out of stop. 14.1.2.2 Power Down Mode Clearing the ATDPU bit in register ATD1C also places the ATD module in a low-power state. The ATD conversion clock is disabled and the analog circuitry is turned off, placing the module in power-down mode. (This mode does not remove power to the ATD module.) Once in power-down mode, the ATD module aborts any conversion in progress. Upon setting the ATDPU bit, the module is reactivated. During power-down mode, the ATD registers are still accessible. Note that the reset state of the ATDPU bit is zero. Therefore, the module is reset into the power-down state. 14.1.3 Block Diagram Figure 14-2 illustrates the functional structure of the ATD module. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 225

Analog-to-Digital Converter (S08ATDV3) CONTROL SAR_REG INTERRUPT DATA <9:0> ADDRESS CONTROL AND JUSTIFICATION RESULT REGISTERS STATUS R/W DATA REGISTERS V CTL DD PRESCALER STATUS V SS CTL BUSCLK CLOCK CONVERSION MODE STATE PRESCALER CONTROL BLOCK MACHINE CONVERSION CLOCK DIGITAL ANALOG POWERDOWN CTL V REFH V REFL V DDAD R E VSSAD ST SUCCESSIVE APPROXIMATION REGISTER GI E AD1P0 ANALOG-TO-DIGITAL CONVERTER (ATD) BLOCK ON R SI AD1P1 R E V AD1P2 N O C AD1P3 INPUT AD1P4 MUX AD1P5 AD1P6 AD1P7 = INTERNAL PINS = CHIP PADS Figure14-2. ATD Block Diagram 14.2 Signal Description 14.2.1 Overview The ATD supports eight input channels and requires 4 supply/reference/ground pins. These pins are listed in Table14-1. MC9S08GB60A Data Sheet, Rev. 2 226 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) Table14-1. Signal Properties Name Function AD7–AD0 Channel input pins VREFH High reference voltage for ATD converter VREFL Low reference voltage for ATD converter VDDAD ATD power supply voltage VSSAD ATD ground supply voltage 14.2.1.1 Channel Input Pins — AD1P7–AD1P0 The channel pins are used as the analog input pins of the ATD. Each pin is connected to an analog switch which serves as the signal gate into the sample submodule. 14.2.1.2 ATD Reference Pins — V , V REFH REFL These pins serve as the source for the high and low reference potentials for the converter. Separation from the power supply pins accommodates the filtering necessary to achieve the accuracy of which the system is capable. 14.2.1.3 ATD Supply Pins — V , V DDAD SSAD These two pins are used to supply power and ground to the analog section of the ATD. Dedicated power is required to isolate the sensitive analog circuitry from the normal levels of noise present on digital power supplies. NOTE V and V must be at the same potential. Likewise, V and V DDAD1 DD SSAD1 SS must be at the same potential. 14.3 Functional Description The ATD uses a successive approximation register (SAR) architecture. The ATD contains all the necessary elements to perform a single analog-to-digital conversion. A write to the ATD1SC register initiates a new conversion. A write to the ATD1C register will interrupt the current conversion but it will not initiate a new conversion. A write to the ATD1PE register will also abort the current conversion but will not initiate a new conversion. If a conversion is already running when a write to the ATD1SC register is made, it will be aborted and a new one will be started. 14.3.1 Mode Control The ATD has a mode control unit to communicate with the sample and hold (S/H) machine and the SAR machine when necessary to collect samples and perform conversions. The mode control unit signals the S/H machine to begin collecting a sample and for the SAR machine to begin receiving a sample. At the end of the sample period, the S/H machine signals the SAR machine to begin the analog-to-digital conversion process. The conversion process is terminated when the SAR machine signals the end of MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 227

Analog-to-Digital Converter (S08ATDV3) conversion to the mode control unit. For V and V , the SAR machine uses the reference potentials REFL REFH to set the sampled signal level within itself without relying on the S/H machine to deliver them. The mode control unit organizes the conversion, specifies the input sample channel, and moves the digital output data from the SAR register to the result register. The result register consists of a dual-port register. The SAR register writes data into the register through one port while the module data bus reads data out of the register through the other port. 14.3.2 Sample and Hold The S/H machine accepts analog signals and stores them as capacitor charge on a storage node located in the SAR machine. Only one sample can be held at a time so the S/H machine and the SAR machine can not run concurrently even though they are independent machines. Figure 14-3 shows the placement of the various resistors and capacitors. ATD SAR R INPUT PIN R ENGINE AS AIN1 V AIN + CHANNEL – C SELECT 0 AS INPUT PIN R AIN2 CHANNEL SELECT 1 INPUT PIN R AIN3 . CHANNEL . SELECT 2 . INPUT PIN R AINn CHANNEL SELECT n C AIN Figure14-3. Resistor and Capacitor Placement When the S/H machine is not sampling, it disables its own internal clocks.The input analog signals are unipolar. The signals must fall within the potential range of V to V . The S/H machine is not SSAD DDAD required to perform special conversions (i.e., convert V and V ). REFL REFH Proper sampling is dependent on the following factors: • Analog source impedance (the real portion, R – see AppendixA, “Electrical Characteristics” ) AS — This is the resistive (or real, in the case of high frequencies) portion of the network driving the analog input voltage V . AIN • Analog source capacitance (C ) — This is the filtering capacitance on the analog input, which (if AS large enough) may help the analog source network charge the ATD input in the case of high R . AS • ATD input resistance (R – maximum value 7 kΩ) — This is the internal resistance of the ATD AIN circuit in the path between the external ATD input and the ATD sample and hold circuit. This resistance varies with temperature, voltage, and process variation but a worst case number is necessary to compute worst case sample error. MC9S08GB60A Data Sheet, Rev. 2 228 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) • ATD input capacitance (C – maximum value 50pF) — This is the internal capacitance of the AIN ATD sample and hold circuit. This capacitance varies with temperature, voltage, and process variation but a worst case number is necessary to compute worst case sample error. • ATD conversion clock frequency (f – maximum value 2 MHz) — This is the frequency of ATDCLK the clock input to the ATD and is dependent on the bus clock frequency and the ATD prescaler. This frequency determines the width of the sample window, which is 14 ATDCLK cycles. • Input sample frequency (f – see AppendixA, “Electrical Characteristics”) — This is the SAMP frequency that a given input is sampled. • Delta-input sample voltage (ΔV ) — This is the difference between the current input voltage SAMP (intended for conversion) and the previously sampled voltage (which may be from a different channel). In non-continuous convert mode, this is assumed to be the greater of (V – V ) and REFH AIN (V – V ). In continuous convert mode, 5 LSB should be added to the known difference to AIN REFL account for leakage and other losses. • Delta-analog input voltage (ΔV ) — This is the difference between the current input voltage and AIN the input voltage during the last conversion on a given channel. This is based on the slew rate of the input. In cases where there is no external filtering capacitance, the sampling error is determined by the number of time constants of charging and the change in input voltage relative to the resolution of the ATD: # of time constants (τ) = (14 / f ) / ((R + R ) * C ) Eqn.14-1 ATDCLK AS AIN AIN sampling error in LSB (E ) = 2N * (ΔV / (V - V )) * e−τ S SAMP REFH REFL The maximum sampling error (assuming maximum change on the input voltage) will be: E = (3.6/3.6) * e–(14/((7 k + 10 k) * 50 p * 2 M)) * 1024 = 0.271 LSB Eqn.14-2 S In the case where an external filtering capacitance is applied, the sampling error can be reduced based on the size of the source capacitor (C ) relative to the analog input capacitance (C ). Ignoring the analog AS AIN source impedance (R ), C will charge C to a value of: AS AS AIN E = 2N * (ΔV / (V – V )) * (C / (C + C )) Eqn.14-3 S SAMP REFH REFL AIN AIN AS In the case of a 0.1 μF C , a worst case sampling error of 0.5 LSB is achieved regardless of R . AS AS However, in the case of repeated conversions at a rate of f , R must re-charge C . This recharge is SAMP AS AS continuous and controlled only by R (not R ), and reduces the overall sampling error to: AS AIN ES = 2N * {(ΔVAIN / (VREFH – VREFL)) * e−(1 / (fSAMP * RAS * CAS ) + (ΔVSAMP / (VREFH - VREFL)) * Min[(CAIN / (CAIN + CAS)), e−(1 / (fATDCLK * (RAS + RAIN) * CAIN )]} Eqn.14-4 This is a worst case sampling error which does not account for R recharging the combination of C AS AS and C during the sample window. It does illustrate that high values of R (>10kΩ) are possible if a AIN AS large C is used and sufficient time to recharge C is provided between samples. In order to achieve AS AS accuracy specified under the worst case conditions of maximum ΔV and minimum C , R must SAMP AS AS be less than the maximum value of 10 kΩ. The maximum value of 10 kΩ for R is to ensure low sampling AS error in the worst case condition of maximum ΔV and minimum C . SAMP AS MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 229

Analog-to-Digital Converter (S08ATDV3) 14.3.3 Analog Input Multiplexer The analog input multiplexer selects one of the eight external analog input channels to generate an analog sample. The analog input multiplexer includes negative stress protection circuitry which prevents cross-talk between channels when the applied input potentials are within specification. Only analog input signals within the potential range of V to V (ATD reference potentials) will result in valid ATD REFL REFH conversions. 14.3.4 ATD Module Accuracy Definitions Figure 14-4 illustrates an ideal ATD transfer function. The horizontal axis represents the ATD input voltage in millivolts. The vertical axis the conversion result code. The ATD is specified with the following figures of merit: • Number of bits (N) — The number of bits in the digitized output • Resolution (LSB) — The resolution of the ATD is the step size of the ideal transfer function. This is also referred to as the ideal code width, or the difference between the transition voltages to a given code and to the next code. This unit, known as 1LSB, is equal to 1LSB = (V – V ) / 2N Eqn.14-5 REFH REFL • Inherent quantization error (E ) — This is the error caused by the division of the perfect ideal Q straight-line transfer function into the quantized ideal transfer function with 2N steps. This error is ± 1/2LSB. • Differential non-linearity (DNL) — This is the difference between the current code width and the ideal code width (1LSB). The current code width is the difference in the transition voltages to the current code and to the next code. A negative DNL means the transfer function spends less time at the current code than ideal; a positive DNL, more. The DNL cannot be less than –1.0; a DNL of greater than 1.0 reduces the effective number of bits by 1. • Integral non-linearity (INL) — This is the difference between the transition voltage to the current code and the transition to the corresponding code on the adjusted transfer curve. INL is a measure of how straight the line is (how far it deviates from a straight line). The adjusted ideal transition voltage is: Eqn.14-6 (Current Code - 1/2) Adjusted Ideal Trans. V = * ((V + E ) - (V + E )) REFH FS REFL ZS 2N • Zero scale error (E ) — This is the difference between the transition voltage to the first valid code ZS and the ideal transition to that code. Normally, it is defined as the difference between the actual and ideal transition to code 0x001, but in some cases the first transition may be to a higher code. The ideal transition to any code is: Eqn.14-7 (Current Code - 1/2) Ideal Transition V = *(V – V ) 2N REFH REFL MC9S08GB60A Data Sheet, Rev. 2 230 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) • Full scale error (E ) — This is the difference between the transition voltage to the last valid code FS and the ideal transition to that code. Normally, it is defined as the difference between the actual and ideal transition to code 0x3FF, but in some cases the last transition may be to a lower code. The ideal transition to any code is: Eqn.14-8 (Current Code - 1/2) Ideal Transition V = *(V – V ) 2N REFH REFL • Total unadjusted error (E ) — This is the difference between the transition voltage to a given code TU and the ideal straight-line transfer function. An alternate definition (with the same result) is the difference between the actual transfer function and the ideal straight-line transfer function. This measure of error includes inherent quantization error and all forms of circuit error (INL, DNL, zero-scale, and full-scale) except input leakage error, which is not due to the ATD. • Input leakage error (E ) — This is the error between the transition voltage to the current code and IL the ideal transition to that code that is the result of input leakage across the real portion of the impedance of the network that drives the analog input. This error is a system-observable error which is not inherent to the ATD, so it is not added to total error. This error is: E (in V) = input leakage * R Eqn.14-9 IL AS There are two other forms of error which are not specified which can also affect ATD accuracy. These are: • Sampling error (E ) — The error due to inadequate time to charge the ATD circuitry S • Noise error (E ) — The error due to noise on V , V , or V due to either direct coupling N AIN REFH REFL (noise source capacitively coupled directly on the signal) or power supply (V , V , V , DDAD SSAD DD and V ) noise interfering with the ATD’s ability to resolve the input accurately. The error due to SS internal sources can be reduced (and specified operation achieved) by operating the ATD conversion in wait mode and ceasing all IO activity. Reducing the error due to external sources is dependent on system activity and board layout. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 231

Analog-to-Digital Converter (S08ATDV3) CODE D C TOTAL UNADJUSTED ERROR BOUNDARY B A IDEAL TRANSFER FUNCTION 9 NEGATIVE DNL (CODE WIDTH <1LSB) 8 IDEAL STRAIGHT-LINE TRANSFER FUNCTION 7 QUANTIZATION 6 ERROR INL (ASSUMES E =E =0) ZS FS 5 1 LSB 4 TOTAL UNADJUSTED 3 ERROR AT THIS CODE 2 POSITIVE DNL 1 (CODE WIDTH >1LSB) 0 1 2 3 4 8 12 LSB NOTES: Graph is for example only and may not represent actual performance Figure14-4. ATD Accuracy Definitions MC9S08GB60A Data Sheet, Rev. 2 232 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) 14.4 Resets The ATD module is reset on system reset. If the system reset signal is activated, the ATD registers are initialized back to their reset state and the ATD module is powered down. This occurs as a function of the register file initialization; the reset definition of the ATDPU bit (power down bit) is zero or disabled. The MCU places the module back into an initialized state. If the module is performing a conversion, the current conversion is terminated, the conversion complete flag is cleared, and the SAR register bits are cleared. Any pending interrupts are also cancelled. Note that the control, test, and status registers are initialized on reset; the initialized register state is defined in the register description section of this specification. Enabling the module (using the ATDPU bit) does not cause the module to reset since the register file is not initialized. Finally, writing to control register ATD1C does not cause the module to reset; the current conversion will be terminated. 14.5 Interrupts The ATD module originates interrupt requests and the MCU handles or services these requests. Details on how the ATD interrupt requests are handled can be found in Chapter 5, “Resets, Interrupts, and System Configuration”. The ATD interrupt function is enabled by setting the ATDIE bit in the ATD1SC register. When the ATDIE bit is set, an interrupt is generated at the end of an ATD conversion and the ATD result registers (ATD1RH and ATD1RL) contain the result data generated by the conversion. If the interrupt function is disabled (ATDIE=0), then the CCF flag must be polled to determine when a conversion is complete. The interrupt will remain pending as long as the CCF flag is set. The CCF bit is cleared whenever the ATD status and control (ATD1SC) register is written. The CCF bit is also cleared whenever the ATD result registers (ATD1RH or ATD1RL) are read. Table14-2. Interrupt Summary Local Interrupt Description Enable CCF ATDIE Conversion complete 14.6 ATD Registers and Control Bits The ATD has seven registers which control ATD functions. Refer to the direct-page register summary in Chapter4, “Memory” of this data sheet for the absolute address assignments for all ATD registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 233

Analog-to-Digital Converter (S08ATDV3) 14.6.1 ATD Control (ATDC) Writes to the ATD control register will abort the current conversion, but will not start a new conversion. 7 6 5 4 3 2 1 0 R ATDPU DJM RES8 SGN PRS W Reset 0 0 0 0 0 0 0 0 Figure14-5. ATD Control Register (ATD1C) Table14-3. ATD1C Field Descriptions Field Description 7 ATD Power Up — This bit provides program on/off control over the ATD, reducing power consumption when the ATDPU ATD is not being used. When cleared, the ATDPU bit aborts any conversion in progress. 0 Disable the ATD and enter a low-power state. 1 ATD functionality. 6 Data Justification Mode — This bit determines how the 10-bit conversion result data maps onto the ATD result DJM register bits. When RES8 is set, bit DJM has no effect and the 8-bit result is always located in ATD1RH. See Section14.6.3, “ATD Result Data (ATD1RH, ATD1RL),” for details. The effect of the DJM bit on the result is shown in Table14-4. 0 Result register data is left justified. 1 Result register data is right justified. 5 ATD Resolution Select — This bit determines the resolution of the ATD converter, 8-bits or 10-bits. The ATD RES8 converter has the accuracy of a 10-bit converter. However, if 8-bit compatibility is required, selecting 8-bit resolution will map result data bits 9-2 onto ATD1RH bits 7-0. The effect of the RES8 bit on the result is shown in Table14-4. 0 10-bit resolution selected. 1 8-bit resolution selected. 4 Signed Result Select — This bit determines whether the result will be signed or unsigned data. Signed data is SGN represented as 2’s complement data and is achieved by complementing the MSB of the result. Signed data mode can be used only when the result is left justified (DJM=0) and is not available for right-justified mode (DJM=1). When a signed result is selected, the range for conversions becomes –512 (0x200) to 511 (0x1FF) for 10-bit resolution and –128 (0x80) to 127 (0x7F) for 8-bit resolution. The effect of the SGN bit on the result is shown in Table14-4. 0 Left justified result data is unsigned. 1 Left justified result data is signed. 3:0 Prescaler Rate Select — This field of bits determines the prescaled factor for the ATD conversion clock. PRS Table14-5 illustrates the divide-by operation and the appropriate range of bus clock frequencies. MC9S08GB60A Data Sheet, Rev. 2 234 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) Table14-4. Available Result Data Formats Analog Input V =V , V =V REFH DDA REFL SSA RES8 DJM SGN Data Formats of Result ATD1RH:ATD1RL V V DDA SSA 1 0 0 8-bit : left justified : unsigned 0xFF:0x00 0x00:0x00 1 0 1 8-bit : left justified : signed 0x7F:0x00 0x80:0x00 1 1 X1 8-bit : left justified2 : unsigned 0xFF:0x00 0x00:0x00 0 0 0 10-bit : left justified : unsigned 0xFF:0xC0 0x00:0x00 0 0 1 10-bit : left justified : signed 0x7F:0xC0 0x80:0x00 0 1 X1 10-bit : right justified : unsigned 0x03:0xFF 0x00:0x00 1 The SGN bit is only effective when DJM=0. When DJM = 1, SGN is ignored. 2 8-bit results are always in ATD1RH. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 235

Analog-to-Digital Converter (S08ATDV3) Table14-5. Clock Prescaler Values Max Bus Clock Max Bus Clock Min Bus Clock3 PRS Factor = (PRS +1) × 2 MHz MHz MHz (2MHz max ATD Clock)1 (1MHz max ATD Clock)2 (500kHz min ATD Clock) 0000 2 4 2 1 0001 4 8 4 2 0010 6 12 6 3 0011 8 16 8 4 0100 10 20 10 5 0101 12 20 12 6 0110 14 20 14 7 0111 16 20 16 8 1000 18 20 18 9 1001 20 20 20 10 1010 22 20 20 11 1011 24 20 20 12 1100 26 20 20 13 1101 28 20 20 14 1110 30 20 20 15 1111 32 20 20 16 1 Maximum ATD conversion clock frequency is 2 MHz. The max bus clock frequency is computed from the max ATD conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus clock = 2 (max ATD conversion clock frequency) × 2 (Factor) = 4MHz. 2 Use these settings if the maximum desired ATD conversion clock frequency is 1MHz. The max bus clock frequency is computed from the max ATD conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus clock = 1 (max ATD conversion clock frequency) × 2 (Factor) = 2 MHz. 3 Minimum ATD conversion clock frequency is 500 kHz. The min bus clock frequency is computed from the min ATD conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 1, min bus clock = 0.5 (min ATD conversion clock frequency) × 2 (Factor) = 1 MHz. 14.6.2 ATD Status and Control (ATD1SC) Writes to the ATD status and control register clears the CCF flag, cancels any pending interrupts, and initiates a new conversion. 7 6 5 4 3 2 1 0 R CCF ATDIE ATDCO ATDCH W Reset 0 0 0 0 0 0 0 1 = Unimplemented or Reserved Figure14-6. ATD Status and Control Register (ATD1SC) MC9S08GB60A Data Sheet, Rev. 2 236 Freescale Semiconductor

Analog-to-Digital Converter (S08ATDV3) Table14-6. ATD1SC Field Descriptions Field Description 7 Conversion Complete Flag — The CCF is a read-only bit which is set each time a conversion is complete. The CCF CCF bit is cleared whenever the ATD1SC register is written. It is also cleared whenever the result registers, ATD1RH or ATD1RL, are read. 0 Current conversion is not complete. 1 Current conversion is complete. 6 ATD Interrupt Enabled — When this bit is set, an interrupt is generated upon completion of an ATD conversion. ATDIE At this time, the result registers contain the result data generated by the conversion. The interrupt will remain pending as long as the conversion complete flag CCF is set. If the ATDIE bit is cleared, then the CCF bit must be polled to determine when the conversion is complete. Note that system reset clears pending interrupts. 0 ATD interrupt disabled. 1 ATD interrupt enabled. 5 ATD Continuous Conversion — When this bit is set, the ATD will convert samples continuously and update the ATDCO result registers at the end of each conversion. When this bit is cleared, only one conversion is completed between writes to the ATD1SC register. 0 Single conversion mode. 1 Continuous conversion mode. 4:0 Analog Input Channel Select — This field of bits selects the analog input channel whose signal is sampled and ATDCH converted to digital codes. Table14-7 lists the coding used to select the various analog input channels. Table14-7. Analog Input Channel Select Coding ATDCH Analog Input Channel 00 AD0 01 AD1 02 AD2 03 AD3 04 AD4 05 AD5 06 AD6 07 AD7 08–1D Reserved (default to VREFL) 1E VREFH 1F VREFL 14.6.3 ATD Result Data (ATD1RH, ATD1RL) For left-justified mode, result data bits 9–2 map onto bits 7–0 of ATD1RH, result data bits 1 and 0 map onto ATD1RL bits 7 and 6, where bit 7 of ATD1RH is the most significant bit (MSB). MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 237

Analog-to-Digital Converter (S08ATDV3) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 RESULT 0 ATD1RH ATD1RL Figure14-7. Left-Justified Mode For right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of ATD1RH, result data bits 7–0 map onto ATD1RL bits 7–0, where bit 1 of ATD1RH is the most significant bit (MSB). 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 RESULT 0 ATD1RH ATD1RL Figure14-8. Right-Justified Mode The ATD 10-bit conversion results are stored in two 8-bit result registers, ATD1RH and ATD1RL. The result data is formatted either left or right justified where the format is selected using the DJM control bit in the ATD1C register. The 10-bit result data is mapped either between ATD1RH bits 7–0 and ATD1RL bits 7–6 (left justified), or ATD1RH bits 1–0 and ATD1RL bits 7–0 (right justified). For 8-bit conversions, the 8-bit result is always located in ATD1RH bits 7–0, and the ATD1RL bits read 0. For 10-bit conversions, the six unused bits always read 0. The ATD1RH and ATD1RL registers are read-only. 14.6.4 ATD Pin Enable (ATD1PE) The ATD pin enable register allows the pins dedicated to the ATD module to be configured for ATD usage. A write to this register will abort the current conversion but will not initiate a new conversion. If the ATDPEx bit is 0 (disabled for ATD usage) but the corresponding analog input channel is selected via the ATDCH bits, the ATD will not convert the analog input but will instead convert V placing zeroes in REFL the ATD result registers. 7 6 5 4 3 2 1 0 R ATDPE7 ATDPE6 ATDPE5 ATDPE4 ATDPE3 ATDPE2 ATDPE1 ATDPE0 W Reset 0 0 0 0 0 0 0 0 Figure14-9. ATD Pin Enable Register (ATD1PE) Table14-8. ATD1PE Field Descriptions Field Description 7 ATD Pin 7–0 Enables ATDPE[7:0] 0 Pin disabled for ATD usage. 1 Pin enabled for ATD usage. MC9S08GB60A Data Sheet, Rev. 2 238 Freescale Semiconductor

Chapter 15 Development Support 15.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip flash and other nonvolatile memories. The BDC is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. In the HCS08 Family, address and data bus signals are not available on external pins (not even in test modes). Debug is done through commands fed into the target MCU via the single-wire background debug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals. The alternate BDC clock source for MC9S08GBxxA/GTxxA is the ICGLCLK. See Chapter7, “Internal Clock Generator (S08ICGV2),” for more information about ICGCLK and how to select clock sources. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 239

Development Support 15.1.1 Features Features of the BDC module include: • Single pin for mode selection and background communications • BDC registers are not located in the memory map • SYNC command to determine target communications rate • Non-intrusive commands for memory access • Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from stop or wait modes • One hardware address breakpoint built into BDC • Oscillator runs in stop mode, if BDC enabled • COP watchdog disabled while in active background mode Features of the ICE system include: • Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W • Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information: — Change-of-flow addresses or — Event-only data • Two types of breakpoints: — Tag breakpoints for instruction opcodes — Force breakpoints for any address access • Nine trigger modes: — Basic: A-only, A OR B — Sequence: A then B — Full: A AND B data, A AND NOT B data — Event (store data): Event-only B, A then event-only B — Range: Inside range (A ≤ address ≤ B), outside range (address < A or address > B) 15.2 Background Debug Controller (BDC) All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources. It does not use any user memory or locations in the memory map and does not share any on-chip peripherals. BDC commands are divided into two groups: • Active background mode commands require that the target MCU is in active background mode (the user program is not running). Active background mode commands allow the CPU registers to be read or written, and allow the user to trace one user instruction at a time, or GO to the user program from active background mode. MC9S08GB60A Data Sheet, Rev. 2 240 Freescale Semiconductor

Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system. Depending on the development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (USB) to communicate between the host PC and the pod. The pod typically connects to the target system with ground, the BKGD pin, RESET, and sometimes V . An open-drain connection to reset allows the host to force a target system reset, DD which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. Sometimes V can be used to allow the pod to use DD power from the target system to avoid the need for a separate power supply. However, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. BKGD 1 2 GND NO CONNECT 3 4 RESET NO CONNECT 5 6 V DD Figure15-1. BDM Tool Connector 15.2.1 BKGD Pin Description BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectional serial communication of active background mode commands and data. During reset, this pin is used to select between starting in active background mode or starting the user’s application program. This pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications. BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers. This protocol assumes the host knows the communication clock rate that is determined by the target BDC clock rate. All communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant bit first (MSB first). For a detailed description of the communications protocol, refer to Section15.2.2, “Communication Details.” If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed. BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Section15.2.2, “Communication Details,” for more detail. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 241

Development Support When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not necessary to reset the target MCU to communicate with it through the background debug interface. 15.2.2 Communication Details The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB first at 16BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source. The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronous to the external host. The internal BDC clock signal is shown for reference in counting cycles. MC9S08GB60A Data Sheet, Rev. 2 242 Freescale Semiconductor

Development Support Figure 15-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period. BDC CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES EARLIEST START OF NEXT BIT SYNCHRONIZATION TARGET SENSES BIT LEVEL UNCERTAINTY PERCEIVED START OF BIT TIME Figure15-2. BDC Host-to-Target Serial Bit Timing MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 243

Development Support Figure 15-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about 10cycles after it started the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure15-3. BDC Target-to-Host Serial Bit Timing (Logic 1) MC9S08GB60A Data Sheet, Rev. 2 244 Freescale Semiconductor

Development Support Figure 15-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE HIGH-IMPEDANCE TO BKGD PIN SPEEDUP TARGET MCU PULSE DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure15-4. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 245

Development Support 15.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program. Table 15-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in Table 15-1 to describe the coding structure of the BDC commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) / = separates parts of the command d = delay 16 target BDC clock cycles AAAA = a 16-bit address in the host-to-target direction RD = 8 bits of read data in the target-to-host direction WD = 8 bits of write data in the host-to-target direction RD16 = 16 bits of read data in the target-to-host direction WD16 = 16 bits of write data in the host-to-target direction SS = the contents of BDCSCR in the target-to-host direction (STATUS) CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register) MC9S08GB60A Data Sheet, Rev. 2 246 Freescale Semiconductor

Development Support Table15-1. BDC Command Summary Command Active BDM/ Coding Description Mnemonic Non-intrusive Structure Request a timed reference pulse to determine SYNC Non-intrusive n/a1 target BDC communication speed Enable acknowledge protocol. Refer to ACK_ENABLE Non-intrusive D5/d Freescale document order no. HCS08RMv1/D. Disable acknowledge protocol. Refer to ACK_DISABLE Non-intrusive D6/d Freescale document order no. HCS08RMv1/D. Enter active background mode if enabled BACKGROUND Non-intrusive 90/d (ignore if ENBDM bit equals 0) READ_STATUS Non-intrusive E4/SS Read BDC status from BDCSCR WRITE_CONTROL Non-intrusive C4/CC Write BDC controls in BDCSCR READ_BYTE Non-intrusive E0/AAAA/d/RD Read a byte from target memory READ_BYTE_WS Non-intrusive E1/AAAA/d/SS/RD Read a byte and report status Re-read byte from address just read and report READ_LAST Non-intrusive E8/SS/RD status WRITE_BYTE Non-intrusive C0/AAAA/WD/d Write a byte to target memory WRITE_BYTE_WS Non-intrusive C1/AAAA/WD/d/SS Write a byte and report status READ_BKPT Non-intrusive E2/RBKP Read BDCBKPT breakpoint register WRITE_BKPT Non-intrusive C2/WBKP Write BDCBKPT breakpoint register Go to execute the user application program GO Active BDM 08/d starting at the address currently in the PC Trace 1 user instruction at the address in the TRACE1 Active BDM 10/d PC, then return to active background mode Same as GO but enable external tagging TAGGO Active BDM 18/d (HCS08 devices have no external tagging pin) READ_A Active BDM 68/d/RD Read accumulator (A) READ_CCR Active BDM 69/d/RD Read condition code register (CCR) READ_PC Active BDM 6B/d/RD16 Read program counter (PC) READ_HX Active BDM 6C/d/RD16 Read H and X register pair (H:X) READ_SP Active BDM 6F/d/RD16 Read stack pointer (SP) Increment H:X by one then read memory byte READ_NEXT Active BDM 70/d/RD located at H:X Increment H:X by one then read memory byte READ_NEXT_WS Active BDM 71/d/SS/RD located at H:X. Report status and data. WRITE_A Active BDM 48/WD/d Write accumulator (A) WRITE_CCR Active BDM 49/WD/d Write condition code register (CCR) WRITE_PC Active BDM 4B/WD16/d Write program counter (PC) WRITE_HX Active BDM 4C/WD16/d Write H and X register pair (H:X) WRITE_SP Active BDM 4F/WD16/d Write stack pointer (SP) Increment H:X by one, then write memory byte WRITE_NEXT Active BDM 50/WD/d located at H:X Increment H:X by one, then write memory byte WRITE_NEXT_WS Active BDM 51/WD/d/SS located at H:X. Also report status. 1 The SYNC command is a special operation that does not have a command code. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 247

Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) • Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically one cycle of the fastest clock in the system.) • Removes all drive to the BKGD pin so it reverts to high impedance • Monitors the BKGD pin for the sync response pulse The target, upon detecting the SYNC request from the host (which is a much longer low time than would ever occur during normal BDC communications): • Waits for BKGD to return to a logic high • Delays 16cycles to allow the host to stop driving the high speedup pulse • Drives BKGD low for 128BDC clock cycles • Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD • Removes all drive to the BKGD pin so it reverts to high impedance The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 15.2.4 BDC Hardware Breakpoint The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to enable the breakpoint logic (BKPTEN= 1). When BKPTEN= 0, its default value after reset, the breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS= 1) or tagged (FTS= 0) type breakpoints. The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are more flexible than the simple breakpoint in the BDC module. MC9S08GB60A Data Sheet, Rev. 2 248 Freescale Semiconductor

Development Support 15.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture. The system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage FIFO. The debug module includes control and status registers that are accessible in the user’s memory map. These registers are located in the high register space to avoid using valuable direct page memory space. Most of the debug module’s functions are used during development, and user programs rarely access any of the control and status registers for the debug module. The one exception is that the debug system can provide the means to implement a form of ROM patching. This topic is discussed in greater detail in Section15.3.6, “Hardware Breakpoints.” 15.3.1 Comparators A and B Two 16-bit comparators (A and B) can optionally be qualified with the R/W signal and an opcode tracking circuit. Separate control bits allow you to ignore R/W for each comparator. The opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opcode at the specified address is actually executed as opposed to only being read from memory into the instruction queue. The comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. Comparators are disabled temporarily during all BDC accesses. The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an additional purpose, in full address plus data comparisons they are used to decide which of these buses to use in the comparator B data bus comparisons. If RWAEN= 1 (enabled) and RWA= 0 (write), the CPU’s write data bus is used. Otherwise, the CPU’s read data bus is used. The currently selected trigger mode determines what the debugger logic does when a comparator detects a qualified match condition. A match can cause: • Generation of a breakpoint to the CPU • Storage of data bus values into the FIFO • Starting to store change-of-flow addresses into the FIFO (begin type trace) • Stopping the storage of change-of-flow addresses into the FIFO (end type trace) 15.3.2 Bus Capture Information and FIFO Operation The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of words of valid information that are in the FIFO as data is stored into it. If a trace run is manually halted by writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position and MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 249

Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port. In the event-only trigger modes (see Section15.3.5, “Trigger Modes”), 8-bit data information is stored into the FIFO. In these cases, the high-order half of the FIFO (DBGFH) is not used and data is read out of the FIFO by simply reading DBGFL. Each time DBGFL is read, the FIFO is shifted so the next data value is available through the FIFO data port at DBGFL. In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU addresses and the input side of the FIFO. Because of this delay, if the trigger event itself is a change-of-flow address or a change-of-flow address appears during the next two bus cycles after a trigger event starts the FIFO, it will not be saved into the FIFO. In the case of an end-trace, if the trigger event is a change-of-flow, it will be saved as the last change-of-flow entry for that debug run. The FIFO can also be used to generate a profile of executed instruction addresses when the debugger is not armed. When ARM= 0, reading DBGFL causes the address of the most-recently fetched opcode to be saved in the FIFO. To use the profiling feature, a host debugger would read addresses out of the FIFO by reading DBGFH then DBGFL at regular periodic intervals. The first eight values would be discarded because they correspond to the eight DBGFL reads needed to initially fill the FIFO. Additional periodic reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger can develop a profile of executed instruction addresses. 15.3.3 Change-of-Flow Information To minimize the amount of information stored in the FIFO, only information related to instructions that cause a change to the normal sequential execution of instructions is stored. With knowledge of the source and object code program stored in the target system, an external debugger system can reconstruct the path of execution through many instructions from the change-of-flow information stored in the FIFO. For conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the address of the conditional branch opcode). Because BRA and BRN instructions are not conditional, these events do not cause change-of-flow information to be stored in the FIFO. Indirect JMP and JSR instructions use the current contents of the H:X index register pair to determine the destination address, so the debug system stores the run-time destination address for any indirect JMP or JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-flow information. 15.3.4 Tag vs. Force Breakpoints and Triggers Tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the CPU. This distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt causes some instructions that have been fetched into the instruction queue to be thrown away without being executed. MC9S08GB60A Data Sheet, Rev. 2 250 Freescale Semiconductor

Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU. The second refers to match signals from the comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the CPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active background mode rather than executing the tagged instruction. When the TRGSEL control bit in the DBGT register is set to select tag-type operation, the output from comparator A or B is qualified by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. There is separate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. 15.3.5 Trigger Modes The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the DBGT register selects one of nine trigger modes. When TRGSEL= 1 in the DBGT register, the output of the comparator must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in DBGT chooses whether the FIFO begins storing data when the qualified trigger is detected (begin trace), or the FIFO stores data in a circular fashion from the time it is armed until the qualified trigger is detected (end trigger). A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF flag and clears the AF and BF flags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets full. An end-trace run ends when the selected trigger event occurs. Any debug run can be stopped manually by writing a 0 to ARM or DBGEN in DBGC. In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only trigger modes, the FIFO stores data in the low-order eight bits of the FIFO. The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type traces. When TRGSEL= 1 to select opcode fetch triggers, it is not necessary to use R/W in comparisons because opcode tags would only apply to opcode fetches that are always read cycles. It would also be unusual to specify TRGSEL =1 while using a full mode trigger because the opcode value is normally known at a particular address. The following trigger mode descriptions only state the primary comparator conditions that lead to a trigger. Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and the corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with optional R/W qualification is used to request a CPU breakpoint if BRKEN =1 and TAG determines whether the CPU request will be a tag request or a force request. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 251

Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparatorB A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally) must match within the same bus cycle to cause a trigger event. Comparator A checks address, the low byte of comparator B checks data, and R/W is checked against RWA if RWAEN= 1. The high-order half of comparator B is not used. In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN= TAG= 1), but if you do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low half of comparator B, and R/W must match RWA if RWAEN= 1. All three conditions must be met within the same bus cycle to cause a trigger. In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN= TAG= 1), but if you do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. Event-Only B (Store Data) — Trigger events occur each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. A Then Event-Only B (Store Data) — After the address has matched the value in comparator A, a trigger event occurs each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. Inside Range (A ≤ Address ≤ B) — A trigger occurs when the address is greater than or equal to the value in comparator A and less than or equal to the value in comparator B at the same time. Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than the value in comparator A or greater than the value in comparator B. MC9S08GB60A Data Sheet, Rev. 2 252 Freescale Semiconductor

Development Support 15.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section15.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to finish the current instruction and then go to active background mode. If the background mode has not been enabled (ENBDM= 1) by a serial WRITE_CONTROL command through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background mode. 15.4 Register Definition This section contains the descriptions of the BDC and DBG registers and control bits. Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute address assignments for all DBG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 15.4.1 BDC Registers and Control Bits The BDC has two registers: • The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller. • The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address. These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU (so they do not have addresses and cannot be accessed by user programs). Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written at any time. For example, the ENBDM control bit may not be written while the MCU is in active background mode. (This prevents the ambiguous condition of the control bit forbidding active background mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS, WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 253

Development Support 15.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 6 5 4 3 2 1 0 R BDMACT WS WSF DVF ENBDM BKPTEN FTS CLKSW W Normal 0 0 0 0 0 0 0 0 Reset Reset in 1 1 0 0 1 0 0 0 Active BDM: = Unimplemented or Reserved Figure15-5. BDC Status and Control Register (BDCSCR) Table15-2. BDCSCR Register Field Descriptions Field Description 7 Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly ENBDM after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it. 0 BDM cannot be made active (non-intrusive commands still allowed) 1 BDM can be made active to allow active background mode commands 6 Background Mode Active Status — This is a read-only status bit. BDMACT 0 BDM not active (user application program running) 1 BDM active and waiting for serial commands 5 BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) BKPTEN control bit and BDCBKPT match register are ignored. 0 BDC breakpoint disabled 1 BDC breakpoint enabled 4 Force/Tag Select — When FTS=1, a breakpoint is requested whenever the CPU address bus matches the FTS BDCBKPT match register. When FTS=0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters active background mode rather than executing the tagged opcode. 0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that instruction 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC clock CLKSW source. 0 Alternate BDC clock source 1 MCU bus clock MC9S08GB60A Data Sheet, Rev. 2 254 Freescale Semiconductor

Development Support Table15-2. BDCSCR Register Field Descriptions (continued) Field Description 2 Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. WS However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work. Whenever the host forces the target MCU into active background mode, the host should issue a READ_STATUS command to check that BDMACT=1 before attempting other BDC commands. 0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to active background mode 1 Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU WSF executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and re-execute the wait or stop instruction.) 0 Memory access did not conflict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode 0 Data Valid Failure Status — This status bit is not used in the MC9S08GBxxA/GTxxA because it does not have DVF any slow access memory. 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a slow memory access 15.4.1.2 BDC Breakpoint Match Register (BDCBKPT) This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal memory map of the MCU. Breakpoints are normally set while the target MCU is in active background mode before running the user application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer to Section15.2.4, “BDC Hardware Breakpoint.” 15.4.2 System Background Debug Force Reset Register (SBDFR) This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 255

Development Support 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W BDFR1 Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure15-6. System Background Debug Force Reset Register (SBDFR) Table15-3. SBDFR Register Field Description Field Description 0 Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. 15.4.3 DBG Registers and Control Bits The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers. These registers are located in the high register space of the normal memory map so they are accessible to normal application programs. These registers are rarely if ever accessed by normal user application programs with the possible exception of a ROM patching mechanism that uses the breakpoint logic. 15.4.3.1 Debug Comparator A High Register (DBGCAH) This register contains compare value bits for the high-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 15.4.3.2 Debug Comparator A Low Register (DBGCAL) This register contains compare value bits for the low-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 15.4.3.3 Debug Comparator B High Register (DBGCBH) This register contains compare value bits for the high-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 15.4.3.4 Debug Comparator B Low Register (DBGCBL) This register contains compare value bits for the low-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. MC9S08GB60A Data Sheet, Rev. 2 256 Freescale Semiconductor

Development Support 15.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the next word of information. 15.4.3.6 Debug FIFO Low Register (DBGFL) This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have no meaning or effect. Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each FIFO word is unused). When reading 8-bit words out of the FIFO, simply read DBGFL repeatedly to get successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case. Do not attempt to read data from the FIFO while it is still armed (after arming but before the FIFO is filled or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can interfere with normal sequencing of reads from the FIFO. Reading DBGFL while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the FIFO. By reading DBGFH then DBGFL periodically, external host software can develop a profile of program execution. After eight reads from the FIFO, the ninth read will return the information that was stored as a result of the first read. To use the profiling feature, read the FIFO eight times without using the data to prime the sequence and then begin using the data to get a delayed picture of what addresses were being executed. The information stored into the FIFO on reads of DBGFL (while the FIFO is not armed) is the address of the most-recently fetched opcode. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 257

Development Support 15.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN W Reset 0 0 0 0 0 0 0 0 Figure15-7. Debug Control Register (DBGC) Table15-4. DBGC Register Field Descriptions Field Description 7 Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure. DBGEN 0 DBG disabled 1 DBG enabled 6 Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is used ARM to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually stopped by writing 0 to ARM or to DBGEN. 0 Debugger not armed 1 Debugger armed 5 Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If TAG BRKEN=0, this bit has no meaning or effect. 0 CPU breaks requested as force type requests 1 CPU breaks requested as tag type requests 4 Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can BRKEN cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of CPU break requests. 0 CPU break requests not enabled 1 Triggers cause a break request to the CPU 3 R/W Comparison Value for Comparator A — When RWAEN=1, this bit determines whether a read or a write RWA access qualifies comparator A. When RWAEN=0, RWA and the R/W signal do not affect comparator A. 0 Comparator A can only match on a write cycle 1 Comparator A can only match on a read cycle 2 Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match. RWAEN 0 R/W is not used in comparison A 1 R/W is used in comparison A 1 R/W Comparison Value for Comparator B — When RWBEN=1, this bit determines whether a read or a write RWB access qualifies comparator B. When RWBEN=0, RWB and the R/W signal do not affect comparator B. 0 Comparator B can match only on a write cycle 1 Comparator B can match only on a read cycle 0 Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match. RWBEN 0 R/W is not used in comparison B 1 R/W is used in comparison B MC9S08GB60A Data Sheet, Rev. 2 258 Freescale Semiconductor

Development Support 15.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM =0, except bits 4 and 5 are hard-wired to 0s. 7 6 5 4 3 2 1 0 R 0 0 TRGSEL BEGIN TRG3 TRG2 TRG1 TRG0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure15-8. Debug Trigger Register (DBGT) Table15-5. DBGT Register Field Descriptions Field Description 7 Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode TRGSEL tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match address is actually executed. 0 Trigger on access to compare address (force) 1 Trigger if opcode at compare address is executed (tag) 6 Begin/End Trigger Select — Controls whether the FIFO starts filling at a trigger or fills in a circular manner until BEGIN a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 Data stored in FIFO until trigger (end trace) 1 Trigger initiates data storage (begin trace) 3:0 Select Trigger Mode — Selects one of nine triggering modes, as described below. TRG[3:0] 0000 A-only 0001 A OR B 0010 A Then B 0011 Event-only B (store data) 0100 A then event-only B (store data) 0101 A AND B data (full mode) 0110 A AND NOT B data (full mode) 0111 Inside range: A ≤ address ≤ B 1000 Outside range: address < A or address > B 1001 – 1111 (No trigger) MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 259

Development Support 15.4.3.9 Debug Status Register (DBGS) This is a read-only status register. 7 6 5 4 3 2 1 0 R AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure15-9. Debug Status Register (DBGS) Table15-6. DBGS Register Field Descriptions Field Description 7 Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A AF condition was met since arming. 0 Comparator A has not matched 1 Comparator A match 6 Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B BF condition was met since arming. 0 Comparator B has not matched 1 Comparator B match 5 Arm Flag — While DBGEN=1, this status bit is a read-only image of ARM in DBGC. This bit is set by writing 1 ARMF to the ARM control bit in DBGC (while DBGEN=1) and is automatically cleared at the end of a debug run. A debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC. 0 Debugger not armed 1 Debugger armed 3:0 FIFO Valid Count — These bits are cleared at the start of a debug run and indicate the number of words of valid CNT[3:0] data in the FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO. The external debug host is responsible for keeping track of the count as information is read out of the FIFO. 0000 Number of valid words in FIFO = No valid data 0001 Number of valid words in FIFO = 1 0010 Number of valid words in FIFO = 2 0011 Number of valid words in FIFO = 3 0100 Number of valid words in FIFO = 4 0101 Number of valid words in FIFO = 5 0110 Number of valid words in FIFO = 6 0111 Number of valid words in FIFO = 7 1000 Number of valid words in FIFO = 8 MC9S08GB60A Data Sheet, Rev. 2 260 Freescale Semiconductor

Appendix A Electrical Characteristics A.1 Introduction This section contains electrical and timing specifications. A.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table A-1 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the programmable SS DD pull-up resistor associated with the pin is enabled. TableA-1. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to +3.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD+0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1,2,3 ID ± 25 mA Storage temperature range Tstg –55 to 150 °C 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (V ) and negative (V ) clamp DD SS voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V and V . SS DD 3 Power supply must maintain regulation within operating V range during instantaneous and DD operating maximum current conditions. If positive injection current (V > V ) is greater than In DD I , the injection current may flow out of V and could result in external power supply going DD DD out of regulation. Ensure external V load will shunt current greater than maximum injection DD current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 261

AppendixA Electrical Characteristics A.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the MCU design. In order to take P into account in power calculations, determine the difference between I/O actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of SS DD unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very SS DD small. TableA-2. Thermal Characteristics Temp. Rating Symbol Value Unit Code Operating temperature range (packaged) TA –40 to 85 °C C Thermal resistance 64-pin LQFP (GBxxA) θ 1,2 65 JA 48-pin QFN (GTxxA) 82 °C/W — 44-pin QFP (GTxxA) 118 42-pin SDIP (GTxxA) 57 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Single layer board is designed per JEDEC JESD51-3. The average chip-junction temperature (T ) in °C can be obtained from: J T = T + (P × θ ) Eqn.A-1 J A D JA where: T = Ambient temperature, °C A θ = Package thermal resistance, junction-to-ambient, °C/W JA P = P + P D int I/O P = I × V , Watts — chip internal power int DD DD P = Power dissipation on input and output pins — user determined I/O For most applications, P << P and can be neglected. An approximate relationship between P and T I/O int D J (if P is neglected) is: I/O P = K ÷ (T + 273°C) Eqn.A-2 D J Solving equations 1 and 2 for K gives: K = P × (T + 273°C) + θ × (P )2 Eqn.A-3 D A JA D where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by D A D J solving equations 1 and 2 iteratively for any value of T . A MC9S08GB60A Data Sheet, Rev. 2 262 Freescale Semiconductor

AppendixA Electrical Characteristics A.4 Electrostatic Discharge (ESD) Protection Characteristics Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E. A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. TableA-3. ESD Protection Characteristics Parameter Symbol Value Unit ESD Target for Machine Model (MM) MM circuit description VTHMM 200 V ESD Target for Human Body Model (HBM) HBM circuit description VTHHBM 2000 V A.5 DC Characteristics This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. TableA-4. DC Characteristics (Sheet 1 of 3) (Temperature Range = –40 to 85°C Ambient) Parameter Symbol Min Typical1 Max Unit Supply voltage (run, wait and stop modes.) 0 < fBus < 8 MHz VDD 1.8 3.6 V 0 < f < 20 MHz 2.08 3.6 Bus Minimum RAM retention supply voltage applied to V 1.02 — V V RAM DD Low-voltage detection threshold — high range (VDD falling) VLVDH 2.08 2.1 2.2 V (V rising) 2.16 2.19 2.27 DD Low-voltage detection threshold — low range (VDD falling) VLVDL 1.80 1.82 1.91 V (V rising) 1.88 1.90 1.99 DD Low-voltage warning threshold — high range (VDD falling) VLVWH 2.35 2.40 2.5 V (V rising) 2.35 2.40 2.5 DD MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 263

AppendixA Electrical Characteristics TableA-4. DC Characteristics (Sheet 2 of 3) (Temperature Range = –40 to 85°C Ambient) Parameter Symbol Min Typical1 Max Unit Low-voltage warning threshold — low range (VDD falling) VLVWL 2.08 2.1 2.2 V (V rising) 2.16 2.19 2.27 DD Power on reset (POR) re-arm voltage(2) Mode = stop VRearm 0.20 0.30 0.40 V Mode = run and Wait 0.50 0.80 1.2 Input high voltage (VDD > 2.3 V) (all digital inputs) VIH 0.70 × VDD — V Input high voltage (1.8 V ≤ V ≤ 2.3 V) DD VIH 0.85 × VDD — V (all digital inputs) Input low voltage (VDD > 2.3 V) (all digital inputs) VIL — 0.35 × VDD V Input low voltage (1.8 V ≤ V ≤ 2.3 V) DD VIL — 0.30 × VDD V (all digital inputs) Input hysteresis (all digital inputs) Vhys 0.06 × VDD — V Input leakage current (per pin) V = V or V all input only pins |IIn| — 0.025 1.0 μA In DD SS, High impedance (off-state) leakage current (per pin) |IOZ| — 0.025 1.0 μA VIn = VDD or VSS, all input/output Internal pullup and pulldown resistors3 kΩ RPU 17.5 52.5 (all port pins and IRQ) Internal pulldown resistors (Port A4–A7 and IRQ) RPD 17.5 52.5 kΩ Output high voltage (V ≥ 1.8 V) DD IOH = –2 mA (ports A, B, D, E, and G) VDD – 0.5 — V Output high voltage (ports C and F) OH V IOH = –10 mA (VDD ≥ 2.7 V) — V – 0.5 IOH = –6 mA (VDD ≥ 2.3 V) DD — IOH = –3 mA (VDD ≥ 1.8 V) — Maximum total IOH for all port pins |IOHT| — 60 mA Output low voltage (V ≥ 1.8 V) DD IOL = 2.0 mA (ports A, B, D, E, and G) — 0.5 Output low voltage (ports C and F) V IOL = 10.0 mA (VDD ≥ 2.7 V) OL — 0.5 V IOL = 6 mA (VDD ≥ 2.3 V) — 0.5 IOL = 3 mA (VDD ≥ 1.8 V) — 0.5 Maximum total IOL for all port pins IOLT — 60 mA MC9S08GB60A Data Sheet, Rev. 2 264 Freescale Semiconductor

AppendixA Electrical Characteristics TableA-4. DC Characteristics (Sheet 3 of 3) (Temperature Range = –40 to 85°C Ambient) Parameter Symbol Min Typical1 Max Unit dc injection current4, 5, 6, 7, 8 V < V , V > V IN SS IN DD |I | Single pin limit IC — 0.2 mA — 5 mA Total MCU limit, includes sum of all stressed pins Input capacitance (all non-supply pins)(2) CIn — 7 pF 1 Typicals are measured at 25°C. 2 This parameter is characterized and not tested on each device. 3 Measurement condition for pull resistors: V = V for pullup and V = V for pulldown. In SS In DD 4 Power supply must maintain regulation within operating V range during instantaneous and operating maximum current DD conditions. If positive injection current (V > V ) is greater than I , the injection current may flow out of V and could result In DD DD DD in external power supply going out of regulation. Ensure external V load will shunt current greater than maximum injection DD current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. 5 All functional non-supply pins are internally clamped to V and V . SS DD 6 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 7 This parameter is characterized and not tested on each device. 8 IRQ does not have a clamp diode to V . Do not drive IRQ above V . DD DD PULLUP RESISTOR TYPICALS 40 PULLDOWN RESISTOR TYPICALS 85°C 40 25°C Ω) 85°C Ω) 35 –40°C E (k – 2450°°CC UP RESISTOR (k2350 WN RESISTANC 3305 PULL- ULLDO 25 20 P 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 20 V (V) 1.8 2.3 2.8 3.3 3.6 DD V (V) DD FigureA-1. Pullup and Pulldown Typical Resistor Values (V = 3.0 V) DD TYPICAL VOL VS IOL AT VDD = 3.0 V TYPICAL VOL VS VDD 1 85°C 0.4 85°C 25°C 25°C 0.8 –40°C –40°C 0.3 0.6 V (V)OL 0.4 V (V)OL 0.2 IOL = 6 mA IOL = 10 mA 0.1 0.2 I = 3 mA OL 0 0 0 10 20 30 1 2 3 4 V (V) I (mA) DD OL FigureA-2. Typical Low-Side Driver (Sink) Characteristics (Ports C and F) MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 265

AppendixA Electrical Characteristics TYPICAL V VS I AT V = 3.0 V TYPICAL V VS V OL OL DD OL DD 1.2 0.2 85°C 25°C 1 –40°C 0.15 0.8 V) 0.6 V) 0.1 V (OL 0.4 V (OL 0.05 85°C, IOL = 2 mA 0.2 25°C, IOL = 2 mA –40°C, IOL = 2 mA 0 0 0 5 10 15 20 1 2 3 4 V (V) I (mA) DD OL FigureA-3. Typical Low-Side Driver (Sink) Characteristics (Ports A, B, D, E, and G) TYPICAL V – V VS V AT SPEC I DD OH DD OH 0.4 TYPICAL V – V VS I AT V = 3.0 V 85°C 0.8 DD OH OH DD 25°C 85°C –40°C 25°C 0.3 V) 0.6 –40°C (H V) V – VDDO 00..24 – V (DOH 00..12 IOH = –6 mA IOH = –10 mA 0 VD IOH = –3 mA 0 –5 –10 –15 –20 –25 –30 0 I (mA) OH 1 2 3 4 V (V) DD FigureA-4. Typical High-Side Driver (Source) Characteristics (Ports C and F) TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V TYPICAL VDD – VOH VS VDD AT SPEC IOH 1.2 0.25 85°C 25°C 85°C, IOH = 2 mA 1 –40°C 0.2 25°C, IOH = 2 mA (V)H 0.8 (V)H 0.15 –40°C, IOH = 2 mA O O – V 0.6 – V D D 0.1 VD 0.4 VD 0.2 0.05 0 0 0 –5 –10 –15 –20 1 2 3 4 IOH (mA) VDD (V) FigureA-5. Typical High-Side (Source) Characteristics (Ports A, B, D, E, and G) MC9S08GB60A Data Sheet, Rev. 2 266 Freescale Semiconductor

AppendixA Electrical Characteristics A.6 Supply Current Characteristics TableA-5. Supply Current Characteristics Parameter Symbol V (V) Typical1 Max2 Temp. (°C) DD 2.1 mA4 55 3 1.1 mA 2.1 mA(4) 70 Run supply current3 measured at 2.1 mA(4) 85 RI DD (CPU clock = 2MHz, fBus = 1 MHz) 1.8 mA(4) 55 2 0.8 mA 1.8 mA(4) 70 1.8 mA(4) 85 7.5 mA(4) 55 3 6.5 mA 7.5 mA(4) 70 Run supply current (3) measured at 7.5 mA5 85 RI DD (CPU clock = 16MHz, fBus = 8 MHz) 5.8 mA(4) 55 2 4.8 mA 5.8 mA(4) 70 5.8 mA(4) 85 0.6 μA(4) 55 3 25 nA 1.8 μA(4) 70 4.0 μA(5) 85 Stop1 mode supply current S1I DD 500 nA(4) 55 2 20 nA 1.5 μA(4) 70 3.3 μA(4) 85 3.0 μA(4) 55 3 550 nA 5.5 μA(4) 70 11 μA(5) 85 Stop2 mode supply current S2I DD 2.4 μA(4) 55 2 400 nA 5.0 μA(4) 70 9.5 μA(4) 85 4.3 μA(4) 55 3 675 nA 7.2 μA(4) 70 17.0 μA(5) 85 Stop3 mode supply current S3I DD 3.5 μA(4) 55 2 500 nA 6.2 μA(4) 70 15.0 μA(4) 85 55 3 300 nA 70 85 RTI adder to stop2 or stop36 55 2 300 nA 70 85 MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 267

AppendixA Electrical Characteristics TableA-5. Supply Current Characteristics (continued) Parameter Symbol V (V) Typical1 Max2 Temp. (°C) DD 55 3 70 μA 70 LVI adder to stop3 85 (LVDSE = LVDE = 1) 55 2 60 μA 70 85 55 3 5 μA 70 Adder to stop3 for oscillator enabled7 85 (OSCSTEN =1) 55 2 5 μA 70 85 55 Adder for loss-of-clock enabled 3 9 μA 70 85 1 Typicals are measured at 25°C. See TableA-6 through TableA-9 for typical curves across voltage/temperature. 2 Values given here are preliminary estimates prior to completing characterization. 3 All modules except ATD active, ICG configured for FBE, and does not include any dc loads on port pins 4 Values are characterized but not tested on every part. 5 Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization. 6 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. Wait mode typical is 560 μA at 3 V and 422 μA at 2V with f = 1 MHz. Bus 7 Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0), clock monitor disabled (LOCD = 1). MC9S08GB60A Data Sheet, Rev. 2 268 Freescale Semiconductor

AppendixA Electrical Characteristics 18 16 14 12 20 MHz, ATD , FEE, 25°C off 10 20 MHz, ATD , FBE, 25°C off A) I (mDD 8 88 MMHHzz,, AATTDDooffff,, FFBEEE,, 2255°°CC 1 MHz, ATD , FEE, 25°C off 6 1 MHz, ATD , FBE, 25°C off 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.8 V (Vdc) DD FigureA-6. Typical Run I for FBE and FEE Modes, I vs V DD DD DD 1200 1000 A) 800 n (D 25°C D P1 I 600 70°C O ST 85°C 400 200 0 1.5 2 2.5 3 3.5 4 V (V) DD NOTES: 1. Clock sources and LVD are all disabled (OSCSTEN = LVDSE = 0). 2. All I/O are set as outputs and driven to V with no load. SS FigureA-7. Typical Stop1 I DD MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 269

AppendixA Electrical Characteristics 4 3.5 3 A) 2.5 μ (D 25°C D P2 I 2 70°C O ST 85°C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 V (V) NOTES: DD 1. Clock sources and LVD are all disabled (OSCSTEN = LVDSE = 0). 2. All I/O are set as outputs and driven to V with no load. SS FigureA-8. Typical Stop 2 I DD 8 7 6 A) 5 μ (D 25°C D P3 I 4 70°C O ST 85°C 3 2 1 0 1.5 2 2.5 3 3.5 4 V (V) DD NOTES: 1. Clock sources and LVD are all disabled (OSCSTEN = LVDSE = 0). 2. All I/O are set as outputs and driven to V with no load. SS FigureA-9. Typical Stop3 I DD MC9S08GB60A Data Sheet, Rev. 2 270 Freescale Semiconductor

AppendixA Electrical Characteristics A.7 ATD Characteristics TableA-6. ATD Electrical Ch aracteristics (Operating) No. Characteristic Condition Symbol Min Typ Max Unit 1 ATD supply1 V 1.80 — 3.6 V DDAD 2 ATD supply current Enabled I — 0.7 1.2 mA DDADrun Disabled (ATDPU = 0 I — 0.02 0.6 μA DDADstop or STOP) 3 Differential supply voltage V –V |V | — — 100 mV DD DDAD DDLT 4 Differential ground voltage V –V |V | — — 100 mV SS SSAD SDLT 5 Reference potential, low |V | — — V V REFL SSAD Reference potential, high 2.08V < V < 3.6V 2.08 — V DDAD DDAD V V REFH 1.80V < V < 2.08V V — V DDAD DDAD DDAD 6 Reference supply current Enabled I — 200 300 REF (V to V ) REFH REFL Disabled μA (ATDPU = 0 I — <0.01 0.02 REF or STOP) 7 Analog input voltage2 V V – 0.3 — V + 0.3 V INDC SSAD DDAD 1 V must be at same potential as V . DDAD DD 2 Maximum electrical operating range, not valid conversion range. TableA-7. ATD Timing/Performance Characteristics1 No. Characteristic Condition Symbol Min Typ Max Unit 1 ATD conversion clock 2.08V < V < 3.6V 0.5 — 2.0 DDAD frequency fATDCLK MHz 1.80V < V < 2.08V 0.5 — 1.0 DDAD 2 Conversion cycles ATDCLK CC 28 28 <30 (continuous convert)2 cycles 3 Conversion time 2.08V < V < 3.6V 14.0 — 60.0 DDAD T μs conv 1.80V < V < 2.08V 28.0 — 60.0 DDAD 4 Source impedance at input3 R — — 10 kΩ AS 5 Analog Input Voltage4 V V V V AIN REFL REFH 6 Ideal resolution (1 LSB)5 2.08V < V < 3.6V 2.031 — 3.516 DDAD RES mV 1.80V < V < 2.08V 1.758 — 2.031 DDAD 7 Differential non-linearity6 1.80V < VDDAD < 3.6V DNL — +0.5 +1.0 LSB 8 Integral non-linearity7 1.80 V < VDDAD < 3.6V INL — +0.5 +1.0 LSB MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 271

AppendixA Electrical Characteristics TableA-7. ATD Timing/Performance Characteristics1 (continued) No. Characteristic Condition Symbol Min Typ Max Unit 9 Zero-scale error8 1.80V < VDDAD < 3.6V EZS — +0.4 +1.0 LSB 10 Full-scale error9 1.80V < VDDAD < 3.6V EFS — +0.4 +1.0 LSB 11 Input leakage error 10 1.80V < VDDAD < 3.6V EIL — +0.05 +5 LSB Total unadjusted 12 error11 1.80V < VDDAD < 3.6V ETU — +1.1 +2.5 LSB 1 All ACCURACY numbers are based on processor and system being in WAIT state (very little activity and no IO switching) and that adequate low-pass filtering is present on analog input pins (filter with 0.01 μF to 0.1 μF capacitor between analog input and V ). REFL Failure to observe these guidelines may result in system or microcontroller noise causing accuracy errors which will vary based on board layout and the type and magnitude of the activity. 2 This is the conversion time for subsequent conversions in continuous convert mode. Actual conversion time for single conversions or the first conversion in continuous mode is extended by one ATD clock cycle and 2 bus cycles due to starting the conversion and setting the CCF flag. The total conversion time in Bus Cycles for a conversion is: SC Bus Cycles = ((PRS+1)×2) × (28+1) + 2 CC Bus Cycles = ((PRS+1)×2) × (28) 3 R is the real portion of the impedance of the network driving the analog input pin. Values greater than this amount may not fully AS charge the input circuitry of the ATD resulting in accuracy error. 4 Analog input must be between V and V for valid conversion. Values greater than V will convert to 0x3FF less the REFL REFH REFH full scale error (E ). FS 5 The resolution is the ideal step size or 1LSB = (V –V )/1024 REFH REFL 6 Differential non-linearity is the difference between the current code width and the ideal code width (1LSB). The current code width is the difference in the transition voltages to and from the current code. 7 Integral non-linearity is the difference between the transition voltage to the current code and the adjusted ideal transition voltage for the current code. The adjusted ideal transition voltage is (Current Code–1/2)×(1/((V +E )–(V +E ))). REFH FS REFL ZS 8 Zero-scale error is the difference between the transition to the first valid code and the ideal transition to that code. The Ideal transition voltage to a given code is (Code–1/2)×(1/(V –V )). REFH REFL 9 Full-scale error is the difference between the transition to the last valid code and the ideal transition to that code. The ideal transition voltage to a given code is (Code–1/2)×(1/(V –V )). REFH REFL 10Input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pin. Reducing the impedance of the network reduces this error. 11Total unadjusted error is the difference between the transition voltage to the current code and the ideal straight-line transfer function. This measure of error includes inherent quantization error (1/2LSB) and circuit error (differential, integral, zero-scale, and full-scale) error. The specified value of E assumes zero E (no leakage or zero real source impedance). T IL MC9S08GB60A Data Sheet, Rev. 2 272 Freescale Semiconductor

AppendixA Electrical Characteristics A.8 Internal Clock Generation Module Characteristics ICG EXTAL XTAL RF RS Crystal or Resonator (See Note) C 1 C 2 NOTE: Use fundamental mode crystal or ceramic resonator only. TableA-8. ICG DC Electrical Specifications (Temperature Range = –40 to 85°C Ambient) Characteristic Symbol Min Typ1 Max Unit Load capacitors C 1 See Note 2 C 2 Feedback resistor Low range (32k to 100 kHz) R 10 MΩ F High range (1M – 16 MHz) 1 MΩ Series resistor Low range Low Gain (HGO = 0) — 0 — High Gain (HGO = 1) — 100 — High range R kΩ Low Gain (HGO = 0) S — 0 — High Gain (HGO = 1) ≥ 8 MHz — 0 — 4 MHz — 10 — 1 MHz — 20 — 1 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. 2 See crystal or resonator manufacturer’s recommendation. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 273

AppendixA Electrical Characteristics A.8.1 ICG Frequency Specifications TableA-9. ICG Freque ncy Specifications (V = V (min) to V (max), Temperature Range = –40 to 85°C Ambient) DDA DDA DDA Characteristic Symbol Min Typical Max Unit Oscillator crystal or resonator4 (REFS = 1) (Fundamental mode crystal or ceramic resonator) Low range flo 32 — 100 kHz High range High Gain, FBE (HGO=1,CLKS = 10) fhi_byp 1 — 16 MHz High Gain, FEE (HGO=1,CLKS = 11) fhi_eng 2 — 10 MHz Low Power, FBE (HGO=0, CLKS=10) flp_byp 1 — 10 MHz Low Power, FEE (HGO=0, CLKS=11) flp_eng 2 — 10 MHz Input clock frequency (CLKS=11, REFS=0) Low range flo 32 — 100 kHz High range fhi_eng 2 — 10 MHz Input clock frequency (CLKS=10, REFS=0) fExtal 0 — 40 MHz Internal reference frequency (untrimmed) fICGIRCLK 182.25 243 303.75 kHz Duty cycle of input clock4 (REFS=0) tdc 40 — 60 % Output clock ICGOUT frequency CLKS=10, REFS=0 f (max) All other cases fICGOUT fExtal (min) fExtal MHz f (min) ICGDCLKmax lo (max) Minimum DCO clock (ICGDCLK) frequency fICGDCLKmin 8 — MHz Maximum DCO clock (ICGDCLK) frequency fICGDCLKmax — 40 MHz Self-clock mode (ICGOUT) frequency 1 fSelf fICGDCLKmin fICGDCLKmax MHz Self-clock mode reset (ICGOUT) frequency fSelf_reset 5.5 8 10.5 MHz Loss of reference frequency 2 Low range fLOR 5 25 kHz High range 50 500 Loss of DCO frequency 3 f LOD 0.5 1.5 MHz Crystal start-up time 4, 5 Low range t CSTL — 430 — High range ms t — 4 — CSTH FLL lock time 4, 6 Low range tLockl — 2 ms High range t — 2 Lockh FLL frequency unlock range nUnlock –4*N 4*N counts FLL frequency lock range nLock –2*N 2*N counts ICGOUT period jitter, 4, 7 measured at f Max ICGOUT Long term jitter (averaged over 2 ms interval) CJitter % f — 0.2 ICG Internal oscillator deviation from trimmed frequency8 V = 1.8 – 3.6 V, (constant temperature) — ±0.5 ±2 VDD = 3.0 V ±10%, –40° C to 85° C ACCint — ±0.5 ±2 % DD MC9S08GB60A Data Sheet, Rev. 2 274 Freescale Semiconductor

AppendixA Electrical Characteristics 1 Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop. 2 Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it is not in the desired range. 3 Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode (if an external reference exists) if it is not in the desired range. 4 This parameter is characterized before qualification rather than 100% tested. 5 Proper PC board layout procedures must be followed to achieve specifications. 6 This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external modes. If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . ICGOUT Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via V and V and variation in crystal oscillator frequency increase the C DDA SSA Jitter percentage for a given interval. 8 See FigureA-10 0.1 80 100 120 –60 –40 –20 0 20 20 60 –0.1 %) T ( N –0.2 E C R E P –0.3 –0.4 2 V –0.5 3 V –0.6 TEMPERATURE (°C) FigureA-10. Internal Oscillator Deviation from Trimmed Frequency A.9 AC Characteristics This section describes ac timing characteristics for each peripheral system. For detailed information about how clocks for the bus are generated, see Chapter 7, “Internal Clock Generator (S08ICGV2).” MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 275

AppendixA Electrical Characteristics A.9.1 Control Timing TableA-10. Co ntrol Timing Parameter Symbol Min Typical Max Unit Bus frequency (tcyc = 1/fBus) fBus dc — 20 MHz Real-time interrupt internal oscillator period tRTI 700 1300 μs 1.5 x External reset pulse width1 textrst f — ns Self_reset 34 x Reset low drive2 trstdrv f — ns Self_reset Active background debug mode latch setup time tMSSU 25 — ns Active background debug mode latch hold time tMSH 25 — ns IRQ pulse width3 tILIH 1.5 x tcyc — ns Port rise and fall time (load = 50 pF)4 Slew rate control disabled tRise, tFall — 3 ns Slew rate control enabled — 30 1 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 2 When any reset is initiated, internal circuitry drives the reset pin low for about 34cycles of f and then samples the level Self_reset on the reset pin about 38cycles later to distinguish external reset requests from internal requests. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V and 80% V levels. Temperature range –40°C to 85°C. DD DD t extrst RESET PIN FigureA-11. Reset Timing BKGD/MS RESET t MSH t MSSU FigureA-12. Active Background Debug Mode Latch Timing MC9S08GB60A Data Sheet, Rev. 2 276 Freescale Semiconductor

AppendixA Electrical Characteristics t ILIH IRQ FigureA-13. IRQ Timing A.9.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. TableA-11. TPM Input Timing Function Symbol Min Max Unit External clock frequency fTPMext dc fBus/4 MHz External clock period tTPMext 4 — tcyc External clock high time tclkh 1.5 — tcyc External clock low time tclkl 1.5 — tcyc Input capture pulse width tICPW 1.5 — tcyc t Text t clkh TPMxCHn t clkl FigureA-14. Timer External Clock t ICPW TPMxCHn TPMxCHn t ICPW FigureA-15. Timer Input Capture Pulse MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 277

AppendixA Electrical Characteristics A.9.3 SPI Timing Table A-12 and FigureA-16 through Figure A-19 describe the timing requirements for the SPI system. TableA-12. SPI Timing No. Function Symbol Min Max Unit Operating frequency Master f f /2048 f /2 Hz op Bus Bus Slave dc f /4 Bus SCK period 1 Master t 2 2048 t SCK cyc Slave 4 — t cyc Enable lead time 2 Master t 1/2 — t Lead SCK Slave 1 — t cyc Enable lag time 3 Master t 1/2 — t Lag SCK Slave 1 — t cyc Clock (SCK) high or low time 4 Master t t – 30 1024 t ns WSCK cyc cyc Slave t – 30 — ns cyc Data setup time (inputs) 5 Master t 15 — ns SU Slave 15 — ns Data hold time (inputs) 6 Master t 0 — ns HI Slave 25 — ns 7 Slave access time t — 1 t a cyc 8 Slave MISO disable time t — 1 t dis cyc Data valid (after SCK edge) 9 Master t — 25 ns v Slave — 25 ns Data hold time (outputs) 10 Master t 0 — ns HO Slave 0 — ns Rise time 11 Input t — t – 25 ns RI cyc Output t — 25 ns RO Fall time 12 Input t — t – 25 ns FI cyc Output t — 25 ns FO MC9S08GB60A Data Sheet, Rev. 2 278 Freescale Semiconductor

AppendixA Electrical Characteristics SS1 (OUTPUT) 2 1 11 3 SCK 4 (CPOL = 0) (OUTPUT) 4 12 SCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 9 9 10 MOSI (OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. FigureA-16. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 12 11 3 SCK (CPOL = 0) (OUTPUT) 4 4 11 12 SCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MSB IN(2) BIT 6 . . . 1 LSB IN 9 10 MOSI PORT DATA MASTER MSB OUT(2) BIT 6 . . . 1 MASTER LSB OUT PORT DATA (OUTPUT) NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. FigureA-17. SPI Master Timing (CPHA = 1) MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 279

AppendixA Electrical Characteristics SS (INPUT) 1 12 11 3 SCK (CPOL = 0) (INPUT) 2 4 4 11 12 SCK (CPOL = 1) (INPUT) 8 7 9 10 10 MISO SEE (OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE 5 6 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally MSB of character just received FigureA-18. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 12 11 SCK (CPOL = 0) (INPUT) 4 4 11 12 SCK (CPOL = 1) (INPUT) 9 10 8 MISO SEE (OUTPUT) NOTE SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT 7 5 6 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received FigureA-19. SPI Slave Timing (CPHA = 1) MC9S08GB60A Data Sheet, Rev. 2 280 Freescale Semiconductor

AppendixA Electrical Characteristics A.10 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal V supply. DD For more detailed information about program/erase operations, see Chapter4, “Memory.” TableA-13. Flash Characteristics Characteristic Symbol Min Typical Max Unit Supply voltage for program/erase Vprog/erase 1.8 3.6 V Supply voltage for read operation 0 < fBus < 8 MHz VRead 1.8 3.6 V 0 < f < 20 MHz 2.08 3.6 Bus Internal FCLK frequency1 fFCLK 150 200 kHz Internal FCLK period (1/FCLK) tFcyc 5 6.67 μs Byte program time (random location)(2) tprog 9 tFcyc Byte program time (burst mode)(2) tBurst 4 tFcyc Page erase time2 tPage 4000 tFcyc Mass erase time(2) tMass 20,000 tFcyc Program/erase endurance3 T to T = –40°C to + 85°C 10,000 — cycles L H T = 25°C 100,000 — Data retention4 tD_ret 15 100 — years 1 The frequency of this clock is controlled by a software setting. 2 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 281

AppendixA Electrical Characteristics MC9S08GB60A Data Sheet, Rev. 2 282 Freescale Semiconductor

Appendix B EB652: Migrating from the GB60 Series to the GB60A Series The following text was taken from Freescale Semiconductor document EB652. It is copied here for your conveninece. Please see EB652 at freescale.com for the must up-to-date information regarding “Migrating from the GB60 series to the GB60A series.” B.1 Overview This document will explain the differences to be aware of when migrating from the MC9S08GB60, MC9S08GB32, MC9S08GT60, and MC9S08GT32 devices to the MC9S08GB60A, MC9S08GB32A, MC9S08GT60A and MC9S08GT32A devices. For the remainder of this document, GB60 series will refer to the original non-”A” devices and GB60A series will refer to the newer “A” suffix devices. Much of the functionality and performance of the GB60 series and the GB60A series will be identical. However, there are several differences designers should understand when migrating to the GB60A series. B.2 Flash Programming Voltage The GB60 series has a minimum V requirement for erasing and programming the flash, equal to 2.1V. DD The GB60A series eliminates this minimum V requirement. On the GB60A series, the flash can be DD programmed and erased across the full operating voltage range of the MCU, or 1.8V to 3.6V. B.3 Flash Block Protection: 60K Devices Only The GB/GT60 flash block protection has a redundant setting. On the GB/GT60A, the redundant setting is used to add a new protection option. On the GB/GT60, when protection is enabled by setting the FPDIS bit, setting the FPS2:FPS1:FPS0 bits to 1:1:1 protects the same range as 1:1:0, which is locations $8000 to $FFFF. On the GB/GT60A, setting the FPS2:FPS1:FPS0 bits to 1:1:0, protects the same range as on the GB/GT60. However, setting the bits to 1:1:1 protects locations $182C to $FFFF, leaving locations $1080 to $17FF open to reprogramming. This new protection option is useful for protecting the main user program area while leaving a small section of 1920 bytes available for data storage. B.4 Internal Clock Generator: High Gain Oscillator Option The GB60 series only has a low-power external oscillator, designed for the low current consumption. The GB60A series has a second external oscillator option: a high gain external oscillator which provides MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 283

AppendixB EB652: Migrating from the GB60 Series to the GB60A Series improved noise immunity in the oscillator circuit. The low-power oscillator is also available for power-sensitive applications. This new oscillator option available on the GB60A series is selected by a new control bit in the ICG control register 1 (ICGC1): the HGO bit. HGO is bit 7 of the ICGC1 register, formerly an unimplemented bit that always read ‘0’. The reset value is ‘0’, which selects the low-power oscillator option—which is consistent with the GB60 series external oscillator. Setting HGO to ‘1’ selects the high gain external oscillator which increases the voltage swing across the external crystal or resonator, making it more immune to external noise. The values of the feedback and series resistors for the external oscillator will be different in most cases between HGO=0 and HGO=1. Consult the ICG DC Electrical Specifications table in the MC9S08GB60A data sheet for the proper values. B.5 Internal Clock Generator: Low-Power Oscillator Maximum Frequency On the GB60 series, the external oscillator’s maximum frequency is 10 MHz when in FEE mode and 16MHz when in FBE mode. On the GB60A series, when HGO=1, the same maximum frequencies apply. However, when HGO=0, the maximum frequency is 10 MHz in FEE and FBE modes. B.6 Internal Clock Generator: Loss-of-Clock Disable Option The ICG module has a clock monitor which will generate a loss-of-clock signal when either the reference clock or the DCO clock does not meet minimum frequency requirements. This signal is used to generate either a reset or an interrupt, depending on the settings in the ICGC2 register. On the GB60 series, this clock monitor cannot be turned on or off by the user. The on/off status of the clock monitor is determined by the state of the ICG module. On the GB60A series, an option has been added to allow the user to disable the clock monitor. A new control bit, LOCD, has been added to the ICGC1 register at bit position 1, formerly an unimplemented bit. The reset state is ‘0’, which enables the clock monitor. Setting LOCD = 1 will disable the clock monitor and thereby eliminate any loss-of-clock resets or interrupts. The advantage of disabling the clock monitor is to reduce the current draw of the ICG module. Disabling the clock monitor when running in stop3 mode with a low-range external oscillator enabled will save approximately 9 μA of current. With LOCD=0 in this configuration, the stop3 I is about 14 μA. When DD LOCD=1 in this configuration, the stop I is about 5 μA. DD For the best combination of power conservation and system protection, Freescale Semiconductor recommends setting the LOCD=0 whenever the MCU is in active run mode and then setting LOCD=1 just before entering stop3 mode when OSCSTEN=1. If OSCSTEN=0, then the LOCD bit will not make a difference in the stop3 current. MC9S08GB60A Data Sheet, Rev. 2 284 Freescale Semiconductor

AppendixB EB652: Migrating from the GB60 Series to the GB60A Series B.7 System Device Identification Register The system device identification register (SDIR) is a 16-bit value that contains a 12-bit part identification number and a 4-bit mask revision number. Both the GB60 series and the GB60A series have the same part identification number, $002. The mask revision number for the last production version of the GB60 series is $4. The first mask revision number for the GB60A series is $8. MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 285

AppendixB EB652: Migrating from the GB60 Series to the GB60A Series MC9S08GB60A Data Sheet, Rev. 2 286 Freescale Semiconductor

Appendix C Ordering Information and Mechanical Drawings C.1 Ordering Information This section contains ordering numbers for MC9S08GB60A, MC9S08GB32A, MC9S08GT60A, and MC9S08GT32A devices. See below for an example of the device numbering system. TableC-1. Device Numbering System Available Device Number Flash Memory RAM TPM Package Type One 3-channel and MC9S08GB60A 60K 4K 64 LQFP one 5-channel 16-bit timer One 3-channel and MC9S08GB32A 32K 2K 64 LQFP one 5-channel 16-bit timer One 3-channel and 48 QFN one 2-channel 16-bit timer MC9S08GT60A 60K 4K Two 2-channel/16-bit timers 44 QFP 42 SDIP One 3-channel and 48 QFN one 2-channel 16-bit timer MC9S08GT32A 32K 2K Two 2-channel/16-bit timers 44 QFP 42 SDIP MC 9 S08 GB60A C XX Status Package designator (MC = Fully qualified) (See TableC-2) Memory Type Temperature range (9 = Flash-based) (C = –40°C to 85°C) Core Family TableC-2. Package Information Pin Count Type Designator Document No. 64 LQFP — Low Quad Flat Package FU 98ASS23234W 48 QFN — Quad Flat Package, No Leads FD 98ARH99048A 44 QFP — Quad Flat Package FB 98ASB42839B 42 SDIP — Skinny Dual In-Line Package B 98ASB42767B MC9S08GB60A Data Sheet, Rev. 2 Freescale Semiconductor 287

AppendixC Ordering Information and Mechanical Drawings C.2 Mechanical Drawings The following pages are mechanical drawings for the packages provided in TableC-2. MC9S08GB60A Data Sheet, Rev. 2 288 Freescale Semiconductor

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: MC9S08GB60ACFUER MC9S08GT60ACFDER MC9S08GT16ACFBER MC9S08GT60ACFBER MC9S08GT8ACFBER MC9S08GT32ACFDER MC9S08GT16ACFCER MC9S08GB60ACFUE MC9S08GT60ACFBE MC9S08GB32ACFUE MC9S08GT60ACFDE MC9S08GT32ACFDE MC9S08GT32ACFBE MC9S08GT16ACFBE MC9S08GT16ACFCE MC9S08GT16ACFDE MC9S08GT16ACFDER MC9S08GT16AMFBE MC9S08GT16AMFCE MC9S08GT16AMFDE MC9S08GT32ACBE MC9S08GT32ACFBER MC9S08GT60ACBE MC9S08GT8ACFBE MC9S08GT8ACFCE MC9S08GT8ACFDE MC9S08GT8AMFBE MC9S08GT8AMFCE MC9S08GT8AMFDE