Freescale Semiconductor DDooccuummeenntt NNuummbbeerr:: MMCC99SS0088FFLL1166 Data Sheet: Technical Data RReevv.. 44,, 55//22001155 MC9S08FL16 MC9S08FL16 Series Covers: MC9S08FL16 and MC9S08FL8 32-Pin LQFP 32-Pin SDIP 873A-03 1376-02 (cid:129) Illegal address detection with reset Features: (cid:129) Flash block protection 8-Bit S08 Central Processor Unit (CPU) Development Support • Up to 20 MHz CPU at 4.5 V to 5.5 V across (cid:129) Single-wire background debug interface temperature range of –40 °C to 85 °C (cid:129) Breakpoint capability to allow single breakpoint (cid:129) HC08 instruction set with added BGND instruction setting during in-circuit debugging (plus two more (cid:129) Support for up to 32 interrupt/reset sources breakpoints). (cid:129) On-chip in-circuit emulator (ICE) debug module On-Chip Memory containing two comparators and nine trigger (cid:129) Up to 16 KB flash read/program/erase over full modes. operating voltage and temperature (cid:129) Up to 1024-byte random-access memory (RAM) Peripherals (cid:129) Security circuitry to prevent unauthorized access • IPC — Interrupt priority controller to provide to RAM and flash contents hardware based nested interrupt mechanism Power-Saving Modes (cid:129) ADC — 12-channel, 8-bit resolution; 2.5μs conversion time; automatic compare function; (cid:129) Two low power stop modes; reduced power wait 1.7mV/°C temperature sensor; internal bandgap mode reference channel; operation in stop; optional (cid:129) Allows clocks to remain enabled to specific hardware trigger; fully functional from 4.5 V to peripherals in stop3 mode 5.5 V (cid:129) TPM — One 4-channel and one 2-channel Clock Source Options timer/pulse-width modulators (TPM) modules; (cid:129) Oscillator (XOSC) — Loop-control Pierce selectable input capture, output compare, or oscillator; crystal or ceramic resonator range of buffered edge- or center-aligned PWM on each 31.25 kHz to 39.0625 kHz or 1 MHz to 16 MHz channel (cid:129) Internal Clock Source (ICS) — Internal clock (cid:129) MTIM16 — One 16-bit modulo timer with optional source module containing a prescaler frequency-locked-loop (FLL) controlled by internal • SCI — One serial communications interface or external reference; precision trimming of module with optional 13-bit break; LIN extensions internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports Input/Output bus frequencies up to 10 MHz (cid:129) 30 GPIOs including 1 output-only pin and 1 System Protection input-only pin (cid:129) Watchdog computer operating properly (COP) Package Options reset with option to run from dedicated 1 kHz (cid:129) 32-pin SDIP internal clock source or bus clock (cid:129) 32-pin LQFP (cid:129) Low-voltage detectionwith reset or interrupt; selectable trip points (cid:129) Illegal opcode detection with reset This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. ©Freescale Semiconductor, Inc., 2009-2015. All rights reserved.

Table of Contents 1 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 System Clock Distribution. . . . . . . . . . . . . . . . . . . . . . .4 5.9 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 21 3 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5.9.1 Control Timing. . . . . . . . . . . . . . . . . . . . . 22 4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 5.9.2 TPM Module Timing . . . . . . . . . . . . . . . . 23 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .9 5.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 24 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . 26 5.2 Parameter Classification . . . . . . . . . . . . . . . . . . .9 5.12 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . 27 5.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . .9 5.12.1Radiated Emissions. . . . . . . . . . . . . . . . . 27 5.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . .10 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 ESD Protection and Latch-Up Immunity . . . . . .11 7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . .12 7.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . 28 5.7 Supply Current Characteristics . . . . . . . . . . . . .17 5.8 External Oscillator (XOSC) and ICS Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev Date Description of Changes 1 March 18, 2009 Initial public release. 2 July 20, 2009 Updated Section5.12, “EMC Performance.” and corrected Figure1 and Table1. Corrected default trim value to 31.25 kHz. 3 Nov. 29, 2010 Updated Table7. 4 May, 2015 Corrected pin 12 of the Figure3. Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9S08FL16RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. MC9S08FL16 Series Data Sheet, Rev. 4 2 Freescale Semiconductor

MCU Block Diagram 1 MCU Block Diagram The block diagram, Figure 1, shows the structure of MC9S08FL16 series MCU. PTA0/ADP0 16-BIT MODULO TIMER TCLK HCS08 CORE (MTIM16) PTA1/ADP1 PTA2/ADP2 CPU BDC A 2-CH TIMER/PWM TPM2CH[1:0] T PTA3/ADP3 R MODULE (TPM2) O PTA4/BKGD/MS P HCS08 SYSTEM CONTROL PTA5/IRQ/TCLK/RESET RESETS AND INTERRUPTS MODES OF OPERATION PTA6/TPM2CH0 RESET POWER MANAGEMENT IRQ PTA7/TPM2CH1 COP IRQ INTERRUPT PRIORITY LVD CONTROLLER (IPC) PTB0/RxD/ADP4 PTB1/TxD/ADP5 ON-CHIP ICE AND SERIAL COMMUNICATIONS TxD DEBUG MODUE (DBG) RxD PTB2/ADP6 INTERFACE (SCI) B T PTB3/ADP7 USER FLASH R MC9S08FL16 — 16,384 BYTES O PTB4/TPM1CH0 P MC9S08FL8 — 8,192 BYTES 4-CH TIMER/PWM TPM1CH[3:0] PTB5/TPM1CH1 USER RAM MODULE (TPM1) PTB6/XTAL MC9S08FL16 — 1,024 BYTES PTB7/EXTAL MC9S08FL8 — 768 BYTES PTC0/ADP8 20 MHz INTERNAL CLOCK SOURCE (ICS) PTC1/ADP9 PTC2/ADP10 EXTAL XTAL EXSTOERUNRACLE O(XSOCSILCL)ATOR T C PTC3/ADP11 R O PTC4 P VDD PTC5 VSS VOLTAGE REGULATOR PTC6 PTC7 VVRREEFFHL 12-CH 8-BIT ADP[11:0] VDDA ANALOG-TO-DIGITAL VSSA CONVERTER (ADC) PTD0 PTD1 T D PTD2/TPM1CH2 R O PTD3/TPM1CH3 P PTD4 NOTE 1. PTA4 is output only when used as port pin. PTD5 2. PTA5 is input only when used as port pin. Figure1. MC9S08FL16 Series Block Diagram MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 3

System Clock Distribution 2 System Clock Distribution MC9S08FL16 series use ICS module as clock sources. The ICS module can use internal or external clock source as reference to provide up to 20 MHz CPU clock. The output of ICS module includes, • OSCOUT — XOSC output provides external reference clock to ADC. • ICSFFCLK — ICS fixed frequency clock reference (around 32.768 kHz) provides double of the fixed lock signal to TPMs and MTIM16. • ICSOUT — ICS CPU clock provides double of the bus clock which is basic clock reference of peripherals. • ICSLCLK — Alternate BDC clock provides debug signal to BDC module. The TCLK pin is an extra external clock source. When TCLK is enabled, it can provide alternate clock source to TPMs and MTIM16. The on-chip 1 kHz clock provides clock source of COP module. TCLK 1 kHz COP TPM1 TPM2 MTIM16 ADC OSCOUT ICSFFCLK FIXED CLOCK (XCLK) ÷2 ICS ICSOUT BUS CLOCK ÷2 ICSLCLK XOSC CPU SCI BDC FLASH RAM IPC EXTAL XTAL Figure2. System Clock Distribution Diagram MC9S08FL16 Series Data Sheet, Rev. 4 4 Freescale Semiconductor

Pin Assignments 3 Pin Assignments This section shows the pin assignments for the MC9S08FL16 series devices. PTC5 1 32 PTC6 PTC4 2 31 PTC7 PTA5/IRQ/TCLK/RESET 3 30 PTA0/ADP0 PTD2/TPM1CH2 4 29 PTD5 PTA4/BKGD/MS 5 28 PTA1/ADP1 PTD0 6 27 PTA2/ADP2 PTD1 7 26 PTA3/ADP3 VDD 8 25 PTA6/TPM2CH0 V 9 24 PTA7/TPM2CH1 SS PTB7/EXTAL 10 23 PTB0/RxD/ADP4 PTB6/XTAL 11 22 PTB1/TxD/ADP5 PTB5/TPM1CH1 12 21 PTB2/ADP6 PTD3/TPM1CH3 13 20 PTD4 PTB4/TPM1CH0 14 19 PTB3/ADP7 PTC3/ADP11 15 18 PTC0/ADP8 PTC2/ADP10 16 17 PTC1/ADP9 Figure3. MC9S08FL16 Series 32-Pin SDIP Package MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 5

Pin Assignments T E S E R 2 K/ H L C C 1 T 0 2/TPM 5/IRQ/ 4 5 6 7 0/ADP 5 D A C C C C A D T T T T T T T T P P P P P P P P 5 2 2 1 0 9 8 7 6 3 3 3 2 2 2 2 PTA4/BKGD/MS 1 24 PTA1/ADP1 PTD0 2 23 PTA2/ADP2 PTD1 3 22 PTA3/ADP3 VDD 4 21 PTA6/TPM2CH0 VSS 5 20 PTA7/TPM2CH1 PTB7/EXTAL 6 19 PTB0/RxD/ADP4 PTB6/XTAL 7 18 PTB1/TxD/ADP5 PTB5/TPM1CH1 8 17 PTB2/ADP6 0 1 2 3 4 5 6 1 1 1 1 1 1 1 9 3 0 1 0 9 8 7 4 H H 1 1 P P P D C C P P D D D T 1 1 D D A A A P PM PM 3/A 2/A C1/ C0/ B3/ T T C C T T T 3/ 4/ T T P P P D B P P T T P P Figure4. MC9S08FL16 Series 32-Pin LQFP Package Table1. Pin Availability by Package Pin-Count Pin Number <-- Lowest Priority --> Highest 32-SDIP 32-LQFP Port Pin I/O Alt 1 I/O Alt 2 I/O Alt 3 I/O 1 29 PTC5 I/O 2 30 PTC4 I/O 3 31 PTA5 I IRQ I TCLK I RESET I 4 32 PTD2 I/O TPM1CH2 I/O 5 1 PTA4 O BKGD I MS I 6 2 PTD0 I/O 7 3 PTD1 I/O 8 4 V I DD 9 5 V I SS 10 6 PTB7 I/O EXTAL I 11 7 PTB6 I/O XTAL O 12 8 PTB5 I/O TPM1CH1 I/O 13 9 PTD3 I/O TPM1CH3 I/O 14 10 PTB4 I/O TPM1CH0 I/O 15 11 PTC3 I/O ADP11 I MC9S08FL16 Series Data Sheet, Rev. 4 6 Freescale Semiconductor

Pin Assignments Table1. Pin Availability by Package Pin-Count (continued) Pin Number <-- Lowest Priority --> Highest 32-SDIP 32-LQFP Port Pin I/O Alt 1 I/O Alt 2 I/O Alt 3 I/O 16 12 PTC2 I/O ADP10 I 17 13 PTC1 I/O ADP9 I 18 14 PTC0 I/O ADP8 I 19 15 PTB3 I/O ADP7 I 20 16 PTD4 I/O 21 17 PTB2 I/O ADP6 I 22 18 PTB1 I/O TxD I/O ADP5 I 23 19 PTB0 I/O RxD I ADP4 I 24 20 PTA7 I/O TPM2CH1 I/O 25 21 PTA6 I/O TPM2CH0 I/O 26 22 PTA3 I/O ADP3 I 27 23 PTA2 I/O ADP2 I 28 24 PTA1 I/O ADP1 I 29 25 PTD5 I/O 30 26 PTA0 I/O ADP0 I 31 27 PTC7 I/O 32 28 PTC6 I/O NOTE When an alternative function is first enabled, it is possible to get a spurious edge to the module. User software must clear out any associated flags before interrupts are enabled. Table 1 illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. Disable all modules that share a pin before enabling another module. MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 7

Memory Map 4 Memory Map Figure 5 shows the memory map for the MC9S08FL16 series. On-chip memory in the MC9S08FL16 series of MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into two groups: • Direct-page registers (0x0000 through 0x003F) • High-page registers (0x1800 through 0x187F) $0000 $0000 DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS $003F $003F $0040 $0040 RAM 768 BYTES $033F RAM 1024 BYTES $0340 $043F $0440 UNIMPLEMENTED UNIMPLEMENTED $17FF $17FF $1800 $1800 HIGH PAGE REGISTERS HIGH PAGE REGISTERS $187F $187F $1880 $1880 UNIMPLEMENTED UNIMPLEMENTED $BFFF $C000 FLASH $DFFF $E000 16384 BYTES FLASH 8192 BYTES $FFFF $FFFF MC9S08FL8 MC9S08FL16 Figure5. MC9S08FL16 Series Memory Map MC9S08FL16 Series Data Sheet, Rev. 4 8 Freescale Semiconductor

Electrical Characteristics 5 Electrical Characteristics 5.1 Introduction This section contains electrical and timing specifications for the MC9S08FL16 series of microcontrollers available at the time of publication. 5.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table2. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant C sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices T under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 5.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the programmable SS DD pullup resistor associated with the pin is enabled. MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 9

Electrical Characteristics Table3. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage V –0.3 to 5.8 V DD Maximum current into V I 120 mA DD DD Digital input voltage V –0.3 to V +0.3 V In DD Instantaneous maximum current I ±25 mA Single pin limit (applies to all port pins)1,2,3 D Storage temperature range T –55 to 150 °C stg 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (V ) and negative (V ) clamp DD SS voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTA5 are internally clamped to V and V . SS DD 3 Power supply must maintain regulation within operating V range during instantaneous and DD operating maximum current conditions. If positive injection current (V > V ) is greater than In DD I , the injection current may flow out of V and could result in external power supply going DD DD out of regulation. Ensure external V load will shunt current greater than maximum injection DD current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 5.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine the difference between actual pin I/O voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high SS DD pin current (heavy loads), the difference between pin voltage and V or V will be very small. SS DD Table4. Thermal Characteristics Rating Symbol Value Unit Operating temperature range T to T T L H °C (packaged) A –40 to 85 Thermal resistance Single-layer board 32-pin SDIP 60 θ °C/W JA 32-pin LQFP 85 Thermal resistance Four-layer board 32-pin SDIP 35 θ °C/W JA 32-pin LQFP 56 The average chip-junction temperature (T ) in °C can be obtained from: J MC9S08FL16 Series Data Sheet, Rev. 4 10 Freescale Semiconductor

Electrical Characteristics T = T + (P × θ ) Eqn.1 J A D JA where: T = Ambient temperature, °C A θ = Package thermal resistance, junction-to-ambient, °C/W JA P = P + P D int I/O P = I × V , Watts — chip internal power int DD DD P = Power dissipation on input and output pins — user determined I/O For most applications, P far much smaller than P and can be neglected. An approximate relationship I/O int between P and T (if P is neglected) is: D J I/O P = K ÷ (T + 273 °C) Eqn.2 D J Solving Equation1 and Equation2 for K gives: K = P × (T + 273 °C) + θ × (P )2 Eqn.3 D A JA D where K is a constant pertaining to the particular part. K can be determined from Equation3 by measuring P (at equilibrium) for an known T . Using this value of K, the values of P and T can be obtained by D A D J solving Equation1 and Equation2 iteratively for any value of T . A 5.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions must be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. During the device qualification, ESD stresses were performed for the human body model (HBM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification. Table5. ESD and Latch-Up Test Conditions Model Description Symbol Value Unit Series resistance R1 1500 Ω Human Storage capacitance C 100 pF body Number of pulses per pin — 3 — Minimum input voltage limit — –2.5 V Latch-up Maximum input voltage limit — 7.5 V MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 11

Electrical Characteristics Table6. ESD and Latch-Up Protection Characteristics No. Rating1 Symbol Min Max Unit 1 Human body model (HBM) VHBM ±2000 — V 2 Charge device model (CDM) VCDM ±500 — V 3 Latch-up current at TA = 85 °C ILAT ±100 — mA 1 Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. 5.6 DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table7. DC Characteristics Num C Characteristic Symbol Condition Min. Typical1 Max. Unit 1 P Operating voltage — — 4.5 — 5.5 V All I/O pins, C I = –2 mA V – 1.5 — — Output high low-drive strength Load DD 2 V V voltage All I/O pins, OH P I = –10 mA V – 1.5 — — high-drive strength Load DD Output high D Max total I for all ports I — — — 100 mA 3 current OH OHT All I/O pins, C I = 2 mA — — 1.5 Output low low-drive strength Load 4 V V voltage All I/O pins, OL P I = 10 mA — — 1.5 high-drive strength Load Output low 5 D Max total I for all ports I — — — 100 mA current OL OLT Input high 6 P All digital inputs V — 0.65 × V — — V voltage IH DD Input low 7 P All digital inputs V — — — 0.35 × V V voltage IL DD Input 8 C All digital inputs V — 0.06 × V — — mV hysteresis hys DD Input All input only pins 9 P leakage |I | V = V or V — 0.1 1 μA (per pin) In In DD SS current Hi-Z (off-state) All input/output 10 P leakage (per pin) |IOZ| VIn = VDD or VSS — 0.1 1 μA current All digital inputs, when Pullup, enabled (all I/O pins other R 11a C pulldown PU, — 17.5 36.5 52.5 kΩ than R resistors PD PTA5/IRQ/TCLK/RESET) Pullup, R PU, 11b C pulldown (PTA5/IRQ/TCLK/RESET) R — 17.5 36.5 52.5 kΩ PD resistors (Note2) MC9S08FL16 Series Data Sheet, Rev. 4 12 Freescale Semiconductor

Electrical Characteristics Table7. DC Characteristics (continued) Num C Characteristic Symbol Condition Min. Typical1 Max. Unit DC injection Single pin limit –0.2 — 0.2 mA 12 C current 3, 4, Total MCU limit, includes IIC VIN < VSS, VIN > VDD 5 –5 — 5 mA sum of allstressed pins 13 C Input capacitance, all pins C — — — 8 pF In 14 C RAM retention voltage V — — 0.6 1.0 V RAM 15 C POR re-arm voltage6 V — 0.9 1.4 2.0 V POR 16 D POR re-arm time t — 10 — — μs POR Low-voltage detection threshold — high range 17 P V 7 — V V falling LVD1 3.9 4.0 4.1 DD V rising 4.0 4.1 4.2 DD Low-voltage warning threshold — high range 1 C V — V V falling LVW3 4.5 4.6 4.7 DD V rising 4.6 4.7 4.8 DD 18 Low-voltage warning threshold — high range 0 P V 7 — V V falling LVW2 4.2 4.3 4.4 DD V rising 4.3 4.4 4.5 DD Low-voltage inhibit reset/recover 19 C V — — 100 — mV hysteresis hys 20 C Bandgap voltage reference8 V — — 1.21 — V BG 1 Typical values are measured at 25 °C. Characterized, not tested. 2 The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when measured externally on the pin. 3 All functional non-supply pins, except for PTA5 are internally clamped to V and V . SS DD 4 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 5 Power supply must maintain regulation within operating V range during instantaneous and operating maximum current DD conditions. If the positive injection current (V > V ) is greater than I , the injection current may flow out of V and could In DD DD DD result in external power supply going out of regulation. Ensure that external V load will shunt current greater than maximum DD injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 6 Maximum is highest voltage that POR is guaranteed. 7 When V is in between the minimun of this parameter and 4.5 V, the CPU, RAM, LVD and flash are full functional, but the DD performance of other modules may be reduced. 8 Factory trimmed at V = 5.0 V, Temp = 25 °C DD MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 13

Electrical Characteristics Typical I vs. V -V V = 5 V (High Drive) OH DD OH DD 50.000 45.000 40.000 35.000 -40C 30.000 0C A m 25.000 25C 55C 20.000 85C 15.000 10.000 5.000 0.000 0 0.3 0.5 0.8 1 1.3 2 V Figure6. Typical I Vs V –V (V = 5.0 V) (High Drive) OH DD OH DD MC9S08FL16 Series Data Sheet, Rev. 4 14 Freescale Semiconductor

Electrical Characteristics Typical I vs. V -V V = 5V (Low Drive) OH DD OH DD 10.000 9.000 8.000 7.000 -40C 6.000 0C A 5.000 25C m 55C 4.000 85C 3.000 2.000 1.000 0.000 0 0.3 0.5 0.8 1 1.3 2 V Figure7. Typical I Vs V –V (V = 5.0 V) (Low Drive) OH DD OH DD MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 15

Electrical Characteristics Typical I vs. V V = 5 V (High Drive) OL OL DD 50.000 45.000 40.000 35.000 -40C 30.000 0C A 25.000 25C m 55C 20.000 85C 15.000 10.000 5.000 0.000 0 0.3 0.5 0.8 1 1.3 2 V Figure8. Typical I Vs V (V = 5.0 V) (High Drive) OH OL DD MC9S08FL16 Series Data Sheet, Rev. 4 16 Freescale Semiconductor

Electrical Characteristics Typical I vs. V V = 5V (Low Drive) OL OL DD 14.000 12.000 10.000 -40C 8.000 0C A 25C m 6.000 55C 85C 4.000 2.000 0.000 0 0.3 0.5 0.8 1 1.3 2 V Figure9. Typical I Vs V (V = 5.0 V) (Low Drive) OH OL DD 5.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 17

Electrical Characteristics Table8. Supply Current Characteristics Num C Parameter Symbol Bus VDD Typical1 Max Unit Temp Freq (V) 5.66 –40 °C P 10 MHz 5.75 — 25 °C 5.80 85 °C Run supply current 1 RI 5 mA FEI mode, all modules off DD 1.61 –40 °C P 1 MHz 1.65 — 25 °C 1.78 85 °C 2.79 –40 °C C 10 MHz 2.86 — 25 °C 2.88 85 °C Wait mode supply current 2 WI 5 μA FEI mode, all modules off DD 1.05 –40 °C C 1 MHz 1.06 — 25 °C 1.06 85 °C C Stop2 mode supply current S2I — 5 1.06 — μA –40 to 85 °C DD 3 Stop3 mode supply current C S3I — 5 1.17 — μA –40 to 85 °C no clocks active DD 4 C ADC adder to stop3 — — 5 163.88 — μA 25 °C ICS adder to stop3 5 C — — 5 1.25 — μA 25 °C EREFSTEN = 1 6 C LVD adder to stop3 — — 5 161.3 — μA 25 °C 1 Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. MC9S08FL16 Series Data Sheet, Rev. 4 18 Freescale Semiconductor

Electrical Characteristics 5.8 External Oscillator (XOSC) and ICS Characteristics Refer to Figure 11 for crystal or resonator circuits. Table9. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient) Num C Characteristic Symbol Min Typical1 Max Unit Oscillator crystal or resonator (EREFS=1, ERCLKEN = 1) Low range (RANGE = 0) High range (RANGE = 1) FEE or FBE mode2 flo 32 — 38.4 kHz 1 C High range (RANGE = 1), high gain (HGO = 1), FBELP fhi 1 — 5 MHz mode fhi 1 — 16 MHz High range (RANGE = 1), low power (HGO = 0), FBELP f 1 — 8 MHz hi mode C 2 D Load capacitors 1 See Note3 C 2 Feedback resistor 3 D Low range (32 kHz to 38.4 kHz) RF 10 MΩ High range (1 MHz to 16 MHz) 1 MΩ Series resistor — Low range 4 D Low gain (HGO = 0) RS — 0 — kΩ High gain (HGO = 1) — 100 — Series resistor — High range Low Gain (HGO = 0) High Gain (HGO = 1) 5 D ≥ 8 MHz RS — 0 0 kΩ 4 MHz — 0 10 1 MHz — 0 20 Crystal startup time4, 5 Low range, low power — 200 — t 6 C Low range, high power CSTL — 400 — ms High range, low power — 5 — t High range, high power CSTH — 15 — 7 T Internal reference start-up time tIRST — 60 100 μs Square wave input clock frequency (EREFS=0, ERCLKEN = 1) 8 D FEE or FBE mode2 fextal 0.03125 — 5 MHz 0 — 20 MHz FBELP mode 9 P Average internal reference frequency — trimmed fint_t — 31.25 — kHz DCO output frequency range — trimmed6 10 P fdco_t 16 — 20 MHz Low range (DRS = 00) Total deviation of DCO output from trimmed frequency4 11 C Over full voltage and temperature range Δfdco_t — –1.0 to 0.5 ± 2 %fdco Over fixed voltage and temperature range of 0 to 70°C ±0.5 ± 1 12 C FLL acquisition time4,7 tAcquire 1 ms MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 19

Electrical Characteristics Table9. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient) (continued) Num C Characteristic Symbol Min Typical1 Max Unit Long term jitter of DCO output clock (averaged over 2 ms 13 C interval) 8 CJitter — 0.02 0.2 %fdco 1 Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. 2 When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25kHz to 39.0625 kHz. 3 See crystal or resonator manufacturer’s recommendation. 4 This parameter is characterized and not tested on each device. 5 Proper PC board layout procedures must be followed to achieve specifications. 6 The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 7 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . Bus Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via V and V and variation in crystal oscillator frequency increase the C percentage for DD SS Jitter a given interval. XOSC EXTAL XTAL R R S F Crystal or Resonator C 1 C 2 Figure10. Typical Crystal or Resonator Circuit MC9S08FL16 Series Data Sheet, Rev. 4 20 Freescale Semiconductor

Electrical Characteristics 1.00% 0.50% 0.00% -60 -40 -20 0 20 40 60 80 100 120 %) n ( o -0.50% ati vi TBD e D -1.00% -1.50% -2.00% Temperature Figure11. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V) 5.9 AC Characteristics This section describes timing characteristics for each peripheral system. MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 21

Electrical Characteristics 5.9.1 Control Timing Table10. Control Timing Num C Rating Symbol Min Typical1 Max Unit 1 D Bus frequency (tcyc = 1/fBus) fBus dc — 10 MHz 2 D Internal low power oscillator period tLPO 700 — 1300 μs 3 D External reset pulse width2 textrst 100 — — ns 4 D Reset low drive trstdrv 34 × tcyc — — ns BKGD/MS setup time after issuing background debug 5 D force reset to enter user or BDM modes tMSSU 500 — — ns BKGD/MS hold time after issuing background debug 6 D force reset to enter user or BDM modes3 tMSH 100 — — μs IRQ pulse width 7 D Asynchronous path2 t t 100 — — ns ILIH, IHIL Synchronous path4 1.5 × t — — cyc Keyboard interrupt pulse width 8 D Asynchronous path2 100 — — t t ns Synchronous path4 ILIH, IHIL 1.5 × t — — cyc Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) tRise, tFall — 16 — ns Slew rate control enabled (PTxSE = 1) — 23 — 9 C Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) tRise, tFall — 5 — ns Slew rate control enabled (PTxSE = 1) — 9 — 1 Typical values are based on characterization data at V = 5.0 V, 25 °C unless otherwise stated. DD 2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3 To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of t after V MSH DD rises above V . LVD 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5 Timing is shown with respect to 20% V and 80% V levels. Temperature range –40 °C to 85 °C. DD DD t extrst RESET PIN Figure12. Reset Timing MC9S08FL16 Series Data Sheet, Rev. 4 22 Freescale Semiconductor

Electrical Characteristics t IHIL KBIPx IRQ/KBIPx t ILIH Figure13. IRQ/KBIPx Timing 5.9.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table11. TPM Input Timing No. C Function Symbol Min Max Unit 1 D External clock frequency f 0 f /4 Hz TCLK Bus 2 D External clock period t 4 — t TCLK cyc 3 D External clock high time t 1.5 — t clkh cyc 4 D External clock low time t 1.5 — t clkl cyc 5 D Input capture pulse width t 1.5 — t ICPW cyc t TCLK t clkh TCLK t clkl Figure14. Timer External Clock t ICPW TPMCHn TPMCHn t ICPW Figure15. Timer Input Capture Pulse MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 23

Electrical Characteristics 5.10 ADC Characteristics Table12. 8-Bit ADC Operating Conditions Characteristic Conditions Symb Min Typical1 Max Unit Comment Absolute V 4.5 — 5.5 V DDA Supply voltage Delta to V (V – V )2 ΔV –100 0 100 mV DD DD DDA DDA Ground voltage Delta to V (V – V )2 ΔV –100 0 100 mV SS SS SSA SSA Input voltage — V V — V V ADIN REFL REFH Input — C — 4.5 5.5 pF capacitance ADIN Input resistance — R — 3 5 kΩ ADIN Analog source 8-bit mode (all valid f ) R — — 10 kΩ External to MCU resistance ADCK AS ADC conversion High speed (ADLPC = 0) 0.4 — 8.0 f MHz clock frequency Low power (ADLPC = 1) ADCK 0.4 — 4.0 1 Typical values assume V = 5.0 V, Temp = 25 °C, f = 1.0 MHz unless otherwise stated. Typical values are for reference DDA ADCK only and are not tested in production. 2 DC potential difference. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad ZAS leakage CHANNEL SELECT due to CIRCUIT ADC SAR R input R ENGINE AS protection ADIN + V ADIN – C V + AS AS – R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure16. ADC Input Impedance Equivalency Diagram MC9S08FL16 Series Data Sheet, Rev. 4 24 Freescale Semiconductor

Electrical Characteristics Table13. 8-Bit ADC Characteristics (V = V , V = V ) REFH DDA REFL SSA C Characteristic Conditions Symb Min Typ1 Max Unit Comment Supply Current ADLPC=1 T I — 133 — μA ADLSMP=1 DDA ADCO=1 Supply Current ADLPC=1 T I — 218 — μA ADLSMP=0 DDA ADCO=1 Supply Current ADLPC=0 T I — 327 — μA ADLSMP=1 DDA ADCO=1 Supply Current ADLPC=0 P I — 0.582 1 mA ADLSMP=0 DDA ADCO=1 C Supply Current Stop, Reset, Module Off I — 0.011 1 μA DDA ADC High Speed (ADLPC = 0) 2 3.3 5 t = P Asynchronous f MHz ADACK ADACK 1/f Clock Source Low Power (ADLPC = 1) 1.25 2 3.3 ADACK Conversion Short Sample (ADLSMP = 0) — 20 — ADCK P Time (Including tADC cycles See reference sample time) Long Sample (ADLSMP = 1) — 40 — manual for conversion Short Sample (ADLSMP = 0) — 3.5 — P Sample Time t ADCK time variances ADS cycles Long Sample (ADLSMP = 1) — 23.5 — –40°C– 25°C — 3.266 — Temp Sensor D m mV/°C Slope 25°C– 125°C — 3.638 — Temp Sensor D 25 °C V — 1.396 — mV Voltage TEMP25 Total Includes P Unadjusted 8-bit mode ETUE — ±0.5 ±1.0 LSB2 quantization Error Differential P 8-bit mode3 DNL — ±0.3 ±0.5 LSB2 Non-Linearity Integral T 8-bit mode INL — ±0.3 ±0.5 LSB2 Non-Linearity Zero-Scale P Error 8-bit mode EZS — ±0.5 ±0.5 LSB2 VADIN = VSSA Full-Scale V = V T Error 8-bit mode EFS — ±0.5 ±0.5 LSB2 ADIN DDA MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 25

Electrical Characteristics Table13. 8-Bit ADC Characteristics (V = V , V = V ) (continued) REFH DDA REFL SSA C Characteristic Conditions Symb Min Typ1 Max Unit Comment Quantization D Error 8-bit mode EQ — — ±0.5 LSB2 Input Leakage Pad leakage2 D Error 8-bit mode EIL — ±0.1 ±1 LSB2 * R AS 1 Typical values assume V = 5.0 V, Temp = 25 °C, f = 1.0 MHz unless otherwise stated. Typical values are for reference DDA ADCK only and are not tested in production. 2 Based on input pad leakage current. Refer to pad electricals. 5.11 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal V supply. DD For more detailed information about program/erase operations, see the Memory section. Table14. Flash Characteristics C Characteristic Symbol Min Typical Max Unit Supply voltage for program/erase D — –40 °C to 85 °C V 4.5 5.5 V prog/erase D Supply voltage for read operation V 4.5 — 5.5 V Read D Internal FCLK frequency1 f 150 — 200 kHz FCLK D Internal FCLK period (1/FCLK) t 5 — 6.67 μs Fcyc P Byte program time (random location)2 t 9 t prog Fcyc P Byte program time (burst mode)2 t 4 t Burst Fcyc P Page erase time2 t 4000 t Page Fcyc P Mass erase time2 t 20,000 t Mass Fcyc Byte program current3 RI — 4 — mA DDBP Page erase current3 RI — 6 — mA DDPE Program/erase endurance4 C T to T = –40 °C to 85 °C — 10,000 — cycles L H T = 25 °C C Data retention5 t 5 100 — years D_ret 1 The frequency of this clock is controlled by a software setting. 2 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures DD with V = 5.0 V, bus frequency = 4.0 MHz. DD 4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. MC9S08FL16 Series Data Sheet, Rev. 4 26 Freescale Semiconductor

Ordering Information 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 5.12 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 5.12.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (the North and East). The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table15. Radiated Emissions, Electric Field Level1 Parameter Symbol Conditions Frequency f /f Unit OSC BUS (Max) Radiated emissions, V V = 5.0 V 0.15 – 50 MHz 4 MHz crystal 9 dBμV RE_TEM DD electric field T = 25 οC 19 MHz bus A 50 – 150 MHz 5 package type 32-pin LQFP 150 – 500 MHz 2 500 – 1000 MHz 1 IEC Level N — SAE Level 1 — 1 Data based on qualification test results. 6 Ordering Information This section contains ordering information for MC9S08FL16 series devices. See below for an example of the device numbering system. Table16. Device Numbering System Memory Device Number1 Available Packages2 FLASH RAM MC9S08FL16 16 KB 1024 32 SDIP MC9S08FL8 8 KB 768 32 LQFP MC9S08FL16 Series Data Sheet, Rev. 4 Freescale Semiconductor 27

Package Information 1 See the reference manual, MC9S08FL16 Series Reference Manual, for a complete description of modules included on each device. 2 See Table17 for package information. Example of the device numbering system: MC9 S08 FL 16 C XX Status (MC = Fully Qualified) Package designator (see Table17) Temperature range Memory (C =–40 °C to 85 °C) (9 = Flash-based) Core Family Approximate flash size in KB 7 Package Information Table17. Package Descriptions Pin Count Package Type Abbreviation Designator Case No. Document No. 32 Low Quad Flat Package LQFP LC 873A-03 98ASH70029A 32 Shrink Dual In-line Package SDIP BM 1376-02 98ASA99330D 7.1 Mechanical Drawings The following pages are mechanical drawings for the packages described in Table 17. MC9S08FL16 Series Data Sheet, Rev. 4 28 Freescale Semiconductor

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