MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16 Data Sheet HCS08 Microcontrollers MC9S08DZ60 Rev. 4 6/2008 freescale.com

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MC9S08DZ60 Series Features 8-Bit HCS08 Central Processor Unit (CPU) Peripherals • 40-MHz HCS08 CPU (20-MHz bus) • ADC — 24-channel, 12-bit resolution, 2.5μs • HC08 instruction set with added BGND instruction conversion time, automatic compare function, temperature sensor, internal bandgap reference channel • Support for up to 32 interrupt/reset sources • ACMPx — Two analog comparators with selectable On-Chip Memory interruptonrising,falling,oreitheredgeofcomparator output; compare option to fixed internal bandgap • Flashread/program/eraseoverfulloperatingvoltageand reference voltage temperature • MSCAN—CANprotocol-Version2.0A,B;standard — MC9S08DZ60 = 60K and extended data frames; Support for remote frames; — MC9S08DZ48 = 48K FivereceivebufferswithFIFOstoragescheme;Flexible — MC9S08DZ32 = 32K identifieracceptancefiltersprogrammableas:2x32-bit, — MC9S08DZ16 = 16K 4 x 16-bit, or 8 x 8-bit • Up to 2K EEPROM in-circuit programmable memory; • SCIx — Two SCIs supporting LIN 2.0 Protocol and 8-byte single-page or 4-byte dual-page erase sector; SAE J2602 protocols; Full duplex non-return to zero Program and Erase while executingFlash; Erase abort (NRZ); Master extended break generation; Slave • Up to 4K random-access memory (RAM) extended break detection; Wakeup on active edge • SPI — Full-duplex or single-wire bidirectional; Power-Saving Modes Double-buffered transmit and receive; Master or Slave • Two very low power stop modes mode; MSB-first or LSB-first shifting • Reduced power wait mode • IIC — Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; • Very low power real time interrupt for use in run, wait, GeneralCallAddress;Interruptdrivenbyte-by-bytedata and stop transfer Clock Source Options • TPMx — One 6-channel (TPM1) and one 2-channel (TPM2); Selectable input capture, output compare, or • Oscillator (XOSC) — Loop-control Pierce oscillator; buffered edge-aligned PWM on each channel Crystal or ceramic resonator range of 31.25kHz to • RTC—(Real-timecounter)8-bitmoduluscounterwith 38.4kHz or 1 MHz to 16 MHz binary or decimal based prescaler; Real-time clock • Multi-purpose Clock Generator (MCG) — PLL and capabilities using external crystal and RTC for precise FLL modes (FLL capable of 1.5% deviation using time base, time-of-day, calendar or task scheduling internal temperature compensation);Internal reference functions; Free running on-chip low power oscillator clock with trim adjustment (trimmed at factory, with (1kHz)forcyclicwake-upwithoutexternalcomponents trim value stored in flash); External reference with oscillator/resonator options Input/Output System Protection • 53 general-purpose input/output (I/O) pins and 1 input-only pin • Watchdog computer operating properly (COP) reset • 24 interrupt pins with selectable polarity on each pin withoptiontorunfrombackupdedicated1-kHzinternal clock source or bus clock • Hysteresisandconfigurablepulldeviceonallinputpins. • Low-voltagedetectionwithresetorinterrupt;selectable • Configurable slew rate and drive strength on all output trip points pins. • Illegalopcode detection withreset Package Options • Illegaladdress detection withreset • 64-pinlow-profilequadflat-pack(LQFP)—10x10mm • Flash block protect • 48-pin low-profile quad flat-pack (LQFP) — 7x7 mm • Loss-of-lock protection • 32-pin low-profile quad flat-pack (LQFP) — 7x7 mm Development Support • Single-wire background debug interface • On-chip,in-circuitemulation(ICE)withreal-timebuscapture

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MC9S08DZ60 Data Sheet Covers MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16 MC9S08DZ60 Rev. 4 6/2008 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. ©Freescale Semiconductor, Inc., 2007-2008. All rights reserved.

Revision History Toprovidethemostup-to-dateinformation,therevisionofourdocumentsontheWorldWideWebwillbe the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Revision Description of Changes Number Date 1 6/2006 Advance Information for alpha samples customers 2 9/2007 ProductLaunch.Removedthe64-pinQFNpackage.Changedfromstandardtoextended mode for MSCAN registers in register summary. Corrected Block diagrams for SCI. UpdatedthelatestTempSensorinformation.MadeFTSTMODreserved.Updateddevice tousetheADC12-bitmodule.RevisedtheMCGmodule.UpdatedtheCPUInstructionSet table.UpdatedtheTPMblockmoduletoversion3.AddedtheTPMblockmoduleversion 2 as an appendix for devices using3M05C (or earlier)mask sets. Heavily revised the Electricals appendix. 3 10/2007 Removed two tables that were inadvertently included in the MC9S08DZ60 version of the book. 4 6/2008 Sustainingupdate.IncorporatedPSIssues#2765,3177,3236,3292,3311,3312,3326, 3335, 3345, 3382, 2795, 3382 and 3386 PLL Jitter Spec update. Also, added internal referenceclocktrimadjustmentstatementtoFeaturespage.UpdatedtheTPMmoduleto thelatestversion.AdjustedvaluesinTableA-13ControlTimingrow2andinTableA-6DC Characteristics row 24 so that it references 5.0 V instead of 3.0 V. ©Freescale Semiconductor, Inc., 2007-2008. All rights reserved. ® This product incorporates SuperFlash Technology licensed from SST. MC9S08DZ60 Series Data Sheet, Rev. 4 6 Freescale Semiconductor

List of Chapters Chapter Title Page Chapter 1 Device Overview..............................................................................21 Chapter 2 Pins and Connections.....................................................................27 Chapter 3 Modes of Operation.........................................................................35 Chapter 4 Memory.............................................................................................41 Chapter 5 Resets, Interrupts, and General System Control..........................69 Chapter 6 Parallel Input/Output Control..........................................................85 Chapter 7 Central Processor Unit (S08CPUV3)............................................115 Chapter 8 Multi-Purpose Clock Generator (S08MCGV1).............................135 Chapter 9 Analog Comparator (S08ACMPV3)..............................................167 Chapter 10 Analog-to-Digital Converter (S08ADC12V1)................................173 Chapter 11 Inter-Integrated Circuit (S08IICV2)...............................................199 Chapter 12 Freescale Controller Area Network (S08MSCANV1)..................219 Chapter 13 Serial Peripheral Interface (S08SPIV3)........................................273 Chapter 14 Serial Communications Interface (S08SCIV4).............................289 Chapter 15 Real-Time Counter (S08RTCV1)...................................................309 Chapter 16 Timer Pulse-Width Modulator (S08TPMV3).................................319 Chapter 17 Development Support...................................................................347 Appendix A Electrical Characteristics..............................................................369 Appendix B Timer Pulse-Width Modulator (TPMV2).......................................391 Appendix C Ordering Information and Mechanical Drawings........................405 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 7

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Contents Section Number Title Page Chapter 1 Device Overview 1.1 Devices in the MC9S08DZ60 Series................................................................................................21 1.2 MCU Block Diagram.......................................................................................................................22 1.3 System Clock Distribution...............................................................................................................24 Chapter 2 Pins and Connections 2.1 Device Pin Assignment....................................................................................................................27 2.2 Recommended System Connections................................................................................................30 2.2.1 Power ................................................................................................................................31 2.2.2 Oscillator ...........................................................................................................................31 2.2.3 RESET ..............................................................................................................................31 2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................32 2.2.5 ADC Reference Pins (V , V ) ..............................................................................32 REFH REFL 2.2.6 General-Purpose I/O and Peripheral Ports ........................................................................32 Chapter 3 Modes of Operation 3.1 Introduction......................................................................................................................................35 3.2 Features............................................................................................................................................35 3.3 Run Mode.........................................................................................................................................35 3.4 Active Background Mode.................................................................................................................35 3.5 Wait Mode........................................................................................................................................36 3.6 Stop Modes.......................................................................................................................................37 3.6.1 Stop3 Mode .......................................................................................................................37 3.6.2 Stop2 Mode .......................................................................................................................38 3.6.3 On-Chip Peripheral Modules in Stop Modes ....................................................................39 Chapter 4 Memory 4.1 MC9S08DZ60 Series Memory Map................................................................................................41 4.2 Reset and Interrupt Vector Assignments..........................................................................................42 4.3 Register Addresses and Bit Assignments.........................................................................................44 4.4 RAM.................................................................................................................................................52 4.5 Flash and EEPROM.........................................................................................................................52 4.5.1 Features .............................................................................................................................52 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 9

Section Number Title Page 4.5.2 Program and Erase Times .................................................................................................53 4.5.3 Program and Erase Command Execution .........................................................................53 4.5.4 Burst Program Execution ..................................................................................................55 4.5.5 Sector Erase Abort ............................................................................................................57 4.5.6 Access Errors ....................................................................................................................58 4.5.7 Block Protection................................................................................................................59 4.5.8 Vector Redirection ............................................................................................................59 4.5.9 Security .............................................................................................................................59 4.5.10 EEPROM Mapping ...........................................................................................................61 4.5.11 Flash and EEPROM Registers and Control Bits ...............................................................61 Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction......................................................................................................................................69 5.2 Features............................................................................................................................................69 5.3 MCU Reset.......................................................................................................................................69 5.4 Computer Operating Properly (COP) Watchdog..............................................................................70 5.5 Interrupts..........................................................................................................................................71 5.5.1 Interrupt Stack Frame .......................................................................................................72 5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................72 5.5.3 Interrupt Vectors, Sources, and Local Masks ....................................................................73 5.6 Low-Voltage Detect (LVD) System.................................................................................................75 5.6.1 Power-On Reset Operation ...............................................................................................75 5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................75 5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................75 5.7 MCLK Output..................................................................................................................................75 5.8 Reset, Interrupt, and System Control Registers and Control Bits....................................................76 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................77 5.8.2 System Reset Status Register (SRS) .................................................................................78 5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................79 5.8.4 System Options Register 1 (SOPT1) ................................................................................80 5.8.5 System Options Register 2 (SOPT2) ................................................................................81 5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................82 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................83 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................84 Chapter 6 Parallel Input/Output Control 6.1 Port Data and Data Direction...........................................................................................................85 6.2 Pull-up, Slew Rate, and Drive Strength............................................................................................86 6.3 Pin Interrupts....................................................................................................................................87 6.3.1 Edge Only Sensitivity .......................................................................................................87 MC9S08DZ60 Series Data Sheet, Rev. 4 10 Freescale Semiconductor

Section Number Title Page 6.3.2 Edge and Level Sensitivity ................................................................................................88 6.3.3 Pull-up/Pull-down Resistors .............................................................................................88 6.3.4 Pin Interrupt Initialization .................................................................................................88 6.4 Pin Behavior in Stop Modes.............................................................................................................88 6.5 Parallel I/O and Pin Control Registers.............................................................................................89 6.5.1 Port A Registers ................................................................................................................90 6.5.2 Port B Registers ................................................................................................................94 6.5.3 Port C Registers ................................................................................................................98 6.5.4 Port D Registers ..............................................................................................................101 6.5.5 Port E Registers ...............................................................................................................105 6.5.6 Port F Registers ...............................................................................................................108 6.5.7 Port G Registers ..............................................................................................................111 Chapter 7 Central Processor Unit (S08CPUV3) 7.1 Introduction....................................................................................................................................115 7.1.1 Features ...........................................................................................................................115 7.2 Programmer’s Model and CPU Registers......................................................................................116 7.2.1 Accumulator (A) .............................................................................................................116 7.2.2 Index Register (H:X) .......................................................................................................116 7.2.3 Stack Pointer (SP) ...........................................................................................................117 7.2.4 Program Counter (PC) ....................................................................................................117 7.2.5 Condition Code Register (CCR) .....................................................................................117 7.3 Addressing Modes..........................................................................................................................119 7.3.1 Inherent Addressing Mode (INH) ...................................................................................119 7.3.2 Relative Addressing Mode (REL) ...................................................................................119 7.3.3 Immediate Addressing Mode (IMM) ..............................................................................119 7.3.4 Direct Addressing Mode (DIR) ......................................................................................119 7.3.5 Extended Addressing Mode (EXT) ................................................................................120 7.3.6 Indexed Addressing Mode ..............................................................................................120 7.4 Special Operations..........................................................................................................................121 7.4.1 Reset Sequence ...............................................................................................................121 7.4.2 Interrupt Sequence ..........................................................................................................121 7.4.3 Wait Mode Operation ......................................................................................................122 7.4.4 Stop Mode Operation ......................................................................................................122 7.4.5 BGND Instruction ...........................................................................................................123 7.5 HCS08 Instruction Set Summary...................................................................................................124 Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.1 Introduction....................................................................................................................................135 8.1.1 Features ...........................................................................................................................137 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 11

Section Number Title Page 8.1.2 Modes of Operation ........................................................................................................139 8.2 External Signal Description...........................................................................................................139 8.3 Register Definition.........................................................................................................................140 8.3.1 MCG Control Register 1 (MCGC1) ...............................................................................140 8.3.2 MCG Control Register 2 (MCGC2) ...............................................................................141 8.3.3 MCG Trim Register (MCGTRM) ...................................................................................142 8.3.4 MCG Status and Control Register (MCGSC) .................................................................143 8.3.5 MCG Control Register 3 (MCGC3) ...............................................................................144 8.4 Functional Description...................................................................................................................146 8.4.1 Operational Modes ..........................................................................................................146 8.4.2 Mode Switching ..............................................................................................................150 8.4.3 Bus Frequency Divider ...................................................................................................151 8.4.4 Low Power Bit Usage .....................................................................................................151 8.4.5 Internal Reference Clock ................................................................................................151 8.4.6 External Reference Clock ...............................................................................................151 8.4.7 Fixed Frequency Clock ...................................................................................................152 8.5 Initialization / Application Information.........................................................................................152 8.5.1 MCG Module Initialization Sequence ............................................................................152 8.5.2 MCG Mode Switching ....................................................................................................153 8.5.3 Calibrating the Internal Reference Clock (IRC) .............................................................164 Chapter 9 Analog Comparator (S08ACMPV3) 9.1 Introduction....................................................................................................................................167 9.1.1 ACMP Configuration Information ..................................................................................167 9.1.2 Features ...........................................................................................................................169 9.1.3 Modes of Operation ........................................................................................................169 9.1.4 Block Diagram ................................................................................................................170 9.2 External Signal Description...........................................................................................................170 9.3 Memory Map/Register Definition..................................................................................................171 9.3.1 ACMPx Status and Control Register (ACMPxSC) .........................................................171 9.4 Functional Description...................................................................................................................172 Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.1 Introduction....................................................................................................................................173 10.1.1 Analog Power and Ground Signal Names ......................................................................173 10.1.2 Channel Assignments......................................................................................................173 10.1.3 Alternate Clock ...............................................................................................................174 10.1.4 Hardware Trigger ............................................................................................................174 10.1.5 Temperature Sensor ........................................................................................................175 10.1.6 Features ...........................................................................................................................177 MC9S08DZ60 Series Data Sheet, Rev. 4 12 Freescale Semiconductor

Section Number Title Page 10.1.7 ADC Module Block Diagram .........................................................................................177 10.2 External Signal Description...........................................................................................................178 10.2.1 Analog Power (V ) ..................................................................................................179 DDAD 10.2.2 Analog Ground (V ) .................................................................................................179 SSAD 10.2.3 Voltage Reference High (V ) ...................................................................................179 REFH 10.2.4 Voltage Reference Low (V ) .....................................................................................179 REFL 10.2.5 Analog Channel Inputs (ADx) ........................................................................................179 10.3 Register Definition.........................................................................................................................179 10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................179 10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................181 10.3.3 Data Result High Register (ADCRH) .............................................................................181 10.3.4 Data Result Low Register (ADCRL) ..............................................................................182 10.3.5 Compare Value High Register (ADCCVH) ....................................................................182 10.3.6 Compare Value Low Register (ADCCVL) .....................................................................183 10.3.7 Configuration Register (ADCCFG) ................................................................................183 10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................184 10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................185 10.3.10Pin Control 3 Register (APCTL3) ..................................................................................186 10.4 Functional Description...................................................................................................................187 10.4.1 Clock Select and Divide Control ....................................................................................188 10.4.2 Input Select and Pin Control ...........................................................................................188 10.4.3 Hardware Trigger ............................................................................................................188 10.4.4 Conversion Control .........................................................................................................188 10.4.5 Automatic Compare Function .........................................................................................191 10.4.6 MCU Wait Mode Operation ............................................................................................191 10.4.7 MCU Stop3 Mode Operation ..........................................................................................192 10.4.8 MCU Stop2 Mode Operation ..........................................................................................192 10.5 Initialization Information...............................................................................................................193 10.5.1 ADC Module Initialization Example .............................................................................193 10.6 Application Information.................................................................................................................195 10.6.1 External Pins and Routing ..............................................................................................195 10.6.2 Sources of Error ..............................................................................................................196 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction....................................................................................................................................199 11.1.1 Features ...........................................................................................................................201 11.1.2 Modes of Operation ........................................................................................................201 11.1.3 Block Diagram ................................................................................................................202 11.2 External Signal Description...........................................................................................................202 11.2.1 SCL — Serial Clock Line ...............................................................................................202 11.2.2 SDA — Serial Data Line ................................................................................................202 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 13

Section Number Title Page 11.3 Register Definition.........................................................................................................................202 11.3.1 IIC Address Register (IICA) ...........................................................................................203 11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................203 11.3.3 IIC Control Register (IICC1) ..........................................................................................206 11.3.4 IIC Status Register (IICS) ...............................................................................................207 11.3.5 IIC Data I/O Register (IICD) ..........................................................................................208 11.3.6 IIC Control Register 2 (IICC2) .......................................................................................208 11.4 Functional Description...................................................................................................................209 11.4.1 IIC Protocol .....................................................................................................................209 11.4.2 10-bit Address .................................................................................................................213 11.4.3 General Call Address ......................................................................................................214 11.5 Resets.............................................................................................................................................214 11.6 Interrupts........................................................................................................................................214 11.6.1 Byte Transfer Interrupt ....................................................................................................214 11.6.2 Address Detect Interrupt .................................................................................................214 11.6.3 Arbitration Lost Interrupt ................................................................................................214 11.7 Initialization/Application Information...........................................................................................216 Chapter 12 Freescale Controller Area Network (S08MSCANV1) 12.1 Introduction....................................................................................................................................219 12.1.1 Features ...........................................................................................................................221 12.1.2 Modes of Operation ........................................................................................................221 12.1.3 Block Diagram ................................................................................................................222 12.2 External Signal Description...........................................................................................................222 12.2.1 RXCAN — CAN Receiver Input Pin .............................................................................222 12.2.2 TXCAN — CAN Transmitter Output Pin .....................................................................222 12.2.3 CAN System ...................................................................................................................222 12.3 Register Definition.........................................................................................................................223 12.3.1 MSCAN Control Register 0 (CANCTL0) ......................................................................223 12.3.2 MSCAN Control Register 1 (CANCTL1) ......................................................................226 12.3.3 MSCAN Bus Timing Register 0 (CANBTR0) ...............................................................227 12.3.4 MSCAN Bus Timing Register 1 (CANBTR1) ...............................................................228 12.3.5 MSCAN Receiver Interrupt Enable Register (CANRIER) .............................................231 12.3.6 MSCAN Transmitter Flag Register (CANTFLG) ..........................................................232 12.3.7 MSCAN Transmitter Interrupt Enable Register (CANTIER) ........................................233 12.3.8 MSCAN Transmitter Message Abort Request Register (CANTARQ) ...........................234 12.3.9 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) .................235 12.3.10MSCAN Transmit Buffer Selection Register (CANTBSEL) .........................................235 12.3.11MSCAN Identifier Acceptance Control Register (CANIDAC) ......................................236 12.3.12MSCAN Miscellaneous Register (CANMISC) ..............................................................237 12.3.13MSCAN Receive Error Counter (CANRXERR) ............................................................238 MC9S08DZ60 Series Data Sheet, Rev. 4 14 Freescale Semiconductor

Section Number Title Page 12.3.14MSCAN Transmit Error Counter (CANTXERR) ..........................................................239 12.3.15MSCAN Identifier Acceptance Registers (CANIDAR0-7) ............................................239 12.3.16MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) .................................240 12.4 Programmer’s Model of Message Storage.....................................................................................241 12.4.1 Identifier Registers (IDR0–IDR3) ...................................................................................244 12.4.2 IDR0–IDR3 for Standard Identifier Mapping .................................................................246 12.4.3 Data Segment Registers (DSR0-7) .................................................................................247 12.4.4 Data Length Register (DLR) ...........................................................................................248 12.4.5 Transmit Buffer Priority Register (TBPR) ......................................................................249 12.4.6 Time Stamp Register (TSRH–TSRL) .............................................................................249 12.5 Functional Description...................................................................................................................250 12.5.1 General ............................................................................................................................250 12.5.2 Message Storage .............................................................................................................251 12.5.3 Identifier Acceptance Filter .............................................................................................254 12.5.4 Modes of Operation ........................................................................................................261 12.5.5 Low-Power Options ........................................................................................................262 12.5.6 Reset Initialization ..........................................................................................................268 12.5.7 Interrupts .........................................................................................................................268 12.6 Initialization/Application Information...........................................................................................270 12.6.1 MSCAN initialization .....................................................................................................270 12.6.2 Bus-Off Recovery ...........................................................................................................271 Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1 Introduction....................................................................................................................................273 13.1.1 Features ...........................................................................................................................275 13.1.2 Block Diagrams ..............................................................................................................275 13.1.3 SPI Baud Rate Generation ..............................................................................................277 13.2 External Signal Description...........................................................................................................278 13.2.1 SPSCK — SPI Serial Clock ............................................................................................278 13.2.2 MOSI — Master Data Out, Slave Data In ......................................................................278 13.2.3 MISO — Master Data In, Slave Data Out ......................................................................278 13.2.4 SS — Slave Select ...........................................................................................................278 13.3 Modes of Operation........................................................................................................................279 13.3.1 SPI in Stop Modes ..........................................................................................................279 13.4 Register Definition.........................................................................................................................279 13.4.1 SPI Control Register 1 (SPIC1) ......................................................................................279 13.4.2 SPI Control Register 2 (SPIC2) ......................................................................................280 13.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................281 13.4.4 SPI Status Register (SPIS) ..............................................................................................282 13.4.5 SPI Data Register (SPID) ................................................................................................283 13.5 Functional Description...................................................................................................................284 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 15

Section Number Title Page 13.5.1 SPI Clock Formats ..........................................................................................................284 13.5.2 SPI Interrupts ..................................................................................................................287 13.5.3 Mode Fault Detection .....................................................................................................287 Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction....................................................................................................................................289 14.1.1 SCI2 Configuration Information .....................................................................................289 14.1.2 Features ...........................................................................................................................291 14.1.3 Modes of Operation ........................................................................................................291 14.1.4 Block Diagram ................................................................................................................292 14.2 Register Definition.........................................................................................................................294 14.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................294 14.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................295 14.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................296 14.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................297 14.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................299 14.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................300 14.2.7 SCI Data Register (SCIxD) .............................................................................................301 14.3 Functional Description...................................................................................................................301 14.3.1 Baud Rate Generation .....................................................................................................301 14.3.2 Transmitter Functional Description ................................................................................302 14.3.3 Receiver Functional Description .....................................................................................303 14.3.4 Interrupts and Status Flags ..............................................................................................305 14.3.5 Additional SCI Functions ...............................................................................................306 Chapter 15 Real-Time Counter (S08RTCV1) 15.1 Introduction....................................................................................................................................309 15.1.1 RTC Clock Signal Names ...............................................................................................309 15.1.2 Features ...........................................................................................................................311 15.1.3 Modes of Operation ........................................................................................................311 15.1.4 Block Diagram ................................................................................................................312 15.2 External Signal Description...........................................................................................................312 15.3 Register Definition.........................................................................................................................312 15.3.1 RTC Status and Control Register (RTCSC) ....................................................................313 15.3.2 RTC Counter Register (RTCCNT) ..................................................................................314 15.3.3 RTC Modulo Register (RTCMOD) ................................................................................314 15.4 Functional Description...................................................................................................................314 15.4.1 RTC Operation Example .................................................................................................315 15.5 Initialization/Application Information...........................................................................................316 MC9S08DZ60 Series Data Sheet, Rev. 4 16 Freescale Semiconductor

Section Number Title Page Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) 16.1 Introduction....................................................................................................................................319 16.1.1 Features ...........................................................................................................................321 16.1.2 Modes of Operation ........................................................................................................321 16.1.3 Block Diagram ................................................................................................................322 16.2 Signal Description..........................................................................................................................324 16.2.1 Detailed Signal Descriptions...........................................................................................324 16.3 Register Definition.........................................................................................................................328 16.3.1 TPM Status and Control Register (TPMxSC) ................................................................328 16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................329 16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................330 16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................331 16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................333 16.4 Functional Description...................................................................................................................334 16.4.1 Counter ............................................................................................................................335 16.4.2 Channel Mode Selection .................................................................................................337 16.5 Reset Overview..............................................................................................................................340 16.5.1 General ............................................................................................................................340 16.5.2 Description of Reset Operation .......................................................................................340 16.6 Interrupts........................................................................................................................................340 16.6.1 General ............................................................................................................................340 16.6.2 Description of Interrupt Operation ..................................................................................341 16.7 The Differences from TPM v2 to TPM v3.....................................................................................342 Chapter 17 Development Support 17.1 Introduction....................................................................................................................................347 17.1.1 Forcing Active Background ............................................................................................347 17.1.2 Features ...........................................................................................................................348 17.2 Background Debug Controller (BDC)...........................................................................................348 17.2.1 BKGD Pin Description ...................................................................................................349 17.2.2 Communication Details ..................................................................................................350 17.2.3 BDC Commands .............................................................................................................354 17.2.4 BDC Hardware Breakpoint .............................................................................................356 17.3 On-Chip Debug System (DBG).....................................................................................................357 17.3.1 Comparators A and B......................................................................................................357 17.3.2 Bus Capture Information and FIFO Operation ...............................................................357 17.3.3 Change-of-Flow Information ..........................................................................................358 17.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................358 17.3.5 Trigger Modes .................................................................................................................359 17.3.6 Hardware Breakpoints ....................................................................................................361 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 17

Section Number Title Page 17.4 Register Definition.........................................................................................................................361 17.4.1 BDC Registers and Control Bits .....................................................................................361 17.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................363 17.4.3 DBG Registers and Control Bits .....................................................................................364 Appendix A Electrical Characteristics A.1 Introduction ...................................................................................................................................369 A.2 Parameter Classification ................................................................................................................369 A.3 Absolute Maximum Ratings ..........................................................................................................369 A.4 Thermal Characteristics .................................................................................................................370 A.5 ESD Protection and Latch-Up Immunity ......................................................................................372 A.6 DC Characteristics .........................................................................................................................373 A.7 Supply Current Characteristics ......................................................................................................375 A.8 Analog Comparator (ACMP) Electricals ......................................................................................376 A.9 ADC Characteristics ......................................................................................................................376 A.10 External Oscillator (XOSC) Characteristics .................................................................................380 A.11 MCG Specifications ......................................................................................................................381 A.12 AC Characteristics .........................................................................................................................383 A.12.1 Control Timing ...............................................................................................................383 A.12.2 Timer/PWM ....................................................................................................................384 A.12.3 MSCAN ..........................................................................................................................385 A.12.4 SPI ...................................................................................................................................386 A.13 Flash and EEPROM ......................................................................................................................389 A.14 EMC Performance .........................................................................................................................390 A.14.1 Radiated Emissions .........................................................................................................390 Appendix B Timer Pulse-Width Modulator (TPMV2) B.0.1 Features ...........................................................................................................................391 B.0.2 Block Diagram ................................................................................................................391 B.1 External Signal Description...........................................................................................................393 B.1.1 External TPM Clock Sources..........................................................................................393 B.1.2 TPMxCHn — TPMx Channel n I/O Pins .......................................................................393 B.2 Register Definition.........................................................................................................................393 B.2.1 Timer Status and Control Register (TPMxSC) ...............................................................394 B.2.2 Timer Counter Registers (TPMxCNTH:TPMxCNTL) ...................................................395 B.2.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL) ..................................396 B.2.4 Timer Channel n Status and Control Register (TPMxCnSC) .........................................397 B.2.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL) .........................................398 B.3 Functional Description...................................................................................................................399 B.3.1 Counter ............................................................................................................................399 MC9S08DZ60 Series Data Sheet, Rev. 4 18 Freescale Semiconductor

Section Number Title Page B.3.2 Channel Mode Selection .................................................................................................400 B.3.3 Center-Aligned PWM Mode ...........................................................................................402 B.4 TPM Interrupts...............................................................................................................................403 B.4.1 Clearing Timer Interrupt Flags .......................................................................................403 B.4.2 Timer Overflow Interrupt Description ............................................................................403 B.4.3 Channel Event Interrupt Description ..............................................................................404 B.4.4 PWM End-of-Duty-Cycle Events ...................................................................................404 Appendix C Ordering Information and Mechanical Drawings C.1 Ordering Information ....................................................................................................................405 C.1.1 MC9S08DZ60 Series Devices ........................................................................................405 C.2 Mechanical Drawings ....................................................................................................................405 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 19

None

Chapter 1 Device Overview MC9S08DZ60SeriesdevicesprovidesignificantvaluetocustomerslookingtocombineControllerArea Network(CAN)andembeddedEEPROMintheirapplications.Thiscombinationwillprovidelowercosts, enhanced performance, and higher quality. 1.1 Devices in the MC9S08DZ60 Series This data sheet covers members of the MC9S08DZ60 Series of MCUs: • MC9S08DZ60 • MC9S08DZ48 • MC9S08DZ32 • MC9S08DZ16 Table1-1 summarizes the feature set available in the MC9S08DZ60 Series. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 21

Chapter1 Device Overview t Table1-1. MC9S08DZ60 Series Features by MCU and Pin Count Feature MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16 Flash size 60032 49152 33792 16896 (bytes) RAMsize(bytes) 4096 3072 2048 1024 EEPROM size 2048 1536 1024 512 (bytes) Pin quantity 64 48 32 64 48 32 64 48 32 48 32 ACMP1 yes ACMP2 yes yes1 no yes yes1 no yes yes1 no yes1 no ADC channels 24 16 10 24 16 10 24 16 10 16 10 DBG yes IIC yes IRQ yes MCG yes MSCAN yes RTC yes SCI1 yes SCI2 yes SPI yes TPM1 channels 6 6 4 6 6 4 6 6 4 6 4 TPM2 channels 2 XOSC yes COP Watchdog yes 1 ACMP2O is not available. 1.2 MCU Block Diagram Figure1-1 is the MC9S08DZ60 Series system-level block diagram. MC9S08DZ60 Series Data Sheet, Rev. 4 22 Freescale Semiconductor

Chapter1 Device Overview HCS08 CORE PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 CPU ANALOG COMPARATOR ACMP1O ORT A PPTTAA34//PPIIAA34//AADDPP34/ACMP1O BKGD/MS (ACMP1) ACMP1- P PTA2/PIA2/ADP2/ACMP1- BDC BKP ACMP1+ PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK HCS08 SYSTEM CONTROL PTB7/PIB7/ADP15 RESET RESETS AND INTERRUPTS PTB6/PIB6/ADP14 MODES OF OPERATION PTB5/PIB5/ADP13 POWER MANAGEMENT T B PTB4/PIB4/ADP12 OR PTB3/PIB3/ADP11 8 P PTB2/PIB2/ADP10 COP LVD Q PTB1/PIB1/ADP9 R INT IRQ I ADP7-ADP0 PTB0/PIB0/ADP8 24-CHANNEL,12-BIT PTC7/ADP23 ADP15-ADP8 ANALOG-TO-DIGITAL PTC6/ADP22 VREFH CONVERTER (ADC) ADP23-ADP16 PTC5/ADP21 V VREFL T C PTC4/ADP20 DDA OR PTC3/ADP19 VSSA P PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 USERFlash TPM1CH5 - PTD7/PID7/TPM1CH5 MC9S08DZ60 = 60K 6-CHANNEL TIMER/PWM TPM1CH0 6 MC9S08DZ48 = 48K MODULE (TPM1) TPM1CLK PTD6/PID6/TPM1CH4 MC9S08DZ32 = 32K PTD5/PID5/TPM1CH3 MC9S08DZ16 = 16K T D PTD4/PID4/TPM1CH2 TPM2CH1, OR PTD3/PID3/TPM1CH1 2-CHANNEL TIMER/PWM TPM2CH0 P PTD2/PID2/TPM1CH0 MODULE (TPM2) TPM2CLK PTD1/PID1/TPM2CH1 USER EEPROM PTD0/PID0/TPM2CH0 MC9S08DZ60 = 2K CONTROLLER AREA RxCAN PTE7/RxD2/RXCAN NETWORK (MSCAN) TXCAN PTE6/TxD2/TXCAN MISO PTE5/SDA/MISO MC9USS0E8RD ZR6A0M = 4K INTSEERRFIAALC EP EMROIPDHUELREA (SLPI) SMPOSSCIK ORT E PPTTEE34//SSPCSL/CMKOSI SS P PTE2/SS RxD1 PTE1/RxD1 DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1 PTE0/TxD1 INTERFACE (SCI1) PTF7 ACMP2O ANALOG COMPARATOR PTF6/ACMP2O REAL-TIME COUNTER (RTC) (ACMP2) ACMP2- PTF5/ACMP2- ACMP2+ VVDDDD VOLTAGE IIC MODULE (IIC) SSCDLA PORT F PPPTTTFFF342///TATPPCMMM21PCC2LL+KK//SSDCAL RxD2 VSS REGULATOR PTF1/RxD2 V SERIAL COMMUNICATIONS TxD2 SS PTF0/TxD2 INTERFACE (SCI2) PTG5 MULTI-PURPOSE PTG4 CLOCK GENERATOR G PTG3 (MCG) T R PTG2 XTAL PO PTG1/XTAL OSCILLATOR (XOSC) EXTAL PTG0/EXTAL - V /V internally connected to V /V in 48-pin and 32-pin packages - Pin not connected in 48-pin and 32-pin packages REFH REFL DDA SSA - V and V pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package DD SS Figure1-1. MC9S08DZ60 Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 23

Chapter1 Device Overview Table1-2 provides the functional version of the on-chip modules. Table1-2. Module Versions Module Version Central Processor Unit (CPU) 3 Multi-Purpose Clock Generator (MCG) 1 Analog Comparator (ACMP) 3 Analog-to-Digital Converter (ADC) 1 Inter-Integrated Circuit (IIC) 2 Freescale’s CAN (MSCAN) 1 Serial Peripheral Interface (SPI) 3 Serial Communications Interface (SCI) 4 Real-Time Counter (RTC) 1 Timer Pulse Width Modulator (TPM) 31 Debug Module (DBG) 2 1 3M05C and older masks have TPM version 2. 1.3 System Clock Distribution Figure1-2showsasimplifiedclockconnectiondiagram.SomemodulesintheMCUhaveselectableclock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. The following are the clocks used in this MCU: • BUSCLK — The frequency of the bus is always half of MCGOUT. • LPO—Independent1-kHzclockthatcanbeselectedasthesourcefortheCOPandRTCmodules. • MCGOUT — Primary output of the MCG and is twice the bus frequency. • MCGLCLK—DevelopmenttoolscanselectthisclocksourcetospeedupBDCcommunications in systems where BUSCLK is configured to run at a very slow frequency. • MCGERCLK—ExternalreferenceclockcanbeselectedastheRTCclocksource.Itcanalsobe used as the alternate clock for the ADC and MSCAN. • MCGIRCLK — Internal reference clock can be selected as the RTC clock source. • MCGFFCLK — Fixed frequency clock can be selected as clock source for the TPM1 and TPM2. • TPM1CLK — External input clock source for TPM1. • TPM2CLK — External input clock source for TPM2. MC9S08DZ60 Series Data Sheet, Rev. 4 24 Freescale Semiconductor

Chapter1 Device Overview TPM1CLK TPM2CLK 1 kHZ RTC COP TPM1 TPM2 IIC SCI1 SCI2 SPI LPO MCGERCLK MCGIRCLK MCGFFCLKVALID MCG MCGFFCLK ÷2 1 FFCLK* 0 MCGOUT ÷ BUSCLK 2 MCGLCLK XOSC CPU BDC ADC MSCAN FLASH EEPROM ADC has min and Flash and EXTAL XTAL max frequency EEPROM have requirements.See frequency * The fixed frequency clock (FFCLK) is internally theADCchapterand requirements for synchronizedtothebusclockandmustnotexceedonehalf electricals appendix program and of the bus clock frequency. for details. erase operation. See the electricals appendix for details. Figure1-2. MC9S08DZ60 System Clock Distribution Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 25

Chapter1 Device Overview MC9S08DZ60 Series Data Sheet, Rev. 4 26 Freescale Semiconductor

Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 Device Pin Assignment This section shows the pin assignments for MC9S08DZ60 Series MCUs in the available packages. 1O 1- 1+ P P P M M M C C C P6P13 P5 P12 P4 P3/AP11 P2/AP10 P1/A DD D D D DD DD D A6/AB5/A A5/ADP20B4/A A4/A A3/AB3/ADP19 A2/AB2/A A1/A PIPI PIAPI PI PIPIA PIPI PI TA6/TB5/ TA5/TC4/TB4/ TA4/ DDA REFH REFL SSATA3/TB3/TC3/ TA2/TB2/ TA1/ PP PPP PVVVVPPP PP P 4321098765432109 PTB6/PIB6/ADP14 1666665555555555448 PTB1/PIB1/ADP9 PTC5/ADP21 2 47 PTC2/ADP18 PTA7/PIA7/ADP7/IRQ 3 46 PTA0/PIA0/ADP0/MCLK PTC6/ADP22 4 45 PTC1/ADP17 PTB7/PIB7/ADP15 5 44 PTB0/PIB0/ADP8 PTC7/ADP23 6 43 PTC0/ADP16 V 7 42 BKGD/MS DD V 8 64-Pin 41 PTD7/PID7/TPM1CH5 SS PTG0/EXTAL 9 LQFP 40 PTD6/PID6/TPM1CH4 PTG1/XTAL 10 39 VDD RESET 11 38 VSS PTF4/ACMP2+ 12 37 PTF7 PTF5/ACMP2- 13 36 PTD5/PID5/TPM1CH3 PTF6/ACMP2O 14 35 PTD4/PID4/TPM1CH2 PTE0/TxD1 15 34 PTD3/PID3/TPM1CH1 PTE1/RxD1 16 33 PTD2/PID2/TPM1CH0 7890123456789012 1112222222222333 PTE2/SS PTE3/SPSCKPTE4/SCL/MOSIPTE5/SDA/MISO PTG2PTG3PTF0/TxD2PTF1/RxD2PTF2/TPM1CLK/SCLPTF3/TPM2CLK/SDA PTG4PTG5PTE6/TxD2/TXCANPTE7/RxD2/RXCANPTD0/PID0/TPM2CH0PTD1/PID1/TPM2CH1 Figure2-1. 64-Pin LQFP MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 27

Chapter2 Pins and Connections 1O 1- 1+ P P P M M M C C C P6P13 P5P12 P4 P3/AP11P2/AP10P1/A DD DD D DDDDD TA6/PIA6/ATB5/PIB5/A TA5/PIA5/ATB4/PIB4/A TA4/PIA4/A/VDDAREFH/VSSAREFLTA3/PIA3/ATB3/PIB3/ATA2/PIA2/ATB2/PIB2/ATA1/PIA1/A PP PP PVVPPPPP 876543210987 PTB6/PIB6/ADP14 144444444433336 PTB1/PIB1/ADP9 PTA7/PIA7/ADP7/IRQ 2 35 PTA0/PIA0/ADP0/MCLK PTB7/PIB7/ADP15 3 34 PTB0/PIB0/ADP8 V 4 33 BKGD/MS DD V 5 32 PTD7/PID7/TPM1CH5 SS PTG0/EXTAL 6 31 PTD6/PID6/TPM1CH4 48-Pin LQFP PTG1/XTAL 7 30 VDD RESET 8 29 VSS PTF4/ACMP2+ 9 28 PTD5/PID5/TPM1CH3 PTF5/ACMP2- 10 27 PTD4/PID4/TPM1CH2 PTE0/TxD1 11 26 PTD3/PID3/TPM1CH1 PTE1/RxD1 12 25 PTD2/PID2/TPM1CH0 345678901234 111111122222 PTE2/SS PTE3/SPSCKPTE4/SCL/MOSIPTE5/SDA/MISOPTF0/TxD2PTF1/RxD2PTF2/TPM1CLK/SCLPTF3/TPM2CLK/SDAPTE6/TxD2/TXCANPTE7/RxD2/RXCANPTD0/PID0/TPM2CH0PTD1/PID1/TPM2CH1 V and V are internally connected to V and V , respectively. REFH REFL DDA SSA Figure2-2. 48-Pin LQFP MC9S08DZ60 Series Data Sheet, Rev. 4 28 Freescale Semiconductor

Chapter2 Pins and Connections PO P- P+ PIA6/ADP6 PIA5/ADP5 PIA4/ADP4 VREFH VREFL ADP3/ACM ADP2/ACM ADP1/ACM PTA6/ PTA5/ PTA4/ V/DDA V/SSA PTA3/ PTA2/ PTA1/ 32 25 31 30 29 28 27 26 PTA7/PIA7/ADP7/IRQ 1 24 PTB1/PIB1/ADP9 VDD 2 23 PTA0/PIA0/ADP0/MCLK VSS 3 22 PTB0/PIB0/ADP8 PTG0/EXTAL 4 21 BKGD/MS 32-Pin LQFP PTG1/XTAL 5 20 PTD5/PID5/TPM1CH3 RESET 6 19 PTD4/PID4/TPM1CH2 PTE0/TxD1 7 18 PTD3/PID3/TPM1CH1 PTE1/RxD1 8 17 PTD2/PID2/TPM1CH0 10 11 12 13 14 15 9 16 TE2/SS SPSCK L/MOSI A/MISO TXCAN RXCAN M2CH0 M2CH1 P PTE3/ PTE4/SC PTE5/SD PTE6/TxD2/ PTE7/RxD2/ TD0/PID0/TP TD1/PID1/TP P P V and V are internally connected to V and V , respectively. REFH REFL DDA SSA Figure2-3. 32-Pin LQFP MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 29

Chapter2 Pins and Connections 2.2 Recommended System Connections Figure2-4 shows pin connections that are common to MC9S08DZ60 Series application systems. MC9S08DZ60 V PTA0/PIA0/ADP0/MCLK DD + PTA1/PIA1/ADP1/ACMP1+ CBLK + CBY 5 V 10μF 0.1μF PTA2/PIA2/ADP2/ACMP1- V PTA3/PIA3/ADP3/ACMP1O SS PORT A PTA4/PIA4/ADP4 V SYSTEM DDA PTA5/PIA5/ADP5 POWER CBY VREFH PTA6/PIA6/ADP6 0.1μF IRQ V PTA7/PIA7/ADP7/IRQ REFL V SSA PTB0/PIB0/ADP8 PTB1/PIB1/ADP9 BACKGROUND HEADER PTB2/PIB2/ADP10 PORT PTB3/PIB3/ADP11 V DD BKGD/MS B PTB4/PIB4/ADP12 V DD PTB5/PIB5/ADP13 4.7 kΩ–10 kΩ PTB6/PIB6/ADP14 PTB7/PIB7/ADP15 RESET PTC0/ADP16 OPTIONAL 0.1μF PTC1/ADP17 MANUAL PTC2/ADP18 RESET PTC3/ADP19 PORT C PTC4/ADP20 PTC5/ADP21 PTC6/ADP22 PTC7/ADP23 R F R S C1 X1 C2 PTD0/PID0/TPM2CH0 PTD1/PID1/TPM2CH1 PTD2/PID2/TPM1CH0 PTG0/EXTAL NOTES: PTG1/XTAL PORT PTD3/PID3/TPM1CH1 1. Erexqteurirneadl cifr uysstinagl c tihrceuit not PTG2 PORT D PTD4/PID4/TPM1CH2 2. iRnEteSrnEaTl cplionc cka onp otinolny. be PTG3 G PTD5/PID5/TPM1CH3 umsoedde t,o y oreus ecat nin tnoo ut seenrter PTG4 PTD6/PID6/TPM1CH4 BDM usingRESET pin. PTG5 PTD7/PID7/TPM1CH5 BDM can be entered by holding MS low during POR or writing a 1 to PTF0/TxD2 PTE0/TxD1 BDFR in SBDFR with MS low after issuing BDM PTF1/RxD2 PTE1/RxD1 command. PTF2/TPM1CLK/SCL PTE2/SS 3. RC filter onRESET pin recommended for noisy PTF3/TPM2CLK/SDA PTE3/SPSCK environments. PORT PORT 4. For 32-pin and 48-pin PTF4/ACMP2+ E PTE4/SCL/MOSI F paarec kdaoguebsle: VbDoDnAdeadn dtoVSSA PTF5/ACMP2– PTE5/SDA/MISO VREFH and VREFL PTF6/ACMP2O PTE6/TxD2/TXCAN respectively. PTF7 PTE7/RxD2/RXCAN Figure2-4. Basic System Connections (Shown in 64-Pin Package) MC9S08DZ60 Series Data Sheet, Rev. 4 30 Freescale Semiconductor

Chapter2 Pins and Connections 2.2.1 Power V and V are the primary power supply pins for the MCU. This voltage source supplies power to all DD SS I/Obuffercircuitryandtoaninternalvoltageregulator.Theinternalvoltageregulatorprovidesregulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there shouldbeabulkelectrolyticcapacitor,suchasa10-μFtantalumcapacitor,toprovidebulkchargestorage for the overall system and a 0.1-μF ceramic bypass capacitor located as near to the MCU power pins as practical to suppress high-frequency noise. The MC9S08DZ60 Series has two V pins except on the DD 32-pin package. Each pin must have a bypass capacitor for best noise suppression. V andV aretheanalogpowersupplypinsfortheMCU.Thisvoltagesourcesuppliespowertothe DDA SSA ADC module. A 0.1-μF ceramic bypass capacitor should be located as near to the MCU power pins as practical to suppress high-frequency noise. 2.2.2 Oscillator Immediatelyafterreset,theMCUusesaninternallygeneratedclockprovidedbythemulti-purposeclock generator (MCG) module. For more information on the MCG, see Chapter8, “Multi-Purpose Clock Generator (S08MCGV1).” The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator.Ratherthanacrystalorceramicresonator,anexternaloscillatorcanbeconnectedtotheEXTAL input pin. Refer toFigure2-4 for the following discussion. R (when used) and R should be low-inductance S F resistors such as carbon composition resistors. Wire-wound resistors and some metal film resistors have toomuchinductance.C1andC2normallyshouldbehigh-qualityceramiccapacitorsthatarespecifically designed for high-frequency applications. R isusedtoprovideabiaspathtokeeptheEXTALinputinitslinearrangeduringcrystalstartup;itsvalue F isnotgenerallycritical.Typicalsystemsuse1MΩto10MΩ.Highervaluesaresensitivetohumidity,and lower values reduce gain and (in extreme cases) could prevent startup. C1andC2aretypicallyinthe5-pFto25-pFrangeandarechosentomatchtherequirementsofaspecific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 (which are usually the same size). As a first-order approximation, use 10pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). 2.2.3 RESET RESETisadedicatedpinwithapull-updevicebuiltin.Ithasinputhysteresis,ahighcurrentoutputdriver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debugconnectorsoadevelopmentsystemcandirectlyresettheMCUsystem.Ifdesired,amanualexternal reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 31

Chapter2 Pins and Connections Wheneveranyresetisinitiated(whetherfromanexternalsignalorfromaninternalsystem),the RESET pin is driven low for about 34 bus cycles. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system reset status register (SRS). 2.2.4 Background / Mode Select (BKGD/MS) While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises, the pin functionsasthebackgroundpinandcanbeusedforbackgrounddebugcommunication.Whilefunctioning asabackgroundormodeselectpin,thepinincludesaninternalpull-updevice,inputhysteresis,astandard output driver, and no output slew rate control. Ifnothingisconnectedtothispin,theMCUwillenternormaloperatingmodeattherisingedgeofreset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD low during the rising edge of reset which forces the MCU to active background mode. The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a customprotocolthatuses16clockcyclesofthetargetMCU’sBDCclockperbittime.ThetargetMCU’s BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. AlthoughtheBKGD/MSpinisapseudoopen-drainpin,thebackgrounddebugcommunicationprotocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cablesandtheabsolutevalueoftheinternalpull-updeviceplayalmostnoroleindeterminingriseandfall times on the BKGD/MS pin. 2.2.5 ADC Reference Pins (V , V ) REFH REFL TheV andV pinsarethevoltagereferencehighandvoltagereferencelowinputs,respectively, REFH REFL for the ADC module. 2.2.6 General-Purpose I/O and Peripheral Ports TheMC9S08DZ60SeriesseriesofMCUssupportupto53general-purposeI/Opinsand1input-onlypin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, MSCAN, etc.). When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. When a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pull-updevice.Immediatelyafterreset,allofthesepinsareconfiguredashigh-impedancegeneral-purpose inputs with internal pull-up devices disabled. Whenanon-chipperipheralsystemiscontrollingapin,datadirectioncontrolbitsstilldeterminewhatis read from port data registers even though the peripheral module controls the pin direction by controlling theenableforthepin’soutputbuffer.Forinformationaboutcontrollingthesepinsasgeneral-purposeI/O pins, seeChapter6, “Parallel Input/Output Control.” MC9S08DZ60 Series Data Sheet, Rev. 4 32 Freescale Semiconductor

Chapter2 Pins and Connections NOTE Toavoidextracurrentdrainfromfloatinginputpins,theresetinitialization routine in the application program should either enable on-chip pull-up devicesorchangethedirectionofunusedornon-bondedpinstooutputsso they do not float. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 33

Chapter2 Pins and Connections Table2-1. Pin Availability by Package Pin-Count 3 Pin Pin <-- Lowest Priority --> Highest <-- Lowest Priority --> Highest Number Number Port Port 64 48 32 Alt 1 Alt 2 64 48 32 Alt 1 Alt 2 Pin/Interrupt Pin/Interrupt 1 1 — PTB6 PIB6 ADP14 33 25 17 PTD2 PID2 TPM1CH0 2 — — PTC5 ADP21 34 26 18 PTD3 PID3 TPM1CH1 3 2 1 PTA7 PIA7 ADP7 IRQ 35 27 19 PTD4 PID4 TPM1CH2 4 — — PTC6 ADP22 36 28 20 PTD5 PID5 TPM1CH3 5 3 — PTB7 PIB7 ADP15 37 — — PTF7 6 — — PTC7 ADP23 38 29 — VSS 7 4 2 VDD 39 30 — VDD 8 5 3 V 40 31 — PTD6 PID6 TPM1CH4 SS 9 6 4 PTG0 EXTAL 41 32 — PTD7 PID7 TPM1CH5 10 7 5 PTG1 XTAL 42 33 21 BKGD MS 11 8 6 RESET 43 — — PTC0 ADP16 12 9 — PTF4 ACMP2+ 44 34 22 PTB0 PIB0 ADP8 13 10 — PTF5 ACMP2- 45 — — PTC1 ADP17 14 — — PTF6 ACMP2O 46 35 23 PTA0 PIA0 ADP0 MCLK 15 11 7 PTE0 TxD1 47 — — PTC2 ADP18 16 12 8 PTE12 RxD12 48 36 24 PTB1 PIB1 ADP9 17 13 9 PTE2 SS 49 37 25 PTA1 PIA1 ADP11 ACMP1+1 18 14 10 PTE3 SPSCK 50 38 — PTB2 PIB2 ADP10 19 15 11 PTE4 SCL3 MOSI 51 39 26 PTA2 PIA2 ADP21 ACMP1-1 20 16 12 PTE5 SDA3 MISO 52 — — PTC3 ADP19 21 — — PTG2 53 40 — PTB3 PIB3 ADP11 22 — — PTG3 54 41 27 PTA3 PIA3 ADP3 ACMP1O 23 17 — PTF0 TxD24 55 VSSA 42 28 24 18 — PTF1 RxD24 56 VREFL 25 19 — PTF2 TPM1CLK SCL3 57 VREFH 43 29 26 20 — PTF3 TPM2CLK SDA3 58 VDDA 27 — — PTG4 59 44 30 PTA4 PIA4 ADP4 28 — — PTG5 60 45 — PTB4 PIB4 ADP12 29 21 13 PTE6 TxD24 TXCAN 61 — — PTC4 ADP20 30 22 14 PTE7 RxD24 RxCAN 62 46 31 PTA5 PIA5 ADP5 31 23 15 PTD0 PID0 TPM2CH0 63 47 — PTB5 PIB5 ADP13 32 24 16 PTD1 PID1 TPM2CH1 64 48 32 PTA6 PIA6 ADP6 1. If both of these analog modules are enabled, they both will have access to the pin. 2.PindoesnotcontainaclampdiodetoV andshouldnotbedrivenaboveV .Thevoltagemeasuredonthispinwheninternal DD DD pull-up is enabled may be as low as V – 0.7 V. The internal gates connected to this pin are pulled to V . DD DD 3.TheIICmodulepinscanberepositionedusingIICPSbitintheSOPT1register.ThedefaultresetlocationsareonPTF2andPTF3. 4.TheSCI2modulepinscanberepositionedusingSCI2PSbitintheSOPT1register.ThedefaultresetlocationsareonPTF0and PTF1. MC9S08DZ60 Series Data Sheet, Rev. 4 34 Freescale Semiconductor

Chapter 3 Modes of Operation 3.1 Introduction TheoperatingmodesoftheMC9S08DZ60Seriesaredescribedinthischapter.Entryintoeachmode,exit from each mode, and functionality while in each of the modes are described. 3.2 Features • Active background mode for code development • Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation is maintained • Stop modes — System clocks are stopped and voltage regulator is in standby — Stop3 — All internal circuits are powered for fast recovery — Stop2 — Partial power down of internal circuits; RAM content is retained 3.3 Run Mode This is the normal operating mode for the MC9S08DZ60 Series. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset. 3.4 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for analyzing MCU operation during software development. Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD/MS pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint Afterenteringactivebackgroundmode,theCPUisheldinasuspendedstatewaitingforserialbackground commands rather than executing instructions from the user application program. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 35

Chapter3 Modes of Operation Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running.Non-intrusivecommandscanbeissuedthroughtheBKGD/MSpinwhiletheMCUisin run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command • Activebackgroundcommands,whichcanonlybeexecutedwhiletheMCUisinactivebackground mode. Active background commands include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user application program (GO) The active background mode is used to program a bootloader or user application program into theFlash program memory before the MCU is operated in run mode for the first time. When the MC9S08DZ60 Series is shipped from the Freescale Semiconductor factory, theFlash program memory is erased by defaultunlessspecificallynotedsothereisnoprogramthatcouldbeexecutedinrunmodeuntiltheFlash memory is initially programmed. The active background mode can also be used to erase and reprogram theFlash memory after it has been previously programmed. For additional information about the active background mode, refer to the Development Support chapter. 3.5 Wait Mode WaitmodeisenteredbyexecutingaWAITinstruction.UponexecutionoftheWAITinstruction,theCPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available whentheMCUisinwaitmode.Thememory-access-with-statuscommandsdonotallowmemoryaccess, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. MC9S08DZ60 Series Data Sheet, Rev. 4 36 Freescale Semiconductor

Chapter3 Modes of Operation 3.6 Stop Modes One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in SOPT1 register is set. In both stop modes, all internal clocks are halted. The MCG module can be configured to leave the reference clocks running. SeeChapter8, “Multi-Purpose Clock Generator (S08MCGV1),” for more information. Table3-1showsallofthecontrolbitsthataffectstopmodeselectionandthemodeselectedundervarious conditions. The selected mode is entered following the execution of a STOP instruction. Table3-1. Stop Mode Selection STOPE ENBDM1 LVDE LVDSE PPDC Stop Mode 0 x x x Stop modes disabled; illegal opcode reset if STOP instruction executed 1 1 x x Stop3 with BDM enabled2 1 0 Bothbitsmustbe1 x Stop3 with voltage regulator active 1 0 Either bit a 0 0 Stop3 1 0 Either bit a 0 1 Stop2 1 ENBDMislocatedintheBDCSCR,whichisonlyaccessiblethroughBDCcommands,seeSection17.4.1.1,“BDCStatusand Control Register (BDCSCR)”. 2 When in Stop3 mode with BDM enabled, The S will be near R levels because internal clocks are enabled. IDD IDD 3.6.1 Stop3 Mode Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. Exitfromstop3isdonebyassertingRESEToranasynchronousinterruptpin.Theasynchronousinterrupt pins are IRQ, PIA0–PIA7, PIB0–PIB7, and PID0–PID7. Exit from stop3 can also be done by the low-voltage detect (LVD) reset, low-voltage warning (LVW) interrupt, ADC conversion complete interrupt, real-time clock (RTC) interrupt, MSCAN wake-up interrupt, or SCI receiver interrupt. If stop3 is exited by means of the RESET pin, the MCU will be reset and operation will resume after fetching the reset vector. Exit by means of an interrupt will result in the MCU fetching the appropriate interrupt vector. 3.6.1.1 LVD Enabled in Stop3 Mode TheLVDsystemiscapableofgeneratingeitheraninterruptoraresetwhenthesupplyvoltagedropsbelow theLVDvoltage.IftheLVDisenabledinstop(LVDEandLVDSEbitsinSPMSC1bothset)atthetime the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. For the ADC to operate the LVD must be left enabled when entering stop3. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 37

Chapter3 Modes of Operation 3.6.1.2 Active BDM Enabled in Stop3 Mode Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This register is described inChapter17, “Development Support.” If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stopmode.Becauseofthis,backgrounddebugcommunicationremainspossible.Inaddition,thevoltage regulator does not enter its low-power standby state but maintains full internal regulation. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background commands are available. 3.6.2 Stop2 Mode Stop2modeisenteredbyexecutingaSTOPinstructionundertheconditionsasshowninTable 3-1.Most oftheinternalcircuitryoftheMCUispoweredoffinstop2withtheexceptionoftheRAM.Uponentering stop2, all I/O pin control signals are latched so that the pins retain their states during stop2. Exitfromstop2isperformedbyassertingRESET.On3M05Coroldermasksetsonly,exitfromstop2can also be performed by asserting PTA7/ADP7/IRQ. NOTE On 3M05C or older masksets only, PTA7/ADP7/IRQ is an active low wake-up and must be configured as an input prior to executing a STOP instructiontoavoidanimmediateexitfromstop2.PTA7/ADP7/IRQcanbe disabledasawake-upifitisconfiguredasahighdrivenoutput.Forlowest power consumption in stop2, this pin should not be left open when configured as input (enable the internal pullup; or tie an external pullup/down device; or set pin as output). In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled. Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR): • All module control and status registers are reset • TheLVDresetfunctionisenabledandtheMCUremainsintheresetstateifV isbelowtheLVD DD trip point (low trip point selected due to POR) • The CPU takes the reset vector Inadditiontotheabove,uponwakingupfromstop2,thePPDFbitinSPMSC2isset.Thisflagisusedto directusercodetogotoastop2recoveryroutine.PPDFremainssetandtheI/Opinstatesremainlatched until a 1 is written to PPDACK in SPMSC2. MC9S08DZ60 Series Data Sheet, Rev. 4 38 Freescale Semiconductor

Chapter3 Modes of Operation TomaintainI/Ostatesforpinsthatwereconfiguredasgeneral-purposeI/Obeforeenteringstop2,theuser must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the pins will switch to their reset states when PPDACK is written. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.3 On-Chip Peripheral Modules in Stop Modes WhentheMCUentersanystopmode,systemclockstotheinternalperipheralmodulesarestopped.Even in the exception case (ENBDM=1), where clocks to the background debug logic continue to operate, clockstotheperipheralsystemsarehaltedtoreducepowerconsumption.RefertoSection3.6.2,“Stop2 Mode” and Section 3.6.1, “Stop3 Mode” for specific information on system behavior in stop modes. Table3-2. Stop Mode Behavior Mode Peripheral Stop2 Stop3 CPU Off Standby RAM Standby Standby Flash/EEPROM Off Standby Parallel Port Registers Off Standby ACMP Off Off ADC Off Optionally On1 IIC Off Standby MCG Off Optionally On2 MSCAN Off Standby RTC Optionally On3 Optionally On3 SCI Off Standby SPI Off Standby TPM Off Standby Voltage Regulator Off Optionally On4 XOSC Off Optionally On5 I/O Pins States Held States Held BDM Off6 Optionally On LVD/LVW Off7 Optionally On 1 Requires the asynchronous ADC clock and LVD to be enabled, else in standby. 2 IRCLKEN and IREFSTEN set in MCGC1, else in standby. 3 Requires the RTC to be enabled, else in standby. 4 Requires the LVD or BDC to be enabled. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 39

Chapter3 Modes of Operation 5 ERCLKEN and EREFSTEN set in MCGC2 for, else in standby. For high frequency range (RANGE in MCGC2 set) requires the LVD to also be enabled in stop3. 6 If ENBDM is set when entering stop2, the MCU will actually enter stop3. 7 If LVDSE is set when entering stop2, the MCU will actually enter stop3. MC9S08DZ60 Series Data Sheet, Rev. 4 40 Freescale Semiconductor

Chapter 4 Memory 4.1 MC9S08DZ60 Series Memory Map On-chip memory in the MC9S08DZ60 Series consists of RAM, EEPROM, andFlash program memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x007F) • High-page registers (0x1800 through 0x18FF) • Nonvolatile registers (0xFFB0 through 0xFFBF) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 41

Chapter4 Memory 0x0000 0x0000 0x0000 0x0000 DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS 0x007F 128 BYTES 0x007F 128 BYTES 0x007F 128 BYTES 0x007F 128 BYTES 0x0080 0x0080 0x0080 0x0080 RAM RAM RAM RAM 4096 BYTES 3072 BYTES 2048 BYTES 1024 BYTES 0x047F 0x087F 0x0480 0x0C7F 0x0880 0x0C80 0x107F 0x1080 FLASH UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED 896 BYTES 2176 BYTES 3456 BYTES 4736 BYTES 0x13FF 0x1400 0x14FF 0x1500 EEPROM1 0x15FF 0x16FF EEPROM1 2 x 768 BYTES 0x1600 EEPROM1 2 x 1024 BYTES 2 x 512 BYTES 0x1700 EEPROM1 0x17FF 0x17FF 0x17FF 0x17FF 2 x 256 BYTES 0x1800 0x1800 0x1800 0x1800 HIGH PAGE REGISTERS HIGH PAGE REGISTERS HIGH PAGE REGISTERS HIGH PAGE REGISTERS 256 BYTES 256 BYTES 256 BYTES 256 BYTES 0x18FF 0x18FF 0x18FF 0x18FF 0x1900 0x1900 0x1900 0x1900 UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED 9984 BYTES 25,344 BYTES 42,240 BYTES 0x3FFF 0x4000 0x7BFF 0x7C00 0xBDFF 0xBE00 FLASH FLASH FLASH FLASH 59136 BYTES 49152 BYTES 33792 BYTES 16896 BYTES 0xFFFF 0xFFFF 0xFFFF 0xFFFF MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16 1 EEPROM address range shows half the total EEPROM. SeeSection 4.5.10, “EEPROM Mapping” for more details. Figure4-1. MC9S08DZ60 Memory Map 4.2 Reset and Interrupt Vector Assignments Table4-1showsaddressassignmentsforresetandinterruptvectors.Thevectornamesshowninthistable are the labels used in the MC9S08DZ60 Series equate file provided by Freescale Semiconductor. Table4-1. Reset and Interrupt Vectors Address Vector Vector Name (High/Low) 0xFFC0:0xFFC1 ACMP2 Vacmp2 0xFFC2:0xFFC3 ACMP1 Vacmp1 0xFFC4:0xFFC5 MSCAN Transmit Vcantx 0xFFC6:0xFFC7 MSCAN Receive Vcanrx 0xFFC8:0xFFC9 MSCAN errors Vcanerr 0xFFCA:0xFFCB MSCAN wake up Vcanwu MC9S08DZ60 Series Data Sheet, Rev. 4 42 Freescale Semiconductor

Chapter4 Memory Table4-1. Reset and Interrupt Vectors Address Vector Vector Name (High/Low) 0xFFCC:0xFFCD RTC Vrtc 0xFFCE:0xFFCF IIC Viic 0xFFD0:0xFFD1 ADC Conversion Vadc 0xFFD2:0xFFD3 Port A, Port B, Port D Vport 0xFFD4:0xFFD5 SCI2 Transmit Vsci2tx 0xFFD6:0xFFD7 SCI2 Receive Vsci2rx 0xFFD8:0xFFD9 SCI2 Error Vsci2err 0xFFDA:0xFFDB SCI1 Transmit Vsci1tx 0xFFDC:0xFFDD SCI1 Receive Vsci1rx 0xFFDE:0xFFDF SCI1 Error Vsci1err 0xFFE0:0xFFE1 SPI Vspi 0xFFE2:0xFFE3 TPM2 Overflow Vtpm2ovf 0xFFE4:0xFFE5 TPM2 Channel 1 Vtpm2ch1 0xFFE6:0xFFE7 TPM2 Channel 0 Vtpm2ch0 0xFFE8:0xFFE9 TPM1 Overflow Vtpm1ovf 0xFFEA:0xFFEB TPM1 Channel 5 Vtpm1ch5 0xFFEC:0xFFED TPM1 Channel 4 Vtpm1ch4 0xFFEE:0xFFEF TPM1 Channel 3 Vtpm1ch3 0xFFF0:0xFFF1 TPM1 Channel 2 Vtpm1ch2 0xFFF2:0xFFF3 TPM1 Channel 1 Vtpm1ch1 0xFFF4:0xFFF5 TPM1 Channel 0 Vtpm1ch0 0xFFF6:0xFFF7 MCG Loss of lock Vlol 0xFFF8:0xFFF9 Low-Voltage Detect Vlvd 0xFFFA:0xFFFB IRQ Virq 0xFFFC:0xFFFD SWI Vswi 0xFFFE:0xFFFF Reset Vreset MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 43

Chapter4 Memory 4.3 Register Addresses and Bit Assignments The registers in the MC9S08DZ60 Series are divided into these groups: • Direct-pageregistersarelocatedinthefirst128locationsinthememorymap;theseareaccessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and RAM. • The nonvolatile register area consists of a block of 16locations inFlash memory at 0xFFB0–0xFFBF. Nonvolatile register locations include: — NVPROT and NVOPT are loaded into working registers at reset — An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory BecausethenonvolatileregisterlocationsareFlashmemory,theymustbeerasedandprogrammed like otherFlash memory locations. Direct-pageregisterscanbeaccessedwithefficientdirectaddressingmodeinstructions.Bitmanipulation instructions can be used to access any bit in any direct-page register. Table4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efficient direct addressing mode, which requires onlythelowerbyteoftheaddress.Becauseofthis,thelowerbyteoftheaddressincolumnoneisshown in bold text. InTable4-3 andTable4-5, the whole address in column one is shown in bold. In Table4-2, Table4-3, andTable4-5, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. MC9S08DZ60 Series Data Sheet, Rev. 4 44 Freescale Semiconductor

Chapter4 Memory Table4-2. Direct-Page Register Summary (Sheet 1 of 3) Register Address Bit 7 6 5 4 3 2 1 Bit 0 Name 0x0000 PTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 0x0001 PTADD PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0 0x0002 PTBD PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 0x0003 PTBDD PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0 0x0004 PTCD PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 0x0005 PTCDD PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0 0x0006 PTDD PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0 0x0007 PTDDD PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0 0x0008 PTED PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0 0x0009 PTEDD PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0 0x000A PTFD PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0 0x000B PTFDD PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0 0x000C PTGD 0 0 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0 0x000D PTGDD 0 0 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0 0x000E ACMP1SC ACME ACBGS ACF ACIE ACO ACOPE ACMOD1 ACMOD0 0x000F ACMP2SC ACME ACBGS ACF ACIE ACO ACOPE ACMOD1 ACMOD0 0x0010 ADCSC1 COCO AIEN ADCO ADCH 0x0011 ADCSC2 ADACT ADTRG ACFE ACFGT 0 0 — — 0x0012 ADCRH 0 0 0 0 ADR11 ADR10 ADR9 ADR8 0x0013 ADCRL ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0x0014 ADCCVH 0 0 0 0 ADCV11 ADCV10 ADCV9 ADCV8 0x0015 ADCCVL ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0 0x0016 ADCCFG ADLPC ADIV ADLSMP MODE ADICLK 0x0017 APCTL1 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0 0x0018 APCTL2 ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 0x0019 APCTL3 ADPC23 ADPC22 ADPC21 ADPC20 ADPC19 ADPC18 ADPC17 ADPC16 0x001A– — — — — — — — — Reserved 0x001B — — — — — — — — 0x001C IRQSC 0 IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD 0x001D– — — — — — — — — Reserved 0x001F — — — — — — — — 0x0020 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0x0021 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x0022 TPM1CNTL Bit 7 6 5 4 3 2 1 Bit 0 0x0023 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8 0x0024 TPM1MODL Bit 7 6 5 4 3 2 1 Bit 0 0x0025 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0x0026 TPM1C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0027 TPM1C0VL Bit 7 6 5 4 3 2 1 Bit 0 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 45

Chapter4 Memory Table4-2. Direct-Page Register Summary (Sheet 2 of 3) Register Address Bit 7 6 5 4 3 2 1 Bit 0 Name 0x0028 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 0x0029 TPM1C1VH Bit 15 14 13 12 11 10 9 Bit 8 0x002A TPM1C1VL Bit 7 6 5 4 3 2 1 Bit 0 0x002B TPM1C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0 0x002C TPM1C2VH Bit 15 14 13 12 11 10 9 Bit 8 0x002D TPM1C2VL Bit 7 6 5 4 3 2 1 Bit 0 0x002E TPM1C3SC CH3F CH3IE MS3B MS3A ELS3B ELS3A 0 0 0x002F TPM1C3VH Bit 15 14 13 12 11 10 9 Bit 8 0x0030 TPM1C3VL Bit 7 6 5 4 3 2 1 Bit 0 0x0031 TPM1C4SC CH4F CH4IE MS4B MS4A ELS4B ELS4A 0 0 0x0032 TPM1C4VH Bit 15 14 13 12 11 10 9 Bit 8 0x0033 TPM1C4VL Bit 7 6 5 4 3 2 1 Bit 0 0x0034 TPM1C5SC CH5F CH5IE MS5B MS5A ELS5B ELS5A 0 0 0x0035 TPM1C5VH Bit 15 14 13 12 11 10 9 Bit 8 0x0036 TPM1C5VL Bit 7 6 5 4 3 2 1 Bit 0 0x0037 Reserved — — — — — — — — 0x0038 SCI1BDH LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8 0x0039 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x003A SCI1C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0x003B SCI1C2 TIE TCIE RIE ILIE TE RE RWU SBK 0x003C SCI1S1 TDRE TC RDRF IDLE OR NF FE PF 0x003D SCI1S2 LBKDIF RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF 0x003E SCI1C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE 0x003F SCI1D Bit 7 6 5 4 3 2 1 Bit 0 0x0040 SCI2BDH LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8 0x0041 SCI2BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x0042 SCI2C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0x0043 SCI2C2 TIE TCIE RIE ILIE TE RE RWU SBK 0x0044 SCI2S1 TDRE TC RDRF IDLE OR NF FE PF 0x0045 SCI2S2 LBKDIF RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF 0x0046 SCI2C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE 0x0047 SCI2D Bit 7 6 5 4 3 2 1 Bit 0 0x0048 MCGC1 CLKS RDIV IREFS IRCLKEN IREFSTEN 0x0049 MCGC2 BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN 0x004A MCGTRM TRIM 0x004B MCGSC LOLS LOCK PLLST IREFST CLKST OSCINIT FTRIM 0x004C MCGC3 LOLIE PLLS CME 0 VDIV 0x004D– — — — — — — — — Reserved 0x004F — — — — — — — — MC9S08DZ60 Series Data Sheet, Rev. 4 46 Freescale Semiconductor

Chapter4 Memory Table4-2. Direct-Page Register Summary (Sheet 3 of 3) Register Address Bit 7 6 5 4 3 2 1 Bit 0 Name 0x0050 SPIC1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0x0051 SPIC2 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0 0x0052 SPIBR 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0 0x0053 SPIS SPRF 0 SPTEF MODF 0 0 0 0 0x0054 Reserved 0 0 0 0 0 0 0 0 0x0055 SPID Bit 7 6 5 4 3 2 1 Bit 0 0x0056– — — — — — — — — 0x0057 Reserved — — — — — — — — 0x0058 IICA AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 0x0059 IICF MULT ICR 0x005A IICC1 IICEN IICIE MST TX TXAK RSTA 0 0 0x005B IICS TCF IAAS BUSY ARBL 0 SRW IICIF RXAK 0x005C IICD DATA 0x005D IICC2 GCAEN ADEXT 0 0 0 AD10 AD9 AD8 0x005E– — — — — — — — — Reserved 0x005F — — — — — — — — 0x0060 TPM2SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0x0061 TPM2CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x0062 TPM2CNTL Bit 7 6 5 4 3 2 1 Bit 0 0x0063 TPM2MODH Bit 15 14 13 12 11 10 9 Bit 8 0x0064 TPM2MODL Bit 7 6 5 4 3 2 1 Bit 0 0x0065 TPM2C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0x0066 TPM2C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0067 TPM2C0VL Bit 7 6 5 4 3 2 1 Bit 0 0x0068 TPM2C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 0x0069 TPM2C1VH Bit 15 14 13 12 11 10 9 Bit 8 0x006A TPM2C1VL Bit 7 6 5 4 3 2 1 Bit 0 0x006B Reserved — — — — — — — — 0x006C RTCSC RTIF RTCLKS RTIE RTCPS 0x006D RTCCNT RTCCNT 0x006E RTCMOD RTCMOD 0x006F Reserved — — — — — — — — 0x0070– — — — — — — — — Reserved 0x007F — — — — — — — — High-pageregisters,showninTable4-3,areaccessedmuchlessoftenthanotherI/Oandcontrolregisters so they have been located outside the direct addressable memory space, starting at 0x1800. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 47

Chapter4 Memory Table4-3. High-Page Register Summary (Sheet 1 of 3) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x1800 SRS POR PIN COP ILOP ILAD LOCS LVD 0 0x1801 SBDFR 0 0 0 0 0 0 0 BDFR 0x1802 SOPT1 COPT STOPE SCI2PS IICPS 0 0 0 0x1803 SOPT2 COPCLKS COPW 0 ADHTS 0 MCSEL 0x1804– — — — — — — — — Reserved 0x1805 — — — — — — — — 0x1806 SDIDH — — — — ID11 ID10 ID9 ID8 0x1807 SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0x1808 Reserved — — — — — — — — 0x1809 SPMSC1 LVWF LVWACK LVWIE LVDRE LVDSE LVDE 0 BGBE 0x180A SPMSC2 0 0 LVDV LVWV PPDF PPDACK 0 PPDC 0x180B– — — — — — — — — Reserved 0x180F — — — — — — — — 0x1810 DBGCAH Bit 15 14 13 12 11 10 9 Bit 8 0x1811 DBGCAL Bit 7 6 5 4 3 2 1 Bit 0 0x1812 DBGCBH Bit 15 14 13 12 11 10 9 Bit 8 0x1813 DBGCBL Bit 7 6 5 4 3 2 1 Bit 0 0x1814 DBGFH Bit 15 14 13 12 11 10 9 Bit 8 0x1815 DBGFL Bit 7 6 5 4 3 2 1 Bit 0 0x1816 DBGC DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0x1817 DBGT TRGSEL BEGIN 0 0 TRG3 TRG2 TRG1 TRG0 0x1818 DBGS AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0x1819– — — — — — — — — Reserved 0x181F — — — — — — — — 0x1820 FCDIV DIVLD PRDIV8 DIV 0x1821 FOPT KEYEN FNORED EPGMOD 0 0 0 SEC 0x1822 Reserved — — — — — — — — 0x1823 FCNFG 0 EPGSEL KEYACC Reserved1 0 0 0 1 0x1824 FPROT EPS FPS 0x1825 FSTAT FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0 0x1826 FCMD FCMD 0x1827– — — — — — — — — Reserved 0x183F — — — — — — — — 0x1840 PTAPE PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 0x1841 PTASE PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 0x1842 PTADS PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0 0x1843 Reserved — — — — — — — — 0x1844 PTASC 0 0 0 0 PTAIF PTAACK PTAIE PTAMOD 0x1845 PTAPS PTAPS7 PTAPS6 PTAPS5 PTAPS4 PTAPS3 PTAPS2 PTAPS1 PTAPS0 0x1846 PTAES PTAES7 PTAES6 PTAES5 PTAES4 PTAES3 PTAES2 PTAES1 PTAES0 MC9S08DZ60 Series Data Sheet, Rev. 4 48 Freescale Semiconductor

Chapter4 Memory Table4-3. High-Page Register Summary (Sheet 2 of 3) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x1847 Reserved — — — — — — — — 0x1848 PTBPE PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0x1849 PTBSE PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 0x184A PTBDS PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0 0x184B Reserved — — — — — — — — 0x184C PTBSC 0 0 0 0 PTBIF PTBACK PTBIE PTBMOD 0x184D PTBPS PTBPS7 PTBPS6 PTBPS5 PTBPS4 PTBPS3 PTBPS2 PTBPS1 PTBPS0 0x184E PTBES PTBES7 PTBES6 PTBES5 PTBES4 PTBES3 PTBES2 PTBES1 PTBES0 0x184F Reserved — — — — — — — — 0x1850 PTCPE PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0x1851 PTCSE PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0 0x1852 PTCDS PTCDS7 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0 0x1853– — — — — — — — — Reserved 0x1857 — — — — — — — — 0x1858 PTDPE PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 0x1859 PTDSE PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 0x185A PTDDS PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0 0x185B Reserved — — — — — — — — 0x185C PTDSC 0 0 0 0 PTDIF PTDACK PTDIE PTDMOD 0x185D PTDPS PTDPS7 PTDPS6 PTDPS5 PTDPS4 PTDPS3 PTDPS2 PTDPS1 PTDPS0 0x185E PTDES PTDES7 PTDES6 PTDES5 PTDES4 PTDES3 PTDES2 PTDES1 PTDES0 0x185F Reserved — — — — — — — — 0x1860 PTEPE PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 0x1861 PTESE PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0 0x1862 PTEDS PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS1 PTEDS0 0x1863– — — — — — — — — Reserved 0x1867 — — — — — — — — 0x1868 PTFPE PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 0x1869 PTFSE PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0 0x186A PTFDS PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0 0x186B– — — — — — — — — Reserved 0x186F — — — — — — — — 0x1870 PTGPE 0 0 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0 0x1871 PTGSE 0 0 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0 0x1872 PTGDS 0 0 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0 0x1873– — — — — — — — — 0x187F Reserved — — — — — — — — 0x1880 CANCTL0 RXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ 0x1881 CANCTL1 CANE CLKSRC LOOPB LISTEN BORM WUPM SLPAK INITAK 0x1882 CANBTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 49

Chapter4 Memory Table4-3. High-Page Register Summary (Sheet 3 of 3) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x1883 CANBTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0x1884 CANRFLG WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF 0x1885 CANRIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE 0x1886 CANTFLG 0 0 0 0 0 TXE2 TXE1 TXE0 0x1887 CANTIER 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 0x1888 CANTARQ 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 0x1889 CANTAAK 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 0x188A CANTBSEL 0 0 0 0 0 TX2 TX1 TX0 0x188B CANIDAC 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0 0x188C Reserved 0 0 0 0 0 0 0 0 0x188D CANMISC 0 0 0 0 0 0 0 BOHOLD 0x188E CANRXERR RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 0x188F CANTXERR TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0x1890– CANIDAR0– AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0x1893 CANIDAR3 0x1894– CANIDMR0– AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 0x1897 CANIDMR3 0x1898– CANIDAR4– AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0x189B CANIDAR7 0x189C– CANIDMR4– AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 0x189F CANIDMR7 0x18BE CANTTSRH TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 0x18BF CANTTSRL TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 0x18C0– — — — — — — — — Reserved 0x18FF — — — — — — — — 1 This bit is reserved. User must write a 1 to this bit. Failing to do so may result in unexpected behavior. Figure4-4 shows the structure of receive and transmit buffers for extended identifier mapping. These registersvarydependingonwhetherstandardorextendedmappingisselected.SeeChapter12,“Freescale Controller Area Network (S08MSCANV1),” for details on extended and standard identifier mapping. Table4-4. MSCAN ForegroundReceiveand Transmit Buffer Layouts — Extended Mapping Shown 0x18A0 CANRIDR0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 0x18A1 CANRIDR1 ID20 ID19 ID18 SRR(1) IDE(1) ID17 ID16 ID15 0x18A2 CANRIDR2 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 0x18A3 CANRIDR3 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR2 0x18A4– CANRDSR0– DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0x18AB CANRDSR7 0x18AC CANRDLR — — — — DLC3 DLC2 DLC1 DLC0 0x18AD Reserved — — — — — — — — 0x18AE CANRTSRH TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 MC9S08DZ60 Series Data Sheet, Rev. 4 50 Freescale Semiconductor

Chapter4 Memory Table4-4. MSCAN ForegroundReceiveand Transmit Buffer Layouts — Extended Mapping Shown 0x18AF CANRTSRL TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 0x18B0 CANTIDR0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 0x18B1 CANTIDR1 ID2 ID1 ID0 RTR IDE — — — 0x18B2 CANTIDR2 — — — — — — — — 0x18B3 CANTIDR3 — — — — — — — — 0x18B4– CANTDSR0– DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0x18BB CANTDSR7 0x18BC CANTDLR — — — — DLC3 DLC2 DLC1 DLC0 0x18BD CANTTBPR PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 1 SRR and IDE are both 1s. 2 The position of RTR differs between extended and standardidentifier mapping. NonvolatileFlashregisters,showninTable 4-5,arelocatedintheFlashmemory.Theseregistersinclude an 8-byte backdoor key, NVBACKKEY, which can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of theFlash memoryaretransferredintocorrespondingFPROTandFOPTworkingregistersinthehigh-pageregisters to control security and block protection options. Table4-5. Nonvolatile Register Summary Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0xFFAE Reserved for 0 0 0 0 0 0 0 FTRIM storage of FTRIM 0xFFAF Res.forstorageof TRIM MCGTRM 0xFFB0– NVBACKKEY 8-Byte Comparison Key 0xFFB7 0xFFB8– Reserved — — — — — — — — 0xFFBC — — — — — — — — 0xFFBD NVPROT EPS FPS 0xFFBE Reserved — — — — — — — — 0xFFBF NVOPT KEYEN FNORED EPGMOD 0 0 0 SEC Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengagememorysecurity.Thiskeymechanismcanbeaccessedonlythroughusercoderunninginsecure memory.(Asecuritykeycannotbeentereddirectlythroughbackgrounddebugcommands.)Thissecurity key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the onlywaytodisengagesecurityisbymasserasingtheFlashifneeded(normallythroughthebackground debug interface) and verifying thatFlash is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC) to the unsecured state (1:0). MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 51

Chapter4 Memory 4.4 RAM The MC9S08DZ60 Series includes static RAM. The locations in RAM below 0x0100 can be accessed usingthemoreefficientdirectaddressingmode,andanysinglebitinthisareacanbeaccessedwiththebit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data while the MCU is in low-power wait, stop2, or stop3 mode. At power-on the contentsofRAMareuninitialized.RAMdataisunaffectedbyanyresetifthesupplyvoltagedoesnotdrop below the minimum value for RAM retention (V ). RAM For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08DZ60Series,itisusuallybesttoreinitializethestackpointertothetopoftheRAMsothedirect page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Includethefollowing2-instructionsequenceinyourresetinitializationroutine(whereRamLastisequated to the highest address of the RAM in the Freescale Semiconductor equate file). LDHX #RamLast+1 ;point one past RAM TXS ;SP<-(H:X-1) Whensecurityisenabled,theRAMisconsideredasecurememoryresourceandisnotaccessiblethrough BDMorcodeexecutingfromnon-securememory.SeeSection4.5.9,“Security”,foradetaileddescription of the security feature. 4.5 Flash and EEPROM MC9S08DZ60 Series devices includeFlash and EEPROM memory intended primarily for program and data storage. In-circuit programming allows the operating program and data to be loaded intoFlash and EEPROM,respectively,afterfinalassemblyoftheapplicationproduct.Itispossibletoprogramthearrays throughthesingle-wirebackgrounddebuginterface.Becausenospecialvoltagesareneededforeraseand programming operations, in-application programming is also possible through other software-controlled communicationpaths.Foramoredetaileddiscussionofin-circuitandin-applicationprogramming,refer to theHCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1. 4.5.1 Features Features of theFlash and EEPROM memory include: • Array size (seeTable1-1 for exact array sizes) • Flash sector size: 768 bytes • EEPROM sector size: selectable 4-byte or 8-byte sector mapping operation • Single power supply program and erase • Command interface for fast program and erase operation • Up to 100,000 program/erase cycles at typical voltage and temperature • Flexible block protection and vector redirection • Security feature forFlash, EEPROM, and RAM MC9S08DZ60 Series Data Sheet, Rev. 4 52 Freescale Semiconductor

Chapter4 Memory • Burst programming capability • Sector erase abort 4.5.2 Program and Erase Times Before any program or erase command can be accepted, theFlash and EEPROM clock divider register (FCDIV) must be written to set the internal clock for theFlash and EEPROM module to a frequency (f ) between 150kHz and 200kHz (seeSection 4.5.11.1, “Flash and EEPROM Clock Divider FCLK Register (FCDIV)”). This register can be written only once, so normally this write is performed during reset initialization. The user must ensure that FACCERR is not set before writing to the FCDIV register. Oneperiodoftheresultingclock(1/f )isusedbythecommandprocessortotimeprogramanderase FCLK pulses.Anintegernumberofthesetimingpulsesisusedbythecommandprocessortocompleteaprogram or erase command. Table4-6showsprogramanderasetimes.ThebusclockfrequencyandFCDIVdeterminethefrequency ofFCLK(f ).ThetimeforonecycleofFCLKist =1/f .Thetimesareshownasanumber FCLK FCLK FCLK of cycles of FCLK and as an absolute time for the case where t = 5μs. Program and erase times FCLK shownincludeoverheadforthecommandstatemachineandenablinganddisablingofprogramanderase voltages. Table4-6. Program and Erase Times Parameter Cycles of FCLK Time if FCLK=200kHz Byte program 9 45μs Burst program 4 20μs1 Sector erase 4000 20ms Mass erase 20,000 100ms Sector erase abort 4 20μs1 1 Excluding start/end overhead 4.5.3 Program and Erase Command Execution The FCDIV register must be initialized after any reset and any error flag is cleared before beginning command execution. The command execution steps are: 1. WriteadatavaluetoanaddressintheFlashorEEPROMarray.Theaddressanddatainformation fromthiswriteislatchedintotheFlashandEEPROMinterface.Thiswriteisarequiredfirststep in any command sequence. For erase and blank check commands, the value of the data is not important. For sector erase commands, the address can be any address in the sector ofFlash or EEPROMtobeerased.Formasseraseandblankcheckcommands,theaddresscanbeanyaddress in theFlash or EEPROM memory.Flash and EEPROM erase independently of each other. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 53

Chapter4 Memory NOTE BeforeprogrammingaparticularbyteintheFlashorEEPROM,thesector inwhichthatparticularbyteresidesmustbeerasedbyamassorsectorerase operation.Reprogrammingbitsinanalreadyprogrammedbytewithoutfirst performing an erase operation may disturb data stored in theFlash or EEPROM memory. 2. Write the command code for the desired command to FCMD. The six valid commands are blank check(0x05),byteprogram(0x20),burstprogram(0x25),sectorerase(0x40),masserase1(0x41), and sector erase abort (0x47). The command code is latched into the command buffer. 3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its address and data information). Apartialcommandsequencecanbeabortedmanuallybywritinga0toFCBEFanytimeafterthe writetothememoryarrayandbeforewritingthe1thatclearsFCBEFandlaunchesthecomplete command. Aborting a command in this way sets the FACCERR access error flag which must be cleared before starting a new command. A strictly monitored procedure must be obeyed or the command will not be accepted. This minimizes the possibility of any unintended changes to the memory contents. The command complete flag (FCCF) indicates when a command is complete. The command sequence must be completedbyclearingFCBEFtolaunchthecommand.Figure4-2isaflowchartforexecutingall of the commands except for burst programming and sector erase abort. 4. Wait until the FCCF bit in FSTAT is set. As soon as FCCF= 1, the operation has completed successfully. 1.A mass erase is possible only when theFlash block is fully unprotected. MC9S08DZ60 Series Data Sheet, Rev. 4 54 Freescale Semiconductor

Chapter4 Memory WRITE TO FCDIV(1) (1) Required only once after reset. PROGRAM AND START ERASE FLOW 0 FACCERR? CLEAR ERROR WRITE TO FLASH OR EEPROM TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF (2) Wait at least four bus cycles TO LAUNCH COMMAND before checking FCBEF or FCCF. AND CLEAR FCBEF(2) YES FPVIOL OR ERROR EXIT FACCERR? NO 0 FCCF? 1 DONE Figure4-2. Program and Erase Flowchart 4.5.4 Burst Program Execution The burst program command is used to program sequential bytes of data in less time than would be requiredusingthestandardprogramcommand.ThisispossiblebecausethehighvoltagetotheFlasharray doesnotneedtobedisabledbetweenprogramoperations.Ordinarily,whenaprogramorerasecommand is issued, an internal charge pump associated with theFlash memory must be enabled to supply high voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst programcommandisissued,thechargepumpisenabledandremainsenabledaftercompletionoftheburst program operation if these two conditions are met: • The next burst program commandsequence has begun before the FCCF bit is set. • The next sequential address selects a byte on the same burst block as the current byte being programmed. A burst block in thisFlash memory consists of 32 bytes. A new burst block begins at each 32-byte address boundary. The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 55

Chapter4 Memory programtimeprovidedthattheconditionsabovearemet.Ifthenextsequentialaddressisthebeginningof anewrow,theprogramtimeforthatbytewillbethestandardtimeinsteadofthebursttime.Thisisbecause thehighvoltagetothearraymustbedisabledandthenenabledagain.Ifanewburstcommandhasnotbeen queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. A flowchart to execute the burst program operation is shown inFigure4-3. WRITE TO FCDIV(1) (1) Required only once after reset. BURST PROGRAM START FLOW 0 FACCERR? 1 CLEAR ERROR 0 FCBEF? 1 WRITE TOFlash TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF (2) Wait at least four bus cycles TO LAUNCH COMMAND before checking FCBEF or FCCF. AND CLEAR FCBEF(2) YES FPVIOL OR ERROR EXIT FACCERR? NO YES NEW BURST COMMAND? NO 0 FCCF? 1 DONE Figure4-3. Burst Program Flowchart MC9S08DZ60 Series Data Sheet, Rev. 4 56 Freescale Semiconductor

Chapter4 Memory 4.5.5 Sector Erase Abort The sector erase abort operation will terminate the active sector erase operation so that other sectors are available for read and program operations without waiting for the sector erase operation to complete. The sector erase abort command write sequence is as follows: 1. Write to anyFlash or EEPROM address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, 0x47, to the FCMD register. 3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the sector erase abort command. If the sector erase abort command is launched resulting in the early termination of an active sector erase operation,theFACCERRflagwillsetoncetheoperationcompletesasindicatedbytheFCCFflagbeing set. The FACCERR flag sets to inform the user that theFlash sector may not be fully erased and a new sector erase command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase operation completes normally, theFACCERRflagwillnotsetuponcompletionoftheoperationasindicatedbytheFCCFflagbeingset. Therefore, if the FACCERR flag is not set after the sector erase abort command has completed, a sector being erased when the abort command was launched will be fully erased. A flowchart to execute the sector erase abort operation is shown inFigure4-4. SECTOR ERASE START ABORT FLOW 1 FCCF? 0 WRITE TOFlash TO BUFFER ADDRESS AND DATA WRITE 0x47 TO FCMD WRITE 1 TO FCBEF (2) Wait at least four bus cycles TO LAUNCH COMMAND before checking FCBEF or FCCF. AND CLEAR FCBEF(2) 0 FCCF? 1 0 SECTOR ERASE COMPLETED FACCERR? 1 SECTOR ERASE ABORTED Figure4-4. Sector Erase Abort Flowchart MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 57

Chapter4 Memory NOTE TheFCBEFflagwillnotsetafterlaunchingthesectoreraseabortcommand. Ifanattemptismadetostartanewcommandwritesequencewithasector eraseabortoperationactive,theFACCERRflagintheFSTATregisterwill be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. 4.5.6 Access Errors An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERRmustbeclearedbywritinga1toFACCERRinFSTATbeforeanycommandcanbeprocessed. • WritingtoaFlashaddressbeforetheinternalFlashandEEPROMclockfrequencyhasbeensetby writing to the FCDIV register. • Writing to aFlash address while FCBEF is not set. (A new command cannot be started until the command buffer is empty.) • Writing a second time to aFlash address before launching the previous command. (There is only one write toFlash for every command.) • WritingasecondtimetoFCMDbeforelaunchingthepreviouscommand.(Thereisonlyonewrite to FCMD for every command.) • Writing to anyFlash control register other than FCMD after writing to aFlash address. • Writing any command code other than the six allowed codes (0x05, 0x20, 0x25, 0x40, 0x41, or 0x47) to FCMD. • Writing anyFlash control register other than to write to FSTAT (to clear FCBEF and launch the command) after writing the command to FCMD. • The MCU enters stop mode while a program or erase command is in progress. (The command is aborted.) • Writingthebyteprogram,burstprogram,sectoreraseorsectoreraseabortcommandcode(0x20, 0x25, 0x40, or 0x47) with a background debug command while the MCU is secured. (The background debug controller can do blank check and mass erase commands only when the MCU is secure.) • Writing 0 to FCBEF to cancel a partial command. MC9S08DZ60 Series Data Sheet, Rev. 4 58 Freescale Semiconductor

Chapter4 Memory 4.5.7 Block Protection The block protection feature prevents the protected region ofFlash or EEPROM from program or erase changes.BlockprotectioniscontrolledthroughtheFlashandEEPROMprotectionregister(FPROT).The EPS bits determine the protected region of EEPROM and the FPS bits determine the protected region of Flash. See Section 4.5.11.4, “Flash and EEPROM Protection Register (FPROT and NVPROT).” After exit from reset, FPROT is loaded with the contents of the NVPROT location, which is in the nonvolatileregisterblockoftheFlashmemory.AnyFPROTwritethatattemptstodecreasethesizeofthe protected region will be ignored. Because NVPROT is within the last sector ofFlash, if any amount of memory is protected, NVPROT is itself protected and cannot be unprotected (intentionally or unintentionally) by the application software. FPROT can be written through background debug commands, which provides a way to erase and reprogram protectedFlash memory. One use for block protection is to block protect an area ofFlash memory for a bootloader program. this bootloaderprogramcancallaroutineoutsideofFlashthatcanbeusedtosectorerasetherestoftheFlash memory and reprogram it. The bootloader is protected even if MCU power is lost during an erase and reprogram operation. 4.5.8 Vector Redirection While anyFlash is block protected, the reset and interrupt vectors will be protected. Vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register located at address 0xFFBF to 0. For redirection to occur, at least some portion of theFlash memory must be block protected by programming the NVPROT register located at address 0xFFBD. All interrupt vectors (memory locations 0xFFC0–0xFFFD) are redirected, though the reset vector (0xFFFE:0xFFFF) is not. For example, if 1536 bytes ofFlash are protected, the protected address region is from 0xFA00 through 0xFFFF. The interrupt vectors (0xFFC0–0xFFFD) are redirected to the locations 0xF9C0–0xF9FD. If vectorredirectionisenabledandaninterruptoccurs,thevaluesinthelocations0xF9E0:0xF9E1areused forthevectorinsteadofthevaluesinthelocations0xFFE0:0xFFE1.Thisallowstheusertoreprogramthe unprotected portion of theFlash with new program code including new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged. 4.5.9 Security The MC9S08DZ60 Series includes circuitry to prevent unauthorized access to the contents ofFlash, EEPROM, and RAM memory. When security is engaged,Flash, EEPROM, and RAM are considered secure resources. Direct-page registers, high-page registers, and the background debug controller are considered unsecured resources. Programs executing within secure memory have normal access to any MCU memory locations and resources. Attempts to access a secure memory location with a program executingfromanunsecuredmemoryspaceorthroughthebackgrounddebuginterfaceareblocked(writes are ignored and reads return all 0s). Securityisengagedordisengagedbasedonthestateoftworegisterbits(SEC[1:0])intheFOPTregister. During reset, the contents of the nonvolatile location NVOPT are copied fromFlash into the working FOPTregisterinhigh-pageregisterspace.AuserengagessecuritybyprogrammingtheNVOPTlocation, MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 59

Chapter4 Memory which can be performed at the same time theFlash memory is programmed. The 1:0 state disengages security; the other three combinations engage security. Notice the erased state (1:1) makes the MCU secure.Duringdevelopment,whenevertheFlashiserased,itisgoodpracticetoimmediatelyprogramthe SEC0bitto0inNVOPTsoSEC=1:0.ThiswouldallowtheMCUtoremainunsecuredafterasubsequent reset. The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug controller can be used for background memory access commands, but the MCU cannot enter active background mode except by holding BKGD low at the rising edge of reset. A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor securitykey.IfthenonvolatileKEYENbitinNVOPT/FOPTis0,thebackdoorkeyisdisabledandthere is no way to disengage security without completely erasing allFlash locations. If KEYEN is 1, a secure user program can temporarily disengage security by: 1. Writing1toKEYACCintheFCNFGregister.ThismakestheFlashmoduleinterpretwritestothe backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the first step in aFlash program or erase command. 2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations. These writes must be performed in order starting with the value for NVBACKKEY and ending with NVBACKKEY+7. STHX must not be used for these writes because these writes cannot be performed on adjacent bus cycles. User software normally would get the key codes from outside the MCU system through a communication interface such as a serial I/O. 3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was written matches the key stored in theFlash locations, SEC bits are automatically changed to 1:0 and security will be disengaged until the next reset. Thesecuritykeycanbewrittenonlyfromsecurememory(eitherRAM,EEPROM,orFlash),soitcannot be entered through background commands without the cooperation of a secure user program. The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located inFlash memory locations in the nonvolatile register space so users can program these locations exactly as they would program any otherFlash memory location. The nonvolatile registers are in the same 768-byte block of Flash as the reset and interrupt vectors, so block protecting that space also block protects the backdoor comparisonkey.Blockprotectscannotbechangedfromuserapplicationprograms,soifthevectorspace is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key. Security can always be disengaged through the background debug interface by taking these steps: 1. Disable any block protections by writing FPROT. FPROT can be written only with background debug commands, not from application software. 2. Mass eraseFlash if necessary. 3. BlankcheckFlash.ProvidedFlashiscompletelyerased,securityisdisengageduntilthenextreset. To avoid returning to secure mode after the next reset, program NVOPT so SEC=1:0. MC9S08DZ60 Series Data Sheet, Rev. 4 60 Freescale Semiconductor

Chapter4 Memory 4.5.10 EEPROM Mapping OnlyhalfoftheEEPROMisinthememorymap.TheEPGSELbitinFCNFGregisterselectswhichhalf ofthearraycanbeaccessedinforegroundwhiletheotherhalfcannotbeaccessedinbackground.There aretwomappingmodeoptionsthatcanbeselectedtoconfigurethe8-byteEEPROMsectors:4-bytemode and 8-byte mode. Each mode is selected by the EPGMOD bit in the FOPT register. In4-bytesectormode(EPGMOD=0),each8-bytesectorsplitsfourbytesonforegroundandfourbytes on background but on the same addresses. The EPGSEL bit selects which four bytes can be accessed. During a sector erase, the entire 8-byte sector (four bytes in foreground and four bytes in background) is erased. In 8-byte sector mode (EPGMOD = 1), each entire 8-byte sector is in a single page. The EPGSEL bit selects which sectors are on background. During a sector erase, the entire 8-byte sector in foreground is erased. 4.5.11 Flash and EEPROM Registers and Control Bits TheFlash and EEPROM modules have seven 8-bit registers in the high-page register space and three locations in the nonvolatile register space inFlash memory. Two of those locations are copied into two corresponding high-page control registers at reset. There is also an 8-byte comparison key inFlash memory.RefertoTable4-3andTable4-5fortheabsoluteaddressassignmentsforallFlashandEEPROM registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 4.5.11.1 Flash and EEPROM Clock Divider Register (FCDIV) Bit7ofthisregisterisaread-onlyflag.Bits6:0maybereadatanytimebutcanbewrittenonlyonetime. Beforeanyeraseorprogrammingoperationsarepossible,writetothisregistertosetthefrequencyofthe clock for the nonvolatile memory system within acceptable limits. 7 6 5 4 3 2 1 0 R DIVLD PRDIV8 DIV W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure4-5.Flash and EEPROM Clock Divider Register (FCDIV) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 61

Chapter4 Memory Table4-7. FCDIV Register Field Descriptions Field Description 7 DivisorLoadedStatusFlag—Whenset,thisread-onlystatusflagindicatesthattheFCDIVregisterhasbeen DIVLD writtensincereset.Resetclearsthisbitandthefirstwritetothisregistercausesthisbittobecomesetregardless of the data written. 0 FCDIV has not been written since reset; erase and program operations disabled forFlash and EEPROM. 1 FCDIV has been written since reset; erase and program operations enabled forFlash and EEPROM. 6 Prescale (Divide)Flash and EEPROM Clock by 8 (This bit is write once.) PRDIV8 0 Clock input to theFlash and EEPROM clock divider is the bus rate clock. 1 Clock input to theFlash and EEPROM clock divider is the bus rate clock divided by8. 5:0 Divisor forFlash and EEPROM Clock Divider —These bits are write once.TheFlash and EEPROM clock DIV dividerdividesthebusrateclock(orthebusrateclockdividedby8ifPRDIV8=1)bythevalueinthe6-bitDIV field plus one. The resulting frequency of the internalFlash and EEPROM clock must fall within the range of 200kHz to 150kHz for properFlash and EEPROM operations. Program/Erase timing pulses are one cycle of this internalFlash and EEPROM clock which corresponds to a range of 5μs to 6.7μs. The automated programming logic uses an integer number of these pulses to complete an erase or program operation. See Equation4-1 andEquation4-2. if PRDIV8=0 — f = f ÷ (DIV + 1) Eqn.4-1 FCLK Bus if PRDIV8=1 — f = f ÷ (8× (DIV + 1)) Eqn.4-2 FCLK Bus Table4-8 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies. Table4-8.Flash and EEPROM Clock Divider Settings PRDIV8 DIV Program/Erase Timing Pulse f f Bus (Binary) (Decimal) FCLK (5μs Min, 6.7 μs Max) 20 MHz 1 12 192.3 kHz 5.2μs 10 MHz 0 49 200 kHz 5μs 8 MHz 0 39 200 kHz 5μs 4 MHz 0 19 200 kHz 5μs 2 MHz 0 9 200 kHz 5μs 1 MHz 0 4 200 kHz 5μs 200 kHz 0 0 200 kHz 5μs 150 kHz 0 0 150 kHz 6.7μs 4.5.11.2 Flash and EEPROM Options Register (FOPT and NVOPT) Duringreset,thecontentsofthenonvolatilelocationNVOPTarecopiedfromFlashintoFOPT.Tochange thevalueinthisregister,eraseandreprogramtheNVOPTlocationinFlashmemoryasusualandthenissue a new MCU reset. MC9S08DZ60 Series Data Sheet, Rev. 4 62 Freescale Semiconductor

Chapter4 Memory 7 6 5 4 3 2 1 0 R KEYEN FNORED EPGMOD 0 0 0 SEC W Reset F F F 0 0 0 F F = Unimplemented or Reserved F = loaded from nonvolatile location NVOPT during reset Figure4-6.Flash and EEPROM Options Register (FOPT) Table4-9. FOPT Register Field Descriptions Field Description 7 Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to KEYEN disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM commandscannotbeusedtowritekeycomparisonvaluesthatwouldunlockthebackdoorkey.Formoredetailed information about the backdoor key mechanism, refer toSection 4.5.9, “Security.” 0 No backdoor key access allowed. 1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through NVBACKKEY+7 in that order), security is temporarily disengaged until the next MCU reset. 6 Vector Redirection Disable — When this bit is 1, then vector redirection is disabled. FNORED 0 Vector redirection enabled. 1 Vector redirection disabled. 5 EEPROMSectorMode—Whenthisbitis0,eachsectorissplitintotwopages(4-bytemode).Whenthisbitis EPGMOD 1, each sector is in a single page (8-byte mode). 0 Half of each EEPROM sector is in Page 0 and the other half is in Page 1. 1 Each sector is in a single page. 1:0 SecurityStateCode—This2-bitfielddeterminesthesecuritystateoftheMCUasshowninTable4-10.When SEC theMCUissecure,thecontentsofRAM,EEPROMandFlashmemorycannotbeaccessedbyinstructionsfrom anyunsecuredsourceincludingthebackgrounddebuginterface.SECchangesto1:0aftersuccessfulbackdoor key entry or a successful blank check ofFlash. For more detailed information about security, refer toSection 4.5.9, “Security.” Table4-10. Security States1 SEC[1:0] Description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure 1 SEC changes to 1:0 after successful backdoor key entry or a successful blank check ofFlash. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 63

Chapter4 Memory 4.5.11.3 Flash and EEPROM Configuration Register (FCNFG) 7 6 5 4 3 2 1 0 R 0 0 0 0 1 EPGSEL KEYACC Reserved1 W Reset 0 0 0 1 0 0 0 1 = Unimplemented or Reserved Figure4-7.Flash Configuration Register (FCNFG) 1 User must write a 1 to this bit. Failing to do so may result in unexpected behavior. Table4-11. FCNFG Register Field Descriptions Field Description 6 EEPROM Page Select— This bit selects which EEPROM page is accessed in the memory map. EPGSEL 0 Page 0 is in foreground of memory map. Page 1 is in background and can not be accessed. 1 Page 1 is in foreground of memory map. Page 0 is in background and can not be accessed. 5 Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed KEYACC information about the backdoor key mechanism, refer toSection 4.5.9, “Security.” 0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of aFlash programming or erase command. 1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes. 4.5.11.4 Flash and EEPROM Protection Register (FPROT and NVPROT) The FPROT register defines whichFlash and EEPROM sectors are protected against program and erase operations. During the reset sequence, the FPROT register is loaded from the nonvolatile location NVPROT. To changetheprotectionthatwillbeloadedduringtheresetsequence,thesectorcontainingNVPROTmust be unprotected and erased, then NVPROT can be reprogrammed. FPROT bits are readable at any time and writable as long as the size of the protected region is being increased.AnywritetoFPROTthatattemptstodecreasethesizeoftheprotectedmemorywillbeignored. Trying to alter data in any protected area will result in a protection violation error and the FPVIOL flag will be set in the FSTAT register. Mass erase is not possible if any one of the sectors is protected. 7 6 5 4 3 2 1 0 R EPS1 FPS1 W Reset This register is loaded from nonvolatile location NVPROT during reset. 1 Background commands can be used to change the contents of these bits in FPROT. Figure4-8.Flash and EEPROM Protection Register (FPROT) MC9S08DZ60 Series Data Sheet, Rev. 4 64 Freescale Semiconductor

Chapter4 Memory Table4-12. FPROT Register Field Descriptions Field Description 7:6 EEPROM Protect Select Bits — This 2-bit field determines the protected EEPROM locations that cannot be EPS erased or programmed. SeeTable4-13. 5:0 FlashProtectSelectBits—This6-bitfielddeterminestheprotectedFlashlocationsthatcannotbeerasedor FPS programmed. SeeTable4-14. Table4-13. EEPROM Block Protection EPS Address Area Protected Memory Size Protected (bytes) Number of Sectors Protected 0x3 N/A 0 0 0x2 0x17F0 - 0x17FF 32 4 0x1 0x17E0 - 0x17FF 64 8 0x0 0x17C0–0x17FF 128 16 Table4-14.Flash Block Protection FPS Address Area Protected Memory Size Protected (bytes) Number of Sectors Protected 0x3F N/A 0 0 0x3E 0xFA00–0xFFFF 1.5K 2 0x3D 0xF400–0xFFFF 3K 4 0x3C 0xEE00–0xFFFF 4.5K 6 0x3B 0xE800–0xFFFF 6K 8 ... ... ... ... 0x37 0xD000–0xFFFF 12K 16 0x36 0xCA00–0xFFFF 13.5K 18 0x35 0xC400–0xFFFF 15K 20 0x34 0xBE00–0xFFFF 16.5K 22 ... ... ... ... 0x2C 0x8E00–0xFFFF 28.5K 38 0x2B 0x8800–0xFFFF 30K 40 0x2A 0x8200–0xFFFF 31.5K 42 0x29 0x7C00–0xFFFF 33K 44 ... ... ... ... 0x22 0x5200–0xFFFF 43.5K 58 0x21 0x4C00–0xFFFF 45K 60 0x20 0x4600–0xFFFF 46.5K 62 0x1F 0x4000–0xFFFF 48K 64 ... ... ... ... MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 65

Chapter4 Memory Table4-14.Flash Block Protection (continued) FPS Address Area Protected Memory Size Protected (bytes) Number of Sectors Protected 0x1B 0x2800–0xFFFF 54K 72 0x1A 0x2200–0xFFFF 55.5K 74 0x19 0x1C00–0xFFFF 57K 76 0x18–0x00 0x0000–0xFFFF 64K 86 4.5.11.5 Flash and EEPROM Status Register (FSTAT) 7 6 5 4 3 2 1 0 R FCCF 0 FBLANK 0 0 FCBEF FPVIOL FACCERR W Reset 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure4-9.Flash and EEPROM Status Register (FSTAT) Table4-15. FSTAT Register Field Descriptions Field Description 7 Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the FCBEF command buffer is empty so that a new command sequence can be executed when performing burst programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. Only burst program commands can be buffered. 0 Command buffer is full (not ready for additional commands). 1 A new burst program command can be written to the command buffer. 6 CommandCompleteFlag—FCCFissetautomaticallywhenthecommandbufferisemptyandnocommand FCCF is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to register a command). Writing to FCCF has no meaning or effect. 0 Command in progress 1 All commands complete 5 ProtectionViolationFlag—FPVIOLissetautomaticallywhenacommandthatattemptstoeraseorprogram FPVIOL alocationinaprotectedblockislaunched(theerroneouscommandisignored).FPVIOLisclearedbywritinga 1 to FPVIOL. 0 No protection violation. 1 An attempt was made to erase or program a protected location. MC9S08DZ60 Series Data Sheet, Rev. 4 66 Freescale Semiconductor

Chapter4 Memory Table4-15. FSTAT Register Field Descriptions (continued) Field Description 4 AccessErrorFlag—FACCERRissetautomaticallywhenthepropercommandsequenceisnotobeyedexactly FACCERR (theerroneouscommandisignored),ifaprogramoreraseoperationisattemptedbeforetheFCDIVregisterhas beeninitialized,oriftheMCUentersstopwhileacommandwasinprogress.Foramoredetaileddiscussionof theexactactionsthatareconsideredaccesserrors,seeSection4.5.6,“AccessErrors.”FACCERRisclearedby writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect. 0 No access error. 1 An access error has occurred. 2 VerifiedasAllBlank(erased)Flag—FBLANKissetautomaticallyattheconclusionofablankcheckcommand FBLANK iftheentireFlashorEEPROMarraywasverifiedtobeerased.FBLANKisclearedbyclearingFCBEFtowritea new valid command. Writing to FBLANK has no meaning or effect. 0 AfterablankcheckcommandiscompletedandFCCF=1,FBLANK=0indicatestheFlashorEEPROMarray is not completely erased. 1 AfterablankcheckcommandiscompletedandFCCF=1,FBLANK=1indicatestheFlashorEEPROMarray is completely erased (all 0xFFFF). 4.5.11.6 Flash and EEPROM Command Register (FCMD) Only six command codes are recognized in normal user modes, as shown in Table 4-16. All other command codes are illegal and generate an access error. Refer to Section 4.5.3, “Program and Erase Command Execution,” for a detailed discussion ofFlash and EEPROM programming and erase operations. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FCMD Reset 0 0 0 0 0 0 0 0 Figure4-10.Flash and EEPROM Command Register (FCMD) Table4-16.Flash and EEPROM Commands Command FCMD Equate File Label Blank check 0x05 mBlank Byte program 0x20 mByteProg Burst program 0x25 mBurstProg Sector erase 0x40 mSectorErase Mass erase 0x41 mMassErase Sector erase abort 0x47 mEraseAbort It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 67

Chapter4 Memory MC9S08DZ60 Series Data Sheet, Rev. 4 68 Freescale Semiconductor

Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction ThissectiondiscussesbasicresetandinterruptmechanismsandtheirvarioussourcesintheMC9S08DZ60 Series. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data sheet. This section gathers basic information about all reset and interrupt sources in oneplaceforeasyreference.Afewresetandinterruptsources,includingthecomputeroperatingproperly (COP) watchdog, are not part of on-chip peripheral systems with their own chapters. 5.2 Features Reset and interrupt features include: • Multiple sources of reset for flexible system configuration and reliable operation • Reset status register (SRS) to indicate source of most recent reset • Separate interrupt vector for each module (reduces polling overhead); see Table5-1 5.3 MCU Reset ResettingtheMCUprovidesawaytostartprocessingfromaknownsetofinitialconditions.Duringreset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially configured as general-purpose high-impedance inputs with pull-up devices disabled. The I bit in the condition code register (CCR) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (SP) and system control settings. (See the CPU chapter for information on the Interrupt (I) bit.) SP is forced to 0x00FF at reset. The MC9S08DZ60 Series has eight sources for reset: • Power-on reset (POR) • External pin reset (PIN) • Computer operating properly (COP) timer • Illegal opcode detect (ILOP) • Illegal address detect (ILAD) • Low-voltage detect (LVD) • Loss of clock (LOC) • Background debug forced reset (BDFR) Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS). MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 69

Chapter5 Resets, Interrupts, and General System Control 5.4 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must resettheCOPcounterperiodically.IftheapplicationprogramgetslostandfailstoresettheCOPcounter before it times out, a system reset is generated to force the system back to a known starting point. After any reset, the COP watchdog is enabled (see Section 5.8.4, “System Options Register 1 (SOPT1),” for additional information). If the COP watchdog is not used in an application, it can be disabled by clearing COPT bits in SOPT1. The COP counter is reset by writing 0x55 and 0xAA (in this order) to the address of SRS during the selectedtimeoutperiod.Writesdonotaffectthedataintheread-onlySRS.Assoonasthewritesequence isdone,theCOPtimeoutperiodisrestarted.Iftheprogramfailstodothisduringthetime-outperiod,the MCU will reset. Also, if any value other than 0x55 or 0xAA is written to SRS, the MCU is immediately reset. The COPCLKS bit in SOPT2 (seeSection 5.8.5, “System Options Register 2 (SOPT2),” for additional information)selectstheclocksourceusedfortheCOPtimer.Theclocksourceoptionsareeitherthebus clock or an internal 1-kHz clock source. With each clock source, there are three associated time-outs controlledbytheCOPTbitsinSOPT1.Table5-6summariesthecontrolfunctionsoftheCOPCLKSand COPTbits.TheCOPwatchdogdefaultstooperationfromthe1-kHzclocksourceandthelongesttime-out (210 cycles). When the bus clock source is selected, windowed COP operation is available by setting COPW in the SOPT2register.Inthismode,writestotheSRSregistertocleartheCOPtimermustoccurinthelast25% of the selected timeout period. A premature write immediately resets the MCU. When the 1-kHz clock source is selected, windowed COP operation is not available. TheCOPcounterisinitializedbythefirstwritestotheSOPT1andSOPT2registersandafteranysystem reset. Subsequent writes to SOPT1 and SOPT2 have no effect on COP operation. Even if the application will use the reset default settings of COPT, COPCLKS, and COPW bits, the user should write to the write-onceSOPT1andSOPT2registersduringresetinitializationtolockinthesettings.Thiswillprevent accidental changes if the application program gets lost. ThewritetoSRSthatservices(clears)theCOPcountershouldnotbeplacedinaninterruptserviceroutine (ISR) because the ISR could continue to be executed periodically even if the main application program fails. Ifthebusclocksourceisselected,theCOPcounterdoesnotincrementwhiletheMCUisinbackground debug mode or while the system is in stop mode. The COP counter resumes when the MCU exits background debug mode or stop mode. If the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either background debug mode or stop mode and begins from zero upon exit from background debug mode or stop mode. MC9S08DZ60 Series Data Sheet, Rev. 4 70 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control 5.5 Interrupts InterruptsprovideawaytosavethecurrentCPUstatusandregisters,executeaninterruptserviceroutine (ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other thanthesoftwareinterrupt(SWI),whichisaprograminstruction,interruptsarecausedbyhardwareevents such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI under certain circumstances. Ifaneventoccursinanenabledinterruptsource,anassociatedread-onlystatusflagwillbecomeset.The CPUwillnotrespondunlessthelocalinterruptenableisa1toenabletheinterruptandtheIbitintheCCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which preventsallmaskableinterruptsources.Theuserprograminitializesthestackpointerandperformsother system setup before clearing the I bit to allow the CPU to respond to interrupts. WhentheCPUreceivesaqualifiedinterruptrequest,itcompletesthecurrentinstructionbeforeresponding totheinterrupt.Theinterruptsequenceobeysthesamecycle-by-cyclesequenceastheSWIinstructionand consists of: • Saving the CPU registers on the stack • Setting the I bit in the CCR to mask further interrupts • Fetching the interrupt vector for the highest-priority interrupt that is currently pending • Filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations WhiletheCPUisrespondingtotheinterrupt,theIbitisautomaticallysettoavoidthepossibilityofanother interruptinterruptingtheISRitself(thisiscallednestingofinterrupts).Normally,theIbitisrestoredto0 whentheCCRisrestoredfromthevaluestackedonentrytotheISR.Inrarecases,theIbitcanbecleared inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be servicedwithoutwaitingforthefirstserviceroutinetofinish.Thispracticeisnotrecommendedforanyone otherthanthemostexperiencedprogrammersbecauseitcanleadtosubtleprogramerrorsthataredifficult to debug. Theinterruptserviceroutineendswithareturn-from-interrupt(RTI)instructionwhichrestorestheCCR, A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the stack. NOTE For compatibility with M68HC08 devices, the H register is not automatically saved and restored. It is good programming practice to push Hontothestackatthestartoftheinterruptserviceroutine(ISR)andrestore it immediately before the RTI that is used to return from the ISR. IfmorethanoneinterruptispendingwhentheIbitiscleared,thehighestprioritysourceisservicedfirst (seeTable5-1). MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 71

Chapter5 Resets, Interrupts, and General System Control 5.5.1 Interrupt Stack Frame Figure5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP)pointsatthenextavailablebytelocationonthestack.ThecurrentvaluesofCPUregistersarestored onthestackstartingwiththelow-orderbyteoftheprogramcounter(PCL)andendingwiththeCCR.After stacking,theSPpointsatthenextavailablelocationonthestackwhichistheaddressthatisonelessthan theaddresswheretheCCRwassaved.ThePCvaluethatisstackedistheaddressoftheinstructioninthe main program that would have executed next if the interrupt had not occurred. UNSTACKING TOWARD LOWER ADDRESSES ORDER 7 0 SP AFTER INTERRUPT STACKING 5 1 CONDITION CODE REGISTER 4 2 ACCUMULATOR 3 3 INDEX REGISTER (LOW BYTE X)* 2 4 PROGRAM COUNTER HIGH SP BEFORE 1 5 PROGRAM COUNTER LOW THE INTERRUPT STACKING TOWARD HIGHER ADDRESSES ORDER * High byte (H) of index register is not automatically stacked. Figure5-1. Interrupt Stack Frame WhenanRTIinstructionisexecuted,thesevaluesarerecoveredfromthestackinreverseorder.Aspartof the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information, starting from the PC address recovered from the stack. The status flag corresponding to the interrupt source must be acknowledged (cleared) before returning from the ISR. Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is generatedbythissamesource,itwillberegisteredsoitcanbeservicedaftercompletionofthecurrentISR. 5.5.2 External Interrupt Request (IRQ) Pin ExternalinterruptsaremanagedbytheIRQstatusandcontrolregister,IRQSC.WhentheIRQfunctionis enabled,synchronouslogicmonitorsthepinforedge-onlyoredge-and-levelevents.WhentheMCUisin stopmodeandsystemclocksareshutdown,aseparateasynchronouspathisusedsotheIRQ(ifenabled) can wake the MCU. 5.5.2.1 Pin Configuration Options TheIRQpinenable(IRQPE)controlbitinIRQSCmustbe1inorderfortheIRQpintoactastheinterrupt request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event causes an interrupt or only sets the IRQF flag which can be polled by software. MC9S08DZ60 Series Data Sheet, Rev. 4 72 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control TheIRQpin,whenenabled,defaultstouseaninternalpulldevice(IRQPDD=0),thedeviceisapull-up orpull-downdependingonthepolaritychosen.Iftheuserdesirestouseanexternalpull-uporpull-down, the IRQPDD can be written to a 1 to turn off the internal device. BIHandBILinstructionsmaybeusedtodetectthelevelontheIRQpinwhenthepinisconfiguredtoact as the IRQ input. 5.5.2.2 Edge and Level Sensitivity The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In the edgeandleveldetectionmode,theIRQFstatusflagbecomessetwhenanedgeisdetected(whentheIRQ pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the IRQ pin remains at the asserted level. 5.5.3 Interrupt Vectors, Sources, and Local Masks Table5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the bottom of the table. The high-order byte of the address for the interrupt service routine is located at the first address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address. When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 73

Chapter5 Resets, Interrupts, and General System Control Table5-1. Vector Summary1 Vector Address Vector Module Source Enable Description No. (High/Low) Name 31 0xFFC0/0xFFC1 Vacmp2 ACMP2 ACF ACIE Analog comparator 2 30 0xFFC2/0xFFC3 Vacmp1 ACMP1 ACF ACIE Analog comparator 1 29 0xFFC4/0xFFC5 Vcantx MSCAN TXE[2:0] TXEIE[2:0] CAN transmit 28 0xFFC6/0xFFC7 Vcanrx MSCAN RXF RXFIE CAN receive 27 0xFFC8/0xFFC9 Vcanerr MSCAN CSCIF, OVRIF CSCIE, OVRIE CAN errors 26 0xFFCA/0xFFCB Vcanwu MSCAN WUPIF WUPIE CAN wake-up 25 0xFFCC/0xFFCD Vrtc RTC RTIF RTIE Real-time interrupt 24 0xFFCE/0xFFCF Viic IIC IICIS IICIE IIC control 23 0xFFD0/0xFFD1 Vadc ADC COCO AIEN ADC 22 0xFFD2/0xFFD3 Vport Port A,B,D PTAIF, PTBIF, PTAIE,PTBIE,PTDIE Port Pins PTDIF 21 0xFFD4/0xFFD5 Vsci2tx SCI2 TDRE, TC TIE, TCIE SCI2 transmit 20 0xFFD6/0xFFD7 Vsci2rx SCI2 IDLE, LBKDIF, ILIE, LBKDIE, RIE, SCI2 receive RDRF,RXEDGIF RXEDGIE 19 0xFFD8/0xFFD9 Vsci2err SCI2 OR, NF ORIE, NFIE, SCI2 error FE, PF FEIE, PFIE 18 0xFFDA/0xFFDB Vsci1tx SCI1 TDRE, TC TIE, TCIE SCI1 transmit 17 0xFFDC/0xFFDD Vsci1rx SCI1 IDLE, LBKDIF, ILIE, LBKDIE, RIE, SCI1 receive RDRF,RXEDGIF RXEDGIE 16 0xFFDE/0xFFDF Vsci1err SCI1 OR, NF, ORIE, NFIE, SCI1 error FE, PF FEIE, PFIE 15 0xFFE0/0xFFE1 Vspi SPI SPIF, MODF, SPIE, SPIE, SPTIE SPI SPTEF 14 0xFFE2/0xFFE3 Vtpm2ovf TPM2 TOF TOIE TPM2 overflow 13 0xFFE4/0xFFE5 Vtpm2ch1 TPM2 CH1F CH1IE TPM2 channel 1 12 0xFFE6/0xFFE7 Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0 11 0xFFE8/0xFFE9 Vtpm1ovf TPM1 TOF TOIE TPM1 overflow 10 0xFFEA/0xFFEB Vtpm1ch5 TPM1 CH5F CH5IE TPM1 channel 5 9 0xFFEC/0xFFED Vtpm1ch4 TPM1 CH4F CH4IE TPM1 channel 4 8 0xFFEE/0xFFEF Vtpm1ch3 TPM1 CH3F CH3IE TPM1 channel 3 7 0xFFF0/0xFFF1 Vtpm1ch2 TPM1 CH2F CH2IE TPM1 channel 2 6 0xFFF2/0xFFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1 5 0xFFF4/0xFFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0 4 0xFFF6/0xFFF7 Vlol MCG LOLS LOLIE MCG loss of lock 3 0xFFF8/0xFFF9 Vlvd System LVWF LVWIE Low-voltage warning control 2 0xFFFA/0xFFFB Virq IRQ IRQF IRQIE IRQ pin 1 0xFFFC/0xFFFD Vswi Core SWI Instruction — Software interrupt 0 0xFFFE/0xFFFF Vreset System COP, COPE Watchdog timer control LOC, CME Loss-of-clock LVD, LVDRE Low-voltage detect RESET, — External pin ILOP, — Illegal opcode ILAD, — Illegal address POR, — Power-on-reset BDFR — BDM-forced reset 1 Vector priority is shown from lowest (first row) to highest (last row). For example, Vreset is the highest priority vector. MC9S08DZ60 Series Data Sheet, Rev. 4 74 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control 5.6 Low-Voltage Detect (LVD) System The MC9S08DZ60 Series includes a system to protect against low-voltage conditions in order to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and detection. The LVD circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon enteringanyofthestopmodesunlessLVDSEissetinSPMSC1.IfLVDSEandLVDEarebothset,then the MCU cannot enter stop2 (it will enter stop3 instead), and the current consumption in stop3 with the LVD enabled will be higher. 5.6.1 Power-On Reset Operation When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset rearm voltage level, V , the POR circuit will cause a reset condition. As the supply voltage rises, the POR LVD circuit will hold the MCU in reset until the supply has risen above the low-voltage detection low threshold, V . Both the POR bit and the LVD bit in SRS are set following a POR. LVDL 5.6.2 Low-Voltage Detection (LVD) Reset Operation The LVD can be configured to generate a reset upon detection of a low-voltage condition by setting LVDREto1.Thelow-voltagedetectionthresholdisdeterminedbytheLVDVbit.AfteranLVDresethas occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the low-voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or POR. 5.6.3 Low-Voltage Warning (LVW) Interrupt Operation The LVD system has a low-voltage warning flag to indicate to the user that the supply voltage is approaching the low-voltage condition. When a low-voltage warning condition is detected and is configuredforinterruptoperation(LVWIEsetto1),LVWFinSPMSC1willbesetandanLVWinterrupt request will occur. 5.7 MCLK Output ThePTA0pinissharedwiththeMCLKclockoutput.IftheMCSELbitsareallzeroes,theMCLKclock isdisabled.SettinganyoftheMCSELbitscausesthePTA0pintooutputadividedversionoftheinternal MCUbusclockregardlessofthestateoftheportdatadirectioncontrolbitforthepin.Thedivideratiois determinedbytheMCSELbits.TheslewrateanddrivestrengthforthepinarecontrolledbyPTASE0and PTADS0,respectively.Themaximumclockoutputfrequencyislimitedifslewratecontrolisenabled,see the electrical specifications for the maximum frequency under different conditions. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 75

Chapter5 Resets, Interrupts, and General System Control 5.8 Reset, Interrupt, and System Control Registers and Control Bits One8-bitregisterinthedirectpageregisterspaceandeight8-bitregistersinthehigh-pageregisterspace are related to reset and interrupt systems. Refer toTable4-2 andTable4-3 inChapter4, “Memory,” of this data sheet for the absolute address assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. SomecontrolbitsintheSOPT1andSPMSC2registersarerelatedtomodesofoperation.Althoughbrief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter3, “Modes of Operation.” MC9S08DZ60 Series Data Sheet, Rev. 4 76 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) This direct page register includes status and control bits which are used to configure the IRQ function, report status, and acknowledge IRQ events. 7 6 5 4 3 2 1 0 R 0 IRQF 0 IRQPDD IRQEDG IRQPE IRQIE IRQMOD W IRQACK Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure5-2. Interrupt Request Status and Control Register (IRQSC) Table5-2. IRQSC Register Field Descriptions Field Description 6 Interrupt Request (IRQ) Pull Device Disable— This read/write control bit is used to disable the internal IRQPDD pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used. 0 IRQ pull device enabled if IRQPE = 1. 1 IRQ pull device disabled if IRQPE = 1. 5 Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or IRQEDG levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is sensitivetobothedgesandlevelsoronlyedges.WhentheIRQpinisenabledastheIRQinputandisconfigured to detect rising edges, it has a pull-down. When the IRQ pin is enabled as the IRQ input and is configured to detect falling edges, it has a pull-up. 0 IRQ is falling edge or falling edge/low-level sensitive. 1 IRQ is rising edge or rising edge/high-level sensitive. 4 IRQPinEnable—Thisread/writecontrolbitenablestheIRQpinfunction.WhenthisbitissettheIRQpincan IRQPE be used as an interrupt request. 0 IRQ pin function is disabled. 1 IRQ pin function is enabled. 3 IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred. IRQF 0 No IRQ request. 1 IRQ event detected. 2 IRQAcknowledge—Thiswrite-onlybitisusedtoacknowledgeinterruptrequestevents(write1toclearIRQF). IRQACK Writing0hasnomeaningoreffect.Readsalwaysreturn0.Ifedge-and-leveldetectionisselected(IRQMOD=1), IRQF cannot be cleared while the IRQ pin remains at its asserted level. 1 IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt IRQIE request. 0 Interrupt request when IRQF set is disabled (use polling). 1 Interrupt requested whenever IRQF=1. 0 IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level IRQMOD detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. SeeSection 5.5.2.2, “Edge and Level Sensitivity” for more details. 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 77

Chapter5 Resets, Interrupts, and General System Control 5.8.2 System Reset Status Register (SRS) Thishighpageregisterincludesread-onlystatusflagstoindicatethesourceofthemostrecentreset.When adebughostforcesresetbywriting1toBDFRintheSBDFRregister,noneofthestatusbitsinSRSwill beset.WritinganyvaluetothisregisteraddresscausesaCOPresetwhentheCOPisenabledexceptthe values 0x55 and 0xAA. Writing a 0x55-0xAA sequence to this address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset. 7 6 5 4 3 2 1 0 R POR PIN COP ILOP ILAD LOC LVD 0 W Writing 0x55, 0xAA to SRS address clears COP watchdog timer. POR: 1 0 0 0 0 0 1 0 LVD: u 0 0 0 0 0 1 0 Any other 0 Note(1) Note(1) Note(1) Note(1) 0 0 0 reset: 1 Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset entry will be cleared. Figure5-3. System Reset Status (SRS) Table5-3. SRS Register Field Descriptions Field Description 7 Power-OnReset—Resetwascausedbythepower-ondetectionlogic.Becausetheinternalsupplyvoltagewas POR rampingupatthetime,thelow-voltagereset(LVD)statusbitisalsosettoindicatethattheresetoccurredwhile the internal supply was below the LVD threshold. 0 Reset not caused by POR. 1 POR caused reset. 6 External Reset Pin — Reset was caused by an active-low level on the external reset pin. PIN 0 Reset not caused by external reset pin. 1 Reset came from external reset pin. 5 ComputerOperatingProperly(COP)Watchdog—ResetwascausedbytheCOPwatchdogtimertimingout. COP This reset source can be blocked by COPE=0. 0 Reset not caused by COP timeout. 1 Reset caused by COP timeout. 4 IllegalOpcode—Resetwascausedbyanattempttoexecuteanunimplementedorillegalopcode.TheSTOP ILOP instructionisconsideredillegalifstopisdisabledbySTOPE=0intheSOPTregister.TheBGNDinstructionis considered illegal if active background mode is disabled by ENBDM=0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode. 3 IllegalAddress—Resetwascausedbyanattempttoaccesseitherdataoraninstructionatanunimplemented ILAD memory address. 0 Reset not caused by an illegal address. 1 Reset caused by an illegal address. MC9S08DZ60 Series Data Sheet, Rev. 4 78 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control Table5-3. SRS Register Field Descriptions Field Description 2 Loss of Clock — Reset was caused by a loss of external clock. LOC 0 Reset not caused by loss of external clock 1 Reset caused by loss of external clock 1 Low-VoltageDetect—IftheLVDREbitissetandthesupplydropsbelowtheLVDtripvoltage,anLVDresetwill LVD occur. This bit is also set by POR. 0 Reset not caused by LVD trip or POR. 1 Reset caused by LVD trip or POR. 5.8.3 System Background Debug Force Reset Register (SBDFR) This high page register contains a single write-only control bit. A serial background command such as WRITE_BYTEmustbeusedtowritetoSBDFR.Attemptstowritethisregisterfromauserprogramare ignored. Reads always return 0x00. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W BDFR1 Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background debug commands, not from user programs. Figure5-4. System Background Debug Force Reset Register (SBDFR) Table5-4. SBDFR Register Field Descriptions Field Description 0 BackgroundDebugForceReset—AserialbackgroundcommandsuchasWRITE_BYTEcanbeusedtoallow BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 79

Chapter5 Resets, Interrupts, and General System Control 5.8.4 System Options Register 1 (SOPT1) Thishighpageregisterisawrite-onceregistersoonlythefirstwriteafterresetishonored.Itcanberead at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to avoidaccidentalchangestothesesensitivesettings.Thisregistershouldbewrittenduringtheuser’sreset initialization program to set the desired controls even if the desired settings are the same as the reset settings. 7 6 5 4 3 2 1 0 R 0 0 0 COPT STOPE SCI2PS IICPS W Reset: 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure5-5. System Options Register 1 (SOPT1) Table5-5. SOPT1 Register Field Descriptions Field Description 7:6 COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with COPT[1:0] COPCLKS in SOPT2 defines the COP timeout period. SeeTable5-6. 5 Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user STOPE program attempts to execute a STOP instruction, an illegal opcode reset is forced. 0 Stop mode disabled. 1 Stop mode enabled. 4 SCI2 Pin Select— This write-once bit selects the location of the RxD2 and TxD2 pins of the SCI2 module. SCI2PS 0 TxD2 on PTF0, RxD2 on PTF1. 1 TxD2 on PTE6, RxD2 on PTE7. 3 IIC Pin Select— This write-once bit selects the location of the SCL and SDA pins of the IIC module. IICPS 0 SCL on PTF2, SDA on PTF3. 1 SCL on PTE4, SDA on PTE5. Table5-6. COP Configuration Options Control Bits COP Window1 Opens Clock Source COP Overflow Count (COPW = 1) COPCLKS COPT[1:0] N/A 0:0 N/A N/A COP is disabled 0 0:1 1 kHz N/A 25cycles (32 ms2) 0 1:0 1 kHz N/A 28 cycles (256 ms1) 0 1:1 1 kHz N/A 210 cycles (1.024 s1) 1 0:1 Bus 6144 cycles 213cycles 1 1:0 Bus 49,152 cycles 216cycles 1 1:1 Bus 196,608 cycles 218cycles 1 WindowedCOPoperationrequirestheusertocleartheCOPtimerinthelast25%oftheselectedtimeoutperiod.Thiscolumn displays the minimum number of clock counts required before the COP timer can be resetwhen in windowed COP mode (COPW=1). 2 Values shown in milliseconds based on t =1ms. See t in the appendixSection A.12.1, “Control Timing,” for the LPO LPO tolerance of this value. MC9S08DZ60 Series Data Sheet, Rev. 4 80 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control 5.8.5 System Options Register 2 (SOPT2) This high page register contains bits to configure MCU specific features on the MC9S08DZ60 Series devices. 7 6 5 4 3 2 1 0 R 0 0 COPCLKS1 COPW1 ADHTS MCSEL W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure5-6. System Options Register 2 (SOPT2) 1 This bit can be written only one time after reset. Additional writes are ignored. Table5-7. SOPT2 Register Field Descriptions Field Description 7 COP Watchdog Clock Select— This write-once bit selects the clock source of the COP watchdog. See COPCLKS Table5-6 for details. 0 Internal 1-kHz clock is source to COP. 1 Bus clock is source to COP. 6 COPWindow—Thiswrite-oncebitselectstheCOPoperationmode.Whenset,the0x55-0xAAwritesequence COPW to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the first 75% of the selected period will reset the MCU. 0 Normal COP operation. 1 Window COP operation. 4 ADC Hardware Trigger Select— This bit selects which hardware trigger initiates conversion for the analog to ADHTS digital converter when the ADC hardware trigger is enabled (ADCTRG is set in ADCSC2 register). 0 Real Time Counter (RTC) overflow. 1 External Interrupt Request (IRQ) pin. 2:0 MCLKDivideSelect—ThesebitsenabletheMCLKoutputonPTA0pinandselectthedivideratiofortheMCLK MCSEL outputaccordingtotheformulabelowwhentheMCSELbitsarenotequaltoallzeroes.IncasethattheMCSEL bits are all zeroes, the MCLK output is disabled. MCLK frequency = Bus Clock frequency ÷ (2 * MCSEL) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 81

Chapter5 Resets, Interrupts, and General System Control 5.8.6 System Device Identification Register (SDIDH, SDIDL) These high page read-only registers are included so host development systems can identify the HCS08 derivativeandrevisionnumber.Thisallowsthedevelopmentsoftwaretorecognizewherespecificmemory blocks, registers, and control bits are located in a target MCU. 7 6 5 4 3 2 1 0 R Reserved ID11 ID10 ID9 ID8 W Reset: 01 01 01 01 0 0 0 0 = Unimplemented or Reserved 1 The revision number that is hard coded into these bits reflects the current silicon revision level. Figure5-7. System Device Identification Register — High (SDIDH) Table5-8. SDIDH Register Field Descriptions Field Description 3:0 PartIdentificationNumber—MC9S08DZ60SeriesMCUsarehard-codedtothevalue0x00E.SeealsoIDbits ID[11:8] inTable5-9. 7 6 5 4 3 2 1 0 R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 W Reset: 0 0 0 0 1 1 1 0 = Unimplemented or Reserved Figure5-8. System Device Identification Register — Low (SDIDL) Table5-9. SDIDL Register Field Descriptions Field Description 7:0 PartIdentificationNumber—MC9S08DZ60SeriesMCUsarehard-codedtothevalue0x00E.SeealsoIDbits ID[7:0] inTable5-8. MC9S08DZ60 Series Data Sheet, Rev. 4 82 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) This high page register contains status and control bits to support the low-voltage detect function, and to enable the bandgap voltage reference for use by the ADC and ACMP modules. This register should be writtenduringtheuser’sresetinitializationprogramtosetthedesiredcontrolsevenifthedesiredsettings are the same as the reset settings. 7 6 5 4 3 2 1 0 R LVWF1 0 0 LVWIE LVDRE2 LVDSE LVDE2 BGBE W LVWACK Reset: 0 0 0 1 1 1 0 0 = Unimplemented or Reserved 1 LVWF will be set in the case when V transitions below the trip point or after reset and V is already below V . Supply Supply LVW 2 This bit can be written only one time after reset. Additional writes are ignored. Figure5-9. System Power Management Status and Control 1 Register (SPMSC1) Table5-10. SPMSC1 Register Field Descriptions Field Description 7 Low-Voltage Warning Flag — The LVWF bit indicates the low-voltage warning status. LVWF 0 low-voltage warning is not present. 1 low-voltage warning is present or was present. 6 Low-VoltageWarningAcknowledge—IfLVWF=1,alow-voltageconditionhasoccurred.Toacknowledgethis LVWACK low-voltage warning, write 1 to LVWACK, which will automatically clear LVWF to 0 if the low-voltage warning is no longer present. 5 Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF. LVWIE 0 Hardware interrupt disabled (use polling). 1 Request a hardware interrupt when LVWF = 1. 4 Low-Voltage Detect Reset Enable — This write-once bit enables LVD events to generate a hardware reset LVDRE (provided LVDE = 1). 0 LVD events do not generate hardware resets. 1 Force an MCU reset when an enabled low-voltage detect event occurs. 3 Low-VoltageDetectStopEnable—ProvidedLVDE=1,thisread/writebitdetermineswhetherthelow-voltage LVDSE detect function operates when the MCU is in stop mode. 0 Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode. 2 Low-VoltageDetectEnable—Thiswrite-oncebitenableslow-voltagedetectlogicandqualifiestheoperation LVDE of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. 0 BandgapBufferEnable—Thisbitenablesaninternalbufferforthebandgapvoltagereferenceforusebythe BGBE ADC and ACMP modules on one of its internal channels. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 83

Chapter5 Resets, Interrupts, and General System Control 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) This register is used to report the status of the low-voltage warning function, and to configure the stop mode behavior of the MCU. This register should be written during the user’s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. 7 6 5 4 3 2 1 0 R 0 0 PPDF 0 0 LVDV1 LVWV PPDC2 W PPDACK Power-on Reset: 0 0 0 0 0 0 0 0 LVD Reset: 0 0 u u 0 0 0 0 Any other Reset: 0 0 u u 0 0 0 0 = Unimplemented or Reserved u = Unaffected by reset 1 This bit can be written only one time after power-on reset. Additional writes are ignored. 2 This bit can be written only one time after reset. Additional writes are ignored. Figure5-10. System Power Management Status and Control 2 Register (SPMSC2) Table5-11. SPMSC2 Register Field Descriptions Field Description 5 Low-VoltageDetectVoltageSelect—Thiswrite-oncebitselectsthelow-voltagedetect(LVD)trippointsetting. LVDV It also selects the warning voltage range. SeeTable5-12. 4 Low-VoltageWarningVoltageSelect—Thisbitselectsthelow-voltagewarning(LVW)trippointvoltage.See LVWV Table5-12. 3 Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode. PPDF 0 MCU has not recovered from stop2 mode. 1 MCU recovered from stop2 mode. 2 Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit. PPDACK 0 Partial Power Down Control — This write-once bit controls whether stop2 or stop3 mode is selected. PPDC 0 Stop3 mode enabled. 1 Stop2, partial power down, mode enabled. Table5-12. LVD and LVW Trip Point Typical Values1 LVDV:LVWV LVW Trip Point LVD Trip Point 0:0 V = 2.74 V V = 2.56 V LVW0 LVD0 0:1 V = 2.92 V LVW1 1:0 V = 4.3 V V = 4.0 V LVW2 LVD1 1:1 V = 4.6 V LVW3 1 See Electrical Characteristics appendix for minimum and maximum values. MC9S08DZ60 Series Data Sheet, Rev. 4 84 Freescale Semiconductor

Chapter 6 Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MC9S08DZ60 Series has seven parallel I/O ports which include a total of up to 53 I/O pins and one input-only pin. SeeChapter2, “Pins and Connections,” for more information about pin assignments and external hardware considerations of these pins. Manyofthesepinsaresharedwithon-chipperipheralssuchastimersystems,communicationsystems,or pin interrupts as shown inTable2-1. The peripheral modules have priority over the general-purpose I/O functions so that when a peripheral is enabled, the I/O functions associated with the shared pins are disabled. After reset, the shared peripheral functions are disabled and the pins are configured as inputs (PTxDDn=0).Thepincontrolfunctionsforeachpinareconfiguredasfollows:slewratecontrolenabled (PTxSEn = 1), low drive strength selected (PTxDSn = 0), and internal pull-ups disabled (PTxPEn = 0). NOTE • Notallgeneral-purposeI/Opinsareavailableonallpackages.Toavoid extracurrentdrainfromfloatinginputpins,theuser’sresetinitialization routine in the application program must either enable on-chip pull-up devices or change the direction of unconnected pins to outputs so the pins do not float. • ThePTE1pindoesnotcontainaclampdiodetoV andshouldnotbe DD driven above V . The voltage measured on the internally pulled up DD PTE1 pin may be as low as V – 0.7 V. The internal gates connected DD to this pin are pulled all the way to V . DD 6.1 Port Data and Data Direction Reading and writing of parallel I/Os are performed through the port data registers. The direction, either inputoroutput,iscontrolledthroughtheportdatadirectionregisters.TheparallelI/Oportfunctionforan individual pin is illustrated in the block diagram shown in Figure6-1. The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is enabled,andalsocontrolsthesourceforportdataregisterreads.Theinputbufferfortheassociatedpinis always enabled unless the pin is enabled as an analog function or is an output-only pin. Whenashareddigitalfunctionisenabledforapin,theoutputbufferiscontrolledbythesharedfunction. However,thedatadirectionregisterbitwillcontinuetocontrolthesourceforreadsoftheportdataregister. Whenasharedanalogfunctionisenabledforapin,boththeinputandoutputbuffersaredisabled.Avalue of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 85

Chapter6 Parallel Input/Output Control In general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. Itisagoodprogrammingpracticetowritetotheportdataregisterbeforechangingthedirectionofaport pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. PTxDDn D Q Output Enable PTxDn D Q Output Data 1 Port Read Data 0 Synchronizer Input Data BUSCLK Figure6-1. Parallel I/O Block Diagram 6.2 Pull-up, Slew Rate, and Drive Strength AssociatedwiththeparallelI/Oportsisasetofregisterslocatedinthehighpageregisterspacethatoperate independentlyoftheparallelI/Oregisters.Theseregistersareusedtocontrolpull-ups,slewrate,anddrive strength for the pins. Aninternalpull-updevicecanbeenabledforeachportpinbysettingthecorrespondingbitinthepull-up enableregister(PTxPEn).Thepull-updeviceisdisabledifthepinisconfiguredasanoutputbytheparallel I/O control logic or any shared peripheral function regardless of the state of the corresponding pull-up enable register bit. The pull-up device is also disabled if the pin is controlled by an analog function. Slewratecontrolcanbeenabledforeachportpinbysettingthecorrespondingbitintheslewratecontrol register(PTxSEn).Whenenabled,slewcontrollimitstherateatwhichanoutputcantransitioninorderto reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs. NOTE Slewrateresetdefaultvaluesmaydifferbetweenengineeringsamplesand final production parts. Always initialize slew rate control to the desired value to ensure correct operation. MC9S08DZ60 Series Data Sheet, Rev. 4 86 Freescale Semiconductor

Chapter6 Parallel Input/Output Control An output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and sinkinggreatercurrent.EventhougheveryI/Opincanbeselectedashighdrive,theusermustensurethat thetotalcurrentsourceandsinklimitsfortheMCUarenotexceeded.Drivestrengthselectionisintended toaffecttheDCbehaviorofI/Opins.However,theACbehaviorisalsoaffected.Highdriveallowsapin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of this, the EMC emissions may be affected by enabling pins as high drive. 6.3 Pin Interrupts PortA,portB,andportDpinscanbeconfiguredasexternalinterruptinputsandasanexternalmeansof waking the MCU from stop or wait low-power modes. The block diagram for each port interrupt logic is shown Figure6-2. PTxACK BUSCLK 1 VDD RESET PTxIF PTxn 0S PTxPS0 DCLRQ SYNCHRONIZER CK PTxES0 PORT STOP STOP BYPASS PTx INTERRUPT FF INTERRUPT 1 REQUEST PTxn 0 S PTxPSn PTxMOD PTxIE PTxESn Figure6-2. Port Interrupt Block Diagram Writing to the PTxPSn bits in the port interrupt pin select register (PTxPS) independently enables or disableseachportpin.Eachportcanbeconfiguredasedgesensitiveoredgeandlevelsensitivebasedon thePTxMODbitintheportinterruptstatusandcontrolregister(PTxSC).Edgesensitivitycanbesoftware programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select register (PTxES). Synchronous logic is used to detect edges. Prior to detecting an edge, enabled port inputs must be at the deassertedlogiclevel.Afallingedgeisdetectedwhenanenabledportinputsignalisseenasalogic1(the deassertedlevel)duringonebuscycleandthenalogic0(theassertedlevel)duringthenextcycle.Arising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle. 6.3.1 Edge Only Sensitivity AvalidedgeonanenabledportpinwillsetPTxIFinPTxSC.IfPTxIEinPTxSCisset,aninterruptrequest will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in PTxSC. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 87

Chapter6 Parallel Input/Output Control 6.3.2 Edge and Level Sensitivity AvalidedgeorlevelonanenabledportpinwillsetPTxIFinPTxSC.IfPTxIEinPTxSCisset,aninterrupt request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in PTxSCprovidedallenabledportinputsareattheirdeassertedlevels.PTxIFwillremainsetifanyenabled port pin is asserted while attempting to clear by writing a 1 to PTxACK. 6.3.3 Pull-up/Pull-down Resistors Theportinterruptpinscanbeconfiguredtouseaninternalpull-up/pull-downresistorusingtheassociated I/O port pull-up enable register. If an internal resistor is enabled, the PTxES register is used to select whether the resistor is a pull-up (PTxESn = 0) or a pull-down (PTxESn = 1). 6.3.4 Pin Interrupt Initialization Whenaninterruptpinisfirstenabled,itispossibletogetafalseinterruptflag.Topreventafalseinterrupt request during pin interrupt initialization, the user should do the following: 1. Mask interrupts by clearing PTxIE in PTxSC. 2. Select the pin polarity by setting the appropriate PTxESn bits in PTxES. 3. If using internal pull-up/pull-down device, configure the associated pull enable bits in PTxPE. 4. Enable the interrupt pins by setting the appropriate PTxPSn bits in PTxPS. 5. Write to PTxACK in PTxSC to clear any false interrupts. 6. Set PTxIE in PTxSC to enable interrupts. 6.4 Pin Behavior in Stop Modes Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An explanation of pin behavior for the various stop modes follows: • Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as beforetheSTOPinstructionwasexecuted.CPUregisterstatusandthestateofI/Oregistersshould besavedinRAMbeforetheSTOPinstructionisexecutedtoplacetheMCUinstop2mode.Upon recoveryfromstop2mode,beforeaccessinganyI/O,theusershouldexaminethestateofthePPDF bitintheSPMSC2register.IfthePPDFbitis0,I/Omustbeinitializedasifapoweronresethad occurred.IfthePPDFbitis1,peripheralsmayrequireinitializationtoberestoredtotheirpre-stop condition.ThiscanbedoneusingdatapreviouslystoredinRAMifitwassavedbeforetheSTOP instructionwasexecuted.Theusermustthenwritea1tothePPDACKbitintheSPMSC2register. Access to I/O is now permitted again in the user application program. • In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon recovery, normal I/O function is available to the user. MC9S08DZ60 Series Data Sheet, Rev. 4 88 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5 Parallel I/O and Pin Control Registers This section provides information about the registers associated with the parallel I/O ports. The data and datadirectionregistersarelocatedinpagezeroofthememorymap.Thepullup,slewrate,drivestrength, and interrupt control registers are located in the high page section of the memory map. RefertotablesinChapter4,“Memory,”fortheabsoluteaddressassignmentsforallparallelI/Oandtheir pin control registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 89

Chapter6 Parallel Input/Output Control 6.5.1 Port A Registers Port A is controlled by the registers listed below. 6.5.1.1 Port A Data Register (PTAD) 7 6 5 4 3 2 1 0 R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-3. Port A Data Register (PTAD) Table6-1. PTAD Register Field Descriptions Field Description 7:0 Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A PTAD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. ResetforcesPTADtoall0s,butthese0sarenotdrivenoutthecorrespondingpinsbecauseresetalsoconfigures all port pins as high-impedance inputs with pull-ups/pull-downs disabled. 6.5.1.2 Port A Data Direction Register (PTADD) 7 6 5 4 3 2 1 0 R PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-4. Port A Data Direction Register (PTADD) Table6-2. PTADD Register Field Descriptions Field Description 7:0 DataDirectionforPortABits—Theseread/writebitscontrolthedirectionofportApinsandwhatisreadfor PTADD[7:0] PTAD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn. MC9S08DZ60 Series Data Sheet, Rev. 4 90 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.1.3 Port A Pull Enable Register (PTAPE) 7 6 5 4 3 2 1 0 R PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-5. Internal Pull Enable for Port A Register (PTAPE) Table6-3. PTAPE Register Field Descriptions Field Description 7:0 InternalPullEnableforPortABits—Eachofthesecontrolbitsdeterminesiftheinternalpull-uporpull-down PTAPE[7:0] deviceisenabledfortheassociatedPTApin.ForportApinsthatareconfiguredasoutputs,thesebitshaveno effect and the internal pull devices are disabled. 0 Internal pull-up/pull-down device disabled for port A bit n. 1 Internal pull-up/pull-down device enabled for port A bit n. NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are configured. 6.5.1.4 Port A Slew Rate Enable Register (PTASE) 7 6 5 4 3 2 1 0 R PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-6. Slew Rate Enable for Port A Register (PTASE) Table6-4. PTASE Register Field Descriptions Field Description 7:0 OutputSlewRateEnableforPortABits—Eachofthesecontrolbitsdeterminesiftheoutputslewratecontrol PTASE[7:0] is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. Note:Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 91

Chapter6 Parallel Input/Output Control 6.5.1.5 Port A Drive Strength Selection Register (PTADS) 7 6 5 4 3 2 1 0 R PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-7. Drive Strength Selection for Port A Register (PTADS) Table6-5. PTADS Register Field Descriptions Field Description 7:0 Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high PTADS[7:0] output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port A bit n. 1 High output drive strength selected for port A bit n. 6.5.1.6 Port A Interrupt Status and Control Register (PTASC) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTAIF 0 PTAIE PTAMOD W PTAACK Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure6-8. Port A Interrupt Status and Control Register (PTASC) Table6-6. PTASC Register Field Descriptions Field Description 3 Port A Interrupt Flag — PTAIF indicates when a port A interrupt is detected. Writes have no effect on PTAIF. PTAIF 0 No port A interrupt detected. 1 Port A interrupt detected. 2 Port A Interrupt Acknowledge — Writing a 1 to PTAACK is part of the flag clearing mechanism. PTAACK PTAACK always reads as 0. 1 Port A Interrupt Enable — PTAIE determines whether a port A interrupt is requested. PTAIE 0 Port A interrupt request not enabled. 1 Port A interrupt request enabled. 0 Port A Detection Mode — PTAMOD (along with the PTAES bits) controls the detection mode of the port A PTAMOD interrupt pins. 0 Port A pins detect edges only. 1 Port A pins detect both edges and levels. MC9S08DZ60 Series Data Sheet, Rev. 4 92 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.1.7 Port A Interrupt Pin Select Register (PTAPS) 7 6 5 4 3 2 1 0 R PTAPS7 PTAPS6 PTAPS5 PTAPS4 PTAPS3 PTAPS2 PTAPS1 PTAPS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-9. Port A Interrupt Pin Select Register (PTAPS) Table6-7. PTAPS Register Field Descriptions Field Description 7:0 Port A Interrupt Pin Selects — Each of the PTAPSn bits enable the corresponding port A interrupt pin. PTAPS[7:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt. 6.5.1.8 Port A Interrupt Edge Select Register (PTAES) 7 6 5 4 3 2 1 0 R PTAES7 PTAES6 PTAES5 PTAES4 PTAES3 PTAES2 PTAES1 PTAES0 W Reset: 0 0 0 0 0 0 0 0 Figure6-10. Port A Edge Select Register (PTAES) Table6-8. PTAES Register Field Descriptions Field Description 7:0 Port A Edge Selects — Each of the PTAESn bits serves a dual purpose by selecting the polarity of the active PTAES[7:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 Apull-updeviceisconnectedtotheassociatedpinanddetectsfallingedge/lowlevelforinterruptgeneration. 1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 93

Chapter6 Parallel Input/Output Control 6.5.2 Port B Registers Port B is controlled by the registers listed below. 6.5.2.1 Port B Data Register (PTBD) 7 6 5 4 3 2 1 0 R PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-11. Port B Data Register (PTBD) Table6-9. PTBD Register Field Descriptions Field Description 7:0 Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B PTBD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. ResetforcesPTBDtoall0s,butthese0sarenotdrivenoutthecorrespondingpinsbecauseresetalsoconfigures all port pins as high-impedance inputs with pull-ups/pull-downs disabled. 6.5.2.2 Port B Data Direction Register (PTBDD) 7 6 5 4 3 2 1 0 R PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-12. Port B Data Direction Register (PTBDD) Table6-10. PTBDD Register Field Descriptions Field Description 7:0 DataDirectionforPortBBits—Theseread/writebitscontrolthedirectionofportBpinsandwhatisreadfor PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. MC9S08DZ60 Series Data Sheet, Rev. 4 94 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.2.3 Port B Pull Enable Register (PTBPE) 7 6 5 4 3 2 1 0 R PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-13. Internal Pull Enable for Port B Register (PTBPE) Table6-11. PTBPE Register Field Descriptions Field Description 7:0 InternalPullEnableforPortBBits—Eachofthesecontrolbitsdeterminesiftheinternalpull-uporpull-down PTBPE[7:0] deviceisenabledfortheassociatedPTBpin.ForportBpinsthatareconfiguredasoutputs,thesebitshaveno effect and the internal pull devices are disabled. 0 Internal pull-up/pull-down device disabled for port B bit n. 1 Internal pull-up/pull-down device enabled for port B bit n. NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are configured. 6.5.2.4 Port B Slew Rate Enable Register (PTBSE) 7 6 5 4 3 2 1 0 R PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-14. Slew Rate Enable for Port B Register (PTBSE) Table6-12. PTBSE Register Field Descriptions Field Description 7:0 OutputSlewRateEnableforPortBBits—Eachofthesecontrolbitsdeterminesiftheoutputslewratecontrol PTBSE[7:0] is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. Note:Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 95

Chapter6 Parallel Input/Output Control 6.5.2.5 Port B Drive Strength Selection Register (PTBDS) 7 6 5 4 3 2 1 0 R PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-15. Drive Strength Selection for Port B Register (PTBDS) Table6-13. PTBDS Register Field Descriptions Field Description 7:0 Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high PTBDS[7:0] output drive for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port B bit n. 1 High output drive strength selected for port B bit n. 6.5.2.6 Port B Interrupt Status and Control Register (PTBSC) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTBIF 0 PTBIE PTBMOD W PTBACK Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure6-16. Port B Interrupt Status and Control Register (PTBSC) Table6-14. PTBSC Register Field Descriptions Field Description 3 Port B Interrupt Flag — PTBIF indicates when a Port B interrupt is detected. Writes have no effect on PTBIF. PTBIF 0 No Port B interrupt detected. 1 Port B interrupt detected. 2 Port B Interrupt Acknowledge — Writing a 1 to PTBACK is part of the flag clearing mechanism. PTBACK PTBACK always reads as 0. 1 Port B Interrupt Enable — PTBIE determines whether a port B interrupt is requested. PTBIE 0 Port B interrupt request not enabled. 1 Port B interrupt request enabled. 0 Port B Detection Mode — PTBMOD (along with the PTBES bits) controls the detection mode of the port B PTBMOD interrupt pins. 0 Port B pins detect edges only. 1 Port B pins detect both edges and levels. MC9S08DZ60 Series Data Sheet, Rev. 4 96 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.2.7 Port B Interrupt Pin Select Register (PTBPS) 7 6 5 4 3 2 1 0 R PTBPS7 PTBPS6 PTBPS5 PTBPS4 PTBPS3 PTBPS2 PTBPS1 PTBPS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-17. Port B Interrupt Pin Select Register (PTBPS) Table6-15. PTBPS Register Field Descriptions Field Description 7:0 Port B Interrupt Pin Selects — Each of the PTBPSn bits enable the corresponding port B interrupt pin. PTBPS[7:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt. 6.5.2.8 Port B Interrupt Edge Select Register (PTBES) 7 6 5 4 3 2 1 0 R PTBES7 PTBES6 PTBES5 PTBES4 PTBES3 PTBES2 PTBES1 PTBES0 W Reset: 0 0 0 0 0 0 0 0 Figure6-18. Port B Edge Select Register (PTBES) Table6-16. PTBES Register Field Descriptions Field Description 7:0 Port B Edge Selects — Each of the PTBESn bits serves a dual purpose by selecting the polarity of the active PTBES[7:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 Apull-updeviceisconnectedtotheassociatedpinanddetectsfallingedge/lowlevelforinterruptgeneration. 1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 97

Chapter6 Parallel Input/Output Control 6.5.3 Port C Registers Port C is controlled by the registers listed below. 6.5.3.1 Port C Data Register (PTCD) 7 6 5 4 3 2 1 0 R PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-19. Port C Data Register (PTCD) Table6-17. PTCD Register Field Descriptions Field Description 7:0 Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C PTCD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pull-ups disabled. 6.5.3.2 Port C Data Direction Register (PTCDD) 7 6 5 4 3 2 1 0 R PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-20. Port C Data Direction Register (PTCDD) Table6-18. PTCDD Register Field Descriptions Field Description 7:0 DataDirectionforPortCBits—Theseread/writebitscontrolthedirectionofportCpinsandwhatisreadfor PTCDD[7:0] PTCD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn. MC9S08DZ60 Series Data Sheet, Rev. 4 98 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.3.3 Port C Pull Enable Register (PTCPE) 7 6 5 4 3 2 1 0 R PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-21. Internal Pull Enable for Port C Register (PTCPE) Table6-19. PTCPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port C Bits — Each of these control bits determines if the internal pull-up device is PTCPE[7:0] enabledfortheassociatedPTCpin.ForportCpinsthatareconfiguredasoutputs,thesebitshavenoeffectand the internal pull devices are disabled. 0 Internal pull-up device disabled for port C bit n. 1 Internal pull-up device enabled for port C bit n. NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are configured. 6.5.3.4 Port C Slew Rate Enable Register (PTCSE) 7 6 5 4 3 2 1 0 R PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-22. Slew Rate Enable for Port C Register (PTCSE) Table6-20. PTCSE Register Field Descriptions Field Description 7:0 OutputSlewRateEnableforPortCBits—Eachofthesecontrolbitsdeterminesiftheoutputslewratecontrol PTCSE[7:0] is enabled for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. Note:Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 99

Chapter6 Parallel Input/Output Control 6.5.3.5 Port C Drive Strength Selection Register (PTCDS) 7 6 5 4 3 2 1 0 R PTCDS7 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-23. Drive Strength Selection for Port C Register (PTCDS) Table6-21. PTCDS Register Field Descriptions Field Description 7:0 Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high PTCDS[7:0] output drive for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port C bit n. 1 High output drive strength selected for port C bit n. MC9S08DZ60 Series Data Sheet, Rev. 4 100 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.4 Port D Registers Port D is controlled by the registers listed below. 6.5.4.1 Port D Data Register (PTDD) 7 6 5 4 3 2 1 0 R PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-24. Port D Data Register (PTDD) Table6-22. PTDD Register Field Descriptions Field Description 7:0 Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D PTDD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pull-ups/pull-downs disabled. 6.5.4.2 Port D Data Direction Register (PTDDD) 7 6 5 4 3 2 1 0 R PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-25. Port D Data Direction Register (PTDDD) Table6-23. PTDDD Register Field Descriptions Field Description 7:0 DataDirectionforPortDBits—Theseread/writebitscontrolthedirectionofportDpinsandwhatisreadfor PTDDD[7:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 101

Chapter6 Parallel Input/Output Control 6.5.4.3 Port D Pull Enable Register (PTDPE) 7 6 5 4 3 2 1 0 R PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-26. Internal Pull Enable for Port D Register (PTDPE) Table6-24. PTDPE Register Field Descriptions Field Description 7:0 InternalPullEnableforPortDBits—Eachofthesecontrolbitsdeterminesiftheinternalpull-uporpull-down PTDPE[7:0] deviceisenabledfortheassociatedPTDpin.ForportDpinsthatareconfiguredasoutputs,thesebitshaveno effect and the internal pull devices are disabled. 0 Internal pull-up/pull-down device disabled for port D bit n. 1 Internal pull-up/pull-down device enabled for port D bit n. NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are configured. 6.5.4.4 Port D Slew Rate Enable Register (PTDSE) 7 6 5 4 3 2 1 0 R PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-27. Slew Rate Enable for Port D Register (PTDSE) Table6-25. PTDSE Register Field Descriptions Field Description 7:0 OutputSlewRateEnableforPortDBits—Eachofthesecontrolbitsdeterminesiftheoutputslewratecontrol PTDSE[7:0] is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port D bit n. 1 Output slew rate control enabled for port D bit n. Note:Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. MC9S08DZ60 Series Data Sheet, Rev. 4 102 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.4.5 Port D Drive Strength Selection Register (PTDDS) 7 6 5 4 3 2 1 0 R PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-28. Drive Strength Selection for Port D Register (PTDDS) Table6-26. PTDDS Register Field Descriptions Field Description 7:0 Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high PTDDS[7:0] output drive for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port D bit n. 1 High output drive strength selected for port D bit n. 6.5.4.6 Port D Interrupt Status and Control Register (PTDSC) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTDIF 0 PTDIE PTDMOD W PTDACK Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure6-29. Port D Interrupt Status and Control Register (PTDSC) Table6-27. PTDSC Register Field Descriptions Field Description 3 Port D Interrupt Flag — PTDIF indicates when a port D interrupt is detected. Writes have no effect on PTDIF. PTDIF 0 No port D interrupt detected. 1 Port D interrupt detected. 2 Port D Interrupt Acknowledge — Writing a 1 to PTDACK is part of the flag clearing mechanism. PTDACK PTDACK always reads as 0. 1 Port D Interrupt Enable — PTDIE determines whether a port D interrupt is requested. PTDIE 0 Port D interrupt request not enabled. 1 Port D interrupt request enabled. 0 Port A Detection Mode — PTDMOD (along with the PTDES bits) controls the detection mode of the port D PTDMOD interrupt pins. 0 Port D pins detect edges only. 1 Port D pins detect both edges and levels. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 103

Chapter6 Parallel Input/Output Control 6.5.4.7 Port D Interrupt Pin Select Register (PTDPS) 7 6 5 4 3 2 1 0 R PTDPS7 PTDPS6 PTDPS5 PTDPS4 PTDPS3 PTDPS2 PTDPS1 PTDPS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-30. Port D Interrupt Pin Select Register (PTDPS) Table6-28. PTDPS Register Field Descriptions Field Description 7:0 Port D Interrupt Pin Selects — Each of the PTDPSn bits enable the corresponding port D interrupt pin. PTDPS[7:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt. 6.5.4.8 Port D Interrupt Edge Select Register (PTDES) 7 6 5 4 3 2 1 0 R PTDES7 PTDES6 PTDES5 PTDES4 PTDES3 PTDES2 PTDES1 PTDES0 W Reset: 0 0 0 0 0 0 0 0 Figure6-31. Port D Edge Select Register (PTDES) Table6-29. PTDES Register Field Descriptions Field Description 7:0 Port D Edge Selects — Each of the PTDESn bits serves a dual purpose by selecting the polarity of the active PTDES[7:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 Apull-updeviceisconnectedtotheassociatedpinanddetectsfallingedge/lowlevelforinterruptgeneration. 1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. MC9S08DZ60 Series Data Sheet, Rev. 4 104 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.5 Port E Registers Port E is controlled by the registers listed below. 6.5.5.1 Port E Data Register (PTED) 7 6 5 4 3 2 1 0 R PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED11 PTED0 W Reset: 0 0 0 0 0 0 0 0 Figure6-32. Port E Data Register (PTED) 1 Reads of this bit always return the pin value of the associated pin, regardless of the value stored in the port data direction bit. Table6-30. PTED Register Field Descriptions Field Description 7:0 Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E PTED[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. ResetforcesPTEDtoall0s,butthese0sarenotdrivenoutthecorrespondingpinsbecauseresetalsoconfigures all port pins as high-impedance inputs with pull-ups disabled. 6.5.5.2 Port E Data Direction Register (PTEDD) 7 6 5 4 3 2 1 0 R PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD11 PTEDD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-33. Port E Data Direction Register (PTEDD) 1 PTEDD1 has no effect on the input-only PTE1 pin. Table6-31. PTEDD Register Field Descriptions Field Description 7:0 DataDirectionforPortEBits—Theseread/writebitscontrolthedirectionofportEpinsandwhatisreadfor PTEDD[7:0] PTED reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 105

Chapter6 Parallel Input/Output Control 6.5.5.3 Port E Pull Enable Register (PTEPE) 7 6 5 4 3 2 1 0 R PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-34. Internal Pull Enable for Port E Register (PTEPE) Table6-32. PTEPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port E Bits — Each of these control bits determines if the internal pull-up device is PTEPE[7:0] enabledfortheassociatedPTEpin.ForportEpinsthatareconfiguredasoutputs,thesebitshavenoeffectand the internal pull devices are disabled. 0 Internal pull-up device disabled for port E bit n. 1 Internal pull-up device enabled for port E bit n. NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are configured. 6.5.5.4 Port E Slew Rate Enable Register (PTESE) 7 6 5 4 3 2 1 0 R PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE11 PTESE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-35. Slew Rate Enable for Port E Register (PTESE) 1 PTESE1 has no effect on the input-only PTE1 pin. Table6-33. PTESE Register Field Descriptions Field Description 7:0 OutputSlewRateEnableforPortEBits—Eachofthesecontrolbitsdeterminesiftheoutputslewratecontrol PTESE[7:0] is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port E bit n. 1 Output slew rate control enabled for port E bit n. Note:Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. MC9S08DZ60 Series Data Sheet, Rev. 4 106 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.5.5 Port E Drive Strength Selection Register (PTEDS) 7 6 5 4 3 2 1 0 R PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS11 PTEDS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-36. Drive Strength Selection for Port E Register (PTEDS) 1 PTEDS1 has no effect on the input-only PTE1 pin. Table6-34. PTEDS Register Field Descriptions Field Description 7:0 Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high PTEDS[7:0] output drive for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port E bit n. 1 High output drive strength selected for port E bit n. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 107

Chapter6 Parallel Input/Output Control 6.5.6 Port F Registers Port F is controlled by the registers listed below. 6.5.6.1 Port F Data Register (PTFD) 7 6 5 4 3 2 1 0 R PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-37. Port F Data Register (PTFD) Table6-35. PTFD Register Field Descriptions Field Description 7:0 Port F Data Register Bits — For port F pins that are inputs, reads return the logic level on the pin. For port F PTFD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. ResetforcesPTFDtoall0s,butthese0sarenotdrivenoutthecorrespondingpinsbecauseresetalsoconfigures all port pins as high-impedance inputs with pull-ups disabled. 6.5.6.2 Port F Data Direction Register (PTFDD) 7 6 5 4 3 2 1 0 R PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-38. Port F Data Direction Register (PTFDD) Table6-36. PTFDD Register Field Descriptions Field Description 7:0 DataDirectionforPortFBits—Theseread/writebitscontrolthedirectionofportFpinsandwhatisreadfor PTFDD[7:0] PTFD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn. MC9S08DZ60 Series Data Sheet, Rev. 4 108 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.6.3 Port F Pull Enable Register (PTFPE) 7 6 5 4 3 2 1 0 R PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-39. Internal Pull Enable for Port F Register (PTFPE) Table6-37. PTFPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port F Bits — Each of these control bits determines if the internal pull-up device is PTFPE[7:0] enabledfortheassociatedPTFpin.ForportFpinsthatareconfiguredasoutputs,thesebitshavenoeffectand the internal pull devices are disabled. 0 Internal pull-up device disabled for port F bit n. 1 Internal pull-up device enabled for port F bit n. NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are configured. 6.5.6.4 Port F Slew Rate Enable Register (PTFSE) 7 6 5 4 3 2 1 0 R PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-40. Slew Rate Enable for Port F Register (PTFSE) Table6-38. PTFSE Register Field Descriptions Field Description 7:0 OutputSlewRateEnableforPortFBits—Eachofthesecontrolbitsdeterminesiftheoutputslewratecontrol PTFSE[7:0] is enabled for the associated PTF pin. For port F pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port F bit n. 1 Output slew rate control enabled for port F bit n. Note:Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 109

Chapter6 Parallel Input/Output Control 6.5.6.5 Port F Drive Strength Selection Register (PTFDS) 7 6 5 4 3 2 1 0 R PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-41. Drive Strength Selection for Port F Register (PTFDS) Table6-39. PTFDS Register Field Descriptions Field Description 7:0 Output Drive Strength Selection for Port F Bits — Each of these control bits selects between low and high PTFDS[7:0] output drive for the associated PTF pin. For port F pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port F bit n. 1 High output drive strength selected for port F bit n. MC9S08DZ60 Series Data Sheet, Rev. 4 110 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.7 Port G Registers Port G is controlled by the registers listed below. 6.5.7.1 Port G Data Register (PTGD) 7 6 5 4 3 2 1 0 R 0 0 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure6-42. Port G Data Register (PTGD) Table6-40. PTGD Register Field Descriptions Field Description 5:0 PortGDataRegisterBits—ForportGpinsthatareinputs,readsreturnthelogiclevelonthepin.ForportG PTGD[5:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pull-ups disabled. 6.5.7.2 Port G Data Direction Register (PTGDD) 7 6 5 4 3 2 1 0 R 0 0 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure6-43. Port G Data Direction Register (PTGDD) Table6-41. PTGDD Register Field Descriptions Field Description 5:0 DataDirectionforPortGBits—Theseread/writebitscontrolthedirectionofportGpinsandwhatisreadfor PTGDD[5:0] PTGD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 111

Chapter6 Parallel Input/Output Control 6.5.7.3 Port G Pull Enable Register (PTGPE) 7 6 5 4 3 2 1 0 R 0 0 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure6-44. Internal Pull Enable for Port G Register (PTGPE) Table6-42. PTGPE Register Field Descriptions Field Description 5:0 Internal Pull Enable for Port G Bits — Each of these control bits determines if the internal pull-up device is PTGPE[5:0] enabledfortheassociatedPTGpin.ForportGpinsthatareconfiguredasoutputs,thesebitshavenoeffectand the internal pull devices are disabled. 0 Internal pull-up device disabled for port G bit n. 1 Internal pull-up device enabled for port G bit n. NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are configured. 6.5.7.4 Port G Slew Rate Enable Register (PTGSE) 7 6 5 4 3 2 1 0 R 0 0 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure6-45. Slew Rate Enable for Port G Register (PTGSE) Table6-43. PTGSE Register Field Descriptions Field Description 5:0 OutputSlewRateEnableforPortGBits—Eachofthesecontrolbitsdeterminesiftheoutputslewratecontrol PTGSE[5:0] is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port G bit n. 1 Output slew rate control enabled for port G bit n. Note:Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. MC9S08DZ60 Series Data Sheet, Rev. 4 112 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.5.7.5 Port G Drive Strength Selection Register (PTGDS) 7 6 5 4 3 2 1 0 R 0 0 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure6-46. Drive Strength Selection for Port G Register (PTGDS) Table6-44. PTGDS Register Field Descriptions Field Description 5:0 Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high PTGDS[5:0 outputdrivefortheassociatedPTGpin.ForportGpinsthatareconfiguredasinputs,thesebitshavenoeffect. 0 Low output drive strength selected for port G bit n. 1 High output drive strength selected for port G bit n. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 113

Chapter6 Parallel Input/Output Control MC9S08DZ60 Series Data Sheet, Rev. 4 114 Freescale Semiconductor

Chapter 7 Central Processor Unit (S08CPUV3) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructionsandenhancedaddressingmodeswereaddedtoimproveCcompilerefficiencyandtosupport anewbackgrounddebugsystemwhichreplacesthemonitormodeofearlierM68HC08microcontrollers (MCU). 7.1.1 Features Features of the HCS08 CPU include: • Object code fully upward-compatible with M68HC05 and M68HC08 Families • All registers and memory are mapped to a single 64-Kbyte address space • 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space) • 16-bit index register (H:X) with powerful indexed addressing modes • 8-bit accumulator (A) • Many instructions treat X as a second general-purpose 8-bit register • Seven addressing modes: — Inherent — Operands in internal registers — Relative — 8-bit signed offset to branch destination — Immediate — Operand in next object code byte(s) — Direct — Operand in memory at 0x0000–0x00FF — Extended — Operand anywhere in 64-Kbyte address space — Indexed relative to H:X — Five submodes including auto increment — Indexed relative to SP — Improves C efficiency dramatically • Memory-to-memory data move instructions with four address mode combinations • Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (BCD) operations • Efficient bit manipulation instructions • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • STOP and WAIT instructions to invoke low-power operating modes MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 115

Chapter7 Central Processor Unit (S08CPUV3) 7.2 Programmer’s Model and CPU Registers Figure7-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) INDEX REGISTER (LOW) X 15 8 7 0 STACK POINTER SP 15 0 PROGRAM COUNTER PC 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure7-1. CPU Registers 7.2.1 Accumulator (A) The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit (ALU)isconnectedtotheaccumulatorandtheALUresultsareoftenstoredintotheAaccumulatorafter arithmeticandlogicaloperations.Theaccumulatorcanbeloadedfrommemoryusingvariousaddressing modes to specify the address where the loaded data comes from, or the contents of A can be stored to memory using various addressing modes to specify the address where data from A will be stored. Reset has no effect on the contents of the A accumulator. 7.2.2 Index Register (H:X) This16-bitregisterisactuallytwoseparate8-bitregisters(HandX),whichoftenworktogetherasa16-bit addresspointerwhereHholdstheupperbyteofanaddressandXholdsthelowerbyteoftheaddress.All indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer; however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the low-order 8-bit half (X). Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data values.Xcanbecleared,incremented,decremented,complemented,negated,shifted,orrotated.Transfer instructionsallowdatatobetransferredfromAortransferredtoAwherearithmeticandlogicaloperations can then be performed. ForcompatibilitywiththeearlierM68HC05Family,Hisforcedto0x00duringreset.Resethasnoeffect on the contents of X. MC9S08DZ60 Series Data Sheet, Rev. 4 116 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV3) 7.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can beanysizeuptotheamountofavailableRAM.Thestackisusedtoautomaticallysavethereturnaddress for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The AIS(addimmediatetostackpointer)instructionaddsan8-bitsignedimmediatevaluetoSP.Thisismost often used to allocate or deallocate space for local variables on the stack. SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs normally change the value in SP to the address of the last location (highest address) in on-chip RAM during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF). The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer. 7.2.4 Program Counter (PC) Theprogramcounterisa16-bitregisterthatcontainstheaddressofthenextinstructionoroperandtobe fetched. During normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location. This is called a change-of-flow. During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF. The vector stored there is the address of the first instruction that will be executed after exiting the reset state. 7.2.5 Condition Code Register (CCR) The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of theinstructionjustexecuted.Bits6and5aresetpermanentlyto1.Thefollowingparagraphsdescribethe functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to theHCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 117

Chapter7 Central Processor Unit (S08CPUV3) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure7-2. Condition Code Register Table7-1. CCR Register Field Descriptions Field Description 7 Two’sComplementOverflowFlag—TheCPUsetstheoverflowflagwhenatwo’scomplementoverflowoccurs. V The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 0 No overflow 1 Overflow 4 Half-CarryFlag—TheCPUsetsthehalf-carryflagwhenacarryoccursbetweenaccumulatorbits3and4during H an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the result to a valid BCD value. 0 No carry between bits 3 and 4 1 Carry between bits 3 and 4 3 Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts I are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automaticallyaftertheCPUregistersaresavedonthestack,butbeforethefirstinstructionoftheinterruptservice routine is executed. Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This ensuresthatthenextinstructionafteraCLIorTAPwillalwaysbeexecutedwithoutthepossibilityofanintervening interrupt, provided I was set. 0 Interrupts enabled 1 Interrupts disabled 2 Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data N manipulationproducesanegativeresult,settingbit7oftheresult.Simplyloadingorstoringan8-bitor16-bitvalue causes N to be set if the most significant bit of the loaded or stored value was 1. 0 Non-negative result 1 Negative result 1 Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation Z produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the loaded or stored value was all 0s. 0 Non-zero result 1 Zero result 0 Carry/BorrowFlag—TheCPUsetsthecarry/borrowflagwhenanadditionoperationproducesacarryoutofbit C 7oftheaccumulatororwhenasubtractionoperationrequiresaborrow.Someinstructions—suchasbittestand branch, shift, and rotate — also clear or set the carry/borrow flag. 0 No carry out of bit 7 1 Carry out of bit 7 MC9S08DZ60 Series Data Sheet, Rev. 4 118 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV3) 7.3 Addressing Modes AddressingmodesdefinethewaytheCPUaccessesoperandsanddata.IntheHCS08,allmemory,status andcontrolregisters,andinput/output(I/O)portsshareasingle64-Kbytelinearaddressspacesoa16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructionsthataccessvariablesinRAMcanalsobeusedtoaccessI/Oandcontrolregistersornonvolatile program space. Someinstructionsusemorethanoneaddressingmode.Forinstance,moveinstructionsuseoneaddressing mode to specify the source operand and a second addressing mode to specify the destination address. InstructionssuchasBRCLR,BRSET,CBEQ,andDBNZuseoneaddressingmodetospecifythelocation of an operand for a test and then use relative addressing mode to specify the branch destination address whenthetestedconditionistrue.ForBRCLR,BRSET,CBEQ,andDBNZ,theaddressingmodelistedin the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 7.3.1 Inherent Addressing Mode (INH) In this addressing mode, operands needed to complete the instruction (if any) are located within CPU registers so the CPU does not need to access memory to get any operands. 7.3.2 Relative Addressing Mode (REL) Relativeaddressingmodeisusedtospecifythedestinationlocationforbranchinstructions.Asigned8-bit offsetvalueislocatedinthememorylocationimmediatelyfollowingtheopcode.Duringexecution,ifthe branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 7.3.3 Immediate Addressing Mode (IMM) In immediate addressing mode, the operand needed to complete the instruction is included in the object codeimmediatelyfollowingtheinstructionopcodeinmemory.Inthecaseofa16-bitimmediateoperand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that. 7.3.4 Direct Addressing Mode (DIR) Indirectaddressingmode,theinstructionincludesthelow-ordereightbitsofanaddressinthedirectpage (0x0000–0x00FF).Duringexecutiona16-bitaddressisformedbyconcatenatinganimplied0x00forthe high-order half of the address and the direct address from the instruction to get the 16-bit address where thedesiredoperandislocated.Thisisfasterandmorememoryefficientthanspecifyingacomplete16-bit address for the operand. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 119

Chapter7 Central Processor Unit (S08CPUV3) 7.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.3.6 Indexed Addressing Mode Indexedaddressingmodehassevenvariationsincludingfivethatusethe16-bitH:Xindexregisterpairand two that use the stack pointer as the base reference. 7.3.6.1 Indexed, No Offset (IX) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairastheaddressof the operand needed to complete the instruction. 7.3.6.2 Indexed, No Offset with Post Increment (IX+) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairastheaddressof the operand needed to complete the instruction. The index register pair is then incremented (H:X=H:X+0x0001) after the operand has been fetched. This addressing mode is only used for MOV and CBEQ instructions. 7.3.6.3 Indexed, 8-Bit Offset (IX1) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairplusanunsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairplusanunsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. Theindexregisterpairisthenincremented(H:X=H:X+0x0001)aftertheoperandhasbeenfetched.This addressing mode is used only for the CBEQ instruction. 7.3.6.5 Indexed, 16-Bit Offset (IX2) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairplusa16-bitoffset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.6 SP-Relative, 8-Bit Offset (SP1) Thisvariationofindexedaddressingusesthe16-bitvalueinthestackpointer(SP)plusanunsigned8-bit offset included in the instruction as the address of the operand needed to complete the instruction. MC9S08DZ60 Series Data Sheet, Rev. 4 120 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV3) 7.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like otherCPUinstructions.Inaddition,afewinstructionssuchasSTOPandWAITdirectlyaffectotherMCU circuitry. This section provides additional information about these operations. 7.4.1 Reset Sequence Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction boundary before responding to a reset event). For a more detailed discussion about how the MCU recognizes resets and determines the source, refer to theResets, Interrupts, and System Configuration chapter. Thereseteventisconsideredconcludedwhenthesequencetodeterminewhethertheresetcamefroman internalsourceisdoneandwhentheresetpinisnolongerasserted.Attheconclusionofaresetevent,the CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for execution of the first program instruction. 7.4.2 Interrupt Sequence When an interrupt is requested, the CPU completes the current instruction before responding to the interrupt.Atthispoint,theprogramcounterispointingatthestartofthenextinstruction,whichiswhere the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the samesequenceofoperationsasforasoftwareinterrupt(SWI)instruction,excepttheaddressusedforthe vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. The CPU sequence for an interrupt is: 1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order. 2. Set the I bit in the CCR. 3. Fetch the high-order half of the interrupt vector. 4. Fetch the low-order half of the interrupt vector. 5. Delay for one free bus cycle. 6. Fetch three bytes of program information starting at the address indicated by the interrupt vector to fill the instruction queue in preparation for execution of the first instruction in the interrupt service routine. After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 121

Chapter7 Central Processor Unit (S08CPUV3) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). ForcompatibilitywiththeearlierM68HC05MCUs,thehigh-orderhalfoftheH:Xindexregisterpair(H) is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends theinterruptserviceroutine.ItisnotnecessarytosaveHifyouarecertainthattheinterruptserviceroutine does not use any instructions or auto-increment addressing modes that might change the value of H. The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 7.4.3 Wait Mode Operation The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that willwaketheCPUfromwaitmode.Whenaninterruptorreseteventoccurs,theCPUclockswillresume and the interrupt or reset event will be processed normally. IfaserialBACKGROUNDcommandisissuedtotheMCUthroughthebackgrounddebuginterfacewhile theCPUisinwaitmode,CPUclockswillresumeandtheCPUwillenteractivebackgroundmodewhere otherserialbackgroundcommandscanbeprocessed.Thisensuresthatahostdevelopmentsystemcanstill gain access to a target MCU even if it is in wait mode. 7.4.4 Stop Mode Operation Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to minimize power consumption. In such systems, external circuitry is needed to control the time spent in stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU fromstop mode. When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control bithasbeensetbyaserialcommandthroughthebackgroundinterface(orbecausetheMCUwasresetinto activebackgroundmode),theoscillatorisforcedtoremainactivewhentheMCUentersstopmode.Inthis case,ifaserialBACKGROUNDcommandisissuedtotheMCUthroughthebackgrounddebuginterface whiletheCPUisinstopmode,CPUclockswillresumeandtheCPUwillenteractivebackgroundmode whereotherserialbackgroundcommandscanbeprocessed.Thisensuresthatahostdevelopmentsystem can still gain access to a target MCU even if it is in stop mode. RecoveryfromstopmodedependsontheparticularHCS08andwhethertheoscillatorwasstoppedinstop mode. Refer to theModes of Operationchapter for more details. MC9S08DZ60 Series Data Sheet, Rev. 4 122 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV3) 7.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface. Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGNDopcode.Whentheprogramreachesthisbreakpointaddress,theCPUisforcedtoactivebackground mode rather than continuing the user program. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 123

Chapter7 Central Processor Unit (S08CPUV3) 7.5 HCS08 Instruction Set Summary Table7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction. Table7-2. Instruction Set Summary (Sheet 1 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C ADC #opr8i IMM A9 ii 2 pp ADC opr8a DIR B9 dd 3 rpp ADC opr16a EXT C9 hh ll 4 prpp ADC oprx16,X Add with Carry IX2 D9 ee ff 4 prpp ↕ 1 1 ↕ – ↕ ↕ ↕ ADC oprx8,X A← (A) + (M) + (C) IX1 E9 ff 3 rpp ADC ,X IX F9 3 rfp ADC oprx16,SP SP2 9E D9 ee ff 5 pprpp ADC oprx8,SP SP1 9E E9 ff 4 prpp ADD #opr8i IMM AB ii 2 pp ADD opr8a DIR BB dd 3 rpp ADD opr16a EXT CB hh ll 4 prpp ADD oprx16,X Add without Carry IX2 DB ee ff 4 prpp ↕ 1 1 ↕ – ↕ ↕ ↕ ADD oprx8,X A← (A) + (M) IX1 EB ff 3 rpp ADD ,X IX FB 3 rfp ADD oprx16,SP SP2 9E DB ee ff 5 pprpp ADD oprx8,SP SP1 9E EB ff 4 prpp Add Immediate Value (Signed) to AIS #opr8i StackPointer IMM A7 ii 2 pp – 1 1 – – – – – SP← (SP) + (M) Add Immediate Value (Signed) to AIX #opr8i IndexRegister (H:X) IMM AF ii 2 pp – 1 1 – – – – – H:X← (H:X) + (M) AND #opr8i IMM A4 ii 2 pp AND opr8a DIR B4 dd 3 rpp AND opr16a EXT C4 hh ll 4 prpp AND oprx16,X Logical AND IX2 D4 ee ff 4 prpp 0 1 1 – –↕ ↕ – AND oprx8,X A← (A) & (M) IX1 E4 ff 3 rpp AND ,X IX F4 3 rfp AND oprx16,SP SP2 9E D4 ee ff 5 pprpp AND oprx8,SP SP1 9E E4 ff 4 prpp ASL opr8a Arithmetic Shift Left DIR 38 dd 5 rfwpp ASLA INH 48 1 p ASLX INH 58 1 p C 0 ↕ 1 1 – –↕ ↕ ↕ ASL oprx8,X IX1 68 ff 5 rfwpp b7 b0 ASL ,X IX 78 4 rfwp ASL oprx8,SP (Same as LSL) SP1 9E 68 ff 6 prfwpp ASR opr8a DIR 37 dd 5 rfwpp ASRA Arithmetic Shift Right INH 47 1 p ASRX INH 57 1 p ↕ 1 1 – –↕ ↕ ↕ ASR oprx8,X C IX1 67 ff 5 rfwpp ASR ,X b7 b0 IX 77 4 rfwp ASR oprx8,SP SP1 9E 67 ff 6 prfwpp MC9S08DZ60 Series Data Sheet, Rev. 4 124 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV3) Table7-2. Instruction Set Summary (Sheet 2 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C Branch if Carry Bit Clear BCC rel REL 24 rr 3 ppp – 1 1 – – – – – (if C = 0) DIR (b0) 11 dd 5 rfwpp DIR (b1) 13 dd 5 rfwpp DIR (b2) 15 dd 5 rfwpp Clear Bit n in Memory DIR (b3) 17 dd 5 rfwpp BCLR n,opr8a – 1 1 – – – – – (Mn← 0) DIR (b4) 19 dd 5 rfwpp DIR (b5) 1B dd 5 rfwpp DIR (b6) 1D dd 5 rfwpp DIR (b7) 1F dd 5 rfwpp Branch if Carry Bit Set (if C = 1) BCS rel REL 25 rr 3 ppp – 1 1 – – – – – (Same as BLO) BEQ rel Branch if Equal (if Z = 1) REL 27 rr 3 ppp – 1 1 – – – – – Branch if Greater Than or Equal To BGE rel REL 90 rr 3 ppp – 1 1 – – – – – (if N ⊕ V=0) (Signed) Enter active background if ENBDM=1 BGND Waits for and processes BDM commands INH 82 5+ fp...ppp – 1 1 – – – – – until GO, TRACE1, or TAGGO Branch if Greater Than (if Z| (N ⊕ V)=0) BGT rel REL 92 rr 3 ppp – 1 1 – – – – – (Signed) BHCC rel Branch if Half Carry Bit Clear (if H = 0) REL 28 rr 3 ppp – 1 1 – – – – – BHCS rel Branch if Half Carry Bit Set (if H = 1) REL 29 rr 3 ppp – 1 1 – – – – – BHI rel Branch if Higher (if C | Z = 0) REL 22 rr 3 ppp – 1 1 – – – – – Branch if Higher or Same (if C = 0) BHS rel REL 24 rr 3 ppp – 1 1 – – – – – (Same as BCC) BIHrel Branch if IRQ Pin High (if IRQ pin = 1) REL 2F rr 3 ppp – 1 1 – – – – – BIL rel Branch if IRQ Pin Low (if IRQ pin = 0) REL 2E rr 3 ppp – 1 1 – – – – – BIT #opr8i IMM A5 ii 2 pp BIT opr8a DIR B5 dd 3 rpp BIT opr16a EXT C5 hh ll 4 prpp Bit Test BIT oprx16,X IX2 D5 ee ff 4 prpp (A) & (M) 0 1 1 – –↕ ↕ – BIT oprx8,X IX1 E5 ff 3 rpp (CCR Updated but Operands Not Changed) BIT ,X IX F5 3 rfp BIT oprx16,SP SP2 9E D5 ee ff 5 pprpp BIT oprx8,SP SP1 9E E5 ff 4 prpp Branch if Less Than or Equal To BLE rel REL 93 rr 3 ppp – 1 1 – – – – – (if Z| (N⊕V) = 1) (Signed) BLO rel Branch if Lower (if C = 1) (Same as BCS) REL 25 rr 3 ppp – 1 1 – – – – – BLS rel Branch if Lower or Same (if C | Z = 1) REL 23 rr 3 ppp – 1 1 – – – – – BLTrel Branch if Less Than (if N ⊕ V =1) (Signed) REL 91 rr 3 ppp – 1 1 – – – – – BMC rel Branch if Interrupt Mask Clear (if I = 0) REL 2C rr 3 ppp – 1 1 – – – – – BMI rel Branch if Minus (if N = 1) REL 2B rr 3 ppp – 1 1 – – – – – BMS rel Branch if Interrupt Mask Set (if I = 1) REL 2D rr 3 ppp – 1 1 – – – – – BNE rel Branch if Not Equal (if Z = 0) REL 26 rr 3 ppp – 1 1 – – – – – MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 125

Chapter7 Central Processor Unit (S08CPUV3) Table7-2. Instruction Set Summary (Sheet 3 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C BPL rel Branch if Plus (if N = 0) REL 2A rr 3 ppp – 1 1 – – – – – BRA rel Branch Always (if I = 1) REL 20 rr 3 ppp – 1 1 – – – – – DIR (b0) 01 dd rr 5 rpppp DIR (b1) 03 dd rr 5 rpppp DIR (b2) 05 dd rr 5 rpppp DIR (b3) 07 dd rr 5 rpppp BRCLR n,opr8a,rel Branch if Bitn inMemory Clear (if (Mn) = 0) – 1 1 – – – –↕ DIR (b4) 09 dd rr 5 rpppp DIR (b5) 0B dd rr 5 rpppp DIR (b6) 0D dd rr 5 rpppp DIR (b7) 0F dd rr 5 rpppp BRN rel Branch Never (if I = 0) REL 21 rr 3 ppp – 1 1 – – – – – DIR (b0) 00 dd rr 5 rpppp DIR (b1) 02 dd rr 5 rpppp DIR (b2) 04 dd rr 5 rpppp DIR (b3) 06 dd rr 5 rpppp BRSET n,opr8a,rel Branch if Bitn inMemory Set (if (Mn) = 1) – 1 1 – – – –↕ DIR (b4) 08 dd rr 5 rpppp DIR (b5) 0A dd rr 5 rpppp DIR (b6) 0C dd rr 5 rpppp DIR (b7) 0E dd rr 5 rpppp DIR (b0) 10 dd 5 rfwpp DIR (b1) 12 dd 5 rfwpp DIR (b2) 14 dd 5 rfwpp DIR (b3) 16 dd 5 rfwpp BSET n,opr8a Set Bitnin Memory (Mn← 1) – 1 1 – – – – – DIR (b4) 18 dd 5 rfwpp DIR (b5) 1A dd 5 rfwpp DIR (b6) 1C dd 5 rfwpp DIR (b7) 1E dd 5 rfwpp Branch to Subroutine PC←(PC) + $0002 BSR rel push (PCL); SP← (SP) – $0001 REL AD rr 5 ssppp – 1 1 – – – – – push (PCH); SP← (SP) – $0001 PC← (PC) +rel CBEQ opr8a,rel Compare and... Branch if (A) = (M) DIR 31 dd rr 5 rpppp CBEQA #opr8i,rel Branch if (A) = (M) IMM 41 ii rr 4 pppp CBEQX #opr8i,rel Branch if (X) = (M) IMM 51 ii rr 4 pppp – 1 1 – – – – – CBEQ oprx8,X+,rel Branch if (A) = (M) IX1+ 61 ff rr 5 rpppp CBEQ ,X+,rel Branch if (A) = (M) IX+ 71 rr 5 rfppp CBEQoprx8,SP,rel Branch if (A) = (M) SP1 9E 61 ff rr 6 prpppp CLC Clear Carry Bit (C← 0) INH 98 1 p – 1 1 – – – – 0 CLI Clear Interrupt Mask Bit (I← 0) INH 9A 1 p – 1 1 – 0 – – – CLR opr8a Clear M← $00 DIR 3F dd 5 rfwpp CLRA A← $00 INH 4F 1 p CLRX X← $00 INH 5F 1 p CLRH H← $00 INH 8C 1 p 0 1 1 – – 0 1 – CLR oprx8,X M← $00 IX1 6F ff 5 rfwpp CLR ,X M← $00 IX 7F 4 rfwp CLR oprx8,SP M← $00 SP1 9E 6F ff 6 prfwpp MC9S08DZ60 Series Data Sheet, Rev. 4 126 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV3) Table7-2. Instruction Set Summary (Sheet 4 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C CMP #opr8i IMM A1 ii 2 pp CMP opr8a DIR B1 dd 3 rpp CMP opr16a EXT C1 hh ll 4 prpp Compare Accumulator with Memory CMP oprx16,X IX2 D1 ee ff 4 prpp A – M ↕ 1 1 – –↕ ↕ ↕ CMP oprx8,X IX1 E1 ff 3 rpp (CCR Updated But Operands Not Changed) CMP ,X IX F1 3 rfp CMP oprx16,SP SP2 9E D1 ee ff 5 pprpp CMP oprx8,SP SP1 9E E1 ff 4 prpp COM opr8a Complement M← (M)= $FF – (M) DIR 33 dd 5 rfwpp COMA (One’s Complement) A← (A) = $FF – (A) INH 43 1 p COMX X← (X) = $FF – (X) INH 53 1 p 0 1 1 – –↕ ↕ 1 COM oprx8,X M← (M) = $FF – (M) IX1 63 ff 5 rfwpp COM ,X M← (M) = $FF – (M) IX 73 4 rfwp COM oprx8,SP M← (M) = $FF – (M) SP1 9E 63 ff 6 prfwpp CPHXopr16a EXT 3E hh ll 6 prrfpp Compare IndexRegister (H:X) withMemory CPHX #opr16i IMM 65 jj kk 3 ppp (H:X) – (M:M + $0001) ↕ 1 1 – –↕ ↕ ↕ CPHXopr8a DIR 75 dd 5 rrfpp (CCR Updated But Operands Not Changed) CPHX oprx8,SP SP1 9E F3 ff 6 prrfpp CPX #opr8i IMM A3 ii 2 pp CPX opr8a DIR B3 dd 3 rpp CPX opr16a Compare X (Index Register Low) with EXT C3 hh ll 4 prpp CPX oprx16,X Memory IX2 D3 ee ff 4 prpp ↕ 1 1 – –↕ ↕ ↕ CPX oprx8,X X – M IX1 E3 ff 3 rpp CPX ,X (CCR Updated But Operands Not Changed) IX F3 3 rfp CPX oprx16,SP SP2 9E D3 ee ff 5 pprpp CPX oprx8,SP SP1 9E E3 ff 4 prpp Decimal Adjust Accumulator DAA INH 72 1 p U 1 1 – –↕ ↕ ↕ After ADD or ADC of BCD Values DBNZ opr8a,rel DIR 3B dd rr 7 rfwpppp DBNZA rel INH 4B rr 4 fppp Decrement A, X, or M and Branch if Not Zero DBNZX rel INH 5B rr 4 fppp (if (result)≠0) – 1 1 – – – – – DBNZ oprx8,X,rel IX1 6B ff rr 7 rfwpppp DBNZX Affects X Not H DBNZ ,X,rel IX 7B rr 6 rfwppp DBNZ oprx8,SP,rel SP1 9E 6B ff rr 8 prfwpppp DEC opr8a Decrement M← (M) – $01 DIR 3A dd 5 rfwpp DECA A← (A) – $01 INH 4A 1 p DECX X← (X) – $01 INH 5A 1 p ↕ 1 1 – –↕ ↕ – DEC oprx8,X M← (M) – $01 IX1 6A ff 5 rfwpp DEC ,X M← (M) – $01 IX 7A 4 rfwp DEC oprx8,SP M← (M) – $01 SP1 9E 6A ff 6 prfwpp Divide DIV INH 52 6 fffffp – 1 1 – – –↕ ↕ A← (H:A)÷(X); H← Remainder EOR #opr8i Exclusive OR Memory with Accumulator IMM A8 ii 2 pp EOR opr8a A← (A⊕ M) DIR B8 dd 3 rpp EOR opr16a EXT C8 hh ll 4 prpp EOR oprx16,X IX2 D8 ee ff 4 prpp 0 1 1 – –↕ ↕ – EOR oprx8,X IX1 E8 ff 3 rpp EOR ,X IX F8 3 rfp EOR oprx16,SP SP2 9E D8 ee ff 5 pprpp EOR oprx8,SP SP1 9E E8 ff 4 prpp MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 127

Chapter7 Central Processor Unit (S08CPUV3) Table7-2. Instruction Set Summary (Sheet 5 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C INC opr8a Increment M← (M) + $01 DIR 3C dd 5 rfwpp INCA A← (A) + $01 INH 4C 1 p INCX X← (X) + $01 INH 5C 1 p ↕ 1 1 – –↕ ↕ – INC oprx8,X M← (M) + $01 IX1 6C ff 5 rfwpp INC ,X M← (M) + $01 IX 7C 4 rfwp INC oprx8,SP M← (M) + $01 SP1 9E 6C ff 6 prfwpp JMP opr8a DIR BC dd 3 ppp JMP opr16a EXT CC hh ll 4 pppp Jump JMP oprx16,X IX2 DC ee ff 4 pppp – 1 1 – – – – – PC← Jump Address JMP oprx8,X IX1 EC ff 3 ppp JMP ,X IX FC 3 ppp JSR opr8a Jump to Subroutine DIR BD dd 5 ssppp JSR opr16a PC← (PC) +n (n = 1, 2, or 3) EXT CD hh ll 6 pssppp JSR oprx16,X Push (PCL); SP← (SP) – $0001 IX2 DD ee ff 6 pssppp – 1 1 – – – – – JSR oprx8,X Push (PCH); SP← (SP) – $0001 IX1 ED ff 5 ssppp JSR ,X PC← Unconditional Address IX FD 5 ssppp LDA #opr8i IMM A6 ii 2 pp LDA opr8a DIR B6 dd 3 rpp LDA opr16a EXT C6 hh ll 4 prpp LDA oprx16,X Load Accumulator from Memory IX2 D6 ee ff 4 prpp 0 1 1 – –↕ ↕ – LDA oprx8,X A← (M) IX1 E6 ff 3 rpp LDA ,X IX F6 3 rfp LDA oprx16,SP SP2 9E D6 ee ff 5 pprpp LDA oprx8,SP SP1 9E E6 ff 4 prpp LDHX #opr16i IMM 45 jj kk 3 ppp LDHX opr8a DIR 55 dd 4 rrpp LDHX opr16a EXT 32 hh ll 5 prrpp Load Index Register (H:X) LDHX ,X IX 9E AE 5 prrfp 0 1 1 – –↕ ↕ – H:X← (M:M+ $0001) LDHX oprx16,X IX2 9E BE ee ff 6 pprrpp LDHX oprx8,X IX1 9E CE ff 5 prrpp LDHX oprx8,SP SP1 9E FE ff 5 prrpp LDX #opr8i IMM AE ii 2 pp LDX opr8a DIR BE dd 3 rpp LDX opr16a EXT CE hh ll 4 prpp LDX oprx16,X Load X (Index Register Low) from Memory IX2 DE ee ff 4 prpp 0 1 1 – –↕ ↕ – LDX oprx8,X X← (M) IX1 EE ff 3 rpp LDX ,X IX FE 3 rfp LDX oprx16,SP SP2 9E DE ee ff 5 pprpp LDX oprx8,SP SP1 9E EE ff 4 prpp LSL opr8a Logical Shift Left DIR 38 dd 5 rfwpp LSLA INH 48 1 p LSLX C 0 INH 58 1 p ↕ 1 1 – –↕ ↕ ↕ LSL oprx8,X IX1 68 ff 5 rfwpp b7 b0 LSL ,X IX 78 4 rfwp LSL oprx8,SP (Same as ASL) SP1 9E 68 ff 6 prfwpp LSR opr8a DIR 34 dd 5 rfwpp Logical Shift Right LSRA INH 44 1 p LSRX INH 54 1 p ↕ 1 1 – – 0↕ ↕ LSR oprx8,X 0 C IX1 64 ff 5 rfwpp LSR ,X b7 b0 IX 74 4 rfwp LSR oprx8,SP SP1 9E 64 ff 6 prfwpp MC9S08DZ60 Series Data Sheet, Rev. 4 128 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV3) Table7-2. Instruction Set Summary (Sheet 6 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C MOVopr8a,opr8a Move DIR/DIR 4E dd dd 5 rpwpp MOV opr8a,X+ (M) ←(M) DIR/IX+ 5E dd 5 rfwpp destination source 0 1 1 – –↕ ↕ – MOV #opr8i,opr8a In IX+/DIR and DIR/IX+ Modes, IMM/DIR 6E ii dd 4 pwpp MOV ,X+,opr8a H:X← (H:X) + $0001 IX+/DIR 7E dd 5 rfwpp Unsigned multiply MUL INH 42 5 ffffp – 1 1 0 – – – 0 X:A← (X)× (A) NEG opr8a Negate M← – (M) = $00 – (M) DIR 30 dd 5 rfwpp NEGA (Two’s Complement) A← – (A) = $00 – (A) INH 40 1 p NEGX X← – (X) = $00 – (X) INH 50 1 p ↕ 1 1 – –↕ ↕ ↕ NEG oprx8,X M← – (M) = $00 – (M) IX1 60 ff 5 rfwpp NEG ,X M← – (M) = $00 – (M) IX 70 4 rfwp NEG oprx8,SP M← – (M) = $00 – (M) SP1 9E 60 ff 6 prfwpp NOP No Operation — Uses 1 Bus Cycle INH 9D 1 p – 1 1 – – – – – Nibble Swap Accumulator NSA INH 62 1 p – 1 1 – – – – – A← (A[3:0]:A[7:4]) ORA #opr8i IMM AA ii 2 pp ORA opr8a DIR BA dd 3 rpp ORA opr16a EXT CA hh ll 4 prpp ORA oprx16,X Inclusive ORAccumulator andMemory IX2 DA ee ff 4 prpp 0 1 1 – –↕ ↕ – ORA oprx8,X A← (A) | (M) IX1 EA ff 3 rpp ORA ,X IX FA 3 rfp ORA oprx16,SP SP2 9E DA ee ff 5 pprpp ORA oprx8,SP SP1 9E EA ff 4 prpp Push Accumulator onto Stack PSHA INH 87 2 sp – 1 1 – – – – – Push (A); SP←(SP) – $0001 Push H (Index Register High) onto Stack PSHH INH 8B 2 sp – 1 1 – – – – – Push (H); SP←(SP) – $0001 Push X (Index Register Low) onto Stack PSHX INH 89 2 sp – 1 1 – – – – – Push (X); SP←(SP) – $0001 Pull Accumulator from Stack PULA INH 86 3 ufp – 1 1 – – – – – SP←(SP +$0001); Pull (A) Pull H (Index Register High) from Stack PULH INH 8A 3 ufp – 1 1 – – – – – SP←(SP +$0001); Pull (H) Pull X (Index Register Low) from Stack PULX INH 88 3 ufp – 1 1 – – – – – SP←(SP +$0001); Pull (X) ROL opr8a Rotate Left through Carry DIR 39 dd 5 rfwpp ROLA INH 49 1 p ROLX INH 59 1 p ROL oprx8,X C IX1 69 ff 5 rfwpp ↕ 1 1 – –↕ ↕ ↕ ROL ,X b7 b0 IX 79 4 rfwp ROL oprx8,SP SP1 9E 69 ff 6 prfwpp ROR opr8a Rotate Right through Carry DIR 36 dd 5 rfwpp RORA INH 46 1 p RORX INH 56 1 p ROR oprx8,X C IX1 66 ff 5 rfwpp ↕ 1 1 – –↕ ↕ ↕ ROR ,X b7 b0 IX 76 4 rfwp ROR oprx8,SP SP1 9E 66 ff 6 prfwpp MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 129

Chapter7 Central Processor Unit (S08CPUV3) Table7-2. Instruction Set Summary (Sheet 7 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C Reset Stack Pointer (Low Byte) RSP SPL← $FF INH 9C 1 p – 1 1 – – – – – (High Byte Not Affected) Return from Interrupt SP← (SP) + $0001; Pull (CCR) SP← (SP) + $0001; Pull (A) RTI INH 80 9 uuuuufppp ↕ 1 1 ↕ ↕ ↕ ↕ ↕ SP← (SP) + $0001; Pull (X) SP← (SP) + $0001; Pull (PCH) SP← (SP) + $0001; Pull (PCL) Return from Subroutine RTS SP← SP + $0001;Pull (PCH) INH 81 5 ufppp – 1 1 – – – – – SP← SP + $0001; Pull (PCL) SBC #opr8i IMM A2 ii 2 pp SBC opr8a DIR B2 dd 3 rpp SBC opr16a EXT C2 hh ll 4 prpp SBC oprx16,X Subtract with Carry IX2 D2 ee ff 4 prpp ↕ 1 1 – –↕ ↕ ↕ SBC oprx8,X A← (A) – (M) – (C) IX1 E2 ff 3 rpp SBC ,X IX F2 3 rfp SBC oprx16,SP SP2 9E D2 ee ff 5 pprpp SBC oprx8,SP SP1 9E E2 ff 4 prpp Set Carry Bit SEC INH 99 1 p – 1 1 – – – – 1 (C← 1) Set Interrupt Mask Bit SEI INH 9B 1 p – 1 1 – 1 – – – (I← 1) STA opr8a DIR B7 dd 3 wpp STA opr16a EXT C7 hh ll 4 pwpp STA oprx16,X IX2 D7 ee ff 4 pwpp Store Accumulator in Memory STA oprx8,X IX1 E7 ff 3 wpp 0 1 1 – –↕ ↕ – M←(A) STA ,X IX F7 2 wp STA oprx16,SP SP2 9E D7 ee ff 5 ppwpp STA oprx8,SP SP1 9E E7 ff 4 pwpp STHXopr8a DIR 35 dd 4 wwpp Store H:X (Index Reg.) STHXopr16a EXT 96 hh ll 5 pwwpp 0 1 1 – –↕ ↕ – (M:M + $0001)← (H:X) STHX oprx8,SP SP1 9E FF ff 5 pwwpp Enable Interrupts: Stop Processing STOP Refer to MCU Documentation INH 8E 2 fp... – 1 1 – 0 – – – I bit← 0; Stop Processing STX opr8a DIR BF dd 3 wpp STX opr16a EXT CF hh ll 4 pwpp STX oprx16,X Store X (Low 8 Bits of Index Register) IX2 DF ee ff 4 pwpp STX oprx8,X in Memory IX1 EF ff 3 wpp 0 1 1 – –↕ ↕ – STX ,X M←(X) IX FF 2 wp STX oprx16,SP SP2 9E DF ee ff 5 ppwpp STX oprx8,SP SP1 9E EF ff 4 pwpp MC9S08DZ60 Series Data Sheet, Rev. 4 130 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV3) Table7-2. Instruction Set Summary (Sheet 8 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C SUB #opr8i IMM A0 ii 2 pp SUB opr8a DIR B0 dd 3 rpp SUB opr16a EXT C0 hh ll 4 prpp SUB oprx16,X Subtract IX2 D0 ee ff 4 prpp ↕ 1 1 – –↕ ↕ ↕ SUB oprx8,X A← (A) – (M) IX1 E0 ff 3 rpp SUB ,X IX F0 3 rfp SUB oprx16,SP SP2 9E D0 ee ff 5 pprpp SUB oprx8,SP SP1 9E E0 ff 4 prpp Software Interrupt PC← (PC) + $0001 Push (PCL); SP← (SP) – $0001 Push (PCH); SP← (SP) – $0001 Push (X); SP← (SP) – $0001 SWI INH 83 11 sssssvvfppp – 1 1 – 1 – – – Push (A); SP← (SP) – $0001 Push (CCR); SP← (SP) – $0001 I← 1; PCH← Interrupt Vector High Byte PCL← Interrupt Vector Low Byte Transfer Accumulator to CCR TAP INH 84 1 p ↕ 1 1 ↕ ↕ ↕ ↕ ↕ CCR← (A) Transfer Accumulator to X (Index Register TAX Low) INH 97 1 p – 1 1 – – – – – X← (A) Transfer CCR to Accumulator TPA INH 85 1 p – 1 1 – – – – – A← (CCR) TST opr8a Test for Negative or Zero (M) – $00 DIR 3D dd 4 rfpp TSTA (A) – $00 INH 4D 1 p TSTX (X) – $00 INH 5D 1 p 0 1 1 – –↕ ↕ – TST oprx8,X (M) – $00 IX1 6D ff 4 rfpp TST ,X (M) – $00 IX 7D 3 rfp TST oprx8,SP (M) – $00 SP1 9E 6D ff 5 prfpp Transfer SP to Index Reg. TSX INH 95 2 fp – 1 1 – – – – – H:X← (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator TXA INH 9F 1 p – 1 1 – – – – – A← (X) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 131

Chapter7 Central Processor Unit (S08CPUV3) Table7-2. Instruction Set Summary (Sheet 9 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C Transfer Index Reg. to SP TXS INH 94 2 fp – 1 1 – – – – – SP← (H:X) – $0001 Enable Interrupts; Wait for Interrupt WAIT INH 8F 2+ fp... – 1 1 – 0 – – – I bit← 0; Halt CPU Source Form: Everything in the source forms columns, except expressions in italic characters, is literal information which must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic and the characters (#, ( ) and +) are always a literal characters. n Any label or expression that evaluates to a single integer in the range 0-7. opr8i Any label or expression that evaluates to an 8-bit immediate value. opr16i Any label or expression that evaluates to a 16-bit immediate value. opr8a Any label or expression that evaluates to an 8-bit direct-page address ($00xx). opr16a Any label or expression that evaluates to a 16-bit address. oprx8 Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing. oprx16 Any label or expression that evaluates to a 16-bit value, used for indexed addressing. rel Any label or expression that refers to an address that is within –128 to +127 locations from the start of the next instruction. Operation Symbols: Addressing Modes: A Accumulator DIR Direct addressing mode CCR Condition code register EXT Extended addressing mode H Index register high byte IMM Immediate addressing mode M Memory location INH Inherent addressing mode n Any bit IX Indexed, no offset addressing mode opr Operand (one or two bytes) IX1 Indexed, 8-bit offset addressing mode PC Program counter IX2 Indexed, 16-bit offset addressing mode PCH Program counter high byte IX+ Indexed, no offset, post increment addressing mode PCL Program counter low byte IX1+ Indexed, 8-bit offset, post increment addressing mode rel Relative program counter offset byte REL Relative addressing mode SP Stack pointer SP1 Stack pointer, 8-bit offset addressing mode SPL Stack pointer low byte SP2 Stack pointer 16-bit offset addressing mode X Index register low byte Cycle-by-Cycle Codes: & Logical AND f Free cycle. This indicates a cycle where the CPU | Logical OR ⊕ does not require use of the system buses. An f Logical EXCLUSIVE OR cycle is always one cycle of the system bus clock ( ) Contents of + Add and is always a read cycle. p Program fetch; read from next consecutive – Subtract, Negation (two’s complement) × Multiply location in program memory ÷ Divide r Read 8-bit operand s Push (write) one byte onto stack # Immediate value ← Loaded with u Pop (read) one byte from stack v Read vector from $FFxx (high byte first) : Concatenated with w Write 8-bit operand CCR Bits: CCR Effects: V Overflow bit ↕ Set or cleared H Half-carry bit – Not affected I Interrupt mask U Undefined N Negative bit Z Zero bit C Carry/borrow bit MC9S08DZ60 Series Data Sheet, Rev. 4 132 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV3) Table7-3. Opcode Map (Sheet 1 of 2) Bit-Manipulation Branch Read-Modify-Write Control Register/Memory 00 5 10 5 20 3 30 5 40 1 50 1 60 5 70 4 80 9 90 3 A0 2 B0 3 C0 4 D0 4 E0 3 F0 3 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI BGE SUB SUB SUB SUB SUB SUB 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 01 5 11 5 21 3 31 5 41 4 51 4 61 5 71 5 81 6 91 3 A1 2 B1 3 C1 4 D1 4 E1 3 F1 3 BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ RTS BLT CMP CMP CMP CMP CMP CMP 3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 02 5 12 5 22 3 32 5 42 5 52 6 62 1 72 1 82 5+ 92 3 A2 2 B2 3 C2 4 D2 4 E2 3 F2 3 BRSET1 BSET1 BHI LDHX MUL DIV NSA DAA BGND BGT SBC SBC SBC SBC SBC SBC 3 DIR 2 DIR 2 REL 3 EXT 1 INH 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 03 5 13 5 23 3 33 5 43 1 53 1 63 5 73 4 83 11 93 3 A3 2 B3 3 C3 4 D3 4 E3 3 F3 3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI BLE CPX CPX CPX CPX CPX CPX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 04 5 14 5 24 3 34 5 44 1 54 1 64 5 74 4 84 1 94 2 A4 2 B4 3 C4 4 D4 4 E4 3 F4 3 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR TAP TXS AND AND AND AND AND AND 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 05 5 15 5 25 3 35 4 45 3 55 4 65 3 75 5 85 1 95 2 A5 2 B5 3 C5 4 D5 4 E5 3 F5 3 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT 3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 06 5 16 5 26 3 36 5 46 1 56 1 66 5 76 4 86 3 96 5 A6 2 B6 3 C6 4 D6 4 E6 3 F6 3 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR PULA STHX LDA LDA LDA LDA LDA LDA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 3 EXT 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 07 5 17 5 27 3 37 5 47 1 57 1 67 5 77 4 87 2 97 1 A7 2 B7 3 C7 4 D7 4 E7 3 F7 2 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR PSHA TAX AIS STA STA STA STA STA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 08 5 18 5 28 3 38 5 48 1 58 1 68 5 78 4 88 3 98 1 A8 2 B8 3 C8 4 D8 4 E8 3 F8 3 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 09 5 19 5 29 3 39 5 49 1 59 1 69 5 79 4 89 2 99 1 A9 2 B9 3 C9 4 D9 4 E9 3 F9 3 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0A 5 1A 5 2A 3 3A 5 4A 1 5A 1 6A 5 7A 4 8A 3 9A 1 AA 2 BA 3 CA 4 DA 4 EA 3 FA 3 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC PULH CLI ORA ORA ORA ORA ORA ORA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0B 5 1B 5 2B 3 3B 7 4B 4 5B 4 6B 7 7B 6 8B 2 9B 1 AB 2 BB 3 CB 4 DB 4 EB 3 FB 3 BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD 3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 INH 3 IX1 2 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0C 5 1C 5 2C 3 3C 5 4C 1 5C 1 6C 5 7C 4 8C 1 9C 1 BC 3 CC 4 DC 4 EC 3 FC 3 BRSET6 BSET6 BMC INC INCA INCX INC INC CLRH RSP JMP JMP JMP JMP JMP 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0D 5 1D 5 2D 3 3D 4 4D 1 5D 1 6D 4 7D 3 9D 1 AD 5 BD 5 CD 6 DD 6 ED 5 FD 5 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0E 5 1E 5 2E 3 3E 6 4E 5 5E 5 6E 4 7E 5 8E 2+ 9E AE 2 BE 3 CE 4 DE 4 EE 3 FE 3 BRSET7 BSET7 BIL CPHX MOV MOV MOV MOV STOP Page 2 LDX LDX LDX LDX LDX LDX 3 DIR 2 DIR 2 REL 3 EXT 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0F 5 1F 5 2F 3 3F 5 4F 1 5F 1 6F 5 7F 4 8F 2+ 9F 1 AF 2 BF 3 CF 4 DF 4 EF 3 FF 2 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA AIX STX STX STX STX STX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Opcode in Hexadecimal F0 3 HCS08 Cycles SUB Instruction Mnemonic Number of Bytes 1 IX Addressing Mode MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 133

Chapter7 Central Processor Unit (S08CPUV3) Table7-3. Opcode Map (Sheet 2 of 2) Bit-Manipulation Branch Read-Modify-Write Control Register/Memory 9E60 6 9ED0 5 9EE0 4 NEG SUB SUB 3 SP1 4 SP2 3 SP1 9E61 6 9ED1 5 9EE1 4 CBEQ CMP CMP 4 SP1 4 SP2 3 SP1 9ED2 5 9EE2 4 SBC SBC 4 SP2 3 SP1 9E63 6 9ED3 5 9EE3 4 9EF3 6 COM CPX CPX CPHX 3 SP1 4 SP2 3 SP1 3 SP1 9E64 6 9ED4 5 9EE4 4 LSR AND AND 3 SP1 4 SP2 3 SP1 9ED5 5 9EE5 4 BIT BIT 4 SP2 3 SP1 9E66 6 9ED6 5 9EE6 4 ROR LDA LDA 3 SP1 4 SP2 3 SP1 9E67 6 9ED7 5 9EE7 4 ASR STA STA 3 SP1 4 SP2 3 SP1 9E68 6 9ED8 5 9EE8 4 LSL EOR EOR 3 SP1 4 SP2 3 SP1 9E69 6 9ED9 5 9EE9 4 ROL ADC ADC 3 SP1 4 SP2 3 SP1 9E6A 6 9EDA 5 9EEA 4 DEC ORA ORA 3 SP1 4 SP2 3 SP1 9E6B 8 9EDB 5 9EEB 4 DBNZ ADD ADD 4 SP1 4 SP2 3 SP1 9E6C 6 INC 3 SP1 9E6D 5 TST 3 SP1 9EAE 5 9EBE 6 9ECE 5 9EDE 5 9EEE 4 9EFE 5 LDHX LDHX LDHX LDX LDX LDHX 2 IX 4 IX2 3 IX1 4 SP2 3 SP1 3 SP1 9E6F 6 9EDF 5 9EEF 4 9EFF 5 CLR STX STX STHX 3 SP1 4 SP2 3 SP1 3 SP1 INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Prebyte (9E) and Opcode in Hexadecimal 9E60 6 HCS08 Cycles NEG Instruction Mnemonic Number of Bytes 3 SP1 Addressing Mode MC9S08DZ60 Series Data Sheet, Rev. 4 134 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.1 Introduction The multi-purpose clock generator (MCG) module provides several clock source choices for the MCU. Themodulecontainsafrequency-lockedloop(FLL)andaphase-lockedloop(PLL)thatarecontrollable byeitheraninternaloranexternalreferenceclock.ThemodulecanselecteitheroftheFLLorPLLclocks, or either of the internal or external reference clocks as a source for the MCU system clock. Whichever clock source is chosen, it is passed through a reduced bus divider which allows a lower output clock frequencytobederived.TheMCGalsocontrolsanexternaloscillator(XOSC)fortheuseofacrystalor resonator as the external reference clock. All devices in the MC9S08DZ60 Series feature the MCG module. NOTE RefertoSection1.3,“SystemClockDistribution,”fordetailedviewofthe distribution clock sources throughout the chip. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 135

Chapter8 Multi-Purpose Clock Generator (S08MCGV1) HCS08 CORE PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 CPU ANALOG COMPARATOR ACMP1O ORT A PPTTAA34//PPIIAA34//AADDPP34/ACMP1O BKGD/MS (ACMP1) ACMP1- P PTA2/PIA2/ADP2/ACMP1- BDC BKP ACMP1+ PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK HCS08 SYSTEM CONTROL PTB7/PIB7/ADP15 RESET RESETS AND INTERRUPTS PTB6/PIB6/ADP14 MODES OF OPERATION PTB5/PIB5/ADP13 POWER MANAGEMENT T B PTB4/PIB4/ADP12 OR PTB3/PIB3/ADP11 8 P PTB2/PIB2/ADP10 COP LVD Q PTB1/PIB1/ADP9 R INT IRQ I ADP7-ADP0 PTB0/PIB0/ADP8 24-CHANNEL,12-BIT PTC7/ADP23 ADP15-ADP8 ANALOG-TO-DIGITAL PTC6/ADP22 VREFH CONVERTER (ADC) ADP23-ADP16 PTC5/ADP21 V VREFL T C PTC4/ADP20 DDA OR PTC3/ADP19 VSSA P PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 USER FLASH TPM1CH5 - PTD7/PID7/TPM1CH5 MC9S0DZ60 = 60K 6-CHANNEL TIMER/PWM TPM1CH0 6 MC9S0DZ48 = 48K MODULE (TPM1) TPM1CLK PTD6/PID6/TPM1CH4 MC9S0DZ32 = 32K PTD5/PID5/TPM1CH3 MC9S0DZ16 = 16K T D PTD4/PID4/TPM1CH2 TPM2CH1, OR PTD3/PID3/TPM1CH1 2-CHANNEL TIMER/PWM TPM2CH0 P PTD2/PID2/TPM1CH0 MODULE (TPM2) TPM2CLK PTD1/PID1/TPM2CH1 USER EEPROM PTD0/PID0/TPM2CH0 MC9S0DZ60 = 2K CONTROLLER AREA RxCAN PTE7/RxD2/RXCAN NETWORK (MSCAN) TxCAN PTE6/TxD2/TXCAN MISO PTE5/SDA/MISO MCU9SS0EDRZ R60A M= 4K INTSEERRFIAALC EP EMROIPDHUELREA (SLPI) SMPOSSCIK ORT E PPTTEE34//SSPCSL/CMKOSI SS P PTE2/SS RxD1 PTE1/RxD1 DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1 PTE0/TxD1 INTERFACE (SCI1) PTF7 ACMP2O ANALOG COMPARATOR PTF6/ACMP2O REAL-TIME COUNTER (RTC) (ACMP2) ACMP2- PTF5/ACMP2- ACMP2+ VVDDDD VOLTAGE IIC MODULE (IIC) SSCDLA PORT F PPPTTTFFF342///TATPPCMMM21PCC2LL+KK//SSDCAL RxD2 VSS REGULATOR PTF1/RxD2 V SERIAL COMMUNICATIONS TxD2 SS PTF0/TxD2 INTERFACE (SCI2) PTG5 MULTI-PURPOSE PTG4 CLOCK GENERATOR G PTG3 (MCG) T R PTG2 XTAL PO PTG1/XTAL OSCILLATOR (XOSC) EXTAL PTG0/EXTAL - V /V internally connected to V /V in 48-pin and 32-pin packages - Pin not connected in 48-pin and 32-pin packages REFH REFL DDA SSA - V and V pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package DD SS Figure8-1. MC9S08DZ60 Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 136 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.1.1 Features Key features of the MCG module are: • Frequency-locked loop (FLL) — 0.2% resolution using internal 32-kHz reference — 2% deviation over voltage and temperature using internal 32-kHz reference — Internal or external reference can be used to control the FLL • Phase-locked loop (PLL) — Voltage-controlled oscillator (VCO) — Modulo VCO frequency divider — Phase/Frequency detector — Integrated loop filter — Lock detector with interrupt capability • Internal reference clock — Nine trim bits for accuracy — Can be selected as the clock source for the MCU • External reference clock — Control for external oscillator — Clock monitor with reset capability — Can be selected as the clock source for the MCU • Reference divider is provided • Clock source selected can be divided down by 1, 2, 4, or 8 • BDC clock (MCGLCLK) is provided as a constant divide by 2 of the DCO output whether in an FLL or PLL mode. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 137

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) External Oscillator (XOSC) MCGERCLK ERCLKEN RANGE EREFS HGO EREFSTEN IRCLKEN MCGIRCLK CME IREFSTEN CLKS BDIV Clock Monitor / 2n Internal MCGOUT n=0-3 Reference LP LOC OSCINIT Clock IREFS 9 DCO DCOOUT TRIM Lock PLLS Detector / 2n RDIV_CLK Filter n=0-7 FLL LOLS LOCK MCGFFCLK RDIV LP MCGFFCLKVALID VCOOUT / 2 MCGLCLK Phase Charge Detector Pump VCO Internal VDIV Filter PLL /(4,8,12,...,40) Multi-purpose Clock Generator (MCG) Figure8-2. Multi-Purpose Clock Generator (MCG) Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 138 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.1.2 Modes of Operation There are nine modes of operation for the MCG: • FLL Engaged Internal (FEI) • FLL Engaged External (FEE) • FLL Bypassed Internal (FBI) • FLL Bypassed External (FBE) • PLL Engaged External (PEE) • PLL Bypassed External (PBE) • Bypassed Low Power Internal (BLPI) • Bypassed Low Power External (BLPE) • Stop For details seeSection8.4.1, “Operational Modes. 8.2 External Signal Description There are no MCG signals that connect off chip. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 139

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.3 Register Definition 8.3.1 MCG Control Register 1 (MCGC1) 7 6 5 4 3 2 1 0 R CLKS RDIV IREFS IRCLKEN IREFSTEN W Reset: 0 0 0 0 0 1 0 0 Figure8-3. MCG Control Register 1 (MCGC1) Table8-1. MCG Control Register 1 Field Descriptions Field Description 7:6 Clock Source Select — Selects the system clock source. CLKS 00 Encoding 0 — Output of FLL or PLL is selected. 01 Encoding 1 — Internal reference clock is selected. 10 Encoding 2 — External reference clock is selected. 11 Encoding 3 — Reserved, defaults to 00. 5:3 Reference Divider — Selects the amount to divide down the reference clock selected by the IREFS bit. If the RDIV FLLisselected,theresultingfrequencymustbeintherange31.25kHzto39.0625kHz.IfthePLLisselected, the resulting frequency must be in the range 1 MHz to 2 MHz. 000 Encoding 0 — Divides reference clock by 1 (reset default) 001 Encoding 1 — Divides reference clock by 2 010 Encoding 2 — Divides reference clock by 4 011 Encoding 3 — Divides reference clock by 8 100 Encoding 4 — Divides reference clock by 16 101 Encoding 5 — Divides reference clock by 32 110 Encoding 6 — Divides reference clock by 64 111 Encoding 7 — Divides reference clock by 128 2 Internal Reference Select — Selects the reference clock source. IREFS 1 Internal reference clock selected 0 External reference clock selected 1 Internal Reference Clock Enable — Enables the internal reference clock for use as MCGIRCLK. IRCLKEN 1 MCGIRCLK active 0 MCGIRCLK inactive 0 InternalReferenceStopEnable—Controlswhetherornottheinternalreferenceclockremainsenabledwhen IREFSTEN the MCG enters stop mode. 1 InternalreferenceclockstaysenabledinstopifIRCLKENissetorifMCGisinFEI,FBI,orBLPImodebefore entering stop 0 Internal reference clock is disabled in stop MC9S08DZ60 Series Data Sheet, Rev. 4 140 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.3.2 MCG Control Register 2 (MCGC2) 7 6 5 4 3 2 1 0 R BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN W Reset: 0 1 0 0 0 0 0 0 Figure8-4. MCG Control Register 2 (MCGC2) Table8-2. MCG Control Register 2 Field Descriptions Field Description 7:6 BusFrequencyDivider—SelectstheamounttodividedowntheclocksourceselectedbytheCLKSbitsinthe BDIV MCGC1 register. This controls the bus frequency. 00 Encoding 0 — Divides selected clock by 1 01 Encoding 1 — Divides selected clock by 2 (reset default) 10 Encoding 2 — Divides selected clock by 4 11 Encoding 3 — Divides selected clock by 8 5 Frequency Range Select — Selects the frequency range for the external oscillator or external clock source. RANGE 1 High frequency range selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external clock source) 0 Low frequency range selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external clock source) 4 High Gain Oscillator Select — Controls the external oscillator mode of operation. HGO 1 Configure external oscillator for high gain operation 0 Configure external oscillator for low power operation 3 Low Power Select — Controls whether the FLL (or PLL) is disabled in bypassed modes. LP 1 FLL (or PLL) is disabled in bypass modes (lower power). 0 FLL (or PLL) is not disabled in bypass modes. 2 External Reference Select — Selects the source for the external reference clock. EREFS 1 Oscillator requested 0 External Clock Source requested 1 External Reference Enable — Enables the external reference clock for use as MCGERCLK. ERCLKEN 1 MCGERCLK active 0 MCGERCLK inactive 0 ExternalReferenceStopEnable—Controlswhetherornottheexternalreferenceclockremainsenabledwhen EREFSTEN the MCG enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, or BLPE mode before entering stop 0 External reference clock is disabled in stop MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 141

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.3.3 MCG Trim Register (MCGTRM) 7 6 5 4 3 2 1 0 R TRIM W POR: 1 0 0 0 0 0 0 0 Reset: U U U U U U U U Figure8-5. MCG Trim Register (MCGTRM) Table8-3. MCG Trim Register Field Descriptions Field Description 7:0 MCGTrimSetting—Controlstheinternalreferenceclockfrequencybycontrollingtheinternalreferenceclock TRIM period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period. An additional fine trim bit is available in MCGSC as the FTRIM bit. If a TRIM[7:0] value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value from the nonvolatile memory location to this register. MC9S08DZ60 Series Data Sheet, Rev. 4 142 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.3.4 MCG Status and Control Register (MCGSC) 7 6 5 4 3 2 1 0 R LOLS LOCK PLLST IREFST CLKST OSCINIT FTRIM W POR: 0 0 0 1 0 0 0 0 Reset: 0 0 0 1 0 0 0 U Figure8-6. MCG Status and Control Register (MCGSC) Table8-4. MCG Status and Control Register Field Descriptions Field Description 7 Loss of Lock Status— This bit is a sticky indication of lock status for the FLL or PLL. LOLS is set when lock LOLS detection is enabled and after acquiring lock, the FLL or PLL output frequency has fallen outside the lock exit frequencytolerance,D .LOLIEdetermineswhetheraninterruptrequestismadewhenset.LOLSisclearedby unl reset or by writing a logic 1 to LOLS when LOLS is set. Writing a logic 0 to LOLS has no effect. 0 FLL or PLL has not lost lock since LOLS was last cleared. 1 FLL or PLL has lost lock since LOLS was last cleared. 6 Lock Status— Indicates whether the FLL or PLL has acquired lock. Lock detection is disabled when both the LOCK FLLandPLLaredisabled.IfthelockstatusbitissetthenchangingthevalueofanyofthefollowingbitsIREFS, PLLS,RDIV[2:0],TRIM[7:0](ifinFEIorFBImodes),orVDIV[3:0](ifinPBEorPEEmodes),willcausethelock statusbittoclearandstaycleareduntiltheFLLorPLLhasreacquiredlock.Stopmodeentrywillalsocausethe lockstatusbittoclearandstaycleareduntiltheFLLorPLLhasreacquiredlock.EntryintoBLPIorBLPEmode will also cause the lock status bit to clear and stay cleared until the MCG has exited these modes and the FLL or PLL has reacquired lock. 0 FLL or PLL is currently unlocked. 1 FLL or PLL is currently locked. 5 PLL Select Status — The PLLST bit indicates the current source for the PLLS clock. The PLLST bit does not PLLST update immediately after a write to the PLLS bit due to internal synchronization between clock domains. 0 Source of PLLS clock is FLL clock. 1 Source of PLLS clock is PLL clock. 4 InternalReferenceStatus—TheIREFSTbitindicatesthecurrentsourceforthereferenceclock.TheIREFST IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains. 0 Sourceofreferenceclockisexternalreferenceclock(oscillatororexternalclocksourceasdeterminedbythe EREFS bit in the MCGC2 register). 1 Source of reference clock is internal reference clock. 3:2 Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits do not update CLKST immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Encoding 0 — Output of FLL is selected. 01 Encoding 1 — Internal reference clock is selected. 10 Encoding 2 — External reference clock is selected. 11 Encoding 3 — Output of PLL is selected. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 143

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) Table8-4. MCG Status and Control Register Field Descriptions (continued) Field Description 1 OSCInitialization—IftheexternalreferenceclockisselectedbyERCLKENorbytheMCGbeinginFEE,FBE, OSCINIT PEE, PBE, or BLPE mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator clock have completed. This bit is only cleared when either EREFS is cleared or when the MCG is in either FEI, FBI, or BLPI mode and ERCLKEN is cleared. 0 MCG Fine Trim — Controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount possible. IfanFTRIMvaluestoredinnonvolatilememoryistobeused,it’stheuser’sresponsibilitytocopythatvaluefrom the nonvolatile memory location to this register’s FTRIM bit. 8.3.5 MCG Control Register 3 (MCGC3) 7 6 5 4 3 2 1 0 R 0 LOLIE PLLS CME VDIV W Reset: 0 0 0 0 0 0 0 1 Figure8-7. MCG PLL Register (MCGPLL) Table8-5. MCG PLL Register Field Descriptions Field Description 7 LossofLockInterruptEnable—Determinesifaninterruptrequestismadefollowingalossoflockindication. LOLIE The LOLIE bit only has an effect when LOLS is set. 0 No request on loss of lock. 1 Generate an interrupt request on loss of lock. 6 PLL Select — Controls whether the PLL or FLL is selected. If the PLLS bit is clear, the PLL is disabled in all PLLS modes. If the PLLS is set, the FLL is disabled in all modes. 1 PLL is selected 0 FLL is selected MC9S08DZ60 Series Data Sheet, Rev. 4 144 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) Table8-5. MCG PLL Register Field Descriptions (continued) Field Description 5 ClockMonitorEnable—Determinesifaresetrequestismadefollowingalossofexternalclockindication.The CME CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled (ERCLKEN=1 in the MCGC2 register).WhenevertheCMEbitissettoalogic1,thevalueoftheRANGEbitintheMCGC2registershouldnot be changed. 0 Clock monitor is disabled. 1 Generate a reset request on loss of external clock. 3:0 VCO Divider— Selects the amount to divide down the VCO output of PLL. The VDIV bits establish the VDIV multiplication factor (M) applied to the reference clock frequency. 0000Encoding 0 — Reserved. 0001Encoding 1 — Multiply by 4. 0010Encoding 2 — Multiply by 8. 0011Encoding 3 — Multiply by 12. 0100Encoding 4 — Multiply by 16. 0101Encoding 5 — Multiply by 20. 0110Encoding 6 — Multiply by 24. 0111Encoding 7 — Multiply by 28. 1000Encoding 8 — Multiply by 32. 1001Encoding 9 — Multiply by 36. 1010Encoding 10 — Multiply by 40. 1011Encoding 11 — Reserved (default to M=40). 11xxEncoding 12-15 — Reserved (default to M=40). MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 145

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.4 Functional Description 8.4.1 Operational Modes IREFS=1 IREFS=0 CLKS=00 FLL Engaged FLL Engaged CLKS=00 PLLS=0 Internal (FEI) External (FEE) PLLS=0 IREFS=1 IREFS=0 CLKS=01 CLKS=10 PLLS=0 PLLS=0 BDM Enabled FLL Bypassed FLL Bypassed BDM Enabled or LP=0 or LP=0 Internal (FBI) External (FBE) Bypassed Bypassed IREFS=0 IREFS=1 Low Power Low Power CLKS=10 CLKS=01 Internal (BLPI) External(BLPE) BDM Disabled PLLS=0 and LP=1 BDM Disabled and LP=1 PLL Bypassed IREFS=0 External (PBE) CLKS=10 PLLS=1 BDM Enabled or LP=0 PLL Engaged IREFS=0 External (PEE) CLKS=00 PLLS=1 Returns to state that was active Entered from any state Stop before MCU entered stop, unless when MCU enters stop RESET occurs while in stop. Figure8-8. Clock Switching Modes MC9S08DZ60 Series Data Sheet, Rev. 4 146 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) TheninestatesoftheMCGareshownasastatediagramandaredescribedbelow.Thearrowsindicatethe allowed movements between the states. 8.4.1.1 FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following conditions occur: • CLKS bits are written to 00 • IREFS bit is written to 1 • PLLS bit is written to 0 • RDIVbitsarewrittento000.Sincetheinternalreferenceclockfrequencyshouldalreadybeinthe range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary. InFLLengagedinternalmode,theMCGOUTclockisderivedfromtheFLLclock,whichiscontrolledby the internal reference clock. The FLL clock frequency locks to 1024 times the reference frequency, as selectedbytheRDIVbits.TheMCGLCLKisderivedfromtheFLLandthePLLisdisabledinalowpower state. 8.4.1.2 FLL Engaged External (FEE) The FLL engaged external (FEE) mode is entered when all the following conditions occur: • CLKS bits are written to 00 • IREFS bit is written to 0 • PLLS bit is written to 0 • RDIVbitsarewrittentodividereferenceclocktobewithintherangeof31.25kHzto39.0625kHz InFLLengagedexternalmode,theMCGOUTclockisderivedfromtheFLLclockwhichiscontrolledby the external reference clock. The external reference clock which is enabled can be an external crystal/resonatororitcanbeanotherexternalclocksource.TheFLLclockfrequencylocksto1024times the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from the FLL and the PLL is disabled in a low power state. 8.4.1.3 FLL Bypassed Internal (FBI) In FLL bypassed internal (FBI) mode, the MCGOUT clock is derived from the internal reference clock andtheFLLisoperationalbutitsoutputclockisnotused.ThismodeisusefultoallowtheFLLtoacquire its target frequency while the MCGOUT clock is driven from the internal reference clock. The FLL bypassed internal mode is entered when all the following conditions occur: • CLKS bits are written to 01 • IREFS bit is written to 1 • PLLS bit is written to 0 • RDIVbitsarewrittento000.Sincetheinternalreferenceclockfrequencyshouldalreadybeinthe range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 147

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) • LP bit is written to 0 InFLLbypassedinternalmode,theMCGOUTclockisderivedfromtheinternalreferenceclock.TheFLL clock is controlled by the internal reference clock, and the FLL clock frequency locks to 1024 times the referencefrequency,asselectedbytheRDIVbits.TheMCGLCLKisderivedfromtheFLLandthePLL is disabled in a low power state. 8.4.1.4 FLL Bypassed External (FBE) InFLLbypassedexternal(FBE)mode,theMCGOUTclockisderivedfromtheexternalreferenceclock andtheFLLisoperationalbutitsoutputclockisnotused.ThismodeisusefultoallowtheFLLtoacquire its target frequency while the MCGOUT clock is driven from the external reference clock. The FLL bypassed external mode is entered when all the following conditions occur: • CLKS bits are written to 10 • IREFS bit is written to 0 • PLLS bit is written to 0 • RDIVbitsarewrittentodividereferenceclocktobewithintherangeof31.25kHzto39.0625kHz • LP bit is written to 0 In FLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The externalreferenceclockwhichisenabledcanbeanexternalcrystal/resonatororitcanbeanotherexternal clock source.The FLL clock is controlled by the external reference clock, and the FLL clock frequency locksto1024timesthereferencefrequency,asselectedbytheRDIVbits.TheMCGLCLKisderivedfrom the FLL and the PLL is disabled in a low power state. NOTE It is possible to briefly operate in FBE mode with an FLL reference clock frequencythatisgreaterthanthespecifiedmaximumfrequency.Thiscanbe necessaryinapplicationsthatoperateinPEEmodeusinganexternalcrystal with a frequency above 5 MHz. Please see8.5.2.4, “Example # 4: Moving fromFEItoPEEMode:ExternalCrystal=8MHz,BusFrequency=8MHz for a detailed example. 8.4.1.5 PLL Engaged External (PEE) The PLL engaged external (PEE) mode is entered when all the following conditions occur: • CLKS bits are written to 00 • IREFS bit is written to 0 • PLLS bit is written to 1 • RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz InPLLengagedexternalmode,theMCGOUTclockisderivedfromthePLLclockwhichiscontrolledby the external reference clock. The external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source The PLL clock frequency locks to a MC9S08DZ60 Series Data Sheet, Rev. 4 148 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) multiplicationfactor,asselectedbytheVDIVbits,timesthereferencefrequency,asselectedbytheRDIV bits.IfBDMisenabledthentheMCGLCLKisderivedfromtheDCO(open-loopmode)dividedbytwo. If BDM is not enabled then the FLL is disabled in a low power state. 8.4.1.6 PLL Bypassed External (PBE) InPLLbypassedexternal(PBE)mode,theMCGOUTclockisderivedfromtheexternalreferenceclock andthePLLisoperationalbutitsoutputclockisnotused.ThismodeisusefultoallowthePLLtoacquire its target frequency while the MCGOUT clock is driven from the external reference clock. The PLL bypassed external mode is entered when all the following conditions occur: • CLKS bits are written to 10 • IREFS bit is written to 0 • PLLS bit is written to 1 • RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz • LP bit is written to 0 In PLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The externalreferenceclockwhichisenabledcanbeanexternalcrystal/resonatororitcanbeanotherexternal clocksource.ThePLLclockfrequencylockstoamultiplicationfactor,asselectedbytheVDIVbits,times thereferencefrequency,asselectedbytheRDIVbits.IfBDMisenabledthentheMCGLCLKisderived fromtheDCO(open-loopmode)dividedbytwo.IfBDMisnotenabledthentheFLLisdisabledinalow power state. 8.4.1.7 Bypassed Low Power Internal (BLPI) The bypassed low power internal (BLPI) mode is entered when all the following conditions occur: • CLKS bits are written to 01 • IREFS bit is written to 1 • PLLS bit is written to 0 • LP bit is written to 1 • BDM mode is not active In bypassed low power internal mode, the MCGOUT clock is derived from the internal reference clock. ThePLLandtheFLLaredisabledatalltimesinBLPImodeandtheMCGLCLKwillnotbeavailablefor BDC communications If the BDM becomes active the mode will switch toFLL bypassed internal (FBI) mode. 8.4.1.8 Bypassed Low Power External (BLPE) The bypassed low power external (BLPE) mode is entered when all the following conditions occur: • CLKS bits are written to 10 • IREFS bit is written to 0 • PLLS bit is written to 0 or 1 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 149

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) • LP bit is written to 1 • BDM mode is not active Inbypassedlowpowerexternalmode,theMCGOUTclockisderivedfromtheexternalreferenceclock. The external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source. The PLL and the FLL are disabled at all times in BLPE mode and the MCGLCLK will not be available for BDC communications. If the BDM becomes active the mode will switch to one of the bypassed external modes as determined by the state of the PLLS bit. 8.4.1.9 Stop StopmodeisenteredwhenevertheMCUentersaSTOPstate.Inthismode,theFLLandPLLaredisabled and all MCG clock signals are static except in the following cases: MCGIRCLK will be active in stop mode when all the following conditions occur: • IRCLKEN = 1 • IREFSTEN = 1 MCGERCLK will be active in stop mode when all the following conditions occur: • ERCLKEN = 1 • EREFSTEN = 1 8.4.2 Mode Switching When switching between engaged internal and engaged external modes the IREFS bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the reference frequency stays in the rangerequiredbythestateofthePLLSbit(31.25kHzto39.0625kHziftheFLLisselected,or1MHzto 2MHzifthePLLisselected).AfterachangeintheIREFSvaluetheFLLorPLLwillbeginlockingagain after the switch is completed. The completion of the switch is shown by the IREFST bit . ForthespecialcaseofenteringstopmodeimmediatelyafterswitchingtoFBEmode,iftheexternalclock andtheinternalclockaredisabledinstopmode,(EREFSTEN=0andIREFSTEN=0),itisnecessaryto allow100usaftertheIREFSTbitisclearedtoallowtheinternalreferencetoshutdown.Formostcasesthe delay due to instruction execution times will be sufficient. TheCLKSbitscanalsobechangedatanytime,butinorderfortheMCGLCLKtobeconfiguredcorrectly theRDIVbitsmustbechangedsimultaneouslysothatthereferencefrequencystaysintherangerequired by the state of the PLLS bit (31.25 kHz to 39.0625 kHz if the FLL is selected, or 1 MHz to 2MHz if the PLL is selected). The actual switch to the newly selected clock will be shown by the CLKST bits. If the newly selected clock is not available, the previous clock will remain selected. For details seeFigure8-8. MC9S08DZ60 Series Data Sheet, Rev. 4 150 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.4.3 Bus Frequency Divider The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur immediately. 8.4.4 Low Power Bit Usage Thelowpowerbit(LP)isprovidedtoallowtheFLLorPLLtobedisabledandthusconservepowerwhen thesesystemsarenotbeingused.However,insomeapplicationsitmaybedesirabletoenabletheFLLor PLLandallowittolockformaximumaccuracybeforeswitchingtoanengagedmode.Dothisbywriting the LP bit to 0. 8.4.5 Internal Reference Clock WhenIRCLKENissettheinternalreferenceclocksignalwillbepresentedasMCGIRCLK,whichcanbe usedasanadditionalclocksource.TheMCGIRCLKfrequencycanbere-targetedbytrimmingtheperiod oftheinternalreferenceclock.ThiscanbedonebywritinganewvaluetotheTRIMbitsintheMCGTRM register. Writing a larger value will decrease the MCGIRCLK frequency, and writing a smaller value to theMCGTRMregisterwillincreasetheMCGIRCLKfrequency.TheTRIMbitswilleffecttheMCGOUT frequency if the MCG is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or bypassed low powerinternal(BLPI)mode.TheTRIMandFTRIMvalueisinitializedbyPORbutisnotaffectedbyother resets. Until MCGIRCLK is trimmed, programming low reference divider (RDIV) factors may result in MCGOUT frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing specifications (see theDevice Overview chapter). IfIREFSTENandIRCLKENbitsarebothset,theinternalreferenceclockwillkeeprunningduringstop mode in order to provide a fast recovery upon exiting stop. 8.4.6 External Reference Clock TheMCGmodulecansupportanexternalreferenceclockwithfrequenciesbetween31.25kHzto5MHz in FEE and FBE modes, 1 MHz to 16 MHz in PEE and PBE modes, and 0 to 40 MHz in BLPE mode. WhenERCLKENisset,theexternalreferenceclocksignalwillbepresentedasMCGERCLK,whichcan be used as an additional clock source. When IREFS = 1, the external reference clock will not be used by theFLLorPLLandwillonlybeusedasMCGERCLK.Inthesemodes,thefrequencycanbeequaltothe maximum frequency the chip-level timing specifications will support (see theDevice Overview chapter). If EREFSTEN and ERCLKEN bits are both set or the MCG is in FEE, FBE, PEE, PBE or BLPE mode, the external reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. If CME bit is written to 1, the clock monitor is enabled. If the external reference falls below a certain frequency(f orf dependingontheRANGEbitintheMCGC2),theMCUwillreset.TheLOC loc_high loc_low bit in the System Reset Status (SRS) register will be set to indicate the error. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 151

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.4.7 Fixed Frequency Clock TheMCGpresentsthedividedreferenceclockasMCGFFCLKforuseasanadditionalclocksource.The MCGFFCLKfrequencymustbenomorethan1/4oftheMCGOUTfrequencytobevalid.Becauseofthis requirement,theMCGFFCLKisnotvalidinbypassmodesforthefollowingcombinationsofBDIVand RDIV values: • BDIV=00 (divide by 1), RDIV< 010 • BDIV=01 (divide by 2), RDIV< 011 When MCGFFCLK is valid then MCGFFCLKVALID is set to 1. When MCGFFCLK is not valid then MCGFFCLKVALID is set to 0. 8.5 Initialization / Application Information This section describes how to initialize and configure the MCG module in application. The following sectionsincludeexamplesonhowtoinitializetheMCGandproperlyswitchbetweenthevariousavailable modes. 8.5.1 MCG Module Initialization Sequence The MCG comes out of reset configured for FEI mode with the BDIV set for divide-by-2. The internal reference will stabilize in t microseconds before the FLL can acquire lock. As soon as the internal irefst reference is stable, the FLL will acquire lock in t milliseconds. fll_lock Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale recommendsusingFLASHlocation0xFFAEforstoringthefinetrimbit,FTRIMintheMCGSCregister, and 0xFFAF for storing the 8-bit trim value in the MCGTRM register. The MCU will not automatically copythevaluesintheseFLASHlocationstotherespectiveregisters.Therefore,usercodemustcopythese values from FLASH to the registers. NOTE The BDIV value should not be changed to divide-by-1 without first trimming the internal reference. Failure to do so could result in the MCU running out of specification. 8.5.1.1 Initializing the MCG BecausetheMCGcomesoutofresetinFEImode,theonlyMCGmodeswhichcanbedirectlyswitched to upon reset are FEE, FBE, and FBI modes (seeFigure8-8). Reaching any of the other modes requires firstconfiguringtheMCGforoneofthesethreeinitialmodes.Caremustbetakentocheckrelevantstatus bits in the MCGSC register reflecting all configuration changes within each mode. To change from FEI mode to FEE or FBE modes, follow this procedure: 1. Enable the external clock source by setting the appropriate bits in MCGC2. 2. Write to MCGC1 to select the clock mode. MC9S08DZ60 Series Data Sheet, Rev. 4 152 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) — IfenteringFEE,setRDIVappropriately,cleartheIREFSbittoswitchtotheexternalreference, and leave the CLKS bits at %00 so that the output of the FLL is selected as the system clock source. — IfenteringFBE,cleartheIREFSbittoswitchtotheexternalreferenceandchangetheCLKS bits to %10 so that the external reference clock is selected as the system clock source. The RDIVbitsshouldalsobesetappropriatelyhereaccordingtotheexternalreferencefrequency because although the FLL is bypassed, it is still on in FBE mode. — The internal reference can optionally be kept running by setting the IRCLKEN bit. This is useful if the application will switch back and forth between internal and external modes. For minimumpowerconsumption,leavetheinternalreferencedisabledwhileinanexternalclock mode. 3. Aftertheproperconfigurationbitshavebeenset,waitfortheaffectedbitsintheMCGSCregister to be changed appropriately, reflecting that the MCG has moved into the proper mode. — If ERCLKEN was set in step 1 or the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and EREFSwasalsosetinstep1,waitherefortheOSCINITbittobecomesetindicatingthatthe externalclocksourcehasfinisheditsinitializationcyclesandstabilized.Typicalcrystalstartup times are given in Appendix A, “Electrical Characteristics”. — IfinFEEmode,checktomakesuretheIREFSTbitisclearedandtheLOCKbitissetbefore moving on. — If in FBE mode, check to make sure the IREFST bit is cleared, the LOCK bit is set, and the CLKST bits have changed to %10 indicating the external reference clock has been appropriatelyselected.AlthoughtheFLLisbypassedinFBEmode,itisstillonandwilllock in FBE mode. To change from FEI clock mode to FBI clock mode, follow this procedure: 1. Change the CLKS bits to %01 so that the internal reference clock is selected as the system clock source. 2. Wait for the CLKST bits in the MCGSC register to change to %01, indicating that the internal reference clock has been appropriately selected. 8.5.2 MCG Mode Switching When switching between operational modes of the MCG, certain configuration bits must be changed in ordertoproperlymovefromonemodetoanother.Eachtimeanyofthesebitsarechanged(PLLS,IREFS, CLKS, or EREFS), the corresponding bits in the MCGSC register (PLLST, IREFST, CLKST, or OSCINIT) must be checked before moving on in the application software. Additionally, care must be taken to ensure that the reference clock divider (RDIV) is set properly for the modebeingswitchedto.Forinstance,inPEEmode,ifusinga4MHzcrystal,RDIVmustbesetto%001 (divide-by-2) or %010 (divide -by-4) in order to divide the external reference down to the required frequency between 1 and 2 MHz. TheRDIVandIREFSbitsshouldalwaysbesetproperlybeforechangingthePLLSbitsothattheFLLor PLL clock has an appropriate reference clock frequency to switch to. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 153

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) ThetablebelowshowsMCGOUTfrequencycalculationsusingRDIV,BDIV,andVDIVsettingsforeach clock mode. The bus frequency is equal to MCGOUT divided by 2. Table8-6. MCGOUT Frequency Calculation Options Clock Mode f 1 Note MCGOUT FEI (FLL engaged internal) (f * 1024) / B Typical f = 16 MHz int MCGOUT immediately after reset. RDIV bits set to %000. FEE (FLL engaged external) (f / R *1024) / B f / R must be in the range of ext ext 31.25 kHz to 39.0625 kHz FBE (FLL bypassed external) f / B f / R must be in the range of ext ext 31.25 kHz to 39.0625 kHz FBI (FLL bypassed internal) f / B Typical f = 32 kHz int int PEE (PLL engaged external) [(f / R) * M] / B f / R must be in the range of 1 ext ext MHz to 2 MHz PBE (PLL bypassed external) f / B f / R must be in the range of 1 ext ext MHz to 2 MHz BLPI (Bypassed low power internal) f / B int BLPE (Bypassed low power external) f / B ext 1 RisthereferencedividerselectedbytheRDIVbits,BisthebusfrequencydividerselectedbytheBDIVbits, and M is the multiplier selected by the VDIV bits. Thissectionwillinclude3modeswitchingexamplesusinga4MHzexternalcrystal.Ifusinganexternal clock source less than 1 MHz, the MCG should not be configured for any of the PLL modes (PEE and PBE). 8.5.2.1 Example # 1: Moving from FEI to PEE Mode: External Crystal = 4 MHz, Bus Frequency = 8 MHz In this example, the MCG will move through the proper operational modes from FEI to PEE mode until the4MHzcrystalreferencefrequencyissettoachieveabusfrequencyof8MHz.BecausetheMCGisin FEImodeoutofreset,thisexamplealsoshowshowtoinitializetheMCGforPEEmodeoutofreset.First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1. First, FEI must transition to FBE mode: a) MCGC2 = 0x36 (%00110110) – BDIV (bits 7 and 6) set to %00, or divide-by-1 – RANGE(bit5)setto1becausethefrequencyof4MHziswithinthehighfrequencyrange – HGO (bit 4) set to 1 to configure external oscillator for high gain operation – EREFS (bit 2) set to 1, because a crystal is being used – ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit has been initialized. MC9S08DZ60 Series Data Sheet, Rev. 4 154 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) c) MCGC1 = 0xB8 (%10111000) – CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock source – RDIV(bits5-3)setto%111,ordivide-by-128because4MHz/128=31.25kHzwhichis in the 31.25 kHz to 39.0625 kHz range required by the FLL – IREFS (bit 2) cleared to 0, selecting the external reference clock d) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current source for the reference clock e) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference clock is selected to feed MCGOUT 2. Then, FBE must transition either directly to PBE mode or first through BLPE mode and then to PBE mode: a) BLPE: If a transition through BLPE mode is desired, first set LP (bit 3) in MCGC2 to 1. b) BLPE/PBE: MCGC1 = 0x90 (%10010000) – RDIV(bits5-3)setto%010,ordivide-by-4because4MHz/4=1MHzwhichisinthe1 MHz to 2 MHz range required by the PLL. In BLPE mode, the configuration of the RDIV doesnotmatterbecauseboththeFLLandPLLaredisabled.Changingthemonlysetsupthe the dividers for PLL usage in PBE mode c) BLPE/PBE: MCGC3 = 0x44 (%01000100) – PLLS (bit 6) set to 1, selects the PLL. In BLPE mode, changing this bit only prepares the MCG for PLL usage in PBE mode – VDIV(bits3-0)setto%0100,ormultiply-by-16because1MHzreference*16=16MHz. In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is disabled. Changing them only sets up the multiply value for PLL usage in PBE mode d) BLPE:IftransitioningthroughBLPEmode,clearLP(bit3)inMCGC2to0heretoswitchto PBE mode e) PBE: Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the PLLS clock is the PLL f) PBE:ThenloopuntilLOCK(bit6)inMCGSCisset,indicatingthatthePLLhasacquiredlock 3. Last, PBE mode transitions into PEE mode: a) MCGC1 = 0x10 (%00010000) – CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the system clock source b) LoopuntilCLKST(bits3and2)inMCGSCare%11,indicatingthatthePLLoutputisselected to feed MCGOUT in the current clock mode – Now,WithanRDIVofdivide-by-4,aBDIVofdivide-by-1,andaVDIVofmultiply-by-16, MCGOUT=[(4MHz/4)*16]/1=16MHz,andthebusfrequencyisMCGOUT/2,or8 MHz MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 155

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) START IN FEI MODE MCGC2 = $36 IN NO BLPE MODE ? (LP=1) CHECK NO OSCINIT = 1 ? YES MCGC2 = $36 YES (LP = 0) MCGC1 = $B8 CHECK NO PLLST = 1? CHECK NO IREFST = 0? YES YES CHECK NO LOCK = 1? CHECK NO CLKST = %10? YES YES MCGC1 = $10 ENTER NO BLPE MODE ? CHECK NO CLKST = %11? YES YES MCGC2 = $3E (LP = 1) CONTINUE IN PEE MODE MCGC1 = $90 MCGC3 = $44 Figure8-9. Flowchart of FEI to PEE Mode Transition using a 4 MHz crystal MC9S08DZ60 Series Data Sheet, Rev. 4 156 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.5.2.2 Example # 2: Moving from PEE to BLPI Mode: External Crystal = 4 MHz, Bus Frequency =16 kHz Inthisexample,theMCGwillmovethroughtheproperoperationalmodesfromPEEmodewitha4MHz crystal configured for an 8 MHz bus frequency (see previous example) to BLPI mode with a 16 kHz bus frequency.First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1. First, PEE must transition to PBE mode: a) MCGC1 = 0x90 (%10010000) – CLKS (bits 7 and 6) set to %10 in order to switch the system clock source to the external reference clock b) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference clock is selected to feed MCGOUT 2. Then, PBE must transition either directly to FBE mode or first through BLPE mode and then to FBE mode: a) BLPE: If a transition through BLPE mode is desired, first set LP (bit 3) in MCGC2 to 1 b) BLPE/FBE: MCGC1 = 0xB8 (%10111000) – RDIV(bits5-3)setto%111,ordivide-by-128because4MHz/128=31.25kHzwhichis in the 31.25 kHz to 39.0625 kHz range required by the FLL. In BLPE mode, the configuration of the RDIV does not matter because both the FLL and PLL are disabled. Changing them only sets up the dividers for FLL usage in FBE mode c) BLPE/FBE: MCGC3 = 0x04 (%00000100) – PLLS(bit6)clearto0toselecttheFLL.InBLPEmode,changingthisbitonlypreparesthe MCG for FLL usage in FBE mode. With PLLS = 0, the VDIV value does not matter. d) BLPE:IftransitioningthroughBLPEmode,clearLP(bit3)inMCGC2to0heretoswitchto FBE mode e) FBE: Loop until PLLST (bit 5) in MCGSC is clear, indicating that the current source for the PLLS clock is the FLL f) FBE: Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has acquired lock. Although the FLL is bypassed in FBE mode, it is still enabled and running. 3. Next, FBE mode transitions into FBI mode: a) MCGC1 = 0x44 (%01000100) – CLKS (bits7 and 6) in MCGSC1 set to %01 in order to switch the system clock to the internal reference clock – IREFS (bit 2) set to 1 to select the internal reference clock as the reference clock source – RDIV(bits5-3)setto%000,ordivide-by-1becausethetrimmedinternalreferenceshould be within the 31.25 kHz to 39.0625 kHz range required by the FLL b) Loop until IREFST (bit 4) in MCGSC is 1, indicating the internal reference clock has been selected as the reference clock source c) Loop until CLKST (bits 3 and 2) in MCGSC are %01, indicating that the internal reference clock is selected to feed MCGOUT MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 157

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 4. Lastly, FBI transitions intoBLPI mode. a) MCGC2 = 0x08 (%00001000) – LP (bit 3) in MCGSC is 1 START IN PEE MODE MCGC1 = $90 CHECK NO PLLST = 0? CHECK NO YES CLKST = %10 ? YES OPTIONAL: NO CHECK LOCK = 1? ENTER NO BLPE MODE ? YES MCGC1 = $44 YES MCGC2 = $3E CHECK NO IREFST = 0? MCGC1 = $B8 MCGC3 = $04 YES IN CHECK NO NO BLPE MODE ? CLKST = %01? (LP=1) YES YES MCGC2 = $08 MCGC2 = $36 (LP = 0) CONTINUE IN BLPI MODE Figure8-10. Flowchart of PEE to BLPI Mode Transition using a 4 MHz crystal MC9S08DZ60 Series Data Sheet, Rev. 4 158 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.5.2.3 Example #3: Moving from BLPI to FEE Mode: External Crystal = 4 MHz, Bus Frequency = 16 MHz Inthisexample,theMCGwillmovethroughtheproperoperationalmodesfromBLPImodeata16kHz bus frequency running off of the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 16 MHz bus frequency. First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1. First, BLPI must transition to FBI mode. a) MCGC2 = 0x00 (%00000000) – LP (bit 3) in MCGSC is 0 b) Optionally,loopuntilLOCK(bit6)intheMCGSCisset,indicatingthattheFLLhasacquired lock. Although the FLL is bypassed in FBI mode, it is still enabled and running. 2. Next, FBI will transition to FEE mode. a) MCGC2 = 0x36 (%00110110) – RANGE(bit5)setto1becausethefrequencyof4MHziswithinthehighfrequencyrange – HGO (bit 4) set to 1 to configure external oscillator for high gain operation – EREFS (bit 2) set to 1, because a crystal is being used – ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit has been initialized. c) MCGC1 = 0x38 (%00111000) – CLKS (bits 7 and 6) set to %00 in order to select the output of the FLL as system clock source – RDIV(bits5-3)setto%111,ordivide-by-128because4MHz/128=31.25kHzwhichis in the 31.25 kHz to 39.0625 kHz range required by the FLL – IREFS (bit 1) cleared to 0, selecting the external reference clock d) LoopuntilIREFST(bit4)inMCGSCis0,indicatingtheexternalreferenceclockisthecurrent source for the reference clock e) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has reacquired lock. f) LoopuntilCLKST(bits3and2)inMCGSCare%00,indicatingthattheoutputoftheFLLis selected to feed MCGOUT MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 159

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) START IN BLPI MODE CHECK NO IREFST = 0? MCGC2 = $00 YES OPTIONAL: NO OPTIONAL: NO CHECK LOCK CHECK LOCK = 1? = 1? YES YES MCGC2 = $36 CHECK NO CLKST = %00? CHECK NO YES OSCINIT = 1 ? CONTINUE YES IN FEE MODE MCGC1 = $38 Figure8-11. Flowchart of BLPI to FEE Mode Transition using a 4 MHz crystal 8.5.2.4 Example # 4: Moving from FEI to PEE Mode: External Crystal = 8 MHz, Bus Frequency = 8 MHz In this example, the MCG will move through the proper operational modes from FEI to PEE mode until the 8 MHz crystal reference frequency is set to achieve a bus frequency of 8 MHz. Thisexampleissimilartoexamplenumberoneexceptthatinthiscasethefrequencyoftheexternalcrystal is 8 MHz instead of 4 MHz. Special consideration must be taken with this case since there is a period of timealongthewayfromFEImodetoPEEmodewheretheFLLoperatesbasedonareferenceclockwith a frequency that is greater than the maximum allowed for the FLL. This occurs because with an 8 MHz MC9S08DZ60 Series Data Sheet, Rev. 4 160 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) external crystal and a maximum reference divider factor of 128, the resulting frequency of the reference clock for the FLL is 62.5 kHz (greater than the 39.0625 kHz maximum allowed). Care must be taken in the software to minimize the amount of time spent in this state where the FLL is operating in this condition. ThefollowingcodesequencedescribeshowtomovefromFEImodetoPEEmodeuntilthe8MHzcrystal referencefrequencyissettoachieveabusfrequencyof8MHz.BecausetheMCGisinFEImodeoutof reset, this example also shows how to initialize the MCG for PEE mode out of reset. First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1. First, FEI must transition to FBE mode: a) MCGC2 = 0x36 (%00110110) – BDIV (bits 7 and 6) set to %00, or divide-by-1 – RANGE(bit5)setto1becausethefrequencyof8MHziswithinthehighfrequencyrange – HGO (bit 4) set to 1 to configure external oscillator for high gain operation – EREFS (bit 2) set to 1, because a crystal is being used – ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit has been initialized. c) Block Interrupts (If applicable by setting the interrupt bit in the CCR). d) MCGC1 = 0xB8 (%10111000) – CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock source – RDIV (bits 5-3) set to %111, or divide-by-128. NOTE 8MHz/128=62.5kHzwhichisgreaterthanthe31.25kHzto39.0625kHz range required by the FLL. Therefore after the transition to FBE is complete, software must progress through to BLPE mode immediately by setting the LP bit in MCGC2. – IREFS (bit 2) cleared to 0, selecting the external reference clock e) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current source for the reference clock f) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference clock is selected to feed MCGOUT 2. Then, FBE mode transitions into BLPE mode: a) MCGC2 = 0x3E (%00111110) – LP (bit 3) in MCGC2 to 1 (BLPE mode entered) NOTE Theremustbenoextrasteps(includinginterrupts)betweensteps1dand2a. b) Enable Interrupts (if applicable by clearing the interrupt bit in the CCR). MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 161

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) c) MCGC1 = 0x98 (%10011000) – RDIV (bits 5-3) set to %011, or divide-by-8 because 8 MHz / 8= 1 MHz which is in the 1 MHz to 2 MHz range required by the PLL. In BLPE mode, the configuration of the RDIV doesnotmatterbecauseboththeFLLandPLLaredisabled.Changingthemonlysetsupthe the dividers for PLL usage in PBE mode d) MCGC3 = 0x44 (%01000100) – PLLS (bit 6) set to 1, selects the PLL. In BLPE mode, changing this bit only prepares the MCG for PLL usage in PBE mode – VDIV(bits3-0)setto%0100,ormultiply-by-16because1MHzreference*16=16MHz. In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is disabled. Changing them only sets up the multiply value for PLL usage in PBE mode e) Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the PLLS clock is the PLL 3. Then, BLPE mode transitions into PBE mode: a) Clear LP (bit 3) in MCGC2 to 0 here to switch to PBE mode b) Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock 4. Last, PBE mode transitions into PEE mode: a) MCGC1 = 0x18 (%00011000) – CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the system clock source b) LoopuntilCLKST(bits3and2)inMCGSCare%11,indicatingthatthePLLoutputisselected to feed MCGOUT in the current clock mode – Now,WithanRDIVofdivide-by-8,aBDIVofdivide-by-1,andaVDIVofmultiply-by-16, MCGOUT=[(8MHz/8)*16]/1=16MHz,andthebusfrequencyisMCGOUT/2,or8 MHz MC9S08DZ60 Series Data Sheet, Rev. 4 162 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) START IN FEI MODE MCGC2 = $36 CHECK NO CHECK NO PLLST = 1? OSCINIT = 1 ? YES YES MCGC2 = $36 (LP = 0) MCGC1 = $B8 CHECK NO IREFST = 0? CHECK NO LOCK = 1? YES YES CHECK NO MCGC1 = $18 CLKST = %10? YES CHECK NO MCGC2 = $3E CLKST = %11? (LP = 1) YES MCGC1 = $98 MCGC3 = $44 CONTINUE IN PEE MODE Figure8-12. Flowchart of FEI to PEE Mode Transition using a 8 MHz crystal MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 163

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.5.3 Calibrating the Internal Reference Clock (IRC) The IRC is calibrated by writing to the MCGTRM register first, then using the FTRIM bit to “fine tune” thefrequency.Wewillrefertothistotal9-bitvalueasthetrimvalue,rangingfrom0x000to0x1FF,where the FTRIM bit is the LSB. ThetrimvalueafteraPORisalways0x100(MCGTRM=0x80andFTRIM=0).Writingalargervalue will decrease the frequency and smaller values will increase the frequency. The trim value is linear with theperiod,exceptthatslightvariationsinwaferfabprocessingproduceslightnon-linearitiesbetweentrim valueandperiod.Thesenon-linearitiesarewhyaniterativetrimmingapproachtosearchforthebesttrim valueisrecommended.InExample#5:InternalReferenceClockTrimthisapproachwillbedemonstrated. After a trim value has been found for a device, this value can be stored in FLASH memory to save the value.Ifpowerisremovedfromthedevice,theIRCcaneasilybere-trimmedbycopyingthesavedvalue from FLASH to the MCG registers. Freescale identifies recommended FLASH locations for storing the trim value for each MCU. Consult the memory map in the data sheet for these locations. On devices that are factory trimmed, the factory trim value will be stored in these locations. 8.5.3.1 Example #5: Internal Reference Clock Trim Forapplicationsthatrequireatightfrequencytolerance,atrimmingprocedureisprovidedthatwillallow averyaccurateinternalclocksource.Thissectionoutlinesoneexampleoftrimmingtheinternaloscillator. Many other possible trimming procedures are valid and can be used. In the example below, the MCG trim will be calibrated for the 9-bit MCGTRM and FTRIM collective value. This value will be referred to as TRMVAL. MC9S08DZ60 Series Data Sheet, Rev. 4 164 Freescale Semiconductor

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) Initial conditions: 1) Clock supplied from ATE has 500μs duty period 2) MCG configured for internal reference with 8MHz bus START TRIM PROCEDURE TRMVAL = $100 n=1 MEASURE INCOMING CLOCK WIDTH (COUNT = # OF BUS CLOCKS / 8) COUNT < EXPECTED =500 (RUNNING TOO SLOW) . COUNT = EXPECTED = 500 CASE STATEMENT COUNT > EXPECTED = 500 (RUNNING TOO FAST) TRMVAL = TRMVAL = STORE MCGTRM AND TRMVAL - 256/ (2**n) TRMVAL + 256/ (2**n) FTRIM VALUES IN (DECREASING TRMVAL (INCREASING TRMVAL NON-VOLATILE MEMORY INCREASES THE FREQUENCY) DECREASES THE FREQUENCY) CONTINUE n = n + 1 YES IS n > 9? NO Figure8-13. Trim Procedure In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final testwithautomatedtestequipment.AseparatesignalormessageisprovidedtotheMCUoperatingunder user provided software control. The MCU initiates a trim procedure as outlined inFigure8-13 while the tester supplies a precision reference signal. Iftheintendedbusfrequencyisnearthemaximumallowedforthedevice,itisrecommendedtotrimusing areferencedividervalue(RDIVsetting)oftwicethefinalvalue.Afterthetrimprocedureiscomplete,the referencedividercanberestored.Thiswillpreventaccidentalovershootofthemaximumclockfrequency. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 165

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) MC9S08DZ60 Series Data Sheet, Rev. 4 166 Freescale Semiconductor

Chapter 9 Analog Comparator (S08ACMPV3) 9.1 Introduction Theanalogcomparatormodule(ACMP)providesacircuitforcomparingtwoanaloginputvoltagesorfor comparingoneanaloginputvoltagetoaninternalreferencevoltage.Thecomparatorcircuitisdesignedto operate across the full range of the supply voltage (rail-to-rail operation). AllMC9S08DZ60SeriesMCUshavetwofullfunctionACMPsina64-pinpackage.MCUsinthe48-pin package have two ACMPs, but the output of ACMP2 is not accessible. MCUs in the 32-pin package contain one full function ACMP. NOTE MC9S08DZ60 Series devices operate at a higher voltage range (2.7 V to 5.5V) and do not include stop1 mode. Please ignore references to stop1. 9.1.1 ACMP Configuration Information WhenusingthebandgapreferencevoltageforinputtoACMP+,theusermustenablethebandgapbuffer by setting BGBE =1 in SPMSC1 seeSection5.8.7, “System Power Management Status and Control 1 Register (SPMSC1).” For value of bandgap voltage reference seeSectionA.6, “DC Characteristics.” MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 167

Chapter9 Analog Comparator (S08ACMPV3) HCS08 CORE PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 CPU ANALOG COMPARATOR ACMP1O ORT A PPTTAA43//PPIIAA43//AADDPP43/ACMP1O BKGD/MS (ACMP1) ACMP1- P PTA2/PIA2/ADP2/ACMP1- BDC BKP ACMP1+ PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK HCS08 SYSTEM CONTROL PTB7/PIB7/ADP15 RESET RESETS AND INTERRUPTS PTB6/PIB6/ADP14 MODES OF OPERATION PTB5/PIB5/ADP13 POWER MANAGEMENT T B PTB4/PIB4/ADP12 OR PTB3/PIB3/ADP11 8 P PTB2/PIB2/ADP10 COP LVD Q PTB1/PIB1/ADP9 R INT IRQ I ADP7-ADP0 PTB0/PIB0/ADP8 24-CHANNEL,12-BIT PTC7/ADP23 ADP15-ADP8 ANALOG-TO-DIGITAL PTC6/ADP22 VREFH CONVERTER (ADC) ADP23-ADP16 PTC5/ADP21 V VREFL T C PTC4/ADP20 DDA OR PTC3/ADP19 VSSA P PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 USER FLASH TPM1CH5 - PTD7/PID7/TPM1CH5 MC9S0DZ60 = 60K 6-CHANNEL TIMER/PWM TPM1CH0 6 MC9S0DZ48 = 48K MODULE (TPM1) TPM1CLK PTD6/PID6/TPM1CH4 MC9S0DZ32 = 32K PTD5/PID5/TPM1CH3 MC9S0DZ16 = 16K T D PTD4/PID4/TPM1CH2 TPM2CH1, OR PTD3/PID3/TPM1CH1 2-CHANNEL TIMER/PWM TPM2CH0 P PTD2/PID2/TPM1CH0 MODULE (TPM2) TPM2CLK PTD1/PID1/TPM2CH1 USER EEPROM PTD0/PID0/TPM2CH0 MC9S0DZ60 = 2K CONTROLLER AREA RxCAN PTE7/RxD2/RXCAN NETWORK (MSCAN) TxCAN PTE6/TxD2/TXCAN MISO PTE5/SDA/MISO MCU9SS0EDRZ R60A M= 4K INTSEERRFIAALC EP EMROIPDHUELREA (SLPI) SMPOSSCIK ORT E PPTTEE34//SSPCSL/CMKOSI SS P PTE2/SS RxD1 PTE1/RxD1 DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1 PTE0/TxD1 INTERFACE (SCI1) PTF7 ACMP2O ANALOG COMPARATOR PTF6/ACMP2O REAL-TIME COUNTER (RTC) (ACMP2) ACMP2- PTF5/ACMP2- ACMP2+ VVDDDD VOLTAGE IIC MODULE (IIC) SSCDLA PORT F PPPTTTFFF342///TATPPCMMM21PCC2LL+KK//SSDCAL RxD2 VSS REGULATOR PTF1/RxD2 V SERIAL COMMUNICATIONS TxD2 SS PTF0/TxD2 INTERFACE (SCI2) PTG5 MULTI-PURPOSE PTG4 CLOCK GENERATOR G PTG3 (MCG) T R PTG2 XTAL PO PTG1/XTAL OSCILLATOR (XOSC) EXTAL PTG0/EXTAL - V /V internally connected to V /V in 48-pin and 32-pin packages - Pin not connected in 48-pin and 32-pin packages REFH REFL DDA SSA - V and V pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package DD SS Figure9-1. MC9S08DZ60 Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 168 Freescale Semiconductor

Chapter 9 Analog Comparator (S08ACMPV3) 9.1.2 Features The ACMP has the following features: • Full rail to rail supply operation. • Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. • Option to compare to fixed internal bandgap reference voltage. • Option to allow comparator output to be visible on a pin, ACMPxO. 9.1.3 Modes of Operation This section defines the ACMP operation in wait, stop, and background debug modes. 9.1.3.1 ACMP in Wait Mode The ACMP continues to run in wait mode if enabled before executing the appropriate instruction. Therefore, the ACMP can be used to bring the MCU out of wait mode if the ACMP interrupt is enabled (ACIEisset).Forlowestpossiblecurrentconsumption,theACMPshouldbedisabledbysoftwareifnot required as an interrupt source during wait mode. 9.1.3.2 ACMP in Stop Modes The ACMP is disabled in all stop modes, regardless of the settings before executing the stop instruction. Therefore, the ACMP cannot be used as a wake up source from stop modes. During stop2 mode, the ACMP module is fully powered down. Upon wake-up from stop2 mode, the ACMP module is in the reset state. During stop3 mode, clocks to the ACMP module are halted. No registers are affected. In addition, the ACMP comparator circuit enters a low-power state. No compare operation occurs while in stop3. Ifstop3isexitedwithareset,theACMPisputintoitsresetstate.Ifstop3isexitedwithaninterrupt,the ACMP continues from the state it was in when stop3 was entered. 9.1.3.3 ACMP in Active Background Mode When the microcontroller is in active background mode, the ACMP continues to operate normally. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 169

Chapter 9 Analog Comparator (S08ACMPV3) 9.1.4 Block Diagram The block diagram for the analog comparator module is shown Figure9-2. Internal Bus Internal Reference ACMPx INTERRUPT ACIE REQUEST ACBGS Status & Control ACME ACF Register ACOPE D F O C M A ACMPx+ AC set + Interrupt Control - ACMPx- Comparator ACMPxO Figure9-2. Analog Comparator (ACMP) Block Diagram 9.2 External Signal Description TheACMPhastwoanaloginputpins,ACMPx+andACMPx−andonedigitaloutputpinACMPxO.Each of these pins can accept an input voltage that varies across the full operating voltage range of the MCU. As shown inFigure9-2, the ACMPx- pin is connected to the inverting input of the comparator, and the ACMPx+pinisconnectedtothecomparatornon-invertinginputifACBGSisa0.AsshowninFigure9-2, the ACMPxO pin can be enabled to drive an external pin. The signal properties of ACMP are shown in Table9-1. Table9-1. Signal Properties Signal Function I/O ACMPx- Inverting analog input to the ACMP. I (Minus input) ACMPx+ Non-inverting analog input to the ACMP. I (Positive input) ACMPxO Digital output of the ACMP. O MC9S08DZ60 Series Data Sheet, Rev. 4 170 Freescale Semiconductor

Chapter 9 Analog Comparator (S08ACMPV3) 9.3 Memory Map/Register Definition The ACMP includes one register: • An 8-bit status and control register Refertothedirect-pageregistersummaryinthememorysectionofthisdocumentfortheabsoluteaddress assignmentsfortheACMPregister.Thissectionreferstoregisterandcontrolbitsonlybytheirnamesand relative address offsets. Some MCUs may have more than one ACMP, so register names include placeholder characters (x) to identify which ACMP is being referenced. Table9-2. ACMP Register Summary Name 7 6 5 4 3 2 1 0 R ACO ACMPxSC ACME ACBGS ACF ACIE ACOPE ACMOD W 9.3.1 ACMPx Status and Control Register (ACMPxSC) ACMPxSC contains the status flag and control bits used to enable and configure the ACMP. 7 6 5 4 3 2 1 0 R ACO ACME ACBGS ACF ACIE ACOPE ACMOD W Reset: 0 0 0 0 0 0 0 0 Figure9-3. ACMPx Status and Control Register (ACMPxSC) Table9-3. ACMPxSC Field Descriptions Field Description 7 Analog Comparator Module Enable. Enables the ACMP module. ACME 0 ACMP not enabled 1 ACMP is enabled 6 AnalogComparatorBandgapSelect.SelectsbetweenthebandgapreferencevoltageortheACMPx+pinasthe ACBGS input to the non-inverting input of the analog comparator. 0 External pin ACMPx+ selected as non-inverting input to comparator 1 Internal reference select as non-inverting input to comparator 5 Analog Comparator Flag. ACF is set when a compare event occurs. Compare events are defined by ACMOD. ACF ACF is cleared by writing a one to it. 0 Compare event has notoccurred 1 Compare event hasoccurred 4 Analog Comparator Interrupt Enable. Enables the interrupt from the ACMP. When ACIE is set, aninterrupt is ACIE asserted when ACF is set. 0 Interrupt disabled 1 Interrupt enabled MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 171

Chapter 9 Analog Comparator (S08ACMPV3) Table9-3. ACMPxSC Field Descriptions (continued) Field Description 3 Analog Comparator Output. Reading ACO returns the current value of the analog comparator output.ACO is ACO reset to a 0 and reads as a 0 when the ACMP is disabled (ACME = 0). 2 Analog Comparator Output Pin Enable. Enables the comparator output to be placed onto the external pin, ACOPE ACMPxO. 0 Analog comparator output not available on ACMPxO 1 Analog comparator output is driven out on ACMPxO 1:0 Analog Comparator Mode. ACMOD selects the type of compare event which sets ACF. ACMOD 00 Encoding 0 — Comparator output falling edge 01 Encoding 1 — Comparator output rising edge 10 Encoding 2 — Comparator output falling edge 11 Encoding 3 — Comparator output rising or falling edge 9.4 Functional Description The analog comparator can compare two analog input voltages applied to ACMPx+ and ACMPx−, or it can compare an analog input voltage applied to ACMPx− with an internal bandgap reference voltage. ACBGS selects between the bandgap reference voltage or the ACMPx+ pin as the input to the non-invertinginputoftheanalogcomparator.Thecomparatoroutputishighwhenthenon-invertinginput isgreaterthantheinvertinginput,andislowwhenthenon-invertinginputislessthantheinvertinginput. ACMODselectstheconditionthatcausesACFtobeset.ACFcanbesetonarisingedgeofthecomparator output,afallingedgeofthecomparatoroutput,orarisingorafallingedge(toggle).Thecomparatoroutput can be read directly through ACO. The comparator output can be driven onto the ACMPxO pin using ACOPE. MC9S08DZ60 Series Data Sheet, Rev. 4 172 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.1 Introduction The12-bitanalog-to-digitalconverter(ADC)isasuccessiveapproximationADCdesignedforoperation within an integrated microcontroller system-on-chip. NOTE MC9S08DZ60 Series devices operate at a higher voltage range (2.7 V to 5.5V) and do not include stop1 mode. Please ignore references to stop1. 10.1.1 Analog Power and Ground Signal Names References to V and V in this chapter correspond to signals V and V , respectively. DDAD SSAD DDA SSA 10.1.2 Channel Assignments NOTE The ADC channel assignments for the MC9S08DZ60 Series devices are shown inTable10-1. Reserved channels convert to an unknown value. This chapter shows bits for all S08ADC12V1 channels. MC9S08DZ60 Series MCUs do not use all of these channels. All bits corresponding to channels that are not available on a device are reserved. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 173

Chapter10 Analog-to-Digital Converter (S08ADC12V1) Table10-1. ADC Channel Assignment ADCH Channel Input ADCH Channel Input 00000 AD0 PTA0/ADP0/MCLK 01111 AD15 PTB7/ADP15 00001 AD1 PTA1/ADP1/ACMP1+ 10000 AD16 PTC0/ADP16 00010 AD2 PTA2/ADP2/ACMP1P- 10001 AD17 PTC1/ADP17 00011 AD3 PTA3/ADP3/ACMP1O 10010 AD18 PTC2/ADP18 00100 AD4 PTA4/ADP4 10011 AD19 PTC3/ADP19 00101 AD5 PTA5/ADP5 10100 AD20 PTC4/ADP20 00110 AD6 PTA6/ADP6 10101 AD21 PTC5/ADP21 00111 AD7 PTA7/ADP7 10110 AD22 PTC6/ADP22 01000 AD8 PTB0/ADP8 10111 AD23 PTC7/ADP23 01001 AD9 PTB1/ADP9 11000– AD24 through AD25 Reserved 01010 AD10 PTB2/ADP10 11001 01011 AD11 PTB3/ADP11 11010 AD26 Temperature Sensor1 01100 AD12 PTB4/ADP12 11011 AD27 Internal Bandgap2 01101 AD13 PTB5/ADP13 11100 Reserved Reserved 01110 AD14 PTB6/ADP14 11101 VREFH VREFH 11110 V V 10.1.3 Alternate Clock The ADC module is capable of performing conversions using the MCU bus clock, the bus clock divided bytwo,thelocalasynchronousclock(ADACK)withinthemodule,orthealternateclock,ALTCLK.The alternateclockfortheMC9S08DZ60SeriesMCUdevicesistheexternalreferenceclock(MCGERCLK). TheselectedclocksourcemustrunatafrequencysuchthattheADCconversionclock(ADCK)runsata frequency within its specified range (f ) after being divided down from the ALTCLK input as ADCK determined by the ADIV bits. ALTCLKisactivewhiletheMCUisinwaitmodeprovidedtheconditionsdescribedabovearemet.This allows ALTCLK to be used as the conversion clock source for the ADC while the MCU is in wait mode. ALTCLK cannot be used as the ADC conversion clock source while the MCU is in either stop2 or stop3. 10.1.4 Hardware Trigger The ADC hardware trigger, ADHWT, is the output from the real time counter (RTC). The RTC counter can be clocked by either MCGERCLK or a nominal 1 kHz clock source. The period of the RTC is determined by the input clock frequency, the RTCPS bits, and the RTCMOD register. When the ADC hardware trigger is enabled, a conversion is initiated upon an RTC counter overflow. The RTC can be configured to cause a hardware trigger in MCU run, wait, and stop3. MC9S08DZ60 Series Data Sheet, Rev. 4 174 Freescale Semiconductor

Chapter10 Analog-to-Digital Converter (S08ADC12V1) 10.1.5 Temperature Sensor To use the on-chip temperature sensor, the user must perform the following: • Configure ADC for long sample with a maximum of 1 MHz clock • Convert the bandgap voltage reference channel (AD27) — By converting the digital value of the bandgap voltage reference channel using the value of V the user can determine V . For value of bandgap voltage, seeSectionA.6, “DC BG DD Characteristics”. • Convert the temperature sensor channel (AD26) — By using the calculated value of V , convert the digital value of AD26 into a voltage, V DD TEMP Equation10-1 provides an approximate transfer function of the temperature sensor. Temp = 25-((V -V )÷ m) Eqn.10-1 TEMP TEMP25 where: — V is the voltage of the temperature sensor channel at the ambient temperature. TEMP — V is the voltage of the temperature sensor channel at 25°C. TEMP25 — m is the hot or cold voltage versus temperature slope in V/°C. For temperature calculations, use the V and m values from the ADC Electricals table. TEMP25 In application code, the user reads the temperature sensor channel, calculates V , and compares to TEMP V .IfV isgreaterthanV thecoldslopevalueisappliedinEquation10-1.IfV is TEMP25 TEMP TEMP25 TEMP less than V the hot slope value is applied in Equation10-1.To improve accuracy the user should TEMP25 calibrate the bandgap voltage reference and temperature sensor. Calibrating at 25°C will improve accuracy to ±4.5°C. Calibration at three points, -40°C, 25°C, and 125°C will improve accuracy to ±2.5°C. Once calibration hasbeencompleted,theuserwillneedtocalculatetheslopeforbothhotandcold.Inapplicationcode,the userwouldthencalculatethetemperatureusingEquation10-1asdetailedaboveandthendetermineifthe temperatureisaboveorbelow25°C.Oncedeterminedifthetemperatureisaboveorbelow25°C,theuser can recalculate the temperature using the hot or cold slope value obtained during calibration. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 175

Chapter10 Analog-to-Digital Converter (S08ADC12V1) HCS08 CORE PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 CPU ANALOG COMPARATOR ACMP1O ORT A PPTTAA34//PPIIAA34//AADDPP34/ACMP1O BKGD/MS (ACMP1) ACMP1- P PTA2/PIA2/ADP2/ACMP1- BDC BKP ACMP1+ PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK HCS08 SYSTEM CONTROL PTB7/PIB7/ADP15 RESET RESETS AND INTERRUPTS PTB6/PIB6/ADP14 MODES OF OPERATION PTB5/PIB5/ADP13 POWER MANAGEMENT T B PTB4/PIB4/ADP12 OR PTB3/PIB3/ADP11 8 P PTB2/PIB2/ADP10 COP LVD Q PTB1/PIB1/ADP9 R INT IRQ I ADP7-ADP0 PTB0/PIB0/ADP8 24-CHANNEL,12-BIT PTC7/ADP23 ADP15-ADP8 ANALOG-TO-DIGITAL PTC6/ADP22 VREFH CONVERTER (ADC) ADP23-ADP16 PTC5/ADP21 V VREFL T C PTC4/ADP20 DDA OR PTC3/ADP19 VSSA P PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 USER FLASH TPM1CH5 - PTD7/PID7/TPM1CH5 MC9S0DZ60 = 60K 6-CHANNEL TIMER/PWM TPM1CH0 6 MC9S0DZ48 = 48K MODULE (TPM1) TPM1CLK PTD6/PID6/TPM1CH4 MC9S0DZ32 = 32K PTD5/PID5/TPM1CH3 MC9S0DZ16 = 16K T D PTD4/PID4/TPM1CH2 TPM2CH1, OR PTD3/PID3/TPM1CH1 2-CHANNEL TIMER/PWM TPM2CH0 P PTD2/PID2/TPM1CH0 MODULE (TPM2) TPM2CLK PTD1/PID1/TPM2CH1 USER EEPROM PTD0/PID0/TPM2CH0 MC9S0DZ60 = 2K CONTROLLER AREA RxCAN PTE7/RxD2/RXCAN NETWORK (MSCAN) TxCAN PTE6/TxD2/TXCAN MISO PTE5/SDA/MISO MCU9SS0EDRZ R60A M= 4K INTSEERRFIAALC EP EMROIPDHUELREA (SLPI) SMPOSSCIK ORT E PPTTEE34//SSPCSL/CMKOSI SS P PTE2/SS RxD1 PTE1/RxD1 DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1 PTE0/TxD1 INTERFACE (SCI1) PTF7 ACMP2O ANALOG COMPARATOR PTF6/ACMP2O REAL-TIME COUNTER (RTC) (ACMP2) ACMP2- PTF5/ACMP2- ACMP2+ VVDDDD VOLTAGE IIC MODULE (IIC) SSCDLA PORT F PPPTTTFFF342///TATPPCMMM21PCC2LL+KK//SSDCAL RxD2 VSS REGULATOR PTF1/RxD2 V SERIAL COMMUNICATIONS TxD2 SS PTF0/TxD2 INTERFACE (SCI2) PTG5 MULTI-PURPOSE PTG4 CLOCK GENERATOR G PTG3 (MCG) T R PTG2 XTAL PO PTG1/XTAL OSCILLATOR (XOSC) EXTAL PTG0/EXTAL - V /V internally connected to V /V in 48-pin and 32-pin packages - Pin not connected in 48-pin and 32-pin packages REFH REFL DDA SSA - V and V pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package DD SS Figure10-1. MC9S08DZ60 Block Diagram Emphasizing the ADC Module and Pins MC9S08DZ60 Series Data Sheet, Rev. 4 176 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.1.6 Features Features of the ADC module include: • Linearsuccessive approximation algorithm with 12-bit resolution • Up to 28 analog inputs • Output formatted in 12-, 10-, or 8-bit right-justified unsigned format • Singleor continuous conversion (automatic return to idle after single conversion) • Configurable sample time and conversion speed/power • Conversion complete flag and interrupt • Inputclock selectable from up to four sources • Operation in wait or stop3 modes for lower noise operation • Asynchronous clock source for lower noise operation • Selectable asynchronous hardware conversion trigger • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value • Temperature sensor 10.1.7 ADC Module Block Diagram Figure10-2 provides a block diagram of the ADC module. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 177

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 3 Compare true ADCSC1 ADCCFG O N C ADCH AIE1 CO2 ADCO complete ADTRG MODE ADLSMP ADLPC ADIV ADICLK CloAcsky Gncen ADACK Bus Clock MCU STOP ADCK Clock ADHWT Control Sequencer Divide ÷2 AD0 initialize sample convert transfer abort ALTCLK • AIEN 1 Interrupt • • ADVIN COCO 2 SAR Converter AD27 V REFH Data Registers V REFL m u S Compare true 3 Compare Logic Value CFGT A Compare Value Registers ADCSC2 Figure10-2. ADC Block Diagram 10.2 External Signal Description TheADCmodulesupportsupto28separateanaloginputs.Italsorequiresfoursupply/reference/ground connections. Table10-2. Signal Properties Name Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL V Analog power supply DDAD V Analog ground SSAD MC9S08DZ60 Series Data Sheet, Rev. 4 178 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.2.1 Analog Power (V ) DDAD The ADC analog portion usesV as its power connection. In some packages, V is connected DDAD DDAD internally to V . If externally available, connect the V pin to the same voltage potential as V . DD DDAD DD External filtering may be necessary to ensure cleanV for good results. DDAD 10.2.2 Analog Ground (V ) SSAD The ADC analog portion usesV as its ground connection. In some packages, V is connected SSAD SSAD internally to V . If externally available, connect theV pin to the same voltage potential as V . SS SSAD SS 10.2.3 Voltage Reference High (V ) REFH V isthehighreferencevoltagefortheconverter.Insomepackages,V isconnectedinternallyto REFH REFH V .Ifexternallyavailable,V maybeconnectedtothesamepotentialasV ormaybedriven DDAD REFH DDAD by an external source between the minimum V spec and the V potential (V must never DDAD DDAD REFH exceed V ). DDAD 10.2.4 Voltage Reference Low (V ) REFL V isthelow-referencevoltagefortheconverter.Insomepackages,V isconnectedinternallyto REFL REFL V .If externally available, connect the V pin to the same voltage potential asV . SSAD REFL SSAD 10.2.5 Analog Channel Inputs (ADx) TheADCmodulesupportsupto28separateanaloginputs.Aninputisselectedforconversionthroughthe ADCH channel select bits. 10.3 Register Definition These memory-mapped registers control and monitor operation of the ADC: • Status and control register, ADCSC1 • Status and control register, ADCSC2 • Data result registers, ADCRH and ADCRL • Compare value registers, ADCCVH and ADCCVL • Configuration register, ADCCFG • Pincontrol registers, APCTL1, APCTL2, APCTL3 10.3.1 Status and Control Register 1 (ADCSC1) ThissectiondescribesthefunctionoftheADCstatusandcontrolregister(ADCSC1).WritingADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 179

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 7 6 5 4 3 2 1 0 R COCO AIEN ADCO ADCH W Reset: 0 0 0 1 1 1 1 1 Figure10-3. Status and Control Register (ADCSC1) Table10-3. ADCSC1 Field Descriptions Field Description 7 ConversionCompleteFlag.TheCOCOflagisaread-onlybitseteachtimeaconversioniscompletedwhenthe COCO comparefunctionisdisabled(ACFE=0).Whenthecomparefunctionisenabled(ACFE=1),theCOCOflagis setuponcompletionofaconversiononlyifthecompareresultistrue.ThisbitisclearedwhenADCSC1iswritten or when ADCRL is read. 0 Conversion not completed 1 Conversion completed 6 Interrupt Enable AIEN enables conversion complete interrupts. When COCO becomes set while AIEN is high, AIEN an interrupt is asserted. 0 Conversion complete interrupt disabled 1 Conversion complete interrupt enabled 5 Continuous Conversion Enable. ADCO enables continuous conversions. ADCO 0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. 1 ContinuousconversionsinitiatedfollowingawritetoADCSC1whensoftwaretriggeredoperationisselected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. 4:0 InputChannelSelect.TheADCHbitsforma5-bitfieldthatselectsoneoftheinputchannels.Theinputchannels ADCH are detailed inTable10-4. The successive approximation converter subsystem is turned off when the channel select bits are all set. This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources. Terminating continuous conversions this way prevents an additional, single conversion from being performed. It is not necessary to set the channel select bits to all ones to place the ADC in a low-power state when continuous conversions are not enabled because the module automatically enters a low-power state when a conversion completes. Table10-4. Input Channel Select ADCH Input Select 00000–01111 AD0–15 10000–11011 AD16–27 11100 Reserved 11101 V REFH 11110 V REFL 11111 Module disabled MC9S08DZ60 Series Data Sheet, Rev. 4 180 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.3.2 Status and Control Register 2 (ADCSC2) TheADCSC2registercontrolsthecomparefunction,conversiontrigger,andconversionactiveoftheADC module. 7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 Figure10-4. Status and Control Register 2 (ADCSC2) Table10-5. ADCSC2 Register Field Descriptions Field Description 7 Conversion Active. Indicates that a conversion is in progress. ADACT is set when a conversion is initiated and ADACT cleared when a conversion is completed or aborted. 0 Conversion not in progress 1 Conversion in progress 6 Conversion Trigger Select. Selects the type of trigger used for initiating a conversion. Two types of triggers are ADTRG selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated followingawritetoADCSC1.Whenhardwaretriggerisselected,aconversionisinitiatedfollowingtheassertion of the ADHWT input. 0 Software trigger selected 1 Hardware trigger selected 5 Compare Function Enable. Enables the compare function. ACFE 0 Compare function disabled 1 Compare function enabled 4 Compare Function Greater Than Enable. Configures the compare function to trigger when the result of the ACFGT conversion of the input being monitored is greater than or equal to the compare value. The compare function defaultstotriggeringwhentheresultofthecompareoftheinputbeingmonitoredislessthanthecomparevalue. 0 Compare triggers when input is less than comparevalue 1 Compare triggers when input is greater than or equal to comparevalue 10.3.3 Data Result High Register (ADCRH) In 12-bit operation, ADCRH contains the upper four bits of the result of a 12-bit conversion. In 10-bit mode,ADCRHcontainstheuppertwobitsoftheresultofa10-bitconversion.Whenconfiguredfor10-bit mode, ADR[11:10] are cleared. When configured for 8-bit mode, ADR[11:8] are cleared. In12-bitand10-bitmode,ADCRHisupdatedeachtimeaconversioncompletesexceptwhenautomatic compareisenabledandthecompareconditionisnotmet.Whenacompareeventdoesoccur,thevalueis theadditionoftheconversionresultandthetwo’scomplementofthecomparevalue.In12-bitand10-bit mode,readingADCRHpreventstheADCfromtransferringsubsequentconversionresultsintotheresult registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, the intermediate conversion result is lost. In 8-bit mode, there is no interlocking with ADCRL. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 181

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) If the MODE bits are changed, any data in ADCRH becomes invalid. 7 6 5 4 3 2 1 0 R 0 0 0 0 ADR11 ADR10 ADR9 ADR8 W Reset: 0 0 0 0 0 0 0 0 Figure10-5. Data Result High Register (ADCRH) 10.3.4 Data Result Low Register (ADCRL) ADCRLcontainsthelowereightbitsoftheresultofa12-bitor10-bitconversion,andalleightbitsofan 8-bit conversion. This register is updated each time a conversion completes except when automatic compareisenabledandthecompareconditionisnotmet.Whenacompareeventdoesoccur,thevalueis theadditionoftheconversionresultandthetwo’scomplementofthecomparevalue.In12-bitand10-bit mode,readingADCRHpreventstheADCfromtransferringsubsequentconversionresultsintotheresult registers until ADCRL is read. If ADCRL is not read until the after next conversion is completed, the intermediateconversionresultsarelost.In8-bitmode,thereisnointerlockingwithADCRH.IftheMODE bits are changed, any data in ADCRL becomes invalid. 7 6 5 4 3 2 1 0 R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 W Reset: 0 0 0 0 0 0 0 0 Figure10-6. Data Result Low Register (ADCRL) 10.3.5 Compare Value High Register (ADCCVH) In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value.When the compare function is enabled, these bits are compared to the upper four bits of the result following a conversion in 12-bit mode. 7 6 5 4 3 2 1 0 R 0 0 0 0 ADCV11 ADCV10 ADCV9 ADCV8 W Reset: 0 0 0 0 0 0 0 0 Figure10-7. Compare Value High Register (ADCCVH) MC9S08DZ60 Series Data Sheet, Rev. 4 182 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) In10-bitmode,theADCCVHregisterholdstheuppertwobitsofthe10-bitcomparevalue(ADCV[9:8]). Thesebitsarecomparedtotheuppertwobitsoftheresultfollowingaconversionin10-bitmodewhenthe compare function is enabled. In 8-bit mode, ADCCVH is not used during compare. 10.3.6 Compare Value Low Register (ADCCVL) Thisregisterholdsthelower8bitsofthe12-bitor10-bitcomparevalueorall8bitsofthe8-bitcompare value.When the compare function is enabled, bits ADCV[7:0] are compared to the lower 8 bits of the result following a conversion in 12-bit, 10-bit or 8-bit mode. 7 6 5 4 3 2 1 0 R ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0 W Reset: 0 0 0 0 0 0 0 0 Figure10-8. Compare Value Low Register(ADCCVL) 10.3.7 Configuration Register (ADCCFG) ADCCFG selects the mode of operation, clock source, clock divide, and configures for low powerand long sample time. 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK W Reset: 0 0 0 0 0 0 0 0 Figure10-9. Configuration Register (ADCCFG) Table10-6. ADCCFG Register Field Descriptions Field Description 7 Low-PowerConfiguration.ADLPCcontrolsthespeedandpowerconfigurationofthesuccessiveapproximation ADLPC converter. This optimizes power consumption when higher sample rates are not required. 0 High speed configuration 1 Low power configuration:The power is reduced at the expense of maximum clock speed. 6:5 Clock Divide Select. ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK. ADIV Table10-7 shows the available clock configurations. 4 Long Sample Time Configuration. ADLSMP selects between long and short sample time. This adjusts the ADLSMP sampleperiodtoallowhigherimpedanceinputstobeaccuratelysampledortomaximizeconversionspeedfor lower impedance inputs. Longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. 0 Short sample time 1 Long sample time MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 183

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) Table10-6. ADCCFG Register Field Descriptions (continued) Field Description 3:2 ConversionModeSelection.MODEbitsareusedtoselectbetween12-,10-,or8-bitoperation.SeeTable10-8. MODE 1:0 Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See ADICLK Table10-9. Table10-7. Clock Divide Select ADIV Divide Ratio Clock Rate 00 1 Input clock 01 2 Input clock÷2 10 4 Input clock÷4 11 8 Input clock÷8 Table10-8. Conversion Modes MODE Mode Description 00 8-bit conversion (N=8) 01 12-bit conversion (N=12) 10 10-bit conversion (N=10) 11 Reserved Table10-9. Input Clock Select ADICLK Selected Clock Source 00 Bus clock 01 Bus clock divided by 2 10 Alternate clock (ALTCLK) 11 Asynchronous clock (ADACK) 10.3.8 Pin Control 1 Register (APCTL1) The pin control registers disable the I/O port control of MCU pins used as analog inputs. APCTL1 is MC9S08DZ60 Series Data Sheet, Rev. 4 184 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) used to control the pins associated with channels 0–7 of the ADC module. 7 6 5 4 3 2 1 0 R ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0 W Reset: 0 0 0 0 0 0 0 0 Figure10-10. Pin Control 1 Register (APCTL1) Table10-10. APCTL1 Register Field Descriptions Field Description 7 ADC Pin Control 7. ADPC7 controls the pin associated with channel AD7. ADPC7 0 AD7 pin I/O control enabled 1 AD7 pin I/O control disabled 6 ADC Pin Control 6. ADPC6 controls the pin associated with channel AD6. ADPC6 0 AD6 pin I/O control enabled 1 AD6 pin I/O control disabled 5 ADC Pin Control 5. ADPC5 controls the pin associated with channel AD5. ADPC5 0 AD5 pin I/O control enabled 1 AD5 pin I/O control disabled 4 ADC Pin Control 4. ADPC4 controls the pin associated with channel AD4. ADPC4 0 AD4 pin I/O control enabled 1 AD4 pin I/O control disabled 3 ADC Pin Control 3. ADPC3 controls the pin associated with channel AD3. ADPC3 0 AD3 pin I/O control enabled 1 AD3 pin I/O control disabled 2 ADC Pin Control 2. ADPC2 controls the pin associated with channel AD2. ADPC2 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled 1 ADC Pin Control 1. ADPC1 controls the pin associated with channel AD1. ADPC1 0 AD1 pin I/O control enabled 1 AD1 pin I/O control disabled 0 ADC Pin Control 0. ADPC0 controls the pin associated with channel AD0. ADPC0 0 AD0 pin I/O control enabled 1 AD0 pin I/O control disabled 10.3.9 Pin Control 2 Register (APCTL2) APCTL2 controls channels 8–15 of the ADC module. 7 6 5 4 3 2 1 0 R ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 W Reset: 0 0 0 0 0 0 0 0 Figure10-11. Pin Control 2 Register (APCTL2) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 185

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) Table10-11. APCTL2 Register Field Descriptions Field Description 7 ADC Pin Control 15. ADPC15 controls the pin associated with channel AD15. ADPC15 0 AD15 pin I/O control enabled 1 AD15 pin I/O control disabled 6 ADC Pin Control 14. ADPC14 controls the pin associated with channel AD14. ADPC14 0 AD14 pin I/O control enabled 1 AD14 pin I/O control disabled 5 ADC Pin Control 13. ADPC13 controls the pin associated with channel AD13. ADPC13 0 AD13 pin I/O control enabled 1 AD13 pin I/O control disabled 4 ADC Pin Control 12. ADPC12 controls the pin associated with channel AD12. ADPC12 0 AD12 pin I/O control enabled 1 AD12 pin I/O control disabled 3 ADC Pin Control 11. ADPC11 controls the pin associated with channel AD11. ADPC11 0 AD11 pin I/O control enabled 1 AD11 pin I/O control disabled 2 ADC Pin Control 10. ADPC10 controls the pin associated with channel AD10. ADPC10 0 AD10 pin I/O control enabled 1 AD10 pin I/O control disabled 1 ADC Pin Control 9. ADPC9 controls the pin associated with channel AD9. ADPC9 0 AD9 pin I/O control enabled 1 AD9 pin I/O control disabled 0 ADC Pin Control 8. ADPC8 controls the pin associated with channel AD8. ADPC8 0 AD8 pin I/O control enabled 1 AD8 pin I/O control disabled 10.3.10 Pin Control 3 Register (APCTL3) APCTL3 controls channels 16–23 of the ADC module. 7 6 5 4 3 2 1 0 R ADPC23 ADPC22 ADPC21 ADPC20 ADPC19 ADPC18 ADPC17 ADPC16 W Reset: 0 0 0 0 0 0 0 0 Figure10-12. Pin Control 3 Register (APCTL3) MC9S08DZ60 Series Data Sheet, Rev. 4 186 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) Table10-12. APCTL3 Register Field Descriptions Field Description 7 ADC Pin Control 23. ADPC23 controls the pin associated with channel AD23. ADPC23 0 AD23 pin I/O control enabled 1 AD23 pin I/O control disabled 6 ADC Pin Control 22. ADPC22 controls the pin associated with channel AD22. ADPC22 0 AD22 pin I/O control enabled 1 AD22 pin I/O control disabled 5 ADC Pin Control 21. ADPC21 controls the pin associated with channel AD21. ADPC21 0 AD21 pin I/O control enabled 1 AD21 pin I/O control disabled 4 ADC Pin Control 20. ADPC20 controls the pin associated with channel AD20. ADPC20 0 AD20 pin I/O control enabled 1 AD20 pin I/O control disabled 3 ADC Pin Control 19. ADPC19 controls the pin associated with channel AD19. ADPC19 0 AD19 pin I/O control enabled 1 AD19 pin I/O control disabled 2 ADC Pin Control 18. ADPC18 controls the pin associated with channel AD18. ADPC18 0 AD18 pin I/O control enabled 1 AD18 pin I/O control disabled 1 ADC Pin Control 17. ADPC17 controls the pin associated with channel AD17. ADPC17 0 AD17 pin I/O control enabled 1 AD17 pin I/O control disabled 0 ADC Pin Control 16. ADPC16 controls the pin associated with channel AD16. ADPC16 0 AD16 pin I/O control enabled 1 AD16 pin I/O control disabled 10.4 Functional Description TheADCmoduleisdisabledduringresetorwhentheADCHbitsareallhigh.Themoduleisidlewhena conversion has completed and another conversion has not been initiated. When idle, the module is in its lowest power state. TheADCcanperformananalog-to-digitalconversiononanyofthesoftwareselectablechannels.In12-bit and 10-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a 12-bit digital result. In 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a 9-bit digital result. When the conversion is completed, the result is placed in the data registers (ADCRH and ADCRL). In 10-bit mode, the result is rounded to 10 bits and placed in the data registers (ADCRH and ADCRL). In 8-bit mode, the result is rounded to 8 bits and placed in ADCRL. The conversion complete flag (COCO) isthensetandaninterruptisgeneratediftheconversioncompleteinterrupthasbeenenabled(AIEN=1). The ADC module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates with any of the conversion modes and configurations. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 187

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.4.1 Clock Select and Divide Control One of four clock sources can be selected as the clock source for the ADC module. This clock source is then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is selected from one of the following sources by means of the ADICLK bits. • The bus clock, which is equal to the frequency at which software is executed. This is the default selection following reset. • The bus clock divided by two. For higher bus clock rates, this allows a maximum divide by 16 of the bus clock. • ALTCLK, as defined for this MCU (See module section introduction). • The asynchronous clock (ADACK). This clock is generated from a clock source within the ADC module.Whenselectedastheclocksource,thisclockremainsactivewhiletheMCUisinwaitor stop3 mode and allows conversions in these modes for lower noise operation. Whicheverclockisselected,itsfrequencymustfallwithinthespecifiedfrequencyrangeforADCK.Ifthe availableclocksaretooslow,theADCdonotperformaccordingtospecifications.Iftheavailableclocks aretoofast,theclockmustbedividedtotheappropriatefrequency.ThisdividerisspecifiedbytheADIV bits and can be divide-by 1, 2, 4, or 8. 10.4.2 Input Select and Pin Control Thepincontrolregisters(APCTL3,APCTL2,andAPCTL1)disabletheI/Oportcontrolofthepinsused asanaloginputs.Whenapincontrolregisterbitisset,thefollowingconditionsareforcedfortheassociated MCU pin: • The output buffer is forced to its high impedance state. • The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer disabled. • The pullup is disabled. 10.4.3 Hardware Trigger The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled whentheADTRGbitisset.ThissourceisnotavailableonallMCUs.Consultthemoduleintroductionfor information on the ADHWT source specific to this MCU. WhenADHWTsourceisavailableandhardwaretriggerisenabled(ADTRG=1),aconversionisinitiated ontherisingedgeofADHWT.Ifaconversionisinprogresswhenarisingedgeoccurs,therisingedgeis ignored.Incontinuousconvertconfiguration,onlytheinitialrisingedgetolaunchcontinuousconversions isobserved.Thehardwaretriggerfunctionoperatesinconjunctionwithanyoftheconversionmodesand configurations. 10.4.4 Conversion Control Conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined by the MODE bits.Conversionscanbeinitiatedbyasoftwareorhardwaretrigger.Inaddition,theADCmodulecanbe MC9S08DZ60 Series Data Sheet, Rev. 4 188 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) configuredforlowpoweroperation,longsampletime,continuousconversion,andautomaticcompareof the conversion result to a software determined compare value. 10.4.4.1 Initiating Conversions A conversion is initiated: • Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is selected. • Following a hardware trigger (ADHWT) event if hardware triggered operation is selected. • Following the transfer of the result to the data registers when continuous conversion is enabled. Ifcontinuousconversionsareenabled,anewconversionisautomaticallyinitiatedafterthecompletionof the current conversion. In software triggered operation, continuous conversions begin after ADCSC1 is writtenandcontinueuntilaborted.Inhardwaretriggeredoperation,continuousconversionsbeginaftera hardware trigger event and continue until aborted. 10.4.4.2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers, ADCRHandADCRL.ThisisindicatedbythesettingofCOCO.AninterruptisgeneratedifAIENishigh at the time that COCO is set. A blocking mechanism prevents a new result from overwriting previous data in ADCRH and ADCRL if thepreviousdataisintheprocessofbeingreadwhilein12-bitor10-bitMODE(theADCRHregisterhas beenreadbuttheADCRLregisterhasnot).Whenblockingisactive,thedatatransferisblocked,COCO is not set, and the new result is lost. In the case of single conversions with the compare function enabled andthecompareconditionfalse,blockinghasnoeffectandADCoperationisterminated.Inallothercases of operation, when a data transfer is blocked, another conversion is initiated regardless of the state of ADCO (single or continuous conversions enabled). If single conversions are enabled, the blocking mechanism could result in several discarded conversions and excess power consumption. To avoid this issue, the data registers must not be read after initiating a single conversion until the conversion completes. 10.4.4.3 Aborting Conversions Any conversion in progress is aborted when: • A write to ADCSC1 occurs (the current conversion will be aborted and a new conversion will be initiated, if ADCH are not all 1s). • A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of operation change has occurred and the current conversion is therefore invalid. • The MCU is reset. • The MCU enters stop mode with ADACK not enabled. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 189

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered. However,theycontinuetobethevaluestransferredafterthecompletionofthelastsuccessfulconversion. If the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states. 10.4.4.4 Power Control The ADC module remains in its idle state until a conversion is initiated.If ADACK is selected as the conversion clock source, the ADACK clock generator is also enabled. PowerconsumptionwhenactivecanbereducedbysettingADLPC.Thisresultsinalowermaximumvalue for f (see the electrical specifications). ADCK 10.4.4.5 Sample Time and Total Conversion Time The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus frequency,theconversionmode(8-bit,10-bitor12-bit),andthefrequencyoftheconversionclock(f ). ADCK After the module becomes active, sampling of the input begins. ADLSMP selects between short (3.5 ADCK cycles) and long (23.5 ADCK cycles) sample times.When sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digitalvalueoftheanalogsignal.TheresultoftheconversionistransferredtoADCRHandADCRLupon completion of the conversion algorithm. If the bus frequency is less than the f frequency, precise sample time for continuous conversions ADCK cannotbeguaranteedwhenshortsampleisenabled(ADLSMP=0).Ifthebusfrequencyislessthan1/11th ofthef frequency,precisesampletimeforcontinuousconversionscannotbeguaranteedwhenlong ADCK sample is enabled (ADLSMP=1). The maximum total conversion time for different conditions is summarized in Table10-13. Table10-13. Total Conversion Time vs. Control Conditions Conversion Type ADICLK ADLSMP Max Total Conversion Time Single or first continuous 8-bit 0x, 10 0 20 ADCK cycles + 5 bus clock cycles Single or first continuous 10-bit or 12-bit 0x, 10 0 23 ADCK cycles + 5 bus clock cycles Single or first continuous 8-bit 0x, 10 1 40 ADCK cycles + 5 bus clock cycles Single or first continuous 10-bit or 12-bit 0x, 10 1 43 ADCK cycles + 5 bus clock cycles Single or first continuous 8-bit 11 0 5μs + 20 ADCK + 5 bus clock cycles Single or first continuous 10-bit or 12-bit 11 0 5μs + 23 ADCK + 5 bus clock cycles Single or first continuous 8-bit 11 1 5μs + 40 ADCK + 5 bus clock cycles Single or first continuous 10-bit or 12-bit 11 1 5μs + 43 ADCK + 5 bus clock cycles Subsequent continuous 8-bit; xx 0 17 ADCK cycles f > f BUS ADCK Subsequent continuous 10-bit or 12-bit; xx 0 20 ADCK cycles f > f BUS ADCK Subsequent continuous 8-bit; xx 1 37 ADCK cycles f > f /11 BUS ADCK MC9S08DZ60 Series Data Sheet, Rev. 4 190 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) Table10-13. Total Conversion Time vs. Control Conditions Conversion Type ADICLK ADLSMP Max Total Conversion Time Subsequent continuous 10-bit or 12-bit; xx 1 40 ADCK cycles f > f /11 BUS ADCK Themaximumtotalconversiontimeisdeterminedbytheclocksourcechosenandthedivideratioselected. TheclocksourceisselectablebytheADICLKbits,andthedivideratioisspecifiedbytheADIVbits.For example,in10-bitmode,withthebusclockselectedastheinputclocksource,theinputclockdivide-by-1 ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is: 23 ADCK Cyc 5 bus Cyc Conversion time = + = 3.5 ms 8 MHz/1 8 MHz Number of bus cycles = 3.5 ms x 8 MHz = 28 cycles NOTE The ADCK frequency must be between f minimum and f ADCK ADCK maximum to meet ADC specifications. 10.4.5 Automatic Compare Function The compare function can be configured to check for an upper or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the comparevalue,COCOisset.Whencomparingtoalowerlimit(ACFGT=0),iftheresultislessthanthe compare value, COCO is set. The value generated by the addition of the conversion result and the two’s complement of the compare value is transferred to ADCRH and ADCRL. Upon completion of a conversion while the compare function is enabled, if the compare condition is not true,COCOisnotsetandnodataistransferredtotheresultregisters.AnADCinterruptisgeneratedupon the setting of COCO if the ADC interrupt is enabled (AIEN = 1). NOTE ThecomparefunctioncanmonitorthevoltageonachannelwhiletheMCU is in wait or stop3 mode. The ADC interrupt wakes the MCU when the compare condition is met. 10.4.6 MCU Wait Mode Operation Wait mode is a lower power-consumption standby mode from which recovery is fast because the clock sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until completion.ConversionscanbeinitiatedwhiletheMCUisinwaitmodebymeansofthehardwaretrigger or if continuous conversions are enabled. Thebusclock,busclockdividedbytwo,andADACKareavailableasconversionclocksourceswhilein wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 191

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this MCU. AconversioncompleteeventsetstheCOCOandgeneratesanADCinterrupttowaketheMCUfromwait mode if the ADC interrupt is enabled (AIEN = 1). 10.4.7 MCU Stop3 Mode Operation Stopmodeisalowpower-consumptionstandbymodeduringwhichmostorallclocksourcesontheMCU are disabled. 10.4.7.1 Stop3 Mode With ADACK Disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode. After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. 10.4.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteedADCoperation,theMCU’svoltageregulatormustremainactiveduringstop3mode.Consult the module introduction for configuration information for this MCU. IfaconversionisinprogresswhentheMCUentersstop3mode,itcontinuesuntilcompletion.Conversions can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. AconversioncompleteeventsetstheCOCOandgeneratesanADCinterrupttowaketheMCUfromstop3 mode if the ADC interrupt is enabled (AIEN = 1). NOTE TheADCmodulecanwakethesystemfromlow-powerstopandcausethe MCU to begin consuming run-level currents without generating a system level interrupt. To prevent this scenario, software should ensure the data transfer blocking mechanism (discussed inSection10.4.4.2, “Completing Conversions) is cleared when entering stop3 and continuing ADC conversions. 10.4.8 MCU Stop2 Mode Operation The ADC module is automatically disabled when the MCU enters stop2 mode. All module registers contain their reset values following exit from stop2. Therefore, the module must be re-enabled and re-configured following exit from stop2. MC9S08DZ60 Series Data Sheet, Rev. 4 192 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.5 Initialization Information This section gives an example that provides some basic direction on how to initialize and configure the ADC module. You can configure the module for 8-, 10-, or 12-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. Refer to Table 10-7, Table10-8, andTable10-9 for information used in this example. NOTE Hexadecimalvaluesdesignatedbyapreceding0x,binaryvaluesdesignated by a preceding %, and decimal values have no preceding character. 10.5.1 ADC Module Initialization Example 10.5.1.1 Initialization Sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is as follows: 1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio usedtogeneratetheinternalclock,ADCK.Thisregisterisalsousedforselectingsampletimeand low-power configuration. 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous orcompletedonlyonce,andtoenableordisableconversioncompleteinterrupts.Theinputchannel on which conversions will be performed is also selected here. 10.5.1.2 Pseudo-Code Example In this example, the ADC module is set up with interrupts enabled to perform a single 10-bit conversion atlowpowerwithalongsampletimeoninputchannel1,wheretheinternalADCKclockisderivedfrom the bus clock divided by 1. ADCCFG = 0x98 (%10011000) Bit 7 ADLPC 1 Configures for low power (lowers maximum clock speed) Bit 6:5 ADIV 00 Sets the ADCK to the input clock ÷ 1 Bit 4 ADLSMP 1 Configures for long sample time Bit 3:2 MODE 10 Sets mode at 10-bit conversions Bit 1:0 ADICLK 00 Selects bus clock as input clock source ADCSC2 = 0x00 (%00000000) Bit 7 ADACT 0 Flag indicates if a conversion is in progress Bit 6 ADTRG 0 Software trigger selected Bit 5 ACFE 0 Compare function disabled Bit 4 ACFGT 0 Not used in this example Bit 3:2 00 Reserved, always reads zero Bit 1:0 00 Reserved for Freescale’s internal use; always write zero MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 193

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ADCSC1 = 0x41 (%01000001) Bit 7 COCO 0 Read-only flag which is set when a conversion completes Bit 6 AIEN 1 Conversion complete interrupt enabled Bit 5 ADCO 0 One conversion only (continuous conversions disabled) Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel ADCRH/L = 0xxx Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that conversion data cannot be overwritten with data from the next conversion. ADCCVH/L = 0xxx Holds compare value when compare function enabled APCTL1=0x02 AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins Reset Initialize ADC ADCCFG = 0x98 ADCSC2 = 0x00 ADCSC1 = 0x41 Check No COCO=1? Yes Read ADCRH Then ADCRL To Clear COCO Bit Continue Figure10-13. Initialization Flowchart for Example MC9S08DZ60 Series Data Sheet, Rev. 4 194 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.6 Application Information ThissectioncontainsinformationforusingtheADCmoduleinapplications.TheADChasbeendesigned to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 10.6.1 External Pins and Routing ThefollowingsectionsdiscusstheexternalpinsassociatedwiththeADCmoduleandhowtheyshouldbe used for best results. 10.6.1.1 Analog Supply Pins The ADC module has analog power and ground supplies (V and V ) available as separate pins DDAD SSAD on some devices. V is shared on the same pin as the MCU digital V on some devices.On other SSAD SS devices,V andV aresharedwiththeMCUdigitalsupplypins.Inthesecases,thereareseparate SSAD DDAD padsfortheanalogsuppliesbondedtothesamepinasthecorrespondingdigitalsupplysothatsomedegree of isolation between the supplies is maintained. Whenavailableonaseparatepin,bothV andV mustbeconnectedtothesamevoltagepotential DDAD SSAD as their corresponding MCU digital supply (V and V ) and must be routed carefully for maximum DD SS noise immunity and bypass capacitors placed as near as possible to the package. If separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the V pin. This should be the only ground connection between these supplies if SSAD possible. The V pin makes a good single point ground location. SSAD 10.6.1.2 Analog Reference Pins Inadditiontotheanalogsupplies,theADCmodulehasconnectionsfortworeferencevoltageinputs.The high reference is V , which may be shared on the same pin as V on some devices. The low REFH DDAD reference is V , which may be shared on the same pin as V on some devices. REFL SSAD When available on a separate pin, V may be connected to the same potential as V , or may be REFH DDAD driven by an external source between the minimum V spec and the V potential (V must DDAD DDAD REFH never exceed V ). When available on a separate pin, V must be connected to the same voltage DDAD REFL potentialasV .V andV mustberoutedcarefullyformaximumnoiseimmunityandbypass SSAD REFH REFL capacitors placed as near as possible to the package. ACcurrentintheformofcurrentspikesrequiredtosupplychargetothecapacitorarrayateachsuccessive approximationstepisdrawnthroughtheV andV loop.Thebestexternalcomponenttomeetthis REFH REFL currentdemandisa0.1μFcapacitorwithgoodhighfrequencycharacteristics.Thiscapacitorisconnected betweenV andV andmustbeplacedasnearaspossibletothepackagepins.Resistanceinthe REFH REFL pathisnotrecommendedbecausethecurrentcausesavoltagedropthatcouldresultinconversionerrors. Inductance in this path must be minimum (parasitic only). MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 195

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.6.1.3 Analog Input Pins TheexternalanaloginputsaretypicallysharedwithdigitalI/OpinsonMCUdevices.ThepinI/Ocontrol is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be performed on inputs without the associated pin control register bit set. It is recommended that the pin controlregisterbitalwaysbesetwhenusingapinasananaloginput.Thisavoidsproblemswithcontention because the output buffer is in its high impedance state and the pullup is disabled. Also, the input buffer drawsDCcurrentwhenitsinputisnotatV orV .Settingthepincontrolregisterbitsforallpinsused DD SS as analog inputs should be done to achieve lowest operating current. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise orwhenthesourceimpedanceishigh.Useof0.01μFcapacitorswithgoodhigh-frequencycharacteristics issufficient.Thesecapacitorsarenotnecessaryinallcases,butwhenusedtheymustbeplacedasnearas possible to the package pins and be referenced toV . SSA For proper conversion, the input voltage must fall between V and V . If the input is equal to or REFH REFL exceedsV ,theconvertercircuitconvertsthesignalto0xFFF(fullscale12-bitrepresentation),0x3FF REFH (full scale 10-bit representation) or 0xFF (full scale 8-bit representation). If the input is equal to or less than V ,the converter circuit converts it to 0x000. Input voltages between V and V are REFL REFH REFL straight-line linear conversions. There is a brief current associated with V when the sampling REFL capacitorischarging.Theinputissampledfor3.5cyclesoftheADCKsourcewhenADLSMPislow,or 23.5cycles when ADLSMP is high. Forminimallossofaccuracyduetocurrentinjection,pinsadjacenttotheanaloginputpinsshouldnotbe transitioning during conversions. 10.6.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 10.6.2.1 Sampling Error Forproperconversions,theinputmustbesampledlongenoughtoachievetheproperaccuracy.Giventhe maximuminputresistanceofapproximately7kΩandinputcapacitanceofapproximately5.5pF,sampling towithin1/4LSB(at12-bitresolution)canbeachievedwithintheminimumsamplewindow(3.5cycles@ 8MHz maximum ADCK frequency) provided the resistance of the external analog source (R ) is kept AS below 2kΩ. Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time. 10.6.2.2 Pin Leakage Error LeakageontheI/Opinscancauseconversionerroriftheexternalanalogsourceresistance(R )ishigh. AS Ifthiserrorcannotbetoleratedbytheapplication,keepR lowerthanV / (2N*I )forlessthan AS DDAD LEAK 1/4LSB leakage error (N = 8 in 8-bit, 10 in 10-bit or 12 in 12-bit mode). MC9S08DZ60 Series Data Sheet, Rev. 4 196 Freescale Semiconductor

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.6.2.3 Noise-Induced Errors System noise that occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: • There is a 0.1μF low-ESR capacitor from V to V . REFH REFL • There is a 0.1μF low-ESR capacitor from V to V . DDAD SSAD • Ifinductiveisolationisusedfromtheprimarysupply,anadditional1μFcapacitorisplacedfrom V to V . DDAD SSAD • V (and V , if connected) is connected to V at a quiet point in the ground plane. SSAD REFL SS • Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the ADC conversion. — For software triggered conversions, immediately follow the write to ADCSC1 with a wait instruction or stop instruction. — Forstop3modeoperation,selectADACKastheclocksource.Operationinstop3reducesV DD noise but increases effective conversion time due to stop recovery. • There is no I/O switching, input or output, on the MCU during the conversion. Therearesomesituationswhereexternalsystemactivitycausesradiatedorconductednoiseemissionsor excessive V noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in DD waitorstop3orI/Oactivitycannotbehalted,theserecommendedactionsmayreducetheeffectofnoise on the accuracy: • Place a 0.01μF capacitor (C ) on the selected input channel to V or V (this improves AS REFL SSAD noise issues, but affects the sample rate based on the external analog source resistance). • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. • Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 10.6.2.4 Code Width and Quantization Error The ADC quantizes the ideal straight-line transfer function into 4096 steps (in 12-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the transition pointstoonecodeandthenext.TheidealcodewidthforanNbitconverter(inthiscaseNcanbe8,10or 12), defined as 1LSB, is: 1 lsb = (V - V ) / 2N Eqn.10-2 REFH REFL Thereisaninherentquantizationerrorduetothedigitizationoftheresult.For8-bitor10-bitconversions thecodetransitionswhenthevoltageisatthemidpointbetweenthepointswherethestraightlinetransfer functionisexactlyrepresentedbytheactualtransferfunction.Therefore,thequantizationerrorwillbe± 1/2lsbin8-or10-bitmode.Asaconsequence,however,thecodewidthofthefirst(0x000)conversionis only 1/2 lsb and the code width of the last (0xFF or 0x3FF) is 1.5 lsb. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 197

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) For 12-bit conversions the code transitions only after the full code width is present, so the quantization error is−1 lsb to 0 lsb and the code width of each step is 1 lsb. 10.6.2.5 Linearity Errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy. These errors are: • Zero-scaleerror(E )(sometimescalledoffset)—Thiserrorisdefinedasthedifferencebetween ZS the actual code width of the first conversion and the ideal code width (1/2lsbin 8-bit or 10-bit modesand1lsbin12-bitmode).Ifthefirstconversionis0x001,thedifferencebetweentheactual 0x001 code width and its ideal (1 lsb) is used. • Full-scale error (E ) — This error is defined as the difference between the actual code width of FS the last conversion and the ideal code width (1.5 lsbin 8-bit or 10-bit modes and 1LSB in 12-bit mode).Ifthelastconversionis0x3FE,thedifferencebetweentheactual0x3FEcodewidthandits ideal (1LSB) is used. • Differentialnon-linearity(DNL)—Thiserrorisdefinedastheworst-casedifferencebetweenthe actual code width and the ideal code width for all conversions. • Integralnon-linearity(INL)—Thiserrorisdefinedasthehighest-valuethe(absolutevalueofthe) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. • Totalunadjustederror(TUE)—Thiserrorisdefinedasthedifferencebetweentheactualtransfer function and the ideal straight-line transfer function and includes all forms of error. 10.6.2.6 Code Jitter, Non-Monotonicity, and Missing Codes Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the converteryieldsthelowercode(andvice-versa).However,evensmallamountsofsystemnoisecancause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage.Thisrangeisnormallyaround 1/2lsbin8-bitor10-bitmode,oraround2lsbin12-bitmode,and increases with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed inSection10.6.2.3 reduces this error. Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. MC9S08DZ60 Series Data Sheet, Rev. 4 198 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction Theinter-integratedcircuit(IIC)providesamethodofcommunicationbetweenanumberofdevices.The interface is designed to operate up to 100kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. All MC9S08DZ60 Series MCUs feature the IIC, as shown in the following block diagram. NOTE Drive strength must be disabled (DSE=0) for the IIC pins when using the IIC module for correct operation. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 199

Chapter11 Inter-Integrated Circuit (S08IICV2) HCS08 CORE PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 CPU ANALOG COMPARATOR ACMP1O ORT A PPTTAA34//PPIIAA34//AADDPP34/ACMP1O BKGD/MS (ACMP1) ACMP1- P PTA2/PIA2/ADP2/ACMP1- BDC BKP ACMP1+ PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK HCS08 SYSTEM CONTROL PTB7/PIB7/ADP15 RESET RESETS AND INTERRUPTS PTB6/PIB6/ADP14 MODES OF OPERATION PTB5/PIB5/ADP13 POWER MANAGEMENT T B PTB4/PIB4/ADP12 OR PTB3/PIB3/ADP11 8 P PTB2/PIB2/ADP10 COP LVD Q PTB1/PIB1/ADP9 R INT IRQ I ADP7-ADP0 PTB0/PIB0/ADP8 24-CHANNEL,12-BIT PTC7/ADP23 ADP15-ADP8 ANALOG-TO-DIGITAL PTC6/ADP22 VREFH CONVERTER (ADC) ADP23-ADP16 PTC5/ADP21 V VREFL T C PTC4/ADP20 DDA OR PTC3/ADP19 VSSA P PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 USER FLASH TPM1CH5 - PTD7/PID7/TPM1CH5 MC9S0DZ60 = 60K 6-CHANNEL TIMER/PWM TPM1CH0 6 MC9S0DZ48 = 48K MODULE (TPM1) TPM1CLK PTD6/PID6/TPM1CH4 MC9S0DZ32 = 32K PTD5/PID5/TPM1CH3 MC9S0DZ16 = 16K T D PTD4/PID4/TPM1CH2 TPM2CH1, OR PTD3/PID3/TPM1CH1 2-CHANNEL TIMER/PWM TPM2CH0 P PTD2/PID2/TPM1CH0 MODULE (TPM2) TPM2CLK PTD1/PID1/TPM2CH1 USER EEPROM PTD0/PID0/TPM2CH0 MC9S0DZ60 = 2K CONTROLLER AREA RxCAN PTE7/RxD2/RXCAN NETWORK (MSCAN) TxCAN PTE6/TxD2/TXCAN MISO PTE5/SDA/MISO MCU9SS0EDRZ R60A M= 4K INTSEERRFIAALC EP EMROIPDHUELREA (SLPI) SMPOSSCIK ORT E PPTTEE34//SSPCSL/CMKOSI SS P PTE2/SS RxD1 PTE1/RxD1 DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1 PTE0/TxD1 INTERFACE (SCI1) PTF7 ACMP2O ANALOG COMPARATOR PTF6/ACMP2O REAL-TIME COUNTER (RTC) (ACMP2) ACMP2- PTF5/ACMP2- ACMP2+ VVDDDD VOLTAGE IIC MODULE (IIC) SSCDLA PORT F PPPTTTFFF342///TATPPCMMM21PCC2LL+KK//SSDCAL RxD2 VSS REGULATOR PTF1/RxD2 V SERIAL COMMUNICATIONS TxD2 SS PTF0/TxD2 INTERFACE (SCI2) PTG5 MULTI-PURPOSE PTG4 CLOCK GENERATOR G PTG3 (MCG) T R PTG2 XTAL PO PTG1/XTAL OSCILLATOR (XOSC) EXTAL PTG0/EXTAL - V /V internally connected to V /V in 48-pin and 32-pin packages - Pin not connected in 48-pin and 32-pin packages REFH REFL DDA SSA - V and V pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package DD SS Figure11-1. MC9S08DZ60 Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 200 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1.1 Features The IIC includes these distinctive features: • Compatible with IIC bus standard • Multi-master operation • Software programmable for one of 64 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection • Repeated start signal generation • Acknowledge bit generation/detection • Bus busy detection • General call recognition • 10-bit address extension 11.1.2 Modes of Operation A brief description of the IIC in the various MCU modes is given here. • Run mode — This is the basic mode of operation. To conserve power in this mode, disable the module. • Wait mode — The module continues to operate while the MCU is in wait mode and can provide a wake-up interrupt. • Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 201

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1.3 Block Diagram Figure11-2 is a block diagram of the IIC. Address Data Bus Interrupt ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync In/Out Start Data Stop Shift Arbitration Register Control Clock Control Address Compare SCL SDA Figure11-2. IIC Functional Block Diagram 11.2 External Signal Description This section describes each user-accessible pin signal. 11.2.1 SCL — Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system. 11.2.2 SDA — Serial Data Line The bidirectional SDA is the serial data line of the IIC system. 11.3 Register Definition This section consists of the IIC register descriptions in address order. MC9S08DZ60 Series Data Sheet, Rev. 4 202 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) Refertothedirect-pageregistersummaryinthememorychapterofthisdocumentfortheabsoluteaddress assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 IIC Address Register (IICA) 7 6 5 4 3 2 1 0 R 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-3. IIC Address Register (IICA) Table11-1. IICA Field Descriptions Field Description 7–1 SlaveAddress.TheAD[7:1]fieldcontainstheslaveaddresstobeusedbytheIICmodule.Thisfieldisusedon AD[7:1] the 7-bit address scheme and the lower seven bits of the 10-bit address scheme. 11.3.2 IIC Frequency Divider Register (IICF) 7 6 5 4 3 2 1 0 R MULT ICR W Reset 0 0 0 0 0 0 0 0 Figure11-4. IIC Frequency Divider Register (IICF) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 203

Chapter 11 Inter-Integrated Circuit (S08IICV2) Table11-2. IICF Field Descriptions Field Description 7–6 IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider, MULT generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved 5–0 IICClockRate.TheICRbitsareusedtoprescalethebusclockforbitrateselection.ThesebitsandtheMULT ICR bits determine the IIC baud rate, the SDA hold time, the SCL Start hold time, and the SCL Stop hold time. Table11-4 provides the SCL divider and hold values for corresponding values of the ICR. The SCL divider multiplied by multiplier factor mul generates IIC baud rate. bus speed (Hz) IIC baud rate = --------------------------------------------- Eqn.11-1 mul×SCLdivider SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data). SDA hold time = bus period (s)× mul× SDA hold value Eqn.11-2 SCLstartholdtimeisthedelayfromthefallingedgeofSDA(IICdata)whileSCLishigh(Startcondition)tothe falling edge of SCL (IIC clock). SCL Start hold time = bus period (s)× mul × SCL Start hold value Eqn.11-3 SCL stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA SDA (IIC data) while SCL is high (Stop condition). SCL Stop hold time = bus period (s)× mul× SCL Stop hold value Eqn.11-4 Forexample,ifthebusspeedis8MHz,thetablebelowshowsthepossibleholdtimevalueswithdifferent ICR and MULT selections to achieve an IIC baud rate of 100kbps. Table11-3. Hold Time Values for 8 MHz Bus Speed Hold Times (μs) MULT ICR SDA SCL Start SCL Stop 0x2 0x00 3.500 3.000 5.500 0x1 0x07 2.500 4.000 5.250 0x1 0x0B 2.250 4.000 5.250 0x0 0x14 2.125 4.250 5.125 0x0 0x18 1.125 4.750 5.125 MC9S08DZ60 Series Data Sheet, Rev. 4 204 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) Table11-4. IIC Divider and Hold Values SCL Hold SDA Hold SCL Hold SCL Hold ICR SCL SDA Hold ICR SCL SDAHold (Start) (Stop) (Start) (Stop) (hex) Divider Value (hex) Divider Value Value Value Value Value 00 20 7 6 11 20 160 17 78 81 01 22 7 7 12 21 192 17 94 97 02 24 8 8 13 22 224 33 110 113 03 26 8 9 14 23 256 33 126 129 04 28 9 10 15 24 288 49 142 145 05 30 9 11 16 25 320 49 158 161 06 34 10 13 18 26 384 65 190 193 07 40 10 16 21 27 480 65 238 241 08 28 7 10 15 28 320 33 158 161 09 32 7 12 17 29 384 33 190 193 0A 36 9 14 19 2A 448 65 222 225 0B 40 9 16 21 2B 512 65 254 257 0C 44 11 18 23 2C 576 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129 446 449 13 72 13 30 37 33 1024 129 510 513 14 80 17 34 41 34 1152 193 574 577 15 88 17 38 45 35 1280 193 638 641 16 104 21 46 53 36 1536 257 766 769 17 128 21 58 65 37 1920 257 958 961 18 80 9 38 41 38 1280 129 638 641 19 96 9 46 49 39 1536 129 766 769 1A 112 17 54 57 3A 1792 257 894 897 1B 128 17 62 65 3B 2048 257 1022 1025 1C 144 25 70 73 3C 2304 385 1150 1153 1D 160 25 78 81 3D 2560 385 1278 1281 1E 192 33 94 97 3E 3072 513 1534 1537 1F 240 33 118 121 3F 3840 513 1918 1921 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 205

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.3 IIC Control Register (IICC1) 7 6 5 4 3 2 1 0 R 0 0 0 IICEN IICIE MST TX TXAK W RSTA Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-5. IIC Control Register (IICC1) Table11-5. IICC1 Field Descriptions Field Description 7 IIC Enable. The IICEN bit determines whether the IIC module is enabled. IICEN 0 IIC is not enabled 1 IIC is enabled 6 IIC Interrupt Enable. The IICIE bit determines whether an IIC interrupt is requested. IICIE 0 IIC interrupt request not enabled 1 IIC interrupt request enabled 5 Master Mode Select. The MST bit changes from a 0 to a 1 when a start signal is generated on the bus and MST master mode is selected. When this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 0 Slave mode 1 Master mode 4 Transmit Mode Select. The TX bit selects the direction of master and slave transfers. In master mode, this bit TX should be set according to the type of transfer required. Therefore, for address cycles, this bit is always high. When addressed as a slave, this bit should be set by software according to the SRW bit in the status register. 0 Receive 1 Transmit 3 Transmit Acknowledge Enable. This bit specifies the value driven onto the SDA during data acknowledge TXAK cycles for master and slave receivers. 0 An acknowledge signal is sent out to the bus after receiving one data byte 1 No acknowledge signal response is sent 2 Repeat start. Writing a 1 to this bit generates a repeated start condition provided it is the current master. This RSTA bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration. MC9S08DZ60 Series Data Sheet, Rev. 4 206 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.4 IIC Status Register (IICS) 7 6 5 4 3 2 1 0 R TCF BUSY 0 SRW RXAK IAAS ARBL IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-6. IIC Status Register (IICS) Table11-6. IICS Field Descriptions Field Description 7 Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or TCF immediatelyfollowingatransfertotheIICmoduleorfromtheIICmodule.TheTCFbitisclearedbyreadingthe IICD register in receive mode or writing to the IICD in transmit mode. 0 Transfer in progress 1 Transfer complete 6 Addressed as a Slave. The IAAS bit is set when the calling address matches the programmed slave address IAAS or when the GCAEN bit is set and a general call is received. Writing the IICC register clears this bit. 0 Not addressed 1 Addressed as a slave 5 Bus Busy. The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is BUSY set when a start signal is detected and cleared when a stop signal is detected. 0 Bus is idle 1 Bus is busy 4 ArbitrationLost.Thisbitissetbyhardwarewhenthearbitrationprocedureislost.TheARBLbitmustbecleared ARBL by software by writing a 1 to it. 0 Standard bus operation 1 Loss of arbitration 2 SlaveRead/Write.Whenaddressedasaslave,theSRWbitindicatesthevalueoftheR/Wcommandbitofthe SRW calling address sent to the master. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave 1 IIC Interrupt Flag. The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by IICIF writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit: • One byte transfer completes • Match of slave address to calling address • Arbitration lost 0 No interrupt pending 1 Interrupt pending 0 ReceiveAcknowledge.WhentheRXAKbitislow,itindicatesanacknowledgesignalhasbeenreceivedafter RXAK thecompletionofonebyteofdatatransmissiononthebus.IftheRXAKbitishighitmeansthatnoacknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 207

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.5 IIC Data I/O Register (IICD) 7 6 5 4 3 2 1 0 R DATA W Reset 0 0 0 0 0 0 0 0 Figure11-7. IIC Data I/O Register (IICD) Table11-7. IICD Field Descriptions Field Description 7–0 Data—Inmastertransmitmode,whendataiswrittentotheIICD,adatatransferisinitiated.Themostsignificant DATA bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data. NOTE When transitioning out of master receive mode, the IIC mode should be switched before reading the IICD register to prevent an inadvertent initiation of a master receive data transfer. In slave mode, the same functions are available after an address match has occurred. The TX bit in IICC must correctly reflect the desired direction of transfer in master and slave modes for thetransmissiontobegin.Forinstance,iftheIICisconfiguredformastertransmitbutamasterreceiveis desired, reading the IICD does not initiate the receive. Reading the IICD returns the last byte received while the IIC is configured in master receive or slave receive modes. The IICD does not reflect every byte transmitted on the IIC bus, nor can software verify that a byte has been written to the IICD correctly by reading it back. Inmastertransmitmode,thefirstbyteofdatawrittentoIICDfollowingassertionofMSTisusedforthe addresstransferandshouldcompriseofthecallingaddress(inbit7tobit1)concatenatedwiththerequired R/W bit (in position bit 0). 11.3.6 IIC Control Register 2 (IICC2) 7 6 5 4 3 2 1 0 R 0 0 0 GCAEN ADEXT AD10 AD9 AD8 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-8. IIC Control Register (IICC2) MC9S08DZ60 Series Data Sheet, Rev. 4 208 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) Table11-8. IICC2 Field Descriptions Field Description 7 General Call Address Enable. The GCAEN bit enables or disables general call address. GCAEN 0 General call address is disabled 1 General call address is enabled 6 Address Extension. The ADEXT bit controls the number of bits used for the slave address. ADEXT 0 7-bit address scheme 1 10-bit address scheme 2–0 Slave Address. The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address AD[10:8] scheme. This field is only valid when the ADEXT bit is set. 11.4 Functional Description This section provides a complete functional description of the IIC module. 11.4.1 IIC Protocol TheIICbussystemusesaserialdataline(SDA)andaserialclockline(SCL)fordatatransfer.Alldevices connectedtoitmusthaveopendrainoropencollectoroutputs.AlogicANDfunctionisexercisedonboth lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: • Start signal • Slave address transmission • Data transfer • Stop signal ThestopsignalshouldnotbeconfusedwiththeCPUstopinstruction.TheIICbussystemcommunication is described briefly in the following sections and illustrated in Figure11-9. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 209

Chapter 11 Inter-Integrated Circuit (S08IICV2) msb lsb msb lsb SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 Start Calling Address Read/ Ack Data Byte No Stop Signal Write Bit Ack Signal Bit msb lsb msb lsb SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Calling Address Read/ Ack Repeated New Calling Address Read/ No Stop Signal Write Bit Start Write Ack Signal Signal Bit Figure11-9. IIC Bus Transmission Signals 11.4.1.1 Start Signal When the bus is free, no master device is engaging the bus (SCL and SDA lines are at logical high), a master may initiate communication by sending a start signal. As shown in Figure11-9, a start signal is definedasahigh-to-lowtransitionofSDAwhileSCLishigh.Thissignaldenotesthebeginningofanew data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. 11.4.1.2 Slave Address Transmission The first byte of data transferred immediately after the start signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Onlytheslavewithacallingaddressthatmatchestheonetransmittedbythemasterrespondsbysending back an acknowledge bit. This is done by pulling the SDA low at the ninth clock (see Figure11-9). Notwoslavesinthesystemmayhavethesameaddress.IftheIICmoduleisthemaster,itmustnottransmit anaddressequaltoitsownslaveaddress.TheIICcannotbemasterandslaveatthesametime.However, ifarbitrationislostduringanaddresscycle,theIICrevertstoslavemodeandoperatescorrectlyevenifit is being addressed by another master. MC9S08DZ60 Series Data Sheet, Rev. 4 210 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.1.3 Data Transfer Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. Alltransfersthatcomeafteranaddresscyclearereferredtoasdatatransfers,eveniftheycarrysub-address information for the slave device Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure11-9. There is one clock pulse on SCL for each data bit, the msb being transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receivingdevice.AnacknowledgeissignalledbypullingtheSDAlowattheninthclock.Insummary,one complete data transfer needs nine clock pulses. Iftheslavereceiverdoesnotacknowledgethemasterintheninthbittime,theSDAlinemustbelefthigh by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer. Ifthemasterreceiverdoesnotacknowledgetheslavetransmitterafteradatabytetransmission,theslave interprets this as an end of data transfer and releases the SDA line. In either case, the data transfer is aborted and the master does one of two things: • Relinquishes the bus by generating a stop signal. • Commences a new calling by generating a repeated start signal. 11.4.1.4 Stop Signal The master can terminate the communication by generating a stop signal to free the bus. However, the master may generate a start signal followed by a calling command without generating a stop signal first. This is called repeated start. A stop signal is defined as a low-to-high transition of SDA while SCL at logical 1 (seeFigure11-9). The master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus. 11.4.1.5 Repeated Start Signal As shown inFigure11-9, a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 11.4.1.6 Arbitration Procedure The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or moremasterstrytocontrolthebusatthesametime,aclocksynchronizationproceduredeterminesthebus clock,forwhichthelowperiodisequaltothelongestclocklowperiodandthehighisequaltotheshortest oneamongthemasters.Therelativepriorityofthecontendingmastersisdeterminedbyadataarbitration procedure,abusmasterlosesarbitrationifittransmitslogic1whileanothermastertransmitslogic0.The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case, MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 211

Chapter 11 Inter-Integrated Circuit (S08IICV2) thetransitionfrommastertoslavemodedoesnotgenerateastopcondition.Meanwhile,astatusbitisset by hardware to indicate loss of arbitration. 11.4.1.7 Clock Synchronization Becausewire-ANDlogicisperformedontheSCLline,ahigh-to-lowtransitionontheSCLlineaffectsall thedevicesconnectedonthebus.Thedevicesstartcountingtheirlowperiodandafteradevice’sclockhas gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to highinthisdeviceclockmaynotchangethestateoftheSCLlineifanotherdeviceclockisstillwithinits low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (seeFigure11-10). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulledhigh.ThereisthennodifferencebetweenthedeviceclocksandthestateoftheSCLlineandallthe devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. Delay Start Counting High Period SCL1 SCL2 SCL Internal Counter Reset Figure11-10. IIC Clock Synchronization 11.4.1.8 Handshaking Theclocksynchronizationmechanismcanbeusedasahandshakeindatatransfer.Slavedevicesmayhold theSCLlowaftercompletionofonebytetransfer(9bits).Insuchacase,ithaltsthebusclockandforces the master clock into wait states until the slave releases the SCL line. 11.4.1.9 Clock Stretching Theclocksynchronizationmechanismcanbeusedbyslavestoslowdownthebitrateofatransfer.After the master has driven SCL low the slave can drive SCL low for the required period and then release it. If theslaveSCLlowperiodisgreaterthanthemasterSCLlowperiodthentheresultingSCLbussignallow period is stretched. MC9S08DZ60 Series Data Sheet, Rev. 4 212 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.2 10-bit Address For10-bitaddressing,0x11110isusedforthefirst5bitsofthefirstaddressbyte.Variouscombinationsof read/write formats are possible within a transfer that includes 10-bit addressing. 11.4.2.1 Master-Transmitter Addresses a Slave-Receiver The transfer direction is not changed (seeTable11-9). When a 10-bit address follows a start condition, each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own address and tests whether the eighth bit (R/W direction bit) is 0. More than one device can find a match and generate an acknowledge (A1). Then, each slave that finds a match compares the eight bits of the second byte of the slave address with its own address. Only one slave finds a match and generates an acknowledge(A2).Thematchingslaveremainsaddressedbythemasteruntilitreceivesastopcondition (P) or a repeated start condition (Sr) followed by a different slave address. Slave Address 1st 7 bits R/W Slave Address 2nd byte S A1 A2 Data A ... Data A/A P 11110 + AD10 + AD9 0 AD[8:1] Table11-9. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt. 11.4.2.2 Master-Receiver Addresses a Slave-Transmitter The transfer direction is changed after the second R/W bit (seeTable11-10). Up to and including acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. After the repeated start condition (Sr), a matching slave remembers that it was addressed before. This slave then checks whether the first seven bits of the first byte of the slave address following Srarethesameastheywereafterthestartcondition(S)andtestswhethertheeighth(R/W)bitis1.Ifthere isamatch,theslaveconsidersthatithasbeenaddressedasatransmitterandgeneratesacknowledgeA3. Theslave-transmitterremainsaddresseduntilitreceivesastopcondition(P)orarepeatedstartcondition (Sr) followed by a different slave address. Afterarepeatedstartcondition(Sr),allotherslavedevicesalsocomparethefirstsevenbitsofthefirstbyte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressedbecauseR/W=1(for10-bitdevices)orthe11110XXslaveaddress(for7-bitdevices)doesnot match. Slave Address Slave Address Slave Address R/W R/W S 1st 7 bits A1 2nd byte A2 Sr 1st 7 bits A3 Data A ... Data A P 11110 + AD10 + AD9 0 AD[8:1] 11110+AD10+AD9 1 Table11-10. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 213

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.3 General Call Address Generalcallscanberequestedin7-bitaddressor10-bitaddress.IftheGCAENbitisset,theIICmatches thegeneralcalladdressaswellasitsownslaveaddress.WhentheIICrespondstoageneralcall,itactsas aslave-receiverandtheIAASbitissetaftertheaddresscycle.SoftwaremustreadtheIICDregisterafter thefirstbytetransfertodeterminewhethertheaddressmatchesisitsownslaveaddressorageneralcall. Ifthevalueis00,thematchisageneralcall.IftheGCAENbitisclear,theIICignoresanydatasupplied from a general call address by not issuing an acknowledgement. 11.5 Resets The IIC is disabled after reset. The IIC cannot cause an MCU reset. 11.6 Interrupts The IIC generates a single interrupt. AninterruptfromtheIICisgeneratedwhenanyoftheeventsinTable11-11occur,providedtheIICIEbit isset.TheinterruptisdrivenbybitIICIF(oftheIICstatusregister)andmaskedwithbitIICIE(oftheIIC controlregister).TheIICIFbitmustbeclearedbysoftwarebywritinga1toitintheinterruptroutine.You can determine the interrupt type by reading the status register. Table11-11. Interrupt Summary Interrupt Source Status Flag Local Enable Complete 1-byte transfer TCF IICIF IICIE Match of received calling address IAAS IICIF IICIE Arbitration Lost ARBL IICIF IICIE 11.6.1 Byte Transfer Interrupt TheTCF(transfercompleteflag)bitissetatthefallingedgeoftheninthclocktoindicatethecompletion of byte transfer. 11.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register) or when the GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is interrupted,providedtheIICIEisset.TheCPUmustchecktheSRWbitandsetitsTxmodeaccordingly. 11.6.3 Arbitration Lost Interrupt TheIICisatruemulti-masterbusthatallowsmorethanonemastertobeconnectedonit.Iftwoormore masterstrytocontrolthebusatthesametime,therelativepriorityofthecontendingmastersisdetermined by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration process and the ARBL bit in the status register is set. MC9S08DZ60 Series Data Sheet, Rev. 4 214 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) Arbitration is lost in the following circumstances: • SDA sampled as a low when the master drives a high during an address or data transmit cycle. • SDAsampledasalowwhenthemasterdrivesahighduringtheacknowledgebitofadatareceive cycle. • A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing a 1 to it. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 215

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.7 Initialization/Application Information Module Initialization (Slave) 1. Write: IICC2 — to enable or disable general call — to select 10-bit or 7-bit addressing mode 2. Write: IICA — to set the slave address 3. Write: IICC1 — to enable IIC and interrupts 4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 5. Initialize RAM variables used to achieve the routine shown inFigure11-12 Module Initialization (Master) 1. Write: IICF — to set the IIC baud rate (example provided in this chapter) 2. Write: IICC1 — to enable IIC and interrupts 3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 4. Initialize RAM variables used to achieve the routine shown inFigure11-12 5. Write: IICC1 — to enable TX 6. Write: IICC1 — to enable MST (master mode) 7. Write: IICD — with the address of the target slave. (The lsb of this byte determines whether the communication is master receive or transmit.) Module Use TheroutineshowninFigure11-12canhandlebothmasterandslaveIICoperations.Forslaveoperation,an incoming IIC message that contains the proper address begins IIC communication. For master operation, communication must be initiated by writing to the IICD register. Register Model IICA AD[7:1] 0 When addressed as a slave (in slave mode), the module responds to this address IICF MULT ICR Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER)) IICC1 IICEN IICIE MST TX TXAK RSTA 0 0 Module configuration IICS TCF IAAS BUSY ARBL 0 SRW IICIF RXAK Module status flags IICD DATA Data register; Write to transmit IIC data read to read IIC data IICC2 GCAEN ADEXT 0 0 0 AD10 AD9 AD8 Address configuration Figure11-11. IIC Module Quick Start MC9S08DZ60 Series Data Sheet, Rev. 4 216 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) Clear IICIF Y Master N Mode ? TX Tx/Rx RX Y Arbitration Lost ? ? N Last Byte Transmitted Y Clear ARBL ? N RXAK=0 N Byte tLoa Bset Read Y N IAAS=1 Y IAAS=1 ? ? ? ? Y N Y N Address Transfer Data Transfer See Note 1 See Note 2 Y Y AdEdnr dC oyfcle Y Byte2 tnod B Lea sRtead (Read) SRW=1 TX/RX RX (Mast?er Rx) ? ? ? N N N(Write) TX Write Next Generate Set TX Y ACK from Set TXACK =1 Stop Signal Receiver Byte to IICD Mode (MST = 0) ? N Read Data Write Data Tx Next from IICD to IICD Byte and Store Switch to Set RX Switch to Rx Mode Mode Rx Mode Generate Read Data Dummy Read Dummy Read Dummy Read Stop Signal from IICD from IICD from IICD from IICD (MST = 0) and Store RTI NOTES: 1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a general call address, then the general call must be handled by user software. 2. When10-bitaddressingisusedtoaddressaslave,theslaveseesaninterruptfollowingthefirstbyteoftheextendedaddress.Usersoftwaremustensurethatfor this interrupt, the contents of IICD are ignored and not treated as a valid data transfer Figure11-12. Typical IIC Interrupt Routine MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 217

Chapter 11 Inter-Integrated Circuit (S08IICV2) MC9S08DZ60 Series Data Sheet, Rev. 4 218 Freescale Semiconductor

Chapter 12 Freescale Controller Area Network (S08MSCANV1) 12.1 Introduction The Freescale controller area network (MSCAN) is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991. To fully understand the MSCANspecification,itisrecommendedthattheBoschspecificationbereadfirsttogainfamiliaritywith the terms and concepts contained within this document. Though not exclusively intended for automotive applications, CAN protocol is designed to meet the specific requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified application software. The MSCAN module is available in all devices in the MC9S08DZ60 Series. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 219

Chapter12 Freescale Controller Area Network (S08MSCANV1) HCS08 CORE PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 CPU ANALOG COMPARATOR ACMP1O ORT A PPTTAA34//PPIIAA34//AADDPP34/ACMP1O BKGD/MS (ACMP1) ACMP1- P PTA2/PIA2/ADP2/ACMP1- BDC BKP ACMP1+ PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK HCS08 SYSTEM CONTROL PTB7/PIB7/ADP15 RESET RESETS AND INTERRUPTS PTB6/PIB6/ADP14 MODES OF OPERATION PTB5/PIB5/ADP13 POWER MANAGEMENT T B PTB4/PIB4/ADP12 OR PTB3/PIB3/ADP11 8 P PTB2/PIB2/ADP10 COP LVD Q PTB1/PIB1/ADP9 R INT IRQ I ADP7-ADP0 PTB0/PIB0/ADP8 24-CHANNEL,12-BIT PTC7/ADP23 ADP15-ADP8 ANALOG-TO-DIGITAL PTC6/ADP22 VREFH CONVERTER (ADC) ADP23-ADP16 PTC5/ADP21 V VREFL T C PTC4/ADP20 DDA OR PTC3/ADP19 VSSA P PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 USER FLASH TPM1CH5 - PTD7/PID7/TPM1CH5 MC9S0DZ60 = 60K 6-CHANNEL TIMER/PWM TPM1CH0 6 MC9S0DZ48 = 48K MODULE (TPM1) TPM1CLK PTD6/PID6/TPM1CH4 MC9S0DZ32 = 32K PTD5/PID5/TPM1CH3 MC9S0DZ16 = 16K T D PTD4/PID4/TPM1CH2 TPM2CH1, OR PTD3/PID3/TPM1CH1 2-CHANNEL TIMER/PWM TPM2CH0 P PTD2/PID2/TPM1CH0 MODULE (TPM2) TPM2CLK PTD1/PID1/TPM2CH1 USER EEPROM PTD0/PID0/TPM2CH0 MC9S0DZ60 = 2K CONTROLLER AREA RxCAN PTE7/RxD2/RXCAN NETWORK (MSCAN) TxCAN PTE6/TxD2/TXCAN MISO PTE5/SDA/MISO MCU9SS0EDRZ R60A M= 4K INTSEERRFIAALC EP EMROIPDHUELREA (SLPI) SMPOSSCIK ORT E PPTTEE34//SSPCSL/CMKOSI SS P PTE2/SS RxD1 PTE1/RxD1 DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1 PTE0/TxD1 INTERFACE (SCI1) PTF7 ACMP2O ANALOG COMPARATOR PTF6/ACMP2O REAL-TIME COUNTER (RTC) (ACMP2) ACMP2- PTF5/ACMP2- ACMP2+ VVDDDD VOLTAGE IIC MODULE (IIC) SSCDLA PORT F PPPTTTFFF342///TATPPCMMM21PCC2LL+KK//SSDCAL RxD2 VSS REGULATOR PTF1/RxD2 V SERIAL COMMUNICATIONS TxD2 SS PTF0/TxD2 INTERFACE (SCI2) PTG5 MULTI-PURPOSE PTG4 CLOCK GENERATOR G PTG3 (MCG) T R PTG2 XTAL PO PTG1/XTAL OSCILLATOR (XOSC) EXTAL PTG0/EXTAL - V /V internally connected to V /V in 48-pin and 32-pin packages - Pin not connected in 48-pin and 32-pin packages REFH REFL DDA SSA - V and V pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package DD SS Figure12-1. MC9S08DZ60 Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 220 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.1.1 Features The basic features of the MSCAN are as follows: • Implementation of the CAN protocol — Version 2.0A/B — Standard and extended data frames — Zero to eight bytes data length 1 — Programmable bit rate up to 1 Mbps — Support for remote frames • Five receive buffers with FIFO storage scheme • Three transmit buffers with internal prioritization using a “local priority” concept • Flexiblemaskableidentifierfiltersupportstwofull-size(32-bit)extendedidentifierfilters,orfour 16-bit filters, or eight 8-bit filters • Programmable wakeup functionality with integrated low-pass filter • Programmable loopback mode supports self-test operation • Programmable listen-only mode for monitoring of CAN bus • Programmable bus-off recovery functionality • Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off) • Programmable MSCAN clock source either bus clock or oscillator clock • Internal timer for time-stamping of received and transmitted messages • Three low-power modes: sleep, power down, and MSCAN enable • Global initialization of configuration registers 12.1.2 Modes of Operation ThefollowingmodesofoperationarespecifictotheMSCAN.SeeSection12.5,“FunctionalDescription,” for details. • Listen-Only Mode • MSCAN Sleep Mode • MSCAN Initialization Mode • MSCAN Power Down Mode • Loopback Self Test Mode 1.Depending on the actual bit timing and the clock jitter of the PLL. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 221

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.1.3 Block Diagram MSCAN Oscillator Clock CANCLK Tq Clk MUX Presc. Bus Clock RXCAN Receive/ Transmit Engine TXCAN Transmit Interrupt Req. Message Receive Interrupt Req. Control Filtering and and Errors Interrupt Req. Status Buffering Wake-Up Interrupt Req. Configuration Registers Wake-Up Low Pass Filter Figure12-2. MSCAN Block Diagram 12.2 External Signal Description The MSCAN uses two external pins: 12.2.1 RXCAN — CAN Receiver Input Pin RXCAN is the MSCAN receiver input pin. 12.2.2 TXCAN — CAN Transmitter Output Pin TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the CAN bus: 0 = Dominant state 1 = Recessive state 12.2.3 CAN System AtypicalCANsystemwithMSCANisshowninFigure12-3.EachCANnodeisconnectedphysicallyto the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current needed for the CAN bus and has current protection against defective CAN or defective nodes. MC9S08DZ60 Series Data Sheet, Rev. 4 222 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) CAN node 1 CAN node 2 CAN node n MCU CAN Controller (MSCAN) TXCAN RXCAN Transceiver CAN_H CAN_L CAN Bus Figure12-3. CAN System 12.3 Register Definition ThissectiondescribesindetailalltheregistersandregisterbitsintheMSCANmodule.Eachdescription includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read. 12.3.1 MSCAN Control Register 0 (CANCTL0) The CANCTL0 register provides various control bits of the MSCAN module as described below. 7 6 5 4 3 2 1 0 R RXFRM RXACT SYNCH CSWAI TIME WUPE SLPRQ INITRQ W Reset: 0 0 0 0 0 0 0 1 = Unimplemented Figure12-4. MSCAN Control Register 0 (CANCTL0) NOTE TheCANCTL0register,exceptWUPE,INITRQ,andSLPRQ,isheldinthe reset state when the initialization mode is active (INITRQ = 1 and INITAK= 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write:Anytimewhenoutofinitializationmode;exceptionsareread-onlyRXACTandSYNCH,RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode). MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 223

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-1. CANCTL0 Register Field Descriptions Field Description 7 ReceivedFrameFlag—Thisbitisreadandclearonly.Itissetwhenareceiverhasreceivedavalidmessage RXFRM1 correctly,independentlyofthefilterconfiguration.Afteritisset,itremainssetuntilclearedbysoftwareorreset. Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode. 0 No valid message was received since last clearing this flag 1 A valid message was received since last clearing of this flag 6 Receiver Active Status — This read-only flag indicates the MSCAN is receiving a message. The flag is RXACT controlled by the receiver front end. This bit is not valid in loopback mode. 0 MSCAN is transmitting or idle2 1 MSCAN is receiving a message (including when arbitration is lost)2 5 CANStopsinWaitMode—Enablingthisbitallowsforlowerpowerconsumptioninwaitmodebydisablingall CSWAI3 the clocks at the CPU bus interface to the MSCAN module. 0 The module is not affected during wait mode 1 The module ceases to be clocked during wait mode 4 SynchronizedStatus—Thisread-onlyflagindicateswhethertheMSCANissynchronizedtotheCANbusand SYNCH able to participate in the communication process. It is set and cleared by the MSCAN. 0 MSCAN is not synchronized to the CAN bus 1 MSCAN is synchronized to the CAN bus 3 TimerEnable—Thisbitactivatesaninternal16-bitwidefreerunningtimerwhichisclockedbythebitclockrate. TIME If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the activeTX/RXbuffer.AssoonasamessageisacknowledgedontheCANbus,thetimestampwillbewrittento the highest bytes (0x000E, 0x000F) in the appropriate buffer (seeSection12.4, “Programmer’s Model of MessageStorage”).Theinternaltimerisreset(allbitssetto0)whendisabled.Thisbitisheldlowininitialization mode. 0 Disable internal MSCAN timer 1 Enable internal MSCAN timer 2 Wake-UpEnable—ThisconfigurationbitallowstheMSCANtorestartfromsleepmodewhentrafficonCANis WUPE4 detected(seeSection12.5.5.4,“MSCANSleepMode”).Thisbitmustbeconfiguredbeforesleepmodeentryfor the selected function to take effect. 0 Wake-up disabled — The MSCAN ignores traffic on CAN 1 Wake-up enabled — The MSCAN is able to restart MC9S08DZ60 Series Data Sheet, Rev. 4 224 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-1. CANCTL0 Register Field Descriptions (continued) Field Description 1 Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving SLPRQ5 mode(seeSection12.5.5.4,“MSCANSleepMode”).ThesleepmoderequestisservicedwhentheCANbusis idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry to sleep mode by setting SLPAK = 1 (seeSection12.3.2, “MSCAN Control Register 1 (CANCTL1)”). SLPRQ cannotbesetwhiletheWUPIFflagisset(seeSection12.3.4.1,“MSCANReceiverFlagRegister(CANRFLG)”). SleepmodewillbeactiveuntilSLPRQisclearedbytheCPUor,dependingonthesettingofWUPE,theMSCAN detects activity on the CAN bus and clears SLPRQ itself. 0 Running — The MSCAN functions normally 1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle 0 Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see INITRQ6,7 Section12.5.5.5, “MSCAN Initialization Mode”). Any ongoing transmission or reception is aborted and synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1 (Section12.3.2, “MSCAN Control Register 1 (CANCTL1)”). The following registers enter their hard reset state and restore their default values: CANCTL08, CANRFLG9, CANRIER10, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the error counters are not affected by initialization mode. When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the MSCANisnotinbus-offstate,itsynchronizesafter11consecutiverecessivebitsontheCANbus;iftheMSCAN is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. Writing to otherbits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after initialization mode is exited, which is INITRQ = 0 and INITAK = 0. 0 Normal operation 1 MSCAN in initialization mode 1 The MSCAN must be in normal mode for this bit to become set. 2 See the Bosch CAN 2.0A/B specificationfor a detailed definition of transmitter and receiver states. 3 InordertoprotectfromaccidentallyviolatingtheCANprotocol,theTXCANpinisimmediatelyforcedtoarecessivestatewhen the CPU enters wait (CSWAI = 1) or stop mode (seeSection12.5.5.2, “Operation in Wait Mode” andSection12.5.5.3, . “Operation in Stop Mode”) 4 The CPU has to make sure that the WUPE bit and the WUPIE wake-up interrupt enable bit (seeSection12.3.5, “MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required. 5 The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1). 6 The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1). 7 InordertoprotectfromaccidentallyviolatingtheCANprotocol,theTXCANpinisimmediatelyforcedtoarecessivestatewhen the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode. 8 Not including WUPE, INITRQ, and SLPRQ. 9 TSTAT1 and TSTAT0 are not affected by initialization mode. 10RSTAT1 and RSTAT0 are not affected by initialization mode. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 225

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.3.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. 7 6 5 4 3 2 1 0 R SLPAK INITAK CANE CLKSRC LOOPB LISTEN BORM WUPM W Reset: 0 0 0 1 0 0 0 1 = Unimplemented Figure12-5. MSCAN Control Register 1(CANCTL1) Read: Anytime Write: Anytime when INITRQ=1 and INITAK=1, except CANE which is write once in normal and anytimeinspecialsystemoperationmodeswhentheMSCANisininitializationmode(INITRQ= 1and INITAK=1). Table12-2. CANCTL1 Register Field Descriptions Field Description 7 MSCAN Enable CANE 0 MSCAN module is disabled 1 MSCAN module is enabled 6 MSCANClockSource—ThisbitdefinestheclocksourcefortheMSCANmodule(onlyforsystemswithaclock CLKSRC generationmodule;Section12.5.3.3,“ClockSystem,”andSectionFigure12-42.,“MSCANClockingScheme,”). 0 MSCAN clock source is the oscillator clock 1 MSCAN clock source is the bus clock 5 LoopbackSelfTestMode—Whenthisbitisset,theMSCANperformsaninternalloopbackwhichcanbeused LOOPB for self test operation. The bit stream output of the transmitter is fed back to the receiver internally.Section12.5.4.6, “Loopback Self Test Mode. 0 Loopback self test disabled 1 Loopback self test enabled 4 ListenOnlyMode—ThisbitconfigurestheMSCANasaCANbusmonitor.WhenLISTENisset,allvalidCAN LISTEN messages with matching ID are received, but no acknowledgement or error frames are sent out (see Section12.5.4.4, “Listen-Only Mode”). In addition, the error counters are frozen. Listen only mode supports applications which require “hot plugging” or throughput analysis. The MSCAN is unable to transmit any messages when listen only mode is active. 0 Normal operation 1 Listen only mode activated 3 Bus-Off Recovery Mode — This bits configures the bus-off state recovery mode of the MSCAN. Refer to BORM Section12.6.2, “Bus-Off Recovery,” for details. 0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specification) 1 Bus-off recovery upon user request 2 Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is WUPM applied to protect the MSCAN from spurious wake-up (seeSection12.5.5.4, “MSCAN Sleep Mode”). 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of T wup MC9S08DZ60 Series Data Sheet, Rev. 4 226 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-2. CANCTL1 Register Field Descriptions (continued) Field Description 1 Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see SLPAK Section12.5.5.4, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ=1 and SLPAK=1. Depending on the setting of WUPE, the MSCAN will cleartheflagifitdetectsactivityontheCANbuswhileinsleepmode.CPUclearingtheSLPRQbitwillalsoreset the SLPAK bit. 0 Running — The MSCAN operates normally 1 Sleep mode active — The MSCAN has entered sleep mode 0 Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode INITAK (seeSection12.5.5.5,“MSCANInitializationMode”).ItisusedasahandshakeflagfortheINITRQinitialization mode request. Initialization mode is active when INITRQ=1 and INITAK=1. The registers CANCTL1, CANBTR0,CANBTR1,CANIDAC,CANIDAR0–CANIDAR7,andCANIDMR0–CANIDMR7canbewrittenonlyby the CPU when the MSCAN is in initialization mode. 0 Running — The MSCAN operates normally 1 Initialization mode active — The MSCAN is in initialization mode 12.3.3 MSCAN Bus Timing Register 0 (CANBTR0) The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module. 7 6 5 4 3 2 1 0 R SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 W Reset: 0 0 0 0 0 0 0 0 Figure12-6. MSCAN Bus Timing Register 0 (CANBTR0) Read: Anytime Write: Anytime in initialization mode (INITRQ=1 and INITAK=1) Table12-3. CANBTR0Register Field Descriptions Field Description 7:6 SynchronizationJumpWidth—Thesynchronizationjumpwidthdefinesthemaximumnumberoftimequanta SJW[1:0] (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus (seeTable12-4). 5:0 BaudRatePrescaler—Thesebitsdeterminethetimequanta(Tq)clockwhichisusedtobuildupthebittiming BRP[5:0] (seeTable12-5). Table12-4. Synchronization Jump Width SJW1 SJW0 Synchronization Jump Width 0 0 1 Tq clock cycle 0 1 2 Tq clock cycles 1 0 3 Tq clock cycles 1 1 4 Tq clock cycles MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 227

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-5. Baud Rate Prescaler BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P) 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : : : : : : 1 1 1 1 1 1 64 12.3.4 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module. 7 6 5 4 3 2 1 0 R SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 W Reset: 0 0 0 0 0 0 0 0 Figure12-7. MSCAN Bus Timing Register 1(CANBTR1) Read: Anytime Write: Anytime in initialization mode (INITRQ=1 and INITAK=1) Table12-6. CANBTR1 Register Field Descriptions Field Description 7 Sampling — This bit determines the number of CAN bus samples taken per bit time. SAMP 0 One sample per bit. 1 Three samples per bit1. If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If SAMP=1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit rates, it is recommended that only one sample is taken per bit time (SAMP = 0). 6:4 TimeSegment2—Timesegmentswithinthebittimefixthenumberofclockcyclesperbittimeandthelocation TSEG2[2:0] of the sample point (seeFigure12-43). Time segment 2 (TSEG2) values are programmable as shown in Table12-7. 3:0 TimeSegment1—Timesegmentswithinthebittimefixthenumberofclockcyclesperbittimeandthelocation TSEG1[3:0] of the sample point (seeFigure12-43). Time segment 1 (TSEG1) values are programmable as shown in Table12-8. 1 In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). MC9S08DZ60 Series Data Sheet, Rev. 4 228 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-7. Time Segment 2 Values TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 1 Tq clock cycle1 0 0 1 2 Tq clock cycles : : : : 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles 1 This setting is not valid. Please refer toTable12-35 for valid settings. Table12-8. Time Segment 1 Values TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 0 0 0 0 1 Tq clock cycle1 0 0 0 1 2 Tq clock cycles1 0 0 1 0 3 Tq clock cycles1 0 0 1 1 4 Tq clock cycles : : : : : 1 1 1 0 15 Tq clock cycles 1 1 1 1 16 Tq clock cycles 1 This setting is not valid. Please refer toTable12-35 for valid settings. The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown in Table 12-7 andTable12-8). Eqn.12-1 (Prescaler value) Bit Time= ------------------------------------------------------•(1+TimeSegment1+TimeSegment2) f CANCLK 12.3.4.1 MSCAN Receiver Flag Register (CANRFLG) Aflagcanbeclearedonlybysoftware(writinga1tothecorrespondingbitposition)whenthecondition which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the CANRIER register. 7 6 5 4 3 2 1 0 R RSTAT1 RSTAT0 TSTAT1 TSTAT0 WUPIF CSCIF OVRIF RXF W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure12-8. MSCAN Receiver Flag Register(CANRFLG) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 229

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) NOTE The CANRFLG register is held in the reset state1 when the initialization modeisactive(INITRQ=1andINITAK=1).Thisregisteriswritableagain as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored. Table12-9. CANRFLG Register Field Descriptions Field Description 7 Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (seeSection12.5.5.4, WUPIF “MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (seeSection12.3.1, “MSCAN Control Register 0 (CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set. 0 No wake-up activity observed while in sleep mode 1 MSCAN detected activity on the CAN bus and requested wake-up 6 CAN Status Change Interrupt Flag — This flag is set when the MSCAN changes its current CAN bus status CSCIF due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system on the actual CAN bus status (seeSection12.3.5, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking interrupt.Thatguaranteesthatthereceiver/transmitterstatusbits(RSTAT/TSTAT)areonlyupdatedwhennoCAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt is cleared again. 0 No change in CAN bus status occurred since last interrupt 1 MSCAN changed current CAN bus status 5:4 Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As RSTAT[1:0] soonasthestatuschangeinterruptflag(CSCIF)isset,thesebitsindicatetheappropriatereceiverrelatedCAN bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is: 00 RxOK:0≤ receive error counter≤ 96 01 RxWRN: 96< receive error counter≤ 127 10 RxERR: 127< receive error counter 11 Bus-off1: transmit error counter> 255 3:2 Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. TSTAT[1:0] Assoonasthestatuschangeinterruptflag(CSCIF)isset,thesebitsindicatetheappropriatetransmitterrelated CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is: 00 TxOK:0≤transmit error counter≤ 96 01 TxWRN: 96< transmit error counter≤ 127 10 TxERR: 127< transmit error counter≤ 255 11 Bus-Off:transmit error counter> 255 1.The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. MC9S08DZ60 Series Data Sheet, Rev. 4 230 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-9. CANRFLG Register Field Descriptions (continued) Field Description 1 OverrunInterruptFlag—Thisflagissetwhenadataoverrunconditionoccurs.Ifnotmasked,anerrorinterrupt OVRIF is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected 0 ReceiveBufferFullFlag—RXFissetbytheMSCANwhenanewmessageisshiftedinthereceiverFIFO.This RXF2 flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier, matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag prohibitstheshiftingofthenextFIFOentryintotheforegroundbuffer(RxFG).Ifnotmasked,areceiveinterrupt is pending while this flag is set. 0 No new message available within the RxFG 1 The receiver FIFO is not empty. A new message is available in the RxFG 1 RedundantInformationforthemostcriticalCANbusstatuswhichis“bus-off”.ThisonlyoccursiftheTxerrorcounterexceeds anumberof255errors.Bus-offaffectsthereceiverstate.Assoonasthetransmitterleavesitsbus-offstatethereceiverstate skips to RxOK too. Refer also to TSTAT[1:0] coding in this register. 2 To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs, reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition. 12.3.5 MSCAN Receiver Interrupt Enable Register (CANRIER) ThisregistercontainstheinterruptenablebitsfortheinterruptflagsdescribedintheCANRFLGregister. 7 6 5 4 3 2 1 0 R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W Reset: 0 0 0 0 0 0 0 0 Figure12-9. MSCAN Receiver Interrupt Enable Register (CANRIER) NOTE TheCANRIERregisterisheldintheresetstatewhentheinitializationmode isactive(INITRQ=1andINITAK=1).Thisregisteriswritablewhennotin initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. Read: Anytime Write: Anytime when not in initialization mode MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 231

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-10. CANRIER Register Field Descriptions Field Description 7 Wake-Up Interrupt Enable WUPIE1 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. 6 CAN Status Change Interrupt Enable CSCIE 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request. 5:4 ReceiverStatusChangeEnable—TheseRSTATenablebitscontrolthesensitivitylevelinwhichreceiverstate RSTATE[1:0] changesarecausingCSCIFinterrupts.IndependentofthechosensensitivityleveltheRSTATflagscontinueto indicate the actual receiver state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by receiver state changes. 01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”2 state. Discard other receiver state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 3:2 TransmitterStatusChangeEnable—TheseTSTATenablebitscontrolthesensitivitylevelinwhichtransmitter TSTATE[1:0] state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by transmitter state changes. 01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 1 Overrun Interrupt Enable OVRIE 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request. 0 Receiver Full Interrupt Enable RXFIE 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request. 1 WUPIE and WUPE(seeSection12.3.1, “MSCAN Control Register 0 (CANCTL0)”) must both be enabled if the recovery mechanism from stop or wait is required. 2 Bus-offstateisdefinedbytheCANstandard(seeBoschCAN2.0A/Bprotocolspecification:foronlytransmitters.Becausethe only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, thecodingoftheRXSTAT[1:0]flagsdefineanadditionalbus-offstateforthereceiver(seeSection12.3.4.1,“MSCANReceiver Flag Register (CANRFLG)”). 12.3.6 MSCAN Transmitter Flag Register (CANTFLG) The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register. MC9S08DZ60 Series Data Sheet, Rev. 4 232 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 7 6 5 4 3 2 1 0 R 0 0 0 0 0 TXE2 TXE1 TXE0 W Reset: 0 0 0 0 0 1 1 1 = Unimplemented Figure12-10. MSCAN Transmitter Flag Register (CANTFLG) NOTE The CANTFLG register is held in the reset state when the initialization modeisactive(INITRQ=1andINITAK=1).Thisregisteriswritablewhen not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write:AnytimeforTXExflagswhennotininitializationmode;writeof1clearsflag,writeof0isignored Table12-11. CANTFLG Register Field Descriptions Field Description 2:0 TransmitterBufferEmpty—Thisflagindicatesthattheassociatedtransmitmessagebufferisempty,andthus TXE[2:0] notscheduledfortransmission.TheCPUmustcleartheflagafteramessageissetupinthetransmitbufferand isduefortransmission.TheMSCANsetstheflagafterthemessageissentsuccessfully.Theflagisalsosetby the MSCAN when the transmission request is successfully aborted due to a pending abort request (see Section12.3.8,“MSCANTransmitterMessageAbortRequestRegister(CANTARQ)”).Ifnotmasked,atransmit interrupt is pending while this flag is set. ClearingaTXExflagalsoclearsthecorrespondingABTAKx(seeSection12.3.9,“MSCANTransmitterMessage AbortAcknowledgeRegister(CANTAAK)”).WhenaTXExflagisset,thecorrespondingABTRQxbitiscleared (seeSection12.3.8, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). Whenlisten-modeisactive(seeSection12.3.2,“MSCANControlRegister1(CANCTL1)”)theTXExflagscannot be cleared and no transmission is started. Readandwriteaccessestothetransmitbufferareblocked,ifthecorrespondingTXExbitiscleared(TXEx=0) and the buffer is scheduled for transmission. 0 The associated message buffer is full (loaded with a message due for transmission) 1 The associated message buffer is empty (not scheduled) 12.3.7 MSCAN Transmitter Interrupt Enable Register (CANTIER) This register contains the interrupt enable bits for the transmit buffer empty interrupt flags. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure12-11. MSCAN Transmitter Interrupt Enable Register (CANTIER) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 233

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) NOTE TheCANTIERregisterisheldintheresetstatewhentheinitializationmode isactive(INITRQ=1andINITAK=1).Thisregisteriswritablewhennot in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode Table12-12. CANTIER Register Field Descriptions Field Description 2:0 Transmitter Empty Interrupt Enable TXEIE[2:0] 0 No interrupt request is generated from this event. 1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. SeeSection12.5.2.2, “Transmit Structures” for details. 12.3.8 MSCAN Transmitter Message Abort Request Register (CANTARQ) The CANTARQ register allows abort request of messages queued for transmission. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure12-12. MSCAN Transmitter Message Abort Request Register (CANTARQ) NOTE The CANTARQ register is held in the reset state when the initialization modeisactive(INITRQ=1andINITAK=1).Thisregisteriswritablewhen not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode Table12-13. CANTARQ Register Field Descriptions Field Description 2:0 Abort Request — The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx=0) be ABTRQ[2:0] aborted. The MSCAN grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see Section12.3.6, “MSCAN Transmitter Flag Register (CANTFLG)”) and abort acknowledge flags (ABTAK, see Section12.3.9,“MSCANTransmitterMessageAbortAcknowledgeRegister(CANTAAK)”)aresetandatransmit interruptoccursifenabled.TheCPUcannotresetABTRQx.ABTRQxisresetwhenevertheassociatedTXEflag is set. 0 No abort request 1 Abort request pending MC9S08DZ60 Series Data Sheet, Rev. 4 234 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.3.9 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) TheCANTAAKregisterindicatesthesuccessfulabortofmessagesqueuedfortransmission,ifrequested by the appropriate bits in the CANTARQ register. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure12-13. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) NOTE The CANTAAK register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). Read: Anytime Write: Unimplemented for ABTAKx flags Table12-14. CANTAAK Register Field Descriptions Field Description 2:0 Abort Acknowledge — This flag acknowledges that a message was aborted due to a pending transmission ABTAK[2:0] abort request from the CPU. After a particular message buffer is flagged empty, this flag can be used by the applicationsoftwaretoidentifywhetherthemessagewasabortedsuccessfullyorwassentanyway.TheABTAKx flag is cleared whenever the corresponding TXE flag is cleared. 0 The message was not aborted. 1 The message was aborted. 12.3.10 MSCAN Transmit Buffer Selection Register (CANTBSEL) TheCANTBSELselectionsoftheactualtransmitmessagebuffer,whichisaccessibleintheCANTXFG register space. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 TX2 TX1 TX0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure12-14. MSCAN Transmit Buffer Selection Register (CANTBSEL) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 235

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) NOTE The CANTBSEL register is held in the reset state when the initialization modeisactive(INITRQ=1andINITAK=1).Thisregisteriswritablewhen not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode Table12-15. CANTBSEL Register Field Descriptions Field Description 2:0 Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG TX[2:0] register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit bufferTX1).Readandwriteaccessestotheselectedtransmitbufferwillbeblocked,ifthecorrespondingTXEx bitisclearedandthebufferisscheduledfortransmission(seeSection12.3.6,“MSCANTransmitterFlagRegister (CANTFLG)”). 0 The associated message buffer is deselected 1 The associated message buffer is selected, if lowest numbered bit The following gives a short programming example of the usage of the CANTBSEL register: Togetthenextavailabletransmitbuffer,applicationsoftwaremustreadtheCANTFLGregisterandwrite thisvaluebackintotheCANTBSELregister.InthisexampleTxbuffersTX1andTX2areavailable.The valuereadfromCANTFLGistherefore0b0000_0110.WhenwritingthisvaluebacktoCANTBSEL,the TxbufferTX1isselectedintheCANTXFGbecausethelowestnumberedbitsetto1isatbitposition1. Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. This mechanism eases the application software the selection of the next available Tx buffer. • LDD CANTFLG; value read is 0b0000_0110 • STD CANTBSEL; value written is 0b0000_0110 • LDD CANTBSEL; value read is 0b0000_0010 If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG buffer register. 12.3.11 MSCAN Identifier Acceptance Control Register (CANIDAC) The CANIDAC register is used for identifier filter acceptance control as described below. 7 6 5 4 3 2 1 0 R 0 0 0 IDHIT2 IDHIT1 IDHIT0 IDAM1 IDAM0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure12-15. MSCAN Identifier Acceptance Control Register (CANIDAC) MC9S08DZ60 Series Data Sheet, Rev. 4 236 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only Table12-16. CANIDAC Register Field Descriptions Field Description 5:4 IdentifierAcceptanceMode—TheCPUsetstheseflagstodefinetheidentifieracceptancefilterorganization IDAM[1:0] (seeSection12.5.3,“IdentifierAcceptanceFilter”).Table12-17summarizesthedifferentsettings.Infilterclosed mode, no message is accepted such that the foreground buffer is never reloaded. 2:0 Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see IDHIT[2:0] Section12.5.3, “Identifier Acceptance Filter”).Table12-18 summarizes the different settings. Table12-17. Identifier Acceptance Mode Settings IDAM1 IDAM0 Identifier Acceptance Mode 0 0 Two 32-bit acceptance filters 0 1 Four 16-bit acceptance filters 1 0 Eight 8-bit acceptance filters 1 1 Filter closed Table12-18. Identifier Acceptance Hit Indication IDHIT2 IDHIT1 IDHIT0 Identifier Acceptance Hit 0 0 0 Filter 0 hit 0 0 1 Filter 1 hit 0 1 0 Filter 2 hit 0 1 1 Filter 3 hit 1 0 0 Filter 4 hit 1 0 1 Filter 5 hit 1 1 0 Filter 6 hit 1 1 1 Filter 7 hit The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well. 12.3.12 MSCAN Miscellaneous Register (CANMISC) This register provides additional features. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 237

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 BOHOLD W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure12-16. MSCAN Miscellaneous Register (CANMISC) Read: Anytime Write: Anytime; write of ‘1’ clears flag; write of ‘0’ ignored Table12-19. CANMISC Register Field Descriptions Field Description 0 Bus-off State Hold Until User Request — If BORM is set inSection12.3.2, “MSCAN Control Register 1 BOHOLD (CANCTL1), this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from bus-off. Refer toSection12.6.2, “Bus-Off Recovery,” for details. 0 Module is not bus-off or recovery has been requested by user in bus-off state 1 Module is bus-off and holds this state until user request 12.3.13 MSCAN Receive Error Counter (CANRXERR) This register reflects the status of the MSCAN receive error counter. 7 6 5 4 3 2 1 0 R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure12-17. MSCAN Receive Error Counter (CANRXERR) Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK=1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. MC9S08DZ60 Series Data Sheet, Rev. 4 238 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.3.14 MSCAN Transmit Error Counter (CANTXERR) This register reflects the status of the MSCAN transmit error counter. 7 6 5 4 3 2 1 0 R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure12-18. MSCAN Transmit Error Counter (CANTXERR) Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK=1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. 12.3.15 MSCAN Identifier Acceptance Registers (CANIDAR0-7) On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section12.4.1, “Identifier Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section12.5.3, “Identifier Acceptance Filter”). Forextendedidentifiers,allfouracceptanceandmaskregistersareapplied.Forstandardidentifiers,only the first two (CANIDAR0/1, CANIDMR0/1) are applied. 7 6 5 4 3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 0 0 0 0 0 0 0 0 Figure12-19. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 239

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-20. CANIDAR0–CANIDAR3 Register Field Descriptions Field Description 7:0 AcceptanceCodeBits—AC[7:0]compriseauser-definedsequenceofbitswithwhichthecorrespondingbits AC[7:0] oftherelatedidentifierregister(IDRn)ofthereceivemessagebufferarecompared.Theresultofthiscomparison is then masked with the corresponding identifier mask register. 7 6 5 4 3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 0 0 0 0 0 0 0 0 Figure12-20. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table12-21. CANIDAR4–CANIDAR7 Register Field Descriptions Field Description 7:0 AcceptanceCodeBits—AC[7:0]compriseauser-definedsequenceofbitswithwhichthecorrespondingbits AC[7:0] oftherelatedidentifierregister(IDRn)ofthereceivemessagebufferarecompared.Theresultofthiscomparison is then masked with the corresponding identifier mask register. 12.3.16 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) Theidentifiermaskregisterspecifieswhichofthecorrespondingbitsintheidentifieracceptanceregister are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to programthelastthreebits(AM[2:0])inthemaskregistersCANIDMR1andCANIDMR5to“don’tcare.” Toreceivestandardidentifiersin16bitfiltermode,itisrequiredtoprogramthelastthreebits(AM[2:0]) in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.” 7 6 5 4 3 2 1 0 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 0 0 0 0 0 0 0 0 Figure12-21. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) MC9S08DZ60 Series Data Sheet, Rev. 4 240 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-22. CANIDMR0–CANIDMR3 Register Field Descriptions Field Description 7:0 AcceptanceMaskBits—Ifaparticularbitinthisregisteriscleared,thisindicatesthatthecorrespondingbitin AM[7:0] theidentifieracceptanceregistermustbethesameasitsidentifierbitbeforeamatchisdetected.Themessage isacceptedifallsuchbitsmatch.Ifabitisset,itindicatesthatthestateofthecorrespondingbitintheidentifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit (don’t care) 7 6 5 4 3 2 1 0 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 0 0 0 0 0 0 0 0 Figure12-22. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table12-23. CANIDMR4–CANIDMR7 Register Field Descriptions Field Description 7:0 AcceptanceMaskBits—Ifaparticularbitinthisregisteriscleared,thisindicatesthatthecorrespondingbitin AM[7:0] theidentifieracceptanceregistermustbethesameasitsidentifierbitbeforeamatchisdetected.Themessage isacceptedifallsuchbitsmatch.Ifabitisset,itindicatesthatthestateofthecorrespondingbitintheidentifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit (don’t care) 12.4 Programmer’s Model of Message Storage The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last twobytesofthismemorymap,theMSCANstoresaspecial16-bittimestamp,whichissampledfroman internal timer after successful transmission or reception of a message. This feature is only available for transmit and receiver buffers if the TIME bit is set (seeSection12.3.1, “MSCAN Control Register 0 (CANCTL0)”). The time stamp register is written by the MSCAN. The CPU can only read these registers. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 241

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-24. Message Buffer Organization Offset Register Access Address 0x00X0 Identifier Register 0 0x00X1 Identifier Register 1 0x00X2 Identifier Register 2 0x00X3 Identifier Register 3 0x00X4 Data Segment Register 0 0x00X5 Data Segment Register 1 0x00X6 Data Segment Register 2 0x00X7 Data Segment Register 3 0x00X8 Data Segment Register 4 0x00X9 Data Segment Register 5 0x00XA Data Segment Register 6 0x00XB Data Segment Register 7 0x00XC Data Length Register 0x00XD Transmit Buffer Priority Register1 0x00XE Time Stamp Register (High Byte)2 0x00XF Time Stamp Register (Low Byte)3 1 Not applicable for receive buffers 2 Read-only for CPU 3 Read-only for CPU Figure12-23 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure12-24. All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation1. All reserved or unused bits of the receive and transmit buffers always read ‘x’. 1.Exception: The transmit priority registers are 0 out of reset. MC9S08DZ60 Series Data Sheet, Rev. 4 242 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Register Bit 7 6 5 4 3 2 1 Bit0 Name R IDR0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 W R IDR1 ID20 ID19 ID18 SRR(1) IDE(1) ID17 ID16 ID15 W R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 IDR2 W R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR2 IDR3 W R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSR0 W R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSR1 W R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSR2 W R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSR3 W R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSR4 W R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSR5 W R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSR6 W R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSR7 W R DLC3 DLC2 DLC1 DLC0 DLR W = Unused, always read ‘x’ Figure12-23. Receive/Transmit Message Buffer — Extended Identifier Mapping 1 SRR and IDE are both 1s. 2 The position of RTR differs between extended and standard indentifier mapping. Read:Fortransmitbuffers,anytimewhenTXExflagisset(seeSection12.3.6,“MSCANTransmitterFlag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 243

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Section12.3.10,“MSCANTransmitBufferSelectionRegister(CANTBSEL)”).Forreceivebuffers,only when RXF flag is set (seeSection12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG)”). Write:Fortransmitbuffers,anytimewhenTXExflagisset(seeSection12.3.6,“MSCANTransmitterFlag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section12.3.10, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for receive buffers. Reset: Undefined (0x00XX) because of RAM-based implementation Register Bit 7 6 5 4 3 2 1 Bit 0 Name R IDR0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 W R IDR1 ID2 ID1 ID0 RTR1 IDE2 W R IDR2 W R IDR3 W = Unused, always read ‘x’ Figure12-24. Receive/Transmit Message Buffer — Standard Identifier Mapping 1 The position of RTR differs between extended and standard indentifier mapping. 2 IDE is 0. 12.4.1 Identifier Registers (IDR0–IDR3) Theidentifierregistersforanextendedformatidentifierconsistofatotalof32bits;ID[28:0],SRR,IDE, andRTRbits.Theidentifierregistersforastandardformatidentifierconsistofatotalof13bits;ID[10:0], RTR, and IDE bits. 12.4.1.1 IDR0–IDR3 for Extended Identifier Mapping 7 6 5 4 3 2 1 0 R ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 W Reset: x x x x x x x x Figure12-25. Identifier Register 0 (IDR0) — Extended Identifier Mapping MC9S08DZ60 Series Data Sheet, Rev. 4 244 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-25. IDR0 Register Field Descriptions— Extended Field Description 7:0 Extended Format Identifier —The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[28:21] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. 7 6 5 4 3 2 1 0 R ID20 ID19 ID18 SRR(1) IDE(1) ID17 ID16 ID15 W Reset: x x x x x x x x Figure12-26. Identifier Register 1 (IDR1) — Extended Identifier Mapping 1 SRR and IDE are both 1s. Table12-26. IDR1 Register Field Descriptions— Extended Field Description 7:5 Extended Format Identifier —The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[20:18] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. 4 Substitute Remote Request — This fixed recessive bit is used only in extended format. It must be set to 1 by SRR the user for transmission buffers and is stored as received on the CAN bus for receive buffers. 3 IDExtended—Thisflagindicateswhethertheextendedorstandardidentifierformatisappliedinthisbuffer.In IDE the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifierregisters.Inthecaseofatransmitbuffer,theflagindicatestotheMSCANwhattypeofidentifiertosend. 0 Standard format (11 bit) 1 Extended format (29 bit) 2:0 Extended Format Identifier —The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[17:15] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. 7 6 5 4 3 2 1 0 R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 W Reset: x x x x x x x x Figure12-27. Identifier Register 2 (IDR2) — Extended Identifier Mapping Table12-27. IDR2 Register Field Descriptions— Extended Field Description 7:0 Extended Format Identifier —The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[14:7] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 245

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 7 6 5 4 3 2 1 0 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W Reset: x x x x x x x x Figure12-28. Identifier Register 3 (IDR3) — Extended Identifier Mapping Table12-28. IDR3 Register Field Descriptions— Extended Field Description 7:1 Extended Format Identifier —The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[6:0] most significant bit and is transmitted first on the CAN bus during the arbithation procedure. The priority of an identifier is defined to be highest for the smallest binary number. 0 Remote Transmission Request — This flag reflects the status of the remote transmission request bit in the RTR CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame 12.4.2 IDR0–IDR3 for Standard Identifier Mapping 7 6 5 4 3 2 1 0 R ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 W Reset: x x x x x x x x Figure12-29. Identifier Register 0 — Standard Mapping Table12-29. IDR0 Register Field Descriptions— Standard Field Description 7:0 Standard Format Identifier —The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the ID[10:3] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits inTable12-30. 7 6 5 4 3 2 1 0 R ID2 ID1 ID0 RTR IDE(1) W Reset: x x x x x x x x = Unused; always read ‘x’ Figure12-30. Identifier Register 1 — Standard Mapping 1 IDE is 0. MC9S08DZ60 Series Data Sheet, Rev. 4 246 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-30. IDR1 Register Field Descriptions Field Description 7:5 Standard Format Identifier —The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the ID[2:0] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits inTable12-29. 4 RemoteTransmissionRequest—ThisflagreflectsthestatusoftheRemoteTransmissionRequestbitinthe RTR CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame 3 IDExtended—Thisflagindicateswhethertheextendedorstandardidentifierformatisappliedinthisbuffer.In IDE the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifierregisters.Inthecaseofatransmitbuffer,theflagindicatestotheMSCANwhattypeofidentifiertosend. 0 Standard format (11 bit) 1 Extended format (29 bit) 7 6 5 4 3 2 1 0 R W Reset: x x x x x x x x = Unused; always read ‘x’ Figure12-31. Identifier Register 2 — Standard Mapping 7 6 5 4 3 2 1 0 R W Reset: x x x x x x x x = Unused; always read ‘x’ Figure12-32. Identifier Register 3 — Standard Mapping 12.4.3 Data Segment Registers (DSR0-7) The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 247

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 7 6 5 4 3 2 1 0 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W Reset: x x x x x x x x Figure12-33. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping Table12-31. DSR0–DSR7 Register Field Descriptions Field Description 7:0 Data bits 7:0 DB[7:0] 12.4.4 Data Length Register (DLR) This register keeps the data length field of the CAN frame. 7 6 5 4 3 2 1 0 R DLC3 DLC2 DLC1 DLC0 W Reset: x x x x x x x x = Unused; always read “x” Figure12-34. Data Length Register (DLR) — Extended Identifier Mapping Table12-32. DLR Register Field Descriptions Field Description 3:0 DataLengthCodeBits—Thedatalengthcodecontainsthenumberofbytes(databytecount)oftherespective DLC[3:0] message.Duringthetransmissionofaremoteframe,thedatalengthcodeistransmittedasprogrammedwhile the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table12-33 shows the effect of setting the DLC bits. MC9S08DZ60 Series Data Sheet, Rev. 4 248 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-33. Data Length Codes Data Length Code Data Byte Count DLC3 DLC2 DLC1 DLC0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 12.4.5 Transmit Buffer Priority Register (TBPR) Thisregisterdefinesthelocalpriorityoftheassociatedmessagetransmitbuffer.Thelocalpriorityisused for the internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms: • All transmission buffers with a cleared TXEx flag participate in the prioritization immediately before the SOF (start of frame) is sent. • The transmission buffer with the lowest local priority field wins the prioritization. Incasesofmorethanonebufferhavingthesamelowestpriority,themessagebufferwiththelowerindex number wins. 7 6 5 4 3 2 1 0 R PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 W Reset: 0 0 0 0 0 0 0 0 Figure12-35. Transmit Buffer Priority Register (TBPR) Read: Anytime when TXEx flag is set (seeSection12.3.6, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section12.3.10, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Anytime when TXEx flag is set (see Section12.3.6, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section12.3.10, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). 12.4.6 Time Stamp Register (TSRH–TSRL) If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active transmit or receive buffer as soon as a message has been acknowledged on the CAN bus (see MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 249

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Section12.3.1,“MSCANControlRegister0(CANCTL0)”).Incaseofatransmission,theCPUcanonly read the time stamp after the respective transmit buffer has been flagged empty. Thetimervalue,whichisusedforstamping,istakenfromafreerunninginternalCANbitclock.Atimer overrunisnotindicatedbytheMSCAN.Thetimerisreset(allbitssetto0)duringinitializationmode.The CPU can only read the time stamp registers. 7 6 5 4 3 2 1 0 R TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 W Reset: x x x x x x x x Figure12-36. Time Stamp Register — High Byte (TSRH) 7 6 5 4 3 2 1 0 R TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 W Reset: x x x x x x x x Figure12-37. Time Stamp Register — Low Byte (TSRL) Read: Anytime when TXEx flag is set (seeSection12.3.6, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section12.3.10, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Unimplemented 12.5 Functional Description 12.5.1 General This section provides a complete functional description of the MSCAN. It describes each of the features and modes listed in the introduction. MC9S08DZ60 Series Data Sheet, Rev. 4 250 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.2 Message Storage CAN CPU12 Receive / Transmit Memory Mapped Engine I/O Rx0 Rx1 Rx2 MSCAN G Rx3 B Rx4 x R RXF CPU bus G Receiver F x R Tx0 TXE0 G B x T PRIO Tx1 TXE1 CPU bus MSCAN G F x T PRIO Tx2 TXE2 G B Transmitter x PRIO T Figure12-38. User Model for Message Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 251

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: • AnyCANnodeisabletosendoutastreamofscheduledmessageswithoutreleasingtheCANbus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration. • The internal message queue within any CAN node is organized such that the highest priority message is sent out first, if more than one message is ready to be sent. Thebehaviordescribedinthebulletsabovecannotbeachievedwithasingletransmitbuffer.Thatbuffer mustbereloadedimmediatelyafterthepreviousmessageissent.Thisloadingprocesslastsafiniteamount of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a message is finished while the CPU re-loads the second buffer. No buffer would then be ready for transmission, and the CAN bus would be released. At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN has three transmit buffers. ThesecondrequirementcallsforsomesortofinternalprioritizationwhichtheMSCANimplementswith the “local priority” concept described inSection12.5.2.2, “Transmit Structures.” 12.5.2.2 Transmit Structures The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. The three buffers are arranged as shown in Figure12-38. Allthreebuffershavea13-bytedatastructuresimilartotheoutlineofthereceivebuffers(seeSection12.4, “Programmer’s Model of Message Storage”). An additionalSection12.4.5, “Transmit Buffer Priority Register (TBPR) contains an 8-bit local priority field (PRIO) (seeSection12.4.5, “Transmit Buffer PriorityRegister(TBPR)”).Theremainingtwobytesareusedfortimestampingofamessage,ifrequired (seeSection12.4.6, “Time Stamp Register (TSRH–TSRL)”). To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (TXEx) flag (see Section12.3.6, “MSCAN Transmitter Flag Register (CANTFLG)”).Ifatransmitbufferisavailable,theCPUmustsetapointertothisbufferbywritingtothe CANTBSEL register (seeSection12.3.10, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see Section12.4, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the CANTBSEL register simplifies the transmit buffer selection. In addition, this scheme makes the handler software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag. MC9S08DZ60 Series Data Sheet, Rev. 4 252 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) The MSCAN then schedules the message for transmission and signals the successful transmission of the bufferbysettingtheassociatedTXEflag.Atransmitinterrupt(seeSection12.5.7.2,“TransmitInterrupt”) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer. IfmorethanonebufferisscheduledfortransmissionwhentheCANbusbecomesavailableforarbitration, the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this purpose,everytransmitbufferhasan8-bitlocalpriorityfield(PRIO).Theapplicationsoftwareprograms this field when the message is set up. The local priority reflects the priority of this particular message relativetothesetofmessagesbeingtransmittedfromthisnode.ThelowestbinaryvalueofthePRIOfield is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error. Whenahighprioritymessageisscheduledbytheapplicationsoftware,itmaybecomenecessarytoabort a lower priority message in one of the three transmit buffers. Because messages that are already in transmissioncannotbeaborted,theusermustrequesttheabortbysettingthecorrespondingabortrequest bit (ABTRQ) (seeSection12.3.8, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”.) The MSCAN then grants the request, if possible, by: 1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register. 2. Setting the associated TXE flag to release the buffer. 3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the settingoftheABTAKflagwhetherthemessagewasaborted(ABTAK=1)orsent(ABTAK=0). 12.5.2.3 Receive Structures The received messages are stored in a five stage input FIFO. The five message buffers are alternately mapped into a single memory area (seeFigure12-38). The background receive buffer (RxBG) is exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (seeFigure12-38). This scheme simplifies the handler software because only one address area is applicable for the receive process. All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or extended), the data contents, and a time stamp, if enabled (seeSection12.4, “Programmer’s Model of Message Storage”). The receiver full flag (RXF) (seeSection12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG)”) signalsthestatusoftheforegroundreceivebuffer.Whenthebuffercontainsacorrectlyreceivedmessage with a matching identifier, this flag is set. On reception, each message is checked to see whether it passes the filter (see Section12.5.3, “Identifier Acceptance Filter”) and simultaneously is written into the active RxBG. After successful reception of a valid message, the MSCAN shifts the content of RxBG into the receiver FIFO2, sets the RXF flag, and generates a receive interrupt (seeSection12.5.7.3, “Receive Interrupt”) to the CPU3. The user’s receive handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the interruptandtoreleasetheforegroundbuffer.Anewmessage,whichcanfollowimmediatelyaftertheIFS 1.The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. 2.Only if the RXF flag is not set. 3.The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 253

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO. When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the backgroundreceivebuffer,RxBG,butdoesnotshiftitintothereceiverFIFO,generateareceiveinterrupt, or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see Section12.3.2, “MSCAN Control Register 1 (CANCTL1)”) where the MSCAN treats its own messages exactlylikeallotherincomingmessages.TheMSCANreceivesitsowntransmittedmessagesintheevent that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver. An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly receivedmessageswithacceptedidentifiersandanothermessageiscorrectlyreceivedfromtheCANbus withanacceptedidentifier.Thelattermessageisdiscardedandanerrorinterruptwithoverrunindication is generated if enabled (seeSection12.5.7.5, “Error Interrupt”). The MSCAN remains able to transmit messages while the receiver FIFO is full, but all incoming messages are discarded. As soon as a receive buffer in the FIFO is available again, new valid messages will be accepted. 12.5.3 Identifier Acceptance Filter TheMSCANidentifieracceptanceregisters(seeSection12.3.11,“MSCANIdentifierAcceptanceControl Register (CANIDAC)”) define the acceptable patterns of the standard or extended identifier (ID[10:0] or ID[28:0]). Any of these bits can be marked ‘don’t care’ in the MSCAN identifier mask registers (see Section12.3.16, “MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)”). Afilterhitisindicatedtotheapplicationsoftwarebyasetreceivebufferfullflag(RXF=1)andthreebits in the CANIDAC register (see Section12.3.11, “MSCAN Identifier Acceptance Control Register (CANIDAC)”). These identifier hit flags (IDHIT[2:0]) clearly identify the filter section that caused the acceptance.Theysimplifytheapplicationsoftware’stasktoidentifythecauseofthereceiverinterrupt.If more than one hit occurs (two or more filters match), the lower hit has priority. A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is programmable to operate in four different modes (see Bosch CAN 2.0A/B protocol specification): • Two identifier acceptance filters, each to be applied to: — The full 29 bits of the extended identifier and to the following bits of the CAN 2.0B frame: – Remote transmission request (RTR) – Identifier extension (IDE) – Substitute remote request (SRR) — The11bitsofthestandardidentifierplustheRTRandIDEbitsoftheCAN2.0A/Bmessages1. This mode implements two filters for a full length CAN 2.0B compliant extended identifier. Figure12-39 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a filter 1 hit. 1.Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters for standard identifiers MC9S08DZ60 Series Data Sheet, Rev. 4 254 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) • Four identifier acceptance filters, each to be applied to — a)the14mostsignificantbitsoftheextendedidentifierplustheSRRandIDEbitsofCAN2.0B messages or — b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure12-40 shows how the first 32-bit filter bank (CANIDAR0–CANIDA3, CANIDMR0–3CANIDMR) produces filter 0 and 1 hits. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 2 and 3 hits. • Eightidentifieracceptancefilters,eachtobeappliedtothefirst8bitsoftheidentifier.Thismode implements eight independent filters for the first 8 bits of a CAN 2.0A/B compliant standard identifier or a CAN 2.0B compliant extended identifier. Figure12-41 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces filter 0 to 3 hits. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 4 to 7 hits. • Closed filter. No CAN message is copied into the foreground buffer RxFG, and the RXF flag is never set. CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 ID7 ID6 IDR3 RTR CAN 2.0A/B Standard Identifier ID10 IDR0 ID3 ID2 IDR1 IDE ID10 IDR2 ID3 ID10 IDR3 ID3 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 0 Hit) Figure12-39. 32-bit Maskable Identifier Acceptance Filter MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 255

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 ID7 ID6 IDR3 RTR CAN 2.0A/B ID10 IDR0 ID3 ID2 IDR1 IDE ID10 IDR2 ID3 ID10 IDR3 ID3 Standard Identifier AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 ID Accepted (Filter 0 Hit) AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 1 Hit) Figure12-40. 16-bit Maskable Identifier Acceptance Filters MC9S08DZ60 Series Data Sheet, Rev. 4 256 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 ID7 ID6 IDR3 RTR CAN 2.0A/B ID10 IDR0 ID3 ID2 IDR1 IDE ID10 IDR2 ID3 ID10 IDR3 ID3 Standard Identifier AM7 CIDMR0 AM0 AC7 CIDAR0 AC0 ID Accepted (Filter 0 Hit) AM7 CIDMR1 AM0 AC7 CIDAR1 AC0 ID Accepted (Filter 1 Hit) AM7 CIDMR2 AM0 AC7 CIDAR2 AC0 ID Accepted (Filter 2 Hit) AM7 CIDMR3 AM0 AC7 CIDAR3 AC0 ID Accepted (Filter 3 Hit) Figure12-41. 8-bit Maskable Identifier Acceptance Filters MSCANfilterusesthreesetsofregisterstoprovidethefilterconfiguration.Firstly,theCANIDACregister determines the configuration of the banks into filter sizes and number of filters. Secondly, registers CANIDMR0/1/2/3determinethosebitsonwhichthefilterwilloperatebyplacinga‘0’attheappropriate MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 257

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) bit position in the filter register. Finally, registers CANIDAR0/1/2/3 determine the value of those bits determined by CANIDMR0/1/2/3. For instance in the case of the filter value of: 0001x1001x0 The CANIDMR0/1/2/3 register would be configured as: 00001000010 andsoallmessageidentifierbitsexceptbit1andbit6wouldbecomparedagainsttheCANIDAR0/1/2/3 registers. These would be configured as: 00010100100 In this case bits 1 and 6 are set to ‘0’, but since they are ignored it is equally valid to set them to ‘1’. 12.5.3.1 Identifier Acceptance Filters example Asdescribedabove,filtersworkbycomparisonstoindividualbitsintheCANmessageidentifierfield.The filterwillcheckeachoneoftheelevenbitsofastandardCANmessageidentifier.Supposeafiltervalueof 0001x1001x0. In this simple example, there are only three possible CAN messages. Filter value: 0001x1001x0 Message 1: 00011100110 Message 2: 00110100110 Message 3: 00010100100 Message 2 will be rejected since its third most significant bit is not ‘0’ - 001. The filter is simply a convenientwayofdefiningthesetofmessagesthattheCPUmustreceive.Forfull29-bitsofanextended CANmessageidentifier,thefilteridentifiestwosetsofmessages:onesetthatitreceivesandonesetthat itrejects.Alternatively,thefiltermaybesplitintotwo.ThisallowstheMSCANtoexamineonlythefirst 16 bits of a message identifier, but allows two separate filters to perform the checking. See the example below: Filter value A: 0001x1001x0 Filter value B: 00x101x01x0 Message 1: 00011100110 Message 2: 00110100110 Message 3: 00010100100 MSCAN will accept all three messages. Filter A will accept messages 1 and 3 as before and filter B will accept message 2. In practice, it is unimportant which filter accepts the message - messages accepted by either will be placed in the input buffer. A message may be accepted by more than one filter. MC9S08DZ60 Series Data Sheet, Rev. 4 258 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.3.2 Protocol Violation Protection TheMSCANprotectstheuserfromaccidentallyviolatingtheCANprotocolthroughprogrammingerrors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • AllregisterswhichcontroltheconfigurationoftheMSCANcannotbemodifiedwhiletheMSCAN is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers (see Section12.3.1, “MSCAN Control Register 0 (CANCTL0)”) serve as a lock to protect the following registers: — MSCAN control 1 register (CANCTL1) — MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1) — MSCAN identifier acceptance control register (CANIDAC) — MSCAN identifier acceptance registers (CANIDAR0–CANIDAR7) — MSCAN identifier mask registers (CANIDMR0–CANIDMR7) • TheTXCANpinisimmediatelyforcedtoarecessivestatewhentheMSCANgoesintothepower down mode or initialization mode (seeSection12.5.5.6, “MSCAN Power Down Mode,” and Section12.5.5.5, “MSCAN Initialization Mode”). • The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which providesfurther protection against inadvertently disabling the MSCAN. 12.5.3.3 Clock System Figure12-42 shows the structure of the MSCAN clock generation circuitry. MSCAN Bus Clock Time quanta clock (Tq) CANCLK Prescaler (1 .. 64) CLKSRC CLKSRC Oscillator Clock Figure12-42. MSCAN Clocking Scheme The clock source bit (CLKSRC) in the CANCTL1 register (12.3.2/-226) defines whether the internal CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. Theclocksourcehastobechosensuchthatthetightoscillatortolerancerequirements(upto0.4%)ofthe CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the clock is required. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 259

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. PLL lock may also be too wide to ensure adequate clock tolerance. For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN. Eqn.12-2 f CANCLK = ------------------------------------------------------ Tq (Prescaler value) A bit time is subdivided into three segments as described in the Bosch CAN specification. (see Figure12-43): • SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. • Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard.ItcanbeprogrammedbysettingtheparameterTSEG1toconsistof4to16timequanta. • Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long. Eqn.12-3 f Tq Bit Rate= --------------------------------------------------------------------------------- (number of Time Quanta) NRZ Signal Time Segment 1 Time Segment 2 SYNC_SEG (PROP_SEG + PHASE_SEG1) (PHASE_SEG2) 1 4 ... 16 2 ... 8 8 ... 25 Time Quanta = 1 Bit Time Transmit Point Sample Point (single or triple sampling) Figure12-43. Segments within the Bit Time MC9S08DZ60 Series Data Sheet, Rev. 4 260 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-34. Time Segment Syntax Syntax Description System expects transitions to occur on the CAN bus during this SYNC_SEG period. A node in transmit mode transfers a new value to the CAN bus at Transmit Point this point. A node in receive mode samples the CAN bus at this point. If the Sample Point three samples per bit option is selected, then this point marks the position of the third sample. The synchronization jump width (see the Bosch CAN specification for details) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. TheSYNC_SEG,TSEG1,TSEG2,andSJWparametersaresetbyprogrammingtheMSCANbustiming registers (CANBTR0, CANBTR1) (seeSection12.3.3, “MSCAN Bus Timing Register 0 (CANBTR0)” andSection12.3.4, “MSCAN Bus Timing Register 1 (CANBTR1)”). Table12-35 gives an overview of the CAN compliant segment settings and the related parameter values. NOTE Itistheuser’sresponsibilitytoensurethebittimesettingsareincompliance with the CAN standard. Table12-35. CAN Standard Compliant Bit Time Segment Settings Synchronization Time Segment 1 TSEG1 Time Segment 2 TSEG2 SJW Jump Width 5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3 12.5.4 Modes of Operation 12.5.4.1 Normal Modes TheMSCANmodulebehavesasdescribedwithinthisspecificationinallnormalsystemoperationmodes. 12.5.4.2 Special Modes TheMSCANmodulebehavesasdescribedwithinthisspecificationinallspecialsystemoperationmodes. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 261

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.4.3 Emulation Modes In all emulation modes, the MSCAN module behaves just like normal system operation modes as described within this specification. 12.5.4.4 Listen-Only Mode InanoptionalCANbusmonitoringmode(listen-only),theCANnodeisabletoreceivevaliddataframes and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a transmision.IftheMACsub-layerisrequiredtosenda“dominant”bit(ACKbit,overloadflag,oractive errorflag),thebitisreroutedinternallysothattheMACsub-layermonitorsthis“dominant”bit,although the CAN bus may remain in recessive state externally. 12.5.4.5 Security Modes The MSCAN module has no security features. 12.5.4.6 Loopback Self Test Mode Loopbackselftestmodeissometimesusedtochecksoftware,independentofconnectionsintheexternal system,tohelpisolatesystemproblems.Inthismode,thetransmitteroutputisinternallyconnectedtothe receiverinput.TheRXCANinputpinisignoredandtheTXCANoutputgoestotherecessivestate(logic 1).TheMSCANbehavesasitdoesnormallywhentransmittingandtreatsitsowntransmittedmessageas amessagereceivedfromaremotenode.Inthisstate,theMSCANignoresthebitsentduringtheACKslot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated. 12.5.5 Low-Power Options If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving. If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power consumption,comparedtonormalmode:sleepandpowerdownmode.Insleepmode,powerconsumption is reduced by stopping all clocks except those to access the registers from the CPU side. In power down mode, all clocks are stopped and no power is consumed. Table12-36 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits. Forallmodes,anMSCANwake-upinterruptcanoccuronlyiftheMSCANisinsleepmode(SLPRQ=1 and SLPAK = 1), wake-up functionality is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE=1). MC9S08DZ60 Series Data Sheet, Rev. 4 262 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Table12-36. CPU vs. MSCAN Operating Modes MSCAN Mode Reduced Power Consumption CPU Mode Normal Disabled Sleep Power Down (CANE=0) CSWAI = X1 CSWAI = X CSWAI = X Run SLPRQ = 0 SLPRQ = 1 SLPRQ = X SLPAK = 0 SLPAK = 1 SLPAK = X CSWAI = 0 CSWAI = 0 CSWAI = 1 CSWAI = X Wait SLPRQ = 0 SLPRQ = 1 SLPRQ = X SLPRQ = X SLPAK = 0 SLPAK = 1 SLPAK = X SLPAK = X CSWAI = X2 CSWAI = X CSWAI = X Stop3 SLPRQ = 1 SLPRQ = 0 SLPRQ = X SLPAK = 1 SLPAK = 0 SLPAK = X CSWAI = X CSWAI = X Stop1 or 2 SLPRQ = X SLPRQ = X SLPAK = X SLPAK = X 1 ‘X’ means don’t care. 2 For a safe wake up from Sleep mode, SLPRQ and SLPAK must be set to 1 before going into Stop3 mode. 12.5.5.1 Operation in Run Mode AsshowninTable12-36,onlyMSCANsleepmodeisavailableaslowpoweroptionwhentheCPUisin run mode. 12.5.5.2 Operation in Wait Mode TheWAITinstructionputstheMCUinalowpowerconsumptionstand-bymode.IftheCSWAIbitisset, additional power can be saved in power down mode because the CPU clocks are stopped. After leaving this power down mode, the MSCAN restarts its internal controllers and enters normal mode again. While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode). The MSCAN can also operate in any of the low-powermodesdependingonthevaluesoftheSLPRQ/SLPAKandCSWAIbitsasseeninTable12-36. 12.5.5.3 Operation in Stop Mode TheSTOPinstructionputstheMCUinalowpowerconsumptionstand-bymode.Instop1orstop2modes, the MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK.In stop3 mode, power down or sleep modes are determined by the SLPRQ/SLPAK values set prior to entering stop3. CSWAI bit has no function in any of the stop modes.Table12-36. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 263

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.5.4 MSCAN Sleep Mode The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a fixed synchronization delay and its current activity: • Ifthereareoneormoremessagebuffersscheduledfortransmission(TXEx=0),theMSCANwill continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode. • If the MSCANis receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle. • If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode. Bus Clock Domain CAN Clock Domain SLPRQ SLPRQ SYNC sync. Flag CPU SLPRQ Sleep Request SLPAK sync. SYNC SLPAK Flag SLPAK MSCAN in Sleep Mode Figure12-44. Sleep Request / Acknowledge Cycle NOTE Theapplicationsoftwaremustavoidsettingupatransmission(byclearing oneormoreTXExflag(s))andimmediatelyrequestsleepmode(bysetting SLPRQ).WhethertheMSCANstartstransmittingorgoesintosleepmode directly depends on the exact sequence of operations. Ifsleepmodeisactive,theSLPRQandSLPAKbitsareset(Figure12-44).Theapplicationsoftwaremust use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode. Wheninsleepmode(SLPRQ=1andSLPAK=1),theMSCANstopsitsinternalclocks.However,clocks that allow register accesses from the CPU side continue to run. If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. The TXCAN pin remains in a recessive state. If RXF = 1, the message can be read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. ItispossibletoaccessthetransmitbuffersandtocleartheassociatedTXEflags.Nomessageaborttakes place while in sleep mode. MC9S08DZ60 Series Data Sheet, Rev. 4 264 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) IftheWUPEbitinCANCLT0isnotasserted,theMSCANwillmaskanyactivityitdetectsonCAN.The RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode (Figure12-45). WUPE must be set before entering sleep mode to take effect. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 265

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) The MSCAN is able to leave sleep mode (wake up) only when: • CAN bus activity occurs and WUPE = 1 or • the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK=1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. Thereceivemessagebuffers(RxFGandRxBG)containmessagesiftheywerereceivedbeforesleepmode wasentered.Allpendingactionswillbeexecuteduponwake-up;copyingofRxBGintoRxFG,message abortsandmessagetransmissions.IftheMSCANremainsinbus-offstateaftersleepmodewasexited,it continues counting the 128 occurrences of 11 consecutive recessive bits. CAN Activity (CAN Activity & WUPE) |SLPRQ Wait StartUp for Idle CAN Activity SLPRQ CAN Activity & Idle Sleep SLPRQ (CAN Activity &WUPE) | CAN Activity CAN Activity & CAN Activity SLPRQ Tx/Rx Message Active CAN Activity Figure12-45. Simplified State Transitions for Entering/Leaving Sleep Mode MC9S08DZ60 Series Data Sheet, Rev. 4 266 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.5.5 MSCAN Initialization Mode Ininitializationmode,anyon-goingtransmissionorreceptionisimmediatelyabortedandsynchronization totheCANbusislost,potentiallycausingCANprotocolviolations.ToprotecttheCANbussystemfrom fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when initialization mode is entered. The recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the INITRQbitintheCANCTL0register.Otherwise,theabortofanon-going message can cause an error condition and can impact other CAN bus devices. Ininitializationmode,theMSCANisstopped.However,interfaceregistersremainaccessible.Thismode is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMRmessagefilters.SeeSection12.3.1,“MSCANControlRegister0(CANCTL0),”foradetailed description of the initialization mode. Bus Clock Domain CAN Clock Domain INIT INITRQ SYNC sync. Flag CPU INITRQ Init Request INITAK sync. SYNC INITAK Flag INITAK Figure12-46. Initialization Request/Acknowledge Cycle DuetoindependentclockdomainswithintheMSCAN,INITRQmustbesynchronizedtoalldomainsby using a special handshake mechanism. This handshake causes additional synchronization delay (see SectionFigure12-46., “Initialization Request/Acknowledge Cycle”). If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the INITAK flag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into initialization mode. NOTE TheCPUcannotclearINITRQbeforeinitializationmode(INITRQ=1and INITAK=1) is active. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 267

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.5.6 MSCAN Power Down Mode The MSCAN is in power down mode (Table12-36) when • CPU is in stop mode or • CPU is in wait mode and the CSWAI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when power down mode is entered. The recommended procedure is to bring the MSCANintoSleepmodebeforetheSTOPorWAITinstruction(ifCSWAI isset)isexecuted.Otherwise,theabortofanongoingmessagecancausean error condition and impact other CAN bus devices. In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleepmodebeforepowerdownmodebecameactive,themoduleperformsaninternalrecoverycycleafter powering up. This causes some fixed delay before the module enters normal mode again. 12.5.5.7 Programmable Wake-Up Function The MSCAN can be programmed to wake up the MSCAN as soon as CAN bus activity is detected (see control bit WUPE inSection12.3.1, “MSCAN Control Register 0 (CANCTL0)”). The sensitivity to existingCANbusactioncanbemodifiedbyapplyingalow-passfilterfunctiontotheRXCANinputline while in sleep mode (see control bit WUPM inSection12.3.2, “MSCAN Control Register 1 (CANCTL1)”). ThisfeaturecanbeusedtoprotecttheMSCANfromwake-upduetoshortglitchesontheCANbuslines. Such glitches can result from—for example—electromagnetic interference within noisy environments. 12.5.6 Reset Initialization The reset state of each individual bit is listed in Section12.3, “Register Definition,” which details all the registers and their bit-fields. 12.5.7 Interrupts ThissectiondescribesallinterruptsoriginatedbytheMSCAN.Itdocumentstheenablebitsandgenerated flags. Each interrupt is listed and described separately. MC9S08DZ60 Series Data Sheet, Rev. 4 268 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.5.7.1 Description of Interrupt Operation TheMSCANsupportsfourinterruptvectors(seeTable12-37),anyofwhichcanbeindividuallymasked (fordetailsseesectionsfromSection12.3.5,“MSCANReceiverInterruptEnableRegister(CANRIER),” toSection12.3.7, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”). NOTE The dedicated interrupt vector addresses are defined in the Resets and Interrupts chapter. Table12-37. Interrupt Vectors Interrupt Source CCR Mask Local Enable Wake-Up Interrupt (WUPIF) I bit CANRIER (WUPIE) Error Interrupts Interrupt (CSCIF, OVRIF) I bit CANRIER (CSCIE, OVRIE) Receive Interrupt (RXF) I bit CANRIER (RXFIE) Transmit Interrupts (TXE[2:0]) I bit CANTIER (TXEIE[2:0]) 12.5.7.2 Transmit Interrupt Atleastoneofthethreetransmitbuffersisempty(notscheduled)andcanbeloadedtoscheduleamessage for transmission. The TXEx flag of the empty message buffer is set. 12.5.7.3 Receive Interrupt A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. ThisinterruptisgeneratedimmediatelyafterreceivingtheEOFsymbol.TheRXFflagisset.Ifthereare multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer. 12.5.7.4 Wake-Up Interrupt Awake-upinterruptisgeneratedifactivityontheCANbusoccursduringMSCANinternalsleepmode. WUPE (seeSection12.3.1, “MSCAN Control Register 0 (CANCTL0)”) must be enabled. 12.5.7.5 Error Interrupt An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition occurrs.Section12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions: • Overrun—AnoverrunconditionofthereceiverFIFOasdescribedinSection12.5.2.3,“Receive Structures,” occurred. • CAN Status Change — The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change, which caused the error condition, is indicated by the TSTAT and RSTAT flags (see MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 269

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) Section12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG)” andSection12.3.5, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). 12.5.7.6 Interrupt Acknowledge Interrupts are directly associated with one or more status flags in either theSection12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG)” or the Section12.3.6, “MSCAN Transmitter Flag Register (CANTFLG).” Interrupts are pending as long as one of the corresponding flags is set. The flags in CANRFLGandCANTFLGmustberesetwithintheinterrupthandlertohandshaketheinterrupt.Theflags are reset by writing a 1 to the corresponding bit position. A flag cannot be cleared if the respective condition prevails. NOTE It must be guaranteed that the CPU clears only the bit causing the current interrupt.Forthisreason,bitmanipulationinstructions(BSET)mustnotbe used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine. 12.5.7.7 Recovery from Stop or Wait TheMSCANcanrecoverfromstoporwaitviathewake-upinterrupt.Thisinterruptcanonlyoccurifthe MSCANwasinsleepmode(SLPRQ=1andSLPAK=1)beforeenteringpowerdownmode,thewake-up option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1). 12.6 Initialization/Application Information 12.6.1 MSCAN initialization The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3. Clear INITRQ to leave initialization mode and enter normal mode If the configuration of registers which are writable in initialization mode needs to be changed only when the MSCAN module is in normal mode: 1. BringthemoduleintosleepmodebysettingSLPRQandawaitingSLPAKtoassertaftertheCAN bus becomes idle. 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the configuration registers in initialization mode 4. Clear INITRQ to leave initialization mode and continue in normal mode MC9S08DZ60 Series Data Sheet, Rev. 4 270 Freescale Semiconductor

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.6.2 Bus-Off Recovery The bus-off recovery is user configurable. The bus-off state can either be exited automatically or on user request. For reasons of backwards compatibility, the MSCAN defaults to automatic recovery after reset. In this case, the MSCAN will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the CAN bus (See the Bosch CAN specification for details). IftheMSCANisconfiguredforuserrequest(BORMsetinSection12.3.2,“MSCANControlRegister1 (CANCTL1)”), the recovery from bus-off starts after both independent events have become true: • 128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored • BOHOLDinSection12.3.12,“MSCANMiscellaneousRegister(CANMISC)hasbeenclearedby the user These two events may occur in any order. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 271

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) MC9S08DZ60 Series Data Sheet, Rev. 4 272 Freescale Semiconductor

Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1 Introduction Theserialperipheralinterface(SPI)moduleprovidesforfull-duplex,synchronous,serialcommunication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, memories, etc. The SPI runs at a baud rate up to the bus clock divided by two in master mode and bus clock divided by four in slave mode. AlldevicesintheMC9S08DZ60SeriesMCUscontainoneSPImodule,asshowninthefollowingblock diagram. NOTE EnsurethattheSPIshouldnotbedisabled(SPE=0)atthesametimeasabit change to the CPHA bit. These changes should be performed as separate operations or unexpected behavior may occur. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 273

Chapter13 Serial Peripheral Interface (S08SPIV3) HCS08 CORE PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 CPU ANALOG COMPARATOR ACMP1O ORT A PPTTAA34//PPIIAA34//AADDPP34/ACMP1O BKGD/MS (ACMP1) ACMP1- P PTA2/PIA2/ADP2/ACMP1- BDC BKP ACMP1+ PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK HCS08 SYSTEM CONTROL PTB7/PIB7/ADP15 RESET RESETS AND INTERRUPTS PTB6/PIB6/ADP14 MODES OF OPERATION PTB5/PIB5/ADP13 POWER MANAGEMENT T B PTB4/PIB4/ADP12 OR PTB3/PIB3/ADP11 8 P PTB2/PIB2/ADP10 COP LVD Q PTB1/PIB1/ADP9 R INT IRQ I ADP7-ADP0 PTB0/PIB0/ADP8 24-CHANNEL,12-BIT PTC7/ADP23 ADP15-ADP8 ANALOG-TO-DIGITAL PTC6/ADP22 VREFH CONVERTER (ADC) ADP23-ADP16 PTC5/ADP21 V VREFL T C PTC4/ADP20 DDA OR PTC3/ADP19 VSSA P PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 USER FLASH TPM1CH5 - PTD7/PID7/TPM1CH5 MC9S0DZ60 = 60K 6-CHANNEL TIMER/PWM TPM1CH0 6 MC9S0DZ48 = 48K MODULE (TPM1) TPM1CLK PTD6/PID6/TPM1CH4 MC9S0DZ32 = 32K PTD5/PID5/TPM1CH3 MC9S0DZ16 = 16K T D PTD4/PID4/TPM1CH2 TPM2CH1, OR PTD3/PID3/TPM1CH1 2-CHANNEL TIMER/PWM TPM2CH0 P PTD2/PID2/TPM1CH0 MODULE (TPM2) TPM2CLK PTD1/PID1/TPM2CH1 USER EEPROM PTD0/PID0/TPM2CH0 MC9S0DZ60 = 2K CONTROLLER AREA RxCAN PTE7/RxD2/RXCAN NETWORK (MSCAN) TxCAN PTE6/TxD2/TXCAN MISO PTE5/SDA/MISO MCU9SS0EDRZ R60A M= 4K INTSEERRFIAALC EP EMROIPDHUELREA (SLPI) SMPOSSCIK ORT E PPTTEE34//SSPCSL/CMKOSI SS P PTE2/SS RxD1 PTE1/RxD1 DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1 PTE0/TxD1 INTERFACE (SCI1) PTF7 ACMP2O ANALOG COMPARATOR PTF6/ACMP2O REAL-TIME COUNTER (RTC) (ACMP2) ACMP2- PTF5/ACMP2- ACMP2+ VVDDDD VOLTAGE IIC MODULE (IIC) SSCDLA PORT F PPPTTTFFF342///TATPPCMMM21PCC2LL+KK//SSDCAL RxD2 VSS REGULATOR PTF1/RxD2 V SERIAL COMMUNICATIONS TxD2 SS PTF0/TxD2 INTERFACE (SCI2) PTG5 MULTI-PURPOSE PTG4 CLOCK GENERATOR G PTG3 (MCG) T R PTG2 XTAL PO PTG1/XTAL OSCILLATOR (XOSC) EXTAL PTG0/EXTAL - V /V internally connected to V /V in 48-pin and 32-pin packages - Pin not connected in 48-pin and 32-pin packages REFH REFL DDA SSA - V and V pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package DD SS Figure13-1. MC9S08DZ60 Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 274 Freescale Semiconductor

Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 13.1.2 Block Diagrams ThissectionincludesblockdiagramsshowingSPIsystemconnections,theinternalorganizationoftheSPI module, and the SPI clock dividers that control the master mode bit rate. 13.1.2.1 SPI System Block Diagram Figure13-2 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master deviceinitiatesallSPIdatatransfers.Duringatransfer,themastershiftsdataout(ontheMOSIpin)tothe slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively exchangesthedatathatwasintheSPIshiftregistersofthetwoSPIsystems.TheSPSCKsignalisaclock output from the master and an input to the slave. The slave device must be selected by a low level on the slaveselectinput(SSpin).Inthissystem,themasterdevicehasconfigureditsSSpinasanoptionalslave select output. MASTER SLAVE MOSI MOSI SPI SHIFTER SPI SHIFTER 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MISO MISO SPSCK SPSCK CLOCK GENERATOR SS SS Figure13-2. SPI System Connections MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 275

Chapter 13 Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure13-2showsasystemwheredataisexchangedbetweentwoMCUs,manypracticalsystemsinvolve simplerconnectionswheredataisunidirectionallytransferredfromthemasterMCUtoaslaveorfroma slave to the master MCU. 13.1.2.2 SPI Module Block Diagram Figure13-3isablockdiagramoftheSPImodule.ThecentralelementoftheSPIistheSPIshiftregister. Data is written to the double-buffered transmitter (write to SPID) and gets transferred to the SPI shift register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from SPID). Pin multiplexing logic controls connections between MCU pins and the SPI module. WhentheSPIisconfiguredasamaster,theclockoutputisroutedtotheSPSCKpin,theshifteroutputis routed to MOSI, and the shifter input is routed from the MISO pin. When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin. IntheexternalSPIsystem,simplyconnectallSPSCKpinstoeachother,allMISOpinstogether,andall MOSI pins together. Peripheral devices often use slightly different names for these pins. MC9S08DZ60 Series Data Sheet, Rev. 4 276 Freescale Semiconductor

Chapter 13 Serial Peripheral Interface (S08SPIV3) PIN CONTROL M MOSI SPE S (MOMI) Tx BUFFER (WRITE SPID) ENABLE SPI SYSTEM M MISO SHIFT SPI SHIFT REGISTER SHIFT S (SISO) OUT IN SPC0 Rx BUFFER (READ SPID) BIDIROE SHIFT SHIFT Rx BUFFER Tx BUFFER LSBFE DIRECTION CLOCK FULL EMPTY MASTER CLOCK M BUS RATE SPIBR CLOCK SPSCK CLOCK CLOCK GENERATOR LOGIC SLAVE CLOCK S MASTER/SLAVE MASTER/ MSTR MODE SELECT SLAVE MODFEN SSOE MODE FAULT SS DETECTION SPRF SPTEF SPTIE SPI INTERRUPT MODF REQUEST SPIE Figure13-3. SPI Module Block Diagram 13.1.3 SPI Baud Rate Generation As shown inFigure13-4, the clock source for the SPI baud rate generator is the bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal SPI master mode bit-rate clock. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 277

Chapter 13 Serial Peripheral Interface (S08SPIV3) PRESCALER CLOCK RATE DIVIDER DIVIDE BY DIVIDE BY MASTER BUS CLOCK SPI 1, 2, 3, 4, 5, 6, 7, or 8 2, 4, 8, 16, 32, 64, 128, or 256 BIT RATE SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 Figure13-4. SPI Baud Rate Generation 13.2 External Signal Description TheSPIoptionallysharesfourportpins.ThefunctionofthesepinsdependsonthesettingsofSPIcontrol bits.WhentheSPIisdisabled(SPE=0),thesefourpinsreverttobeinggeneral-purposeportI/Opinsthat are not controlled by the SPI. 13.2.1 SPSCK — SPI Serial Clock WhentheSPIisenabledasaslave,thispinistheserialclockinput.WhentheSPIisenabledasamaster, this pin is the serial clock output. 13.2.2 MOSI — Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0=0, this pin is the serial data input.IfSPC0=1toselectsingle-wirebidirectionalmode,andmastermodeisselected,thispinbecomes thebidirectionaldataI/Opin(MOMI).Also,thebidirectionalmodeoutputenablebitdetermineswhether the pin acts as an input (BIDIROE=0) or an output (BIDIROE=1). If SPC0=1 and slave mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 13.2.3 MISO — Master Data In, Slave Data Out When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data input. When the SPI is enabled as a slave and SPC0=0, this pin is the serial data output.IfSPC0=1toselectsingle-wirebidirectionalmode,andslavemodeisselected,thispinbecomes thebidirectionaldataI/Opin(SISO)andthebidirectionalmodeoutputenablebitdetermineswhetherthe pinactsasaninput(BIDIROE=0)oranoutput(BIDIROE=1).IfSPC0=1andmastermodeisselected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 13.2.4 SS — Slave Select WhentheSPIisenabledasaslave,thispinisthelow-trueslaveselectinput.WhentheSPIisenabledas amasterandmodefaultenableisoff(MODFEN=0),thispinisnotusedbytheSPIandrevertstobeing a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN=1, the slave select outputenablebitdetermineswhetherthispinactsasthemodefaultinput(SSOE=0)orastheslaveselect output (SSOE=1). MC9S08DZ60 Series Data Sheet, Rev. 4 278 Freescale Semiconductor

Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.3 Modes of Operation 13.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. Duringeitherstop1orstop2mode,theSPImodulewillbefullypowereddown.Uponwake-upfromstop1 orstop2mode,theSPImodulewillbeintheresetstate.Duringstop3mode,clockstotheSPImoduleare halted. No registers are affected. If stop3 is exited with a reset, the SPI will be put into its reset state. If stop3 is exited with an interrupt, the SPI continues from the state it was in when stop3 was entered. 13.4 Register Definition The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for transmit/receive data. Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignmentsforallSPIregisters.Thissectionreferstoregistersandcontrolbitsonlybytheirnames,and a Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.4.1 SPI Control Register 1 (SPIC1) This read/write register includes the SPI enable control, interrupt enables, and configuration options. 7 6 5 4 3 2 1 0 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W Reset 0 0 0 0 0 1 0 0 Figure13-5. SPI Control Register 1 (SPIC1) Table13-1. SPIC1 Field Descriptions Field Description 7 SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF) SPIE and mode fault (MODF) events. 0 Interrupts from SPRF and MODF inhibited (use polling) 1 When SPRF or MODF is 1, request a hardware interrupt 6 SPISystemEnable—DisablingtheSPIhaltsanytransferthatisinprogress,clearsdatabuffers,andinitializes SPE internal state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty. 0 SPI system inactive 1 SPI system enabled 5 SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). SPTIE 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 279

Chapter 13 Serial Peripheral Interface (S08SPIV3) Table13-1. SPIC1 Field Descriptions (continued) Field Description 4 Master/Slave Mode Select MSTR 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 ClockPolarity—ThisbiteffectivelyplacesaninverterinserieswiththeclocksignalfromamasterSPIortoa CPOL slave SPI device. Refer toSection13.5.1, “SPI Clock Formats” for more details. 0 Active-high SPI clock (idles low) 1 Active-low SPI clock (idles high) 2 Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral CPHA devices. Refer toSection13.5.1, “SPI Clock Formats” for more details. 0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer 1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer 1 Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in SSOE SPCR2andthemaster/slave(MSTR)controlbittodeterminethefunctionoftheSSpinasshowninTable13-2. 0 LSB First (Shifter Direction) LSBFE 0 SPI serial data transfers start with most significant bit 1 SPI serial data transfers start with least significant bit Table13-2.SS Pin Function MODFEN SSOE Master Mode Slave Mode 0 0 General-purpose I/O (not SPI) Slave select input 0 1 General-purpose I/O (not SPI) Slave select input 1 0 SS input for mode fault Slave select input 1 1 AutomaticSS output Slave select input NOTE EnsurethattheSPIshouldnotbedisabled(SPE=0)atthesametimeasabitchangetotheCPHAbit.These changes should be performed as separate operations or unexpected behavior may occur. 13.4.2 SPI Control Register 2 (SPIC2) This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not implemented and always read 0. 7 6 5 4 3 2 1 0 R 0 0 0 0 MODFEN BIDIROE SPISWAI SPC0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure13-6. SPI Control Register 2 (SPIC2) MC9S08DZ60 Series Data Sheet, Rev. 4 280 Freescale Semiconductor

Chapter 13 Serial Peripheral Interface (S08SPIV3) Table13-3. SPIC2 Register Field Descriptions Field Description 4 MasterMode-FaultFunctionEnable—WhentheSPIisconfiguredforslavemode,thisbithasnomeaningor MODFEN effect. (TheSS pin is the slave select input.) In master mode, this bit determines how theSS pin is used (refer toTable13-2 for more details). 0 Mode fault function disabled, masterSS pin reverts to general-purpose I/O not controlled by SPI 1 Mode fault function enabled, masterSS pin acts as the mode fault input or the slave select output 3 Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0)=1, BIDIROE BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO (SISO) pin, respectively, as the single SPI data I/O pin. When SPC0=0, BIDIROE has no meaning or effect. 0 Output driver disabled so SPI data I/O pin acts as an input 1 SPI I/O pin enabled as an output 1 SPI Stop in Wait Mode SPISWAI 0 SPI clocks continue to operate in wait mode 1 SPI clocks stop when the MCU enters wait mode 0 SPIPinControl0—TheSPC0bitchoosessingle-wirebidirectionalmode.IfMSTR=0(slavemode),theSPI SPC0 uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR=1 (master mode), the SPI uses the MOSI(MOMI)pinforbidirectionalSPIdatatransfers.WhenSPC0=1,BIDIROEisusedtoenableordisablethe output driver for the single bidirectional SPI I/O pin. 0 SPI uses separate pins for data input and data output 1 SPI configured for single-wire bidirectional operation 13.4.3 SPI Baud Rate Register (SPIBR) ThisregisterisusedtosettheprescalerandbitratedivisorforanSPImaster.Thisregistermaybereador written at any time. 7 6 5 4 3 2 1 0 R 0 0 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure13-7. SPI Baud Rate Register (SPIBR) Table13-4. SPIBR Register Field Descriptions Field Description 6:4 SPIBaudRatePrescaleDivisor—This3-bitfieldselectsoneofeightdivisorsfortheSPIbaudrateprescaler SPPR[2:0] asshowninTable13-5.Theinputtothisprescaleristhebusrateclock(BUSCLK).Theoutputofthisprescaler drives the input of the SPI baud rate divider (seeFigure13-4). 2:0 SPIBaudRateDivisor—This3-bitfieldselectsoneofeightdivisorsfortheSPIbaudratedividerasshownin SPR[2:0] Table13-6.TheinputtothisdividercomesfromtheSPIbaudrateprescaler(seeFigure13-4).Theoutputofthis divider is the SPI bit rate clock for master mode. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 281

Chapter 13 Serial Peripheral Interface (S08SPIV3) Table13-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table13-6. SPI Baud Rate Divisor SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 13.4.4 SPI Status Register (SPIS) Thisregisterhasthreeread-onlystatusbits.Bits6,3,2,1,and0arenotimplementedandalwaysread0. Writes have no meaning or effect. 7 6 5 4 3 2 1 0 R SPRF 0 SPTEF MODF 0 0 0 0 W Reset 0 0 1 0 0 0 0 0 = Unimplemented or Reserved Figure13-8. SPI Status Register (SPIS) MC9S08DZ60 Series Data Sheet, Rev. 4 282 Freescale Semiconductor

Chapter 13 Serial Peripheral Interface (S08SPIV3) Table13-7. SPIS Register Field Descriptions Field Description 7 SPIReadBufferFullFlag—SPRFissetatthecompletionofanSPItransfertoindicatethatreceiveddatamay SPRF bereadfromtheSPIdataregister(SPID).SPRFisclearedbyreadingSPRFwhileitisset,thenreadingtheSPI data register. 0 No data available in the receive data buffer 1 Data available in the receive data buffer 5 SPITransmitBufferEmptyFlag—Thisbitissetwhenthereisroominthetransmitdatabuffer.Itisclearedby SPTEF readingSPISwithSPTEFset,followedbywritingadatavaluetothetransmitbufferatSPID.SPISmustberead withSPTEF=1beforewritingdatatoSPIDortheSPIDwritewillbeignored.SPTEFgeneratesanSPTEFCPU interruptrequestiftheSPTIEbitintheSPIC1isalsoset.SPTEFisautomaticallysetwhenadatabytetransfers fromthetransmitbufferintothetransmitshiftregister.ForanidleSPI(nodatainthetransmitbufferortheshift register and no transfer in progress), data written to SPID is transferred to the shifter almost immediately so SPTEFissetwithintwobuscyclesallowingasecond8-bitdatavaluetobequeuedintothetransmitbuffer.After completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and SPTEF will be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter. 0 SPI transmit buffer not empty 1 SPI transmit buffer empty 4 Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes MODF low,indicatingsomeotherSPIdeviceisalsoconfiguredasamaster.TheSSpinactsasamodefaulterrorinput only when MSTR=1, MODFEN=1, and SSOE=0; otherwise, MODF will never be set. MODF is cleared by reading MODF while it is 1, then writing to SPI control register 1 (SPIC1). 0 No mode fault error 1 Mode fault error detected 13.4.5 SPI Data Register (SPID) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure13-9. SPI Data Register (SPID) Readsofthisregisterreturnthedatareadfromthereceivedatabuffer.Writestothisregisterwritedatato the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data buffer initiates an SPI transfer. Data should not be written to the transmit data buffer unless the SPI transmit buffer empty flag (SPTEF) is set, indicating there is room in the transmit buffer to queue a new transmit byte. DatamaybereadfromSPIDanytimeafterSPRFissetandbeforeanothertransferisfinished.Failureto read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 283

Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF=1) and then writingabyteofdatatotheSPIdataregister(SPID)inthemasterSPIdevice.WhentheSPIshiftregister isavailable,thisbyteofdataismovedfromthetransmitdatabuffertotheshifter,SPTEFissettoindicate thereisroominthebuffertoqueueanothertransmitcharacterifdesired,andtheSPIserialtransferstarts. DuringtheSPItransfer,dataissampled(read)ontheMISOpinatoneSPSCKedgeandshifted,changing thebitvalueontheMOSIpin,one-halfSPSCKcyclelater.AftereightSPSCKcycles,thedatathatwasin theshiftregisterofthemasterhasbeenshiftedouttheMOSIpintotheslavewhileeightbitsofdatawere shiftedintheMISOpinintothemaster’sshiftregister.Attheendofthistransfer,thereceiveddatabyteis moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read by reading SPID. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved into the shifter, SPTEF is set, and a new transfer is started. Normally, SPI data is transferred most significant bit (MSB) first. If the least significant bit first enable (LSBFE) bit is set, SPI data is shifted LSB first. When the SPI is configured as a slave, its SS pin must be driven low before a transfer starts and SS must stay low throughout the transfer. If a clock format where CPHA=0 is selected, SS must be driven to a logic1betweensuccessivetransfers.IfCPHA=1,SSmayremainlowbetweensuccessivetransfers.See Section13.5.1, “SPI Clock Formats” for more details. Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffer, and a previously received character can be in the receive data buffer while a new character is being shifted in. The SPTEF flag indicates when the transmit buffer has room for a new character. The SPRF flag indicates when a received character is available in the receive data buffer. The received character must be read out of the receive buffer (read SPID) before the next transfer is finished or a receive overrun error results. In the case of a receive overrun, the new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. There is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 13.5.1 SPI Clock Formats To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses between two different clock phase relationships between the clock and data. Figure13-10 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are shownforreferencewithbit1startingatthefirstSPSCKedgeandbit8endingone-halfSPSCKcycleafter the sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending onthesettinginLSBFE.BothvariationsofSPSCKpolarityareshown,butonlyoneofthesewaveforms appliesforaspecifictransfer,dependingonthevalueinCPOL.TheSAMPLEINwaveformappliestothe MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output MC9S08DZ60 Series Data Sheet, Rev. 4 284 Freescale Semiconductor

Chapter 13 Serial Peripheral Interface (S08SPIV3) pin from a master and the MISOwaveform applies to the MISO output from a slave. The SS OUT waveformappliestotheslaveselectoutputfromamaster(providedMODFENandSSOE=1).Themaster SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SSIN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL=0) SPSCK (CPOL=1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 BIT 6 ... BIT 2 BIT 1 BIT 0 LSB FIRST BIT 0 BIT 1 ... BIT 5 BIT 6 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure13-10. SPI Clock Formats (CPHA = 1) WhenCPHA=1,theslavebeginstodriveitsMISOoutputwhenSSgoestoactivelow,butthedataisnot defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the thirdSPSCKedge,theSPIshiftershiftsonebitpositionwhichshiftsinthebitvaluethatwasjustsampled, andshiftstheseconddatabitvalueouttheotherendoftheshiftertotheMOSIandMISOoutputsofthe master and slave, respectively. When CHPA=1, the slave’s SS input is not required to go to its inactive high level between transfers. Figure13-11 shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are shownforreferencewithbit1startingastheslaveisselected(SSINgoeslow),andbit8endsatthelast SPSCKedge.TheMSBfirstandLSBfirstlinesshowtheorderofSPIdatabitsdependingonthesetting MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 285

Chapter 13 Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specifictransfer,dependingonthevalueinCPOL.TheSAMPLEINwaveformappliestotheMOSIinput of a slave or the MISO input of a master. The MOSIwaveform applies to the MOSI output pin from a masterandtheMISOwaveformappliestotheMISOoutputfromaslave.TheSSOUTwaveformapplies totheslaveselectoutputfromamaster(providedMODFENandSSOE=1).Themaster SSoutputgoes toactivelowatthestartofthefirstbittimeofthetransferandgoesbackhighone-halfSPSCKcycleafter the end of the eighth bit time of the transfer. The SSIN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL=0) SPSCK (CPOL=1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 BIT 6 ... BIT 2 BIT 1 BIT 0 LSB FIRST BIT 0 BIT 1 ... BIT 5 BIT 6 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure13-11. SPI Clock Formats (CPHA = 0) When CPHA=0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB dependingonLSBFE)whenSSgoestoactivelow.ThefirstSPSCKedgecausesboththemasterandthe slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK edge,theSPIshiftershiftsonebitpositionwhichshiftsinthebitvaluethatwasjustsampledandshiftsthe second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CPHA=0, the slave’s SS input must go to its inactive high level between transfers. MC9S08DZ60 Series Data Sheet, Rev. 4 286 Freescale Semiconductor

Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.5.2 SPI Interrupts Therearethreeflagbits,twointerruptmaskbits,andoneinterruptvectorassociatedwiththeSPIsystem. TheSPIinterruptenablemask(SPIE)enablesinterruptsfromtheSPIreceiverfullflag(SPRF)andmode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmitbufferemptyflag(SPTEF).Whenoneoftheflagbitsisset,andtheassociatedinterruptmaskbit isset,ahardwareinterruptrequestissenttotheCPU.Iftheinterruptmaskbitsarecleared,softwarecan poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should checktheflagbitstodeterminewhateventcausedtheinterrupt.Theserviceroutineshouldalsoclearthe flag bit(s) before returning from the ISR (usually near the beginning of the ISR). 13.5.3 Mode Fault Detection A mode fault occurs and the mode fault flag (MODF) becomes set when a master SPI device detects an error on theSS pin (provided theSS pin is configured as the mode fault input signal). TheSS pin is configured to be the mode fault input signal when MSTR=1, mode fault enable is set (MODFEN=1), and slave select output enable is clear (SSOE=0). ThemodefaultdetectionfeaturecanbeusedinasystemwheremorethanoneSPIdevicemightbecome amasteratthesametime.Theerrorisdetectedwhenamaster’sSSpinislow,indicatingthatsomeother SPIdeviceistryingtoaddressthismasterasifitwereaslave.Thiscouldindicateaharmfuloutputdriver conflict,sothemodefaultlogicisdesignedtodisableallSPIoutputdriverswhensuchanerrorisdetected. When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are disabled. MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIC1). User software should verify the error condition has been corrected before changing the SPI back to master mode. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 287

Chapter 13 Serial Peripheral Interface (S08SPIV3) MC9S08DZ60 Series Data Sheet, Rev. 4 288 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction All MCUs in the MC9S08DZ60 Series include SCI1 and SCI2. NOTE • MC9S08DZ60Seriesdevicesoperateatahighervoltagerange(2.7Vto 5.5V)anddonotincludestop1mode.Pleaseignorereferencestostop1. • TheRxD1pindoesnotcontainaclampdiodetoV andshouldnotbe DD driven above V . The voltage measured on the internally pulled up DD RxD1 pin may be as low as V – 0.7 V. The internal gates connected DD to this pin are pulled all the way to V . DD 14.1.1 SCI2 Configuration Information The SCI2 module pins, TxD2 and RxD2 can be repositioned under software control using SCI2PS in SOPT1asshowninTable 14-1.SCI2PSinSOPT1selectswhichgeneral-purposeI/Oportsareassociated with SCI2 operation. Table14-1. SCI2 Position Options SCI2PS in SOPT1 Port Pin for TxD2 Port Pin for RxD2 0 (default) PTF0 PTF1 1 PTE6 PTE7 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 289

Chapter14 Serial Communications Interface (S08SCIV4) HCS08 CORE PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 CPU ANALOG COMPARATOR ACMP1O ORT A PPTTAA34//PPIIAA34//AADDPP34/ACMP1O BKGD/MS (ACMP1) ACMP1- P PTA2/PIA2/ADP2/ACMP1- BDC BKP ACMP1+ PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK HCS08 SYSTEM CONTROL PTB7/PIB7/ADP15 RESET RESETS AND INTERRUPTS PTB6/PIB6/ADP14 MODES OF OPERATION PTB5/PIB5/ADP13 POWER MANAGEMENT T B PTB4/PIB4/ADP12 OR PTB3/PIB3/ADP11 8 P PTB2/PIB2/ADP10 COP LVD Q PTB1/PIB1/ADP9 R INT IRQ I ADP7-ADP0 PTB0/PIB0/ADP8 24-CHANNEL,12-BIT PTC7/ADP23 ADP15-ADP8 ANALOG-TO-DIGITAL PTC6/ADP22 VREFH CONVERTER (ADC) ADP23-ADP16 PTC5/ADP21 V VREFL T C PTC4/ADP20 DDA OR PTC3/ADP19 VSSA P PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 USER FLASH TPM1CH5 - PTD7/PID7/TPM1CH5 MC9S0DZ60 = 60K 6-CHANNEL TIMER/PWM TPM1CH0 6 MC9S0DZ48 = 48K MODULE (TPM1) TPM1CLK PTD6/PID6/TPM1CH4 MC9S0DZ32 = 32K PTD5/PID5/TPM1CH3 MC9S0DZ16 = 16K T D PTD4/PID4/TPM1CH2 TPM2CH1, OR PTD3/PID3/TPM1CH1 2-CHANNEL TIMER/PWM TPM2CH0 P PTD2/PID2/TPM1CH0 MODULE (TPM2) TPM2CLK PTD1/PID1/TPM2CH1 USER EEPROM PTD0/PID0/TPM2CH0 MC9S0DZ60 = 2K CONTROLLER AREA RxCAN PTE7/RxD2/RXCAN NETWORK (MSCAN) TxCAN PTE6/TxD2/TXCAN MISO PTE5/SDA/MISO MCU9SS0EDRZ R60A M= 4K INTSEERRFIAALC EP EMROIPDHUELREA (SLPI) SMPOSSCIK ORT E PPTTEE34//SSPCSL/CMKOSI SS P PTE2/SS RxD1 PTE1/RxD1 DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1 PTE0/TxD1 INTERFACE (SCI1) PTF7 ACMP2O ANALOG COMPARATOR PTF6/ACMP2O REAL-TIME COUNTER (RTC) (ACMP2) ACMP2- PTF5/ACMP2- ACMP2+ VVDDDD VOLTAGE IIC MODULE (IIC) SSCDLA PORT F PPPTTTFFF342///TATPPCMMM21PCC2LL+KK//SSDCAL RxD2 VSS REGULATOR PTF1/RxD2 V SERIAL COMMUNICATIONS TxD2 SS PTF0/TxD2 INTERFACE (SCI2) PTG5 MULTI-PURPOSE PTG4 CLOCK GENERATOR G PTG3 (MCG) T R PTG2 XTAL PO PTG1/XTAL OSCILLATOR (XOSC) EXTAL PTG0/EXTAL - V /V internally connected to V /V in 48-pin and 32-pin packages - Pin not connected in 48-pin and 32-pin packages REFH REFL DDA SSA - V and V pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package DD SS Figure14-1. MC9S08DZ60 Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 290 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) 14.1.2 Features Features of SCI module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Interrupt-driven or polled operation: — Transmit data register empty and transmission complete — Receive data register full — Receive overrun, parity error, framing error, and noise error — Idle receiver detect — Active edge on receive pin — Break detect supporting LIN • Hardware parity generation and checking • Programmable 8-bit or 9-bit character length • Receiver wakeup by idle-line or address-mark • Optional 13-bit break character generation / 11-bit break character detection • Selectable transmitter output polarity 14.1.3 Modes of Operation SeeSection14.3, “Functional Description,” For details concerning SCI operation in these modes: • 8- and 9-bit data modes • Stop mode operation • Loop mode • Single-wire mode MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 291

Chapter 14 Serial Communications Interface (S08SCIV4) 14.1.4 Block Diagram Figure14-2 shows the transmitter portion of the SCI. INTERNAL BUS (WRITE-ONLY) LOOPS SCID – Tx BUFFER RSRC LOOP TO RECEIVE 11-BIT TRANSMIT SHIFT REGISTER CONTROL DATA IN M P RT O A T T S S TO TxD PIN 1× BAUD H 8 7 6 5 4 3 2 1 0 L RATE CLOCK B SHIFT DIRECTION S L TXINV D s) PE PTA8RITY D FROM SCIx SHIFT ENABLE REAMBLE (ALL 1 BREAK (ALL 0s) PT GENERATION OA P L SCI CONTROLS TxD TE SBK TO TxD TRANSMIT CONTROL TxD DIRECTION PIN LOGIC TXDIR BRK13 TDRE TIE Tx INTERRUPT TC REQUEST TCIE Figure14-2. SCI Transmitter Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 292 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) Figure14-3 shows the receiver portion of the SCI. INTERNAL BUS (READ-ONLY) 16× BAUD DIVIDE RATE CLOCK SCID – Rx BUFFER BY 16 FROM TRANSMITTER 11-BIT RECEIVE SHIFT REGISTER LOOPS SINGLE-WIRE M OP B ART RSRC LOOP CONTROL ST LS ST LBKDE H 8 7 6 5 4 3 2 1 0 L FROM RxD PIN s RXINV DATA RECOVERY ALL 1 MSB SHIFT DIRECTION WAKE WAKEUP RWU RWUID LOGIC ILT ACTIVE EDGE DETECT RDRF RIE IDLE ILIE Rx INTERRUPT REQUEST LBKDIF LBKDIE RXEDGIF RXEDGIE OR ORIE FE FEIE ERROR INTERRUPT REQUEST NF NEIE PE PARITY PF CHECKING PT PEIE Figure14-3. SCI Receiver Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 293

Chapter 14 Serial Communications Interface (S08SCIV4) 14.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignments for all SCI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 14.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ThispairofregisterscontrolstheprescaledivisorforSCIbaudrategeneration.Toupdatethe13-bitbaud ratesetting[SBR12:SBR0],firstwritetoSCIxBDHtobufferthehighhalfofthenewvalueandthenwrite to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written. SCIxBDLisresettoanon-zerovalue,soafterresetthebaudrategeneratorremainsdisableduntilthefirst time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1). 7 6 5 4 3 2 1 0 R 0 LBKDIE RXEDGIE SBR12 SBR11 SBR10 SBR9 SBR8 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure14-4. SCI Baud Rate Register (SCIxBDH) Table14-2. SCIxBDH Field Descriptions Field Description 7 LIN Break Detect Interrupt Enable (for LBKDIF) LBKDIE 0 Hardware interrupts from LBKDIF disabled (use polling). 1 Hardware interrupt requested when LBKDIFflag is 1. 6 RxD Input Active Edge Interrupt Enable (for RXEDGIF) RXEDGIE 0 Hardware interrupts from RXEDGIF disabled (use polling). 1 Hardware interrupt requested when RXEDGIF flag is 1. 4:0 Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the SBR[12:8] modulo divide rate for the SCI baud rate generator. When BR=0, the SCI baud rate generator is disabled to reduce supply current. When BR=1 to 8191, the SCI baud rate=BUSCLK/(16×BR). See also BR bits in Table14-3. MC9S08DZ60 Series Data Sheet, Rev. 4 294 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) 7 6 5 4 3 2 1 0 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W Reset 0 0 0 0 0 1 0 0 Figure14-5. SCI Baud Rate Register (SCIxBDL) Table14-3. SCIxBDL Field Descriptions Field Description 7:0 Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the SBR[7:0] modulo divide rate for the SCI baud rate generator. When BR=0, the SCI baud rate generator is disabled to reduce supply current. When BR=1 to 8191, the SCI baud rate=BUSCLK/(16×BR). See also BR bits in Table14-2. 14.2.2 SCI Control Register 1 (SCIxC1) This read/write register is used to control various optional features of the SCI system. 7 6 5 4 3 2 1 0 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W Reset 0 0 0 0 0 0 0 0 Figure14-6. SCI Control Register 1 (SCIxC1) Table14-4. SCIxC1 Field Descriptions Field Description 7 Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS LOOPS=1, the transmitter output is internally connected to the receiver input. 0 Normal operation — RxD and TxD use separate pins. 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by SCI. 6 SCI Stops in Wait Mode SCISWAI 0 SCIclockscontinuetoruninwaitmodesotheSCIcanbethesourceofaninterruptthatwakesuptheCPU. 1 SCI clocks freeze while CPU is in wait mode. 5 Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When RSRC LOOPS=1, the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output. 0 Provided LOOPS=1, RSRC=0 selects internal loop back mode and the SCI does not use the RxD pins. 1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input. 4 9-Bit or 8-Bit Mode Select M 0 Normal — start + 8 data bits (LSB first) + stop. 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (LSB first) + 9th data bit + stop. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 295

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-4. SCIxC1 Field Descriptions (continued) Field Description 3 Receiver Wakeup Method Select — Refer toSection14.3.3.2, “Receiver Wakeup Operation” for more WAKE information. 0 Idle-line wakeup. 1 Address-mark wakeup. 2 Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic1 bits at the end of a character ILT do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to Section14.3.3.2.1, “Idle-Line Wakeup” for more information. 0 Idle character bit count starts after start bit. 1 Idle character bit count starts after stop bit. 1 ParityEnable—Enableshardwareparitygenerationandchecking.Whenparityisenabled,themostsignificant PE bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking. 1 Parity enabled. 0 ParityType—Providedparityisenabled(PE=1),thisbitselectsevenoroddparity.Oddparitymeansthetotal PT number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity. 14.2.3 SCI Control Register 2 (SCIxC2) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R TIE TCIE RIE ILIE TE RE RWU SBK W Reset 0 0 0 0 0 0 0 0 Figure14-7. SCI Control Register 2 (SCIxC2) Table14-5. SCIxC2 Field Descriptions Field Description 7 Transmit Interrupt Enable (for TDRE) TIE 0 Hardware interrupts from TDRE disabled (use polling). 1 Hardware interrupt requested when TDRE flag is 1. 6 Transmission Complete Interrupt Enable (for TC) TCIE 0 Hardware interrupts from TC disabled (use polling). 1 Hardware interrupt requested when TC flag is 1. 5 Receiver Interrupt Enable (for RDRF) RIE 0 Hardware interrupts from RDRF disabled (use polling). 1 Hardware interrupt requested when RDRF flag is 1. 4 Idle Line Interrupt Enable (for IDLE) ILIE 0 Hardware interrupts from IDLE disabled (use polling). 1 Hardware interrupt requested when IDLE flag is 1. MC9S08DZ60 Series Data Sheet, Rev. 4 296 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-5. SCIxC2 Field Descriptions (continued) Field Description 3 Transmitter Enable TE 0 Transmitter off. 1 Transmitter on. TE must be 1 in order to use the SCI transmitter. When TE=1, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is configured for single-wire operation (LOOPS=RSRC=1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin). TEalsocanbeusedtoqueueanidlecharacterbywritingTE=0thenTE=1whileatransmissionisinprogress. Refer toSection14.3.2.1, “Send Break and Queued Idle” for more details. WhenTEiswrittento0,thetransmitterkeepscontroloftheportTxDpinuntilanydata,queuedidle,orqueued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin. 2 Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. RE If LOOPS=1 the RxD pin reverts to being a general-purpose I/O pin even if RE=1. 0 Receiver off. 1 Receiver on. 1 Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it RWU waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle linebetweenmessages(WAKE=0,idle-linewakeup),oralogic1inthemostsignificantdatabitinacharacter (WAKE=1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware condition automatically clears RWU. Refer toSection14.3.3.2, “Receiver Wakeup Operation” for more details. 0 Normal SCI receiver operation. 1 SCI receiver in standby waiting for wakeup condition. 0 SendBreak—Writinga1andthena0toSBKqueuesabreakcharacterinthetransmitdatastream.Additional SBK break characters of 10 or 11(13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK=1. Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a secondbreakcharactermaybequeuedbeforesoftwareclearsSBK.RefertoSection14.3.2.1,“SendBreakand Queued Idle” for more details. 0 Normal transmitter operation. 1 Queue break character(s) to be sent. 14.2.4 SCI Status Register 1 (SCIxS1) Thisregisterhaseightread-onlystatusflags.Writeshavenoeffect.Specialsoftwaresequences(whichdo not involve writing to this register) are used to clear these status flags. 7 6 5 4 3 2 1 0 R TDRE TC RDRF IDLE OR NF FE PF W Reset 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure14-8. SCI Status Register 1 (SCIxS1) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 297

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-6. SCIxS1 Field Descriptions Field Description 7 TransmitDataRegisterEmptyFlag—TDREissetoutofresetandwhenatransmitdatavaluetransfersfrom TDRE thetransmitdatabuffertothetransmitshifter,leavingroomforanewcharacterinthebuffer.ToclearTDRE,read SCIxS1 with TDRE=1 and then write to the SCI data register (SCIxD). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty. 6 Transmission Complete Flag — TC is set out of reset and when TDRE=1 and no data, preamble, or break TC character is being transmitted. 0 Transmitter active (sending data, a preamble, or a break). 1 Transmitter idle (transmission activity complete). TC is cleared automatically by reading SCIxS1 with TC=1 and then doing one of the following three things: • Write to the SCI data register (SCIxD) to transmit new data • Queue a preamble by changing TE from 0 to 1 • Queue a break character by writing 1 to SBK in SCIxC2 5 ReceiveDataRegisterFullFlag—RDRFbecomessetwhenacharactertransfersfromthereceiveshifterinto RDRF the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data register (SCIxD). 0 Receive data register empty. 1 Receive data register full. 4 Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of IDLE activity. When ILT=0, the receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times dependingontheMcontrolbit)neededforthereceivertodetectanidleline.WhenILT=1,thereceiverdoesn’t start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the previouscharacterdonotcounttowardthefullcharactertimeoflogichighneededforthereceivertodetectan idle line. To clear IDLE, read SCIxS1 with IDLE=1 and then read the SCI data register (SCIxD). After IDLE has been cleared,itcannotbecomesetagainuntilafteranewcharacterhasbeenreceivedandRDRFhasbeenset.IDLE will get set only once even if the receive line remains idle for an extended period. 0 No idle line detected. 1 Idle line was detected. 3 ReceiverOverrunFlag—ORissetwhenanewserialcharacterisreadytobetransferredtothereceivedata OR register (buffer), but the previously received character has not been read from SCIxD yet. In this case, the new character(andallassociatederrorinformation)islostbecausethereisnoroomtomoveitintoSCIxD.Toclear OR, read SCIxS1 with OR=1 and then read the SCI data register (SCIxD). 0 No overrun. 1 Receive overrun (new SCI data lost). 2 NoiseFlag—Theadvancedsamplingtechniqueusedinthereceivertakessevensamplesduringthestartbit NF andthreesamplesineachdatabitandthestopbit.Ifanyofthesesamplesdisagreeswiththerestofthesamples within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No noise detected. 1 Noise detected in the received character in SCIxD. MC9S08DZ60 Series Data Sheet, Rev. 4 298 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-6. SCIxS1 Field Descriptions (continued) Field Description 1 FramingErrorFlag—FEissetatthesametimeasRDRFwhenthereceiverdetectsalogic0wherethestop FE bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE=1 and then read the SCI data register (SCIxD). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error. 0 Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE=1) and the parity bit in PF the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No parity error. 1 Parity error. 14.2.5 SCI Status Register 2 (SCIxS2) This register has one read-only status flag. 7 6 5 4 3 2 1 0 R 0 RAF LBKDIF RXEDGIF RXINV RWUID BRK13 LBKDE W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure14-9. SCI Status Register 2 (SCIxS2) Table14-7. SCIxS2 Field Descriptions Field Description 7 LINBreakDetectInterruptFlag—LBKDIFissetwhentheLINbreakdetectcircuitryisenabledandaLINbreak LBKDIF character is detected. LBKDIF is cleared by writing a “1” to it. 0 No LIN break character has been detected. 1 LIN break character has been detected. 6 RxD Pin Active Edge Interrupt Flag — RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXEDGIF RXINV=1) on the RxD pin occurs. RXEDGIF is cleared by writing a “1” to it. 0 No active edge on the receive pin has occurred. 1 An active edge on the receive pin has occurred. 4 Receive Data Inversion — Setting this bit reverses the polarity of the received data input. RXINV1 0 Receive data not inverted 1 Receive data inverted 3 ReceiveWakeUpIdleDetect—RWUIDcontrolswhethertheidlecharacterthatwakesupthereceiversetsthe RWUID IDLE bit. 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. 2 BreakCharacterGenerationLength—BRK13isusedtoselectalongertransmittedbreakcharacterlength. BRK13 Detection of a framing error is not affected by the state of this bit. 0 Break character is transmitted with length of 10 bit times (11 if M = 1) 1 Break character is transmitted with length of 13 bit times (14 if M = 1) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 299

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-7. SCIxS2 Field Descriptions (continued) Field Description 1 LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 Break character is detected at length of 10 bit times (11 if M = 1). 1 Break character is detected at length of 11 bit times (12 if M = 1). 0 ReceiverActiveFlag—RAFissetwhentheSCIreceiverdetectsthebeginningofavalidstartbit,andRAFis RAF cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an SCI character is being received before instructing the MCU to go to stop mode. 0 SCI receiver idle waiting for a start bit. 1 SCI receiver active (RxD input not idle). 1 Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle. WhenusinganinternaloscillatorinaLINsystem,itisnecessarytoraisethebreakdetectionthresholdby one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data charactercanappeartobe10.26bittimeslongataslavewhichisrunning14%fasterthanthemaster.This would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. When theLBKDEbitisset,framingerrorsareinhibitedandthebreakdetectionthresholdchangesfrom10bits to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol. 14.2.6 SCI Control Register 3 (SCIxC3) 7 6 5 4 3 2 1 0 R R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure14-10. SCI Control Register 3 (SCIxC3) Table14-8. SCIxC3 Field Descriptions Field Description 7 Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M=1), R8 can be thought of as a R8 ninthreceivedatabittotheleftoftheMSBofthebuffereddataintheSCIxDregister.Whenreading9-bitdata, read R8 before reading SCIxD because reading SCIxD completes automatic flag clearing sequences which could allow R8 and SCIxD to be overwritten with new data. 6 NinthDataBitforTransmitter—WhentheSCIisconfiguredfor9-bitdata(M=1),T8maybethoughtofasa T8 ninthtransmitdatabittotheleftoftheMSBofthedataintheSCIxDregister.Whenwriting9-bitdata,theentire 9-bit value is transferred to the SCI shift register after SCIxD is written so T8 should be written (if it needs to change from its previous value) before SCIxD is written. If T8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time SCIxD is written. 5 TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation TXDIR (LOOPS=RSRC=1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. MC9S08DZ60 Series Data Sheet, Rev. 4 300 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-8. SCIxC3 Field Descriptions (continued) Field Description 4 Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output. TXINV1 0 Transmit data not inverted 1 Transmit data inverted 3 Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. ORIE 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR=1. 2 Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests. NEIE 0 NF interrupts disabled (use polling). 1 Hardware interrupt requested when NF=1. 1 Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt FEIE requests. 0 FE interrupts disabled (use polling). 1 Hardware interrupt requested when FE=1. 0 Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt PEIE requests. 0 PF interrupts disabled (use polling). 1 Hardware interrupt requested when PF=1. 1 Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle. 14.2.7 SCI Data Register (SCIxD) This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags. 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 0 0 0 0 0 Figure14-11. SCI Data Register (SCIxD) 14.3 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices,includingotherMCUs.TheSCIcomprisesabaudrategenerator,transmitter,andreceiverblock. Thetransmitterandreceiveroperateindependently,althoughtheyusethesamebaudrategenerator.During normaloperation,theMCUmonitorsthestatusoftheSCI,writesthedatatobetransmitted,andprocesses received data. The following describes each of the blocks of the SCI. 14.3.1 Baud Rate Generation As shown inFigure14-12, the clock source for the SCI baud rate generator is the bus-rate clock. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 301

Chapter 14 Serial Communications Interface (S08SCIV4) MODULO DIVIDE BY (1 THROUGH 8191) DIVIDE BY BUSCLK SBR12:SBR0 16 Tx BAUD RATE Rx SAMPLING CLOCK BAUD RATE GENERATOR (16× BAUD RATE) OFF IF [SBR12:SBR0] =0 BUSCLK BAUD RATE = [SBR12:SBR0]× 16 Figure14-12. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independentclocksources)tousethesamebaudrate.Allowedtoleranceonthisbaudfrequencydepends onthedetailsofhowthereceiversynchronizestotheleadingedgeofthestartbitandhowbitsamplingis performed. TheMCUresynchronizestobitboundariesoneveryhigh-to-lowtransition,butintheworstcase,thereare no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus frequencyisdrivenbyacrystal,theallowedbaudratemismatchisabout 4.5percentfor8-bitdataformat and about 4 percent for 9-bit data format. Although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 14.3.2 Transmitter Functional Description This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and idle characters. The transmitter block diagram is shown in Figure14-2. Thetransmitteroutput(TxD)idlestatedefaultstologichigh(TXINV=0followingreset).Thetransmitter outputisinvertedbysettingTXINV=1.ThetransmitterisenabledbysettingtheTEbitinSCIxC2.This queuesapreamblecharacterthatisonefullcharacterframeoftheidlestate.Thetransmitterthenremains idleuntildataisavailableinthetransmitdatabuffer.Programsstoredataintothetransmitdatabufferby writing to the SCI data register (SCIxD). The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the M control bit. For the remainder of this section, we will assume M=0, selectingthenormal8-bitdatamode.In8-bitdatamode,theshiftregisterholdsastartbit,eightdatabits, and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in thetransmitdataregisteristransferredtotheshiftregister(synchronizedwiththebaudrateclock)andthe transmit data register empty (TDRE) status flag is set to indicate another character may be written to the transmit data buffer at SCIxD. If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more characters to transmit. MC9S08DZ60 Series Data Sheet, Rev. 4 302 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) Writing0toTEdoesnotimmediatelyreleasethepintobeageneral-purposeI/Opin.Anytransmitactivity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 14.3.2.1 Send Break and Queued Idle The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break charactertobesentassoonastheshifterisavailable.IfSBKisstill1whenthequeuedbreakmovesinto theshifter(synchronizedtothebaudrateclock),anadditionalbreakcharacterisqueued.Ifthereceiving deviceisanotherFreescaleSemiconductorSCI,thebreakcharacterswillbereceivedas0sinalleightdata bits and a framing error (FE=1) occurs. Whenidle-linewakeupisused,afullcharactertimeofidle(logic1)isneededbetweenmessagestowake up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last characterofamessagehasmovedtothetransmitshifter,thenwrite0andthenwrite1totheTEbit.This actionqueuesanidlecharactertobesentassoonastheshifterisavailable.Aslongasthecharacterinthe shifterdoesnotfinishwhileTE=0,theSCItransmitterneveractuallyreleasescontroloftheTxDpin.If there is a possibility of the shifter finishing while TE =0, set the general-purpose I/O controls so the pin thatissharedwithTxDisanoutputdrivingalogic1.ThisensuresthattheTxDlinewilllooklikeanormal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE. The length of the break character is affected by the BRK13 and M bits as shown below. Table14-9. Break Character Length BRK13 M Break Character Length 0 0 10 bit times 0 1 11 bit times 1 0 13 bit times 1 1 14 bit times 14.3.3 Receiver Functional Description In this section, the receiver block diagram (Figure14-3) is used as a guide for the overall receiver functionaldescription.Next,thedatasamplingtechniqueusedtoreconstructreceiverdataisdescribedin more detail. Finally, two variations of the receiver wakeup function are explained. The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in SCIxC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bitoflogic1.Forinformationabout9-bitdatamode,refertoSection14.3.5.1,“8-and9-BitDataModes.” For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode. Afterreceivingthestopbitintothereceiveshifter,andprovidedthereceivedataregisterisnotalreadyfull, thedatacharacteristransferredtothereceivedataregisterandthereceivedataregisterfull(RDRF)status MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 303

Chapter 14 Serial Communications Interface (S08SCIV4) flagisset.IfRDRFwasalreadysetindicatingthereceivedataregister(buffer)wasalreadyfull,theoverrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program hasonefullcharactertimeafterRDRFissetbeforethedatainthereceivedatabuffermustbereadtoavoid a receiver overrun. Whenaprogramdetectsthatthereceivedataregisterisfull(RDRF=1),itgetsthedatafromthereceive data register by reading SCIxD. The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s program that handles receive data. Refer to Section14.3.4, “Interrupts and Status Flags” for more details about flag clearing. 14.3.3.1 Data Sampling Technique TheSCIreceiverusesa16×baudrateclockforsampling.Thereceiverstartsbytakinglogiclevelsamples at 16 times the baud rate to search for a falling edge on the RxD serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock is used to dividethebittimeinto16segmentslabeledRT1throughRT16.Whenafallingedgeislocated,threemore samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determinethelogiclevelforthatbit.Thelogiclevelisinterpretedtobethatofthemajorityofthesamples takenduringthebittime.Inthecaseofthestartbit,thebitisassumedtobe0ifatleasttwoofthesamples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive data buffer. Thefallingedgedetectionlogiccontinuouslylooksforfallingedges,andifanedgeisdetected,thesample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. Inthecaseofaframingerror,providedthereceivedcharacterwasnotabreakcharacter,thesamplinglogic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. Inthecaseofaframingerror,thereceiverisinhibitedfromreceivinganynewcharactersuntiltheframing error flag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set. 14.3.3.2 Receiver Wakeup Operation Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU bit is set, thestatusflagsassociatedwiththereceiver(withtheexceptionoftheidlebit,IDLE,whenRWUIDbitis set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant MC9S08DZ60 Series Data Sheet, Rev. 4 304 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. 14.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automaticallywhenthereceiverdetectsafullcharactertimeoftheidle-linelevel.TheMcontrolbitselects 8-bitor9-bitdatamodethatdetermineshowmanybittimesofidleareneededtoconstituteafullcharacter time (10 or 11 bit times because of the start and stop bits). WhenRWUisoneandRWUIDiszero,theidleconditionthatwakesupthereceiverdoesnotsettheIDLE flag. The receiver wakes up and waits for the first data character of the next message which will set the RDRF flag and generate an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE flag and generates an interrupt if enabled, regardless of whether RWU is zero or one. The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward thefullcharactertimeofidle.WhenILT=1,theidlebitcounterdoesnotstartuntilafterastopbittime, so the idle detection is not affected by the data in the last character of the previous message. 14.3.3.2.2 Address-Mark Wakeup When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared automaticallywhenthereceiverdetectsalogic1inthemostsignificantbitofareceivedcharacter(eighth bit in M = 0 mode and ninth bit in M = 1 mode). Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved foruseinaddressframes.Thelogic1MSBofanaddressframeclearstheRWUbitbeforethestopbitis received and sets the RDRF flag.In this case the character with the MSB set is received even though the receiver was sleeping during most of this character time. 14.3.4 Interrupts and Status Flags TheSCIsystemhasthreeseparateinterruptvectorstoreducetheamountofsoftwareneededtoisolatethe cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events. AnotherinterruptvectorisassociatedwiththereceiverforRDRF,IDLE,RXEDGIFandLBKDIFevents, andathirdvectorisusedforOR,NF,FE,andPFerrorconditions.Eachoftheseteninterruptsourcescan be separately masked by local interrupt enable masks. The flags can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. TheSCItransmitterhastwostatusflagsthatoptionallycangeneratehardwareinterruptrequests.Transmit data register empty (TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be requested whenever TDRE=1. Transmit complete (TC) indicates that the transmitter is finished transmittingalldata,preamble,andbreakcharactersandisidlewithTxDattheinactivelevel.Thisflagis often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC=1. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 305

Chapter 14 Serial Communications Interface (S08SCIV4) Insteadofhardwareinterrupts,softwarepollingmaybeusedtomonitortheTDREandTCstatusflagsif the corresponding TIE or TCIE local interrupt masks are 0s. Whenaprogramdetectsthatthereceivedataregisterisfull(RDRF=1),itgetsthedatafromthereceive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF=1 and then reading SCIxD. When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardwareinterruptsareused,SCIxS1mustbereadintheinterruptserviceroutine(ISR).Normally,thisis done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied. TheIDLEstatusflagincludeslogicthatpreventsitfromgettingsetrepeatedlywhentheRxDlineremains idleforanextendedperiodoftime.IDLEisclearedbyreadingSCIxS1whileIDLE=1andthenreading SCIxD.AfterIDLEhasbeencleared,itcannotbecomesetagainuntilthereceiverhasreceivedatleastone new character and has set RDRF. IftheassociatederrorwasdetectedinthereceivedcharacterthatcausedRDRFtobeset,theerrorflags— noiseflag(NF),framingerror(FE),andparityerrorflag(PF)—getsetatthesametimeasRDRF.These flags are not set in overrun cases. If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receivedatabuffer,theoverrun(OR)flaggetssetinsteadthedataalongwithanyassociatedNF,FE,orPF condition is lost. At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The RXEDGIFflagisclearedbywritinga“1”toit.Thisfunctiondoesdependonthereceiverbeingenabled (RE = 1). 14.3.5 Additional SCI Functions The following sections describe additional SCI functions. 14.3.5.1 8- and 9-Bit Data Modes The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the M control bit in SCIxC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data register. For the transmit data buffer, this bit is stored in T8 in SCIxC3. For the receiver, the ninth bit is held in R8 in SCIxC3. For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCIxD. Ifthebitvaluetobetransmittedastheninthbitofanewcharacteristhesameasforthepreviouscharacter, it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data is transferred from SCIxD to the shifter. 9-bitdatamodetypicallyisusedinconjunctionwithparitytoalloweightbitsofdataplustheparityinthe ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker. MC9S08DZ60 Series Data Sheet, Rev. 4 306 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) 14.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. Instop1andstop2modes,allSCIregisterdataislostandmustbere-initializeduponrecoveryfromthese two stop modes. No SCI module registers are affected in stop3 mode. Thereceiveinputactiveedgedetectcircuitisstillactiveinstop3mode,butnotinstop2..Anactiveedge on the receive input brings the CPU out of stop3 mode if the interrupt is not masked (RXEDGIE = 1). Note, because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3mode).Softwareshouldensurestopmodeisnotenteredwhilethereisacharacterbeingtransmitted out of or received into the SCI module. 14.3.5.3 Loop Mode When LOOPS=1, the RSRC bit in the same register chooses between loop mode (RSRC=0) or single-wire mode (RSRC=1). Loop mode is sometimes used to check software, independent of connectionsintheexternalsystem,tohelpisolatesystemproblems.Inthismode,thetransmitteroutputis internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. 14.3.5.4 Single-Wire Operation When LOOPS=1, the RSRC bit in the same register chooses between loop mode (RSRC=0) or single-wire mode (RSRC=1). Single-wire mode is used to implement a half-duplex serial connection. ThereceiverisinternallyconnectedtothetransmitteroutputandtotheTxDpin.TheRxDpinisnotused and reverts to a general-purpose port I/O pin. Insingle-wiremode,theTXDIRbitinSCIxC3controlsthedirectionofserialdataontheTxDpin.When TXDIR=0, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected fromtheTxDpinsoanexternaldevicecansendserialdatatothereceiver.WhenTXDIR=1,theTxDpin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 307

Chapter 14 Serial Communications Interface (S08SCIV4) MC9S08DZ60 Series Data Sheet, Rev. 4 308 Freescale Semiconductor

Chapter 15 Real-Time Counter (S08RTCV1) 15.1 Introduction The RTC module consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, three clock sources, and one programmable periodic interrupt. This modulecanbeusedfortime-of-day,calendaroranytaskschedulingfunctions.Itcanalsoserveasacyclic wake up from low power modes without the need of external components. All devices in the MC9S08DZ60 Series feature the RTC. 15.1.1 RTC Clock Signal Names ReferencestoERCLKandIRCLKinthischaptercorrespondtosignalsMCGERCLKandMCGIRCLK, respectively. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 309

Chapter15 Real-Time Counter (S08RTCV1) HCS08 CORE PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 CPU ANALOG COMPARATOR ACMP1O ORT A PPTTAA34//PPIIAA34//AADDPP34/ACMP1O BKGD/MS (ACMP1) ACMP1- P PTA2/PIA2/ADP2/ACMP1- BDC BKP ACMP1+ PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK HCS08 SYSTEM CONTROL PTB7/PIB7/ADP15 RESET RESETS AND INTERRUPTS PTB6/PIB6/ADP14 MODES OF OPERATION PTB5/PIB5/ADP13 POWER MANAGEMENT T B PTB4/PIB4/ADP12 OR PTB3/PIB3/ADP11 8 P PTB2/PIB2/ADP10 COP LVD Q PTB1/PIB1/ADP9 R INT IRQ I ADP7-ADP0 PTB0/PIB0/ADP8 24-CHANNEL,12-BIT PTC7/ADP23 ADP15-ADP8 ANALOG-TO-DIGITAL PTC6/ADP22 VREFH CONVERTER (ADC) ADP23-ADP16 PTC5/ADP21 V VREFL T C PTC4/ADP20 DDA OR PTC3/ADP19 VSSA P PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 USER FLASH TPM1CH5 - PTD7/PID7/TPM1CH5 MC9S0DZ60 = 60K 6-CHANNEL TIMER/PWM TPM1CH0 6 MC9S0DZ48 = 48K MODULE (TPM1) TPM1CLK PTD6/PID6/TPM1CH4 MC9S0DZ32 = 32K PTD5/PID5/TPM1CH3 MC9S0DZ16 = 16K T D PTD4/PID4/TPM1CH2 TPM2CH1, OR PTD3/PID3/TPM1CH1 2-CHANNEL TIMER/PWM TPM2CH0 P PTD2/PID2/TPM1CH0 MODULE (TPM2) TPM2CLK PTD1/PID1/TPM2CH1 USER EEPROM PTD0/PID0/TPM2CH0 MC9S0DZ60 = 2K CONTROLLER AREA RxCAN PTE7/RxD2/RXCAN NETWORK (MSCAN) TxCAN PTE6/TxD2/TXCAN MISO PTE5/SDA/MISO MCU9SS0EDRZ R60A M= 4K INTSEERRFIAALC EP EMROIPDHUELREA (SLPI) SMPOSSCIK ORT E PPTTEE34//SSPCSL/CMKOSI SS P PTE2/SS RxD1 PTE1/RxD1 DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1 PTE0/TxD1 INTERFACE (SCI1) PTF7 ACMP2O ANALOG COMPARATOR PTF6/ACMP2O REAL-TIME COUNTER (RTC) (ACMP2) ACMP2- PTF5/ACMP2- ACMP2+ VVDDDD VOLTAGE IIC MODULE (IIC) SSCDLA PORT F PPPTTTFFF342///TATPPCMMM21PCC2LL+KK//SSDCAL RxD2 VSS REGULATOR PTF1/RxD2 V SERIAL COMMUNICATIONS TxD2 SS PTF0/TxD2 INTERFACE (SCI2) PTG5 MULTI-PURPOSE PTG4 CLOCK GENERATOR G PTG3 (MCG) T R PTG2 XTAL PO PTG1/XTAL OSCILLATOR (XOSC) EXTAL PTG0/EXTAL - V /V internally connected to V /V in 48-pin and 32-pin packages - Pin not connected in 48-pin and 32-pin packages REFH REFL DDA SSA - V and V pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package DD SS Figure15-1. MC9S08DZ60 Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 310 Freescale Semiconductor

Chapter 15 Real-Time Counter (S08RTCV1) 15.1.2 Features Features of the RTC module include: • 8-bit up-counter — 8-bit modulo match limit — Software controllable periodic interrupt on match • Three software selectable clock sources for input to prescaler with selectable binary-based and decimal-based divider values — 1-kHz internal low-power oscillator (LPO) — External clock (ERCLK) — 32-kHz internal clock (IRCLK) 15.1.3 Modes of Operation This section defines the operation in stop, wait and background debug modes. 15.1.3.1 Wait Mode TheRTCcontinuestoruninwaitmodeifenabledbeforeexecutingtheappropriateinstruction.Therefore, the RTC can bring the MCU out of wait mode if the real-time interrupt is enabled. For lowest possible current consumption, the RTC should be stopped by software if not needed as an interrupt source during wait mode. 15.1.3.2 Stop Modes The RTC continues to run in stop2 or stop3 mode if the RTC is enabled before executing the STOP instruction.Therefore,theRTCcanbringtheMCUoutofstopmodeswithnoexternalcomponents,ifthe real-time interrupt is enabled. The LPO clock can be used in stop2 and stop3 modes. ERCLK and IRCLK clocks are only available in stop3 mode. Power consumption is lower when all clock sources are disabled, but in that case, the real-time interrupt cannot wake up the MCU from stop modes. 15.1.3.3 Active Background Mode TheRTCsuspendsallcountingduringactivebackgroundmodeuntilthemicrocontrollerreturnstonormal useroperatingmode.CountingresumesfromthesuspendedvalueaslongastheRTCMODregisterisnot written and the RTCPS and RTCLKS bits are not altered. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 311

Chapter 15 Real-Time Counter (S08RTCV1) 15.1.4 Block Diagram The block diagram for the RTC module is shown in Figure15-2. LPO Clock Source ERCLK Select IRCLK V 8-Bit Modulo DD (RTCMOD) RTCLKS Background D Q RTIF RTC Mode Interrupt Request RTCLKS[0] RTCPS 8-Bit Comparator E R RTC RTIE Write 1 to Prescaler Clock 8-Bit Counter RTIF Divide-By (RTCCNT) Figure15-2. Real-Time Counter (RTC) Block Diagram 15.2 External Signal Description The RTC does not include any off-chip signals. 15.3 Register Definition The RTC includes a status and control register, an 8-bit counter register, and an 8-bit modulo register. Refertothedirect-pageregistersummaryinthememorysectionofthisdocumentfortheabsoluteaddress assignmentsforallRTCregisters.Thissectionreferstoregistersandcontrolbitsonlybytheirnamesand relative address offsets. Table15-1 is a summary of RTC registers. Table15-1.RTC Register Summary Name 7 6 5 4 3 2 1 0 R RTCSC RTIF RTCLKS RTIE RTCPS W R RTCCNT RTCCNT W R RTCMOD RTCMOD W MC9S08DZ60 Series Data Sheet, Rev. 4 312 Freescale Semiconductor

Chapter 15 Real-Time Counter (S08RTCV1) 15.3.1 RTC Status and Control Register (RTCSC) RTCSC contains the real-time interrupt status flag (RTIF), the clock select bits (RTCLKS), the real-time interrupt enable bit (RTIE), and the prescaler select bits (RTCPS). 7 6 5 4 3 2 1 0 R RTIF RTCLKS RTIE RTCPS W Reset: 0 0 0 0 0 0 0 0 Figure15-3. RTC Status and Control Register (RTCSC) Table15-2. RTCSC Field Descriptions Field Description 7 Real-TimeInterruptFlagThisstatusbitindicatestheRTCcounterregisterreachedthevalueintheRTCmodulo RTIF register.Writingalogic0hasnoeffect.Writingalogic1clearsthebitandthereal-timeinterruptrequest.Reset clears RTIF. 0 RTC counter has not reached the value in the RTC modulo register. 1 RTC counter has reached the value in the RTC modulo register. 6–5 Real-Time Clock Source Select. These two read/write bits select the clock source input to the RTC prescaler. RTCLKS ChangingtheclocksourceclearstheprescalerandRTCCNTcounters.Whenselectingaclocksource,ensure that the clock source is properly enabled (if applicable) to ensure correct operation of the RTC. Reset clears RTCLKS. 00 Real-time clock source is the 1-kHz low power oscillator (LPO) 01 Real-time clock source is the external clock (ERCLK) 1x Real-time clock source is the internal clock (IRCLK) 4 Real-Time Interrupt Enable. This read/write bit enables real-time interrupts. If RTIE is set, then an interrupt is RTIE generated when RTIF is set. Reset clears RTIE. 0 Real-time interrupt requests are disabled. Use software polling. 1 Real-time interrupt requests are enabled. 3–0 Real-Time Clock Prescaler Select. These four read/write bits select binary-based or decimal-based divide-by RTCPS values for the clock source. SeeTable15-3. Changing the prescaler value clears the prescaler and RTCCNT counters. Reset clears RTCPS. Table15-3. RTC Prescaler Divide-by values RTCPS RTCLKS[0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Off 23 25 26 27 28 29 210 1 2 22 10 24 102 5x102 103 1 Off 210 211 212 213 214 215 216 103 2x103 5x103 104 2x104 5x104 105 2x105 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 313

Chapter 15 Real-Time Counter (S08RTCV1) 15.3.2 RTC Counter Register (RTCCNT) RTCCNT is the read-only value of the current RTC count of the 8-bit counter. 7 6 5 4 3 2 1 0 R RTCCNT W Reset: 0 0 0 0 0 0 0 0 Figure15-4. RTC Counter Register (RTCCNT) Table15-4. RTCCNT Field Descriptions Field Description 7:0 RTCCount.Theseeightread-onlybitscontainthecurrentvalueofthe8-bitcounter.Writeshavenoeffecttothis RTCCNT register. Reset, writing to RTCMOD, or writing different values to RTCLKS and RTCPS clear the count to 0x00. 15.3.3 RTC Modulo Register (RTCMOD) 7 6 5 4 3 2 1 0 R RTCMOD W Reset: 0 0 0 0 0 0 0 0 Figure15-5. RTC Modulo Register (RTCMOD) Table15-5. RTCMOD Field Descriptions Field Description 7:0 RTCModulo.Theseeightread/writebitscontainthemodulovalueusedtoresetthecountto0x00uponacompare RTCMOD match and set the RTIF status bit. A value of 0x00 sets the RTIF bit on each rising edge of the prescaler output. Writing to RTCMOD resets the prescaler and the RTCCNT counters to 0x00. Reset sets the modulo to 0x00. 15.4 Functional Description The RTC is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with binary-based and decimal-based selectable values. The module also contains software selectable interrupt logic. AfteranyMCUreset,thecounterisstoppedandresetto0x00,themodulusregisterissetto0x00,andthe prescaler is off. The 1-kHz internal oscillator clock is selected as the default clock source. To start the prescaler, write any value other than zero to the prescaler select bits (RTCPS). Three clock sources are software selectable: the low power oscillator clock (LPO), the external clock (ERCLK),andtheinternalclock(IRCLK).TheRTCclockselectbits(RTCLKS)selectthedesiredclock source. Ifa different value is written toRTCLKS, the prescaler and RTCCNT counters are reset to 0x00. MC9S08DZ60 Series Data Sheet, Rev. 4 314 Freescale Semiconductor

Chapter 15 Real-Time Counter (S08RTCV1) RTCPSandtheRTCLKS[0]bitselectthedesireddivide-byvalue.IfadifferentvalueiswrittentoRTCPS, theprescalerandRTCCNTcountersareresetto0x00.Table15-6showsdifferentprescalerperiodvalues. Table15-6. Prescaler Period 1-kHz Internal Clock 1-MHz External Clock 32-kHz Internal Clock 32-kHz Internal Clock RTCPS (RTCLKS = 00) (RTCLKS = 01) (RTCLKS = 10) (RTCLKS = 11) 0000 Off Off Off Off 0001 8 ms 1.024 ms 250μs 32 ms 0010 32 ms 2.048 ms 1 ms 64 ms 0011 64 ms 4.096 ms 2 ms 128 ms 0100 128 ms 8.192 ms 4 ms 256 ms 0101 256 ms 16.4 ms 8 ms 512 ms 0110 512 ms 32.8 ms 16 ms 1.024 s 0111 1.024 s 65.5 ms 32 ms 2.048 s 1000 1 ms 1 ms 31.25μs 31.25 ms 1001 2 ms 2 ms 62.5μs 62.5 ms 1010 4 ms 5 ms 125μs 156.25 ms 1011 10 ms 10 ms 312.5μs 312.5 ms 1100 16 ms 20 ms 0.5 ms 0.625 s 1101 0.1 s 50 ms 3.125 ms 1.5625 s 1110 0.5 s 0.1 s 15.625 ms 3.125 s 1111 1 s 0.2 s 31.25 ms 6.25 s TheRTCmoduloregister(RTCMOD)allowsthecomparevaluetobesettoanyvaluefrom0x00to0xFF. Whenthecounterisactive,thecounterincrementsattheselectedrateuntilthecountmatchesthemodulo value.Whenthesevaluesmatch,thecounterresetsto0x00andcontinuescounting.Thereal-timeinterrupt flag (RTIF) is set when a match occurs. The flag sets on the transition from the modulo value to 0x00. Writing toRTCMOD resets the prescaler and the RTCCNT counters to 0x00. The RTC allows for an interrupt to be generated when RTIF is set. To enable the real-time interrupt, set the real-time interrupt enable bit (RTIE) inRTCSC. RTIF is cleared by writing a 1 to RTIF. 15.4.1 RTC Operation Example This section shows an example of the RTC operation as the counter reaches a matching value from the modulo register. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 315

Chapter 15 Real-Time Counter (S08RTCV1) Internal 1-kHz Clock Source RTC Clock (RTCPS=0xA) RTCCNT 0x52 0x53 0x54 0x55 0x00 0x01 RTIF RTCMOD 0x55 Figure15-6. RTC Counter Overflow Example IntheexampleofFigure15-6,theselectedclocksourceisthe1-kHzinternaloscillatorclocksource.The prescaler(RTCPS)issetto0xAordivide-by-4.ThemodulovalueintheRTCMODregisterissetto0x55. When the counter, RTCCNT, reaches the modulo value of 0x55, the counter overflows to 0x00 and continuescounting.Thereal-timeinterruptflag,RTIF,setswhenthecountervaluechangesfrom0x55to 0x00. A real-time interrupt is generated when RTIF is set, if RTIE is set. 15.5 Initialization/Application Information Thissectionprovidesexamplecodetogivesomebasicdirectiontoauseronhowtoinitializeandconfigure the RTC module. The example software is implemented in C language. The example below shows how to implement time of day with the RTC using the 1-kHz clock source to achieve the lowest possible power consumption. Because the 1-kHz clock source is not as accurate as a crystal, software can be added for any adjustments. For accuracy without adjustments at the expense of additionalpowerconsumption,theexternalclock(ERCLK)ortheinternalclock(IRCLK)canbeselected with appropriate prescaler and modulo values. /* Initialize the elapsed time counters */ Seconds = 0; Minutes = 0; Hours = 0; Days=0; /* Configure RTC to interrupt every 1 second from 1-kHz clock source */ RTCMOD.byte = 0x00; RTCSC.byte = 0x1F; /********************************************************************** Function Name : RTC_ISR Notes : Interrupt service routine for RTC module. **********************************************************************/ MC9S08DZ60 Series Data Sheet, Rev. 4 316 Freescale Semiconductor

Chapter 15 Real-Time Counter (S08RTCV1) #pragma TRAP_PROC void RTC_ISR(void) { /* Clear the interrupt flag */ RTCSC.byte = RTCSC.byte | 0x80; /* RTC interrupts every 1 Second */ Seconds++; /* 60 seconds in a minute */ if (Seconds > 59){ Minutes++; Seconds = 0; } /* 60 minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = 0; } /* 24 hours in a day */ if (Hours > 23){ Days ++; Hours = 0; } MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 317

Chapter 15 Real-Time Counter (S08RTCV1) MC9S08DZ60 Series Data Sheet, Rev. 4 318 Freescale Semiconductor

Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) NOTE ThischapterreferstoS08TPMversion3,whichappliestothe0M74Kand newer mask sets of this device. 3M05C and older mask set devices use S08TPM version 2. If your device uses mask 3M05C or older, please refer toAppendixB, “Timer Pulse-Width Modulator (TPMV2)on page 391 for information pertaining to that module. 16.1 Introduction TheTPMisaone-to-eight-channeltimersystemwhichsupportstraditionalinputcapture,outputcompare, or edge-aligned PWM on each channel. A control bit allows the TPM to be configured such that all channelsmaybeusedforcenter-alignedPWMfunctions.Timingfunctionsarebasedona16-bitcounter withprescalerandmodulofeaturestocontrolfrequencyandrange(periodbetweenoverflows)ofthetime reference. This timing system is ideally suited for a wide range of control applications, and the center-aligned PWM capability extends the field of application to motor control in small appliances. The TPM uses one input/output (I/O) pin per channel, TPMxCHn, where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 0–5). The TPM shares its I/O pins with general-purpose I/O port pins (refer to thePins and Connections chapter for more information). MC9S08DZ60SeriesMCUshavetwoTPMmodules.Inallpackages,TPM2is2-channel.Thenumberof channels available on external pins in TPM1 depends on the package: • Six channels in 64-pin and 48-pin packages • Four channels in 32-pin packages. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 319

Chapter16 Timer Pulse-Width Modulator (S08TPMV3) HCS08 CORE PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 CPU ANALOG COMPARATOR ACMP1O ORT A PPTTAA34//PPIIAA34//AADDPP34/ACMP1O BKGD/MS (ACMP1) ACMP1- P PTA2/PIA2/ADP2/ACMP1- BDC BKP ACMP1+ PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK HCS08 SYSTEM CONTROL PTB7/PIB7/ADP15 RESET RESETS AND INTERRUPTS PTB6/PIB6/ADP14 MODES OF OPERATION PTB5/PIB5/ADP13 POWER MANAGEMENT T B PTB4/PIB4/ADP12 OR PTB3/PIB3/ADP11 8 P PTB2/PIB2/ADP10 COP LVD Q PTB1/PIB1/ADP9 R INT IRQ I ADP7-ADP0 PTB0/PIB0/ADP8 24-CHANNEL,12--BIT PTC7/ADP23 ADP15-ADP8 ANALOG-TO-DIGITAL PTC6/ADP22 VREFH CONVERTER (ADC) ADP23-ADP16 PTC5/ADP21 V VREFL T C PTC4/ADP20 DDA OR PTC3/ADP19 VSSA P PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 USER FLASH TPM1CH5 - PTD7/PID7/TPM1CH5 MC9S0DZ60 = 60K 6-CHANNEL TIMER/PWM TPM1CH0 6 MC9S0DZ48 = 48K MODULE (TPM1) TPM1CLK PTD6/PID6/TPM1CH4 MC9S0DZ32 = 32K PTD5/PID5/TPM1CH3 MC9S0DZ16 = 16K T D PTD4/PID4/TPM1CH2 TPM2CH1, OR PTD3/PID3/TPM1CH1 2-CHANNEL TIMER/PWM TPM2CH0 P PTD2/PID2/TPM1CH0 MODULE (TPM2) TPM2CLK PTD1/PID1/TPM2CH1 USER EEPROM PTD0/PID0/TPM2CH0 MC9S0DZ60 = 2K CONTROLLER AREA RxCAN PTE7/RxD2/RXCAN NETWORK (MSCAN) TxCAN PTE6/TxD2/TXCAN MISO PTE5/SDA/MISO MCU9SS0EDRZ R60A M= 4K INTSEERRFIAALC EP EMROIPDHUELREA (SLPI) SMPOSSCIK ORT E PPTTEE34//SSPCSL/CMKOSI SS P PTE2/SS RxD1 PTE1/RxD1 DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1 PTE0/TxD1 INTERFACE (SCI1) PTF7 ACMP2O ANALOG COMPARATOR PTF6/ACMP2O REAL-TIME COUNTER (RTC) (ACMP2) ACMP2- PTF5/ACMP2- ACMP2+ VVDDDD VOLTAGE IIC MODULE (IIC) SSCDLA PORT F PPPTTTFFF342///TATPPCMMM21PCC2LL+KK//SSDCAL RxD2 VSS REGULATOR PTF1/RxD2 V SERIAL COMMUNICATIONS TxD2 SS PTF0/TxD2 INTERFACE (SCI2) PTG5 MULTI-PURPOSE PTG4 CLOCK GENERATOR G PTG3 (MCG) T R PTG2 XTAL PO PTG1/XTAL OSCILLATOR (XOSC) EXTAL PTG0/EXTAL - V /V internally connected to V /V in 48-pin and 32-pin packages - Pin not connected in 48-pin and 32-pin packages REFH REFL DDA SSA - V and V pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package DD SS Figure16-1. MC9S08DZ60 Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 320 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) 16.1.1 Features The TPM includes these distinctive features: • One to eightchannels: — Each channel may be input capture, output compare, or edge-aligned PWM — Rising-Edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs • Module may be configured for buffered,center-aligned pulse-width-modulation (CPWM) on all channels • Timer clock source selectable as prescaled bus clock, fixed system clock, or an external clock pin — Prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128 — Fixed system clock source are synchronized to the bus clock by an on-chip synchronization circuit — External clock pin may be shared with any timer channel pin or a separated input pin • 16-bit free-running or modulo up/down count operation • Timer system enable • One interrupt per channel plus terminal count interrupt 16.1.2 Modes of Operation In general, TPM channels may be independently configured to operate in input capture, output compare, or edge-aligned PWM modes. A control bit allows the whole TPM (all channels) to switch to center-alignedPWMmode.Whencenter-alignedPWMmodeisselected,inputcapture,outputcompare, and edge-aligned PWM functions are not available on any channels of this TPM module. WhenthemicrocontrollerisinactiveBDMbackgroundorBDMforegroundmode,theTPMtemporarily suspendsallcountinguntilthemicrocontrollerreturnstonormaluseroperatingmode.Duringstopmode, all system clocks, including the main oscillator, are stopped; therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to operate normally. Provided the TPM does notneedtoproducearealtimereferenceorprovidetheinterruptsource(s)neededtowaketheMCUfrom wait mode, the user can save power by disabling TPM functions before entering wait mode. • Input capture mode WhenaselectededgeeventoccursontheassociatedMCUpin,thecurrentvalueofthe16-bittimer counter is captured into the channel value register and an interrupt flag bit is set. Rising edges, falling edges, any edge, or no edge (disable channel) may be selected as the active edge which triggers the input capture. • Output compare mode When the value in the timer counter register matches the channel value register, an interrupt flag bit is set, and a selected output action is forced on the associated MCU pin. The output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions). MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 321

Chapter 16 Timer/PWM Module (S08TPMV3) • Edge-aligned PWM mode Thevalueofa16-bitmoduloregisterplus1setstheperiodofthePWMoutputsignal.Thechannel valueregistersetsthedutycycleofthePWMoutputsignal.Theusermayalsochoosethepolarity of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle transition point. This type of PWM signal is called edge-aligned because the leading edges of all PWMsignalsarealignedwiththebeginningoftheperiod,whichisthesameforallchannelswithin a TPM. • Center-aligned PWM mode Twice the value of a 16-bit modulo register sets the period of the PWM output, and the channel-value register sets the half-duty-cycle duration. The timer counter counts up until it reaches the modulo value and then counts down until it reaches zero. As the count matches the channel value register while counting down, the PWM output becomes active. When the count matchesthechannelvalueregisterwhilecountingup,thePWMoutputbecomesinactive.Thistype ofPWMsignaliscalledcenter-alignedbecausethecentersoftheactivedutycycleperiodsforall channelsarealignedwithacountvalueofzero.ThistypeofPWMisrequiredfortypesofmotors used in small appliances. This is a high-level description only. Detailed descriptions of operating modes are in later sections. 16.1.3 Block Diagram TheTPMusesoneinput/output(I/O)pinperchannel,TPMxCHn(timerchanneln)wherenisthechannel number(1-8).TheTPMsharesitsI/OpinswithgeneralpurposeI/Oportpins(refertoI/Opindescriptions in full-chip specification for the specific chip implementation). Figure16-2 shows the TPM structure. The central component of the TPM is the 16-bit counter that can operate as a free-running counter or a modulo up/down counter. The TPM counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control themodulovalueofthecounter(thevalues0x0000or0xFFFFeffectivelymakethecounterfreerunning). Software can read the counter value at any time without affecting the counting sequence. Any write to either half of the TPMxCNT counter resets the counter, regardless of the data value written. MC9S08DZ60 Series Data Sheet, Rev. 4 322 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) BUS CLOCK CLOCK SOURCE PRESCALE AND SELECT SELECT 1, 2, 4, 8, 16, 32, 64, FIXED SYSTEM CLOCK OFF, BUS, FIXED SYNC or 128 EXTERNAL CLOCK SYSTEM CLOCK, EXT CLKSB:CLKSA PS2:PS1:PS0 CPWMS 16-BIT COUNTER TOF INTER- COUNTER RESET RUPT TOIE LOGIC 16-BIT COMPARATOR TPMxMODH:TPMxMODL CHANNEL 0 ELS0B ELS0A PORT TPMxCH0 LOGIC 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTER- 16-BIT LATCH RUPT LOGIC MS0B MS0A CH0IE S CHANNEL 1 ELS1B ELS1A PORT TPMxCH1 U LOGIC L B 16-BIT COMPARATOR A N TPMxC1VH:TPMxC1VL CH1F R E INTER- NT 16-BIT LATCH RUPT I LOGIC CH1IE MS1B MS1A Up to 8 channels CHANNEL 7 ELS7B ELS7A PORT TPMxCH7 LOGIC 16-BIT COMPARATOR TPMxC7VH:TPMxC7VL CH7F INTER- 16-BIT LATCH RUPT LOGIC CH7IE MS7B MS7A Figure16-2. TPM Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 323

Chapter 16 Timer/PWM Module (S08TPMV3) The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWMchannels.Alternately,theTPMcanbeconfiguredtoproduceCPWMoutputsonallchannels.When the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output compare, and EPWM functions are not practical. Ifachannelisconfiguredasinputcapture,aninternalpullupdevicemaybeenabledforthatchannel.The detailsofhowamoduleinteractswithpincontrolsdependsuponthechipimplementationbecausetheI/O pinsandassociatedgeneralpurposeI/Ocontrolsarenotpartofthemodule.Refertothediscussionofthe I/O port logic in a full-chip specification. Because center-aligned PWMs are usually used to drive 3-phase AC-induction motors and brushless DC motors, they are typically used in sets of three or six channels. 16.2 Signal Description Table16-1 shows the user-accessible signals for the TPM. The number of channels may be varied from onetoeight.Whenanexternalclockisincluded,itcanbesharedwiththesamepinasanyTPMchannel; however, it could be connected to a separate input pin. Refer to the I/O pin descriptions in full-chip specification for the specific chip implementation. Table16-1. Signal Properties Name Function EXTCLK1 External clock source which may be selected to drive the TPM counter. TPMxCHn2 I/O pin associated with TPM channel n 1 When preset, this signal can share any channel pin; however depending upon full-chip implementation, this signal could be connected to a separate external pin. 2 n=channel number (1 to 8) Refertodocumentationforthefull-chipfordetailsaboutresetstates,portconnections,andwhetherthere is any pullup device on these pins. TPMchannelpinscanbeassociatedwithgeneralpurposeI/Opinsandhavepassivepullupdeviceswhich can be enabled with a control bit when the TPM or general purpose I/O controls have configured the associated pin as an input. When no TPM function is enabled to use a corresponding pin, the pin reverts to being controlled by general purpose I/O controls, including the port-data and data-direction registers. Immediatelyafterreset,noTPMfunctionsareenabled,soallassociatedpinsreverttogeneralpurposeI/O control. 16.2.1 Detailed Signal Descriptions Thissectiondescribeseachuser-accessiblepinsignalindetail.AlthoughTable16-1groupedallchannel pinstogether,anyTPMpincanbesharedwiththeexternalclocksourcesignal.SinceI/Opinlogicisnot part of the TPM, refer to full-chip documentation for a specific derivative for more details about the interactionofTPMpinfunctionsandgeneralpurposeI/Ocontrolsincludingportdata,datadirection,and pullup controls. MC9S08DZ60 Series Data Sheet, Rev. 4 324 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) 16.2.1.1 EXTCLK — External Clock Source Control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rateclock(thenormaldefaultsource),acrystal-relatedclock,oranexternalclockastheclockwhich drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is synchronizedintheTPM.Thebusclockclocksthesynchronizer;thefrequencyoftheexternalsourcemust benomorethanone-fourththefrequencyofthebus-rateclock,tomeetNyquistcriteriaandallowingfor jitter. The external clock signal shares the same pin as a channel I/O pin, so the channel pin will not be usable forchannelI/Ofunctionwhenselectedastheexternalclocksource.Itistheuser’sresponsibilitytoavoid suchsettings.Ifthispinisusedasanexternalclocksource(CLKSB:CLKSA=1:1),thechannelcanstill be used in output compare mode as a software timer (ELSnB:ELSnA = 0:0). 16.2.1.2 TPMxCHn — TPM Channel n I/O Pin(s) Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the channelconfiguration.TheTPMpinssharewithgeneralpurposeI/Opins,whereeachpinhasaportdata registerbit,andadatadirectioncontrolbit,andtheporthasoptionalpassivepullupswhichmaybeenabled whenever a port pin is acting as an input. TheTPMchanneldoesnotcontroltheI/Opinwhen(ELSnB:ELSnA=0:0)orwhen(CLKSB:CLKSA= 0:0)soitnormallyrevertstogeneralpurposeI/Ocontrol.WhenCPWMS=1(andELSnB:ELSnAnot= 0:0),allchannelswithintheTPMareconfiguredforcenter-alignedPWMandtheTPMxCHnpinsareall controlled by the TPM system. When CPWMS=0, the MSnB:MSnA control bits determine whether the channel is configured for input capture, output compare, or edge-aligned PWM. Whenachannelisconfiguredforinputcapture(CPWMS=0,MSnB:MSnA=0:0andELSnB:ELSnAnot = 0:0), the TPMxCHn pin is forced to act as an edge-sensitive input to the TPM. ELSnB:ELSnA control bitsdeterminewhatpolarityedgeoredgeswilltriggerinput-captureevents.Asynchronizerbasedonthe busclockisusedtosynchronizeinputedgestothebusclock.Thisimpliestheminimumpulsewidth—that canbereliablydetected—onaninputcapturepinisfourbusclockperiods(withidealclockpulsesasnear as two bus clocks can be detected). TPM uses this pin as an input capture input to override the port data and data direction controls for the same pin. When a channel is configured for output compare (CPWMS=0, MSnB:MSnA = 0:1 and ELSnB:ELSnA not=0:0),theassociateddatadirectioncontrolisoverridden,theTPMxCHnpinisconsideredanoutput controlled by the TPM, and the ELSnB:ELSnA control bits determine how the pin is controlled. The remainingthreecombinationsofELSnB:ELSnAdeterminewhethertheTPMxCHnpinistoggled,cleared, or set each time the 16-bit channel value register matches the timer counter. Whentheoutputcomparetogglemodeisinitiallyselected,thepreviousvalueonthepinisdrivenoutuntil the next output compare event—then the pin is toggled. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 325

Chapter 16 Timer/PWM Module (S08TPMV3) When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not = 0:0),thedatadirectionisoverridden,theTPMxCHnpinisforcedtobeanoutputcontrolledbytheTPM, and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced low when the channel value register matches the timer counter. When ELSnA=1, the TPMxCHn pin is forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the channel value register matches the timer counter. TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL ... 0 1 2 3 4 5 6 7 8 0 1 2 ... TPMxCHn CHnF BIT TOF BIT Figure16-3. High-True Pulse of an Edge-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL ... 0 1 2 3 4 5 6 7 8 0 1 2 ... TPMxCHn CHnF BIT TOF BIT Figure16-4.Low-True Pulse of an Edge-Aligned PWM MC9S08DZ60 Series Data Sheet, Rev. 4 326 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) WhentheTPMisconfiguredforcenter-alignedPWM(andELSnB:ELSnAnot=0:0),thedatadirection forallchannelsinthisTPMareoverridden,theTPMxCHnpinsareforcedtobeoutputscontrolledbythe TPM, and the ELSnA bits control the polarity of each TPMxCHn output. If ELSnB:ELSnA=1:0, the corresponding TPMxCHn pin is cleared when the timer counter is counting up, and the channel value registermatchesthetimercounter;theTPMxCHnpinissetwhenthetimercounteriscountingdown,and thechannelvalueregistermatchesthetimercounter.IfELSnA=1,thecorrespondingTPMxCHnpinisset when the timer counter is counting up and the channel value register matches the timer counter; the TPMxCHnpinisclearedwhenthetimercounteriscountingdownandthechannelvalueregistermatches the timer counter. TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ... TPMxCHn CHnF BIT TOF BIT Figure16-5.High-True Pulse of a Center-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ... TPMxCHn CHnF BIT TOF BIT Figure16-6.Low-True Pulse of a Center-Aligned PWM MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 327

Chapter 16 Timer/PWM Module (S08TPMV3) 16.3 Register Definition Thissectionconsistsofregisterdescriptionsinaddressorder.AtypicalMCUsystemmaycontainmultiple TPMs,andeachTPMmayhaveonetoeightchannels,soregisternamesincludeplaceholdercharactersto identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1. 16.3.1 TPM Status and Control Register (TPMxSC) TPMxSC contains the overflow status flag and control bits used to configure the interrupt enable, TPM configuration, clock source, and prescale factor. These controls relate to all channels within this timer module. 7 6 5 4 3 2 1 0 R TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 W 0 Reset 0 0 0 0 0 0 0 0 Figure16-7. TPM Status and Control Register (TPMxSC) Table16-2. TPMxSC Field Descriptions Field Description 7 Timeroverflowflag.Thisread/writeflagissetwhentheTPMcounterresetsto0x0000afterreachingthemodulo TOF value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control register when TOF is set and then writing a logic 0 to TOF. If another TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect. 0 TPM counter has not reached modulo value or overflow 1 TPM counter has overflowed 6 Timeroverflowinterruptenable.Thisread/writebitenablesTPMoverflowinterrupts.IfTOIEisset,aninterruptis TOIE generated when TOF equals one. Reset clears TOIE. 0 TOF interrupts inhibited (use for software polling) 1 TOF interrupts enabled 5 Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the CPWMS TPMoperatesinup-countingmodeforinputcapture,outputcompare,andedge-alignedPWMfunctions.Setting CPWMSreconfigurestheTPMtooperateinup/downcountingmodeforCPWMfunctions.ResetclearsCPWMS. 0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channel’s status and control register. 1 All channels operate in center-aligned PWM mode. MC9S08DZ60 Series Data Sheet, Rev. 4 328 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) Table16-2. TPMxSC Field Descriptions (continued) Field Description 4–3 Clock source selects. As shown inTable16-3, this 2-bit field is used to disable the TPM system or select one of CLKS[B:A] three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems withaPLL-basedorFLL-basedsystemclock.WhenthereisnoPLLorFLL,thefixed-systemclocksourceisthe sameasthebusrateclock.TheexternalsourceissynchronizedtothebusclockbyTPMmodule,andthefixed system clock source (when a PLL or FLL is present) is synchronized to the bus clock by an on-chip synchronizationcircuit.WhenaPLLorFLLispresentbutnotenabled,thefixed-systemclocksourceisthesame as the bus-rate clock. 2–0 Prescale factor select. This 3-bit field selects one of 8 division factors for the TPM clock input as shown in PS[2:0] Table16-4.Thisprescalerislocatedafteranyclocksourcesynchronizationorclocksourceselectionsoitaffects the clock source selected to drive the TPM system. The new prescale factor will affect the clock source on the next system clock cycle after the new value is updated into the register bits. Table16-3. TPM-Clock-Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 00 No clock selected (TPM counter disable) 01 Bus rate clock 10 Fixed system clock 11 External source Table16-4. Prescale Factor Selection PS2:PS1:PS0 TPM Clock Source Divided-by 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) Thetworead-onlyTPMcounterregisterscontainthehighandlowbytesofthevalueintheTPMcounter. Readingeitherbyte(TPMxCNTHorTPMxCNTL)latchesthecontentsofbothbytesintoabufferwhere they remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or little-endian order which makes this more friendly to various compiler implementations. The coherency mechanism is automatically restarted by an MCU reset or any write to the timer status/control register (TPMxSC). MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 329

Chapter 16 Timer/PWM Module (S08TPMV3) ResetclearstheTPMcounterregisters.WritinganyvaluetoTPMxCNTHorTPMxCNTLalsoclearsthe TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Any write to TPMxCNTH clears the 16-bit counter Reset 0 0 0 0 0 0 0 0 Figure16-8. TPM Counter Register High (TPMxCNTH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Any write to TPMxCNTL clears the 16-bit counter Reset 0 0 0 0 0 0 0 0 Figure16-9. TPM Counter Register Low (TPMxCNTL) WhenBDMisactive,thetimercounterisfrozen(thisisthevaluethatwillbereadbyuser);thecoherency mechanismisfrozensuchthatthebufferlatchesremaininthestatetheywereinwhentheBDMbecame active, even if one or both counter halves are read while BDM is active. This assures that if the user was inthemiddleofreadinga16-bitregisterwhenBDMbecameactive,itwillreadtheappropriatevaluefrom the other half of the 16-bit value after returning to normal execution. In BDM mode, writing any value to TPMxSC, TPMxCNTH or TPMxCNTL registers resets the read coherency mechanism of the TPMxCNTH:L registers, regardless of the data involved in the write. 16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counterreachesthemodulovalue,theTPMcounterresumescountingfrom0x0000atthenextclock,and theoverflowflag(TOF)becomesset.WritingtoTPMxMODHorTPMxMODLinhibitstheTOFbitand overflowinterruptsuntiltheotherbyteiswritten.ResetsetstheTPMcountermoduloregistersto0x0000 which results in a free running timer counter (modulo disabled). Writingtoeitherbyte(TPMxMODHorTPMxMODL)latchesthevalueintoabufferandtheregistersare updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written • If(CLKSB:CLKSAnot=0:0),thentheregistersareupdatedafterbothbyteswerewritten,andthe TPMcounterchangesfrom(TPMxMODH:TPMxMODL-1)to(TPMxMODH:TPMxMODL).If theTPMcounterisafree-runningcounter,theupdateismadewhentheTPMcounterchangesfrom 0xFFFE to 0xFFFF The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is active or not). MC9S08DZ60 Series Data Sheet, Rev. 4 330 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register) suchthatthebufferlatchesremaininthestatetheywereinwhentheBDMbecameactive,evenifoneor both halves of the modulo register are written while BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while BDM is active. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure16-10. TPM Counter Modulo Register High (TPMxMODH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure16-11. TPM Counter Modulo Register Low (TPMxMODL) ResettheTPMcounterbeforewritingtotheTPMmoduloregisterstoavoidconfusionaboutwhenthefirst counter overflow will occur. 16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 1 0 R CHnF 0 0 CHnIE MSnB MSnA ELSnB ELSnA W 0 Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure16-12. TPM Channel n Status and Control Register (TPMxCnSC) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 331

Chapter 16 Timer/PWM Module (S08TPMV3) Table16-5. TPMxCnSC Field Descriptions Field Description 7 Channelnflag.Whenchannelnisaninput-capturechannel,thisread/writebitissetwhenanactiveedgeoccurs CHnF onthechannelnpin.Whenchannelnisanoutputcompareoredge-aligned/center-alignedPWMchannel,CHnF issetwhenthevalueintheTPMcounterregistersmatchesthevalueintheTPMchannelnvalueregisters.When channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF will not be set even when the value in the TPM counter registers matches the value in the TPM channel n value registers. AcorrespondinginterruptisrequestedwhenCHnFissetandinterruptsareenabled(CHnIE=1).ClearCHnFby reading TPMxCnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence completedfortheearlierCHnF.ThisisdonesoaCHnFinterruptrequestcannotbelostduetoclearingaprevious CHnF. Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect. 0 No input capture or output compare event occurred on channel n 1 Input capture or output compare event on channel n 6 Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears CHnIE. CHnIE 0 Channel n interrupt requests disabled (use for software polling) 1 Channel n interrupt requests enabled 5 ModeselectBforTPMchanneln.WhenCPWMS=0,MSnB=1configuresTPMchannelnforedge-alignedPWM MSnB mode. Refer to the summary of channel mode and setup controls inTable16-6. 4 Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA configures TPM channel n for MSnA input-capture mode or output compare mode. Refer toTable16-6 for a summary of channel mode and setup controls. Note:If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. 3–2 Edge/levelselectbits.DependingupontheoperatingmodeforthetimerchannelassetbyCPWMS:MSnB:MSnA ELSnB andshowninTable16-6,thesebitsselectthepolarityoftheinputedgethattriggersaninputcaptureevent,select ELSnA the level that will be driven in response to an output compare match, or select the polarity of the PWM output. SettingELSnB:ELSnAto0:0configurestherelatedtimerpinasageneralpurposeI/Opinnotrelatedtoanytimer functions.Thisfunctionistypicallyusedtotemporarilydisableaninputcapturechannelortomakethetimerpin availableasageneralpurposeI/Opinwhentheassociatedtimerchannelissetupasasoftwaretimerthatdoes not require the use of a pin. Table16-6. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration X XX 00 Pin not used for TPM - revert to general purpose I/O or other peripheral control MC9S08DZ60 Series Data Sheet, Rev. 4 332 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) Table16-6. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration 0 00 01 Input capture Captureonrisingedge only 10 Captureonfallingedge only 11 Capture on rising or falling edge 01 01 Output compare Toggle output on compare 10 Clearoutput on compare 11 Setoutput on compare 1X 10 Edge-aligned High-true pulses (clear PWM output on compare) X1 Low-true pulses (set output on compare) 1 XX 10 Center-aligned High-true pulses (clear PWM output on compare-up) X1 Low-true pulses (set output on compare-up) 16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel registers are cleared by reset. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure16-13. TPM Channel Value Register High (TPMxCnVH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure16-14. TPM Channel Value Register Low (TPMxCnVL) Ininputcapturemode,readingeitherbyte(TPMxCnVHorTPMxCnVL)latchesthecontentsofbothbytes into a buffer where they remain latched until the other half is read. This latching mechanism also resets MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 333

Chapter 16 Timer/PWM Module (S08TPMV3) (becomesunlatched)whentheTPMxCnSCregisteriswritten(whetherBDMmodeisactiveornot).Any write to the channel registers will be ignored during the input capture mode. WhenBDMisactive,thecoherencymechanismisfrozen(unlessresetbywritingtoTPMxCnSCregister) suchthatthebufferlatchesremaininthestatetheywereinwhentheBDMbecameactive,evenifoneor both halves of the channel register are read while BDM is active. This assures that if the user was in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. The value read from the TPMxCnVH and TPMxCnVL registers in BDM mode is the value of these registers and not the value of their read buffer. InoutputcompareorPWMmodes,writingtoeitherbyte(TPMxCnVHorTPMxCnVL)latchesthevalue into a buffer. After both bytes are written, they are transferred as a coherent 16-bit value into the timer-channel registers according to the value of CLKSB:CLKSA bits and the selected mode, so: • If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written. • If(CLKSB:CLKSAnot=0:0andinoutputcomparemode)thentheregistersareupdatedafterthe secondbyteiswrittenandonthenextchangeoftheTPMcounter(endoftheprescalercounting). • If(CLKSB:CLKSAnot=0:0andinEPWMorCPWMmodes),thentheregistersareupdatedafter thebothbyteswerewritten,andtheTPMcounterchangesfrom(TPMxMODH:TPMxMODL-1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. The latching mechanism may be manually reset by writing to the TPMxCnSC register (whether BDM mode is active or not). This latching mechanism allows coherent 16-bit writes in either big-endian or little-endian order which is friendly to various compiler implementations. When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became active even if one or both halves of the channel register are written while BDM is active. Any write to the channel registers bypasses the buffer latches and directly write to thechannelregisterwhileBDMisactive.ThevalueswrittentothechannelregisterwhileBDMisactive are used for PWM & output compare operation once normal execution resumes. Writes to the channel registerswhileBDMisactivedonotinterferewithpartialcompletionofacoherencysequence.Afterthe coherencymechanismhasbeenfullyexercised,thechannelregistersareupdatedusingthebufferedvalues written (while BDM was not active) by the user. 16.4 Functional Description AllTPMfunctionsareassociatedwithacentral16-bitcounterwhichallowsflexibleselectionoftheclock source and prescale factor. There is also a 16-bit modulo register associated with the main counter. The CPWMS control bit chooses between center-aligned PWM operation for all channels in the TPM (CPWMS=1)orgeneralpurposetimingfunctions(CPWMS=0)whereeachchannelcanindependentlybe configuredtooperateininputcapture,outputcompare,oredge-alignedPWMmode.TheCPWMScontrol bit is located in the main TPM status and control register because it affects all channels within the TPM and influences the way the main counter operates. (In CPWM mode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.) MC9S08DZ60 Series Data Sheet, Rev. 4 334 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) The following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend upon the operating mode, these topics will be covered in the associated mode explanation sections. 16.4.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section discusses selection of the clock source, end-of-count overflow, up-counting vs. up/down counting, and manual counter reset. 16.4.1.1 Counter Clock Source The 2-bit field, CLKSB:CLKSA, in the timer status and control register (TPMxSC) selects one of three possibleclocksourcesorOFF(whicheffectivelydisablestheTPM).SeeTable 16-3.AfteranyMCUreset, CLKSB:CLKSA=0:0 so no clock source is selected, and the TPM is in a very low power state. These controlbitsmaybereadorwrittenatanytimeanddisablingthetimer(writing00totheCLKSB:CLKSA field) does not affect the values in the counter or other timer registers. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 335

Chapter 16 Timer/PWM Module (S08TPMV3) Table16-7. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 00 No clock selected (TPM counter disabled) 01 Bus rate clock 10 Fixed system clock 11 External source The bus rate clock is the main system bus clock for the MCU. This clock source requires no synchronization because it is the clock that is used for all internal MCU activities including operation of the CPU and buses. In MCUs that have no PLL and FLL or the PLL and FLL are not engaged, the fixed system clock source is the same as the bus-rate-clock source, and it does not go through a synchronizer. When a PLL or FLL ispresentandengaged,asynchronizerisrequiredbetweenthecrystaldivided-bytwoclocksourceandthe timercountersocountertransitionswillbeproperlyalignedtobus-clocktransitions.Asynchronizerwill be used at chip level to synchronize the crystal-related source clock to the bus clock. TheexternalclocksourcemaybeconnectedtoanyTPMchannelpin.Thisclocksourcealwayshastopass throughasynchronizertoassurethatcountertransitionsareproperlyalignedtobusclocktransitions.The bus-rateclockdrivesthesynchronizer;therefore,tomeetNyquistcriteriaevenwithjitter,thefrequencyof theexternalclocksourcemustnotbefasterthanthebusratedivided-byfour.Withidealclockstheexternal clock can be as fast as bus clock divided by four. WhentheexternalclocksourcesharestheTPMchannelpin,thispinshouldnotbeusedforotherchannel timing functions. For example, it would be ambiguous to configure channel 0 for input capture when the TPM channel 0 pin was also being used as the timer external clock source. (It is the user’s responsibility toavoidsuchsettings.)TheTPMchannelcouldstillbeusedinoutputcomparemodeforsoftwaretiming functions (pin controls set not to affect the TPM channel pin). 16.4.1.2 Counter Overflow and Modulo Reset An interrupt flag and enable are associated with the 16-bit main counter. The flag (TOF) is a software-accessible indication that the timer counter has overflowed. The enable signal selects between software polling (TOIE=0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE=1) where a static hardware interrupt is generated whenever the TOF flag is equal to one. The conditions causing TOF to become set depend on whether the TPM is configured for center-aligned PWM (CPWMS=1). In the simplest mode, there is no modulus limit and the TPM is not in CPWMS=1 mode.Inthiscase,the16-bittimercountercountsfrom0x0000through0xFFFFandoverflowsto0x0000 onthenextcountingclock.TOFbecomessetatthetransitionfrom0xFFFFto0x0000.Whenamodulus limitisset,TOFbecomessetatthetransitionfromthevaluesetinthemodulusregisterto0x0000.When the TPM is in center-aligned PWM mode (CPWMS=1), the TOF flag gets set as the counter changes direction at the end of the count value set in the modulus register (that is, at the transition from the value set in the modulus register to the next lower count value). This corresponds to the end of a PWM period (the 0x0000 count value corresponds to the center of a period). MC9S08DZ60 Series Data Sheet, Rev. 4 336 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) 16.4.1.3 Counting Modes Themaintimercounterhastwocountingmodes.Whencenter-alignedPWMisselected(CPWMS=1),the counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL. Whencenter-alignedPWMoperationisspecified,thecountercountsupfrom0x0000throughitsterminal countandthendownto0x0000whereitchangesbacktoupcounting.Both0x0000andtheterminalcount valuearenormallengthcounts(onetimerclockperiodlong).Inthismode,thetimeroverflowflag(TOF) becomes set at the end of the terminal-count period (as the count changes to the next lower count value). 16.4.1.4 Manual Counter Reset The main timer counter can be manually reset at any time by writing any value to either half of TPMxCNTHorTPMxCNTL.Resettingthecounterinthismanneralsoresetsthecoherencymechanism in case only half of the counter was read before resetting the count. 16.4.2 Channel Mode Selection Provided CPWMS=0, the MSnB and MSnA control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output compare, and edge-aligned PWM. 16.4.2.1 Input Capture Mode Withtheinput-capturefunction,theTPMcancapturethetimeatwhichanexternaleventoccurs.Whenan activeedgeoccursonthepinofaninput-capturechannel,theTPMlatchesthecontentsoftheTPMcounter intothechannel-valueregisters(TPMxCnVH:TPMxCnVL).Risingedges,fallingedges,oranyedgemay be chosen as the active edge that triggers an input capture. In input capture mode, the TPMxCnVH and TPMxCnVL registers are read only. When either half of the 16-bit capture register is read, the other half is latched into a buffer to support coherent 16-bit accesses in big-endian or little-endian order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An input capture event sets a flag bit (CHnF) which may optionally generate a CPU interrupt request. WhileinBDM,theinputcapturefunctionworksasconfiguredbytheuser.Whenanexternaleventoccurs, the TPM latches the contents of the TPM counter (which is frozen because of the BDM mode) into the channel value registers and sets the flag bit. 16.4.2.2 Output Compare Mode With the output-compare function, the TPM can generate timed pulses with programmable position, polarity,duration,andfrequency.Whenthecounterreachesthevalueinthechannel-valueregistersofan output-compare channel, the TPM can set, clear, or toggle the channel pin. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 337

Chapter 16 Timer/PWM Module (S08TPMV3) Inoutputcomparemode,valuesaretransferredtothecorrespondingtimerchannelregistersonlyafterboth 8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter (end of the prescaler counting) after the second byte is written. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An output compare event sets a flag bit (CHnF) which may optionally generate a CPU-interrupt request. 16.4.2.3 Edge-Aligned PWM Mode This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can be used when other channels in the same TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the value of the modulus register (TPMxMODH:TPMxMODL) plus 1. The duty cycle is determined by the setting in the timer channel register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. 0% and 100% duty cycle cases are possible. The output compare value in the TPM channel registers determines the pulse width (duty cycle) of the PWMsignal(Figure16-15).Thetimebetweenthemodulusoverflowandtheoutputcompareisthepulse width.IfELSnA=0,thecounteroverflowforcesthePWMsignalhigh,andtheoutputcompareforcesthe PWMsignallow.IfELSnA=1,thecounteroverflowforcesthePWMsignallow,andtheoutputcompare forces the PWM signal high. OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TPMxCHn OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE Figure16-15. PWM Period and Pulse Width (ELSnA=0) Whenthechannelvalueregisterissetto0x0000,thedutycycleis0%.100%dutycyclecanbeachieved by setting the timer-channel register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting. This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle. BecausetheTPMmaybeusedinan8-bitMCU,thesettingsinthetimerchannelregistersarebufferedto ensurecoherent16-bitupdatesandtoavoidunexpectedPWMpulsewidths.Writestoanyoftheregisters TPMxCnVHandTPMxCnVL,actuallywritetobufferregisters.Inedge-alignedPWMmode,valuesare transferredtothecorrespondingtimer-channelregistersaccordingtothevalueofCLKSB:CLKSAbits,so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If(CLKSB:CLKSAnot=0:0),theregistersareupdatedafterthebothbyteswerewritten,andthe TPMcounterchangesfrom(TPMxMODH:TPMxMODL-1)to(TPMxMODH:TPMxMODL).If MC9S08DZ60 Series Data Sheet, Rev. 4 338 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) theTPMcounterisafree-runningcounterthentheupdateismadewhentheTPMcounterchanges from 0xFFFE to 0xFFFF. 16.4.2.4 Center-Aligned PWM Mode ThistypeofPWMoutputusestheup/downcountingmodeofthetimercounter(CPWMS=1).Theoutput compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal whiletheperiodisdeterminedbythevalueinTPMxMODH:TPMxMODL.TPMxMODH:TPMxMODL shouldbekeptintherangeof0x0001to0x7FFFbecausevaluesoutsidethisrangecanproduceambiguous results. ELSnA will determine the polarity of the CPWM output. pulse width = 2 x (TPMxCnVH:TPMxCnVL) period = 2 x (TPMxMODH:TPMxMODL); TPMxMODH:TPMxMODL=0x0001-0x7FFF Ifthechannel-valueregisterTPMxCnVH:TPMxCnVLiszeroornegative(bit15set),thedutycyclewill be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (non-zero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This impliestheusablerangeofperiodssetbythemodulusregisteris0x0001through0x7FFE(0x7FFFifyou donotneedtogenerate100%dutycycle).Thisisnotasignificantlimitation.Theresultingperiodwould be much longer than required for normal applications. TPMxMODH:TPMxMODL=0x0000 is a special case that should not be used with center-aligned PWM mode.WhenCPWMS=0,thiscasecorrespondstothecounterrunningfreefrom0x0000through0xFFFF, but when CPWMS=1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. TheoutputcomparevalueintheTPMchannelregisters(times2)determinesthepulsewidth(dutycycle) of the CPWM signal (Figure16-16). If ELSnA=0, a compare occurred while counting up forces the CPWM output signal low and a compare occurred while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL. OUTPUT COUNT= 0 OUTPUT COUNT= COMPARE COMPARE COUNT= TPMxMODH:TPMxMODL (COUNT DOWN) (COUNT UP) TPMxMODH:TPMxMODL TPMxCHn PULSE WIDTH 2 x TPMxCnVH:TPMxCnVL PERIOD 2 x TPMxMODH:TPMxMODL Figure16-16. CPWM Period and Pulse Width (ELSnA=0) Center-alignedPWMoutputstypicallyproducelessnoisethanedge-alignedPWMsbecausefewerI/Opin transitionsarelinedupatthesamesystemclockedge.ThistypeofPWMisalsorequiredforsometypes of motor drives. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 339

Chapter 16 Timer/PWM Module (S08TPMV3) Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is operatinginup/downcountingmodesothisimpliesthatallactivechannelswithinaTPMmustbeusedin CPWM mode when CPWMS=1. TheTPMmaybeusedinan8-bitMCU.Thesettingsinthetimerchannelregistersarebufferedtoensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Incenter-alignedPWMmode,theTPMxCnVH:Lregistersareupdatedwiththevalueoftheirwritebuffer according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If(CLKSB:CLKSAnot=0:0),theregistersareupdatedafterthebothbyteswerewritten,andthe TPMcounterchangesfrom(TPMxMODH:TPMxMODL-1)to(TPMxMODH:TPMxMODL).If theTPMcounterisafree-runningcounter,theupdateismadewhentheTPMcounterchangesfrom 0xFFFE to 0xFFFF. When TPMxCNTH:TPMxCNTL=TPMxMODH:TPMxMODL, the TPM can optionally generate a TOF interrupt (at the end of this count). Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the coherencymechanismforthemoduloregisters.WritingtoTPMxCnSCcancelsanyvalueswrittentothe channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. 16.5 Reset Overview 16.5.1 General The TPM is reset whenever any MCU reset occurs. 16.5.2 Description of Reset Operation ResetclearstheTPMxSCregisterwhichdisablesclockstotheTPManddisablestimeroverflowinterrupts (TOIE=0). CPWMS, MSnB, MSnA, ELSnB, and ELSnA are all cleared which configures all TPM channelsforinput-captureoperationwiththeassociatedpinsdisconnectedfromI/Opinlogic(soallMCU pins related to the TPM revert to general purpose I/O pins). 16.6 Interrupts 16.6.1 General TheTPMgeneratesanoptionalinterruptforthemaincounteroverflowandaninterruptforeachchannel. The meaning of channel interrupts depends on each channel’s mode of operation. If the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized.IfthechannelisconfiguredforoutputcompareorPWMmodes,theinterruptflagisseteach time the main timer counter matches the value in the 16-bit channel value register. MC9S08DZ60 Series Data Sheet, Rev. 4 340 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) AllTPMinterruptsarelistedinTable16-8whichshowstheinterruptname,thenameofanylocalenable thatcanblocktheinterruptrequestfromleavingtheTPMandgettingrecognizedbytheseparateinterrupt processing logic. Table16-8. Interrupt Summary Local Interrupt Source Description Enable TOF TOIE Counter overflow Seteachtimethetimercounterreachesitsterminal count (at transition to next count value which is usually 0x0000) CHnF CHnIE Channel event An input capture or output compare event took place on channel n The TPM module will provide a high-true interrupt signal. Vectors and priorities are determined at chip integrationtimeintheinterruptmodulesorefertotheuser’sguidefortheinterruptmoduleortothechip’s complete documentation for details. 16.6.2 Description of Interrupt Operation For each interrupt source in the TPM, a flag bit is set upon recognition of the interrupt condition such as timer overflow, channel-input capture, or output-compare events. This flag may be read (polled) by softwaretodeterminethattheactionhasoccurred,oranassociatedenablebit(TOIEorCHnIE)canbeset toenablehardwareinterruptgeneration.Whiletheinterruptenablebitisset,astaticinterruptwillgenerate whenever the associated interrupt flag equals one. The user’s software must perform a sequence of steps to clear the interrupt flag before returning from the interrupt-service routine. TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set (1) followedbyawriteofzero(0)tothebit.Ifaneweventisdetectedbetweenthesetwosteps,thesequence isresetandtheinterruptflagremainssetafterthesecondsteptoavoidthepossibilityofmissingthenew event. 16.6.2.1 Timer Overflow Interrupt (TOF) Description The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of operation of the TPM system (general purpose timing functions versus center-aligned PWM operation). The flag is cleared by the two step sequence described above. 16.6.2.1.1 Normal Case Normally TOF is set when the timer counter changes from 0xFFFF to 0x0000. When the TPM is not configuredforcenter-alignedPWM(CPWMS=0),TOFgetssetwhenthetimercounterchangesfromthe terminalcount(thevalueinthemoduloregister)to0x0000.Thiscasecorrespondstothenormalmeaning of counter overflow. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 341

Chapter 16 Timer/PWM Module (S08TPMV3) 16.6.2.1.2 Center-Aligned PWM Case When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF corresponds to the end of a PWM period. 16.6.2.2 Channel Event Interrupt Description Themeaningofchannelinterruptsdependsonthechannel’scurrentmode(input-capture,output-compare, edge-aligned PWM, or center-aligned PWM). 16.6.2.2.1 Input Capture Events Whenachannelisconfiguredasaninputcapturechannel,theELSnB:ELSnAcontrolbitsselectnoedge (off),risingedges,fallingedgesoranyedgeastheedgewhichtriggersaninputcaptureevent.Whenthe selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step sequence described inSection16.6.2, “Description of Interrupt Operation.” 16.6.2.2.2 Output Compare Events When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step sequence describedSection16.6.2, “Description of Interrupt Operation.” 16.6.2.2.3 PWM End-of-Duty-Cycle Events For channels configured for PWM operation there are two possibilities. When the channel is configured foredge-alignedPWM,thechannelflaggetssetwhenthetimercountermatchesthechannelvalueregister which marks the end of the active duty cycle period. When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value register. The flag is cleared by the two-step sequence describedSection16.6.2, “Description of Interrupt Operation.” 16.7 The Differences from TPM v2 to TPM v3 1. Write to TPMxCNTH:L registers (Section16.3.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL)) [SE110-TPM case 7] Any write to TPMxCNTH or TPMxCNTL registers in TPM v3 clears the TPM counter (TPMxCNTH:L)andtheprescalercounter.Instead,intheTPMv2onlytheTPMcounteriscleared in this case. 2. Read of TPMxCNTH:L registers (Section16.3.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL)) — In TPM v3, any read of TPMxCNTH:L registers during BDM mode returns the value of the TPM counter that is frozen. In TPM v2, if only one byte of the TPMxCNTH:L registers was read before the BDM mode became active, then any read of TPMxCNTH:L registers during MC9S08DZ60 Series Data Sheet, Rev. 4 342 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the frozen TPM counter value. — This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxSC,TPMxCNTHorTPMxCNTL.Instead,intheseconditionstheTPMv2doesnotclear this read coherency mechanism. 3. Read of TPMxCnVH:L registers (Section16.3.5, “TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)) — In TPM v3, any read of TPMxCnVH:L registers during BDM mode returns the value of the TPMxCnVH:L register. In TPM v2, if only one byte of the TPMxCnVH:L registers was read before the BDM mode became active, then any read of TPMxCnVH:L registers during BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the value in the TPMxCnVH:L registers. — This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxCnSC. Instead, in this condition the TPM v2 does not clear this read coherency mechanism. 4. Write to TPMxCnVH:L registers — Input Capture Mode (Section16.4.2.1, “Input Capture Mode) In this mode the TPM v3 does not allow the writes to TPMxCnVH:L registers. Instead, the TPM v2 allows these writes. — Output Compare Mode (Section16.4.2.2, “Output Compare Mode) In this mode and if (CLKSB:CLKSA not = 0:0), the TPM v3 updates the TPMxCnVH:L registerswiththevalueoftheirwritebufferatthenextchangeoftheTPMcounter(endofthe prescalercounting)afterthesecondbyteiswritten.Instead,theTPMv2alwaysupdatesthese registers when their second byte is written. The following procedure can be used in the TPM v3 to verify if the TPMxCnVH:L registers wereupdatedwiththenewvaluethatwaswrittentotheseregisters(valueintheirwritebuffer). ... write the new value to TPMxCnVH:L; read TPMxCnVH and TPMxCnVL registers; while (the read value of TPMxCnVH:L is different from the new value written to TPMxCnVH:L) begin read again TPMxCnVH and TPMxCnVL; end ... Inthispoint,theTPMxCnVH:Lregisterswereupdated,sotheprogramcancontinueand,for example, write to TPMxC0SC without cancelling the previous write to TPMxCnVH:L registers. — Edge-Aligned PWM (Section16.4.2.3, “Edge-Aligned PWM Mode) In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L registerswiththevalueoftheirwritebufferafterthatthebothbyteswerewrittenandwhenthe MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 343

Chapter 16 Timer/PWM Module (S08TPMV3) TPMcounterchangesfrom(TPMxMODH:L-1)to(TPMxMODH:L).IftheTPMcounteris a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and when the TPM counter changes from TPMxMODH:L to $0000. — Center-Aligned PWM (Section16.4.2.4, “Center-Aligned PWM Mode) In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L registerswiththevalueoftheirwritebufferafterthatthebothbyteswerewrittenandwhenthe TPMcounterchangesfrom(TPMxMODH:L-1)to(TPMxMODH:L).IftheTPMcounteris a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and when the TPM counter changes from TPMxMODH:L to (TPMxMODH:L - 1). 5. Center-Aligned PWM (Section16.4.2.4, “Center-Aligned PWM Mode) — TPMxCnVH:L = TPMxMODH:L [SE110-TPM case 1] In this case, the TPM v3 produces 100% duty cycle. Instead, the TPM v2 produces 0% duty cycle. — TPMxCnVH:L = (TPMxMODH:L - 1) [SE110-TPM case 2] Inthiscase,theTPMv3producesalmost100%dutycycle.Instead,theTPMv2produces0% duty cycle. — TPMxCnVH:L is changed from 0x0000 to a non-zero value [SE110-TPM case 3 and 5] Inthiscase,theTPMv3waitsforthestartofanewPWMperiodtobeginusingthenewduty cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current PWM period (when the count reaches 0x0000). — TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4] In this case, the TPM v3 finishes the current PWM period using the old duty cycle setting. Instead, the TPM v2 finishes the current PWM period using the new duty cycle setting. 6. Write to TPMxMODH:L registers in BDM mode (Section16.3.3, “TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)) In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism ofTPMxMODH:Lregisters.Instead,intheTPMv2thiscoherencymechanismisnotclearedwhen there is a write to TPMxSC register. 7. Update of EPWM signal when CLKSB:CLKSA = 00 IntheTPMv3ifCLKSB:CLKSA=00,thentheEPWMsignalinthechanneloutputisnotupdate (itisfrozenwhileCLKSB:CLKSA=00).Instead,intheTPMv2theEPWMsignalisupdatedat the next rising edge of bus clock after a write to TPMxCnSC register. TheFigure0-1andFigure0-2showwhentheEPWMsignalsgeneratedbyTPMv2andTPMv3 after the reset (CLKSB:CLKSA = 00) and if there is a write to TPMxCnSC register. MC9S08DZ60 Series Data Sheet, Rev. 4 344 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) EPWM mode TPMxMODH:TPMxMODL = 0x0007 TPMxCnVH:TPMxCnVL = 0x0005 RESET (active low) BUS CLOCK TPMxCNTH:TPMxCNTL 0 1 2 3 4 5 6 7 0 1 2 ... CLKSB:CLKSA BITS 00 01 MSnB:MSnA BITS 00 10 ELSnB:ELSnA BITS 00 10 TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3) Figure0-1.Generation of high-true EPWM signal by TPM v2 and v3 after the reset EPWM mode TPMxMODH:TPMxMODL = 0x0007 TPMxCnVH:TPMxCnVL = 0x0005 RESET (active low) BUS CLOCK TPMxCNTH:TPMxCNTL 0 1 2 3 4 5 6 7 0 1 2 ... CLKSB:CLKSA BITS 00 01 MSnB:MSnA BITS 00 10 ELSnB:ELSnA BITS 00 01 TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3) Figure0-2.Generation of low-true EPWM signal by TPM v2 and v3 after the reset ThefollowingprocedurecanbeusedinTPMv3(whenthechannelpinisalsoaportpin)toemulate the high-true EPWM generated by TPM v2 after the reset. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 345

Chapter 16 Timer/PWM Module (S08TPMV3) ... configure the channel pin as output port pin and set the output pin; configure the channel to generate the EPWM signal but keep ELSnB:ELSnA as 00; configure the other registers (TPMxMODH, TPMxMODL, TPMxCnVH, TPMxCnVL, ...); configure CLKSB:CLKSA bits (TPM v3 starts to generate the high-true EPWM signal, however TPM does not control the channel pin, so the EPWM signal is not available); wait until the TOF is set (or use the TOF interrupt); enable the channel output by configuring ELSnB:ELSnA bits (now EPWM signal is available); ... MC9S08DZ60 Series Data Sheet, Rev. 4 346 Freescale Semiconductor

Chapter 17 Development Support 17.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chipFlash and other nonvolatile memories. The BDCisalsotheprimarydebuginterfacefordevelopmentandallowsnon-intrusiveaccesstomemorydata and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. In the HCS08 Family, address and data bus signals are not available on external pins (not even in test modes).DebugisdonethroughcommandsfedintothetargetMCUviathesingle-wirebackgrounddebug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals. 17.1.1 Forcing Active Background The method for forcing active background mode depends on the specific HCS08 derivative. For the MC9S08DZ60,youcanforceactivebackgroundafterapower-onresetbyholdingtheBKGDpinlowas the device exits the reset condition. You can also force active background by driving BKGD low immediatelyafteraserialbackgroundcommandthatwritesaonetotheBDFRbitintheSBDFRregister. If no debug pod is connected to the BKGD pin, the MCU will always reset into normal operating mode. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 347

Chapter 17 Development Support 17.1.2 Features Features of the BDC module include: • Single pin for mode selection and background communications • BDC registers are not located in the memory map • SYNC command to determine target communications rate • Non-intrusive commands for memory access • Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from stop or wait modes • One hardware address breakpoint built into BDC • Oscillator runs in stop mode, if BDC enabled • COP watchdog disabled while in active background mode Features of the ICE system include: • Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W • Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information: — Change-of-flow addresses or — Event-only data • Two types of breakpoints: — Tag breakpoints for instruction opcodes — Force breakpoints for any address access • Nine trigger modes: — Basic: A-only, A OR B — Sequence: A then B — Full: A AND B data, A AND NOT B data — Event (store data): Event-only B, A then event-only B — Range: Inside range (A≤ address≤ B), outside range (address < A or address > B) 17.2 Background Debug Controller (BDC) AllMCUsintheHCS08Familycontainasingle-wirebackgrounddebuginterfacethatsupportsin-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debuginterfacesonearlier8-bitMCUs,thissystemdoesnotinterferewithnormalapplicationresources. It does not use any user memory or locations in the memory map and does not share any on-chip peripherals. BDC commands are divided into two groups: • ActivebackgroundmodecommandsrequirethatthetargetMCUisinactivebackgroundmode(the user program is not running). Active background mode commands allow the CPU registers to be readorwritten,andallowtheusertotraceoneuserinstructionatatime,orGOtotheuserprogram from active background mode. MC9S08DZ60 Series Data Sheet, Rev. 4 348 Freescale Semiconductor

Chapter 17 Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusivecommandsallowausertoreadorwriteMCUmemorylocationsoraccessstatusand control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commandsforthecustomserialinterfacetothesingle-wirebackgrounddebugsystem.Dependingonthe developmenttoolvendor,thisinterfacepodmayuseastandardRS-232serialport,aparallelprinterport, orsomeothertypeofcommunicationssuchasauniversalserialbus(USB)tocommunicatebetweenthe hostPCandthepod.Thepodtypicallyconnectstothetargetsystemwithground,theBKGDpin,RESET, and sometimes V . An open-drain connection to reset allows the host to force a target system reset, DD which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. Sometimes V can be used to allow the pod to use DD powerfromthetargetsystemtoavoidtheneedforaseparatepowersupply.However,ifthepodispowered separately,itcanbeconnectedtoarunningtargetsystemwithoutforcingatargetsystemresetorotherwise disturbing the running application program. BKGD 1 2 GND NO CONNECT 3 4 RESET NO CONNECT 5 6 V DD Figure17-1. BDM Tool Connector 17.2.1 BKGD Pin Description BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectionalserialcommunicationofactivebackgroundmodecommandsanddata.Duringreset,thispin is used to select between starting in active background mode or starting the user’s application program. Thispinisalsousedtorequestatimedsyncresponsepulsetoallowahostdevelopmenttooltodetermine the correct clock frequency for background debug serial communications. BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers.Thisprotocolassumesthehostknowsthecommunicationclockratethatisdetermined by the target BDC clock rate. All communication is initiated and controlled by the host that drives a high-to-lowedgetosignalthebeginningofeachbittime.Commandsanddataaresentmostsignificantbit first (MSB first). For a detailed description of the communications protocol, refer to Section17.2.2, “Communication Details.” IfahostisattemptingtocommunicatewithatargetMCUthathasanunknownBDCclockrate,aSYNC commandmaybesenttothetargetMCUtorequestatimedsyncresponsesignalfromwhichthehostcan determine the correct communication speed. BKGDisapseudo-open-drainpinandthereisanon-chippullupsonoexternalpullupresistorisrequired. Unliketypicalopen-drainpins,theexternalRCtimeconstantonthispin,whichisinfluencedbyexternal capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer toSection17.2.2, “Communication Details,” for more detail. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 349

Chapter 17 Development Support Whennodebuggerpodisconnectedtothe6-pinBDMinterfaceconnector,theinternalpulluponBKGD choosesnormaloperatingmode.WhenadebugpodisconnectedtoBKGDitispossibletoforcetheMCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not necessary to reset the target MCU to communicate with it through the background debug interface. 17.2.2 Communication Details The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGDisapseudo-open-drainpinthatcanbedriveneitherbyanexternalcontrollerorbytheMCU.Data is transferred MSB first at 16BDC clock cycles per bit (nominal speed). The interface times out if 512BDCclockcyclesoccurbetweenfallingedgesfromthehost.AnyBDCcommandthatwasinprogress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. Theclockswitch(CLKSW)controlbitintheBDCstatusandcontrolregisterallowstheusertoselectthe BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source. The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronoustotheexternalhost.TheinternalBDCclocksignalisshownforreferenceincountingcycles. MC9S08DZ60 Series Data Sheet, Rev. 4 350 Freescale Semiconductor

Chapter 17 Development Support Figure17-2showsanexternalhosttransmittingalogic1or0totheBKGDpinofatargetHCS08MCU. Thehostisasynchronoustothetargetsothereisa0-to-1cycledelayfromthehost-generatedfallingedge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target sensesthebitlevelontheBKGDpin.Typically,thehostactivelydrivesthepseudo-open-drainBKGDpin duringhost-to-targettransmissionstospeeduprisingedges.BecausethetargetdoesnotdrivetheBKGD pinduringthehost-to-targettransmissionperiod,thereisnoneedtotreatthelineasanopen-drainsignal during this period. BDC CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES EARLIEST START OF NEXT BIT SYNCHRONIZATION TARGET SENSES BIT LEVEL UNCERTAINTY PERCEIVED START OF BIT TIME Figure17-2. BDC Host-to-Target Serial Bit Timing MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 351

Chapter 17 Development Support Figure17-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enoughforthetargettorecognizeit(atleasttwotargetBDCcycles).Thehostmustreleasethelowdrive beforethetargetMCUdrivesabriefactive-highspeeduppulsesevencyclesaftertheperceivedstartofthe bit time. The host should sample the bit level about 10cycles after it started the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure17-3. BDC Target-to-Host Serial Bit Timing (Logic 1) MC9S08DZ60 Series Data Sheet, Rev. 4 352 Freescale Semiconductor

Chapter 17 Development Support Figure17-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the targetHCS08finishesit.Becausethetargetwantsthehosttoreceivealogic0,itdrivestheBKGDpinlow for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE HIGH-IMPEDANCE TO BKGD PIN SPEEDUP TARGET MCU PULSE DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure17-4. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 353

Chapter 17 Development Support 17.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commandsanddataaresentMSB-firstusingacustomBDCcommunicationsprotocol.Activebackground mode commands require that the target MCU is currently in the active background mode while non-intrusivecommandsmaybeissuedatanytimewhetherthetargetMCUisinactivebackgroundmode or running a user application program. Table17-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used inTable17-1 to describe the coding structure of the BDC commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) / = separates parts of the command d = delay 16 target BDC clock cycles AAAA = a 16-bit address in the host-to-target direction RD = 8 bits of read data in the target-to-host direction WD = 8 bits of write data in the host-to-target direction RD16 = 16 bits of read data in the target-to-host direction WD16 = 16 bits of write data in the host-to-target direction SS = the contents of BDCSCR in the target-to-host direction (STATUS) CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP = 16bitsofwritedatainthehost-to-targetdirection(forBDCBKPTbreakpointregister) MC9S08DZ60 Series Data Sheet, Rev. 4 354 Freescale Semiconductor

Chapter 17 Development Support Table17-1. BDC Command Summary Command Active BDM/ Coding Description Mnemonic Non-intrusive Structure Request a timed reference pulse to determine SYNC Non-intrusive n/a1 target BDC communication speed Enable acknowledge protocol. Refer to ACK_ENABLE Non-intrusive D5/d Freescale document order no. HCS08RMv1/D. Disable acknowledge protocol. Refer to ACK_DISABLE Non-intrusive D6/d Freescale document order no. HCS08RMv1/D. Enter active background mode if enabled BACKGROUND Non-intrusive 90/d (ignore if ENBDM bit equals 0) READ_STATUS Non-intrusive E4/SS Read BDC status from BDCSCR WRITE_CONTROL Non-intrusive C4/CC Write BDC controls in BDCSCR READ_BYTE Non-intrusive E0/AAAA/d/RD Read a byte from target memory READ_BYTE_WS Non-intrusive E1/AAAA/d/SS/RD Read a byte and report status Re-read byte from address just read and READ_LAST Non-intrusive E8/SS/RD report status WRITE_BYTE Non-intrusive C0/AAAA/WD/d Write a byte to target memory WRITE_BYTE_WS Non-intrusive C1/AAAA/WD/d/SS Write a byte and report status READ_BKPT Non-intrusive E2/RBKP Read BDCBKPT breakpoint register WRITE_BKPT Non-intrusive C2/WBKP Write BDCBKPT breakpoint register Go to execute the user application program GO Active BDM 08/d starting at the address currently in the PC Trace 1 user instruction at the address in the TRACE1 Active BDM 10/d PC, then return to active background mode Same as GO but enable external tagging TAGGO Active BDM 18/d (HCS08 devices have no external tagging pin) READ_A Active BDM 68/d/RD Read accumulator (A) READ_CCR Active BDM 69/d/RD Read condition code register (CCR) READ_PC Active BDM 6B/d/RD16 Read program counter (PC) READ_HX Active BDM 6C/d/RD16 Read H and X register pair (H:X) READ_SP Active BDM 6F/d/RD16 Read stack pointer (SP) Increment H:X by one then read memory byte READ_NEXT Active BDM 70/d/RD located at H:X Increment H:X by one then read memory byte READ_NEXT_WS Active BDM 71/d/SS/RD located at H:X. Report status and data. WRITE_A Active BDM 48/WD/d Write accumulator (A) WRITE_CCR Active BDM 49/WD/d Write condition code register (CCR) WRITE_PC Active BDM 4B/WD16/d Write program counter (PC) WRITE_HX Active BDM 4C/WD16/d Write H and X register pair (H:X) WRITE_SP Active BDM 4F/WD16/d Write stack pointer (SP) IncrementH:Xbyone,thenwritememorybyte WRITE_NEXT Active BDM 50/WD/d located at H:X IncrementH:Xbyone,thenwritememorybyte WRITE_NEXT_WS Active BDM 51/WD/d/SS located at H:X. Also report status. 1 The SYNC command is a special operation that does not have a command code. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 355

Chapter 17 Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correctcommunicationsspeedtouseforBDCcommunicationsuntilafterithasanalyzedtheresponseto the SYNC command. To issue a SYNC command, the host: • DrivestheBKGDpinlowforatleast128cyclesoftheslowestpossibleBDCclock(Theslowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) • DrivesBKGDhighforabriefspeeduppulsetogetafastrisetime(Thisspeeduppulseistypically one cycle of the fastest clock in the system.) • Removes all drive to the BKGD pin so it reverts to high impedance • Monitors the BKGD pin for the sync response pulse Thetarget,upondetectingtheSYNCrequestfromthehost(whichisamuchlongerlowtimethanwould ever occur during normal BDC communications): • Waits for BKGD to return to a logic high • Delays 16cycles to allow the host to stop driving the high speedup pulse • Drives BKGD low for 128BDC clock cycles • Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD • Removes all drive to the BKGD pin so it reverts to high impedance Thehostmeasuresthelowtimeofthis128-cyclesyncresponsepulseanddeterminesthecorrectspeedfor subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 17.2.4 BDC Hardware Breakpoint The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bitmatchvalueintheBDCBKPTregister.Thisbreakpointcangenerateaforcedbreakpointoratagged breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies that taggedbreakpointscanonlybeplacedattheaddressofaninstructionopcodewhileforcedbreakpointscan be set at any address. Thebreakpointenable(BKPTEN)controlbitintheBDCstatusandcontrolregister(BDCSCR)isusedto enable the breakpoint logic (BKPTEN=1). When BKPTEN=0, its default value after reset, the breakpointlogicisdisabledandnoBDCbreakpointsarerequestedregardlessofthevaluesinotherBDC breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS=1) or tagged (FTS=0) type breakpoints. Theon-chipdebugmodule(DBG)includescircuitryfortwoadditionalhardwarebreakpointsthataremore flexible than the simple breakpoint in the BDC module. MC9S08DZ60 Series Data Sheet, Rev. 4 356 Freescale Semiconductor

Chapter 17 Development Support 17.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuitemulatorhavebeenbuiltontothechipwiththeMCU.Thedebugsystemconsistsofan8-stage FIFOthatcanstoreaddressordatabusinformation,andaflexibletriggersystemtodecidewhentocapture businformationandwhatinformationtocapture.Thesystemreliesonthesingle-wirebackgrounddebug system to access debug control registers and to read results out of the eight stage FIFO. The debug module includes control and status registers that are accessible in the user’s memory map. These registers are located in the high register space to avoid using valuable direct page memory space. Mostofthedebugmodule’sfunctionsareusedduringdevelopment,anduserprogramsrarelyaccessany of the control and status registers for the debug module. The one exception is that the debug system can provide the means to implement a form of ROM patching. This topic is discussed in greater detail in Section17.3.6, “Hardware Breakpoints.” 17.3.1 Comparators A and B Two16-bitcomparators(AandB)canoptionallybequalifiedwiththeR/Wsignalandanopcodetracking circuit.SeparatecontrolbitsallowyoutoignoreR/Wforeachcomparator.Theopcodetrackingcircuitry optionally allows you to specify that a trigger will occur only if the opcode at the specified address is actuallyexecutedasopposedtoonlybeingreadfrommemoryintotheinstructionqueue.Thecomparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. Comparators are disabled temporarily during all BDC accesses. The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an additional purpose, in full address plus data comparisons they are used to decide which of these buses to useinthecomparatorBdatabuscomparisons.IfRWAEN=1(enabled)andRWA=0(write),theCPU’s write data bus is used. Otherwise, the CPU’s read data bus is used. Thecurrentlyselectedtriggermodedetermineswhatthedebuggerlogicdoeswhenacomparatordetects a qualified match condition. A match can cause: • Generation of a breakpoint to the CPU • Storage of data bus values into the FIFO • Starting to store change-of-flow addresses into the FIFO (begin type trace) • Stopping the storage of change-of-flow addresses into the FIFO (end type trace) 17.3.2 Bus Capture Information and FIFO Operation The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of wordsofvalidinformationthatareintheFIFOasdataisstoredintoit.Ifatracerunismanuallyhaltedby writing0toARMbeforetheFIFOisfull(CNT=1:0:0:0),theinformationisshiftedbyonepositionand MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 357

Chapter 17 Development Support thehostmustperform((8–CNT)–1)dummyreadsoftheFIFOtoadvanceittothefirstsignificantentry in the FIFO. Inmosttriggermodes,theinformationstoredintheFIFOconsistsof16-bitchange-of-flowaddresses.In thesecases,readDBGFHthenDBGFLtogetonecoherentwordofinformationoutoftheFIFO.Reading DBGFL(thelow-orderbyteoftheFIFOdataport)causestheFIFOtoshiftsothenextwordofinformation isavailableattheFIFOdataport.Intheevent-onlytriggermodes(seeSection17.3.5,“TriggerModes”), 8-bitdatainformationisstoredintotheFIFO.Inthesecases,thehigh-orderhalfoftheFIFO(DBGFH)is notusedanddataisreadoutoftheFIFObysimplyreadingDBGFL.EachtimeDBGFLisread,theFIFO is shifted so the next data value is available through the FIFO data port at DBGFL. In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU addressesandtheinputsideoftheFIFO.Becauseofthisdelay,ifthetriggereventitselfisachange-of-flow addressorachange-of-flowaddressappearsduringthenexttwobuscyclesafteratriggereventstartsthe FIFO,itwillnotbesavedintotheFIFO.Inthecaseofanend-trace,ifthetriggereventisachange-of-flow, it will be saved as the last change-of-flow entry for that debug run. TheFIFOcanalsobeusedtogenerateaprofileofexecutedinstructionaddresseswhenthedebuggerisnot armed. When ARM=0, reading DBGFL causes the address of the most-recently fetched opcode to be savedintheFIFO.Tousetheprofilingfeature,ahostdebuggerwouldreadaddressesoutoftheFIFOby reading DBGFH then DBGFL at regular periodic intervals. The first eight values would be discarded because they correspond to the eight DBGFL reads needed to initially fill the FIFO. Additional periodic readsofDBGFHandDBGFLreturndelayedinformationaboutexecutedinstructionssothehostdebugger can develop a profile of executed instruction addresses. 17.3.3 Change-of-Flow Information To minimize the amount of information stored in the FIFO, only information related to instructions that causeachangetothenormalsequentialexecutionofinstructionsisstored.Withknowledgeofthesource andobjectcodeprogramstoredinthetargetsystem,anexternaldebuggersystemcanreconstructthepath of execution through many instructions from the change-of-flow information stored in the FIFO. For conditional branch instructions where the branch is taken (branch condition was true), the source addressisstored(theaddressoftheconditionalbranchopcode).BecauseBRAandBRNinstructionsare not conditional, these events do not cause change-of-flow information to be stored in the FIFO. IndirectJMPandJSRinstructionsusethecurrentcontentsoftheH:Xindexregisterpairtodeterminethe destination address, so the debug system stores the run-time destination address for any indirect JMP or JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-flow information. 17.3.4 Tag vs. Force Breakpoints and Triggers Taggingisatermthatreferstoidentifyinganinstructionopcodeasitisfetchedintotheinstructionqueue, but not taking any other action until and unless that instruction is actually executed by the CPU. This distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt causessomeinstructionsthathavebeenfetchedintotheinstructionqueuetobethrownawaywithoutbeing executed. MC9S08DZ60 Series Data Sheet, Rev. 4 358 Freescale Semiconductor

Chapter 17 Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. Thetagvs.forceterminologyisusedintwocontextswithinthedebugmodule.Thefirstcontextrefersto breakpoint requests from the debug module to the CPU. The second refers to match signals from the comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is enteredintotheinstructionqueuealongwiththeopcodesothatif/whenthisopcodeeverexecutes,theCPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active background moderatherthanexecutingthetaggedinstruction.WhentheTRGSELcontrolbitintheDBGTregisteris set to select tag-type operation, the output from comparator A or B is qualified by a block of logic in the debugmodulethattracksopcodesandonlyproducesatriggertothedebuggeriftheopcodeatthecompare addressisactuallyexecuted.Thereisseparateopcodetrackinglogicforeachcomparatorsomorethanone compare event can be tracked through the instruction queue at a time. 17.3.5 Trigger Modes Thetriggermodecontrolstheoverallbehaviorofadebugrun.The4-bitTRGfieldintheDBGTregister selectsoneofninetriggermodes.WhenTRGSEL=1intheDBGTregister,theoutputofthecomparator must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in DBGTchooseswhethertheFIFObeginsstoringdatawhenthequalifiedtriggerisdetected(begintrace), ortheFIFOstoresdatainacircularfashionfromthetimeitisarmeduntilthequalifiedtriggerisdetected (end trigger). Adebugrunisstartedbywritinga1totheARMbitintheDBGCregister,whichsetstheARMFflagand clearstheAFandBFflagsandtheCNTbitsinDBGS.Abegin-tracedebugrunendswhentheFIFOgets full.Anend-tracerunendswhentheselectedtriggereventoccurs.Anydebugruncanbestoppedmanually by writing a 0 to ARM or DBGEN in DBGC. In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only trigger modes, the FIFO stores data in the low-order eight bits of the FIFO. The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type traces.WhenTRGSEL=1toselectopcodefetchtriggers,itisnotnecessarytouseR/Wincomparisons because opcode tags would only apply to opcode fetches that are always read cycles. It would also be unusual to specify TRGSEL=1 while using a full mode trigger because the opcode value is normally known at a particular address. Thefollowingtriggermodedescriptionsonlystatetheprimarycomparatorconditionsthatleadtoatrigger. Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and the corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with optional R/W qualification is used to request a CPU breakpoint if BRKEN=1 and TAG determines whether the CPU request will be a tag request or a force request. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 359

Chapter 17 Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparatorB A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally) mustmatchwithinthesamebuscycletocauseatriggerevent.ComparatorAchecksaddress,thelowbyte of comparator B checks data, and R/W is checked against RWA if RWAEN=1. The high-order half of comparator B is not used. Infulltriggermodesitisnotusefultospecifyatag-typeCPUbreakpoint(BRKEN=TAG=1),butifyou do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low halfofcomparatorB,andR/WmustmatchRWAifRWAEN=1.Allthreeconditionsmustbemetwithin the same bus cycle to cause a trigger. Infulltriggermodesitisnotusefultospecifyatag-typeCPUbreakpoint(BRKEN=TAG=1),butifyou do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. Event-Only B (Store Data) — Trigger events occur each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. AThenEvent-OnlyB(StoreData)—AftertheaddresshasmatchedthevalueincomparatorA,atrigger eventoccurseachtimetheaddressmatchesthevalueincomparatorB.Triggereventscausethedatatobe captured into the FIFO. The debug run ends when the FIFO becomes full. InsideRange(A≤Address≤B)—Atriggeroccurswhentheaddressisgreaterthanorequaltothevalue in comparator A and less than or equal to the value in comparator B at the same time. Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than the value in comparator A or greater than the value in comparator B. MC9S08DZ60 Series Data Sheet, Rev. 4 360 Freescale Semiconductor

Chapter 17 Development Support 17.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions describedinSection17.3.5,“TriggerModes,”tobeusedtogenerateahardwarebreakpointrequesttothe CPU.TAGinDBGCcontrolswhetherthebreakpointrequestwillbetreatedasatag-typebreakpointora force-typebreakpoint.Atagbreakpointcausesthecurrentopcodetobemarkedasitenterstheinstruction queue.Ifataggedopcodereachestheendofthepipe,theCPUexecutesaBGNDinstructiontogotoactive background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to finish the current instruction and then go to active background mode. If the background mode has not been enabled (ENBDM=1) by a serial WRITE_CONTROL command through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background mode. 17.4 Register Definition This section contains the descriptions of the BDC and DBG registers and control bits. Refertothehigh-pageregistersummaryinthedeviceoverviewchapterofthisdatasheetfortheabsolute address assignments for all DBG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 17.4.1 BDC Registers and Control Bits The BDC has two registers: • The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller. • The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address. These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU (so they do not have addresses and cannot be accessed by user programs). SomeofthebitsintheBDCSCRhavewritelimitations;otherwise,theseregistersmaybereadorwritten at any time. For example, the ENBDM control bit may not be written while the MCU is in active backgroundmode.(Thispreventstheambiguousconditionofthecontrolbitforbiddingactivebackground mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS, WSF,andDVF)areread-onlystatusindicatorsandcanneverbewrittenbytheWRITE_CONTROLserial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 361

Chapter 17 Development Support 17.4.1.1 BDC Status and Control Register (BDCSCR) ThisregistercanbereadorwrittenbyserialBDCcommands(READ_STATUSandWRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 6 5 4 3 2 1 0 R BDMACT WS WSF DVF ENBDM BKPTEN FTS CLKSW W Normal 0 0 0 0 0 0 0 0 Reset Reset in 1 1 0 0 1 0 0 0 Active BDM: = Unimplemented or Reserved Figure17-5. BDC Status and Control Register (BDCSCR) Table17-2. BDCSCR Register Field Descriptions Field Description 7 Enable BDM (Permit Active Background Mode)— Typically, this bit is written to 1 by the debug host shortly ENBDM afterthebeginningofadebugsessionorwheneverthedebughostresetsthetargetandremains1untilanormal reset clears it. 0 BDM cannot be made active (non-intrusive commands still allowed) 1 BDM can be made active to allow active background mode commands 6 Background Mode Active Status — This is a read-only status bit. BDMACT 0 BDM not active (user application program running) 1 BDM active and waiting for serial commands 5 BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) BKPTEN control bit and BDCBKPT match register are ignored. 0 BDC breakpoint disabled 1 BDC breakpoint enabled 4 Force/Tag Select — When FTS=1, a breakpoint is requested whenever the CPU address bus matches the FTS BDCBKPT match register. When FTS=0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters active background mode rather than executing the tagged opcode. 0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that instruction 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC CLKSW clock source. 0 Alternate BDC clock source 1 MCU bus clock MC9S08DZ60 Series Data Sheet, Rev. 4 362 Freescale Semiconductor

Chapter 17 Development Support Table17-2. BDCSCR Register Field Descriptions (continued) Field Description 2 Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. WS However,theBACKGROUNDcommandcanbeusedtoforcethetargetCPUoutofwaitorstopandintoactive background mode where all BDC commands work. Whenever the host forces the target MCU into active background mode, the host should issue a READ_STATUS command to check that BDMACT=1 before attempting other BDC commands. 0 TargetCPUisrunninguserapplicationcodeorinactivebackgroundmode(wasnotinwaitorstopmodewhen background became active) 1 TargetCPUisinwaitorstopmode,oraBACKGROUNDcommandwasusedtochangefromwaitorstopto active background mode 1 WaitorStopFailureStatus—ThisstatusbitissetifamemoryaccesscommandfailedduetothetargetCPU WSF executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command thatfailed,thenreturntotheuserprogram.(Typically,thehostwouldrestoreCPUregistersandstackvaluesand re-execute the wait or stop instruction.) 0 Memory access did not conflict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode 0 Data Valid Failure Status — This status bit is not used in the MC9S08DZ60 Series because it does not have DVF any slow access memory. 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a slow memory access 17.4.1.2 BDC Breakpoint Match Register (BDCBKPT) This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal memory map of the MCU. BreakpointsarenormallysetwhilethetargetMCUisinactivebackgroundmodebeforerunningtheuser application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer toSection17.2.4, “BDC Hardware Breakpoint.” 17.4.2 System Background Debug Force Reset Register (SBDFR) This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTEmustbeusedtowritetoSBDFR.Attemptstowritethisregisterfromauserprogramare ignored. Reads always return 0x00. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 363

Chapter 17 Development Support 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W BDFR1 Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure17-6. System Background Debug Force Reset Register (SBDFR) Table17-3. SBDFR Register Field Description Field Description 0 BackgroundDebugForceReset—AserialactivebackgroundmodecommandsuchasWRITE_BYTEallows BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. 17.4.3 DBG Registers and Control Bits The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers. These registers are located in the high register space of the normal memory map so theyareaccessibletonormalapplicationprograms.Theseregistersarerarelyifeveraccessedbynormal user application programs with the possible exception of a ROM patching mechanism that uses the breakpoint logic. 17.4.3.1 Debug Comparator A High Register (DBGCAH) This register contains compare value bits for the high-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.2 Debug Comparator A Low Register (DBGCAL) This register contains compare value bits for the low-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.3 Debug Comparator B High Register (DBGCBH) This register contains compare value bits for the high-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.4 Debug Comparator B Low Register (DBGCBL) This register contains compare value bits for the low-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. MC9S08DZ60 Series Data Sheet, Rev. 4 364 Freescale Semiconductor

Chapter 17 Development Support 17.4.3.5 Debug FIFO High Register (DBGFH) Thisregisterprovidesread-onlyaccesstothehigh-ordereightbitsoftheFIFO.Writestothisregisterhave nomeaningoreffect.Intheevent-onlytriggermodes,theFIFOonlystoresdataintothelow-orderbyteof each FIFO word, so this register is not used and will read 0x00. ReadingDBGFHdoesnotcausetheFIFOtoshifttothenextword.Whenreading16-bitwordsoutofthe FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the next word of information. 17.4.3.6 Debug FIFO Low Register (DBGFL) Thisregisterprovidesread-onlyaccesstothelow-ordereightbitsoftheFIFO.Writestothisregisterhave no meaning or effect. Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each FIFOwordisunused).Whenreading8-bitwordsoutoftheFIFO,simplyreadDBGFLrepeatedlytoget successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case. DonotattempttoreaddatafromtheFIFOwhileitisstillarmed(afterarmingbutbeforetheFIFOisfilled or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can interfere with normal sequencing of reads from the FIFO. ReadingDBGFLwhilethedebuggerisnotarmedcausestheaddressofthemost-recentlyfetchedopcode tobestoredtothelastlocationintheFIFO.ByreadingDBGFHthenDBGFLperiodically,externalhost softwarecandevelopaprofileofprogramexecution.AftereightreadsfromtheFIFO,theninthreadwill returntheinformationthatwasstoredasaresultofthefirstread.Tousetheprofilingfeature,readtheFIFO eight times without using the data to prime the sequence and then begin using the data to get a delayed pictureofwhataddresseswerebeingexecuted.TheinformationstoredintotheFIFOonreadsofDBGFL (while the FIFO is not armed) is the address of the most-recently fetched opcode. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 365

Chapter 17 Development Support 17.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN W Reset 0 0 0 0 0 0 0 0 Figure17-7. Debug Control Register (DBGC) Table17-4. DBGC Register Field Descriptions Field Description 7 Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure. DBGEN 0 DBG disabled 1 DBG enabled 6 ArmControl—ControlswhetherthedebuggeriscomparingandstoringinformationintheFIFO.Awriteisused ARM tosetthisbit(andARMF)andcompletionofadebugrunautomaticallyclearsit.Anydebugruncanbemanually stopped by writing 0 to ARM or to DBGEN. 0 Debugger not armed 1 Debugger armed 5 Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If TAG BRKEN=0, this bit has no meaning or effect. 0 CPU breaks requested as force type requests 1 CPU breaks requested as tag type requests 4 BreakEnable—ControlswhetheratriggereventwillgenerateabreakrequesttotheCPU.Triggereventscan BRKEN causeinformationtobestoredintheFIFOwithoutgeneratingabreakrequesttotheCPU.Foranendtrace,CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a begintrace,CPUbreakrequestsareissuedwhentheFIFObecomesfull.TRGSELdoesnotaffectthetimingof CPU break requests. 0 CPU break requests not enabled 1 Triggers cause a break request to the CPU 3 R/WComparisonValueforComparatorA—WhenRWAEN=1,thisbitdetermineswhetherareadorawrite RWA access qualifies comparator A. When RWAEN=0, RWA and the R/W signal do not affect comparator A. 0 Comparator A can only match on a write cycle 1 Comparator A can only match on a read cycle 2 Enable R/W for Comparator A— Controls whether the level of R/W is considered for a comparator A match. RWAEN 0 R/W is not used in comparison A 1 R/W is used in comparison A 1 R/WComparisonValueforComparatorB—WhenRWBEN=1,thisbitdetermineswhetherareadorawrite RWB access qualifies comparator B. When RWBEN=0, RWB and the R/W signal do not affect comparator B. 0 Comparator B can match only on a write cycle 1 Comparator B can match only on a read cycle 0 Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match. RWBEN 0 R/W is not used in comparison B 1 R/W is used in comparison B MC9S08DZ60 Series Data Sheet, Rev. 4 366 Freescale Semiconductor

Chapter 17 Development Support 17.4.3.8 Debug Trigger Register (DBGT) Thisregistercanbereadanytime,butmaybewrittenonlyifARM=0,exceptbits4and5arehard-wired to 0s. 7 6 5 4 3 2 1 0 R 0 0 TRGSEL BEGIN TRG3 TRG2 TRG1 TRG0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure17-8. Debug Trigger Register (DBGT) Table17-5. DBGT Register Field Descriptions Field Description 7 Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode TRGSEL tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate throughtheopcodetrackinglogicandatriggereventisonlysignalledtotheFIFOlogiciftheopcodeatthematch address is actually executed. 0 Trigger on access to compare address (force) 1 Trigger if opcode at compare address is executed (tag) 6 Begin/EndTriggerSelect—ControlswhethertheFIFOstartsfillingatatriggerorfillsinacircularmanneruntil BEGIN a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 Data stored in FIFO until trigger (end trace) 1 Trigger initiates data storage (begin trace) 3:0 Select Trigger Mode — Selects one of nine triggering modes, as described below. TRG[3:0] 0000 A-only 0001 A OR B 0010 A Then B 0011 Event-only B (store data) 0100 A then event-only B (store data) 0101 A AND B data (full mode) 0110 A AND NOT B data (full mode) 0111 Inside range: A≤ address≤ B 1000 Outside range: address < A or address > B 1001 – 1111 (No trigger) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 367

Chapter 17 Development Support 17.4.3.9 Debug Status Register (DBGS) This is a read-only status register. 7 6 5 4 3 2 1 0 R AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure17-9. Debug Status Register (DBGS) Table17-6. DBGS Register Field Descriptions Field Description 7 Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A AF condition was met since arming. 0 Comparator A has not matched 1 Comparator A match 6 Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B BF condition was met since arming. 0 Comparator B has not matched 1 Comparator B match 5 ArmFlag—WhileDBGEN=1,thisstatusbitisaread-onlyimageofARMinDBGC.Thisbitissetbywriting1 ARMF to the ARM control bit in DBGC (while DBGEN=1) and is automatically cleared at the end of a debug run. A debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC. 0 Debugger not armed 1 Debugger armed 3:0 FIFOValidCount—Thesebitsareclearedatthestartofadebugrunandindicatethenumberofwordsofvalid CNT[3:0] dataintheFIFOattheendofadebugrun.ThevalueinCNTdoesnotdecrementasdataisreadoutoftheFIFO. The external debug host is responsible for keeping track of the count as information is read out of the FIFO. 0000 Number of valid words in FIFO = No valid data 0001 Number of valid words in FIFO = 1 0010 Number of valid words in FIFO = 2 0011 Number of valid words in FIFO = 3 0100 Number of valid words in FIFO = 4 0101 Number of valid words in FIFO = 5 0110 Number of valid words in FIFO = 6 0111 Number of valid words in FIFO = 7 1000 Number of valid words in FIFO = 8 MC9S08DZ60 Series Data Sheet, Rev. 4 368 Freescale Semiconductor

Appendix A Electrical Characteristics A.1 Introduction ThissectioncontainsthemostaccurateelectricalandtiminginformationfortheMC9S08DZ60Seriesof microcontrollers available at the time of publication. A.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: TableA-1. Parameter Classifications P Thoseparametersareguaranteedduringproductiontestingoneachindividualdevice. Those parameters are achieved by the design characterization by measuring a C statistically relevant sample size across process variations. Thoseparametersareachievedbydesigncharacterizationonasmallsamplesizefrom T typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. A.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in TableA-2 may affect device reliability or cause permanentdamagetothedevice.Forfunctionaloperatingconditions,refertotheremainingtablesinthis section. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 369

AppendixA Electrical Characteristics This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V or V ). SS DD TableA-2. Absolute Maximum Ratings Num Rating Symbol Value Unit 1 Supply voltage V –0.3 to + 5.8 V DD 2 Input voltage V – 0.3 to V + 0.3 V In DD Instantaneous maximum current Single pin limit 3 (applies to all port pins)1,2,3 ID ± 25 mA 4 Maximum current into V I 120 mA DD DD 5 Storage temperature Tstg –55 to +150 °C 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (V ) and negative (V ) clamp DD SS voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V and V . SS DD 3 PowersupplymustmaintainregulationwithinoperatingV rangeduringinstantaneousandoperating DD maximum current conditions. If positive injection current (V > V ) is greater than I , the injection In DD DD current may flow out of V and could result in external power supply going out of regulation. Ensure DD external V load will shunt current greater than maximum injection current. This will be the greatest DD riskwhentheMCUisnotconsumingpower.Examplesare:ifnosystemclockispresent,oriftheclock rate is very low which would reduce overall power consumption. A.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take P into account in power calculations, determine the difference between actual pin voltage and V or I/O SS V andmultiplybythepincurrentforeachI/Opin.Exceptincasesofunusuallyhighpincurrent(heavy DD loads), the difference between pin voltage and V or V will be very small. SS DD MC9S08DZ60 Series Data Sheet, Rev. 4 370 Freescale Semiconductor

AppendixA Electrical Characteristics TableA-3. Thermal Characteristics Temp. Num C Rating Symbol Value Unit Code 1 D –40 to 125 M Operating temperature range (packaged) TA –40 to 105 °C V –40 to 85 C 2 T Maximum Junction Temperature1 TJ 135 °C — 3 D Thermal resistance2 Single-layer board 64-pin LQFP θJA 69 °C/W 48-pin LQFP θJA 75 °C/W 32-pin LQFP θJA 80 °C/W Four-Layer board 64-pin LQFP θJA 51 °C/W 48-pin LQFP θJA 51 °C/W 32-pin LQFP θJA 52 °C/W 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection The average chip-junction temperature (T ) in°C can be obtained from: J T = T + (P ×θ ) Eqn.A-1 J A D JA where: T = Ambient temperature,°C A θ = Package thermal resistance, junction-to-ambient,°C/W JA P = P +P D int I/O P = I × V , Watts — chip internal power int DD DD P = Power dissipation on input and output pins — user determined I/O Formostapplications,P <<P andcanbeneglected.AnapproximaterelationshipbetweenP andT I/O int D J (if P is neglected) is: I/O P = K÷ (T + 273°C) Eqn.A-2 D J Solving equations 1 and 2 for K gives: K = P × (T + 273°C) +θ × (P )2 Eqn.A-3 D A JA D MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 371

AppendixA Electrical Characteristics whereKisaconstantpertainingtotheparticularpart.Kcanbedeterminedfromequation3bymeasuring P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by D A D J solving equations 1 and 2 iteratively for any value of T . A A.5 ESD Protection and Latch-Up Immunity Althoughdamagefromelectrostaticdischarge(ESD)ismuchlesscommononthesedevicesthanonearly CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualificationtestsareperformedtoensurethatthesedevicescanwithstandexposuretoreasonablelevels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM) and the Charge Device Model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. TableA-4. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Ω Series Resistance R1 1500 Human Body Storage Capacitance C 100 pF Number of Pulse per pin – 3 Minimum input voltage limit –2.5 V Latch-up Maximum input voltage limit 7.5 V TableA-5. ESD and Latch-Up Protection Characteristics Num Rating Symbol Min Max Unit 1 Human Body Model (HBM) VHBM +/- 2000 – V 2 Charge Device Model (CDM) VCDM +/- 500 – V 3 Latch-up Current at TA = 125°C ILAT +/- 100 – mA MC9S08DZ60 Series Data Sheet, Rev. 4 372 Freescale Semiconductor

AppendixA Electrical Characteristics A.6 DC Characteristics This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. TableA-6. DC Characteristics Num C Characteristic Symbol Condition Min Typ1 Max Unit 1 — Operating Voltage V 2.7 — 5.5 V DD P All I/O pins, low-drive strength 5 V, I = –2 mA V – 1.5 — — Load DD C 3 V, I = –0.6 mA V – 1.5 — — Load DD C Outputhigh 5 V, I = –0.4 mA V – 0.8 — — Load DD voltage 2 C V 3 V, I = –0.24 mA V – 0.8 — — V OH Load DD P All I/O pins, high-drive strength 5 V, I = –10 mA V – 1.5 — — Load DD C 3 V, I = –3 mA V – 1.5 — — Load DD C 5 V, I = –2 mA V – 0.8 — — Load DD C 3 V, I = –0.4 mA V – 0.8 — — Load DD 3 C Output MaxtotalI forallports I 5 V 0 — -100 mA OH OHT high current 3 V 0 — -60 P All I/O pins, low-drive strength 5 V, I = 2 mA — — 1.5 Load C 3 V, I = 0.6 mA — — 1.5 Load C Output low 5 V, I = 0.4 mA — — 0.8 Load voltage 4 C V 3 V, I = 0.24 mA — — 0.8 V OL Load P All I/O pins, high-drive strength 5 V, I = 10 mA — — 1.5 Load C 3 V, I = 3 mA — — 1.5 Load C 5 V, I = 2 mA — — 0.8 Load C 3 V, I = 0.4 mA — — 0.8 Load 5 C Output Max total I for all ports I 5 V 0 — 100 mA OL OLT low current 3 V 0 — 60 6 C Input high voltage; all digital inputs V 5V 0.65 x V — — IH DD V 7 C Input low voltage; all digital inputs V 5V — — 0.35 x V IL DD 8 C Input hysteresis V 0.06 x V mV hys DD Input leakage V = V or V — 0.1 1 μA | | In DD SS 9 P current (Per pin) I In all input only pins Hi-Z (off-state) leakage V = V or V — 0.1 1 μA | | In DD SS current (per pin) I 10 P OZ all input/output Pullup resistors (or Pulldown2 resistors R , 5 V 20 45 65 P PU 11 when enabled) RPD kΩ C 3 V 20 45 65 Input Capacitance, all pins 12 T C — — 8 pF In 13 D RAM retention voltage V — 0.6 1.0 V RAM MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 373

AppendixA Electrical Characteristics TableA-6. DC Characteristics (continued) Num C Characteristic Symbol Condition Min Typ1 Max Unit 14 D POR re-arm voltage3 V 0.9 1.4 2.0 V POR 15 D POR re-arm time4 t 10 — — μs POR Low-voltage detection threshold — high range V 16 P LVD1 V falling 3.9 4.0 4.1 V DD V rising 4.0 4.1 4.2 DD Low-voltage detection threshold — low range V 17 P LVD0 V falling 2.48 2.56 2.64 V DD V rising 2.54 2.62 2.70 DD Low-voltage warning threshold — high range 1 V 18 C LVW3 V falling 4.5 4.6 4.7 V DD V rising 4.6 4.7 4.8 DD Low-voltage warning threshold — high range 0 V 19 P LVW2 V falling 4.2 4.3 4.4 V DD V rising 4.3 4.4 4.5 DD Low-voltage warning threshold low range 1 V 20 P LVW1 V falling 2.84 2.92 3.00 V DD V rising 2.90 2.98 3.06 DD Low-voltage warning threshold — low range 0 V 21 C LVW0 V falling 2.66 2.74 2.82 V DD V rising 2.72 2.80 2.88 DD Low-voltage inhibit reset/recover V 5 V — 100 — hys 22 T mV hysteresis 3 V — 60 — dc injection current5, 6, 7, 8 Single pin limit V > V 0 — 2 IN DD D I V < V 0 — –0.2 mA 23 IC IN SS Total MCU limit, includes V > V 0 — 25 IN DD sum of all stressed pins V < V 0 — –5 IN SS Bandgap Voltage Reference V BG 24 C Factory trimmed at 1.19 1.20 1.21 V V =5.0 V, Temp = 25°C DD 1 Typical values are measured at 25°C. Characterized, not tested 2 When a pin interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors. 3 Maximum is highest voltage that POR is guaranteed. 4 Simulated, not tested 5 Power supply must maintain regulation within operating V range during instantaneous and operating maximum current DD conditions.Ifpositiveinjectioncurrent(V >V )isgreaterthanI ,theinjectioncurrentmayflowoutofV andcouldresult In DD DD DD inexternalpowersupplygoingoutofregulation.EnsureexternalV loadwillshuntcurrentgreaterthanmaximuminjection DD current.ThiswillbethegreatestriskwhentheMCUisnotconsumingpower.Examplesare:ifnosystemclockispresent,or if clock rate is very low which (would reduce overall power consumption). 6 All functional non-supply pins are internally clamped to V and V . SS DD MC9S08DZ60 Series Data Sheet, Rev. 4 374 Freescale Semiconductor

AppendixA Electrical Characteristics 7 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 8 PTE1 does not have a clamp diode to V . Do not drivePTE1 above V . DD DD A.7 Supply Current Characteristics TableA-7. Supply Current Characteristics Num C Parameter Symbol V (V) Typical1 Max2 Unit DD C Run supply current3measured at 5 3 7.5 1 (CPU clock = 2MHz, f = 1 MHz) RI mA Bus DD C 3 2.8 7.4 3 P Run supply current measured at 5 7.7 11.4 2 (CPU clock = 16MHz, fBus = 8 MHz) RIDD mA C 3 7.4 11.2 P Run supply current3 measured at 5 15 24 3 (CPU clock = 40MHz, fBus = 20 MHz) RIDD mA C 3 14 23 Stop3mode P4 supply current –40°C (C, V, & M suffix) 0.9 — P4 25°C (All parts) 5 1.0 — P 105 °C (V suffix only) 26 39 4 P 125°C (M suffix only) S3I 62 90 μA DD C –40°C (C, V, & M suffix) 0.8 — C 25°C (All parts) 3 0.9 — C 105 °C (V suffix only) 21 32 C 125°C (M suffix only) 52 80 Stop2mode P4 supply current –40°C (C, V, & M suffix) 0.8 — P4 25°C (All parts) 5 0.9 — P 105 °C (V suffix only) 25 37 5 P 125°C (M suffix only) S2I 46 70 μA DD C –40°C (C, V, & M suffix) 0.7 — C 25°C (All parts) 3 0.8 — C 105 °C (V suffix only) 20 30 C 125°C (M suffix only) 40 60 MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 375

AppendixA Electrical Characteristics TableA-7. Supply Current Characteristics (continued) Num C Parameter Symbol V (V) Typical1 Max2 Unit DD RTC adder to stop2 or stop35, 25°C 5 300 — nA 6 C 3 300 — nA LVD adder to stop3 (LVDE = LVDSE = 1) 5 110 — μA 7 C 3 90 — μA Adder to stop3 for oscillator enabled6 5 5 — μA 8 C (IRCLKEN = 1 and IREFSTEN = 1 or ERCLKEN=1 and EREFSTEN = 1) 3 5 — μA 1 Typicals are measured at 25°C, unless otherwise noted. 2 Maximum values in this column apply for the full operating temperature range of the device unless otherwise noted. 3 All modules except ADC active, MCG configured for FBE, and does not include any dc loads on port pins 4 Stopcurrentsaretestedinproductionfor25°Conallparts.Testsatothertemperaturesdependuponthepartnumber suffix and maturity of the product. Freescale may eliminate a test insertion at a particular temperature from the production test flow once sufficient data has been collected and is approved. 5 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. 6 Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0). A.8 Analog Comparator (ACMP) Electricals TableA-8. Analog Comparator Electrical Specifications Num C Rating Symbol Min Typical Max Unit 1 — Supply voltage VDD 2.7 — 5.5 V 2 D Supply current (active) IDDAC — 20 35 μA 3 D Analog input voltage V V – 0.3 — V V AIN SS DD 4 D Analog input offset voltage V 20 40 mV AIO 5 D Analog Comparator hysteresis VH 3.0 6.0 20.0 mV 6 D Analog input leakage current IALKG -- -- 1.0 μA 7 D Analog Comparator initialization delay t — — 1.0 μs AINIT A.9 ADC Characteristics TableA-9.12-bit ADC Operating Conditions Characteristic Conditions Symb Min Typ1 Max Unit Comment Supply voltage Absolute V 2.7 — 5.5 V DDAD Delta to V (V -V )2 ΔV -100 0 +100 mV DD DD DDAD DDAD Ground voltage Delta to V (V -V )2 ΔV -100 0 +100 mV SS SS SSAD SSAD MC9S08DZ60 Series Data Sheet, Rev. 4 376 Freescale Semiconductor

AppendixA Electrical Characteristics TableA-9.12-bit ADC Operating Conditions (continued) Characteristic Conditions Symb Min Typ1 Max Unit Comment Ref Voltage V 2.7 V V V Applicable in only REFH DDAD DDAD High 64-pin packages {V < V REFH DDAD characterized but notproductiontest} Ref Voltage V V V V V Not Applicable in REFL SSAD SSAD SSAD Low 64-pin packages (only 32- and 48-pin packages) Input Voltage V V — V V ADIN REFL REFH Input C — 4.5 5.5 pF ADIN Capacitance Input R — 3 5 kΩ ADIN Resistance Analog Source 12 bit mode R kΩ External to MCU AS Resistance f > 4MHz — — 2 ADCK f < 4MHz — — 5 ADCK 10 bit mode f > 4MHz — — 5 ADCK f < 4MHz — — 10 ADCK 8 bit mode (all valid f ) — — 10 ADCK ADC High Speed (ADLPC=0) f 0.4 — 8.0 MHz ADCK Conversion Clock Freq. Low Power (ADLPC=1) 0.4 — 4.0 1 TypicalvaluesassumeV =5.0V,Temp=25°C,f =1.0MHzunlessotherwisestated.Typicalvaluesareforreference DDAD ADCK only and are not tested in production. 2 DC potential difference. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 377

AppendixA Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad ZAS leakage CHANNEL SELECT due to CIRCUIT ADC SAR R input R ENGINE AS protection ADIN + V ADIN – C V + AS AS – R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN FigureA-1. ADC Input Impedance Equivalency Diagram TableA-10.12-bit ADC Characteristics (V = V , V = V ) REFH DDAD REFL SSAD Characteristic Conditions C Symb Min Typ1 Max Unit Comment Supply Current ADLPC=1 T I + — 133 — μA ADC current DD ADLSMP=1 I only DDAD ADCO=1 Supply Current ADLPC=1 T I + — 218 — μA ADC current DD ADLSMP=0 I only DDAD ADCO=1 Supply Current ADLPC=0 T I + — 327 — μA ADC current DD ADLSMP=1 I only DDAD ADCO=1 Supply Current ADLPC=0 D I + — 0.582 1 mA ADC current DD ADLSMP=0 I only DDAD ADCO=1 Supply Current Stop, Reset, Module Off I + — 0.011 1 μA ADC current DD I only DDAD ADC High Speed (ADLPC=0) P f 2 3.3 5 MHz t = ADACK ADACK Asynchronous 1/f ADACK Clock Source Low Power (ADLPC=1) 1.25 2 3.3 MC9S08DZ60 Series Data Sheet, Rev. 4 378 Freescale Semiconductor

AppendixA Electrical Characteristics TableA-10.12-bit ADC Characteristics (V = V , V = V ) (continued) REFH DDAD REFL SSAD Characteristic Conditions C Symb Min Typ1 Max Unit Comment Conversion Short Sample (ADLSMP=0) D t — 20 — ADCK See ADC Time(Including cycles Table10-13 Long Sample (ADLSMP=1) — 40 — sample time) forconversion time variances Sample Time Short Sample (ADLSMP=0) D t — 3.5 — ADCK ADS cycles Long Sample (ADLSMP=1) — 23.5 — Total 12 bit mode T E — ±3.0 ±10 LSB2 Includes TUE Unadjusted quantization Error 10 bit mode P — ±1 ±2.5 8 bit mode T — ±0.5 ±1.0 Differential 12 bit mode T DNL — ±1.75 ±4.0 LSB2 Non-Linearity 10 bit mode3 P — ±0.5 ±1.0 8 bit mode3 T — ±0.3 ±0.5 Integral 12 bit mode T INL — ±1.5 ±4.0 LSB2 Non-Linearity 10 bit mode T — ±0.5 ±1.0 8 bit mode T — ±0.3 ±0.5 Zero-Scale 12 bit mode T E — ±1.5 ±6.0 LSB2 V = V ZS ADIN SSAD Error 10 bit mode P — ±0.5 ±1.5 8 bit mode T — ±0.5 ±0.5 Full-ScaleError 12 bit mode T E — ±1 ±4.0 LSB2 V =V FS ADIN DDAD 10 bit mode T — ±0.5 ±1 8 bit mode T — ±0.5 ±0.5 Quantization 12 bit mode D E — -1 to 0 -1 to 0 LSB2 Q Error 10 bit mode — — ±0.5 8 bit mode — — ±0.5 Input Leakage 12 bit mode D E — ±1 ±10.0 LSB2 Padleakage4* IL Error R 10 bit mode — ±0.2 ±2.5 AS 8 bit mode — ±0.1 ±1 Temp Sensor -40°C– 25°C D m — 3.266 — mV/°C Slope 25°C– 125°C — 3.638 — Temp Sensor 25°C D V — 1.396 — V TEMP25 Voltage 1 Typical values assume V = 5.0V, Temp = 25°C, f =1.0MHz unless otherwise stated. Typical values are for reference DDAD ADCK only and are not tested in production. 2 1 LSB = (V - V )/2N REFH REFL MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 379

AppendixA Electrical Characteristics 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals. A.10 External Oscillator (XOSC) Characteristics TableA-11. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient) Num C Rating Symbol Min Typ1 Max Unit Oscillator crystal or resonator (EREFS=1, ERCLKEN = 1 Low range (RANGE = 0) flo 32 — 38.4 kHz C High range (RANGE = 1) FEE or FBE mode2 fhi-fll 1 — 5 MHz 1 High range (RANGE = 1) PEE or PBE mode3 fhi-pll 1 — 16 MHz High range (RANGE = 1, HGO = 1) BLPE mode fhi-hgo 1 — 16 MHz High range (RANGE = 1, HGO = 0) BLPE mode fhi-lp 1 — 8 MHz C1 See crystal or resonator 2 — Load capacitors C manufacturer’s recommendation. 2 Feedback resistor 3 — Low range (32 kHz to 100 kHz) RF — 10 — MΩ High range (1 MHz to 16 MHz) — 1 — MΩ Series resistor Low range, low gain (RANGE = 0, HGO = 0) — 0 — Low range, high gain (RANGE = 0, HGO = 1) — 100 — 4 — High range, low gain (RANGE = 1, HGO = 0) RS — 0 — kΩ Highrange,highgain(RANGE=1,HGO=1) ≥8MHz — 0 0 4 MHz — 0 10 1 MHz — 0 20 Crystal start-up time4 Low range, low gain (RANGE = 0, HGO = 0) t — 200 — CSTL-LP 5 T Low range, high gain (RANGE = 0, HGO = 1) t — 400 — CSTL-HGO High range, low gain (RANGE = 1, HGO = 0)5 tCSTH-LP — 5 — ms High range, high gain (RANGE = 1, HGO = 1)4 tCSTH-HGO — 15 — Square wave input clock frequency (EREFS=0, ERCLKEN = 1) T FEE or FBE mode2 0.03125 — 5 6 PEE or PBE mode3 fextal 1 — 16 MHz BLPE mode 0 — 40 1 Typical data was characterized at 3.0 V, 25°C or is recommended value. 2 When MCG is configured for FEE or FBE mode, the input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 WhenMCGisconfiguredforPEEorPBEmode,inputclocksourcemustbedivisibleusingRDIVtowithintherangeof1MHz to 2 MHz. 4 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. This data will vary based upon the crystal manufacturer and board design. The crystal should be characterized by the crystal manufacturer. 5 4 MHz crystal. MC9S08DZ60 Series Data Sheet, Rev. 4 380 Freescale Semiconductor

AppendixA Electrical Characteristics MCU EXTAL XTAL R R S F C1 Crystal or Resonator C2 A.11 MCG Specifications TableA-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) Num C Rating Symbol Min Typical Max Unit Internalreferencefrequency-factorytrimmedat 1 P V = 5 V and temperature = 25°C fint_ft — 31.25 — kHz DD Average internal reference frequency - 2 P untrimmed1 fint_ut 25 32.7 41.66 kHz Average internal reference frequency -user 3 P trimmed fint_t 31.25 — 39.0625 kHz 4 D Internal reference startup time tirefst — 60 100 us DCO output frequency range - untrimmed1 5 — value provided for reference: fdco_ut = 1024 X fdco_ut 25.6 33.48 42.66 MHz f int_ut 6 P DCO output frequency range - trimmed fdco_t 32 — 40 MHz 7 C Rfixeesdo lvuotilotang oef atrnidm tmemedp eDrCatOu roeu (tupsuitn fgr eFqTuReInMcy) at Δfdco_res_t — ±0.1 ±0.2 %fdco 8 C Rfixeesdo lvuotilotang oef atrnidm tmemedp eDrCatOu roeu (tnpoutt ufrseinqgu eFnTcRy IaMt) Δfdco_res_t — ±0.2 ±0.4 %fdco 9 P Toovetarl vdoelvtaiagteio annodf tterimmpmeerdatDurCeOoutputfrequency Δfdco_t — +- 10..05 ±2 %fdco TotaldeviationoftrimmedDCOoutputfrequency 10 C over fixed voltage and temperature range of Δfdco_t — ±0.5 ±1 %fdco 0-70°C 11 C FLL acquisition time2 tfll_acquire — — 1 ms 12 D PLL acquisition time3 tpll_acquire — — 1 ms Long term Jitter of DCO output clock (averaged 13 C over 2ms interval)4 CJitter — 0.02 0.2 %fdco 14 D VCO operating frequency fvco 7.0 — 55.0 MHz 15 D PLL reference frequency range fpll_ref 1.0 — 2.0 MHz RMS frequency variation of a single clock cycle 16 T measured 2ms after reference edge.5 fpll_cycjit_2ms — 0.5904 — %fpll 17 T M2amxsim wuinmd ofrwe.quency variation averaged over fpll_maxjit_2ms — 0.001 — %fpll MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 381

AppendixA Electrical Characteristics TableA-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) (continued) Num C Rating Symbol Min Typical Max Unit RMS frequency variation of a single clock cycle 18 T measured 625ns after reference edge.6 fpll_cycjit_625ns — 0.5664 — %fpll Maximum frequency variation averaged over 19 T 625ns window. fpll_maxjit_625ns — 0.113 — %fpll 20 D Lock entry frequency tolerance7 Dlock ±1.49 — ±2.98 % 21 D Lock exit frequency tolerance8 Dunl ±4.47 — ±5.97 % t 22 D Lock time - FLL tfll_lock — — fll_acqfuire+ s 1075(1/int_t) t 23 D Lock time - PLL tpll_lock — — pll_acfquire+ s 1075(1/pll_ref) Loss of external clock minimum frequency - 24 D RANGE = 0 floc_low (3/5) x fint — — kHz Loss of external clock minimum frequency - 25 D RANGE = 1 floc_high (16/5) x fint — — kHz 1 TRIM register at default value (0x80) and FTRIM control bit at default value (0x0). 2 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,BLPI)toPLLenabled(PBE,PEE).Ifacrystal/resonatorisbeingusedasthereference,thisspecificationassumesit is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . BUS Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injectedintotheFLLcircuitryviaV andV andvariationincrystaloscillatorfrequencyincreasetheC percentagefor DD SS Jitter a given interval. Jitter measurements are based upon a 40MHz MCGOUT clock frequency. 5 Insomespecifications,thisvalueisdescribedas“longtermaccuracyofPLLoutputclock(averagedover2ms)”withsymbol “f .” The parameter is unchanged, but the description has been changed for clarification purposes. pll_jitter_2ms 6 In some specifications, this value is described as “Jitter of PLL output clock measured over 625ns” with symbol “f .” The parameter is unchanged, but the description has been changed for clarification purposes. pll_jitter_625ns 7 Below D minimum, the MCG is guaranteed to enter lock. Above D maximum, the MCG will not enter lock. But if the lock lock MCG is already in lock, then the MCG may stay in lock. 8 Below D minimum, the MCG will not exit lock if already in lock. Above D maximum, the MCG is guaranteed to exit lock. unl unl MC9S08DZ60 Series Data Sheet, Rev. 4 382 Freescale Semiconductor

AppendixA Electrical Characteristics A.12 AC Characteristics This section describes ac timing characteristics for each peripheral system. A.12.1 Control Timing TableA-13. Control Timing Nu C Rating Symbol Min Typical1 Max Unit m D/ 1 P Bus frequency (tcyc = 1/fBus) fBus dc — 20 MHz 2 T Internal low-power oscillator period tLPO — 1500 — μs 3 D External reset pulse width2 textrst 1.5 x tcyc — ns 4 D Reset low drive3 trstdrv 34 x tcyc — ns 5 D Active background debug mode latch setup time tMSSU 25 — ns 6 D Active background debug mode latch hold time tMSH 25 — ns IRQ/PIAx/ PIBx/PIDx pulse width 7 D Asynchronous path2 t t 100 — — ns ILIH, IHIL Synchronous path3 1.5 t cyc Port rise and fall time— Low output drive (PTxDS = 0) (load = 50 pF)4 Slew rate control disabled (PTxSE = 0) tRise, tFall — 40 ns Slew rate control enabled(PTxSE = 1) — 75 8 T Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF)4 Slew rate control disabled (PTxSE = 0) tRise, tFall — 11 ns Slew rate control enabled(PTxSE = 1) — 35 1 Typical data was characterized at 5.0 V, 25°C unless otherwise stated. 2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 When any reset is initiated, internal circuitry drives theRESET pin low for about 34 cycles of t . After POR reset, the bus cyc clockfrequencychangestotheuntrimmedDCOfrequency(freset=(f )/4)becauseTRIMisresetto0x80andFTRIMis dco_ut resetto0;andthereisanextradivide-by-twobecauseBDIVisresetto0:1.Afterotherresets,trimstaysatthepre-resetvalue. 4 Timing is shown with respect to 20% V and 80% V levels. Temperature range –40°C to 125°C. DD DD t extrst RESET PIN FigureA-2. Reset Timing MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 383

AppendixA Electrical Characteristics BKGD/MS RESET t MSH t MSSU FigureA-3. Active Background Debug Mode Latch Timing t IHIL PIAx/PIBx/PIDx IRQ/PIAx/PIBx/PIDx t ILIH FigureA-4. Pin Interrupt Timing A.12.2 Timer/PWM Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. TableA-14. TPM Input Timing Num C Rating Symbol Min Max Unit 1 — External clock frequency fTCLK dc fBus/4 MHz 2 — External clock period tTCLK 4 — tcyc 3 D External clock high time tclkh 1.5 — tcyc 4 D External clock low time tclkl 1.5 — tcyc 5 D Input capture pulse width tICPW 1.5 — tcyc MC9S08DZ60 Series Data Sheet, Rev. 4 384 Freescale Semiconductor

AppendixA Electrical Characteristics t TCLK t clkh TPMxCHn t clkl FigureA-5. Timer External Clock t ICPW TPMxCHn TPMxCHn t ICPW FigureA-6. Timer Input Capture Pulse A.12.3 MSCAN TableA-15. MSCAN Wake-up Pulse Characteristics Num C Rating Symbol Min Typ Max Unit 1 D MSCAN Wake-up dominant pulse filtered t — — 2 μs WUP 2 D MSCAN Wake-up dominant pulse pass t 5 — — μs WUP MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 385

AppendixA Electrical Characteristics A.12.4 SPI TableA-16 andFigureA-7 through FigureA-10 describe the timing requirements for the SPI system. TableA-16. SPI Electrical Characteristic Num1 C Rating2 Symbol Min Max Unit Cycle time 1 D Master tSCK 2 2048 tcyc Slave tSCK 4 — tcyc Enablelead time t 2 D Master t — 1/2 SCK Lead t Slave t 1/2 — SCK Lead Enable lag time t 3 D Master t — 1/2 SCK Lag t Slave t 1/2 — SCK Lag Clock (SPSCK)high time 4 D Master and Slave t (1/2 t )– 25 — ns SCKH SCK Clock (SPSCK) low time 5 D Master and Slave tSCKL (1/2 tSCK) – 25 — ns Datasetup time (inputs) 6 D Master t 30 — ns SI(M) Slave t 30 — ns SI(S) Datahold time (inputs) 7 D Master t 30 — ns HI(M) Slave t 30 — ns HI(S) 8 D Accesstime, slave3 t 0 40 ns A 9 D Disabletime, slave4 t — 40 ns dis Datasetup time (outputs) 10 D Master t 25 — ns SO Slave t 25 — ns SO Datahold time (outputs) 11 D Master t –10 — ns HO Slave t –10 — ns HO Operating frequency5 12 D Master fop fBus/2048 5 MHz Slave f dc f /4 op Bus 1 Refer toFigureA-7 throughFigureA-10. 2 All timing is shown with respect to 20% V and 70% V , unless noted; 100 pF load on all SPI DD DD pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Time to data active from high-impedance state. 4 Hold time to high-impedance state. 5 Maximum baud rate must be limited to 5 MHz due to pad input characteristics. MC9S08DZ60 Series Data Sheet, Rev. 4 386 Freescale Semiconductor

AppendixA Electrical Characteristics SS1 (OUTPUT) 2 1 3 SCK 5 (CPOL = 0) (OUTPUT) 4 SCK 5 (CPOL = 1) 4 (OUTPUT) 6 7 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 10 10 11 MOSI MSB OUT2 BIT 6 . . . 1 LSB OUT (OUTPUT) NOTES: 1.SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. FigureA-7. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 3 SCK 5 (CPOL = 0) (OUTPUT) 4 SCK 5 (CPOL = 1) 4 (OUTPUT) 6 7 MISO (INPUT) MSB IN(2) BIT 6 . . . 1 LSB IN 10 11 MOSI MSB OUT(2) BIT 6 . . . 1 LSB OUT (OUTPUT) NOTES: 1.SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. FigureA-8. SPI Master Timing (CPHA = 1) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 387

AppendixA Electrical Characteristics SS (INPUT) 1 3 SCK 5 (CPOL = 0) (INPUT) 4 2 SCK 5 (CPOL = 1) (INPUT) 4 9 8 10 11 MISO SEE (OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally MSB of character just received FigureA-9. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 SCK (CPOL = 0) 5 (INPUT) 4 SCK 5 (CPOL = 1) 4 (INPUT) 10 11 9 MISO SEE (OUTPUT) NOTE SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT 8 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received FigureA-10. SPI Slave Timing (CPHA = 1) MC9S08DZ60 Series Data Sheet, Rev. 4 388 Freescale Semiconductor

AppendixA Electrical Characteristics A.13 Flash and EEPROM This section provides details about program/erase times and program-erase endurance for theFlashand EEPROMmemory. ProgramanderaseoperationsdonotrequireanyspecialpowersourcesotherthanthenormalV supply. DD For more detailed information about program/erase operations, seeChapter4, “Memory.” TableA-17.Flash and EEPROM Characteristics Num C Rating Symbol Min Typical Max Unit 1 — Supply voltage for program/erase Vprog/erase 2.7 5.5 V Supply voltage for read operation 2 — 0 < fBus < 8 MHz VRead 2.7 5.5 V 0<f <20MHz Bus 3 — Internal FCLK frequency1 fFCLK 150 200 kHz 4 — Internal FCLK period (1/FCLK) tFcyc 5 6.67 μs 5 — Byte program time (random location)(2) tprog 9 tFcyc 6 — Byte program time (burst mode)(2) tBurst 4 tFcyc 7 — Page erase time2 tPage 4000 tFcyc 8 — Mass erase time(2) tMass 20,000 tFcyc Flash Program/erase endurance3 9 C TL to TH = –40°C to + 125°C nFLPE 10,000 — — cycles T = 25°C 100,000 — — EEPROM Program/erase endurance3 T to T = –40°C to + 0°C 10,000 — — 10 C L H TL to TH = 0°C to + 125°C nEEPE 50,000 — — cycles T = 25°C — 100,000 — 11 C Data retention4 tD_ret 15 100 — years 1 The frequency of this clock is controlled by a software setting. 2 Thesevaluesarehardwarestatemachinecontrolled.Usercodedoesnotneedtocountcycles.Thisinformationsuppliedfor calculating approximate time to program and erase. 3 TypicalenduranceforFlashandEEPROMisbasedontheintrinsicbitcellperformance.Foradditionalinformationonhow Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619,Typical Endurance for Nonvolatile Memory. 4 Typicaldataretentionvaluesarebasedonintrinsiccapabilityofthetechnologymeasuredathightemperatureandde-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618,Typical Data Retention for Nonvolatile Memory. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 389

AppendixA Electrical Characteristics A.14 EMC Performance Electromagneticcompatibility(EMC)performanceishighlydependantontheenvironmentinwhichthe MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. A.14.1 Radiated Emissions MicrocontrollerradiatedRFemissionsaremeasuredfrom150kHzto1GHzusingtheTEM/GTEMCell methodinaccordancewiththeIEC61967-2andSAEJ1752/3standards.Themeasurementisperformed withthemicrocontrollerinstalledonacustomEMCevaluationboardwhilerunningspecializedEMCtest software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations(NorthandEast).Formoredetailedinformationconcerningtheevaluationresults,conditions and setup, please refer to the EMC Evaluation Report for this device. The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. TableA-18. Radiated Emissions for 3M05C Mask Set Level1 Parameter Symbol Conditions Frequency f /f Unit osc CPU (Max) V V =5 0.15 – 50 MHz 18 dBμV RE_TEM DD T = +25oC A 50 – 150 MHz 18 64 LQFP 150 – 500 MHz 16 MHz 13 Radiated emissions, Crystal electric field — Conditions - 500 – 1000 MHz 20 MHz Bus 7 IEC Level L — SAE Level 2 — 1 Data based on qualification test results. MC9S08DZ60 Series Data Sheet, Rev. 4 390 Freescale Semiconductor

Appendix B Timer Pulse-Width Modulator (TPMV2) NOTE ThischapterreferstoS08TPMversion2,whichappliestothe3M05Cand older mask sets of this device. )M74K and newer mask set devices use S08TPMversion3.Ifyourdeviceusesmask0M74Kornewer,pleaserefer toChapter16, “Timer Pulse-Width Modulator (S08TPMV3) for information pertaining to that module. The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 0–4). The TPM shares its I/O pins with general-purpose I/O port pins (refer to thePins and Connections chapter for more information). B.0.1 Features The TPM has the following features: • EachTPMmaybeconfiguredforbuffered,center-alignedpulse-widthmodulation(CPWM)onall channels • Clock sources independently selectable per TPM (multiple TPMs device) • Selectable clock sources (device dependent): bus clock, fixed system clock, external pin • Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 • 16-bit free-running or up/down (CPWM) count operation • 16-bit modulus register to control counter range • Timer system enable • One interrupt per channel plus a terminal count interrupt for each TPM module (multiple TPMs device) • Channel features: — Each channel may be input capture, output compare, or buffered edge-aligned PWM — Rising-edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs B.0.2 Block Diagram FigureB-1showsthestructureofaTPM.SomeMCUsincludemorethanoneTPM,withvariousnumbers of channels. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 391

AppendixB Timer Pulse-Width Modulator (TPMV2) BUSCLK CLOCK SOURCE PRESCALE AND SELECT SELECT DIVIDE BY XCLK SYNC OFF, BUS, XCLK, EXT 1, 2, 4, 8, 16, 32, 64, or 128 TPMxCLK CLKSB CLKSA PS2 PS1 PS0 CPWMS MAIN 16-BIT COUNTER TOF COUNTER RESET INTERRUPT TOIE LOGIC 16-BIT COMPARATOR TPMxMODH:TPMxMODL ELS0B ELS0A CHANNEL 0 PORT TPMxCH0 16-BIT COMPARATOR LOGIC TPMxC0VH:TPMxC0VL CH0F 16-BIT LATCH INTERRUPT LOGIC MS0B MS0A CH0IE S CHANNEL 1 ELS1B ELS1A PORT TPMxCH1 BU 16-BIT COMPARATOR LOGIC L NA TPMxC1VH:TPMxC1VL CH1F R E T 16-BIT LATCH INTERRUPT N I LOGIC MS1B MS1A CH1IE . . . . . . . . . ELSnB ELSnA CHANNEL n PORT TPMxCHn 16-BIT COMPARATOR LOGIC TPMxCnVH:TPMxCnVL CHnF 16-BIT LATCH INTERRUPT LOGIC CHnIE MSnB MSnA FigureB-1.TPM Block Diagram The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a modulocounter,oranup-/down-counterwhentheTPMisconfiguredforcenter-alignedPWM.TheTPM counter(whenoperatinginnormalup-countingmode)providesthetimingreferencefortheinputcapture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control the modulo value of the counter. (The values 0x0000 or 0xFFFF effectively make the counter free running.) Software can read the counter value at any time without affecting the counting sequence. Any write to either byte of the TPMxCNT counter resets the counter regardless of the data value written. MC9S08DZ60 Series Data Sheet, Rev. 4 392 Freescale Semiconductor

AppendixB Timer Pulse-Width Modulator (TPMV2) All TPM channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels. B.1 External Signal Description When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled. Afterreset,theTPMmodulesaredisabledandallpinsdefaulttogeneral-purposeinputswiththepassive pullups disabled. B.1.1 External TPM Clock Sources WhencontrolbitsCLKSB:CLKSAinthetimerstatusandcontrolregisteraresetto1:1,theprescalerand consequentlythe16-bitcounterforTPMxaredrivenbyanexternalclocksource,TPMxCLK,connected to an I/O pin. A synchronizer is needed between the external clock and the rest of the TPM. This synchronizerisclockedbythebusclocksothefrequencyoftheexternalsourcemustbelessthanone-half thefrequencyofthebusrateclock.Theupperfrequencylimitforthisexternalclocksourceisspecifiedto beone-fourththebusfrequencytoconservativelyaccommodatedutycycleandphase-lockedloop(PLL) or frequency-locked loop (FLL) frequency jitter effects. OnsomedevicestheexternalclockinputissharedwithoneoftheTPMchannels.WhenaTPMchannel issharedastheexternalclockinput,theassociatedTPMchannelcannotusethepin.(Thechannelcanstill be used in output compare mode as a software timer.) Also, if one of the TPM channels is used as the externalclockinput,thecorrespondingELSnB:ELSnAcontrolbitsmustbesetto0:0sothechannelisnot trying to use the same pin. B.1.2 TPMxCHn — TPMx Channel n I/O Pins Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the configurationofthechannel.Insomecases,nopinfunctionisneededsothepinrevertstobeingcontrolled by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction registersdonotaffecttherelatedpin(s).SeethePinsandConnectionschapterforadditionalinformation about shared pin functions. B.2 Register Definition The TPM includes: • An 8-bit status and control register (TPMxSC) • A 16-bit counter (TPMxCNTH:TPMxCNTL) • A 16-bit modulo register (TPMxMODH:TPMxMODL) Each timer channel has: • An 8-bit status and control register (TPMxCnSC) • A 16-bit channel value register (TPMxCnVH:TPMxCnVL) Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignmentsforallTPMregisters.Thissectionreferstoregistersandcontrolbitsonlybytheirnames.A MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 393

AppendixB Timer Pulse-Width Modulator (TPMV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. B.2.1 Timer Status and Control Register (TPMxSC) TPMxSCcontainstheoverflowstatusflagandcontrolbitsthatareusedtoconfiguretheinterruptenable, TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this timer module. 7 6 5 4 3 2 1 0 R TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved FigureB-2. Timer Status and Control Register (TPMxSC) TableB-1. TPMxSC Register Field Descriptions Field Description 7 Timer Overflow Flag — This flag is set when the TPM counter changes to 0x0000 after reaching the modulo TOF value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set after the counter has reached the value in the modulo register, at the transition to the next lower count value. ClearTOFbyreadingtheTPMstatusandcontrolregisterwhenTOFissetandthenwritinga0toTOF.Ifanother TPMoverflowoccursbeforetheclearingsequenceiscomplete,thesequenceisresetsoTOFwouldremainset aftertheclearsequencewascompletedfortheearlierTOF.ResetclearsTOF.Writinga1toTOFhasnoeffect. 0 TPM counter has not reached modulo value or overflow 1 TPM counter has overflowed 6 Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an TOIE interrupt is generated when TOF equals 1. Reset clears TOIE. 0 TOF interrupts inhibited (use software polling) 1 TOF interrupts enabled 5 Center-AlignedPWMSelect—Thisread/writebitselectsCPWMoperatingmode.Resetclearsthisbitsothe CPWMS TPMoperatesinup-countingmodeforinputcapture,outputcompare,andedge-alignedPWMfunctions.Setting CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears CPWMS. 0 AllTPMxchannelsoperateasinputcapture,outputcompare,oredge-alignedPWMmodeasselectedbythe MSnB:MSnA control bits in each channel’s status and control register 1 All TPMx channels operate in center-aligned PWM mode 4:3 ClockSourceSelect—AsshowninTableB-2,this2-bitfieldisusedtodisabletheTPMsystemorselectone CLKS[B:A] ofthreeclocksourcestodrivethecounterprescaler.TheexternalsourceandtheXCLKaresynchronizedtothe bus clock by an on-chip synchronization circuit. 2:0 Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in PS[2:0] TableB-3.Thisprescalerislocatedafteranyclocksourcesynchronizationorclocksourceselection,soitaffects whatever clock source is selected to drive the TPM system. MC9S08DZ60 Series Data Sheet, Rev. 4 394 Freescale Semiconductor

AppendixB Timer Pulse-Width Modulator (TPMV2) TableB-2. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 0:0 No clock selected (TPMx disabled) 0:1 Bus rate clock (BUSCLK) 1:0 Fixed system clock (XCLK) 1:1 External source (TPMxCLK)1,2 1 The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency. 2 If the external clock input is shared with channel n and is selected as the TPM clock source, the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try to use the same pin for a conflicting function. TableB-3. Prescale Divisor Selection PS2:PS1:PS0 TPM Clock Source Divided-By 0:0:0 1 0:0:1 2 0:1:0 4 0:1:1 8 1:0:0 16 1:0:1 32 1:1:0 64 1:1:1 128 B.2.2 Timer Counter Registers (TPMxCNTH:TPMxCNTL) Thetworead-onlyTPMcounterregisterscontainthehighandlowbytesofthevalueintheTPMcounter. Readingeitherbyte(TPMxCNTHorTPMxCNTL)latchesthecontentsofbothbytesintoabufferwhere they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The coherencymechanismisautomaticallyrestartedbyanMCUreset,awriteofanyvaluetoTPMxCNTHor TPMxCNTL, or any write to the timer status/control register (TPMxSC). Reset clears the TPM counter registers. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Any write to TPMxCNTH clears the 16-bit counter. Reset 0 0 0 0 0 0 0 0 FigureB-3. Timer Counter Register High (TPMxCNTH) MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 395

AppendixB Timer Pulse-Width Modulator (TPMV2) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Any write to TPMxCNTL clears the 16-bit counter. Reset 0 0 0 0 0 0 0 0 FigureB-4. Timer Counter Register Low (TPMxCNTL) Whenbackgroundmodeisactive,thetimercounterandthecoherencymechanismarefrozensuchthatthe buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. B.2.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL) The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock (CPWMS=0)orstartscountingdown(CPWMS=1),andtheoverflowflag(TOF)becomesset.Writing toTPMxMODHorTPMxMODLinhibitsTOFandoverflowinterruptsuntiltheotherbyteiswritten.Reset setstheTPMcountermoduloregistersto0x0000,whichresultsinafree-runningtimercounter(modulo disabled). 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 FigureB-5. Timer Counter Modulo Register High (TPMxMODH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 FigureB-6. Timer Counter Modulo Register Low (TPMxMODL) Itisgoodpracticetowaitforanoverflowinterruptsobothbytesofthemoduloregistercanbewrittenwell before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. MC9S08DZ60 Series Data Sheet, Rev. 4 396 Freescale Semiconductor

AppendixB Timer Pulse-Width Modulator (TPMV2) B.2.4 Timer Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 1 0 R 0 0 CHnF CHnIE MSnB MSnA ELSnB ELSnA W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved FigureB-7. Timer Channel n Status and Control Register (TPMxCnSC) TableB-4. TPMxCnSC Register Field Descriptions Field Description 7 ChannelnFlag—Whenchannelnisconfiguredforinputcapture,thisflagbitissetwhenanactiveedgeoccurs CHnF on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag is seldom used with center-aligned PWMs because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF byreadingTPMxCnSCwhileCHnFissetandthenwritinga0toCHnF.Ifanotherinterruptrequestoccursbefore the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect. 0 No input capture or output compare event occurred on channeln 1 Input capture or output compare event occurred on channeln 6 Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE. CHnIE 0 Channel n interrupt requests disabled (use software polling) 1 Channel n interrupt requests enabled 5 Mode Select B for TPM Channel n — When CPWMS=0, MSnB=1 configures TPM channel n for MSnB edge-aligned PWM mode. For a summary of channel mode and setup controls, refer toTableB-5. 4 ModeSelectAforTPMChanneln—WhenCPWMS=0andMSnB=0,MSnAconfiguresTPMchannelnfor MSnA input capture mode or output compare mode. Refer toTableB-5 for a summary of channel mode and setup controls. 3:2 Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by ELSn[B:A] CPWMS:MSnB:MSnA and shown inTableB-5, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. SettingELSnB:ELSnAto0:0configurestherelatedtimerpinasageneral-purposeI/Opinunrelatedtoanytimer channelfunctions.Thisfunctionistypicallyusedtotemporarilydisableaninputcapturechannelortomakethe timerpinavailableasageneral-purposeI/Opinwhentheassociatedtimerchannelissetupasasoftwaretimer that does not require the use of a pin. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 397

AppendixB Timer Pulse-Width Modulator (TPMV2) TableB-5. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration X XX 00 PinnotusedforTPMchannel;useasanexternalclockfortheTPMor revert to general-purpose I/O 0 00 01 Input capture Capture onrising edge only 10 Capture onfalling edge only 11 Capture on rising or falling edge 01 00 Output Software compare only compare 01 Toggle output on compare 10 Clearoutput on compare 11 Setoutput on compare 1X 10 Edge-aligned High-true pulses (clearoutput on compare) PWM X1 Low-true pulses (setoutput on compare) 1 XX 10 Center-aligned High-true pulses (clearoutput on compare-up) PWM X1 Low-true pulses (setoutput on compare-up) If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior. B.2.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL) These read/write registers contain the captured TPM counter value of the input capture function or the outputcomparevaluefortheoutputcompareorPWMfunctions.Thechannelvalueregistersarecleared by reset. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 FigureB-8. TimerChannel Value Register High (TPMxCnVH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 FigureB-9. TimerChannel Value Register Low (TPMxCnVL) MC9S08DZ60 Series Data Sheet, Rev. 4 398 Freescale Semiconductor

AppendixB Timer Pulse-Width Modulator (TPMV2) Ininputcapturemode,readingeitherbyte(TPMxCnVHorTPMxCnVL)latchesthecontentsofbothbytes into a buffer where they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPMxCnSC register is written. InoutputcompareorPWMmodes,writingtoeitherbyte(TPMxCnVHorTPMxCnVL)latchesthevalue into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. B.3 Functional Description All TPM functions are associated with a main 16-bit counter that allows flexible selection of the clock sourceandprescaledivisor.A16-bitmoduloregisteralsoisassociatedwiththemain16-bitcounterinthe TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function. TheTPMhascenter-alignedPWMcapabilitiescontrolledbytheCPWMScontrolbitinTPMxSC.When CPWMS is set to 1, timer counter TPMxCNT changes to an up-/down-counter and all channels in the associated TPM act as center-aligned PWM channels. When CPWMS=0, each channel can independentlybeconfiguredtooperateininputcapture,outputcompare,orbufferededge-alignedPWM mode. The following sections describe the main 16-bit counter and each of the timer operating modes (input capture,outputcompare,edge-alignedPWM,andcenter-alignedPWM).Becausedetailsofpinoperation and interrupt activity depend on the operating mode, these topics are covered in the associated mode sections. B.3.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overflow, and manual counter reset. After any MCU reset, CLKSB:CLKSA=0:0 so no clock source is selected and the TPM is inactive. Normally,CLKSB:CLKSAwouldbesetto0:1sothebusclockdrivesthetimercounter.Theclocksource forthe TPM can beselected to be off, the bus clock (BUSCLK), the fixed system clock (XCLK), or an external input. The maximum frequency allowed for the external clock option is one-fourth the bus rate. Refer toSectionB.2.1, “Timer Status and Control Register (TPMxSC)”andTableB-2 for more information about clock source selection. Whenthemicrocontrollerisinactivebackgroundmode,theTPMtemporarilysuspendsallcountinguntil themicrocontrollerreturnstonormaluseroperatingmode.Duringstopmode,allTPMclocksarestopped; therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to operate normally. Themain16-bitcounterhastwocountingmodes.Whencenter-alignedPWMisselected(CPWMS=1), thecounteroperatesinup-/down-countingmode.Otherwise,thecounteroperatesasasimpleup-counter. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 399

AppendixB Timer Pulse-Width Modulator (TPMV2) As an up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then continueswith0x0000.Theterminalcountis0xFFFForamodulusvalueinTPMxMODH:TPMxMODL. When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminalcountandthencountsdownwardto0x0000whereitreturnstoup-counting.Both0x0000andthe terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock period long). Aninterruptflagandenableareassociatedwiththemain16-bitcounter.Thetimeroverflowflag(TOF)is asoftware-accessibleindicationthatthetimercounterhasoverflowed.Theenablesignalselectsbetween software polling (TOIE=0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE=1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1. The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-countingmode,themain16-bitcountercountsfrom0x0000through0xFFFFandoverflowsto0x0000 onthenextcountingclock.TOFbecomessetatthetransitionfrom0xFFFFto0x0000.Whenamodulus limitisset,TOFbecomessetatthetransitionfromthevaluesetinthemodulusregisterto0x0000.When the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changesdirectionatthetransitionfromthevaluesetinthemodulusregisterandthenextlowercountvalue. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter forreadoperations.Whenevereitherbyteofthecounterisread(TPMxCNTHorTPMxCNTL),bothbytes arecapturedintoabuffersowhentheotherbyteisread,thevaluewillrepresenttheotherbyteofthecount atthetimethefirstbytewasread.Thecountercontinuestocountnormally,butnonewvaluecanberead from either byte until both bytes of the old count have been read. Themaintimercountercanberesetmanuallyatanytimebywritinganyvaluetoeitherbyteofthetimer count TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was read before resetting the count. B.3.2 Channel Mode Selection ProvidedCPWMS=0(center-alignedPWMoperationisnotspecified),theMSnBandMSnAcontrolbits inthechannelnstatusandcontrolregistersdeterminethebasicmodeofoperationforthecorresponding channel. Choices include input capture, output compare, and buffered edge-aligned PWM. B.3.2.1 Input Capture Mode Withtheinputcapturefunction,theTPMcancapturethetimeatwhichanexternaleventoccurs.Whenan activeedgeoccursonthepinofaninputcapturechannel,theTPMlatchesthecontentsoftheTPMcounter intothechannelvalueregisters(TPMxCnVH:TPMxCnVL).Risingedges,fallingedges,oranyedgemay be chosen as the active edge that triggers an input capture. When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent16-bitaccessesregardlessoforder.Thecoherencysequencecanbemanuallyresetbywritingto the channel status/control register (TPMxCnSC). MC9S08DZ60 Series Data Sheet, Rev. 4 400 Freescale Semiconductor

AppendixB Timer Pulse-Width Modulator (TPMV2) An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. B.3.2.2 Output Compare Mode With the output compare function, the TPM can generate timed pulses with programmable position, polarity,duration,andfrequency.Whenthecounterreachesthevalueinthechannelvalueregistersofan output compare channel, the TPM can set, clear, or toggle the channel pin. In output compare mode, values are transferred to the corresponding timer channel value registers only afterboth8-bitbytesofa16-bitregisterhavebeenwritten.Thiscoherencysequencecanbemanuallyreset by writing to the channel status/control register (TPMxCnSC). An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. B.3.2.3 Edge-Aligned PWM Mode ThistypeofPWMoutputusesthenormalup-countingmodeofthetimercounter(CPWMS=0)andcan be used when other channels in the same TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the setting in the modulus register (TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. Duty cycle cases of 0percent and 100percent are possible. AsFigureB-10shows,theoutputcomparevalueintheTPMchannelregistersdeterminesthepulsewidth (duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the pulse width. If ELSnA=0, the counter overflow forces the PWM signal high and the output compare forcesthePWMsignallow.IfELSnA=1,thecounteroverflowforcesthePWMsignallowandtheoutput compare forces the PWM signal high. OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TPMxC OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE FigureB-10.PWM Period and Pulse Width (ELSnA=0) Whenthechannelvalueregisterissetto0x0000,thedutycycleis0percent.Bysettingthetimerchannel value register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting, 100% duty cycle can be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register, TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the correspondingtimerchannelregistersonlyafterboth8-bitbytesofa16-bitregisterhavebeenwrittenand MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 401

AppendixB Timer Pulse-Width Modulator (TPMV2) the value in the TPMxCNTH:TPMxCNTL counter is 0x0000. (The new duty cycle does not take effect until the next full period.) B.3.3 Center-Aligned PWM Mode This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS=1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODLshouldbekeptintherangeof0x0001to0x7FFFbecausevaluesoutsidethis range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output. pulse width=2 x (TPMxCnVH:TPMxCnVL) Eqn.17-1 period = 2 x (TPMxMODH:TPMxMODL); for TPMxMODH:TPMxMODL=0x0001–0x7FFF Eqn.17-2 IfthechannelvalueregisterTPMxCnVH:TPMxCnVLiszeroornegative(bit15set),thedutycyclewill be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if generationof100%dutycycleisnotnecessary).Thisisnotasignificantlimitationbecausetheresulting period is much longer than required for normal applications. TPMxMODH:TPMxMODL=0x0000isaspecialcasethatshouldnotbeusedwithcenter-alignedPWM mode. When CPWMS=0, this case corresponds to the counter running free from 0x0000 through 0xFFFF,butwhenCPWMS=1thecounterneedsavalidmatchtothemodulusregistersomewhereother than at 0x0000 in order to change directions from up-counting to down-counting. FigureB-11 shows the output compare value in the TPM channel registers (multiplied by 2), which determines the pulse width (duty cycle) of the CPWM signal. If ELSnA=0, the compare match while counting up forces the CPWM output signal low and a compare match while counting down forces the outputhigh.ThecountercountsupuntilitreachesthemodulosettinginTPMxMODH:TPMxMODL,then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL. COUNT=0 OUTPUT OUTPUT COUNT= COMPARE COMPARE COUNT= TPMxMODH:TPMx (COUNT DOWN) (COUNT UP) TPMxMODH:TPMx TPM1C PULSE WIDTH 2 x PERIOD 2 x FigureB-11.CPWM Period and Pulse Width (ELSnA=0) Center-alignedPWMoutputstypicallyproducelessnoisethanedge-alignedPWMsbecausefewerI/Opin transitionsarelinedupatthesamesystemclockedge.ThistypeofPWMisalsorequiredforsometypes of motor drives. MC9S08DZ60 Series Data Sheet, Rev. 4 402 Freescale Semiconductor

AppendixB Timer Pulse-Width Modulator (TPMV2) Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensurecoherent16-bitupdatesandtoavoidunexpectedPWMpulsewidths.Writestoanyoftheregisters, TPMxMODH,TPMxMODL,TPMxCnVH,andTPMxCnVL,actuallywritetobufferregisters.Valuesare transferredtothecorrespondingtimerchannelregistersonlyafterboth8-bitbytesofa16-bitregisterhave beenwrittenandthetimercounteroverflows(reversesdirectionfromup-countingtodown-countingatthe endoftheterminalcountinthemodulusregister).ThisTPMxCNToverflowrequirementonlyappliesto PWM channels, not output compares. Optionally,whenTPMxCNTH:TPMxCNTL=TPMxMODH:TPMxMODL,theTPMcangenerateaTOF interruptattheendofthiscount.TheusercanchoosetoreloadanynumberofthePWMbuffers,andthey will all update simultaneously at the start of a new period. Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the coherencymechanismforthemoduloregisters.WritingtoTPMxCnSCcancelsanyvalueswrittentothe channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. B.4 TPM Interrupts TheTPMgeneratesanoptionalinterruptforthemaincounteroverflowandaninterruptforeachchannel. The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized.IfthechannelisconfiguredforoutputcompareorPWMmodes,theinterruptflagisseteach time the main timer counter matches the value in the 16-bit channel value register. See the Resets, Interrupts, and System Configuration chapter for absolute interrupt vector addresses, priority, and local interrupt mask control bits. ForeachinterruptsourceintheTPM,aflagbitissetonrecognitionoftheinterruptconditionsuchastimer overflow, channel input capture, or output compare events. This flag may be read (polled) by software to verify that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated whenever the associated interrupt flag equals 1. It is the responsibility of user software to perform a sequence of steps to clear the interrupt flag before returning from the interrupt service routine. B.4.1 Clearing Timer Interrupt Flags TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1) followedbyawriteof0tothebit.Ifaneweventisdetectedbetweenthesetwosteps,thesequenceisreset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. B.4.2 Timer Overflow Interrupt Description The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-countingmode,the16-bittimercountercountsfrom0x0000through0xFFFFandoverflowsto0x0000 onthenextcountingclock.TOFbecomessetatthetransitionfrom0xFFFFto0x0000.Whenamodulus limitisset,TOFbecomessetatthetransitionfromthevaluesetinthemodulusregisterto0x0000.When thecounterisoperatinginup-/down-countingmode,theTOFflaggetssetasthecounterchangesdirection MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 403

AppendixB Timer Pulse-Width Modulator (TPMV2) atthetransitionfromthevaluesetinthemodulusregisterandthenextlowercountvalue.Thiscorresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) B.4.3 Channel Event Interrupt Description The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges,fallingedges,anyedge,ornoedge(off)astheedgethattriggersaninputcaptureevent.Whenthe selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in SectionB.4.1, “Clearing Timer Interrupt Flags.” When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step sequence described inSectionB.4.1, “Clearing Timer Interrupt Flags.” B.4.4 PWM End-of-Duty-Cycle Events For channels that are configured for PWM operation, there are two possibilities: • When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter matches the channel value register that marks the end of the active duty cycle period. • When the channel is configured for center-aligned PWM, the timer count matches the channel valueregistertwiceduringeachPWMcycle.InthisCPWMcase,thechannelflagissetatthestart and at the end of the active duty cycle, which are the times when the timer counter matches the channel value register. The flag is cleared by the 2-step sequence described inSectionB.4.1, “Clearing Timer Interrupt Flags.” MC9S08DZ60 Series Data Sheet, Rev. 4 404 Freescale Semiconductor

Appendix C Ordering Information and Mechanical Drawings C.1 Ordering Information This section contains ordering information forMC9S08DZ60 Series devices. Example of the device numbering system: MC9 S08 DZ 60 F1 M XX Status (MC = Fully Qualified) Package designator (seeTableC-2) (S = Auto Qualified) Temperature range Memory (C = –40°C to 85°C) (9 =Flash-based) (V = –40°C to 105°C) Core (M = –40°C to 125°C) Family Mast Set Identifier Only appears for “Auto Qualified” part numbers ApproximateFlash beginning with “S” size in KB F1 = 1M74K mask set C.1.1 MC9S08DZ60 Series Devices TableC-1. Devices in the MC9S08DZ60 Series Memory Device Number Available Packages1 FLASH RAM EEPROM MC9S08DZ60 60,032 4096 2048 64-LQFP, MC9S08DZ48 49,152 3072 1536 48-LQFP, 32-LQFP MC9S08DZ32 33,792 2048 1024 MC9S08DZ16 16,896 1024 512 48-LQFP, 32-LQFP 1 SeeTableC-2 for package information. C.2 Mechanical Drawings The following pages are mechanical drawings for the packages described in the following table: MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 405

AppendixC Ordering Information and Mechanical Drawings TableC-2. Package Descriptions Pin Count Type Abbreviation Designator Document No. 64 Low Quad Flat Package LQFP LH 98ASS23234W 48 Low Quad Flat Package LQFP LF 98ASH00962A 32 Low Quad Flat Package LQFP LC 98ASH70029A MC9S08DZ60 Series Data Sheet, Rev. 4 406 Freescale Semiconductor

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