Freescale Semiconductor Document Number: QFN_Addendum Rev. 0, 07/2014 Addendum Addendum for New QFN Package Migration This addendum provides the changes to the 98A case outline numbers for products covered in this book. Case outlines were changed because of the migration from gold wire to copper wire in some packages. See the table below for the old (gold wire) package versus the new (copper wire) package. To view the new drawing, go to Freescale.com and search on the new 98A package number for your device. For more information about QFN package use, see EB806: Electrical Connection Recommendations for the Exposed Pad on QFN and DFN Packages. ©Freescale Semiconductor, Inc., 2014. All rights reserved.

Original (gold wire) Current (copper wire) Part Number Package Description package document number package document number MC68HC908JW32 48 QFN 98ARH99048A 98ASA00466D MC9S08AC16 MC9S908AC60 MC9S08AC128 MC9S08AW60 MC9S08GB60A MC9S08GT16A MC9S08JM16 MC9S08JM60 MC9S08LL16 MC9S08QE128 MC9S08QE32 MC9S08RG60 MCF51CN128 MC9RS08LA8 48 QFN 98ARL10606D 98ASA00466D MC9S08GT16A 32 QFN 98ARH99035A 98ASA00473D MC9S908QE32 32 QFN 98ARE10566D 98ASA00473D MC9S908QE8 32 QFN 98ASA00071D 98ASA00736D MC9S08JS16 24 QFN 98ARL10608D 98ASA00734D MC9S08QB8 MC9S08QG8 24 QFN 98ARL10605D 98ASA00474D MC9S08SH8 24 QFN 98ARE10714D 98ASA00474D MC9RS08KB12 24 QFN 98ASA00087D 98ASA00602D MC9S08QG8 16 QFN 98ARE10614D 98ASA00671D MC9RS08KB12 8 DFN 98ARL10557D 98ASA00672D MC9S08QG8 MC9RS08KA2 6 DFN 98ARL10602D 98ASA00735D Addendum for New QFN Package Migration, Rev. 0 2 Freescale Semiconductor

Freescale Semiconductor Document Number: MC9S08AC128 Data Sheet: Technical Data Rev. 4, 8/2011 MC9S08AC128 8-Bit MC9S08AC128 Microcontroller Data Sheet 917A-03 840B-01 824D-02 8-Bit HCS08 Central Processor Unit (CPU) Power-Saving Modes • 40-MHz HCS08 CPU (central processor unit) (cid:129) Wait plus two stops (cid:129) 20-MHz internal bus frequency Peripherals (cid:129) HC08 instruction set with added BGND, CALL and (cid:129) ADC — 16-channel, 10-bit resolution, 2.5s RTC instructions conversion time, automatic compare function, (cid:129) Memory Management Unit to support paged temperature sensor, internal bandgap reference memory. channel (cid:129) Linear Address Pointer to allow direct page data (cid:129) SCIx — Two serial communications interface accesses of the entire memory map modules supporting LIN 2.0 Protocol and SAE J2602 Development Support protocols; Full duplex non-return to zero (NRZ); (cid:129) Background debugging system Master extended break generation; Slave extended (cid:129) Breakpoint capability to allow single breakpoint break detection; Wakeup on active edge setting during in-circuit debugging (plus two more (cid:129) SPIx — One full and one master-only serial breakpoints in on-chip debug module) peripheral interface modules; Full-duplex or (cid:129) On-chip in-circuit emulator (ICE) Debug module single-wire bidirectional; Double-buffered transmit containing three comparators and nine trigger and receive; Master or Slave mode; MSB-first or modes. Eight deep FIFO for storing change-of-flow LSB-first shifting addresses and event-only data. Supports both tag (cid:129) IIC — Inter-integrated circuit bus module; Up to 100 and force breakpoints. kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt Memory Options driven byte-by-byte data transfer; supports broadcast (cid:129) Up to 128K FLASH — read/program/erase over full mode and 10 bit addressing operating voltage and temperature (cid:129) TPMx — One 2-channel and two 6-channel 16-bit (cid:129) Up to 8K Random-access memory (RAM) timer/pulse-width modulator (TPM) modules: (cid:129) Security circuitry to prevent unauthorized access to Selectable input capture, output compare, and RAM and FLASH contents edge-aligned PWM capability on each channel. Each Clock Source Options timer module may be configured for buffered, (cid:129) Clock source options include crystal, resonator, centered PWM (CPWM) on all channels external clock, or internally generated clock with (cid:129) KBI — 8-pin keyboard interrupt module precision NVM trimming using ICG module Input/Output System Protection (cid:129) Up to 70 general-purpose input/output pins (cid:129) Optional computer operating properly (COP) reset (cid:129) Software selectable pullups on input port pins with option to run from independent internal clock (cid:129) Software selectable drive strength and slew rate source or bus clock control on ports when used as outputs (cid:129) CRC module to support fast cyclic redundancy Package Options checks on system memory (cid:129) 80-pin low-profile quad flat package (LQFP) (cid:129) Low-voltage detection with reset or interrupt (cid:129) 64-pin quad flat package (QFP) (cid:129) Illegal opcode detection with reset (cid:129) 48-pin quad flat no-lead package (QFN) (cid:129) Master reset pin and power-on reset (POR) (cid:129) 44-pin low-profile quad flat package (LQFP) This document contains information on a new product. Specifications and information herein are subject to change without notice. ©Freescale Semiconductor, Inc., 2007-2011. All rights reserved.

Table of Contents Chapter1 3.9 Internal Clock Generation Module Characteristics . . . 24 Device Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3.9.1 ICG Frequency Specifications . . . . . . . . . . . . . 25 1.1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter2 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pins and Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.10.2 Timer/PWM (TPM) Module Timing. . . . . . . . . . 28 2.1 Device Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . .5 3.11 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Chapter3 3.12 FLASH Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 33 Electrical Characteristics and Timing Specifications . . . . . . .11 3.13 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.13.1 Radiated Emissions. . . . . . . . . . . . . . . . . . . . . 34 3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . .11 Chapter4 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .11 Ordering Information and Mechanical Drawings. . . . . . . . . . 35 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13 4.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5 ESD Protection and Latch-Up Immunity. . . . . . . . . . . .14 4.2 Orderable Part Numbering System. . . . . . . . . . . . . . . 35 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.7 Supply Current Characteristics. . . . . . . . . . . . . . . . . . .18 Chapter5 3.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Related Documentation MC9S08AC128 Series Reference Manual (MC9S08AC128RM) contains extensive product information including modes of operartion, memory, resets and interrupts, reg- ister definitions, port pins, CPU, and all peripheral module information. For the latest version of the documentation, check our website at: http://www.freescale.com MC9S08AC128 MCU Series Data Sheet, Rev. 4 2 Freescale Semiconductor

Chapter 1 Device Overview The MC9S08AC128 is a member of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). The MC9S08AC128 uses the enhanced HCS08 core. 1.1 MCU Block Diagram The block diagram in Figure 1-1 shows the structure of the MC9S08AC128 Series MCU. MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 3

Chapter1 Device Overview HCS08 CORE DEBUG MODULE (DBG) PTA7 PTA6 PTA5 A BKGD/MS BDC CPU CYCLIC REDUNDANCY RT PTA4 CHECK MODULE (CRC) O PTA3 P PTA2 PTA1 PTA0 HCS08 SYSTEM CONTROL INTERNAL CLOCK RESET RESETS AND INTERRUPTS GENERATOR (ICG) PTB7/AD1P7 MODES OF OPERATION PTB6/AD1P6 RQ/TPMCLK POWER MANAGEMENT LOW-POWER OSC EXXTATALL T B PPTTBB54//AADD11PP54 R O PTB3/AD1P3 RTI COP P PTB2/AD1P2 8-BIT KEYBOARD KBI1P7–KBI1P0 PTB1/TPM3CH1/AD1P1 IRQ LVD INTERRUPT MODULE (KBI1) PTB0/TPM3CH0/AD1P0 VDDAD PTC6 VSSAD ANALOG10-T-BOI-TDIGITAL AD1P15–AD1P0 PTC5/RxD2 V C PTC4 REFL CONVERTER (ADC) T VREFH OR PTC3/TxD2 P PTC2/MCLK USERMEMORY SCL PTC1/SDA1 FLASH, RAM IIC MODULE (IIC1) SDA PTC0/SCL1 (BYTES) (AW128 = 128K, 8K) (AW96 = 96K, 6K) SERIAL COMMUNICATIONS RXD1 PTD7/KBI1P7/AD1P15 INTERFACE MODULE (SCI1) TXD1 PTD6/TPM1CLK/AD1P14 VDD PTD5/AD1P13 VSS VOLTAGE REGULATOR SERIAL COMMUNICATIONS RXD2 RT D PPTTDD34//KTPBMI12PC6/LAKD/A1DP111P12 O PTJ7 INTERFACE MODULE (SCI2) TXD2 P PTD2/KBI1P5/AD1P10 PTJ6 PTD1/AD1P9 PTJ5 SPSCK1 PTD0/AD1P8 J PTJ4 T MOSI1 PTJ3 OR SERIAL PERIPHERAL MISO1 PTE7/SPSCK1 PTJ2 P INTERFACE MODULE (SPI1) SS1 PTE6/MOSI1 PTJ1 PTE5/MISO1 PTJ0 SPSCK2 SERIAL PERIPHERAL MOSI2 PTE4/SS1 E PTH6/MISO2 INTERFACE MODULE (SPI2) MISO2 T R PTH5/MOSI2 H O PTE3/TPM1CH1 PTH4/SPSCK2 T P PTE2/TPM1CH0 R PTH3/TPM2CH5 O TPM1CLK or TPMCLK PTE1/RxD1 PTH2/TPM2CH4 P 6-CHANNEL TIMER/PWM TPM1CH0–TPM1CH5 PTE0/TxD1 PTH1/TPM2CH3 MODULE (TPM1) PTH0/TPM2CH2 PTF7 TPM2CLK or TPMCLK PTF6 6-CHANNEL TIMER/PWM PTG6/EXTAL TPM2CH0–TPM2CH5 PTF5/TPM2CH1 PTG5/XTAL G MODULE (TPM2) T F PTF4/TPM2CH0 PTG4/KBI1P4 T OR PTF3/TPM1CH5 PTG3/KBI1P3 OR TPMCLK P PTF2/TPM1CH4 PTG2/KBI1P2 P 2-CHANNEL TIMER/PWM TPM3CH1 PTF1/TPM1CH3 PTG1/KBI1P1 MODULE (TPM3) TPM3CH0 PTF0/TPM1CH2 PTG0/KBIP0 - Pin not connected in 64-pin and 48-pin packages - Pin not connected in 48-pin and 44-pin package - Pin not connected in 44-pin package Figure1-1. MC9S08AC128 Series Block Diagram MC9S08AC128 MCU Series Data Sheet, Rev. 4 4 Freescale Semiconductor

Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 Device Pin Assignment Figure 2-1 shows the 80-pin LQFP package pin assignments for the MC9S08AC128 Series device. 4 2 1 1 5P P 11 1 PD D 1A A PTC5/RxD2PTC3/TxD2PTC2/MCLKPTH6/MISO2PTH5/MIOSI2PTH4/SPCK2PTC1/SDA1PTC0/SCL1V (NC)DDVSSPTG6/EXTALPTG5/XTALBKGD/MSVREFLVREFHPTD7/KBI1P7/ADPTD6/TPM1CLK/PTD5/AD1P13PTD4/TPM2CLK/PTG4/KBI1P4 09876543210987654321 PTC4 18777777777766666666660 PTG3/KBI1P3 IRQ/TPMCLK 2 59 PTD3/KBI1P6/AD1P11 RESET 3 58 PTD2/KBI1P5/AD1P10 PTF0/TPM1CH2 4 57 VSSAD PTF1/TPM1CH3 5 56 VDDAD PTF2/TPM1CH4 6 55 PTD1/AD1P9 PTF3/TPM1CH5 7 54 PTD0/AD1P8 PTF4/TPM2CH0 8 53 PTB7/AD1P7 PTC6 9 52 PTB6/AD1P6 PTF7 10 80-Pin 51 PTB5/AD1P5 PTF5/TPM2CH1 11 LQFP 50 PTB4/AD1P4 PTF6 12 49 PTB3/AD1P3 PTJ0 13 48 PTB2/AD1P2 PTJ1 14 47 PTB1/TPM3CH1/AD1P1 PTJ2 15 46 PTB0/TPM3CH0/AD1P0 PTJ3 16 45 PTH3/TPM2CH5 PTE0/TxD1 17 44 PTH2/TPM2CH4 PTE1/RxD1 18 43 PTH1/TPM2CH3 PTE2/TPM1CH0 19 42 PTH0/TPM2CH2 PTE3/TPM1CH1 20 41 PTA7 12345678901234567890 22222222233333333334 Note: Pin names in bold 1111 S D45670120123456 are lost in lower pin count PTE4/SSPTE5/MISOPTE6/MOSIPTE7/SPSCKVSVDPTJPTJPTJPTJPTG0/KBI1PPTG1/KBI1PPTG2/KBI1PPTAPTAPTAPTAPTAPTAPTA packages. Figure2-1. MC9S08AC128 Series in 80-Pin LQFP Package MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 5

Chapter2 Pins and Connections Figure 2-2 shows the 64-pin package assignments for the MC9S08AC128 Series devices. K L 7 C P 2 1 M PTC5/RxD2 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 VSS PTG6/EXTAL PTG5/XTAL BKGD/MS VREFL VREFH PTD7/AD1P15/KBI PTD6//TPM1CLK PTD5/AD1P13 PTD4/AD1P12/TP PTG4/KBI1P4 64 49 63 62 61 60 59 58 57 56 55 54 53 52 51 50 PTC4 1 48 PTG3/KBI1P3 IRQ/TPMCLK 2 47 PTD3/KBI1P6/AD1P11 RESET 3 46 PTD2KBI1P5/AD1P10 PTF0/TPM1CH2 4 45 VSSAD PTF1/TPM1CH3 5 44 V DDAD PTF2/TPM1CH4 6 43 PTD1/AD1P9 PTF3/TPM1CH5 7 42 PTD0/AD1P8 PTF4/TPM2CH0 8 41 PTB7/AD1P7 64-Pin QFP PTC6 9 40 PTB6/AD1P6 PTF7 10 39 PTB5/AD1P5 PTF5/TPM2CH1 11 38 PTB4/AD1P4 PTF6 12 37 PTB3/AD1P3 PTE0/TxD1 13 36 PTB2/AD1P2 PTE1/RxD1 14 35 PTB1/TPM3CH1/AD1P1 PTE2/TPM1CH0 15 34 PTB0/TPM3CH0/AD1P0 PTE3/TPM1CH1 16 33 PTA7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 17 32 Note: Pin names in bold PTE4/SS1 E5/MISO1 E6/MOSI1 7/SPSCK1 VSS VDD G0/KBI1P0 G1/KBI1P1 G2/KBI1P2 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 apraec kloasgte ins. lower pin count PT PT PTE PT PT PT Figure2-2. MC9S08AC128 Series in 64-Pin QFP Package MC9S08AC128 MCU Series Data Sheet, Rev. 4 6 Freescale Semiconductor

Chapter2 Pins and Connections Figure 2-1 shows the 48-pin package assignments for the MC9S08AC128 Series devices. PTC5/RxD2 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 VSS PTG6/EXTAL PTG5/XTAL BKGD/MS VREFL VREFH PTG4/KBI1P4 48 37 47 46 45 44 43 42 41 40 39 38 PTC4 1 36 PTG3/KBI1P3 IRQ/TPMCLK 2 35 PTD3/KBI1P6/AD1P11 RESET 3 34 PTD2KBI1P5/AD1P10 PTF0/TPM1CH2 4 33 VSSAD PTF1/TPM1CH3 5 32 VDDAD 48-Pin QFN PTF4/TPM2CH0 6 31 PTD1/AD1P9 PTF5/TPM2CH1 7 30 PTD0/AD1P8 PTF6 8 29 PTB3/AD1P3 PTE0/TxD1 9 28 PTB2/AD1P2 PTE1/RxD1 10 27 PTB1/TPM3CH1/AD1P1 PTE2/TPM1CH0 11 26 PTB0/TPM3CH0/AD1P0 PTE3/TPM1CH1 12 25 PTA7 14 15 16 17 18 19 20 21 22 23 13 24 PTE4/SS1 E5/MISO1 E6/MOSI1 7/SPSCK1 VSS VDD G0/KBI1P0 G1/KBI1P1 G2/KBI1P2 PTA0 PTA1 PTA2 PT PT PTE PT PT PT Note: Pin names in bold are lost in lower pin count packages. Figure2-1. MC9S08AC128 Series in 48-Pin QFN Package MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 7

Chapter2 Pins and Connections Figure 2-3 shows the 44-pin LQFP pin assignments for the MC9S08AC128 Series device. L PTC5/RxD2 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 VSS PTG6/EXTA PTG5/XTAL BKGD/MS VREFL VREFH 44 34 43 42 41 40 39 38 37 36 35 PTC4 1 33 PTG3/KBI1P3 IRQ/TPMCLK 2 32 PTD3/KBI1P6/AD1P11 RESET 3 31 PTD2/KBI1P5/AD1P10 PTF0/TPM1CH2 4 30 V SSAD PTF1/TPM1CH3 5 29 V DDAD 44-Pin LQFP PTF4/TPM2CH0 6 28 PTD1/AD1P9 PTF5/TPM2CH1 7 27 PTD0/AD1P8 PTE0/TxD1 8 26 PTB3/AD1P3 PTE1/RxD1 9 25 PTB2/AD1P2 PTE2/TPM1CH0 10 24 PTB1/TPM3CH1/AD1P1 PTE3/TPM1CH1 11 23 PTB0/TPM3CH0/AD1P0 13 14 15 16 17 18 19 20 21 12 22 1 1 1 1 S D 0 1 2 0 1 PTE4/SS PTE5/MISO PTE6/MOSI PTE7/SPSCK VS VD PTG0/KBI1P PTG1/KBI1P PTG2/KBI1P PTA PTA Figure2-3. MC9S08AC128 Series in 44-Pin LQFP Package Table2-4. Pin Availability by Package Pin-Count Pin Number Lowest <-- Priority --> Highest 80 64 48 44 Port Pin Alt 1 Alt 2 1 1 1 1 PTC4 2 2 2 2 IRQ TPMCLK1 3 3 3 3 RESET 4 4 4 4 PTF0 TPM1CH2 5 5 5 5 PTF1 TPM1CH3 6 6 — — PTF2 TPM1CH4 7 7 — — PTF3 TPM1CH5 8 8 6 6 PTF4 TPM2CH0 9 9 — — PTC6 10 10 — — PTF7 11 11 7 7 PTF5 TPM2CH1 12 12 8 — PTF6 MC9S08AC128 MCU Series Data Sheet, Rev. 4 8 Freescale Semiconductor

Chapter2 Pins and Connections Table2-4. Pin Availability by Package Pin-Count (continued) Pin Number Lowest <-- Priority --> Highest 80 64 48 44 Port Pin Alt 1 Alt 2 13 — — — PTJ0 14 — — — PTJ1 15 — — — PTJ2 16 — — — PTJ3 17 13 9 8 PTE0 TxD1 18 14 10 9 PTE1 RxD1 19 15 11 10 PTE2 TPM1CH0 20 16 12 11 PTE3 TPM1CH1 21 17 13 12 PTE4 SS1 22 18 14 13 PTE5 MISO1 23 19 15 14 PTE6 MOSI1 24 20 16 15 PTE7 SPSCK1 25 21 17 16 V SS 26 22 18 17 V DD 27 — — — PTJ4 28 — — — PTJ5 29 — — — PTJ6 30 — — — PTJ7 31 23 19 18 PTG0 KBI1P0 32 24 20 19 PTG1 KBI1P1 33 25 21 20 PTG2 KBI1P2 34 26 22 21 PTA0 35 27 23 22 PTA1 36 28 24 — PTA2 37 29 — — PTA3 38 30 — — PTA4 39 31 — — PTA5 40 32 — — PTA6 41 33 25 — PTA7 42 — — — PTH0 TPM2CH2 43 — — — PTH1 TPM2CH3 44 — — — PTH2 TPM2CH4 45 — — — PTH3 TPM2CH5 46 34 26 23 PTB0 TPM3CH0 AD1P0 47 35 27 24 PTB1 TPM3CH1 AD1P1 48 36 28 25 PTB2 AD1P2 49 37 29 26 PTB3 AD1P3 50 38 — — PTB4 AD1P4 51 39 — — PTB5 AD1P5 52 40 — — PTB6 AD1P6 53 41 — — PTB7 AD1P7 MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 9

Chapter2 Pins and Connections Table2-4. Pin Availability by Package Pin-Count (continued) Pin Number Lowest <-- Priority --> Highest 80 64 48 44 Port Pin Alt 1 Alt 2 54 42 30 27 PTD0 AD1P8 55 43 31 28 PTD1 AD1P9 56 44 32 29 V DDAD 57 45 33 30 V SSAD 58 46 34 31 PTD2 KBI1P5 AD1P10 59 47 35 32 PTD3 KBI1P6 AD1P11 60 48 36 33 PTG3 KBI1P3 61 49 37 — PTG4 KBI1P4 62 50 — — PTD4 TPM2CLK AD1P12 63 51 — — PTD5 AD1P13 64 52 — — PTD6 TPM1CLK AD1P14 65 53 — — PTD7 KBI1P7 AD1P15 66 54 38 34 V REFH 67 55 39 35 V REFL 68 56 40 36 BKGD MS 69 57 41 37 PTG5 XTAL 70 58 42 38 PTG6 EXTAL 71 59 43 39 V SS 72 — — — V (NC) DD 73 60 44 40 PTC0 SCL1 74 61 45 41 PTC1 SDA1 75 — — — PTH4 SPSCK2 76 — — — PTH5 MOSI2 77 — — — PTH6 MISO2 78 62 46 42 PTC2 MCLK 79 63 47 43 PTC3 TxD2 80 64 48 44 PTC5 RxD2 1 TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. MC9S08AC128 MCU Series Data Sheet, Rev. 4 10 Freescale Semiconductor

Chapter 3 Electrical Characteristics and Timing Specifications 3.1 Introduction This section contains electrical and timing specifications. 3.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table3-1. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table3-2 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V or V ). SS DD MC9S08AC128 Series Data Sheet, Rev. 4 Freescale Semiconductor 11

Chapter3 Electrical Characteristics and Timing Specifications Table3-2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage V –0.3 to + 5.8 V DD Input voltage V – 0.3 to V + 0.3 V In DD Instantaneous maximum current Single pin limit (applies to all port pins)1,2,3 ID  25 mA Maximum current into V I 120 mA DD DD Storage temperature Tstg –55 to +150 C 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (V ) and negative (V ) clamp DD SS voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V and V . SS DD 3 Power supply must maintain regulation within operating V range during instantaneous and DD operating maximum current conditions. If positive injection current (V > V ) is greater than In DD I , the injection current may flow out of V and could result in external power supply going DD DD out of regulation. Ensure external V load will shunt current greater than maximum injection DD current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. MC9S08AC128 Series Data Sheet, Rev. 4 12 Freescale Semiconductor

Chapter3 Electrical Characteristics and Timing Specifications 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take P into account in power calculations, determine the difference between I/O actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current SS DD (heavy loads), the difference between pin voltage and V or V will be very small. SS DD Table3-3. Thermal Characteristics Rating Symbol Value Unit T to T Operating temperature range (packaged) TA L H C –40 to 125 Maximum junction temperature T 150 C J Thermal resistance 1,2,3,4 80-pin LQFP 1s 61 2s2p 47 64-pin QFP 1s 57 2s2p JA 43 C/W 48-pin QFN 1s 81 2s2p 28 44-pin LQFP 1s 73 2s2p 56 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection 3 1s - Single Layer Board, one signal layer 4 2s2p - Four Layer Board, 2 signal and 2 power layers The average chip-junction temperature (T ) in C can be obtained from: J T = T + (P   ) Eqn.3-1 J A D JA where: T = Ambient temperature, C A  = Package thermal resistance, junction-to-ambient, C/W JA P = P P D int I/O P = I  V , Watts — chip internal power int DD DD P = Power dissipation on input and output pins — user determined I/O For most applications, P  P and can be neglected. An approximate relationship between P and T (if P is neglected) I/O int D J I/O is: P = K  (T + 273C) Eqn.3-2 D J MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 13

Chapter3 Electrical Characteristics and Timing Specifications Solving equations 1 and 2 for K gives: K = P  (T + 273C) +   (P )2 Eqn.3-3 D A JA D where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium) D for a known T . Using this value of K, the values of P and T can be obtained by solving equations 1 and 2 iteratively for any A D J value of T . A 3.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits and JEDEC Standard for Non-Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table3-4. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Series Resistance R1 1500  Human Body Storage Capacitance C 100 pF Number of Pulse per pin – 3 Series Resistance R1 0  Machine Storage Capacitance C 200 pF Number of Pulse per pin – 3 Minimum input voltage limit – 2.5 V Latch-up Maximum input voltage limit 7.5 V Table3-5. ESD and Latch-Up Protection Characteristics Num C Rating Symbol Min Max Unit 1 C Human Body Model (HBM) VHBM 2000 – V 2 C Machine Model (MM) VMM 200 – V 3 C Charge Device Model (CDM) VCDM 500 – V 4 C Latch-up Current at TA = 125C ILAT 100 – mA 3.6 DC Characteristics This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. MC9S08AC128 Series Data Sheet, Rev. 4 14 Freescale Semiconductor

Chapter3 Electrical Characteristics and Timing Specifications Table3-6. DC Characteristics Num C Parameter Symbol Min Typ1 Max Unit 1 — Operating Voltage V 2.7 — 5.5 V DD 2 P Output high voltage — Low Drive (PTxDSn = 0) 5 V, I = –2 mA V – 1.5 — — Load DD 3 V, I = –0.6 mA V – 1.5 — — Load DD 5 V, I = –0.4 mA V – 0.8 — — Load DD 3 V, I = –0.24 mA V – 0.8 — — Load DD V V P Output high voltage — High Drive (PTxDSn = 1) OH 5 V, I = –10 mA V – 1.5 — — Load DD 3 V, I = –3 mA V – 1.5 — — Load DD 5 V, I = –2 mA V – 0.8 — — Load DD 3 V, I = –0.4 mA V – 0.8 — — Load DD 3 P Output low voltage — Low Drive (PTxDSn = 0) 5 V, I = 2 mA — — 1.5 Load 3 V, I = 0.6 mA — — 1.5 Load 5 V, I = 0.4 mA — — 0.8 Load 3 V, I = 0.24 mA — — 0.8 Load V V P Output low voltage — High Drive (PTxDSn = 1) OL 5 V, I = 10 mA — — 1.5 Load 3 V, I = 3 mA — — 1.5 Load 5 V, I = 2 mA — — 0.8 Load 3 V, I = 0.4 mA — — 0.8 Load 4 P Output high current — Max total I for all ports OH 5V I — — 100 mA OHT 3V — — 60 5 P Output low current — Max total I for all ports OL 5V I — — 100 mA OLT 3V — — 60 6 P Input high 2.7v V 4.5v V 0.70xV — — DD IH DD voltage; all V 0.65xV — — V 4.5v V 5.5v IH DD digital inputs DD 7 P Input low voltage; all digital inputs V — — 0.35 x V IL DD 8 P Input hysteresis; all digital inputs V 0.06 x V mV hys DD 9 P Input leakage current; input only pins2 |I | — 0.1 1 A In 10 P High Impedance (off-state) leakage current2 |I | — 0.1 1 A OZ 11 P Internal pullup resistors3 R 20 45 65 k PU 12 P Internal pulldown resistors4 R 20 45 65 k PD 13 C Input Capacitance; all non-supply pins C — — 8 pF In 14 D RAM retention voltage V — 0.6 1.0 V RAM 15 P POR rearm voltage V 0.9 1.4 2.0 V POR 16 D POR rearm time t 10 — — s POR 17 P Low-voltage detection threshold — high range V falling V 4.2 4.3 4.4 V DD LVDH V rising 4.3 4.4 4.5 DD Low-voltage detection threshold — low range 18 P V falling V 2.48 2.56 2.64 V DD LVDL V rising 2.54 2.62 2.7 DD MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 15

Chapter3 Electrical Characteristics and Timing Specifications Table3-6. DC Characteristics (continued) Num C Parameter Symbol Min Typ1 Max Unit Low-voltage warning threshold — high range 19 P V falling V 4.2 4.3 4.4 V DD LVWH V rising 4.3 4.4 4.5 DD Low-voltage warning threshold — low range 20 P V 2.48 2.56 2.64 V V falling LVWL DD 2.54 2.62 2.7 V rising DD 21 Low-voltage inhibit reset/recover hysteresis P 5V V — 100 — mV hys 3V — 60 — 22 P Bandgap Voltage Reference5 V 1.170 1.200 1.230 V BG 1 Typical values are based on characterization data at 25C unless otherwise stated. 2 Measured with V = V or V . In DD SS 3 Measured with V = V . In SS 4 Measured with V = V . In DD 5 Factory trimmed at V = 3.0 V, Temperature = 25C. DD V –V (V) DD OH Average of I OH –6.0E-3 –5.0E-3 –40C 25C 125C –4.0E-3 A) –3.0E-3 (H O I –2.0E-3 –1.0E-3 000E+0 0 0.3 0.5 0.8 0.9 1.2 1.5 V –V Supply OH Figure3-1. Typical I (Low Drive) vs V –V at V = 3 V OH DD OH DD MC9S08AC128 Series Data Sheet, Rev. 4 16 Freescale Semiconductor

Chapter3 Electrical Characteristics and Timing Specifications Average of IOH VDD–VOH (V) –20.0E-3 –18.0E-3 –16.0E-3 –40C 25C –14.0E-3 125C –12.0E-3 –10.0E-3 A) –8.0E-3 (OH I –6.0E-3 –4.0E-3 –2.0E-3 000.0E-3 0 0.3 0.5 0.8 0.9 1.2 1.5 V –V Supply OH Figure3-2. Typical I (High Drive) vs V –V at V = 3 V OH DD OH DD Average of I OH –7.0E-3 –6.0E-3 –40C 25C –5.0E-3 125C –4.0E-3 A) –3.0E-3 (OH I –2.0E-3 –1.0E-3 000E+0 0.00 0.30 0.50 0.80 1.00 1.30 2.00 V –V (V) DD OH V –V Supply OH Figure3-3. Typical I (Low Drive) vs V –V at V = 5 V OH DD OH DD Average of IOH VDD–VOH (V) –30.0E-3 –25.0E-3 –40C –20.0E-3 25C 125C –15.0E-3 A) (H O –10.0E-3 I –5.0E-3 000.0E+3 0.00 0.30 0.50 0.80 1.00 1.30 2.00 V –V Supply OH Figure3-4. Typical I (High Drive) vs V –V at V = 5 V OH DD OH DD MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 17

Chapter3 Electrical Characteristics and Timing Specifications 3.7 Supply Current Characteristics Table3-7. Supply Current Characteristics Num C Parameter Symbol VDD Typ1 Max Unit Temp (V) (C) 2 5 1.1 1.43 Run supply current measured at 1 C RI mA –40 to 125C (CPU clock = 2MHz, f = 1 MHz) DD 3 1.0 1.2 Bus 4 5 6.7 8.05 Run supply current measured at 2 C RI mA –40 to 125C (CPU clock = 16MHz, f = 8 MHz) DD 3 6 7.5 Bus Stop2 mode supply current 5 25 A –40 to 85C 1.0 160 –40 to 125C 3 C 23 –40 to 85C S2I 3 A DD 0.8 150 –40 to 125C 27 –40 to 85C 5 A Stop3 mode supply current 1.2 1803 –40 to 125C 4 C S3I 25 –40 to 85C DD 3 A 1.0 170 –40 to 125C 500 –40 to 85C 5 300 nA 500 –40 to 125C 5 C RTI adder to stop2 or stop36 S23I 500 –40 to 85C DDRTI 3 300 nA 500 –40 to 125C 180 –40 to 85C 5 110 A 180 –40 to 125C 6 C LVD adder to stop3 (LVDE = LVDSE = 1) S3I DDLVD 160 –40 to 85C 3 90 A 160 –40 to 125C Adder to stop3 for oscillator enabled7 8 A –40 to 85C 7 C 5,3 5 (OSCSTEN =1) S3I 8 A –40 to 125C DDOSC 1 Typical values are based on characterization data at 25C unless otherwise stated. See Figure3-5 through Figure3-7 for typical curves across voltage/temperature. 2 All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins 3 Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization. 4 All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins 5 Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization. 6 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. Wait mode typical is 560 A at 3 V with f = 1 MHz. Bus 7 Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal, low power mode (HGO = 0), clock monitor disabled (LOCD = 1). MC9S08AC128 Series Data Sheet, Rev. 4 18 Freescale Semiconductor

Chapter3 Electrical Characteristics and Timing Specifications 18 16 20 MHz, ADC off, FEE, 25C 20 MHz, ADC off, FBE, 25C 14 12 10 I DD 8 8 MHz, ADC off, FEE, 25C 8 MHz, ADC off, FBE, 25C 6 4 1 MHz, ADC off, FEE, 25C 1 MHz, ADC off, FBE, 25C 2 0 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 V DD Note: External clock is square wave supplied by function generator. For FEE mode, external reference frequency is 4 MHz Figure3-5. Typical Run I for FBE and FEE Modes, I vs. V DD DD DD MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 19

Chapter3 Electrical Characteristics and Timing Specifications –40C Stop2 I (A) 25C DD 55C 85C Average of Measurement I DD –8.0E-3 –7.0E-3 –6.0E-3 –5.0E-3 A) (D –4.0E-3 D I –3.0E-3 –2.0E-3 –1.0E-3 000E+0 1.8 2 2.5 3 3.5 4 4.5 5 V (V) DD Figure3-6. Typical Stop 2 I DD –40C Stop3 I (A) 25C DD 55C 85C Average of Measurement I DD –8.0E-3 –7.0E-3 –6.0E-3 –5.0E-3 A) (D –4.0E-3 D I –3.0E-3 –2.0E-3 –1.0E-3 000E+0 1.8 2 2.5 3 3.5 4 4.5 5 V (V) DD Figure3-7. Typical Stop3 I DD MC9S08AC128 Series Data Sheet, Rev. 4 20 Freescale Semiconductor

Chapter3 Electrical Characteristics and Timing Specifications 3.8 ADC Characteristics Table3-8. 5 Volt 10-bit AD C Operating Conditions Characteristic Conditions Symb Min Typ1 Max Unit Absolute V 2.7 — 5.5 V DDAD Supply voltage Delta to V (V –V )2 V –100 0 +100 mV DD DD DDAD DDAD Ground voltage Delta to V (V –V )2 V –100 0 +100 mV SS SS SSAD SSAD Ref voltage high VREFH 2.7 VDDAD VDDAD V Ref voltage low VREFL VSSAD VSSAD VSSAD V Supply current Stop, reset, module off I — 0.011 1 A DDAD Input voltage V V — V V ADIN REFL REFH Input capacitance C — 4.5 5.5 pF ADIN Input resistance R — 3 5 k ADIN 10-bit mode f > 4MHz — — 5 Analog source resistance ADCK External to MCU fADCK < 4MHz RAS — — 10 k 8-bit mode (all valid f ) — — 10 ADCK High speed (ADLPC = 0) 0.4 — 8.0 ADC conversion clock frequency f MHz ADCK Low power (ADLPC = 1) 0.4 — 4.0 –40C to 25C 3.266 — Temp Sensor mV/ m Slope — C 25C to 125C 3.638 — Temp Sensor 25C V 1.396 — V Voltage TEMP25 — 1 Typical values assume V = 5.0 V, Temp = 25C, f = 1.0MHz unless otherwise stated. Typical values are for reference DDAD ADCK only and are not tested in production. 2 dc potential difference. MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 21

Chapter3 Electrical Characteristics and Timing Specifications SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad ZAS leakage CHANNEL SELECT due to CIRCUIT ADC SAR R input R ENGINE AS protection ADIN + V ADIN – C V + AS AS – R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure3-8. ADC Input Impedance Equivalency Diagram MC9S08AC128 Series Data Sheet, Rev. 4 22 Freescale Semiconductor

Chapter3 Electrical Characteristics and Timing Specifications Table3-9. 5 Volt 10-bit ADC Character istics (V = V , V = V ) REFH DDAD REFL SSAD Characteristic Conditions C Symb Min Typ1 Max Unit Supply current T I — 133 — A DDAD ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply current T I — 218 — A DDAD ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply current T I — 327 — A DDAD ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply current T I — 582 — A DDAD ADLPC = 0 ADLSMP = 0 P — — 1 mA V < 5.5 V DDAD ADCO = 1 High speed (ADLPC = 0) f 2 3.3 5 MHz ADC asynchronous clock source P ADACK t = 1/f ADACK ADACK Low power (ADLPC = 1) 1.25 2 3.3 Conversion time Short sample (ADLSMP = 0) P t — 20 — ADCK ADC (Including sample time) cycles Long sample (ADLSMP = 1) — 40 — Short sample (ADLSMP = 0) P t — 3.5 — ADCK Sample time ADS cycles Long sample (ADLSMP = 1) — 23.5 — 10-bit mode P E — 1 2.5 LSB2 Total unadjusted error TUE Includes quantization 8-bit mode — 0.5 1.0 10-bit mode P DNL — 0.5 1.0 LSB2 Differential non-linearity 8-bit mode — 0.3 0.5 Monotonicity and no-missing-codes guaranteed 10-bit mode C INL — 0.5 1.0 LSB2 Integral non-linearity 8-bit mode — 0.3 0.5 10-bit mode E — 0.5 1.5 LSB2 Zero-scale error P ZS V = V ADIN SSA 8-bit mode — 0.5 0.5 10-bit mode E — 0.5 1.5 LSB2 Full-scale error P FS V = V ADIN DDA 8-bit mode — 0.5 0.5 10-bit mode D E — — 0.5 LSB2 Q Quantization error 8-bit mode — — 0.5 MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 23

Chapter3 Electrical Characteristics and Timing Specifications Table3-9. 5 Volt 10-bit ADC Characteristics (V = V , V = V ) REFH DDAD REFL SSAD Characteristic Conditions C Symb Min Typ1 Max Unit 10-bit mode D E — 0.2 2.5 LSB2 Input leakage error IL Pad leakage3 * R AS 8-bit mode — 0.1 1 1 Typical values assume V = 5.0V, Temp = 25C, f =1.0 MHz unless otherwise stated. Typical values are for reference DDAD ADCK only and are not tested in production. 2 1 LSB = (V – V )/2N REFH REFL 3 Based on input pad leakage current. Refer to pad electricals. 3.9 Internal Clock Generation Module Characteristics ICG EXTAL XTAL R R S F Crystal or Resonator C 1 C 2 Table3-10. ICG DC Electrical Specifications (Temperature Range = –40 to 125C Ambient) Characteristic Symbol Min Typ1 Max Unit C Load capacitors 1 See Note 2 C 2 Feedback resistor Low range (32k to 100 kHz) R 10 M F High range (1M – 16 MHz) 1 M Series resistor Low range Low Gain (HGO = 0) — 0 — High Gain (HGO = 1) — 100 — High range R k Low Gain (HGO = 0) S — 0 — High Gain (HGO = 1)  8 MHz — 0 — 4 MHz — 10 — MHz — 20 — 1 Typical values are based on characterization data at V = 5.0V, 25C or is typical recommended value. DD 2 See crystal or resonator manufacturer’s recommendation. MC9S08AC128 Series Data Sheet, Rev. 4 24 Freescale Semiconductor

Chapter3 Electrical Characteristics and Timing Specifications 3.9.1 ICG Frequency Specifications Table3-11. ICG Frequ ency Specifications (V = V (min) to V (max), Temperature Range = –40 to 125C Ambient) DDA DDA DDA Num C Characteristic Symbol Min Typ1 Max Unit Oscillator crystal or resonator (REFS = 1) (Fundamental mode crystal or ceramic resonator) Low range flo 32 — 100 kHz High range 1 High Gain, FBE (HGO = 1,CLKS = 10) fhi_byp 1 — 16 MHz High Gain, FEE (HGO = 1,CLKS = 11) fhi_eng 2 — 10 MHz Low Power, FBE (HGO = 0, CLKS = 10) flp_byp 1 8 MHz Low Power, FEE (HGO = 0, CLKS = 11) flp_eng 2 8 MHz Input clock frequency (CLKS=11, REFS=0) 2 Low range flo 32 — 100 kHz High range fhi_eng 2 — 10 MHz 3 Input clock frequency (CLKS=10, REFS=0) fExtal 0 — 40 MHz 4 Internal reference frequency (untrimmed) fICGIRCLK 182.25 243 303.75 kHz 5 Duty cycle of input clock (REFS=0) tdc 40 — 60 % Output clock ICGOUT frequency f (max) 6 CLKS=10, REFS=0 fICGOUT fExtal (min) — f Extal ( MHz All other cases f (min) — ICGDCLKmax lo max) 7 Minimum DCO clock (ICGDCLK) frequency fICGDCLKmin 3 — MHz 8 Maximum DCO clock (ICGDCLK) frequency fICGDCLKmax — 40 MHz 9 Self-clock mode (ICGOUT) frequency 2 fSelf fICGDCLKmin fICGDCLKmax MHz 10 Self-clock mode reset (ICGOUT) frequency fSelf_reset 5.5 8 10.5 MHz Loss of reference frequency 3 11 Low range fLOR 5 25 kHz High range 50 500 12 Loss of DCO frequency 4 fLOD 0.5 1.5 MHz Crystal start-up time 5, 6 t CSTL 13 Low range — 430 — t ms High range CSTH — 4 — FLL lock time , 7 t Lockl 14 Low range — 2 ms t High range Lockh — 2 15 FLL frequency unlock range nUnlock –4*N 4*N counts 16 FLL frequency lock range nLock –2*N 2*N counts ICGOUT period jitter, , 8 measured at f Max 17 Long term jitter (averaged over 2 msIC iGnOteUrTval) CJitter — 0.2 % fICG Internal oscillator deviation from trimmed frequency9 0.5 18 — 2 VDD = 2.7 – 5.5 V, (constant temperature) ACCint — 0.5 2 % V = 5.0 V 10%, –40 C to 125C DD 1 Typical values are based on characterization data at V = 5.0V, 25C unless otherwise stated. DD 2 Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop. MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 25

Chapter3 Electrical Characteristics and Timing Specifications 3 Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it is not in the desired range. 4 Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode (if an external reference exists) if it is not in the desired range. 5 This parameter is characterized before qualification rather than 100% tested. 6 Proper PC board layout procedures must be followed to achieve specifications. 7 This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external modes. If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . ICGOUT Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via V and V and variation in crystal oscillator frequency increase the C percentage for DDA SSA Jitter a given interval. 9 See Figure3-9 Average of Percentage Error Variable 3 V 5 V Figure3-9. Internal Oscillator Deviation from Trimmed Frequency MC9S08AC128 Series Data Sheet, Rev. 4 26 Freescale Semiconductor

Chapter3 Electrical Characteristics and Timing Specifications 3.10 AC Characteristics This section describes ac timing characteristics for each peripheral system. 3.10.1 Control Timing Table3-12. Co ntrol Timing Num C Parameter Symbol Min Typ1 Max Unit 1 Bus frequency (tcyc = 1/fBus) fBus dc — 20 MHz 2 Real-time interrupt internal oscillator period tRTI 600 1500 s  External reset pulse width2 1.5 x (tcyc = 1/fSelf_reset) textrst tSelf_reset — ns 4 Reset low drive3 trstdrv 34 x tcyc — ns 5 Active background debug mode latch setup time tMSSU 25 — ns 6 Active background debug mode latch hold time tMSH 25 — ns IRQ pulse width 7 Asynchronous path2 t t 100 — — ns ILIH, IHIL Synchronous path4 1.5 x t cyc 8 KBIPx pulse width Asynchronous path2 t t 100 — — ns ILIH, IHIL Synchronous path3 1.5 x t cyc Port rise and fall time (load = 50 pF)5 9 Slew rate control disabled (PTxSE = 0) tRise, tFall — 3 ns Slew rate control enabled (PTxSE = 1) — 30 1 Typical values are based on characterization data at V = 5.0V, 25C unless otherwise stated. DD 2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 When any reset is initiated, internal circuitry drives the reset pin low for about 34bus cycles and then samples the level on the reset pin about 38bus cycles later to distinguish external reset requests from internal requests. 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 5 Timing is shown with respect to 20% V and 80% V levels. Temperature range –40C to 125C. DD DD t extrst RESET PIN Figure3-10. Reset Timing MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 27

Chapter3 Electrical Characteristics and Timing Specifications BKGD/MS RESET t MSH t MSSU Figure3-11. Active Background Debug Mode Latch Timing t IHIL IRQ/KBIP7-KBIP4 IRQ/KBIPx t ILIH Figure3-12. IRQ/KBIPx Timing 3.10.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table3-13. TPM Input Timing Function Symbol Min Max Unit External clock frequency fTPMext dc fBus/4 MHz External clock period tTPMext 4 — tcyc External clock high time tclkh 1.5 — tcyc External clock low time tclkl 1.5 — tcyc Input capture pulse width tICPW 1.5 — tcyc MC9S08AC128 Series Data Sheet, Rev. 4 28 Freescale Semiconductor

Chapter3 Electrical Characteristics and Timing Specifications t TPMext t clkh TPMxCLK t clkl Figure3-13. Timer External Clock t ICPW TPMxCHn TPMxCHn t ICPW Figure3-14. Timer Input Capture Pulse MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 29

Chapter3 Electrical Characteristics and Timing Specifications 3.11 SPI Characteristics Table3-14 and Figure3-15 through Figure3-18 describe the timing requirements for the SPI system. Table3-14. SPI Electrical Characteristic Num1 C Characteristic2 Symbol Min Max Unit Operating frequency3 Master fop fBus/2048 fBus/2 Hz Slave f dc f /4 op Bus 1 Cycle time Master tSCK 2 2048 tcyc Slave tSCK 4 — tcyc 2 Enable lead time Master t — 1/2 t Lead SCK Slave t 1/2 — t Lead SCK 3 Enable lag time Master t — 1/2 t Lag SCK Slave t 1/2 — t Lag SCK 4 Clock (SPSCK) high time Master and Slave tSCKH 1/2 tSCK – 25 — ns 5 Clock (SPSCK) low time Master and Slave tSCKL 1/2 tSCK – 25 — ns 6 Data setup time (inputs) Master t 30 — ns SI(M) Slave t 30 — ns SI(S) 7 Data hold time (inputs) Master t 30 — ns HI(M) Slave t 30 — ns HI(S) 8 Access time, slave4 t 0 40 ns A 9 Disable time, slave5 t — 40 ns dis 10 Data setup time (outputs) Master t 25 — ns SO Slave t 25 — ns SO 11 Data hold time (outputs) Master t –10 — ns HO Slave t –10 — ns HO 1 Refer to Figure3-15 through Figure3-18. 2 All timing is shown with respect to 20% V and 70% V , unless noted; 100 pF load on all SPI DD DD pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Maximum baud rate must be limited to 5 MHz due to pad input characteristics. 4 Time to data active from high-impedance state. 5 Hold time to high-impedance state. MC9S08AC128 Series Data Sheet, Rev. 4 30 Freescale Semiconductor

Chapter3 Electrical Characteristics and Timing Specifications SS1 (OUTPUT) 2 1 3 SCK 5 (CPOL = 0) (OUTPUT) 4 SCK 5 (CPOL = 1) 4 (OUTPUT) 6 7 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 10 10 11 MOSI MSB OUT2 BIT 6 . . . 1 LSB OUT (OUTPUT) NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure3-15. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 3 SCK 5 (CPOL = 0) (OUTPUT) 4 SCK 5 (CPOL = 1) 4 (OUTPUT) 6 7 MISO (INPUT) MSB IN(2) BIT 6 . . . 1 LSB IN 10 11 MOSI MSB OUT(2) BIT 6 . . . 1 LSB OUT (OUTPUT) NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure3-16. SPI Master Timing (CPHA = 1) MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 31

Chapter3 Electrical Characteristics and Timing Specifications SS (INPUT) 1 3 SCK 5 (CPOL = 0) (INPUT) 4 2 SCK 5 (CPOL = 1) (INPUT) 4 9 8 10 11 MISO SEE (OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure3-17. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 SCK (CPOL = 0) 5 (INPUT) 4 SCK 5 (CPOL = 1) 4 (INPUT) 10 11 9 MISO SEE (OUTPUT) NOTE SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT 8 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure3-18. SPI Slave Timing (CPHA = 1) MC9S08AC128 Series Data Sheet, Rev. 4 32 Freescale Semiconductor

Chapter3 Electrical Characteristics and Timing Specifications 3.12 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal V supply. DD Table3-15. Flash Characteristics Num C Characteristic Symbol Min Typ1 Max Unit 1 P Supply voltage for program/erase Vprog/erase 2.7 5.5 V 2 P Supply voltage for read operation VRead 2.7 5.5 V  P Internal FCLK frequency2 fFCLK 150 200 kHz 4 P Internal FCLK period (1/FCLK) tFcyc 5 6.67 s 5 P Byte program time (random location)(2) tprog 9 tFcyc 6 C Byte program time (burst mode)(2) tBurst 4 tFcyc 7 P Page erase time3 tPage 4000 tFcyc 8 P Mass erase time(2) tMass 20,000 tFcyc Program/erase endurance4 9 C T to T = –40C to + 125C 10,000 — — cycles L H T = 25C — 100,000 — 10 C Data retention5 tD_ret 15 100 — years 1 Typical values are based on characterization data at V = 5.0 V, 25C unless otherwise stated. DD 2 The frequency of this clock is controlled by a software setting. 3 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 4 Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 33

Chapter3 Electrical Characteristics and Timing Specifications 3.13 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 3.13.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device. The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table3-16. Radiated Emissions Level1 Parameter Symbol Conditions Frequency f /f Unit OSC BUS (Max) V V = 5.0 V 0.15 – 50 MHz 32kHz crystal 30 dBV RE_TEM DD T = +25oC 20MHz Bus A 50 – 150 MHz 32 package type 80 LQFP 150 – 500 MHz 19 Radiated emissions, electric field and magnetic field 500 – 1000 MHz 7 IEC Level I2 — SAE Level I2 — 1 Data based on laboratory test results. 2 IEC and SAE Level Maximums: I=36 dBuV. MC9S08AC128 Series Data Sheet, Rev. 4 34 Freescale Semiconductor

Chapter 4 Ordering Information and Mechanical Drawings 4.1 Ordering Information This section contains ordering numbers for MC9S08AC128 Series devices. See below for an example of the device numbering system. Table4-1. Device Numbering System Memory Available Packages1 Device Number FLASH RAM Type MC9S08AC128 128K 8K 80 LQFP, 64 QFP, 48-QFN, 44-LQFP MC9S08AC96 96K 6K 80 LQFP, 64 QFP, 48-QFN, 44-LQFP 1 See Table4-2 for package information. 4.2 Orderable Part Numbering System MC 9 S08AC128C XX E Pb free indicator Status (MC = Fully Qualified) Package designator (See Table4-2) Memory Temperature range (9 = FLASH-based) (C = –40C to 85C) Core (M = –40C to 125C) Family Approximate memory size (in KB) 4.3 Mechanical Drawings Table4-2 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MC9S08AC128 Series Product Summary pages at http://www.freescale.com. To view the latest drawing, either: • Click on the appropriate link in Table4-2, or • Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number (from Table4-2) in the “Enter Keyword” search box at the top of the page. Table4-2. Package Information Pin Count Type Designator Document No. 80 LQFP LK 98ASS23237W 64 QFP FU 98ASB42844B 48 QFN FT 98ARH99048A 44 LQFP FG 98ASS23225W MC9S08AC128 Series Data Sheet, Rev. 4 Freescale Semiconductor 35

Chapter4 Ordering Information and Mechanical Drawings MC9S08AC128 Series Data Sheet, Rev. 4 36 Freescale Semiconductor

Chapter 5 Revision History To provide the most up-to-date information, the version of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Revision Description of Changes Number Date Initial release of a separate data sheet and reference manual. Removed PTH7, clarified SPI as one full and one master-only, added missing RoHS logo, updated 1 9/2008 back cover addresses, and incorporated general release edits and updates. Added some finalized electrical characteristics. Added the parameter “Bandgap Voltage Reference” in Table3-6 2 6/2009 Updated Section 3.13, “EMC Performance” and corrected Table3-16. Updated disclaimer page. 3 9/2010 Added 48-pin QFN package information. Updated the t in the Table3-12. 4 8/2011 RTI Updated the RI in the Table3-7. DD MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 37

MC9S08AC128 MCU Series Data Sheet, Rev. 4 Freescale Semiconductor 38

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