MC68HC908JL16 Data Sheet M68HC08 Microcontrollers MC68HC908JL16 Rev. 1.1 11/2005 freescale.com

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MC68HC908JL16 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. ©Freescale Semiconductor, Inc., 2005. All rights reserved. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 3

Revision History Revision History Revision Page Date Description Level Number(s) November, 1.1 Order part number: MC908JL16CFAE changed to MC908JL16CFJE. 217 2005 November, 1 First general release. N/A 2005 MC68HC908JL16 Data Sheet, Rev. 1.1 4 Freescale Semiconductor

List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Chapter 2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Chapter 3 Configuration and Mask Option Registers (CONFIG and MOR) . . . . . . . . . . . .41 Chapter 4 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Chapter 5 Oscillator (OSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Chapter 6 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Chapter 7 Serial Communications Interface (SCI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Chapter 8 Multi-Master IIC Interface (MMIIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Chapter 9 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Chapter 10 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Chapter 11 External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Chapter 12 Keyboard Interrupt Module (KBI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Chapter 13 Computer Operating Properly (COP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 Chapter 14 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Chapter 15 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Chapter 16 Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 Chapter 17 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 Chapter 18 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . .217 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 5

List of Chapters MC68HC908JL16 Data Sheet, Rev. 1.1 6 Freescale Semiconductor

Table of Contents Chapter 1 General Description 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5 Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 2 Memory Map 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 I/O Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4 Random-Access Memory (RAM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5 FLASH Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5.2 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.5.3 FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.5.4 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.5.5 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5.6 FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.5.7 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Chapter 3 Configuration and Mask Option Registers (CONFIG and MOR) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3 Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4 Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.5 Mask Option Register (MOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Chapter 4 System Integration Module (SIM) 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 SIM Bus Clock Control and Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.1 Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.2 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 7

Table of Contents 4.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3.1 External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3.2.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.5.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.5.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.5.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.5.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.5.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.6 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.7.1 Break Status Register (BSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.7.2 Reset Status Register (RSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.7.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Chapter 5 Oscillator (OSC) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2 Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.1 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2.2 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3 Internal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.4 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.4.2 Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6) . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.4.3 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.4.4 XTAL Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4.5 RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4.6 Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4.7 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4.8 Internal Oscillator Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 MC68HC908JL16 Data Sheet, Rev. 1.1 8 Freescale Semiconductor

5.5 Low Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.6 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Chapter 6 Timer Interface Module (TIM) 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.1 TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.2 Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.4 Pulse Width Modulation (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.4.3 PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.8 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.8.1 TIM Clock Pin (ADC12/T2CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.8.2 TIM Channel I/O Pins (PTD4/T1CH0, PTD5/T1CH1, PTE0/T2CH0, PTE1/T2CH1). . . . . . 77 6.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.9.2 TIM Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Chapter 7 Serial Communications Interface (SCI) 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.4.1 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.4.2 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.2.2 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 9

Table of Contents 7.4.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.3 Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.4.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.4.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.6 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.7 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.7.1 TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.7.2 RxD (Receive Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.8.1 SCI Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.8.2 SCI Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.8.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.8.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.8.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.8.7 SCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Chapter 8 Multi-Master IIC Interface (MMIIC) 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4.1 IIC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4.2 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4.3 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.4.4 Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.4.5 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.4.6 Repeated START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.7 Arbitration Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.8 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.9 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.10 Clock Stretching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.11 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.6 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 MC68HC908JL16 Data Sheet, Rev. 1.1 10 Freescale Semiconductor

8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.7 MMIIC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.8 Multi-Master IIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.8.1 Multi-Master IIC Address Register (MMADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.8.2 Multi-Master IIC Control Register (MMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.8.3 Multi-Master IIC Master Control Register (MIMCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.8.4 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.8.5 Multi-Master IIC Data Transmit Register (MMDTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.8.6 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.9 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Chapter 9 Analog-to-Digital Converter (ADC) 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.3.1 Clock Select and Divide Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.3.2 Input Select and Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.3.3 Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.3.3.1 Initiating Conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.3.3.2 Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.3.3.3 Aborting Conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.3.3.4 Total Conversion Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.3.4 Sources of Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.3.4.1 Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.3.4.2 Pin Leakage Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.3.4.3 Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.3.4.4 Code Width and Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.3.4.5 Linearity Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.5 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.6 ADC10 During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.7 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.7.1 ADC10 Analog Power Pin (VDDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.7.2 ADC10 Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.7.3 ADC10 Voltage Reference High Pin (VREFH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.7.4 ADC10 Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.7.5 ADC10 Channel Pins (ADn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.8.1 ADC10 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.8.2 ADC10 Result High Register (ADRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.8.3 ADC10 Result Low Register (ADRL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.8.4 ADC10 Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 11

Table of Contents Chapter 10 Input/Output (I/O) Ports 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.2 Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.2.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.2.2 Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.2.3 Port A Input Pull-Up Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.3 Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.3.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.3.2 Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.4 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10.4.1 Port D Data Register (PTD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.4.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.4.3 Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.5 Port E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.5.1 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.5.2 Data Direction Register E (DDRE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Chapter 11 External Interrupt (IRQ) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.3.1 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.4 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5 IRQ Status and Control Register (INTSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Chapter 12 Keyboard Interrupt Module (KBI) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.5 Keyboard Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.5.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.5.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.6 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.7 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Chapter 13 Computer Operating Properly (COP) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 MC68HC908JL16 Data Sheet, Rev. 1.1 12 Freescale Semiconductor

13.3 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 13.3.1 ICLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 13.3.2 COPCTL Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 13.3.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 13.3.4 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 13.3.5 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 13.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 13.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.6 Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.7 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Chapter 14 Low-Voltage Inhibit (LVI) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.4 LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.5 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Chapter 15 Central Processor Unit (CPU) 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.3 CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.3.1 Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.5 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.6 CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 13

Table of Contents Chapter 16 Development Support 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.2.2 Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.2.3 CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.2.4 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.2.5 COP During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.2.6 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.2.6.1 Break Status and Control Register (BRKSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.2.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.2.6.3 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.2.6.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.2.7 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.2.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.2.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.3.2 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 16.3.3 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 16.3.4 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 16.3.5 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 16.3.6 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.3.7 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.3.8 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16.3.9 ROM-Resident Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16.3.9.1 PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 16.3.9.2 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.3.9.3 LDRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.3.9.4 MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.3.9.5 MON_ERARNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.3.9.6 MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16.3.9.7 EE_WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16.3.9.8 EE_READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Chapter 17 Electrical Specifications 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 17.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 17.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 17.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 17.5 5-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 17.6 5-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 17.7 5-V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 17.8 3-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 17.9 3-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 MC68HC908JL16 Data Sheet, Rev. 1.1 14 Freescale Semiconductor

17.10 3-V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 17.11 Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 17.12 Timer Interface Module Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 17.13 ADC10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 17.14 MMIIC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 17.15 Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Chapter 18 Ordering Information and Mechanical Specifications 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 18.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 18.3 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 15

Table of Contents MC68HC908JL16 Data Sheet, Rev. 1.1 16 Freescale Semiconductor

Chapter 1 General Description 1.1 Introduction The MC68HC908JL16 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.2 Features Features include: (cid:127) High-performance M68HC08 architecture (cid:127) Fully upward-compatible object code with M6805, M146805, and M68HC05 Families (cid:127) Low-power design; fully static with stop and wait modes (cid:127) Maximum internal bus frequency: – 8-MHz at 5-V operating voltage – 4-MHz at 3-V operating voltage (cid:127) Oscillator options: – Crystal or resonator – RC oscillator (cid:127) 16,384 bytes user program FLASH memory with security(1) (cid:127) 512 bytes of on-chip random-access memory (RAM) (cid:127) Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, and pulse-width modulation (PWM) capability on each channel; external clock input option on TIM2 (cid:127) 13-channel, 10-bit analog-to-digital converter with internal bandgap reference channel (ADC10) (cid:127) Serial communications interface module (SCI) (cid:127) Multi-master IIC module (MMIIC) (cid:127) Up to 26 general-purpose input/output (I/O) ports: – 8 keyboard interrupt with internal pull up – 11 LED drivers (sink) – 2 × 25 mA open-drain I/O with pull up – Inputs contain hysteresis buffer for improved noise immunity (cid:127) Resident routines for in-circuit programming and EEPROM emulation (cid:127) System protection features: – Optional computer operating properly (COP) reset, driven by internal RC oscillator – Optional low-voltage detection with reset and selectable trip points for 3-V and 5-V operation – Illegal opcode detection with reset – Illegal address detection with reset 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 17

General Description (cid:127) Master reset pin with internal pull-up and power-on reset (cid:127) IRQ with schmitt-trigger input and programmable pull up (cid:127) The MC68HC908JL16 is available in the following packages: – 28-pin plastic dual in-line package (PDIP) – 28-pin small outline integrated package (SOIC) – 32-pin shrink dual in-line package (SDIP) – 32-pin low-profile quad flat pack (LQFP) (cid:127) Specific features in 28-pin packages are: – 23 general-purpose I/Os only – 7 keyboard interrupt with internal pull up – 10 light-emitting diode (LED) drivers (sink) – 12-channel ADC – Timer I/O pins on TIM1 only Features of the CPU08 include the following: (cid:127) Enhanced HC05 programming model (cid:127) Extensive loop control functions (cid:127) 16 addressing modes (eight more than the HC05) (cid:127) 16-bit index register and stack pointer (cid:127) Memory-to-memory data transfers (cid:127) Fast 8 × 8 multiply instruction (cid:127) Fast 16/8 divide instruction (cid:127) Binary-coded decimal (BCD) instructions (cid:127) Optimization for controller applications (cid:127) Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908JL16. MC68HC908JL16 Data Sheet, Rev. 1.1 18 Freescale Semiconductor

MCU Block Diagram INTERNAL BUS M68HC08 CPU KEYBOARD INTERRUPT PTA7/KBI7(3)(4) (7) CPU ARITHMETIC/LOGIC MODULE PTA6/KBI6(1)(3) REGISTERS UNIT (ALU) PTA5/KBI5(3)(4) CONTROL AND STATUS REGISTERS — 64 BYTES 10-CBOITN AVNEARLTOEGR- TMOO-DDUIGLIETAL DDRA PORTA PPPTTTAAA432///KKKBBBIII432(//3SS)CD(4LA)((33))((44))((66)) PTA1/KBI1(3)(4) USER FLASH — 16,384 BYTES PTA0/KBI0(3)(4) 2-CHANNEL TIMER INTERFACE MODULE 1 PTB7/ADC7 USER RAM — 512 BYTES PTB6/ADC6 2-CHANNEL TIMER PTB5/ADC5 MONITOR ROM — 959 BYTES INTERFACE MODULE 2 DDRB PORTB PPTTBB43//AADDCC43 PTB2/ADC2 USER FLASH VECTORS — 36 BYTES BREAK PTB1/ADC1 MODULE PTB0/ADC0 ADC12/T2CLK (7) CRYSTAL OSCILLATOR OSC1 SERIAL COMMUNICATIONS PTD7/RxD/SDA(3)(4)(5)(6) INTERFACE MODULE OSC2/RCCLK(1) RC OSCILLATOR PTD6/TxD/SCL(3)(4)(5)(6) PTD5/T1CH1 INTERNAL OSCILLATOR POWEMRO-DOUNL REESET DDRD PORTD PPPTTTDDD324///AAT1DDCCCH890((44)) PTD1/ADC10 RST(2) SYSTEM INTEGRATION LOW-VOLTAGE INHIBIT PTD0/ADC11 MODULE MODULE IRQ(2) EXTERNMAOLD IUNLTEERRUPT COPRMOPPUETRERLY O MPOERDAUTLIENG DDRE PORTE PPTTEE10//TT22CCHH10 (7) MULTI-MASTER IIC V DD MODULE POWER V SS ADC REFERENCE NOTES: 1.Shared pin: OSC2/RCCLK/PTA6/KBI6 2.Pin contains integrated pull-up device 3.Pin contains programmable pull-up device 4.LED direct sink pin 5.25-mA output drive pin 6.Pin is open-drain output when MMIIC function enabled; position of SDA and SCL are selected in CONFIG2 register. 7.Pins available on 32-pin packages only Figure 1-1. MC68HC908JL16 Block Diagram MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 19

General Description 1.4 Pin Assignments K L 0 C H BI0 T2 BI7 BI5 1C VSS PTA0/K IRQ ADC12/ PTA7/K RST PTA5/K PTD4/T 32 25 OSC1 1 31 30 29 28 27 26 24 PTD5/T1CH1 OSC2/RCCLK/PTA6/KBI6 2 23 PTD2/ADC9 PTA1/KBI1 3 22 PTA4/KBI4 V 4 21 PTD3/ADC8 DD PTA2/KBI2/SDA 5 20 PTB0/ADC0 PTA3/KBI3/SCL 6 19 PTB1/ADC1 PTB7/ADC7 7 18 PTD1/ADC10 PTB6/ADC6 8 17 PTB2/ADC2 0 1 2 3 4 5 1 1 1 1 1 1 9 16 5 A L 0 1 4 1 3 C D C H H C 1 C D S S C C D C D B5/A RxD/ TxD/ 0/T2 1/T2 B4/A 0/AD B3/A PT PTD7/ PTD6/ PTE PTE PT PTD PT Figure 1-2. 32-Pin LQFP Pin Assignment IRQ 1 32 ADC12/T2CLK PTA0/KBI0 2 31 PTA7/KBI7 V 3 30 RST SS OSC1 4 29 PTA5/KBI5 OSC2/RCCLK/PTA6/KBI6 5 28 PTD4/T1CH0 PTA1/KBI1 6 27 PTD5/T1CH1 V 7 26 PTD2/ADC9 DD PTA2/KBI2/SDA 8 25 PTA4/KBI4 PTA3/KBI3/SCL 9 24 PTD3/ADC8 PTB7/ADC7 10 23 PTB0/ADC0 PTB6/ADC6 11 22 PTB1/ADC1 PTB5/ADC5 12 21 PTD1/ADC10 PTD7/RxD/SDA 13 20 PTB2/ADC2 PTD6/TxD/SCL 14 19 PTB3/ADC3 PTE0/T2CH0 15 18 PTD0/ADC11 PTE1/T2CH1 16 17 PTB4/ADC4 Figure 1-3. 32-Pin SDIP Pin Assignment MC68HC908JL16 Data Sheet, Rev. 1.1 20 Freescale Semiconductor

Pin Functions IRQ 1 28 RST PTA0/KBI0 2 27 PTA5/KBI5 V 3 26 PTD4/T1CH0 SS OSC1 4 25 PTD5/T1CH1 OSC2/RCCLK/PTA6/KBI6 5 24 PTD2/ADC9 PTA1/KBI1 6 23 PTA4/KBI4 V 7 22 PTD3/ADC8 DD Pins not available on 28-pin packages PTA2/KBI2/SDA 8 21 PTB0/ADC0 PTE0/T2CH0 PTA3/KBI3/SCL 9 20 PTB1/ADC1 PTE1/T2CH1 PTB7/ADC7 10 19 PTD1/ADC10 PTB6/ADC6 11 18 PTB2/ADC2 ADC12/T2CLK PTB5/ADC5 12 17 PTB3/ADC3 PTA7/KBI7 PTD7/RxD/SDA 13 16 PTD0/ADC11 Internal pads are unconnected. PTD6/TxD/SCL 14 15 PTB4/ADC4 Set these unused port I/Os to output low. Figure 1-4. 28-Pin PDIP/SOIC Pin Assignment 1.5 Pin Functions Description of the pin functions are provided in Table 1-1. Table 1-1. Pin Functions Voltage Pin Name Pin Description Input/Output Level VDD Power supply Input 5 V or 3 V VSS Power supply ground Output 0V RST Reset input, active low; with internal pull up and Schmitt trigger input Input/output VDD External IRQ pin; with programmable internal pull up and Schmitt trigger input Input VDD IRQ Used for monitor mode entry Input VDD to VTST V DD OSC1 Crystal or RC oscillator input Input V DD OSC2: crystal oscillator output; inverted OSC1 signal Output VDD OSC2/RCCLK RCCLK: RC oscillator clock output Output VDD Pin as PTA6/KBI6 (see PTA0–PTA7) Input/output VDD Continued on next page MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 21

General Description Table 1-1. Pin Functions (Continued) Voltage Pin Name Pin Description Input/Output Level ADC12: channel-12 input of ADC Input VSS to VDD ADC12/T2CLK T2CLK: external input clock for TIM2 Input VDD 8-bit general-purpose I/O port Input/output VDD Each pin has programmable internal pull up when configured as input Input VDD Pins as keyboard interrupts, KBI0–KBI7 Input VDD PTA0–PTA5 and PTA7 have LED direct sink capability Output VDD PTA0–PTA7 PTA6 as OSC2/RCCLK Output VDD V to V PTA2 as SDA of MMIIC Input/output SS DD (open-drain) V to V PTA3 as SCL of MMIIC Input/output SS DD (open-drain) 8-bit general-purpose I/O port Input/output VDD PTB0–PTB7 Pins as ADC input channels, ADC0–ADC7 Input VSS to VDD 8-bit general purpose I/O port; with programmable internal pull ups on PTD6–PTD7 Input/output VDD PTD0–PTD3 as ADC input channels, ADC11–ADC8 Input VSS to VDD PTD2–PTD3 and PTD6–PTD7 have LED direct sink capability Output VSS PTD4 as T1CH0 of TIM1 Input/output VDD PTD5 as T1CH1 of TIM1 Input/output VDD PTD0–PTD7 PTD6–PTD7 have configurable 25-mA open-drain output Output VSS PTD6 as TxD of SCI Output VDD PTD7 as RxD of SCI Input VDD V to V PTD6 as SCL of MMIIC Input/output SS DD (open-drain) V to V PTD7 as SDA of MMIIC Input/output SS DD (open-drain) 2-bit general-purpose I/O port Input/output VDD PTE0–PTE1 PTE0 as T2CH0 of TIM2 Input/output VDD PTE1 as T2CH1 of TIM2 Input/output VDD NOTE Devices in 28-pin packages, the following pins are not available: PTA7/KBI7, PTE0/T2CH0, PTE1/T2CH1, and ADC12/T2CLK. MC68HC908JL16 Data Sheet, Rev. 1.1 22 Freescale Semiconductor

Chapter 2 Memory 2.1 Introduction The CPU08 can address 64-kbytes of memory space. The memory map, shown in Figure 2-1, includes: (cid:127) 16,384 bytes of user FLASH memory (cid:127) 36 bytes of user-defined vectors (cid:127) 512 bytes of random access memory (RAM) (cid:127) 959 bytes of monitor ROM 2.2 I/O Section Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have the following addresses: (cid:127) $FE00; Break status register, BSR (cid:127) $FE01; Reset status register, RSR (cid:127) $FE02; Reserved (cid:127) $FE03; Break flag control register, BFCR (cid:127) $FE04; Interrupt status register 1, INT1 (cid:127) $FE05; Interrupt status register 2, INT2 (cid:127) $FE06; Interrupt status register 3, INT3 (cid:127) $FE07; Reserved (cid:127) $FE08; FLASH control register, FLCR (cid:127) $FE09; Reserved (cid:127) $FE0A; Reserved (cid:127) $FE0B; Reserved (cid:127) $FE0C; Break address register high, BRKH (cid:127) $FE0D; Break address register low, BRKL (cid:127) $FE0E; Break status and control register, BRKSCR (cid:127) $FE0F; Reserved (cid:127) $FFCF; FLASH block protect register, FLBPR (FLASH register) (cid:127) $FFD0; Mask option register, MOR (FLASH register) (cid:127) $FFFF; COP control register, COPCTL MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 23

Memory $0000 I/O REGISTERS ↓ 70 BYTES $0045 $0046 RESERVED ↓ 26 BYTES $005F $0060 RAM ↓ 512 BYTES $025F $0260 UNIMPLEMENTED ↓ 47,520 BYTES $BBFF $BC00 FLASH MEMORY ↓ 16,384 BYTES $FBFF $FC00 MONITOR ROM ↓ 512 BYTES $FDFF $FE00 BREAK STATUS REGISTER (BSR) $FE01 RESET STATUS REGISTER (RSR) $FE02 RESERVED $FE03 BREAK FLAG CONTROL REGISTER (BFCR) $FE04 INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER 3 (INT3) $FE07 RESERVED $FE08 FLASH CONTROL REGISTER (FLCR) $FE09 ↓ RESERVED $FF0B $FE0C BREAK ADDRESS HIGH REGISTER (BRKH) $FE0D BREAK ADDRESS LOW REGISTER (BRKL) $FE0E BREAK STATUS AND CONTROL REGISTER (BRKSCR) $FE0F RESERVED $FE10 MONITOR ROM ↓ 447 BYTES $FFCE $FFCF FLASH BLOCK PROTECT REGISTER (FLBPR) $FFD0 MASK OPTION REGISTER (MOR) $FFD1 RESERVED ↓ 11 BYTES $FFDB $FFDC USER FLASH VECTORS ↓ 36 BYTES $FFFF Figure 2-1. Memory Map MC68HC908JL16 Data Sheet, Rev. 1.1 24 Freescale Semiconductor

I/O Section Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: Port A Data Register PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 $0000 Write: (PTA) Reset: Unaffected by reset Read: Port B Data Register PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 $0001 Write: (PTB) Reset: Unaffected by reset Read: $0002 Unimplemented Write: Read: Port D Data Register PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 $0003 Write: (PTD) Reset: Unaffected by reset Read: Data Direction Register A DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 $0004 Write: (DDRA) Reset: 0 0 0 0 0 0 0 0 Read: Data Direction Register B DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 $0005 Write: (DDRB) Reset: 0 0 0 0 0 0 0 0 $0006 Unimplemented Read: Data Direction Register D DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 $0007 Write: (DDRD) Reset: 0 0 0 0 0 0 0 0 Read: Port E Data Register PTE1 PTE0 $0008 Write: (PTE) Reset: Unaffected by reset $0009 Unimplemented Read: 0 0 0 0 Port D Control Register SLOWD7 SLOWD6 PTDPU7 PTDPU6 $000A Write: (PDCR) Reset: 0 0 0 0 0 0 0 0 $000B Unimplemented Read: Data Direction Register E DDRE1 DDRE0 $000C Write: (DDRE) Reset: 0 0 0 0 0 0 0 0 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 25

Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: Port A Input Pullup Enable PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 $000D Write: Register (PTAPUE) Reset: 0 0 0 0 0 0 0 0 Read: PTA7 Input Pullup Enable PTAPUE7 $000E Write: Register (PTA7PUE) Reset: 0 0 0 0 0 0 0 0 $000F ↓ Unimplemented $0012 Read: SCI Control Register 1 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY $0013 Write: (SCC1) Reset: 0 0 0 0 0 0 0 0 Read: SCI Control Register 2 SCTIE TCIE SCRIE ILIE TE RE RWU SBK $0014 Write: (SCC2) Reset: 0 0 0 0 0 0 0 0 Read: R8 SCI Control Register 3 T8 DMARE DMATE ORIE NEIE FEIE PEIE $0015 Write: (SCC3) Reset: U U 0 0 0 0 0 0 Read: SCTE TC SCRF IDLE OR NF FE PE SCI Status Register 1 $0016 Write: (SCS1) Reset: 1 1 0 0 0 0 0 0 Read: BKF RPF SCI Status Register 2 $0017 Write: (SCS2) Reset: 0 0 0 0 0 0 0 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 SCI Data Register $0018 Write: T7 T6 T5 T4 T3 T2 T1 T0 (SCDR) Reset: Unaffected by reset Read: SCI Baud Rate Register SCP1 SCP0 R SCR2 SCR1 SCR0 $0019 Write: (SCBR) Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 0 KEYF 0 Keyboard Status and Control IMASKK MODEK $001A Write: ACKK Register (KBSCR) Reset: 0 0 0 0 0 0 0 0 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 7) MC68HC908JL16 Data Sheet, Rev. 1.1 26 Freescale Semiconductor

I/O Section Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: Keyboard Interrupt Enable KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 $001B Write: Register (KBIER) Reset: 0 0 0 0 0 0 0 0 $001C Unimplemented Read: 0 0 0 0 IRQF 0 IRQ Status and Control IMASK MODE $001D Write: ACK Register (INTSCR) Reset: 0 0 0 0 0 0 0 0 Read: STOP_ $001E Configuration Register 2 Write: IRQPUD R R LVIT1 LVIT0 R IICSEL ICLKDIS (CONFIG2)(1) Reset: 0 0 0 0(2) 0(2) 0 0 0 Read: Configuration Register 1 COPRS R R LVID R SSREC STOP COPD $001F Write: (CONFIG1)(1) Reset: 0 0 0 0 0 0 0 0 1. One-time writable register after each reset. 2. LVIT1 and LVIT0 reset to 0 by a power-on reset (POR) only. Read: TOF 0 0 TIM1 Status and Control TOIE TSTOP PS2 PS1 PS0 $0020 Write: 0 TRST Register (T1SC) Reset: 0 0 1 0 0 0 0 0 Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TIM1 Counter Register High $0021 Write: (T1CNTH) Reset: 0 0 0 0 0 0 0 0 Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIM1 Counter Register $0022 Write: Low (T1CNTL) Reset: 0 0 0 0 0 0 0 0 Read: TIM Counter Modulo Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $0023 Write: High (TMODH) Reset: 1 1 1 1 1 1 1 1 Read: TIM1 Counter Modulo Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0024 Write: Register Low (T1MODL) Reset: 1 1 1 1 1 1 1 1 Read: CH0F TIM1 Channel 0 Status and CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX $0025 Write: 0 Control Register (T1SC0) Reset: 0 0 0 0 0 0 0 0 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 27

Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: TIM1 Channel 0 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $0026 Write: High (T1CH0H) Reset: Indeterminate after reset Read: TIM1 Channel 0 Register Low Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0027 Write: (T1CH0L) Reset: Indeterminate after reset Read: CH1F 0 TIM1 Channel 1 Status and CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX $0028 Write: 0 Control Register (T1SC1) Reset: 0 0 0 0 0 0 0 0 Read: TIM1 Channel 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $0029 Write: Register High (T1CH1H) Reset: Indeterminate after reset Read: TIM1 Channel 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $002A Write: Register Low (T1CH1L) Reset: Indeterminate after reset $002B ↓ Unimplemented $002F Read: TOF 0 0 TIM2 Status and Control TOIE TSTOP PS2 PS1 PS0 $0030 Write: 0 TRST Register (T2SC) Reset: 0 0 1 0 0 0 0 0 Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TIM2 Counter Register High $0031 Write: (T2CNTH) Reset: 0 0 0 0 0 0 0 0 Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIM2 Counter Register $0032 Low Write: (T2CNTL) Reset: 0 0 0 0 0 0 0 0 Read: TIM2 Counter Modulo Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $0033 Register High Write: (T2MODH) Reset: 1 1 1 1 1 1 1 1 Read: TIM2 Counter Modulo Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0034 Register Low Write: (T2MODL) Reset: 1 1 1 1 1 1 1 1 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 7) MC68HC908JL16 Data Sheet, Rev. 1.1 28 Freescale Semiconductor

I/O Section Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: CH0F TIM2 Channel 0 Status and CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX $0035 Control Register Write: 0 (T2SC0) Reset: 0 0 0 0 0 0 0 0 Read: TIM2 Channel 0 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $0036 Write: High (T2CH0H) Reset: Indeterminate after reset Read: TIM2 Channel 0 Register Low Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0037 Write: (T2CH0L) Reset: Indeterminate after reset Read: CH1F 0 TIM2 Channel 1 Status and CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX $0038 Write: 0 Control Register (T2SC1) Reset: 0 0 0 0 0 0 0 0 Read: TIM2 Channel 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $0039 Write: Register High (T2CH1H) Reset: Indeterminate after reset Read: TIM2 Channel 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $003A Write: Register Low (T2CH1L) Reset: Indeterminate after reset $003B Unimplemented Read: COCO ADC10 Status and Control AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 $003C Write: Register (ADCSC) Reset: 0 0 0 1 1 1 1 1 Read: 0 0 0 0 0 0 0/AD9 0/AD8 ADC10 Data Register High $003D Write: R R R R R R R R 8/10-Bit Mode (ADRH) Reset: 0 0 0 0 0 0 0 0 Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADC10 Data Register Low $003E Write: R R R R R R R R (ADRL) Reset: 0 0 0 0 0 0 0 0 Read: ADC10 Clock Register ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ADACKEN $003F Write: (ADCLK) Reset: 0 0 0 0 0 0 0 0 Read: MMALIF MMNAKIF MMBB Multi-Master IIC MMAST MMRW MMBR2 MMBR1 MMBR0 $0040 Master Control Register Write: 0 0 (MIMCR) Reset: 0 0 0 0 0 0 0 0 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 29

Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: Multi-Master IIC Address MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD $0041 Register Write: (MMADR) Reset: 1 0 1 0 0 0 0 0 Read: 0 0 0 0 Multi-Master IIC Control MMEN MMIEN MMTXAK REPSEN $0042 Register Write: (MMCR) Reset: 0 0 0 0 0 0 0 0 Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK 0 MMTXBE MMRXBF Multi-Master IIC Status $0043 Write: 0 0 Register (MMSR) Reset: 0 0 0 0 1 0 1 0 Read: Multi-Master IIC Data MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0 $0044 Write: Transmit Register (MMDTR) Reset: 1 1 1 1 1 1 1 1 Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0 Multi-Master IIC Data $0045 Receive Register (MMDRR) Write: Reset: 0 0 0 0 0 0 0 0 Read: SBSW Break Status Register R R R R R R R $FE00 Write: See note (BSR) Reset: 0 Note: Writing a 0 clears SBSW. Read: POR PIN COP ILOP ILAD MODRST LVI 0 Reset Status Register $FE01 Write: (RSR) POR: 1 0 0 0 0 0 0 0 $FE02 Reserved R R R R R R R R Read: Break Flag Control Register BCFE R R R R R R R $FE03 Write: (BFCR) Reset: 0 Read: IF6 IF5 IF4 IF3 0 IF1 0 0 Interrupt Status Register1 $FE04 Write: R R R R R R R R (INT1) Reset: 0 0 0 0 0 0 0 0 Read: IF14 IF13 IF12 IF11 IF10 0 IF8 IF7 Interrupt Status Register2 $FE05 Write: R R R R R R R R (INT2) Reset: 0 0 0 0 0 0 0 0 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7) MC68HC908JL16 Data Sheet, Rev. 1.1 30 Freescale Semiconductor

I/O Section Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 IF15 Interrupt Status Register 3 $FE06 Write: R R R R R R R R (INT3) Reset: 0 0 0 0 0 0 0 0 $FE07 Reserved R R R R R R R R Read: 0 0 0 0 FLASH Control Register HVEN MASS ERASE PGM $FE08 Write: (FLCR) Reset: 0 0 0 0 0 0 0 0 $FE09 ↓ Reserved R R R R R R R R $FE0B Read: Break Address High Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $FE0C Write: (BRKH) Reset: 0 0 0 0 0 0 0 0 Read: Break Address Low Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $FE0D Write: (BRKL) Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 0 0 0 Break Status and Control BRKE BRKA $FE0E Register Write: (BRKSCR) Reset: 0 0 0 0 0 0 0 0 Read: FLASH Block Protect BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 $FFCF Register Write: (FLBPR)(1) Reset: Unaffected by reset; $FF when blank Read: Mask Option Register OSCSEL R R R R R R R $FFD0 Write: (MOR)(1) Reset: Unaffected by reset; $FF when blank 1. Non-volatile FLASH registers; write by programming. Read: Low byte of reset vector COP Control Register $FFFF Write: Writing clears COP counter (any value) (COPCTL) Reset: Unaffected by reset U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 7) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 31

Memory 2.3 Monitor ROM The 959 bytes at addresses $FC00–$FDFF and $FE10–$FFCE are reserved ROM addresses that contain the instructions for the monitor functions. (See Chapter 16 Development Support.) . Table 2-1. Vector Addresses Vector Priority INT Flag Address Vector $FFD0 Lowest — ↓ Not Used $FFDD $FFDE ADC conversion complete vector (high) IF15 $FFDF ADC Conversion complete vector (low) $FFE0 Keyboard interrupt vector (high) IF14 $FFE1 Keyboard interrupt vector (low) $FFE2 SCI transmit vector (high) IF13 $FFE3 SCI transmit vector (low) $FFE4 SCI receive vector (high) IF12 $FFE5 SCI receive vector (low) $FFE6 SCI error vector (high) IF11 $FFE7 SCI error vector (low) $FFE8 MMIIC vector (high) IF10 $FFE9 MMIIC vector (low) IF9 — Not used $FFEC TIM2 overflow vector (high) IF8 $FFED TIM2 overflow vector (low) $FFEE TIM2 channel 1 vector (high) IF7 $FFEF TIM2 channel 1 vector (low) $FFF0 TIM2 channel 0 vector (high) IF6 $FFF1 TIM2 channel 0 vector (low) $FFF2 TIM1 overflow vector (high) IF5 $FFF3 TIM1 overflow vector (low) $FFF4 TIM1 channel 1 vector (high) IF4 $FFF5 TIM1 channel 1 vector (low) $FFF6 TIM1 channel 0 vector (high) IF3 $FFF7 TIM1 channel 0 vector (low) IF2 — Not used $FFFA IRQ vector (high) IF1 $FFFB IRQ vector (low) $FFFC SWI vector (high) — $FFFD SWI vector (low) $FFFE Reset vector (high) — Highest $FFFF Reset vector (low) MC68HC908JL16 Data Sheet, Rev. 1.1 32 Freescale Semiconductor

Random-Access Memory (RAM) 2.4 Random-Access Memory (RAM) Addresses $0060 through $025F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE For M6805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. 2.5 FLASH Memory This sub-section describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. 2.5.1 Functional Description The FLASH memory consists of an array of 16,384 bytes for user memory plus a block of 36 bytes for user interrupt vectors. An erased bit reads as 1 and a programmed bit reads as a 0. The FLASH memory page size is defined as 64 bytes, and is the minimum size that can be erased in a page erase operation. Program and erase operations are facilitated through control bits in FLASH control register (FLCR). The address ranges for the FLASH memory are: (cid:127) $BC00–$FBFF; user memory; 16,384 bytes (cid:127) $FFDC–$FFFF; user interrupt vectors; 36 bytes Programming tools are available from Freescale Semiconductor. Contact your local representative for more information. NOTE A security feature prevents viewing of the FLASH contents.(1) 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 33

Memory 2.5.2 FLASH Control Register The FLASH control register (FCLR) controls FLASH program and erase operations. Address: $FE08 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 HVEN MASS ERASE PGM Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 2-3. FLASH Control Register (FLCR) HVEN — High Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS — Mass Erase Control Bit This read/write bit configures the memory for mass erase operation or page erase operation when the ERASE bit is set. 1 = Mass erase operation selected 0 = Page erase operation selected ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation not selected PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation not selected MC68HC908JL16 Data Sheet, Rev. 1.1 34 Freescale Semiconductor

FLASH Memory 2.5.3 FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 36-byte user interrupt vectors area also forms a page. Any page within the 16,384 bytes user memory area can be erased alone. 1. Set the ERASE bit and clear the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address within the page address range desired. 4. Wait for a time, t (10 µs). NVS 5. Set the HVEN bit. 6. Wait for a time t (4 ms). Erase 7. Clear the ERASE bit. 8. Wait for a time, t (5 µs). NVH 9. Clear the HVEN bit. 10. After time, t (1 µs) the memory can be accessed in read mode again. RCV , NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 2.5.4 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the FLASH memory address range. 4. Wait for a time, t (10 µs). NVS 5. Set the HVEN bit. 6. Wait for a time t (4 ms). Erase 7. Clear the ERASE bit. 8. Wait for a time, t (100 µs). NVH1 9. Clear the HVEN bit. 10. After time, t (1 µs) the memory can be accessed in read mode again. RCV , NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 35

Memory 2.5.5 FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this step-by-step procedure to program a row of FLASH memory: 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the address range of the row to be programmed. 4. Wait for a time, t (10 µs). NVS 5. Set the HVEN bit. 6. Wait for a time, t (5 µs). PGS 7. Write data to the FLASH address to be programmed. 8. Wait for time, t (30 µs). PROG 9. Repeat steps 7 and 8 until all bytes within the row are programmed. 10. Clear the PGM bit. 11. Wait for time, t (5 µs). NVH 12. Clear the HVEN bit. 13. After time, t (1 µs), the memory can be accessed in read mode again. RCV Figure 2-4 shows a flowchart of the programming algorithm. This program sequence is repeated throughout the memory until all data is programmed. NOTE The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH addressed programmed to clearing the PGM bit (step 7 to step 10), must not exceed the maximum programming time, t max. PROG Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. MC68HC908JL16 Data Sheet, Rev. 1.1 36 Freescale Semiconductor

FLASH Memory Algorithm for Programming 1 SET PGM BIT a Row (32 Bytes) of FLASH Memory 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 WAIT FOR A TIME, t NVS 5 SET HVEN BIT 6 WAIT FOR A TIME, t PGS 7 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, t PROG COMPLETED Y 9 PROGRAMMING THIS ROW? N 10 CLEAR PGM BIT 11 WAIT FOR A TIME, t NVH NOTES: 12 CLEAR HVEN BIT The time between each FLASH address change (step 7to step 7), or the time between the last FLASH address programmed 13 to clearing PGM bit (step 6 to step 10) WAIT FOR A TIME, t RCV must not exceed the maximum programming time, t max. PROG This row program algorithm assumes the row/s END OF PROGRAMMING to be programmed are initially erased. Figure 2-4. FLASH Programming Flowchart MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 37

Memory 2.5.6 FLASH Block Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program operations. NOTE In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit When the FLBPR is program with all 0s, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1s), the entire memory is accessible for program and erase. When bits within the FLBPR are programmed, they lock a block of memory, address ranges as shown in 2.5.7 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. The FLBPR itself can be erased or programmed only with an external voltage, V , present on the IRQ pin. This voltage TST also allows entry from reset into the monitor mode. 2.5.7 FLASH Block Protect Register The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory. Address: $FFCF Bit 7 6 5 4 3 2 1 Bit 0 Read: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Write: Reset: Unaffected by reset; $FF when blank Non-volatile FLASH register; write by programming. Figure 2-5. FLASH Block Protect Register (FLBPR) BPR[7:0] — FLASH Block Protect Bits BPR[7:0] represent bits [13:6] of a 16-bit memory address. Bits [15:14] are 1s and bits [5:0] are 0s. 16-bit memory address Start address of FLASH 1 1 0 0 0 0 0 0 block protect BPR[7:0] The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page boundaries — 64 bytes) within the FLASH memory. MC68HC908JL16 Data Sheet, Rev. 1.1 38 Freescale Semiconductor

FLASH Memory Table 2-2. Examples of Protect Start Address BPR[7:0] Start of Address of Protect Range(1) $00(2) The entire FLASH memory is protected. $01 $C040 (1100 0000 0100 0000) (0000 0001) $02 $C080 (1100 0000 1000 0000) (0000 0010) $03 $C0C0 (1100 0000 1100 0000) (0000 0011) and so on... $FD $FF40 (1111 1111 0100 0000) (1111 1101) $FE $FF80 (1111 1111 1000 0000) (1111 1110) $FF The entire FLASH memory is not protected. 1. The end address of the protected range is always $FFFF. 2. $BC00–$BFFF is always protected unless entire FLASH memory is unprotected, BPR[7:0} = $FF. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 39

Memory MC68HC908JL16 Data Sheet, Rev. 1.1 40 Freescale Semiconductor

Chapter 3 Configuration and Mask Option Registers (CONFIG and MOR) 3.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option register (MOR). The configuration registers enable or disable these options: (cid:127) Computer operating properly module (COP) (cid:127) COP timeout period (213–24 or 218–24 ICLK cycles) (cid:127) Internal oscillator during stop mode (cid:127) Low voltage inhibit (LVI) module (cid:127) LVI module voltage trip point selection (cid:127) STOP instruction (cid:127) Stop mode recovery time (32 or 4096 ICLK cycles) (cid:127) Pull-up on IRQ pin (cid:127) MMIIC pin selection The mask option register selects the oscillator option: (cid:127) Crystal or RC Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: STOP_ Configuration Register 2 IRQPUD R R LVIT1 LVIT0 R IICSEL $001E Write: ICLKDIS (CONFIG2)(1) Reset: 0 0 0 0(2) 0(2) 0 0 0 Read: Configuration Register 1 COPRS R R LVID R SSREC STOP COPD $001F Write: (CONFIG1)(1) Reset: 0 0 0 0 0 0 0 0 Read: Mask Option Register OSCSEL R R R R R R R $FFD0 Write: (MOR)(3) Reset: Unaffected by reset; $FF when blank 1. One-time writable register after each reset. 2. LVIT1 and LVIT0 reset to 0 by a power-on reset (POR) only. 3. Non-volatile FLASH register; write by programming. R =Reserved Figure 3-1. CONFIG Registers Summary MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 41

Configuration and Mask Option Registers (CONFIG and MOR) 3.2 Functional Description The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU, it is recommended that these registers be written immediately after reset. The configuration registers are located at $001E and $001F. The configuration registers may be read at anytime. NOTE The options except LVIT[1:0] are one-time writable by the user after each reset. The LVIT[1:0] bits are one-time writable by the user only after each POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 3-2 and Figure 3-3. The mask option register (MOR) is used to select the oscillator option for the MCU: crystal oscillator or RC oscillator. The MOR is implemented as a byte in FLASH memory. Hence, writing to the MOR requires programming the byte. 3.3 Configuration Register 1 (CONFIG1) Address: $001F Bit 7 6 5 4 3 2 1 Bit 0 Read: COPRS R R LVID R SSREC STOP COPD Write: Reset: 0 0 0 0 0 0 0 0 R =Reserved Figure 3-2. Configuration Register 1 (CONFIG1) COPRS — COP Rate Select Bit COPRS selects the COP time-out period. Reset clears COPRS. (See Chapter 13 Computer Operating Properly (COP).) 1 = COP timeout period is (213 – 24) ICLK cycles 0 = COP timeout period is (218 – 24) ICLK cycles LVID — Low Voltage Inhibit Disable Bit LVID disables the LVI module. Reset clears LVID. (See Chapter 14 Low-Voltage Inhibit (LVI).) 1 = Low voltage inhibit disabled 0 = Low voltage inhibit enabled SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK cycle delay. 1 = Stop mode recovery after 32 ICLK cycles 0 = Stop mode recovery after 4096 ICLK cycles NOTE Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. MC68HC908JL16 Data Sheet, Rev. 1.1 42 Freescale Semiconductor

Configuration Register 2 (CONFIG2) STOP — STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. Reset clears COPD. (See Chapter 13 Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled 3.4 Configuration Register 2 (CONFIG2) Address: $001E Bit 7 6 5 4 3 2 1 Bit 0 Read: STOP_ IRQPUD R R LVIT1 LVIT0 R IICSEL Write: ICLKDIS Reset: 0 0 0 U U 0 0 0 POR: 0 0 0 0 0 0 0 0 R =Reserved U = Unaffected Figure 3-3. Configuration Register 2 (CONFIG2) IRQPUD — IRQ Pin Pull-Up Disable Bit IRQPUD disconnects the internal pull-up on the IRQ pin. 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ pin and V DD LVIT1, LVIT0 — LVI Trip Voltage Selection Bits Detail description of trip voltage selection is given in Chapter 14 Low-Voltage Inhibit (LVI). IICSEL — MMIIC Pin Selection Bit IICSEL selects the pins to be used as MMIIC I/Os when the MMIIC module is enabled. (See Chapter 8 Multi-Master IIC Interface (MMIIC).) 1 = SDA on PTA2/KBI2 pin; SCL on PTA3/KBI3 pin 0 = SDA on PTD7/RxD pin; SCL on PTD6/TxD pin STOP_ICLKDIS — Internal Oscillator Stop Mode Disable Bit Setting STOP_ICLKDIS disables the internal oscillator during stop mode. When this bit is cleared, the internal oscillator continues to operate in stop mode. Reset clears this bit. 1 = Internal oscillator disabled during stop mode 0 = Internal oscillator enabled during stop mode MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 43

Configuration and Mask Option Registers (CONFIG and MOR) 3.5 Mask Option Register (MOR) The mask option register (MOR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. This register is read after a power-on reset to determine the type of oscillator selected. (See Chapter 5 Oscillator (OSC).) Address: $FFD0 Bit 7 6 5 4 3 2 1 Bit 0 Read: OSCSEL R R R R R R R Write: Erased: 1 1 1 1 1 1 1 1 Reset: Unaffected by reset Non-volatile FLASH register; write by programming. R =Reserved Figure 3-4. Mask Option Register (MOR) OSCSEL — Oscillator Select Bit OSCSEL selects the oscillator type for the MCU. The erased or unprogrammed state of this bit is logic 1, selecting the crystal oscillator option. This bit is unaffected by reset. 1 = Crystal oscillator 0 = RC oscillator Bits 6–0 — Should be left as logic 1’s. NOTE When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is used as OSC2; other functions such as PTA6/KBI6 will not be available. MC68HC908JL16 Data Sheet, Rev. 1.1 44 Freescale Semiconductor

Chapter 4 System Integration Module (SIM) 4.1 Introduction This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 4-1. Figure 4-2 is a summary of the SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: (cid:127) Bus clock generation and control for CPU and peripherals – Stop/wait/reset/break entry and recovery – Internal clock control (cid:127) Master reset control, including power-on reset (POR) and COP timeout (cid:127) Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation (cid:127) CPU enable/disable timing (cid:127) Modular architecture expandable to 128 interrupt sources Table 4-1. Signal Name Conventions Signal Name Description ICLK Internal oscillator clock The XTAL or RC frequency divided by two. This signal is again divided by two in the SIM to OSCOUT generate the internal bus clocks. (Bus clock = OSCOUT ÷ 2) IAB Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 45

System Integration Module (SIM) MODULE STOP MODULE WAIT STOP/WAIT CPU STOP (FROM CPU) CONTROL CPU WAIT (FROM CPU) SIMOSCEN (TO OSCILLATOR) SIM COP CLOCK COUNTER ICLK (FROM OSCILLATOR) OSCOUT (FROM OSCILLATOR) ÷2 V DD CLOCK CLOCK GENERATORS INTERNAL CLOCKS CONTROL INTERNAL PULL-UP RESET POR CONTROL ILLEGAL OPCODE (FROM CPU) PIN LOGIC MASTER ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) RESET PIN CONTROL RESET CONTROL COP TIMEOUT (FROM COP MODULE) SIM RESET STATUS REGISTER LVI RESET (FROM LVI MODULE) RESET INTERRUPT SOURCES INTERRUPT CONTROL AND PRIORITY DECODE CPU INTERFACE Figure 4-1. SIM Block Diagram Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: SBSW Break Status Register R R R R R R R $FE00 Write: NOTE (BSR) Reset: 0 0 0 0 0 0 0 0 Note: Writing a 0 clears SBSW. Read: POR PIN COP ILOP ILAD MODRST LVI 0 Reset Status Register $FE01 Write: (RSR) POR: 1 0 0 0 0 0 0 0 $FE02 Reserved R R R R R R R R Figure 4-2. SIM I/O Register Summary MC68HC908JL16 Data Sheet, Rev. 1.1 46 Freescale Semiconductor

SIM Bus Clock Control and Generation Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: Break Flag Control BCFE R R R R R R R $FE03 Write: Register (BFCR) Reset: 0 Read: IF6 IF5 IF4 IF3 0 IF1 0 0 Interrupt Status Register1 $FE04 Write: R R R R R R R R (INT1) Reset: 0 0 0 0 0 0 0 0 Read: IF14 IF13 IF12 IF11 IF10 0 IF8 IF7 Interrupt Status Register2 $FE05 Write: R R R R R R R R (INT2) Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 0 0 0 0 IF15 Interrupt Status Register3 $FE06 Write: R R R R R R R R (INT3) Reset: 0 0 0 0 0 0 0 0 =Unimplemented R =Reserved Figure 4-2. SIM I/O Register Summary (Continued) 4.2 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 4-3. INTERNAL RC ICLK OSCILLATOR SIM COUNTER XTALCLK / RCCLK ÷ 2 OSCOUT ÷ 2 BUS CLOCK GENERATORS OSC SIM Figure 4-3. SIM Clock Signals 4.2.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency divided by four. 4.2.2 Clock Start-Up from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 ICLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 47

System Integration Module (SIM) 4.2.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt, break, or reset, the SIM allows ICLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time-out. This time-out is selectable as 4096 or 32 ICLK cycles. (See 4.6.2 Stop Mode.) In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. 4.3 Reset and System Initialization The MCU has these reset sources: (cid:127) Power-on reset module (POR) (cid:127) External reset pin (RST) (cid:127) Computer operating properly module (COP) (cid:127) Low-voltage inhibit module (LVI) (cid:127) Illegal opcode (cid:127) Illegal address All of these resets produce the vector $FFFE–$FFFF ($FEFE–$FEFF in Monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 4.4 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the reset status register (RSR). (See 4.7 SIM Registers.) 4.3.1 External Pin Reset The RST pin circuits include an internal pull-up device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the reset status register (RSR) is set as long as RST is held low for a minimum of 67 ICLK cycles, assuming that the POR was not the source of the reset. See Table 4-2 for details. Figure 4-4 shows the relative timing. Table 4-2. PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR 4163 (4096 + 64 + 3) All others 67 (64 + 3) ICLK RST IAB PC VECT H VECT L Figure 4-4. External Reset Timing MC68HC908JL16 Data Sheet, Rev. 1.1 48 Freescale Semiconductor

Reset and System Initialization 4.3.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 ICLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (Figure 4-5). An internal reset can be caused by an illegal address, illegal opcode, COP time-out, or POR. (See Figure 4-6. Sources of Internal Reset.) Note that for POR resets, the SIM cycles through 4096 ICLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 4-5. IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES ICLK IAB VECTOR HIGH Figure 4-5. Internal Reset Timing The COP reset is asynchronous to the bus clock. ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET POR LVI Figure 4-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 4.3.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 ICLK cycles. Sixty-four ICLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: (cid:127) A POR pulse is generated. (cid:127) The internal reset signal is asserted. (cid:127) The SIM enables OSCOUT. (cid:127) Internal clocks to the CPU and modules are held inactive for 4096 ICLK cycles to allow stabilization of the oscillator. (cid:127) The RST pin is driven low during the oscillator stabilization time. (cid:127) The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 49

System Integration Module (SIM) OSC1 PORRST 4096 32 32 CYCLES CYCLES CYCLES ICLK OSCOUT RST IAB $FFFE $FFFF Figure 4-7. POR Recovery 4.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module time-out, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every (212 – 24) ICLK cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time-out. The COP module is disabled if the RST pin or the IRQ pin is held at V while the MCU is in monitor TST mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, V on the RST pin disables the COP module. TST 4.3.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the reset status register (RSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic zero, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 4.3.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the reset status register (RSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. MC68HC908JL16 Data Sheet, Rev. 1.1 50 Freescale Semiconductor

SIM Counter 4.3.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the V voltage falls to the LVI DD trip voltage V . The LVI bit in the reset status register (RSR) is set, and the external reset pin (RST) is TRIP held low while the SIM counter counts out 4096 ICLK cycles. Sixty-four ICLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources. 4.4 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of ICLK. 4.4.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine. 4.4.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 ICLK cycles down to 32 ICLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register 1 (CONFIG1). 4.4.3 SIM Counter and Reset States External reset has no effect on the SIM counter. (See 4.6.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 4.3.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.) 4.5 Exception Control Normal, sequential program execution can be changed in three different ways: (cid:127) Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) (cid:127) Reset (cid:127) Break interrupts 4.5.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 4-8 flow charts the handling of system interrupts. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 51

System Integration Module (SIM) FROM RESET YES BREAIK B IINT TSEERTR?UPT? NO YES I BIT SET? NO IRQ YES INTERRUPT? NO TIMER 1 YES INTERRUPT? NO STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. (As many interrupts as exist on chip) FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? UNSTACK CPU REGISTERS. NO EXECUTE INSTRUCTION. Figure 4-8. Interrupt Processing MC68HC908JL16 Data Sheet, Rev. 1.1 52 Freescale Semiconductor

Exception Control Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 4-9 shows interrupt entry timing. Figure 4-10 shows interrupt recovery timing. MODULE INTERRUPT I BIT IAB DUMMY SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR IDB DUMMY PC – 1[7:0] PC – 1[15:8] X A CCR V DATA H V DATA L OPCODE R/W Figure 4-9. Interrupt Entry MODULE INTERRUPT I BIT IAB SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1 IDB CCR A X PC – 1[15:8] PC – 1[7:0] OPCODE OPERAND R/W Figure 4-10. Interrupt Recovery 4.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 53

System Integration Module (SIM) If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 4-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. CLI LDA #$FF BACKGROUND ROUTINE INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 4-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. 4.5.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. 4.5.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 4-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. MC68HC908JL16 Data Sheet, Rev. 1.1 54 Freescale Semiconductor

Exception Control Table 4-3. Interrupt Sources Priority Source Flag Mask1(1) INT Flag Vector Address Highest Reset — — — $FFFE–$FFFF SWI Instruction — — — $FFFC–$FFFD IRQ Pin IRQF IMASK IF1 $FFFA–$FFFB Timer 1 Channel 0 Interrupt CH0F CH0IE IF3 $FFF6–$FFF7 Timer 1 Channel 1 Interrupt CH1F CH1IE IF4 $FFF4–$FFF5 Timer 1 Overflow Interrupt TOF TOIE IF5 $FFF2–$FFF3 Timer 2 Channel 0 Interrupt CH0F CH0IE IF6 $FFF0–$FFF1 Timer 2 Channel 1 Interrupt CH1F CH1IE IF7 $FFEE–$FFEF Timer 2 Overflow Interrupt TOF TOIE IF8 $FFEC–$FFED MMALIF, MMNAKIF, MMBF, MMRXIF, MMIEN MMIIC Interrupt IF10 $FFE8–$FFE9 MMTXIF, MMTXBE, to mask MMRXBF OR ORIE NF NEIE SCI Error IF11 $FFE6–$FFE7 FE FEIE PE PEIE SCRF SCRIE SCI Receive IF12 $FFE4–$FFE5 IDLE ILIE SCTE SCTIE SCI Transmit IF13 $FFE2–$FFE3 TC TCIE Keyboard Interrupt KEYF IMASKK IF14 $FFE0–$FFE1 Lowest ADC Conversion Complete Interrupt COCO AIEN IF15 $FFDE–$FFDF 1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction. 4.5.2.1 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF6 IF5 IF4 IF3 0 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 4-12. Interrupt Status Register 1 (INT1) IF1, IF3 to IF6 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 4-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0, 1, and 3 — Always read 0 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 55

System Integration Module (SIM) 4.5.2.2 Interrupt Status Register 2 Address: $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF14 IF13 IF12 IF11 IF10 0 IF8 IF7 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 4-13. Interrupt Status Register 2 (INT2) IF7, IF8, IF10 to F14 — Interrupt Flags These flags indicates the presence of interrupt requests from the sources shown in Table 4-3. 1 = Interrupt request present 0 = No interrupt request present Bit 2 — Always reads 0 4.5.2.3 Interrupt Status Register 3 Address: $FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 IF15 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 4-14. Interrupt Status Register 3 (INT3) IF15 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 4-3. 1 = Interrupt request present 0 = No interrupt request present Bit 1 to 7 — Always read 0 4.5.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 4.5.4 Break Interrupts The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (See Chapter 16 Development Support.) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. MC68HC908JL16 Data Sheet, Rev. 1.1 56 Freescale Semiconductor

Low-Power Modes 4.5.5 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example, a read of one register followed by the read or write of another — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal. 4.6 Low-Power Modes Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 4.6.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 4-15 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the mask option register is logic zero, then the computer operating properly module (COP) is enabled and remains active in wait mode. IAB WAIT ADDR WAIT ADDR + 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME SAME R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 4-15. Wait Mode Entry Timing MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 57

System Integration Module (SIM) Figure 4-16 and Figure 4-17 show the timing for WAIT recovery. IAB $6E0B $6E0C $00FF $00FE $00FD $00FC IDB $A6 $A6 $A6 $01 $0B $6E EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt Figure 4-16. Wait Recovery from Interrupt or Break 32 32 Cycles Cycles IAB $6E0B RST VCT H RST VCT L IDB $A6 $A6 $A6 RST ICLK Figure 4-17. Wait Recovery from Internal Reset 4.6.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the oscillator signals (OSCOUT) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 ICLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. NOTE External crystal applications should use the full stop recovery time by clearing the SSREC bit. A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register (BSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 4-18 shows stop mode entry timing. NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0. MC68HC908JL16 Data Sheet, Rev. 1.1 58 Freescale Semiconductor

SIM Registers CPUSTOP IAB STOP ADDR STOP ADDR + 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME SAME R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. Figure 4-18. Stop Mode Entry Timing STOP RECOVERY PERIOD ICLK INT/BREAK IAB STOP +1 STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 4-19. Stop Mode Recovery from Interrupt or Break 4.7 SIM Registers The SIM has three memory mapped registers. (cid:127) Break Status Register (BSR) (cid:127) Reset Status Register (RSR) (cid:127) Break Flag Control Register (BFCR) 4.7.1 Break Status Register (BSR) The break status register contains a flag to indicate that a break caused an exit from stop or wait mode. Address: $FE00 Bit 7 6 5 4 3 2 1 Bit 0 Read: SBSW R R R R R R R Write: Note(1) Reset: 0 R = Reserved 1. Writing a clears SBSW. Figure 4-20. Break Status Register (BSR) SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 59

System Integration Module (SIM) SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 4.7.2 Reset Status Register (RSR) This register contains six flags that show the source of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register. Address: $FE01 Bit 7 6 5 4 3 2 1 Bit 0 Read: POR PIN COP ILOP ILAD MODRST LVI 0 Write: POR: 1 0 0 0 0 0 0 0 = Unimplemented Figure 4-21. Reset Status Register (RSR) POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of RSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of RSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of RSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of RSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of RSR MODRST — Monitor Mode Entry Module Reset bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = V DD 0 = POR or read of RSR LVI — Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of RSR MC68HC908JL16 Data Sheet, Rev. 1.1 60 Freescale Semiconductor

SIM Registers 4.7.3 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read: BCFE R R R R R R R Write: Reset: 0 R = Reserved Figure 4-22. Break Flag Control Register (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 61

System Integration Module (SIM) MC68HC908JL16 Data Sheet, Rev. 1.1 62 Freescale Semiconductor

Chapter 5 Oscillator (OSC) 5.1 Introduction The oscillator module provides the reference clocks for the MCU system and bus. Two oscillators are running on the device: Selectable oscillator — for bus clock (cid:127) Crystal oscillator (XTAL) — built-in oscillator that requires an external crystal or ceramic-resonator. This option also allows an external clock that can be driven directly into OSC1. (cid:127) RC oscillator (RC) — built-in oscillator that requires an external resistor-capacitor connection only. The selected oscillator is used to drive the bus clock, the SIM, and other modules on the MCU. The oscillator type is selected by programming a bit FLASH memory. The RC and crystal oscillator cannot run concurrently; one is disabled while the other is selected; because the RC and XTAL circuits share the same OSC1 pin. Non-selectable oscillator — for COP (cid:127) Internal oscillator — built-in RC oscillator that requires no external components. This internal oscillator is used to drive the computer operating properly (COP) module and the SIM. The internal oscillator runs continuously after a POR or reset, and is always available. 5.2 Oscillator Selection The oscillator type is selected by programming a bit in a FLASH memory location; the mask option register (MOR), at $FFD0. (See 3.5 Mask Option Register (MOR).) NOTE On the ROM device, the oscillator is selected by a ROM-mask layer at factory. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 63

Oscillator (OSC) Address: $FFD0 Bit 7 6 5 4 3 2 1 Bit 0 Read: OSCSEL R R R R R R R Write: Erased: 1 1 1 1 1 1 1 1 Reset: Unaffected by reset Non-volatile FLASH register; write by programming. R =Reserved Figure 5-1. Mask Option Register (MOR) OSCSEL — Oscillator Select Bit OSCSEL selects the oscillator type for the MCU. The erased or unprogrammed state of this bit is logic 1, selecting the crystal oscillator option. This bit is unaffected by reset. 1 = Crystal oscillator 0 = RC oscillator Bits 6–0 — Should be left as logic 1’s. NOTE When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is used as OSC2; other functions such as PTA6/KBI6 will not be available. 5.2.1 XTAL Oscillator The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide accurate clock source. In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown in Figure 5-2. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: (cid:127) Crystal, X 1 (cid:127) Fixed capacitor, C 1 (cid:127) Tuning capacitor, C (can also be a fixed capacitor) 2 (cid:127) Feedback resistor, R B (cid:127) Series resistor, R (optional) S The series resistor (R ) is included in the diagram to follow strict Pierce oscillator guidelines and may not S be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information. 5.2.2 RC Oscillator The RC oscillator circuit is designed for use with external resistor and capacitor to provide a clock source with tolerance less than 10%. See Figure 5-3. In its typical configuration, the RC oscillator requires two external components, one R and one C. Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance. The oscillator configuration uses two components: (cid:127) C EXT (cid:127) R EXT MC68HC908JL16 Data Sheet, Rev. 1.1 64 Freescale Semiconductor

Oscillator Selection FROM SIM TO SIM TO SIM 2OSCOUT OSCOUT XTALCLK ÷ 2 SIMOSCEN MCU OSC1 OSC2 R B R * S *R can be zero (shorted) when used with higher-frequency crystals. S X refer to manufacturer’s data. 1 See Chapter 17 Electrical Specifications for component value requirements. C C 1 2 Figure 5-2. XTAL Oscillator External Connections FROM SIM TO SIM TO SIM 2OSCOUT OSCOUT SIMOSCEN EXT-RC RCCLK EN ÷ 2 OSCILLATOR 0 PTA6 1 PTA6 I/O MCU PTA6EN OSC1 RCCLK/PTA6 (OSC2) VDD See Chapter 17 Electrical Specifications for component value requirements. R C EXT EXT Figure 5-3. RC Oscillator External Connections MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 65

Oscillator (OSC) 5.3 Internal Oscillator The internal oscillator clock (ICLK) is a free running 50-kHz clock that requires no external components. It is used as the reference clock input to the computer operating properly (COP) module and the SIM. The internal oscillator by default is always available and is free running after POR or reset. It can be stopped in stop mode by setting the STOP_ICLKDIS bit before executing the STOP instruction. Figure 5-4 shows the logical representation of components of the internal oscillator circuitry. FROM SIM TO SIM AND COP SIMOSCEN ICLK CONFIG2 EN STOP_ICLKDIS INTERNAL OSCILLATOR Figure 5-4. Internal Oscillator NOTE The internal oscillator is a free running oscillator and is available after each POR or reset. It is turned-off in stop mode by setting the STOP_ICLKDIS bit in CONFIG2 (see 3.4 Configuration Register 2 (CONFIG2)). 5.4 I/O Signals The following paragraphs describe the oscillator I/O signals. 5.4.1 Crystal Amplifier Input Pin (OSC1) OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit. 5.4.2 Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6) For the XTAL oscillator, OSC2 pin is the output of the crystal oscillator inverting amplifier. For the RC oscillator, OSC2 pin can be configured as a general purpose I/O pin PTA6, or the output of the RC oscillator, RCCLK. Oscillator OSC2 Pin Function XTAL Inverting OSC1 Controlled by PTA6EN bit in PTAPUE ($000D) RC PTA6EN = 0: RCCLK output PTA6EN = 1: PTA6/KBI6 5.4.3 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables the XTAL oscillator circuit or the RC-oscillator. MC68HC908JL16 Data Sheet, Rev. 1.1 66 Freescale Semiconductor

Low Power Modes 5.4.4 XTAL Oscillator Clock (XTALCLK) XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (f ) and comes XCLK directly from the crystal oscillator circuit. Figure 5-2 shows only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be unstable at start-up. 5.4.5 RC Oscillator Clock (RCCLK) RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the external R and C. Figure 5-3 shows only the logical relation of RCCLK to OSC1 and may not represent the actual circuitry. 5.4.6 Oscillator Out 2 (2OSCOUT) 2OSCOUT is same as the input clock (XTALCLK or RCCLK). This signal is driven to the SIM module. 5.4.7 Oscillator Out (OSCOUT) The frequency of this signal is equal to half of the 2OSCOUT, this signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the SIM and results in the internal bus frequency being one fourth of the XTALCLK or RCCLK frequency. 5.4.8 Internal Oscillator Clock (ICLK) ICLK is the internal oscillator output signal (typically 50-kHz), for the COP module and the SIM. Its frequency depends on the V voltage. (See Chapter 17 Electrical Specifications for ICLK parameters.) DD 5.5 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. 5.5.1 Wait Mode The WAIT instruction has no effect on the oscillator logic. OSCOUT, 2OSCOUT, and ICLK continues to drive to the SIM module. 5.5.2 Stop Mode The STOP instruction disables the XTALCLK or the RCCLK output, hence, OSCOUT and 2OSCOUT are disabled. The STOP instruction also turns off the ICLK input to the COP module if the STOP_ICLKDIS bit is set in configuration register 2 (CONFIG2). After reset, the STOP_ICLKDIS bit is clear by default and ICLK is enabled during stop mode. 5.6 Oscillator During Break Mode The OSCOUT, 2OSCOUT, and ICLK clocks continue to be driven out when the device enters the break state. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 67

Oscillator (OSC) MC68HC908JL16 Data Sheet, Rev. 1.1 68 Freescale Semiconductor

Chapter 6 Timer Interface Module (TIM) 6.1 Introduction This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with Input capture, output compare, and pulse-width-modulation functions. Figure 6-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2. 6.2 Features Features of the TIM include: (cid:127) Two input capture/output compare channels: – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action (cid:127) Buffered and unbuffered pulse-width-modulation (PWM) signal generation (cid:127) Programmable TIM clock input – 7-frequency internal bus clock prescaler selection – External clock input on timer 2 (bus frequency ÷2 maximum) (cid:127) Free-running or modulo up-count operation (cid:127) Toggle any channel pin on overflow (cid:127) TIM counter stop and reset bits 6.3 Pin Name Conventions The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are T[1,2]CH0 (timer channel 0) and T[1,2]CH1 (timer channel 1), where “1” is used to indicate TIM1 and “2” is used to indicate TIM2. The two TIMs share four I/O pins with four I/O port pins. The external clock input for TIM2 is shared with the an ADC channel pin. The full names of the TIM I/O pins are listed in Table 6-1. The generic pin names appear in the text that follows. Table 6-1. Pin Name Conventions TIM Generic Pin Names: T[1,2]CH0 T[1,2]CH1 T2CLK TIM1 PTD4/T1CH0 PTD5/T1CH1 — Full TIM Pin Names: TIM2 PTE0/T2CH0 PTE1/T2CH1 ADC12/T2CLK NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TCH0 may refer generically to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 69

Timer Interface Module (TIM) 6.4 Functional Description Figure 6-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels (per timer) are programmable independently as input capture or output compare channels. T2CLK (FOR TIM2 ONLY) PRESCALER SELECT INTERNAL PRESCALER BUS CLOCK TSTOP PS2 PS1 PS0 TRST 16-BIT COUNTER TOF INTERRUPT LOGIC TOIE 16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 ELS0B ELS0A CH0MAX PORT T[1,2]CH0 LOGIC 16-BIT COMPARATOR TCH0H:TCH0L CH0F 16-BIT LATCH INTERRUPT LOGIC MS0A CH0IE MS0B TOV1 CHANNEL 1 ELS0B ELS0A CH1MAX PORT T[1,2]CH1 S LOGIC U B 16-BIT COMPARATOR L A N TCH1H:TCH1L CH1F R TE 16-BIT LATCH CH01IE INTERRUPT IN LOGIC MS0A CH1IE Figure 6-1. TIM Block Diagram Figure 6-2 summarizes the timer registers. NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC and T2SC. MC68HC908JL16 Data Sheet, Rev. 1.1 70 Freescale Semiconductor

Functional Description Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 TIM1 Status and Control Read: TOF 0 0 TOIE TSTOP PS2 PS1 PS0 $0020 Register Write: 0 TRST (T1SC) Reset: 0 0 1 0 0 0 0 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 TIM1 Counter Register High $0021 Write: (T1CNTH) Reset: 0 0 0 0 0 0 0 0 TIM1 Counter Register Read: Bit 7 6 5 4 3 2 1 Bit 0 $0022 Low Write: (T1CNTL) Reset: 0 0 0 0 0 0 0 0 TIM Counter Modulo Register Read: Bit 15 14 13 12 11 10 9 Bit 8 $0023 High Write: (TMODH) Reset: 1 1 1 1 1 1 1 1 TIM1 Counter Modulo Read: Bit 7 6 5 4 3 2 1 Bit 0 $0024 Register Low Write: (T1MODL) Reset: 1 1 1 1 1 1 1 1 TIM1 Channel 0 Status and Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX $0025 Control Register Write: 0 (T1SC0) Reset: 0 0 0 0 0 0 0 0 TIM1 Channel 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 $0026 Register High Write: (T1CH0H) Reset: Indeterminate after reset TIM1 Channel 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 $0027 Register Low Write: (T1CH0L) Reset: Indeterminate after reset TIM1 Channel 1 Status and Read: CH1F 0 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX $0028 Control Register Write: 0 (T1SC1) Reset: 0 0 0 0 0 0 0 0 TIM1 Channel 1 Read: Bit 15 14 13 12 11 10 9 Bit 8 $0029 Register High Write: (T1CH1H) Reset: Indeterminate after reset TIM1 Channel 1 Read: Bit 7 6 5 4 3 2 1 Bit 0 $002A Register Low Write: (T1CH1L) Reset: Indeterminate after reset TIM2 Status and Control Read: TOF 0 0 TOIE TSTOP PS2 PS1 PS0 $0030 Register Write: 0 TRST (T2SC) Reset: 0 0 1 0 0 0 0 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 TIM2 Counter Register High $0031 Write: (T2CNTH) Reset: 0 0 0 0 0 0 0 0 TIM2 Counter Register Read: Bit 7 6 5 4 3 2 1 Bit 0 $0032 Low Write: (T2CNTL) Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 6-2. TIM I/O Register Summary (Sheet 1 of 2) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 71

Timer Interface Module (TIM) Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 TIM2 Counter Modulo Read: Bit 15 14 13 12 11 10 9 Bit 8 $0033 Register High Write: (T2MODH) Reset: 1 1 1 1 1 1 1 1 TIM2 Counter Modulo Read: Bit 7 6 5 4 3 2 1 Bit 0 $0034 Register Low Write: (T2MODL) Reset: 1 1 1 1 1 1 1 1 TIM2 Channel 0 Status and Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX $0035 Control Register Write: 0 (T2SC0) Reset: 0 0 0 0 0 0 0 0 TIM2 Channel 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 $0036 Register High Write: (T2CH0H) Reset: Indeterminate after reset TIM2 Channel 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 $0037 Register Low Write: (T2CH0L) Reset: Indeterminate after reset TIM2 Channel 1 Status and Read: CH1F 0 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX $0038 Control Register Write: 0 (T2SC1) Reset: 0 0 0 0 0 0 0 0 TIM2 Channel 1 Read: Bit 15 14 13 12 11 10 9 Bit 8 $0039 Register High Write: (T2CH1H) Reset: Indeterminate after reset TIM2 Channel 1 Read: Bit 7 6 5 4 3 2 1 Bit 0 $003A Register Low Write: (T2CH1L) Reset: Indeterminate after reset =Unimplemented Figure 6-2. TIM I/O Register Summary (Sheet 2 of 2) 6.4.1 TIM Counter Prescaler The TIM1 clock source can be one of the seven prescaler outputs; TIM2 clock source can be one of the seven prescaler outputs or the TIM2 clock pin, T2CLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register select the TIM clock source. 6.4.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. 6.4.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. MC68HC908JL16 Data Sheet, Rev. 1.1 72 Freescale Semiconductor

Functional Description 6.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 6.4.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: (cid:127) When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. (cid:127) When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 6.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares. 6.4.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 6-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 73

Timer Interface Module (TIM) to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See 6.9.1 TIM Status and Control Register. OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TCHx OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE Figure 6-3. PWM Period and Pulse Width The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 6.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 6.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: (cid:127) When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. (cid:127) When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the MC68HC908JL16 Data Sheet, Rev. 1.1 74 Freescale Semiconductor

Functional Description event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 6.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 6.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 6-3.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 6-3.) NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 75

Timer Interface Module (TIM) 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 6.9.4 TIM Channel Status and Control Registers.) 6.5 Interrupts The following TIM sources can generate interrupt requests: (cid:127) TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. (cid:127) TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM channel x status and control register. 6.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 6.6.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 6.6.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. 6.7 TIM During Break Interrupts A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 16.2.6.4 Break Flag Control Register (BFCR).) MC68HC908JL16 Data Sheet, Rev. 1.1 76 Freescale Semiconductor

I/O Signals To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. 6.8 I/O Signals Port D shares two of its pins with TIM1 and port E shares two of its pins with TIM2. The ADC12/T2CLK pin is an external clock input to TIM2. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0, and T2CH1. 6.8.1 TIM Clock Pin (ADC12/T2CLK) ADC12/T2CLK is an external clock input that can be the clock source for the TIM2 counter instead of the prescaled internal bus clock. Select the ADC12/T2CLK input by writing logic 1’s to the three prescaler select bits, PS[2:0]. (See 6.9.1 TIM Status and Control Register.) The minimum T2CLK pulse width, T2CLK or T2CLK , is: LMIN HMIN 1 -------------------------------------+t SU bus frequency The maximum T2CLK frequency is: bus frequency ÷ 2 ADC12/T2CLK is available as a ADC input channel pin when not used as the TIM2 clock input. 6.8.2 TIM Channel I/O Pins (PTD4/T1CH0, PTD5/T1CH1, PTE0/T2CH0, PTE1/T2CH1) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins. 6.9 I/O Registers NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC AND T2SC. These I/O registers control and monitor operation of the TIM: (cid:127) TIM status and control register (TSC) (cid:127) TIM counter registers (TCNTH:TCNTL) (cid:127) TIM counter modulo registers (TMODH:TMODL) (cid:127) TIM channel status and control registers (TSC0, TSC1) (cid:127) TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 77

Timer Interface Module (TIM) 6.9.1 TIM Status and Control Register The TIM status and control register (TSC): (cid:127) Enables TIM overflow interrupts (cid:127) Flags TIM overflows (cid:127) Stops the TIM counter (cid:127) Resets the TIM counter (cid:127) Prescales the TIM counter clock Address: T1SC, $0020 and T2SC, $0030 Bit 7 6 5 4 3 2 1 Bit 0 Read: TOF 0 0 TOIE TSTOP PS2 PS1 PS0 Write: 0 TRST Reset: 0 0 1 0 0 0 0 0 = Unimplemented Figure 6-4. TIM Status and Control Register (TSC) TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST — TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. MC68HC908JL16 Data Sheet, Rev. 1.1 78 Freescale Semiconductor

I/O Registers PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 6-2 shows. Reset clears the PS[2:0] bits. Table 6-2. Prescaler Selection PS2 PS1 PS0 TIM Clock Source 0 0 0 Internal bus clock ÷ 1 0 0 1 Internal bus clock ÷ 2 0 1 0 Internal bus clock ÷ 4 0 1 1 Internal bus clock ÷ 8 1 0 0 Internal bus clock ÷ 16 1 0 1 Internal bus clock ÷ 32 1 1 0 Internal bus clock ÷ 64 1 1 1 T2CLK (for TIM2 only) 6.9.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. Address: T1CNTH, $0021 and T2CNTH, $0031 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 6-5. TIM Counter Registers High (TCNTH) Address: T1CNTL, $0022 and T2CNTL, $0032 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 6-6. TIM Counter Registers Low (TCNTL) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 79

Timer Interface Module (TIM) 6.9.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers. Address: T1MODH, $0023 and T2MODH, $0033 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: 1 1 1 1 1 1 1 1 Figure 6-7. TIM Counter Modulo Register High (TMODH) Address: T1MODL, $0024 and T2MODL, $0034 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Reset: 1 1 1 1 1 1 1 1 Figure 6-8. TIM Counter Modulo Register Low (TMODL) NOTE Reset the TIM counter before writing to the TIM counter modulo registers. 6.9.4 TIM Channel Status and Control Registers Each of the TIM channel status and control registers: (cid:127) Flags input captures and output compares (cid:127) Enables input capture and output compare interrupts (cid:127) Selects input capture, output compare, or PWM operation (cid:127) Selects high, low, or toggling output on output compare (cid:127) Selects rising edge, falling edge, or any edge as the active input capture trigger (cid:127) Selects output toggling on TIM overflow (cid:127) Selects 0% and 100% PWM duty cycle (cid:127) Selects buffered or unbuffered output compare/PWM operation Address: T1SC0, $0025 and T2SC0, $0035 Bit 7 6 5 4 3 2 1 Bit 0 Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write: 0 Reset: 0 0 0 0 0 0 0 0 Figure 6-9. TIM Channel 0 Status and Control Register (TSC0) MC68HC908JL16 Data Sheet, Rev. 1.1 80 Freescale Semiconductor

I/O Registers Address: T1SC1, $0028 and T2SC1, $0038 Bit 7 6 5 4 3 2 1 Bit 0 Read: CH1F 0 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX Write: 0 Reset: 0 0 0 0 0 0 0 0 Figure 6-10. TIM Channel 1 Status and Control Register (TSC1) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA — Mode Select Bit A When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 6-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See Table 6-3. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 81

Timer Interface Module (TIM) ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 6-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 6-3. Mode, Edge, and Level Selection MSxB:MSxA ELSxB:ELSxA Mode Configuration X0 00 Pin under port control; initial output level high Output preset X1 00 Pin under port control; initial output level low 00 01 Capture on rising edge only 00 10 Input capture Capture on falling edge only 00 11 Capture on rising or falling edge 01 01 Toggle output on compare 01 10 Output compare or PWM Clear output on compare 01 11 Set output on compare 1X 01 Toggle output on compare Buffered output 1X 10 compare or Clear output on compare buffered PWM 1X 11 Set output on compare NOTE Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. TOVx — Toggle On Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow 0 = Channel x pin does not toggle on TIM counter overflow NOTE When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 6-11 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. MC68HC908JL16 Data Sheet, Rev. 1.1 82 Freescale Semiconductor

I/O Registers OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD TCHx OUTPUT OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE COMPARE CHxMAX Figure 6-11. CHxMAX Latency 6.9.5 TIM Channel Registers These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. Address: T1CH0H, $0026 and T2CH0H, $0036 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: Indeterminate after reset Figure 6-12. TIM Channel 0 Register High (TCH0H) Address: T1CH0L, $0027 and T2CH0L $0037 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Reset: Indeterminate after reset Figure 6-13. TIM Channel 0 Register Low (TCH0L) Address: T1CH1H, $0029 and T2CH1H, $0039 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: Indeterminate after reset Figure 6-14. TIM Channel 1 Register High (TCH1H) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 83

Timer Interface Module (TIM) Address: T1CH1L, $002A and T2CH1L, $003A Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Reset: Indeterminate after reset Figure 6-15. TIM Channel 1 Register Low (TCH1L) MC68HC908JL16 Data Sheet, Rev. 1.1 84 Freescale Semiconductor

Chapter 7 Serial Communications Interface (SCI) 7.1 Introduction This section describes the serial communications interface (SCI) module, which allows high-speed asynchronous communications with peripheral devices and other MCUs. NOTE References to DMA (direct-memory access) and associated functions are only valid if the MCU has a DMA module. This MCU does not have the DMA function. Any DMA-related register bits should be left in their reset state for normal MCU operation. 7.2 Features Features of the SCI module include the following: (cid:127) Full-duplex operation (cid:127) Standard mark/space non-return-to-zero (NRZ) format (cid:127) 32 programmable baud rates (cid:127) Programmable 8-bit or 9-bit character length (cid:127) Separately enabled transmitter and receiver (cid:127) Separate receiver and transmitter CPU interrupt requests (cid:127) Programmable transmitter output polarity (cid:127) Two receiver wakeup methods: – Idle line wakeup – Address mark wakeup (cid:127) Interrupt-driven operation with eight interrupt flags: – Transmitter empty – Transmission complete – Receiver full – Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error (cid:127) Receiver framing error detection (cid:127) Hardware parity checking (cid:127) 1/16 bit-time noise detection (cid:127) Bus clock as baud rate clock source MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 85

Serial Communications Interface (SCI) 7.3 Pin Name Conventions The generic names of the SCI I/O pins are: (cid:127) RxD (receive data) (cid:127) TxD (transmit data) The SCI I/O (input/output) lines are dedicated pins for the SCI module. Table 7-1 shows the full names and the generic names of the SCI I/O pins. The generic pin names appear in the text of this section. Table 7-1. Pin Name Conventions Generic Pin Names: RxD TxD Full Pin Names: PTD7/RxD/SDA(1) PTD6/TxD/SCL(1) 1. Position of MMIIC module pins (SDA and SCL) is user selectable using CONFIG2 option bit. Refer to Chapter 3 Configuration and Mask Option Registers (CONFIG and MOR) for additional information. SDA/SCL have priority over the RxD/TxD when MMIIC is enabled and using PTD7/PTD6 for its pins. For more information on MMIIC, (see Chapter 8 Multi-Master IIC Interface (MMIIC)). 7.4 Functional Description Figure 7-2 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. The baud rate clock source for the SCI is the bus clock. Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: SCI Control Register 1 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY $0013 Write: (SCC1) Reset: 0 0 0 0 0 0 0 0 Read: SCI Control Register 2 SCTIE TCIE SCRIE ILIE TE RE RWU SBK $0014 Write: (SCC2) Reset: 0 0 0 0 0 0 0 0 Read: R8 SCI Control Register 3 T8 DMARE DMATE ORIE NEIE FEIE PEIE $0015 Write: (SCC3) Reset: U U 0 0 0 0 0 0 Read: SCTE TC SCRF IDLE OR NF FE PE SCI Status Register 1 $0016 Write: (SCS1) Reset: 1 1 0 0 0 0 0 0 Read: BKF RPF SCI Status Register 2 $0017 Write: (SCS2) Reset: 0 0 0 0 0 0 0 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 SCI Data Register $0018 Write: T7 T6 T5 T4 T3 T2 T1 T0 (SCDR) Reset: Unaffected by reset Read: 0 0 SCI Baud Rate Register SCP1 SCP0 R SCR2 SCR1 SCR0 $0019 Write: (SCBR) Reset: 0 0 0 0 0 0 0 0 =Unimplemented R = Reserved U = Unaffected Figure 7-1. SCI I/O Register Summary MC68HC908JL16 Data Sheet, Rev. 1.1 86 Freescale Semiconductor

Functional Description INTERNAL BUS SCI DATA SCI DATA REGISTER REGISTER R RxD SHIFRTE RCEEGIVISETER DMAINTERRUPTCONTROL TRANSMITTEINTERRUPTCONTROL RECEIVERINTERRUPTCONTROL ERRORINTERRUPTCONTROL SHITFRT ARNESGMISITTER TxD TXINV SCTIE R8 TCIE T8 SCRIE ILIE DMARE TE SCTE DMATE RE TC RWU SCRF OR ORIE SBK IDLE NF NEIE FE FEIE PE PEIE LOOPS LOOPS ENSCI WAKEUP RECEIVE FLAG TRANSMIT CONTROL CONTROL CONTROL CONTROL M BKF ENSCI WAKE RPF ILTY PRE- BAUD PEN BUS CLOCK ÷ 4 SCALER DIVIDER PTY ÷ 16 DATA SELECTION CONTROL Figure 7-2. SCI Module Block Diagram 7.4.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 7-3. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 87

Serial Communications Interface (SCI) 8-BIT DATA FORMAT PARITY BIT M IN SCC1 CLEAR BIT NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT BIT 9-BIT DATA FORMAT PARITY BIT M IN SCC1 SET BIT NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP BIT BIT Figure 7-3. SCI Data Formats 7.4.2 Transmitter Figure 7-4 shows the structure of the SCI transmitter. The baud rate clock source for the SCI is the bus clock. INTERNAL BUS PRE- BAUD BUS CLOCK ÷ 4 ÷ 16 SCI DATA REGISTER SCALER DIVIDER SCP1 11-BIT T SCP0 OP TRANSMIT AR T SHIFT REGISTER T SCR1 S S H 8 7 6 5 4 3 2 1 0 L TxD SCR2 SCR0 B UEST EST TXINV MS Q U E Q R E RRUPT VICE R M DR MITTER CPU INTE MITTER DMA SER PPETNY GENPAETRR8IATTYION LOAD FROM SC SHIFT ENABLE PREAMBLEALL 1s BREAKALL 0s S S AN AN DMATE TRANSMITTER TR TR DMATE CONTROL LOGIC SCTIE SCTE SCTE SBK DMATE SCTE LOOPS SCTIE SCTIE ENSCI TC TC TE TCIE TCIE Figure 7-4. SCI Transmitter MC68HC908JL16 Data Sheet, Rev. 1.1 88 Freescale Semiconductor

Functional Description 7.4.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 7.4.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The SCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1). 2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register 2 (SCC2). 3. Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing to the SCDR. 4. Repeat step 3 for each subsequent transmission. At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt request. When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port pin. 7.4.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers: (cid:127) Sets the framing error bit (FE) in SCS1 (cid:127) Sets the SCI receiver full bit (SCRF) in SCS1 (cid:127) Clears the SCI data register (SCDR) (cid:127) Clears the R8 bit in SCC3 (cid:127) Sets the break flag bit (BKF) in SCS2 (cid:127) May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 89

Serial Communications Interface (SCI) 7.4.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost. Toggle the TE bit for a queued idle character when the SCTE bit becomes set and just before writing the next byte to the SCDR. 7.4.2.5 Inversion of Transmitted Output The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at logic 1. (See 7.8.1 SCI Control Register 1.) 7.4.2.6 Transmitter Interrupts These conditions can generate CPU interrupt requests from the SCI transmitter: (cid:127) SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. (cid:127) Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. 7.4.3 Receiver Figure 7-5 shows the structure of the SCI receiver. 7.4.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 7.4.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. MC68HC908JL16 Data Sheet, Rev. 1.1 90 Freescale Semiconductor

Functional Description INTERNAL BUS SCR1 SCP1 SCR2 SCI DATA REGISTER SCP0 SCR0 PRE- BAUD BUS CLOCK ÷ 4 SCALER DIVIDER ÷ 16 P 11-BIT RT O A T RECEIVE SHIFT REGISTER T S S DATA RxD RECOVERY H 8 7 6 5 4 3 2 1 0 L ALL 0s BKF s 1 RPF ALL MSB T S E U Q M E T RWU RRUPT R QUEST REQUES WILATKYE WLAOKGEIUCP SIDCLREF PU INTE VICE RE RRUPT PEN PARITY R8 C R E CHECKING RROR MA SE PU INT PTY IDLE E D C ILIE ILIE DMARE SCRF SCRIE SCRIE DMARE SCRF SCRIE DMARE DMARE OR OR ORIE ORIE NF NF NEIE NEIE FE FE FEIE FEIE PE PE PEIE PEIE Figure 7-5. SCI Receiver Block Diagram MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 91

Serial Communications Interface (SCI) 7.4.3.3 Data Sampling The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following times (see Figure 7-6): (cid:127) After every start bit (cid:127) After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. START BIT LSB RxD START BIT START BIT DATA SAMPLES QUALIFICATION VERIFICATION SAMPLING RT CLOCK RT CLOCK 1 1 1 1 1 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 STATE RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT CLOCK RESET Figure 7-6. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 7-2 summarizes the results of the start bit verification samples. Table 7-2. Start Bit Verification RT3, RT5, and RT7 Start Bit Noise Flag Samples Verification 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. MC68HC908JL16 Data Sheet, Rev. 1.1 92 Freescale Semiconductor

Functional Description To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 7-3 summarizes the results of the data bit samples. Table 7-3. Data Bit Recovery RT8, RT9, and RT10 Data Bit Noise Flag Samples Determination 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 7-4 summarizes the results of the stop bit samples. Table 7-4. Stop Bit Recovery RT8, RT9, and RT10 Framing Noise Flag Samples Error Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 7.4.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 93

Serial Communications Interface (SCI) 7.4.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance Figure 7-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. MSB STOP RECEIVER RT CLOCK 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 T T T T T T T T T 1 1 1 1 1 1 1 R R R R R R R R R T T T T T T T R R R R R R R DATA SAMPLES Figure 7-7. Slow Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 7-7, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is 154–147 -------------------------- ×100 = 4.54% 154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 7-7, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170–163 -------------------------- ×100 = 4.12% 170 MC68HC908JL16 Data Sheet, Rev. 1.1 94 Freescale Semiconductor

Functional Description Fast Data Tolerance Figure 7-8 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. STOP IDLE OR NEXT CHARACTER RECEIVER RT CLOCK 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 T T T T T T T T T 1 1 1 1 1 1 1 R R R R R R R R R T T T T T T T R R R R R R R DATA SAMPLES Figure 7-8. Fast Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 7-8, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times × 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 154–160 · -------------------------- ×100 = 3.90% 154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 7-8, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 170–176 -------------------------- ×100 = 3.53% 170 7.4.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 95

Serial Communications Interface (SCI) (cid:127) Address mark — An address mark is a logic 1 in the most significant bit position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. (cid:127) Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. NOTE With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately. 7.4.3.7 Receiver Interrupts The following sources can generate CPU interrupt requests from the SCI receiver: (cid:127) SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU interrupts. (cid:127) Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU interrupt requests. 7.4.3.8 Error Interrupts The following receiver error flags in SCS1 can generate CPU interrupt requests: (cid:127) Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR. The previous character remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. (cid:127) Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. (cid:127) Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. (cid:127) Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests. MC68HC908JL16 Data Sheet, Rev. 1.1 96 Freescale Semiconductor

Low-Power Modes 7.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 7.5.1 Wait Mode The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. Refer to 4.6 Low-Power Modes in for information on exiting wait mode. 7.5.2 Stop Mode The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect SCI register states. SCI module operation resumes after an external interrupt. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data. Refer to 4.6 Low-Power Modes for information on exiting stop mode. 7.6 SCI During Break Module Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. 7.7 I/O Signals The two SCI I/O pins are: (cid:127) PTD6/TxD/SCL — Transmit data (cid:127) PTD7/RxD/SDA — Receive data 7.7.1 TxD (Transmit Data) The PTD6/TxD/SCL pin is the serial data output from the SCI transmitter. 7.7.2 RxD (Receive Data) The PTD7/RxD/SDA pin is the serial data input to the SCI receiver. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 97

Serial Communications Interface (SCI) 7.8 I/O Registers These I/O registers control and monitor SCI operation: (cid:127) SCI control register 1 (SCC1) (cid:127) SCI control register 2 (SCC2) (cid:127) SCI control register 3 (SCC3) (cid:127) SCI status register 1 (SCS1) (cid:127) SCI status register 2 (SCS2) (cid:127) SCI data register (SCDR) (cid:127) SCI baud rate register (SCBR) 7.8.1 SCI Control Register 1 SCI control register 1: (cid:127) Enables loop mode operation (cid:127) Enables the SCI (cid:127) Controls output polarity (cid:127) Controls character length (cid:127) Controls SCI wakeup method (cid:127) Controls idle character detection (cid:127) Enables parity function (cid:127) Controls parity type Address: $0013 Bit 7 6 5 4 3 2 1 Bit 0 Read: LOOPS ENSCI TXINV M WAKE ILTY PEN PTY Write: Reset: 0 0 0 0 0 0 0 0 Figure 7-9. SCI Control Register 1 (SCC1) LOOPS — Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled ENSCI — Enable SCI Bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = SCI enabled 0 = SCI disabled TXINV — Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted NOTE Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits. MC68HC908JL16 Data Sheet, Rev. 1.1 98 Freescale Semiconductor

I/O Registers M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 7-5.) The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters WAKE — Wakeup Condition Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup ILTY — Idle Line Type Bit This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit PEN — Parity Enable Bit This read/write bit enables the SCI parity function. (See Table 7-5.) When enabled, the parity function inserts a parity bit in the most significant bit position. (See Figure 7-3.) Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled PTY — Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 7-5.) Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Table 7-5. Character Format Selection Control Bits Character Format M PEN and PTY Start Bits Data Bits Parity Stop Bits Character Length 0 0X 1 8 None 1 10 bits 1 0X 1 9 None 1 11 bits 0 10 1 7 Even 1 10 bits 0 11 1 7 Odd 1 10 bits 1 10 1 8 Even 1 11 bits 1 11 1 8 Odd 1 11 bits MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 99

Serial Communications Interface (SCI) 7.8.2 SCI Control Register 2 SCI control register 2: (cid:127) Enables the following CPU interrupt requests: – Enables the SCTE bit to generate transmitter CPU interrupt requests – Enables the TC bit to generate transmitter CPU interrupt requests – Enables the SCRF bit to generate receiver CPU interrupt requests – Enables the IDLE bit to generate receiver CPU interrupt requests (cid:127) Enables the transmitter (cid:127) Enables the receiver (cid:127) Enables SCI wakeup (cid:127) Transmits SCI break characters Address: $0014 Bit 7 6 5 4 3 2 1 Bit 0 Read: SCTIE TCIE SCRIE ILIE TE RE RWU SBK Write: Reset: 0 0 0 0 0 0 0 0 Figure 7-10. SCI Control Register 2 (SCC2) SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt TCIE — Transmission Complete Interrupt Enable Bit This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests SCRIE — SCI Receive Interrupt Enable Bit This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt ILIE — Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests MC68HC908JL16 Data Sheet, Rev. 1.1 100 Freescale Semiconductor

I/O Registers TE — Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the TxD returns to the idle condition (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled NOTE Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RWU — Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK — Send Break Bit Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted NOTE Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 101

Serial Communications Interface (SCI) 7.8.3 SCI Control Register 3 SCI control register 3: (cid:127) Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted (cid:127) Enables these interrupts: – Receiver overrun interrupts – Noise error interrupts – Framing error interrupts (cid:127) Parity error interrupts Address: $0015 Bit 7 6 5 4 3 2 1 Bit 0 Read: R8 T8 DMARE DMATE ORIE NEIE FEIE PEIE Write: Reset: U U 0 0 0 0 0 0 = Unimplemented U = Unaffected Figure 7-11. SCI Control Register 3 (SCC3) R8 — Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset has no effect on the T8 bit. DMARE — DMA Receive Enable Bit CAUTION The DMA module is not included on this MCU. Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance. 1 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI receiver CPU interrupt requests enabled) 0 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI receiver CPU interrupt requests enabled) DMATE — DMA Transfer Enable Bit CAUTION The DMA module is not included on this MCU. Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance. 1 = SCTE DMA service requests enabled; SCTE CPU interrupt requests disabled 0 = SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled ORIE — Receiver Overrun Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR. 1 = SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled MC68HC908JL16 Data Sheet, Rev. 1.1 102 Freescale Semiconductor

I/O Registers NEIE — Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = SCI error CPU interrupt requests from NE bit enabled 0 = SCI error CPU interrupt requests from NE bit disabled FEIE — Receiver Framing Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = SCI error CPU interrupt requests from FE bit enabled 0 = SCI error CPU interrupt requests from FE bit disabled PEIE — Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the parity error bit, PE. (See 7.8.4 SCI Status Register 1.) Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled 7.8.4 SCI Status Register 1 SCI status register 1 (SCS1) contains flags to signal these conditions: (cid:127) Transfer of SCDR data to transmit shift register complete (cid:127) Transmission complete (cid:127) Transfer of receive shift register data to SCDR complete (cid:127) Receiver input idle (cid:127) Receiver overrun (cid:127) Noisy data (cid:127) Framing error (cid:127) Parity error Address: $0016 Bit 7 6 5 4 3 2 1 Bit 0 Read: SCTE TC SCRF IDLE OR NF FE PE Write: Reset: 1 1 0 0 0 0 0 0 = Unimplemented Figure 7-12. SCI Status Register 1 (SCS1) SCTE — SCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 103

Serial Communications Interface (SCI) TC — Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF — SCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR IDLE — Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) OR — Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence. Figure 7-13 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register. NF — Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an SCI error CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected MC68HC908JL16 Data Sheet, Rev. 1.1 104 Freescale Semiconductor

I/O Registers FE — Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected PE — Receiver Parity Error Bit This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates an SCI error CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected NORMAL FLAG CLEARING SEQUENCE 1 0 1 0 1 0 = = = = = = F F F F F F R R R R R R C C C C C C S S S S S S BYTE 1 BYTE 2 BYTE 3 BYTE 4 READ SCS1 READ SCS1 READ SCS1 SCRF = 1 SCRF = 1 SCRF = 1 OR = 0 OR = 0 OR = 0 READ SCDR READ SCDR READ SCDR BYTE 1 BYTE 2 BYTE 3 DELAYED FLAG CLEARING SEQUENCE 1 1 0 1 0 CRF = CRF = R = 1 CRF = R = 1 CRF = R = 1 CRF = R = 0 S SO SO SO SO BYTE 1 BYTE 2 BYTE 3 BYTE 4 READ SCS1 READ SCS1 SCRF = 1 SCRF = 1 OR = 0 OR = 1 READ SCDR READ SCDR BYTE 1 BYTE 3 Figure 7-13. Flag Clearing Sequence MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 105

Serial Communications Interface (SCI) 7.8.5 SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions: (cid:127) Break character detected (cid:127) Incoming data Address: $0017 Bit 7 6 5 4 3 2 1 Bit 0 Read: BKF RPF Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 7-14. SCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected RPF — Reception in Progress Flag Bit This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress 7.8.6 SCI Data Register The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register. Address: $0018 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset Figure 7-15. SCI Data Register (SCDR) R7/T7–R0/T0 — Receive/Transmit Data Bits Reading the SCDR accesses the read-only received data bits, R[7:0]. Writing to the SCDR writes the data to be transmitted, T[7:0]. Reset has no effect on the SCDR. NOTE Do not use read/modify/write instructions on the SCI data register. MC68HC908JL16 Data Sheet, Rev. 1.1 106 Freescale Semiconductor

I/O Registers 7.8.7 SCI Baud Rate Register The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter. Address: $0019 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 SCP1 SCP0 R SCR2 SCR1 SCR0 Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented R = Reserved Figure 7-16. SCI Baud Rate Register (SCBR) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 7-6. Reset clears SCP1 and SCP0. Table 7-6. SCI Baud Rate Prescaling SCP1 and SCP0 Prescaler Divisor (PD) 00 1 01 3 10 4 11 13 SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 7-7. Reset clears SCR2–SCR0. Table 7-7. SCI Baud Rate Selection SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Use this formula to calculate the SCI baud rate: SCI clock source baud rate = --------------------------------------------- 64×PD×BD where: SCI clock source = bus clock PD = prescaler divisor BD = baud rate divisor Table 7-8 shows the SCI baud rates that can be generated with a 4.9152 MHz bus clock. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 107

Serial Communications Interface (SCI) Table 7-8. SCI Baud Rate Selection Examples Prescaler SCR2, SCR1, Baud Rate Baud Rate SCP1 and SCP0 Divisor (PD) and SCR0 Divisor (BD) (BUS CLOCK= 4.9152 MHz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9,600 00 1 100 16 4,800 00 1 101 32 2,400 00 1 110 64 1,200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6,400 01 3 011 8 3,200 01 3 100 16 1,600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9,600 10 4 010 4 4,800 10 4 011 8 2,400 10 4 100 16 1,200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5,908 11 13 001 2 2,954 11 13 010 4 1,477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 MC68HC908JL16 Data Sheet, Rev. 1.1 108 Freescale Semiconductor

Chapter 8 Multi-Master IIC Interface (MMIIC) 8.1 Introduction The Multi-master IIC (MMIIC) Interface is designed for internal serial communication between the MCU and other IIC devices. A hardware circuit generates “start” and “stop” signal, while byte by byte data transfer is interrupt driven by the software algorithm. Therefore, it can greatly help the software in dealing with other devices to have higher system efficiency in a typical digital monitor system. The MMIIC not only can be applied in internal communications, but can also be used as a typical command reception serial bus for factory setup and alignment purposes. It also provides the flexibility of hooking additional devices to an existing system for future expansion without adding extra hardware. This Multi-master IIC module uses the SCL clock line and the SDA data line to communicate with external DDC host or IIC interface. These two pins are user selectable using the CONFIG2 register (see Figure 3-3. Configuration Register 2 (CONFIG2)) to share either PTA2/PTA3 or PTD6/PTD7 based on their application needs. The maximum data rate typically is 400k-bps. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pF. NOTE The outputs of SCL and SDA pins are open-drain type, these pins contain ESD clamping diodes to V and therefore cannot be driven to higher than DD V + 0.3 V. DD 8.2 Features (cid:127) Compatibility with multi-master IIC bus standard (cid:127) Software controllable acknowledge bit generation (cid:127) Interrupt driven byte by byte data transfer (cid:127) Calling address identification interrupt (cid:127) Auto detection of R/W bit and switching of transmit or receive mode (cid:127) Detection of START, repeated START, and STOP signals (cid:127) Auto generation of START and STOP condition in master mode (cid:127) Arbitration loss detection and No-ACK awareness in master mode (cid:127) 8 selectable baud rate master clocks (cid:127) Automatic recognition of the received acknowledge bit MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 109

Multi-Master IIC Interface (MMIIC) 8.3 I/O Pins The MMIIC module uses two I/O pins, shared with standard port I/O pins. The full name of the MMIIC I/O pins are listed in Table 8-1. The generic pin name appear in the text that follows. Table 8-1. Pin Name Conventions MMIIC Full MCU Pin Names: Generic Pin Names: PTA2/KBI2/SDA(1) SDA PTD7/RxD/SDA PTA3/KBI3/SCL(1) SCL PTD6/TxD/SCL 1. Position of MMIIC module pins is user selectable using CONFIG2 option bit. Refer to Chapter 3 Configuration and Mask Option Registers (CONFIG and MOR) for additional information. Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: MMALIF MMNAKIF MMBB Multi-Master IIC MMAST MMRW MMBR2 MMBR1 MMBR0 $0040 Master Control Register Write: 0 0 (MIMCR) Reset: 0 0 0 0 0 0 0 0 Read: Multi-Master IIC Address MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD $0041 Register Write: (MMADR) Reset: 1 0 1 0 0 0 0 0 Read: 0 0 0 0 Multi-Master IIC Control Reg- MMEN MMIEN MMTXAK REPSEN $0042 ister Write: (MMCR) Reset: 0 0 0 0 0 0 0 0 Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK 0 MMTXBE MMRXBF Multi-Master IIC $0043 Status Register Write: 0 0 (MMSR) Reset: 0 0 0 0 1 0 1 0 Read: Multi-Master IIC MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0 $0044 Data Transmit Register Write: (MMDTR) Reset: 1 1 1 1 1 1 1 1 Multi-Master IIC Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0 Data Receive Register $0045 Write: (MMDRR) Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 8-1. MMIIC I/O Register Summary MC68HC908JL16 Data Sheet, Rev. 1.1 110 Freescale Semiconductor

Functional Description 8.4 Functional Description The Multi-master IIC (MMIIC) Interface is designed for internal serial communication between the MCU and other IIC devices. The interface uses 2 pins, SCL and SDA for clocking and serial data. 8.4.1 IIC Protocol The IIC bus system uses a Serial Data line (SDA) and a Serial Clock Line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. Logic AND function is exercised on both lines with external pull-up resistors, the value of these resistors is system dependent. Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system communication is described briefly in the following sections and illustrated in Figure 8-2. MSB LSB MSB LSB SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 Start Calling Address Read/ Ack Data Byte No Stop Signal Write Bit Ack Signal Bit MSB LSB MSB LSB SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Calling Address Read/ Ack Repeated New Calling Address Read/ No Stop Signal Write Bit Start Write Ack Signal Signal Bit Figure 8-2. IIC Bus Transmission Signals 8.4.2 START Signal When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 8-2, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 111

Multi-Master IIC Interface (MMIIC) 8.4.3 Slave Address Transmission The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 8-2). No two slaves in the system may have the same address. If the IIC is master and it transmits an address that is equal to its own slave address an interrupt flag is set. The IIC cannot be master and slave at the same time. However, if arbitration is lost during an address cycle the IIC will revert to slave mode and operate correctly even if it is being addressed by another master. 8.4.4 Data Transfer Once successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 8-2. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one complete data transfer needs nine clock pulses. If the slave receiver does not acknowledge the master in the 9th bit time, the SDA line must be left high by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer. If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the SDA line. In either case, the data transfer is aborted and the master does one of two things: (cid:127) Relinquishes the bus by generating a STOP signal. (cid:127) Commences a new calling by generating a repeated START signal. 8.4.5 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical “1” (see Figure 8-2). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus. MC68HC908JL16 Data Sheet, Rev. 1.1 112 Freescale Semiconductor

Functional Description 8.4.6 Repeated START Signal As shown in Figure 8-2, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 8.4.7 Arbitration Procedure The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic “1” while another master transmits logic “0”. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 8.4.8 Clock Synchronization Since wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all the devices connected on the bus. The devices start counting their low period and once a device's clock has gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is still within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 8-3). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. Delay Start Counting High Period SCL1 SCL2 SCL Internal Counter Reset Figure 8-3. IIC Clock Synchronization MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 113

Multi-Master IIC Interface (MMIIC) 8.4.9 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 8.4.10 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it. If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. 8.4.11 Modes of Operation The basic mode of operation for the IIC module is normal mode. When the MCU issues a STOP instruction, the IIC module will power down while the STOP mode signal is active. The STOP instruction does not affect IIC register states. 8.5 Interrupts The following MMIIC source can generate interrupt requests: (cid:127) Multi-Master IIC Arbitration Lost Interrupt Flag (MMALIF) — MMALIF is set when software attempt to set MMAST but the MMBB has been set by detecting the start condition on the lines or when the MMIIC is transmitting a “1” to SDA line but detected a “0” from SDA line in master mode – an arbitration loss. (cid:127) Multi-Master IIC Receive Interrupt Flag (MMRXIF) — MMRXIF is set after the data receive register (MMDRR) is loaded with a new received data. Once the MMDRR is loaded with received data, no more received data can be loaded to the MMDRR register until the CPU reads the data from the MMDRR to clear MMRXBF flag. (cid:127) Multi-Master IIC Transmit Interrupt Flag (MMTXIF) — MMTXIF is set when data in the data transmit register (MMDTR) is downloaded to the output circuit, and that new data can be written to the MMDTR. 8.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 8.6.1 Wait Mode The MMIC module remains active in wait mode. 8.6.2 Stop Mode The MMIIC module remains active in stop mode. MC68HC908JL16 Data Sheet, Rev. 1.1 114 Freescale Semiconductor

MMIIC During Break Interrupts 8.7 MMIIC During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See BFCR in the SIM section of this data sheet. To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 8.8 Multi-Master IIC Registers Six registers are associated with the Multi-master IIC module, they are outlined in the following sections. 8.8.1 Multi-Master IIC Address Register (MMADR) Address:$0041 Bit 7 6 5 4 3 2 1 Bit 0 Read: MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD Write: Reset: 1 0 1 0 0 0 0 0 Figure 8-4. Multi-Master IIC Address Register (MMADR) MMAD[7:1] — Multi-Master Address These seven bits represent the MMIIC interface’s own specific slave address when in slave mode, and the calling address when in master mode. Software must update MMAD[7:1] as the calling address while entering master mode and restore its own slave address after master mode is relinquished. This register is cleared as $A0 upon reset. MMEXTAD — Multi-Master Expanded Address This bit is set to expand the address of the MMIIC in slave mode. When set, the MMIIC will acknowledge the following addresses from a calling master: $MMAD[7:1], 0000000, and 0001100. Reset clears this bit. 1 = MMIIC responds to the following calling addresses: $MMAD[7:1], 0000000, and 0001100. 0 = MMIIC responds to address $MMAD[7:1] For example, when MMADR is configured as: MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD 1 1 0 1 0 1 0 1 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 115

Multi-Master IIC Interface (MMIIC) The MMIIC module will respond to the calling address: Bit 7 6 5 4 3 2 Bit 1 1 1 0 1 0 1 0 or the general calling address: 0 0 0 0 0 0 0 or the calling address: 0 0 0 1 1 0 0 NOTE Bit 0 of the 8-bit calling address is the MMRW bit from the calling master. 8.8.2 Multi-Master IIC Control Register (MMCR) Address:$0042 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 MMEN MMIEN MMTXAK REPSEN Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 8-5. Multi-Master IIC Control Register (MMCR) MMEN — Multi-Master IIC Enable This bit is set to enable the Multi-master IIC module. When MMEN = 0, module is disabled and all flags will restore to its power-on default states. Reset clears this bit. 1 = MMIIC module enabled 0 = MMIIC module disabled MMIEN — Multi-Master IIC Interrupt Enable When this bit is set, the MMTXIF, MMRXIF, MMALIF, and MMNAKIF flags are enabled to generate an interrupt request to the CPU. When MMIEN is cleared, the these flags are prevented from generating an interrupt request. Reset clears this bit. 1 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will generate interrupt request to CPU 0 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will not generate interrupt request to CPU MMTXAK — Transmit Acknowledge Enable This bit is set to disable the MMIIC from sending out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. When MMTXAK is cleared, an acknowledge signal will be sent at the 9th clock bit. Reset clears this bit. 1 = MMIIC does not send acknowledge signals at 9th clock bit 0 = MMIIC sends acknowledge signal at 9th clock bit REPSEN — Repeated Start Enable This bit is set to enable repeated START signal to be generated when in master mode transfer (MMAST = 1). The REPSEN bit is cleared by hardware after the completion of repeated START signal or when the MMAST bit is cleared. Reset clears this bit. 1 = Repeated START signal will be generated if MMAST bit is set 0 = No repeated START signal will be generated MC68HC908JL16 Data Sheet, Rev. 1.1 116 Freescale Semiconductor

Multi-Master IIC Registers 8.8.3 Multi-Master IIC Master Control Register (MIMCR) Address:$0040 Bit 7 6 5 4 3 2 1 Bit 0 Read: MMALIF MMNAKIF MMBB MMAST MMRW MMBR2 MMBR1 MMBR0 Write: 0 0 Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 8-6. Multi-Master IIC Master Control Register (MIMCR) MMALIF — Multi-Master Arbitration Lost Interrupt Flag This flag is set when software attempt to set MMAST but the MMBB has been set by detecting the start condition on the lines or when the MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA line in master mode – an arbitration loss. This bit generates an interrupt request to the CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset. 1 = Lost arbitration in master mode 0 = No arbitration lost MMNAKIF — No Acknowledge Interrupt Flag This flag is only set in master mode (MMAST = 1) when there is no acknowledge bit detected after one data byte or calling address is transferred. This flag also clears MMAST. MMNAKIF generates an interrupt request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset. 1 = No acknowledge bit detected 0 = Acknowledge bit detected MMBB — Bus Busy Flag This flag is set after a start condition is detected (bus busy), and is cleared when a stop condition (bus idle) is detected. Reset clears this bit. 1 = Start condition detected 0 = Stop condition detected or MMIIC is disabled MMAST — Master Control Bit This bit is set to initiate a master mode transfer. In master mode, the module generates a start condition to the SDA and SCL lines, followed by sending the calling address stored in MMADR. When the MMAST bit is cleared by MMNAKIF set (no acknowledge) or by software, the module generates the stop condition to the lines after the current byte is transmitted. If an arbitration loss occurs (MMALIF = 1), the module reverts to slave mode by clearing MMAST, and releasing SDA and SCL lines immediately. This bit is cleared by writing “0” to it or by reset. 1 = Master mode operation 0 = Slave mode operation MMRW — Master Read/Write This bit will be transmitted out as bit 0 of the calling address when the module sets the MMAST bit to enter master mode. The MMRW bit determines the transfer direction of the data bytes that follows. When it is "1", the module is in master receive mode. When it is "0", the module is in master transmit mode. Reset clears this bit. 1 = Master mode receive 0 = Master mode transmit MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 117

Multi-Master IIC Interface (MMIIC) MMBR2–MMBR0 — Baud Rate Select These three bits select one of eight clock rates as the master clock when the module is in master mode. Since this master clock is derived the CPU bus clock, the user program should not execute the WAIT instruction when the MMIIC module in master mode. This will cause the SDA and SCL lines to hang, as the WAIT instruction places the MCU in wait mode, with CPU clock is halted. These bits are cleared upon reset. (See Table 8-2.) Table 8-2. Baud Rate Select MMBR2 MMBR1 MMBR0 Baud Rate 0 0 0 Internal bus clock ÷ 8 0 0 1 Internal bus clock ÷ 16 0 1 0 Internal bus clock ÷ 32 0 1 1 Internal bus clock ÷ 64 1 0 0 Internal bus clock ÷ 128 1 0 1 Internal bus clock ÷ 256 1 1 0 Internal bus clock ÷ 512 1 1 1 Internal bus clock ÷ 1024 8.8.4 Multi-Master IIC Status Register (MMSR) Address:$0043 Bit 7 6 5 4 3 2 1 Bit 0 Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK 0 MMTXBE MMRXBF Write: 0 0 Reset: 0 0 0 0 1 0 1 0 =Unimplemented Figure 8-7. Multi-Master IIC Status Register (MMSR) MMRXIF — Multi-Master IIC Receive Interrupt Flag This flag is set after the data receive register (MMDRR) is loaded with a new received data. Once the MMDRR is loaded with received data, no more received data can be loaded to the MMDRR register until the CPU reads the data from the MMDRR to clear MMRXBF flag. MMRXIF generates an interrupt request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset; or when the MMEN = 0. 1 = New data in data receive register (MMDRR) 0 = No data received MMTXIF — Multi-Master Transmit Interrupt Flag This flag is set when data in the data transmit register (MMDTR) is downloaded to the output circuit, and that new data can be written to the MMDTR. MMTXIF generates an interrupt request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or when the MMEN = 0. 1 = Data transfer completed 0 = Data transfer in progress MMATCH — Multi-Master Address Match This flag is set when the received data in the data receive register (MMDRR) is an calling address which matches with the address or its extended addresses (MMEXTAD=1) specified in the MMADR register. 1 = Received address matches MMADR 0 = Received address does not match MC68HC908JL16 Data Sheet, Rev. 1.1 118 Freescale Semiconductor

Multi-Master IIC Registers MMSRW — Multi-Master Slave Read/Write This bit indicates the data direction when the module is in slave mode. It is updated after the calling address is received from a master device. MMSRW = 1 when the calling master is reading data from the module (slave transmit mode). MMSRW = 0 when the master is writing data to the module (receive mode). 1 = Slave mode transmit 0 = Slave mode receive MMRXAK — Multi-Master Receive Acknowledge When this bit is cleared, it indicates an acknowledge signal has been received after the completion of 8 data bits transmission on the bus. When MMRXAK is set, it indicates no acknowledge signal has been detected at the 9th clock; the module will release the SDA line for the master to generate "stop" or "repeated start" condition. Reset sets this bit. 1 = No acknowledge signal received at 9th clock bit 0 = Acknowledge signal received at 9th clock bit MMTXBE — Multi-Master Transmit Buffer Empty This flag indicates the status of the data transmit register (MMDTR). When the CPU writes the data to the MMDTR, the MMTXBE flag will be cleared. MMTXBE is set when MMDTR is emptied by a transfer of its data to the output circuit. Reset sets this bit. 1 = Data transmit register empty 0 = Data transmit register full MMRXBF — Multi-Master Receive Buffer Full This flag indicates the status of the data receive register (MMDRR). When the CPU reads the data from the MMDRR, the MMRXBF flag will be cleared. MMRXBF is set when MMDRR is full by a transfer of data from the input circuit to the MMDRR. Reset clears this bit. 1 = Data receive register full 0 = Data receive register empty 8.8.5 Multi-Master IIC Data Transmit Register (MMDTR) Address:$0044 Bit 7 6 5 4 3 2 1 Bit 0 Read: MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0 Write: Reset: 1 1 1 1 1 1 1 1 Figure 8-8. Multi-Master IIC Data Transmit Register (MMDTR) When the MMIIC module is enabled, MMEN = 1, data written into this register depends on whether module is in master or slave mode. In slave mode, the data in MMDTR will be transferred to the output circuit when: (cid:127) the module detects a matched calling address (MMATCH = 1), with the calling master requesting data (MMSRW = 1); or (cid:127) the previous data in the output circuit has be transmitted and the receiving master returns an acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0). If the calling master does not return an acknowledge bit (MMRXAK = 1), the module will release the SDA line for master to generate a "stop" or "repeated start" condition. The data in the MMDTR will not be MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 119

Multi-Master IIC Interface (MMIIC) transferred to the output circuit until the next calling from a master. The transmit buffer empty flag remains cleared (MMTXBE = 0). In master mode, the data in MMDTR will be transferred to the output circuit when: (cid:127) the module receives an acknowledge bit (MMRXAK = 0), after setting master transmit mode (MMRW = 0), and the calling address has been transmitted; or (cid:127) the previous data in the output circuit has be transmitted and the receiving slave returns an acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0). If the slave does not return an acknowledge bit (MMRXAK = 1), the master will generate a "stop" or "repeated start" condition. The data in the MMDTR will not be transferred to the output circuit. The transmit buffer empty flag remains cleared (MMTXBE = 0). The sequence of events for slave transmit and master transmit are illustrated in Figure 8-10. 8.8.6 Multi-Master IIC Data Receive Register (MMDRR) Address:$0045 Bit 7 6 5 4 3 2 1 Bit 0 Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0 Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 8-9. Multi-Master IIC Data Receive Register (MMDRR) When the MMIIC module is enabled, MMEN = 1, data in this read-only register depends on whether module is in master or slave mode. In slave mode, the data in MMDRR is: (cid:127) the calling address from the master when the address match flag is set (MMATCH = 1); or (cid:127) the last data received when MMATCH = 0. In master mode, the data in the MMDRR is: (cid:127) the last data received. When the MMDRR is read by the CPU, the receive buffer full flag is cleared (MMRXBF = 0), and the next received data is loaded to the MMDRR. Each time when new data is loaded to the MMDRR, the MMRXIF interrupt flag is set, indicating that new data is available in MMDRR. The sequence of events for slave receive and master receive are illustrated in Figure 8-10. 8.9 Programming Considerations When the MMIIC module detects an arbitration loss in master mode, it will release both SDA and SCL lines immediately. But if there are no further STOP conditions detected, the module will hang up. Therefore, it is recommended to have time-out software to recover from such ill condition. The software can start the time-out counter by looking at the MMBB (Bus Busy) flag in the MIMCR and reset the counter on the completion of one byte transmission. If a time-out occur, software can clear the MMEN bit (disable MMIIC module) to release the bus, and hence clearing the MMBB flag. This is the only way to clear the MMBB flag by software if the module hangs up due to a no STOP condition received. The MMIIC can resume operation again by setting the MMEN bit. MC68HC908JL16 Data Sheet, Rev. 1.1 120 Freescale Semiconductor

Programming Considerations (a) Master Transmit Mode START Address 0 ACK TX Data1 ACK TX DataN ACK STOP MMTXBE=0 MMTXBE=1 MMTXBE=1 MMTXBE=1 MMNAKIF=1 MMRW=0 MMTXIF=1 MMTXIF=1 MMTXIF=1 MMAST=0 MMAST=1 Data2 → MMDTR Data3 → MMDTR DataN+2 → MMDTR MMTXBE=0 Data1 → MMDTR (b) Master Receive Mode START Address 1 ACK RX Data1 ACK RX DataN NAK STOP MMRXBF=0 Data1 → MMDRR DataN → MMDRR MMNAKIF=1 MMRW=1 MMRXIF=1 MMRXIF=1 MMAST=0 MMAST=1 MMRXBF=1 MMRXBF=1 MMTXBE=0 (dummy data → MMDTR) (c) Slave Transmit Mode START Address 1 ACK TX Data1 ACK TX DataN NAK STOP MMTXBE=1 MMRXIF=1 MMTXBE=1 MMTXBE=1 MMNAKIF=1 MMRXBF=0 MMRXBF=1 MMTXIF=1 MMTXIF=1 MMTXBE=0 MMATCH=1 Data2 → MMDTR DataN+2 → MMDTR MMSRW=1 Data1 → MMDTR (d) Slave Receive Mode START Address 0 ACK RX Data1 ACK RX DataN ACK STOP MMTXBE=0 MMRXIF=1 Data1 → MMDRR DataN → MMDRR MMRXBF=0 MMRXBF=1 MMRXIF=1 MMRXIF=1 MMATCH=1 MMRXBF=1 MMRXBF=1 MMSRW=0 Shaded data packets indicate transmissions by the MCU Figure 8-10. Data Transfer Sequences for Master/Slave Transmit/Receive Modes MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 121

Multi-Master IIC Interface (MMIIC) MC68HC908JL16 Data Sheet, Rev. 1.1 122 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (ADC) 9.1 Introduction This section describes the 10-bit successive approximation analog-to-digital converter (ADC10). The ADC10 on this MCU uses V and V as its supply and reference pins. This MCU uses OSCOUT DD SS as its alternate clock source for the ADC. This MCU does not have a hardware conversion trigger. 9.2 Features Features of the ADC10 module include: (cid:127) Linear successive approximation algorithm with 10-bit resolution (cid:127) Output formatted in 10- or 8-bit right-justified format (cid:127) Single or continuous conversion (automatic power-down in single conversion mode) (cid:127) Configurable sample time and conversion speed (to save power) (cid:127) Conversion complete flag and interrupt (cid:127) Input clock selectable from up to three sources (cid:127) Operation in wait and stop modes for lower noise operation (cid:127) Selectable asynchronous hardware conversion trigger Figure 9-1 provides a summary of the input/output (I/O) registers. Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: COCO ADC Status and Control Reg- AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 $003C ister Write: (ADCSC) Reset: 0 0 0 1 1 1 1 1 Read: 0 0 0 0 0 0 0/AD9 0/AD8 ADC10 Data Register High $003D 8/10-Bit Mode Write: Reserved (ADRH) Reset: 0 0 0 0 0 0 0 0 Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADC10 Data Register $003E Low Write: Reserved (ADRL) Reset: 0 0 0 0 0 0 0 0 Read: $003F ADC10 Clock Register ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ACLKEN Write: (ADCLK) Reset: 0 0 0 0 0 0 0 0 Figure 9-1. ADC I/O Register Summary MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 123

Analog-to-Digital Converter (ADC) 9.3 Functional Description The ADC10 uses successive approximation to convert the input sample taken from ADVIN to a digital representation. The approximation is taken and then rounded to the nearest 10- or 8-bit value to provide greater accuracy and to provide a more robust mechanism for achieving the ideal code-transition voltage. Figure 9-2 shows a block diagram of the ADC10. ADCSC ADCLK N O O E P C V K CH AIE COC ADC PLETE MOD ADLSM ADLP ADI ADICL ACLKEN ACSLOYNCCK D 1 2 M GENERATOR A O C ACLK MCU STOP ADCK CLOCK BUS CLOCK CONTROL SEQUENCER ADHWT DIVIDE ALTERNATE CLOCK SOURCE E E T R T Z L R E R ALI MP VE SF BO AD0 NITI SA CON RAN A I T AIEN 1 INTERRUPT (cid:127) (cid:127) (cid:127) ADVIN SAR CONVERTER COCO 2 ADn V REFH DATA REGISTERS ADRH:ADRL V REFL Figure 9-2. ADC10 Block Diagram For proper conversion, the voltage on ADVIN must fall between V and V . If ADVIN is equal to REFH REFL or exceeds V , the converter circuit converts the signal to $3FF for a 10-bit representation or $FF for REFH a 8-bit representation. If ADVIN is equal to or less than V ,the converter circuit converts it to $000. REFL Input voltages between V and V are straight-line linear conversions. REFH REFL NOTE Input voltage must not exceed the analog supply voltages. The ADC10 can perform an analog-to-digital conversion on one of the software selectable channels. The output of the input multiplexer (ADVIN) is converted by a successive approximation algorithm into a 10-bit digital result. When the conversion is completed, the result is placed in the data registers (ADRH and ADRL). In 8-bit mode, the result is rounded to 8 bits and placed in ADRL. The conversion complete flag is then set and an interrupt is generated if the interrupt has been enabled. MC68HC908JL16 Data Sheet, Rev. 1.1 124 Freescale Semiconductor

Functional Description 9.3.1 Clock Select and Divide Circuit The clock select and divide circuit selects one of three clock sources and divides it by a configurable value to generate the input clock to the converter (ADCK). The clock can be selected from one of the following sources: (cid:127) The asynchronous clock source (ACLK) — This clock source is generated from a dedicated clock source which is enabled when the ADC10 is converting and the clock source is selected by setting the ACLKEN bit. When the ADLPC bit is clear, this clock operates from 1–2 MHz; when ADLPC is set it operates at 0.5–1 MHz. This clock is not disabled in STOP and allows conversions in stop mode for lower noise operation. (cid:127) Alternate Clock Source — This clock source is equal to the external oscillator clock or a four times the bus clock. The alternate clock source is MCU specific, see Table 9-1 to determine source and availability of this clock source option. This clock is selected when ADICLK and ACLKEN are both low. (cid:127) The bus clock — This clock source is equal to the bus frequency. This clock is selected when ADICLK is high and ACLKEN is low. Whichever clock is selected, its frequency must fall within the acceptable frequency range for ADCK. If the available clocks are too slow, the ADC10 will not perform according to specifications. If the available clocks are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV[1:0] bits and can be divide-by 1, 2, 4, or 8. 9.3.2 Input Select and Pin Control Only one analog input may be used for conversion at any given time. The channel select bits in ADCSC are used to select the input signal for conversion. 9.3.3 Conversion Control Conversions can be performed in either 10-bit mode or 8-bit mode as determined by the MODE bits. Conversions can be initiated by either a software or hardware trigger. In addition, the ADC10 module can be configured for low power operation, long sample time, and continuous conversion. 9.3.3.1 Initiating Conversions A conversion is initiated: (cid:127) Following a write to ADCSC (with ADCH bits not all 1s) if software triggered operation is selected. (cid:127) Following a hardware trigger event if hardware triggered operation is selected. (cid:127) Following the transfer of the result to the data registers when continuous conversion is enabled. If continuous conversions are enabled a new conversion is automatically initiated after the completion of the current conversion. In software triggered operation, continuous conversions begin after ADCSC is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. 9.3.3.2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers, ADRH and ADRL. This is indicated by the setting of the COCO bit. An interrupt is generated if AIEN is high at the time that COCO is set. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 125

Analog-to-Digital Converter (ADC) A blocking mechanism prevents a new result from overwriting previous data in ADRH and ADRL if the previous data is in the process of being read while in 10-bit mode (ADRH has been read but ADRL has not). In this case the data transfer is blocked, COCO is not set, and the new result is lost. When a data transfer is blocked, another conversion is initiated regardless of the state of ADCO (single or continuous conversions enabled). If single conversions are enabled, this could result in several discarded conversions and excess power consumption. To avoid this issue, the data registers must not be read after initiating a single conversion until the conversion completes. 9.3.3.3 Aborting Conversions Any conversion in progress will be aborted when: (cid:127) A write to ADCSC occurs (the current conversion will be aborted and a new conversion will be initiated, if ADCH are not all 1s). (cid:127) A write to ADCLK occurs. (cid:127) The MCU is reset. (cid:127) The MCU enters stop mode with ACLK not enabled. When a conversion is aborted, the contents of the data registers, ADRH and ADRL, are not altered but continue to be the values transferred after the completion of the last successful conversion. In the case that the conversion was aborted by a reset, ADRH and ADRL return to their reset states. Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive state. In this state, all internal clocks and references are disabled. This state is entered asynchronously and immediately upon aborting of a conversion. 9.3.3.4 Total Conversion Time The total conversion time depends on many factors such as sample time, bus frequency, whether ACLKEN is set, and synchronization time. The total conversion time is summarized in Table 9-1. Table 9-1. Total Conversion Time versus Control Conditions Conversion Mode ACLKEN Maximum Conversion Time 8-Bit Mode (short sample — ADLSMP = 0): Single or 1st continuous 0 18 ADCK + 3 bus clock Single or 1st continuous 1 18 ADCK + 3 bus clock + 5 µs Subsequent continuous (fBus ≥ fADCK) X 16 ADCK 8-Bit Mode (long sample — ADLSMP = 1): Single or 1st continuous 0 38 ADCK + 3 bus clock Single or 1st continuous 1 38 ADCK + 3 bus clock + 5 µs Subsequent continuous (fBus ≥ fADCK) X 36 ADCK 10-Bit Mode (short sample — ADLSMP = 0): Single or 1st continuous 0 21 ADCK + 3 bus clock Single or 1st continuous 1 21 ADCK + 3 bus clock + 5 µs Subsequent continuous (fBus ≥ fADCK) X 19 ADCK 10-Bit Mode (long sample — ADLSMP = 1): Single or 1st continuous 0 41 ADCK + 3 bus clock Single or 1st continuous 1 41 ADCK + 3 bus clock + 5 µs Subsequent continuous (fBus ≥ fADCK) X 39 ADCK MC68HC908JL16 Data Sheet, Rev. 1.1 126 Freescale Semiconductor

Functional Description The maximum total conversion time for a single conversion or the first conversion in continuous conversion mode is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by the ADICLK and ACLKEN bits, and the divide ratio is specified by the ADIV bits. For example, if the alternate clock source is 16 MHz and is selected as the input clock source, the input clock divide-by-8 ratio is selected and the bus frequency is 4 MHz, then the conversion time for a single 10-bit conversion is: 21 ADCK cycles 3 bus cycles Maximum Conversion time = + = 11.25 µs 16 MHz/8 4 MHz Number of bus cycles = 11.25 µs x 4 MHz = 45 cycles NOTE The ADCK frequency must be between f minimum and f ADCK ADCK maximum to meet A/D specifications. 9.3.4 Sources of Error Several sources of error exist for ADC conversions. These are discussed in the following sections. 9.3.4.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 15 kΩand input capacitance of approximately 10 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles / 2 MHz maximum ADCK frequency) provided the resistance of the external analog source (R ) is kept below 10 AS kΩ. Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time. 9.3.4.2 Pin Leakage Error Leakage on the I/O pins can cause conversion error if the external analog source resistance (R ) is high. AS If this error cannot be tolerated by the application, keep R lower than V / (4096*I ) for less than AS ADVIN Leak 1/4LSB leakage error (at 10-bit resolution). 9.3.4.3 Noise-Induced Errors System noise which occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC10 accuracy numbers are guaranteed as specified only if the following conditions are met: (cid:127) There is a 0.1µF low-ESR capacitor from V to V (if available). REFH REFL (cid:127) There is a 0.1µF low-ESR capacitor from V to V (if available). DDA SSA (cid:127) If inductive isolation is used from the primary supply, an additional 1µF capacitor is placed from V to V (if available). DDA SSA (cid:127) V and V (if available) is connected to V at a quiet point in the ground plane. SSA REFL SS (cid:127) The MCU is placed in wait mode immediately after initiating the conversion (next instruction after write to ADCSC). (cid:127) There is no I/O switching, input or output, on the MCU during the conversion. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 127

Analog-to-Digital Converter (ADC) There are some situations where external system activity causes radiated or conducted noise emissions or excessive V noise is coupled into the ADC10. In these cases, or when the MCU cannot be placed DD in wait or I/O activity cannot be halted, the following recommendations may reduce the effect of noise on the accuracy: (cid:127) Place a 0.01 µF capacitor on the selected input channel to V or V (if available). This will REFL SSA improve noise issues but will affect sample rate based on the external analog source resistance. (cid:127) Operate the ADC10 in stop mode by setting ACLKEN, selecting the channel in ADCSC, and executing a STOP instruction. This will reduce V noise but will increase effective conversion time DD due to stop recovery. (cid:127) Average the input by converting the output many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. (cid:127) Reduce the effect of synchronous noise by operating off the asynchronous clock (ACLKEN=1) and averaging. Noise that is synchronous to the ADCK cannot be averaged out. 9.3.4.4 Code Width and Quantization Error The ADC10 quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the transition points from one code to the next. The ideal code width for an N bit converter (in this case N can be 8 or 10), defined as 1LSB, is: 1LSB = (VREFH–VREFL) / 2N Because of this quantization, there is an inherent quantization error. Because the converter performs a conversion and then rounds to 8 or 10 bits, the code will transition when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. Therefore, the quantization error will be ± 1/2LSB in 8- or 10-bit mode. As a consequence, however, the code width of the first ($000) conversion is only 1/2LSB and the code width of the last ($FF or $3FF) is 1.5LSB. 9.3.4.5 Linearity Errors The ADC10 may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors but the user should be aware of them because they affect overall accuracy. These errors are: (cid:127) Zero-Scale Error (E ) (sometimes called offset) — This error is defined as the difference between ZS the actual code width of the first conversion and the ideal code width (1/2LSB). Note, if the first conversion is $001, then the difference between the actual $001 code width and its ideal (1LSB) is used. (cid:127) Full-Scale Error (E ) — This error is defined as the difference between the actual code width of FS the last conversion and the ideal code width (1.5LSB). Note, if the last conversion is $3FE, then the difference between the actual $3FE code width and its ideal (1LSB) is used. (cid:127) Differential Non-Linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. (cid:127) Integral Non-Linearity (INL) — This error is defined as the highest-value the (absolute value of the) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. (cid:127) Total Unadjusted Error (TUE) — This error is defined as the difference between the actual transfer function and the ideal straight-line transfer function, and therefore includes all forms of error. MC68HC908JL16 Data Sheet, Rev. 1.1 128 Freescale Semiconductor

Interrupts 9.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. (cid:127) Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around ±1/2 LSB but will increase with noise. (cid:127) Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. (cid:127) Missing codes are those which are never converted for any input value. In 8-bit or 10-bit mode, the ADC10 is guaranteed to be monotonic and to have no missing codes. 9.4 Interrupts When AIEN is set, the ADC10 is capable of generating a CPU interrupt after each conversion. A CPU interrupt is generated when the conversion completes (indicated by COCO being set). COCO will set at the end of a conversion regardless of the state of AIEN. 9.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 9.5.1 Wait Mode The ADC10 will continue the conversion process and will generate an interrupt following a conversion if AIEN is set. If the ADC10 is not required to bring the MCU out of wait mode, ensure that the ADC10 is not in continuous conversion mode by clearing ADCO in the ADC10 status and Control Register before executing the WAIT instruction. In single conversion mode the ADC10 automatically enters a low-power state when the conversion is complete. It is not necessary to set the channel select bits (ADCH[4:0]) to all 1s to enter a low power state. 9.5.2 Stop Mode If ACLKEN is clear, executing a STOP instruction will abort the current conversion and place the ADC10 in a low-power state. Upon return from stop mode, a write to ADCSC is required to resume conversions, and the result stored in ADRH and ADRL will represent the last completed conversion until the new conversion completes. If ACLKEN is set, the ADC10 continues normal operation during stop mode. The ADC10 will continue the conversion process and will generate an interrupt following a conversion if AIEN is set. If the ADC10 is not required to bring the MCU out of stop mode, ensure that the ADC10 is not in continuous conversion mode by clearing ADCO in the ADC10 status and Control Register before executing the STOP instruction. In single conversion mode the ADC10 automatically enters a low-power state when the conversion is complete. It is not necessary to set the channel select bits (ADCH[4:0]) to all 1s to enter a low-power state. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 129

Analog-to-Digital Converter (ADC) If ACLKEN is set, a conversion can be initiated while in stop using the external hardware trigger ADEXTCO when in external convert mode. The ADC10 will operate in a low-power mode until the trigger is asserted, at which point it will perform a conversion and assert the interrupt when complete (if AIEN is set). 9.6 ADC10 During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. BCFE in the break flag control register (BFCR) enables software to clear status bits during the break state. See BFCR in the SIM section of this data sheet. To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 9.7 Input/Output Signals The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. The ADC10 on this MCU uses V and V as its supply and reference pins. This MCU does not have an external trigger DD SS source. 9.7.1 ADC10 Analog Power Pin (V ) DDA The ADC10 analog portion uses V as its power pin. In some packages, V is connected internally DDA DDA to V . If externally available, connect the V pin to the same voltage potential as V . External filtering DD DDA DD may be necessary to ensure clean V for good results. DDA NOTE If externally available, route V carefully for maximum noise immunity DDA and place bypass capacitors as near as possible to the package. 9.7.2 ADC10 Analog Ground Pin (V ) SSA The ADC10 analog portion uses V as its ground pin. In some packages, V is connected internally SSA SSA to V . If externally available, connect the V pin to the same voltage potential as V . SS SSA SS In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies should be at the V pin. This should be the only ground connection between SSA these supplies if possible. The V pin makes a good single point ground location. SSA 9.7.3 ADC10 Voltage Reference High Pin (V ) REFH V is the power supply for setting the high-reference voltage for the converter. In some packages, REFH V is connected internally to V . If externally available, V may be connected to the same REFH DDA REFH potential as V , or may be driven by an external source that is between the minimum V spec and DDA DDA the V potential (V must never exceed V ). DDA REFH DDA MC68HC908JL16 Data Sheet, Rev. 1.1 130 Freescale Semiconductor

Registers NOTE Route V carefully for maximum noise immunity and place bypass REFH capacitors as near as possible to the package. AC current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the V and V loop. The best external component REFH REFL to meet this current demand is a 0.1 µF capacitor with good high frequency characteristics. This capacitor is connected between V and V and must be placed as close as possible to the package pins. REFH REFL Resistance in the path is not recommended because the current will cause a voltage drop which could result in conversion errors. Inductance in this path must be minimum (parasitic only). 9.7.4 ADC10 Voltage Reference Low Pin (V ) REFL V is the power supply for setting the low-reference voltage for the converter. In some packages, REFL V is connected internally to V . If externally available, connect the V pin to the same voltage REFL SSA REFL potential as V . There will be a brief current associated with V when the sampling capacitor is SSA REFL charging. If externally available, connect the V pin to the same potential as V at the single point REFL SSA ground location. 9.7.5 ADC10 Channel Pins (ADn) The ADC10 has multiple input channels. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. 0.01 µF capacitors with good high-frequency characteristics are sufficient. These capacitors are not necessary in all cases, but when used they must be placed as close as possible to the package pins and be referenced to V . SSA 9.8 Registers These registers control and monitor operation of the ADC10: (cid:127) ADC10 status and control register, ADCSC (cid:127) ADC10 data registers, ADRH and ADRL (cid:127) ADC10 clock register, ADCLK 9.8.1 ADC10 Status and Control Register This section describes the function of the ADC10 status and control register (ADCSC). Writing ADCSC aborts the current conversion and initiates a new conversion (if the ADCH[4:0] bits are equal to a value other than all 1s). Address: $003C Bit 7 6 5 4 3 2 1 Bit 0 Read: COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Write: Reset: 0 0 0 1 1 1 1 1 = Unimplemented Figure 9-3. ADC10 Status and Control Register (ADCSC) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 131

Analog-to-Digital Converter (ADC) COCO — Conversion Complete Bit The COCO bit is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the status and control register is written or whenever the data register (low) is read. 1 = Conversion completed 0 = Conversion not completed AIEN — ADC10 Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of a conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC10 interrupt enabled 0 = ADC10 interrupt disabled ADCO — ADC10 Continuous Conversion Bit When written high, the ADC10 will begin to convert samples continuously (continuous conversion mode) and update the result registers at the end of each conversion, provided the ADCH[4:0] bits do not decode to all 1s. The ADC10 will continue to convert until the MCU enters reset, the MCU enters stop mode (if ACLKEN is clear), the ADCLK register is written, or until the ADCSC is written again. If Stop is entered (with ACLKEN low), continuous conversions will cease and can only be restarted with a write to the ADCSC. Any write to the ADCSC with the ADCO bit set and the ADCH bits not all 1s will abort the current conversion and begin continuous conversions. If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in short-sample mode (ADLSMP = 0). If the bus frequency is less than 1/11th of the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in long-sample mode (ADLSMP = 1). When clear, the ADC10 will perform a single conversion (single conversion mode) each time the ADCSC is written (assuming the ADCH[4:0] bits do not decode all 1s). Reset clears the ADCO bit. 1 = Continuous conversion following a write to the ADCSC 0 = One conversion following a write to the ADCSC ADCH[4:0] — Channel Select Bits ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field which is used to select one of the input channels. The input channels are detailed in Table 9-2. The successive approximation converter subsystem is turned off when the channel select bits are all set to 1. This feature allows for explicit disabling of the ADC10 and isolation of the input channel from the I/O pad. Terminating continuous convert mode this way will prevent an additional, single conversion from being performed. It is not necessary to set the channel select bits to all 1s to place the ADC10 in a low-power state, however, because the module is automatically placed in a low-power state when a conversion completes. MC68HC908JL16 Data Sheet, Rev. 1.1 132 Freescale Semiconductor

Registers Table 9-2. Input C hannel Select(1) ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select(2) 0 0 0 0 0 AD0 0 0 0 0 1 AD1 0 0 0 1 0 AD2 0 0 0 1 1 AD3 0 0 1 0 0 AD4 0 0 1 0 1 AD5 0 0 1 1 0 AD6 0 0 1 1 1 AD7 0 1 0 0 0 AD8 0 1 0 0 1 AD9 0 1 0 1 0 AD10 0 1 0 1 1 AD11 0 1 1 0 0 AD12 0 1 1 0 1 Unused Continuing to: Unused 1 1 0 0 1 Unused 1 1 0 1 0 BANDGAP REF(3) 1 1 0 1 1 Reserved 1 1 1 0 0 Reserved 1 1 1 0 1 VREFH 1 1 1 1 0 VREFL 1 1 1 1 1 Low-power state 1. Accuracy is guaranteed for conversions on the selected channel only if V falls in the DDA specified range. 2. If any unused or reserved channels are selected, the resulting conversion will be unknown. 3. Requires LVI to be powered (LVID = 0 in CONFIG1). MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 133

Analog-to-Digital Converter (ADC) 9.8.2 ADC10 Result High Register (ADRH) This register holds the MSB’s of the result and is updated each time a conversion completes. All other bits read as 0s. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the results registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the intermediate conversion results will be lost. In 8-bit mode, this register contains no interlocking with ADRL. Address: $003D Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R =Reserved Figure 9-4. ADC10 Data Register High (ADRH), 8-Bit Mode Address: $003D Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 AD9 AD8 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R =Reserved Figure 9-5. ADC10 Data Register High (ADRH), 10-Bit Mode 9.8.3 ADC10 Result Low Register (ADRL) This register holds the LSB’s of the result. This register is updated each time a conversion completes. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the results registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the intermediate conversion results will be lost. In 8-bit mode, there is no interlocking with ADRH. Address: $003E Bit 7 6 5 4 3 2 1 Bit 0 Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R =Reserved Figure 9-6. ADC10 Data Register Low (ADRL) MC68HC908JL16 Data Sheet, Rev. 1.1 134 Freescale Semiconductor

Registers 9.8.4 ADC10 Clock Register (ADCLK) This register selects the clock frequency for the ADC10 and the modes of operation. Address: $003F Bit 7 6 5 4 3 2 1 Bit 0 Read: ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ACLKEN Write: Reset: 0 0 0 0 0 0 0 0 Figure 9-7. ADC10 Clock Register (ADCLK) ADLPC — ADC10 Low-Power Configuration Bit ADLPC controls the speed and power configuration of the successive approximation converter. This is used to optimize power consumption when higher sample rates are not required. 1 = Low-power configuration: The power is reduced at the expense of maximum clock speed. 0 = High-speed configuration ADIV[1:0] — ADC10 Clock Divider Bits ADIV1 and ADIV0 select the divide ratio used by the ADC10 to generate the internal clock ADCK. Table 9-3 shows the available clock configurations. Table 9-3. ADC10 Clock Divide Ratio ADIV1 ADIV0 Divide Ratio (ADIV) Clock Rate 0 0 1 Input clock ÷ 1 0 1 2 Input clock ÷ 2 1 0 4 Input clock ÷ 4 1 1 8 Input clock ÷ 8 ADICLK — Input Clock Select Bit If ACLKEN is clear, ADICLK selects either the bus clock or an alternate clock source as the input clock source to generate the internal clock ADCK. If the alternate clock source is less than the minimum clock speed, use the internally-generated bus clock as the clock source. As long as the internal clock ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency (f ) between ADCK the minimum and maximum clock speeds (considering ALPC), correct operation can be guaranteed. 1 = The internal bus clock is selected as the input clock source 0 = The alternate clock source IS SELECTED MODE[1:0] — 10- or 8-Bit or External-Triggered Mode Selection This bit selects between 10- or 8-bit operation. The successive approximation converter generates a result which is rounded to 8- or 10-bit value based on the mode selection. This rounding process sets the transfer function to transition at the midpoint between the ideal code voltages, causing a quantization error of 1/2LSB. Reset returns 8-bit mode. Table 9-4. Mode Selection MODE1 MODE0 Mode 0 0 8-bit, right-justified, ADCSC write-triggered mode enabled 0 1 10-bit, right-justified, ADCSC write-triggered mode enabled 1 0 Reserved. 1 1 10-bit, right-justified, external triggered mode enabled MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 135

Analog-to-Digital Converter (ADC) ADLSMP — Long Sample Time Configuration This bit configures the sample time of the ADC10 to either 3.5 or 23.5 ADCK clock cycles. This adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption in continuous conversion mode if high conversion rates are not required. 1 = Long sample time (23.5 cycles) 0 = Short sample time (3.5 cycles) ACLKEN — Asynchronous Clock Source Enable This bit enables the asynchronous clock source as the input clock to generate the internal clock ADCK, and allows operation in stop mode. The asynchronous clock source will operate between 1 MHz and 2 MHz if the ADLPC bit is clear, and between 0.5 MHz and 1 MHz if the ADLPC bit is set. As long as the internal clock ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency (f ) between the minimum and maximum required clock frequencies (considering ALPC), correct ADCK operation is guaranteed. 1 = The asynchronous clock is selected as the input clock source (the clock generator is only enabled during the conversion) 0 = The ADICLK bit specifies the input clock source and conversions will not continue in stop mode MC68HC908JL16 Data Sheet, Rev. 1.1 136 Freescale Semiconductor

Chapter 10 Input/Output (I/O) Ports 10.1 Introduction Twenty six (26) bidirectional input-output (I/O) pins form four parallel ports. All I/O pins are programmable as inputs or outputs. NOTE Connect any unused I/O pins to an appropriate logic level, either V or DD V . Although the I/O ports do not require termination for proper operation, SS termination reduces excess current consumption and the possibility of electrostatic damage. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 137

Input/Output (I/O) Ports Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: Port A Data Register PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 $0000 Write: (PTA) Reset: Unaffected by reset Read: Port B Data Register PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 $0001 Write: (PTB) Reset: Unaffected by reset Read: Port D Data Register PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 $0003 Write: (PTD) Reset: Unaffected by reset Read: Data Direction Register A DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 $0004 Write: (DDRA) Reset: 0 0 0 0 0 0 0 0 Read: Data Direction Register B DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 $0005 Write: (DDRB) Reset: 0 0 0 0 0 0 0 0 Read: Data Direction Register D DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 $0007 Write: (DDRD) Reset: 0 0 0 0 0 0 0 0 Read: Port E Data Register PTE1 PTE0 $0008 Write: (PTE) Reset: Unaffected by reset Read: 0 0 0 0 Port D Control Register SLOWD7 SLOWD6 PTDPU7 PTDPU6 $000A Write: (PDCR) Reset: 0 0 0 0 0 0 0 0 Read: Data Direction Register E DDRE1 DDRE0 $000C Write: (DDRE) Reset: 0 0 0 0 0 0 0 0 Read: Port A Input Pull-up Enable PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 $000D Write: Register (PTAPUE) Reset: 0 0 0 0 0 0 0 0 Read: PTA7 Input Pull-up Enable PTAPUE7 $000E Write: Register (PTA7PUE) Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-1. I/O Port Register Summary MC68HC908JL16 Data Sheet, Rev. 1.1 138 Freescale Semiconductor

Introduction Table 10-1. Port Control Register Bits Summary Module Control Port Bit DDR Pin Module Register Control Bit 0 DDRA0 KBI KBIER ($001B) KBIE0 PTA0/KBI0 1 DDRA1 KBI KBIER ($001B) KBIE1 PTA1/KBI1 KBI KBIER ($001B) KBIE2 PTA2/KBI2 2 DDRA2 MMIIC MMCR MMEN PTA2/KBI2/SDA(1)(2) KBI KBIER ($001B) KBIE3 PTA3/KBI3 3 DDRA3 A MMIIC MMCR MMEN PTA3/KBI3/SCL(1)(2) 4 DDRA4 KBI KBIER ($001B) KBIE4 PTA4/KBI4 5 DDRA5 KBI KBIER ($001B) KBIE5 PTA5/KBI5 OSC PTAPUE ($000D) PTA6EN 6 DDRA6 RCCLK/PTA6/KBI6(3) KBI KBIER ($001B) KBIE6 7 DDRA7 KBI KBIER ($001B) KBIE7 PTA7/KBI7 0 DDRB0 ADC ADSCR ($003C) ADCH[4:0] PTB0/ADC0 1 DDRB1 ADC ADSCR ($003C) ADCH[4:0] PTB1/ADC1 2 DDRB2 ADC ADSCR ($003C) ADCH[4:0] PTB2/ADC2 3 DDRB3 ADC ADSCR ($003C) ADCH[4:0] PTB3/ADC3 B 4 DDRB4 ADC ADSCR ($003C) ADCH[4:0] PTB4/ADC4 5 DDRB5 ADC ADSCR ($003C) ADCH[4:0] PTB5/ADC5 6 DDRB6 ADC ADSCR ($003C) ADCH[4:0] PTB6/ADC6 7 DDRB7 ADC ADSCR ($003C) ADCH[4:0] PTB7/ADC7 0 DDRD0 ADC ADSCR ($003C) ADCH[4:0] PTD0/ADC11 1 DDRD1 ADC ADSCR ($003C) ADCH[4:0] PTD1/ADC10 2 DDRD2 ADC ADSCR ($003C) ADCH[4:0] PTD2/ADC9 3 DDRD3 ADC ADSCR ($003C) ADCH[4:0] PTD3/ADC8 4 DDRD4 TIM1 T1SC0 ($0025) ELS/0B:ELS0A PTD4/T1CH0 D 5 DDRD5 TIM1 T1SC1 ($0028) ELS1B:ELS1A PTD5/T1CH1 SCI SCC1 ($0013) ENSCI PTD6/TxD 6 DDRD6 MMIIC MMCR MMEN PTD6/TxD/SCL(1)(4) SCI SCI ENSCI PTD7/RxD 7 DDRD7 MMIIC MMCR MMEN PTD7/RxD/SDA(1)(4) 0 DDRE0 TIM2 T2SC0 ($0035) ELS0B:ELS0A PTE0/T2CH0 E 1 DDRE1 TIM2 T2SC1 ($0038) ELS1B:ELS1A PTE1/T2CH1 1. Position of MMIIC module pins is user selectable using CONFIG2 option bit. 2. If MMIIC module is using the PTA2/PTA3 pairs for IIC (CONFIG2 – IICSEL = 1, MMEN = 1), the MMIIC module will have priority over the KBI module. 3. RCCLK/PTA6/KBI6 pin is only available when OSCSEL=0 (RC option); PTAPUE register has priority control over the port pin. RCCLK/PTA6/KBI6 is the OSC2 pin when OSCSEL=1 (XTAL option). 4. If ESCI module is enabled (ENSCI = 1), the ESCI will have priority over the PTD6/PTD7 pins regardless of the state of the MMIIC module. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 139

Input/Output (I/O) Ports 10.2 Port A Port A is an 8-bit special function port that shares all of its pins with the keyboard interrupt (KBI) module (see Chapter 12 Keyboard Interrupt Module (KBI)) and two of its pins with the MMIIC module (see Chapter 8 Multi-Master IIC Interface (MMIIC)). Each port A pin also has software configurable pull-up device if the corresponding port pin is configured as input port. PTA0–PTA5 and PTA7 has direct LED drive capability. NOTE PTA7 pin is available on 32-pin packages only. 10.2.1 Port A Data Register (PTA) The port A data register (PTA) contains a data latch for each of the eight port A pins. Address: $0000 Bit 7 6 5 4 3 2 1 Bit 0 Read: PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Write: Reset: Unaffected by Reset LED LED LED LED LED LED LED Additional Functions: (Sink) (Sink) (Sink) (Sink) (Sink) (Sink) (Sink) pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Alternative Functions: Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Alternative Functions: SCL SDA = Unimplemented Figure 10-2. Port A Data Register (PTA) PTA[7:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. KBI7–KBI0 — Port A Keyboard Interrupts The keyboard interrupt enable bits, KBIE[7:0], in the keyboard interrupt control register (KBIER) enable the port A pins as external interrupt pins, Chapter 12 Keyboard Interrupt Module (KBI). SCL and SDA — MMIIC Module Pins The MMIIC pins can be configured to use PTA2 and PTA3 as IIC communication pins, see Chapter 8 Multi-Master IIC Interface (MMIIC). The position of MMIIC module pins is user selectable using CONFIG2 option bit, to allow PTA2/PTA3 to be MMIIC pins (see 3.4Configuration Register 2 (CONFIG2)). MC68HC908JL16 Data Sheet, Rev. 1.1 140 Freescale Semiconductor

Port A 10.2.2 Data Direction Register A (DDRA) Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer. NOTE For those devices packaged in a 28-pin package, PTA7 is not connected. DDRA7 should be set to a 1 to configure PTA7 as an output. Address: $0004 Bit 7 6 5 4 3 2 1 Bit 0 Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 10-3. Data Direction Register A (DDRA) DDRA[7:0] — Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 10-4 shows the port A I/O logic. READ DDRA ($0004) PTAPUEx WRITE DDRA ($0004) S DDRAx U RESET B A T A D WRITE PTA ($0000) AL PTAx PTAx N R E T N I READ PTA ($0000) To KBI Figure 10-4. Port A I/O Circuit When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 141

Input/Output (I/O) Ports Table 10-2 summarizes the operation of the port A pins. Table 10-2. Port A Pin Functions Accesses Accesses PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode to DDRA to PTA Read/Write Read Write 1 0 X(1) Input, VDD(2) DDRA[7:0] Pin PTA[7:0](3) 0 0 X Input, Hi-Z(4) DDRA[7:0] Pin PTA[7:0](3) X 1 X Output DDRA[7:0] PTA[7:0] PTA[7:0] 1. X = Don’t care. 2. Pin pulled to V by internal pull-up. DD 3. Writing affects data register, but does not affect input. 4. Hi-Z = High impedance. 10.2.3 Port A Input Pull-Up Enable Registers The port A input pull-up enable registers contain a software configurable pull-up device for each of the eight port A pins. Each bit is individually configurable and requires the corresponding data direction register, DDRAx be configured as input. Each pull-up device is automatically disabled when its corresponding DDRAx bit is configured as output. Address: $000D Bit 7 6 5 4 3 2 1 Bit 0 Read: PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 10-5. Port A Input Pull-up Enable Register (PTAPUE) Address: $000E Bit 7 6 5 4 3 2 1 Bit 0 Read: PTAPUE7 Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-6. PTA7 Input Pull-up Enable Register (PTA7PUE) PTA6EN — Enable PTA6 on OSC2 This read/write bit configures the OSC2 pin function when RC oscillator option is selected. This bit has no effect for XTAL oscillator option. 1 = OSC2 pin configured for PTA6 I/O, and has all the interrupt and pull-up functions 0 = OSC2 pin outputs the RC oscillator clock (RCCLK) PTAPUE[7:0] — Port A Input Pull-up Enable Bits These read/write bits are software programmable to enable pull-up devices on port A pins. 1 = Corresponding port A pin configured to have internal pull-up if its DDRA bit is set to 0 0 = Pull-up device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit MC68HC908JL16 Data Sheet, Rev. 1.1 142 Freescale Semiconductor

Port B 10.3 Port B Port B is an 8-bit special function port that shares all of its port pins with the analog-to-digital converter (ADC) module (see Chapter 9 Analog-to-Digital Converter (ADC)). 10.3.1 Port B Data Register (PTB) The port B data register contains a data latch for each of the eight port B pins. Address: $0001 Bit 7 6 5 4 3 2 1 Bit 0 Read: PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 Write: Reset: Unaffected by reset Alternative Functions: ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC2 ADC0 Figure 10-7. Port B Data Register (PTB) PTB[7:0] — Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. ADC7–ADC0 — ADC channels 7 to 0 ADC7–ADC0 are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an ADC input. See Chapter 9 Analog-to-Digital Converter (ADC). NOTE When a pin is to be used as an ADC channel, the user must make sure that any pin that is shared with another module is disabled and pin is configured as input port. 10.3.2 Data Direction Register B (DDRB) Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. Address: $0005 Bit 7 6 5 4 3 2 1 Bit 0 Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 10-8. Data Direction Register B (DDRB) DDRB[7:0] — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 143

Input/Output (I/O) Ports NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 10-9 shows the port B I/O logic. READ DDRB ($0005) WRITE DDRB ($0005) S DDRBX U RESET B A T A D WRITE PTB ($0001) AL PTBX PTBX N R E T N I READ PTB ($0001) TO ANALOG-TO-DIGITAL CONVERTER Figure 10-9. Port B I/O Circuit When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 10-3 summarizes the operation of the port B pins. Table 10-3. Port B Pin Functions Accesses to DDRB Accesses to PTB DDRB Bit PTB Bit I/O Pin Mode Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRB[7:0] Pin PTB[7:0](3) 1 X Output DDRB[7:0] PTB[7:0] PTB[7:0] 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input. 10.4 Port D Port D is an 8-bit special function port that shares two of its pins with the serial communications interface module (see Chapter 7 Serial Communications Interface (SCI)), two of its pins with the timer 1 interface module (see Chapter 6 Timer Interface Module (TIM)), four of its pins with the analog-to-digital converter module (see Chapter 9 Analog-to-Digital Converter (ADC)), and two of its pins with the MMIIC module (see Chapter 8 Multi-Master IIC Interface (MMIIC)). PTD6 and PTD7 each has high current sink (25mA) and programmable pull-up. PTD2, PTD3, PTD6 and PTD7 each has LED sink capability. MC68HC908JL16 Data Sheet, Rev. 1.1 144 Freescale Semiconductor

Port D 10.4.1 Port D Data Register (PTD) The port D data register contains a data latch for each of the eight port D pins. Address: $0003 Bit 7 6 5 4 3 2 1 Bit 0 Read: PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Write: Reset: Unaffected by reset LED LED LED LED Additional Functions (Sink) (Sink) (Sink) (Sink) 25mA sink 25mA sink (Slow Edge) (Slow Edge) pull-up pull-up Alternative Functions: RxD TxD T1CH1 T1CH0 ADC8 ADC9 ADC10 ADC11 Alternative Functions: SDA SCL = Unimplemented Figure 10-10. Port D Data Register (PTD) PTD[7:0] — Port D Data Bits These read/write bits are software programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D. Reset has no effect on port D data. ADC11–ADC8 — ADC channels 11 to 8 ADC[11:8] are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an ADC input. See Chapter 9 Analog-to-Digital Converter (ADC). NOTE When a pin is to be used as an ADC channel, the user must make sure that any pin that is shared with another module is disabled and pin is configured as input port. T1CH1, T1CH0 — Timer 1 Channel I/Os The T1CH1 and T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTD4/T1CH0 and PTD5/T1CH1 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 6 Timer Interface Module (TIM). TxD, RxD — SCI Data I/O Pins The TxD and RxD pins are the transmit data output and receive data input for the SCI module. The enable SCI bit, ENSCI, in the SCI control register 1 enables the PTD6/TxD and PTD7/RxD pins as SCI TxD and RxD pins and overrides any control from the port I/O logic. See Chapter 7 Serial Communications Interface (SCI). SDA and SCL — MMIIC Module Pins The MMIIC pins can be configured to use PTD6 and PTD7 as IIC communication pins, see Chapter 8 Multi-Master IIC Interface (MMIIC). The position of MMIIC module pins is user selectable using CONFIG2 option bit, to allow PTD6/PTD7 to be MMIIC pins (see Figure 3-3. Configuration Register 2 (CONFIG2)). MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 145

Input/Output (I/O) Ports 10.4.2 Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. Address: $0007 Bit 7 6 5 4 3 2 1 Bit 0 Read: DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 10-11. Data Direction Register D (DDRD) DDRD[7:0] — Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 10-12 shows the port D I/O logic. READ DDRD ($0007) PTDPU[6:7] WRITE DDRD ($0007) S DDRDX U RESET B A T A D WRITE PTD ($0003) AL PTDX PTDX N R E T N I READ PTD ($0003) TO ADC, TIM1, SCI Figure 10-12. Port D I/O Circuit When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. MC68HC908JL16 Data Sheet, Rev. 1.1 146 Freescale Semiconductor

Port E Table 10-4 summarizes the operation of the port D pins. Table 10-4. Port D Pin Functions Accesses to DDRD Accesses to PTD DDRD Bit PTD Bit I/O Pin Mode Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRD[7:0] Pin PTD[7:0](3) 1 X Output DDRD[7:0] PTD[7:0] PTD[7:0] 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input. 10.4.3 Port D Control Register (PDCR) The port D control register enables/disables the pull-up resistor and slow-edge high current capability of pins PTD6 and PTD7. Address: $000A Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 SLOWD7 SLOWD6 PTDPU7 PTDPU6 Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-13. Port D Control Register (PDCR) SLOWDx — Slow Edge Enable The SLOWD6 and SLOWD7 bits enable the slow-edge, open-drain, high current output (25mA sink) of port pins PTD6 and PTD7 respectively. DDRDx bit is not affected by SLOWDx. 1 = Slow edge enabled; pin is open-drain output 0 = Slow edge disabled; pin is push-pull (standard I/O) PTDPUx — Port D Pull-up Enable Bits The PTDPU6 and PTDPU7 bits enable the pull-up device on PTD6 and PTD7 respectively, regardless the status of DDRDx bit. 1 = Enable pull-up device 0 = Disable pull-up device 10.5 Port E Port E is a 2-bit special function port that shares its pins with the timer 2 interface module (see Chapter 6 Timer Interface Module (TIM)). NOTE PTE0–PTE1 are available on 32-pin packages only. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 147

Input/Output (I/O) Ports 10.5.1 Port E Data Register (PTE) The port E data register contains a data latch for each of the two port E pins. Address: $0008 Bit 7 6 5 4 3 2 1 Bit 0 Read: PTE1 PTE0 Write: Reset: Unaffected by reset Alternative Functions: T2CH1 T2CH0 = Unimplemented Figure 10-14. Port E Data Register (PTE) PTE[1:0] — Port E Data Bits These read/write bits are software programmable. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. Reset has no effect on port D data. T2CH1, T2CH0 — Timer 2 Channel I/Os The T2CH1 and T2CH0 pins are the TIM2 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTE0/T2CH0 and PTE1/T2CH1 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 6 Timer Interface Module (TIM). 10.5.2 Data Direction Register E (DDRE) Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer. Address: $000C Bit 7 6 5 4 3 2 1 Bit 0 Read: DDRE1 DDRE0 Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-15. Data Direction Register E (DDRE) DDRE[1:0] — Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE[1:0], configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input NOTE Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 10-16 shows the port E I/O logic. MC68HC908JL16 Data Sheet, Rev. 1.1 148 Freescale Semiconductor

Port E READ DDRE ($000C) WRITE DDRE ($000C) S DDREX U RESET B A T A D WRITE PTE ($0008) AL PTEX PTEX N R E T N I READ PTE ($0008) TO TIM2 Figure 10-16. Port E I/O Circuit When DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 10-5 summarizes the operation of the port E pins. Table 10-5. Port E Pin Functions Accesses to DDRE Accesses to PTE DDRE Bit PTE Bit I/O Pin Mode Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRE[1:0] Pin PTE[1:0](3) 1 X Output DDRE[1:0] PTE[1:0] PTE[1:0] 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 149

Input/Output (I/O) Ports MC68HC908JL16 Data Sheet, Rev. 1.1 150 Freescale Semiconductor

Chapter 11 External Interrupt (IRQ) 11.1 Introduction The external interrupt (IRQ) module provides a maskable interrupt input. 11.2 Features Features of the IRQ module include the following: (cid:127) A dedicated external interrupt pin (IRQ) (cid:127) IRQ interrupt control bits (cid:127) Hysteresis buffer (cid:127) Programmable edge-only or edge and level interrupt sensitivity (cid:127) Automatic interrupt acknowledge (cid:127) Selectable internal pullup resistor 11.3 Functional Description A logic zero applied to the external interrupt pin can latch a CPU interrupt request. Figure 11-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: (cid:127) Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. (cid:127) Software clear — Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (INTSCR). Writing a logic one to the ACK bit clears the IRQ latch. (cid:127) Reset — A reset automatically clears the interrupt latch. The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge or falling-edge and low-level-triggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch, software clear, or reset occurs. When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: (cid:127) Vector fetch or software clear (cid:127) Return of the interrupt pin to logic one MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 151

External Interrupt (IRQ) The vector fetch or software clear may occur before or after the interrupt pin returns to logic one. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear. NOTE The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See 4.5 Exception Control.) RESET ACK TO CPU FOR VECTOR US FETCH BINILS/TBRIHUCTIONS B DECODER S RES VDD D D IRQPUD L A INTERNAL VDD IRQF A PULLUP N ER DEVICE CLR INT D Q SYNCHRONIZER IINRTQERRUPT IRQ CK REQUEST IMASK MODE HIGH TO MODE VOLTAGE SELECT DETECT LOGIC Figure 11-1. IRQ Module Block Diagram Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 IRQF 0 IRQ Status and Control IMASK MODE $001D Register Write: ACK (INTSCR) Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 11-2. IRQ I/O Register Summary MC68HC908JL16 Data Sheet, Rev. 1.1 152 Freescale Semiconductor

IRQ Module During Break Interrupts 11.3.1 IRQ Pin A logic zero on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set, both of the following actions must occur to clear IRQ: (cid:127) Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. (cid:127) Return of the IRQ pin to logic one — As long as the IRQ pin is at logic zero, IRQ remains active. The vector fetch or software clear and the return of the IRQ pin to logic one may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic zero. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ pin. NOTE When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. NOTE An internal pull-up resistor to V is connected to the IRQ pin; this can be DD disabled by setting the IRQPUD bit in the CONFIG2 register ($001E). 11.4 IRQ Module During Break Interrupts The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Chapter 4 System Integration Module (SIM).) To allow software to clear the IRQ latch during a break interrupt, write a logic one to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 153

External Interrupt (IRQ) 11.5 IRQ Status and Control Register (INTSCR) The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR has the following functions: (cid:127) Shows the state of the IRQ flag (cid:127) Clears the IRQ latch (cid:127) Masks IRQ and interrupt request (cid:127) Controls triggering sensitivity of the IRQ interrupt pin Address: $001D Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 IRQF IMASK MODE Write: ACK Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 11-3. IRQ Status and Control Register (INTSCR) IRQF — IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK — IRQ Interrupt Request Acknowledge Bit Writing a logic one to this write-only bit clears the IRQ latch. ACK always reads as logic zero. Reset clears ACK. IMASK — IRQ Interrupt Mask Bit Writing a logic one to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only Address: $001E Bit 7 6 5 4 3 2 1 Bit 0 Read: IRQPUD R R LVIT1 LVIT0 R R R Write: Reset: 0 0 0 U U 0 0 0 POR: 0 0 0 0 0 0 0 0 R =Reserved U = Unaffected Figure 11-4. Configuration Register 2 (CONFIG2) IRQPUD — IRQ Pin Pull-Up Disable Bit IRQPUD disconnects the internal pull-up on the IRQ pin. 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ pin and V DD MC68HC908JL16 Data Sheet, Rev. 1.1 154 Freescale Semiconductor

Chapter 12 Keyboard Interrupt Module (KBI) 12.1 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0–PTA7. When a port pin is enabled for keyboard interrupt function, an internal pull-up device is also enabled on the pin. 12.2 Features Features of the keyboard interrupt module include the following: (cid:127) Eight keyboard interrupt pins with pull-up devices (cid:127) Separate keyboard interrupt enable bits and one keyboard interrupt mask (cid:127) Programmable edge-only or edge- and level- interrupt sensitivity (cid:127) Exit from low-power modes Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 KEYF 0 Keyboard Status and IMASKK MODEK $001A Control Register Write: ACKK (KBSCR) Reset: 0 0 0 0 0 0 0 0 Read: Keyboard Interrupt KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 $001B Enable Register Write: (KBIER) Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 12-1. KBI I/O Register Summary 12.3 I/O Pins The eight keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins are listed in Table 12-1. The generic pin name appear in the text that follows. Table 12-1. Pin Name Conventions Pin Selected for KBI Function KBI Generic Pin Name Full MCU Pin Name by KBIEx Bit in KBIER KBI0–KBI5 PTA0/KBI0–PTA5/KBI5 KBIE0–KBIE5 KBI6 OSC2/RCCLK/PTA6/KBI6(1) KBIE6 KBI7 PTA7/KBI7 KBIE7 1. PTA6/KBI6 is only available when OSCSEL=0 at $FFD0 (RC option), and PTA6EN=1 at $000D. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 155

Keyboard Interrupt Module (KBI) 12.4 Functional Description INTERNAL BUS NOTE: To prevent false interrupts, user should use software to debounce keyboard interrupt inputs. VECTOR FETCH KBI0 DECODER ACKK V DD KEYF RESET . CLR D Q KBIE0 SYNCHRONIZER KEYBOARD . CK INTERRUPT TO PULLUP ENABLE REQUEST . KEYBOARD IMASKK KBI7 INTERRUPT FF MODEK KBIE7 TO PULLUP ENABLE Figure 12-2. Keyboard Interrupt Block Diagram Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also enables its internal pull-up device regardless of PTAPUEx bits in the port A input pull-up enable register (see 10.2.3 Port A Input Pull-Up Enable Registers). A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. (cid:127) If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. (cid:127) If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: (cid:127) Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE0 and $FFE1. (cid:127) Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. MC68HC908JL16 Data Sheet, Rev. 1.1 156 Freescale Semiconductor

Keyboard Interrupt Registers The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, disable the pull-up device, use the data direction register to configure the pin as an input and then read the data register. NOTE Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. 12.4.1 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction register A. 2. Write logic 1’s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 12.5 Keyboard Interrupt Registers Two registers control the operation of the keyboard interrupt module: (cid:127) Keyboard status and control register (cid:127) Keyboard interrupt enable register MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 157

Keyboard Interrupt Module (KBI) 12.5.1 Keyboard Status and Control Register (cid:127) Flags keyboard interrupt requests (cid:127) Acknowledges keyboard interrupt requests (cid:127) Masks keyboard interrupt requests (cid:127) Controls keyboard interrupt triggering sensitivity Address: $001A Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 KEYF 0 IMASKK MODEK Write: ACKK Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 12-3. Keyboard Status and Control Register (KBSCR) KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port A. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request on port A. ACKK always reads as logic 0. Reset clears ACKK. IMASKK— Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port A. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port A. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only 12.5.2 Keyboard Interrupt Enable Register The port-A keyboard interrupt enable register enables or disables each port-A pin to operate as a keyboard interrupt pin. Address: $001B Bit 7 6 5 4 3 2 1 Bit 0 Read: KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 12-4. Keyboard Interrupt Enable Register (KBIER) MC68HC908JL16 Data Sheet, Rev. 1.1 158 Freescale Semiconductor

Low-Power Modes KBIE7–KBIE0 — Port-A Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin on port-A to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin 12.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 12.6.1 Wait Mode The keyboard modules remain active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 12.6.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 12.7 Keyboard Module During Break Interrupts The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 159

Keyboard Interrupt Module (KBI) MC68HC908JL16 Data Sheet, Rev. 1.1 160 Freescale Semiconductor

Chapter 13 Computer Operating Properly (COP) 13.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG1 register. 13.2 Functional Description Figure 13-1 shows the structure of the COP module. SIM ICLK 12-BIT SIM COUNTER SIM RESET CIRCUIT RESET STATUS REGISTER 2 INTERNAL RESET SOURCES(1) CLEAR ALL STAGES CLEAR STAGES 5–1 TIMEOUT P O RESET VECTOR FETCH C COPCTL WRITE COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COPD (FROM CONFIG1) RESET CLEAR COPCTL WRITE COP COUNTER COP RATE SEL (COPRS FROM CONFIG1) Figure 13-1. COP Block Diagram MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 161

Computer Operating Properly (COP) The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218– 24 or 213– 24 ICLK cycles; depending on the state of the COP rate select bit, COPRS, in configuration register 1. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the SIM counter. NOTE Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 × ICLK cycles and sets the COP bit in the reset status register (RSR). (See 4.7.2 Reset Status Register (RSR).). NOTE Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. 13.3 I/O Signals The following paragraphs describe the signals shown in Figure 13-1. 13.3.1 ICLK ICLK is the internal oscillator output signal, typically 50-kHz. The ICLK frequency varies depending on the supply voltage. See Chapter 17 Electrical Specifications for ICLK parameters. 13.3.2 COPCTL Write Writing any value to the COP control register (COPCTL) (see 13.4 COP Control Register) clears the COP counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns the low byte of the reset vector. 13.3.3 Power-On Reset The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 ×ICLK cycles after power-up. 13.3.4 Internal Reset An internal reset clears the SIM counter and the COP counter. 13.3.5 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter. 13.3.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register 1 (CONFIG1). (See Chapter 3 Configuration and Mask Option Registers (CONFIG and MOR).) MC68HC908JL16 Data Sheet, Rev. 1.1 162 Freescale Semiconductor

COP Control Register 13.3.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1. Address: $001F Bit 7 6 5 4 3 2 1 Bit 0 Read: COPRS R R LVID R SSREC STOP COPD Write: Reset: 0 0 0 0 0 0 0 0 R =Reserved Figure 13-2. Configuration Register 1 (CONFIG1) COPRS — COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. 1 = COP timeout period is (213 – 24) ICLK cycles 0 = COP timeout period is (218 – 24) ICLK cycles COPD — COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled 13.4 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Bit 7 6 5 4 3 2 1 Bit 0 Read: Low byte of reset vector Write: Clear COP counter Reset: Unaffected by reset Figure 13-3. COP Control Register (COPCTL) 13.5 Interrupts The COP does not generate CPU interrupt requests. 13.6 Monitor Mode The COP is disabled in monitor mode when V is present on the IRQ pin or on the RST pin. TST 13.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 163

Computer Operating Properly (COP) 13.7.1 Wait Mode The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 13.7.2 Stop Mode Stop mode turns off the ICLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction is disabled, execution of a STOP instruction results in an illegal opcode reset. 13.8 COP Module During Break Mode The COP is disabled during a break interrupt when V is present on the RST pin. TST MC68HC908JL16 Data Sheet, Rev. 1.1 164 Freescale Semiconductor

Chapter 14 Low-Voltage Inhibit (LVI) 14.1 Introduction This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the V pin DD and generates a reset when the V voltage falls to the LVI trip (LVI ) voltage. DD TRIP 14.2 Features Features of the LVI module include the following: (cid:127) Selectable LVI trip voltage (cid:127) Selectable LVI circuit disable 14.3 Functional Description Figure 14-1 shows the structure of the LVI module. The LVI is enabled after a reset. The LVI module contains a bandgap reference circuit and comparator. Setting LVI disable bit (LVID) disables the LVI to monitor V voltage. The LVI trip voltage selection bits (LVIT1, LVIT0) determine at which V level the DD DD LVI module should take actions. The LVI module generates one output signal: LVI Reset — an reset signal will be generated to reset the CPU when V drops to below the set trip DD point. V DD LVID V > LVI = 0 DD TRIP LVI RESET LOW VDD VDD < LVITRIP = 1 DETECTOR LVIT1 LVIT0 Figure 14-1. LVI Module Block Diagram MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 165

Low-Voltage Inhibit (LVI) 14.4 LVI Control Register (CONFIG2/CONFIG1) The LVI module is controlled by three bits in the configuration registers, CONFIG1 and CONFIG2. Address: $001E Bit 7 6 5 4 3 2 1 Bit 0 Read: STOP_ IRQPUD R R LVIT1 LVIT0 R R Write: ICLKDIS Reset: 0 0 0 U U 0 0 0 POR: 0 0 0 0 0 0 0 0 R =Reserved U = Unaffected Figure 14-2. Configuration Register 2 (CONFIG2) Address: $001F Bit 7 6 5 4 3 2 1 Bit 0 Read: COPRS R R LVID R SSREC STOP COPD Write: Reset: 0 0 0 0 0 0 0 0 R =Reserved Figure 14-3. Configuration Register 1 (CONFIG1) LVID — Low Voltage Inhibit Disable Bit LVID disables the LVI module. Reset clears LVID. 1 = Low voltage inhibit disabled 0 = Low voltage inhibit enabled LVIT1, LVIT0 — LVI Trip Voltage Selection Bits These two bits determine at which level of V the LVI module will come into action. LVIT1 and LVIT0 DD are cleared by a power-on reset only. Table 14-1. Trip Voltage Selection LVIT1 LVIT0 Comments(1) 0 0 For VDD = 3 V operation 0 1 For VDD = 3 V operation 1 0 For VDD = 5 V operation 1 1 Reserved 1. See Chapter 17 Electrical Specifications for full parameters. 14.5 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 14.5.1 Wait Mode The LVI module, when enabled, will continue to operate in wait mode. 14.5.2 Stop Mode The LVI module, when enabled, will continue to operate in stop mode. MC68HC908JL16 Data Sheet, Rev. 1.1 166 Freescale Semiconductor

Chapter 15 Central Processor Unit (CPU) 15.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 15.2 Features Features of the CPU include: (cid:127) Object code fully upward-compatible with M68HC05 Family (cid:127) 16-bit stack pointer with stack manipulation instructions (cid:127) 16-bit index register with x-register manipulation instructions (cid:127) 8-MHz CPU internal bus frequency (cid:127) 64-Kbyte program/data memory space (cid:127) 16 addressing modes (cid:127) Memory-to-memory data moves without using accumulator (cid:127) Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions (cid:127) Enhanced binary-coded decimal (BCD) data handling (cid:127) Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes (cid:127) Low-power stop and wait modes 15.3 CPU Registers Figure 15-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 167

Central Processor Unit (CPU) 7 0 ACCUMULATOR (A) 15 0 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 15-1. CPU Registers 15.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Unaffected by reset Figure 15-2. Accumulator (A) 15.3.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location. Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X X = Indeterminate Figure 15-3. Index Register (H:X) MC68HC908JL16 Data Sheet, Rev. 1.1 168 Freescale Semiconductor

CPU Registers 15.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Figure 15-4. Stack Pointer (SP) NOTE The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations. 15.3.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read: Write: Reset: Loaded with vector from $FFFE and $FFFF Figure 15-5. Program Counter (PC) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 169

Central Processor Unit (CPU) 15.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Bit 7 6 5 4 3 2 1 Bit 0 Read: V 1 1 H I N Z C Write: Reset: X 1 1 X 1 X X X X = Indeterminate Figure 15-6. Condition Code Register (CCR) V — Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H — Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result MC68HC908JL16 Data Sheet, Rev. 1.1 170 Freescale Semiconductor

Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 15.4 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU. 15.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 15.5.1 Wait Mode The WAIT instruction: (cid:127) Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. (cid:127) Disables the CPU clock 15.5.2 Stop Mode The STOP instruction: (cid:127) Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. (cid:127) Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. 15.6 CPU During Break Interrupts If a break module is present on the MCU, the CPU starts a break interrupt by: (cid:127) Loading the instruction register with the SWI instruction (cid:127) Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 171

Central Processor Unit (CPU) 15.7 Instruction Set Summary Table 15-1 provides a summary of the M68HC08 instruction set. Table 15-1. Instruction Set Summary (Sheet 1 of 6) SFoourrmce Operation Description oEnf fCeCctR dressde code erand cles V H I N Z C do p p y AM O O C ADC #opr IMM A9 ii 2 ADC opr DIR B9 dd 3 ADC opr EXT C9 hh ll 4 ADC opr,X IX2 D9 ee ff 4 Add with Carry A ← (A) + (M) + (C) (cid:21) (cid:21) – (cid:21) (cid:21) (cid:21) ADC opr,X IX1 E9 ff 3 ADC ,X IX F9 2 ADC opr,SP SP1 9EE9 ff 4 ADC opr,SP SP2 9ED9 ee ff 5 ADD #opr IMM AB ii 2 ADD opr DIR BB dd 3 ADD opr EXT CB hh ll 4 ADD opr,X IX2 DB ee ff 4 Add without Carry A ← (A) + (M) (cid:21) (cid:21) – (cid:21) (cid:21) (cid:21) ADD opr,X IX1 EB ff 3 ADD ,X IX FB 2 ADD opr,SP SP1 9EEB ff 4 ADD opr,SP SP2 9EDB ee ff 5 AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) – – – – – – IMM A7 ii 2 AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) – – – – – – IMM AF ii 2 AND #opr IMM A4 ii 2 AND opr DIR B4 dd 3 AND opr EXT C4 hh ll 4 AND opr,X IX2 D4 ee ff 4 Logical AND A ← (A) & (M) 0 – – (cid:21) (cid:21) – AND opr,X IX1 E4 ff 3 AND ,X IX F4 2 AND opr,SP SP1 9EE4 ff 4 AND opr,SP SP2 9ED4 ee ff 5 ASL opr DIR 38 dd 4 ASLA INH 48 1 ASLX Arithmetic Shift Left INH 58 1 C 0 (cid:21) – – (cid:21) (cid:21) (cid:21) ASL opr,X (Same as LSL) IX1 68 ff 4 ASL ,X b7 b0 IX 78 3 ASL opr,SP SP1 9E68 ff 5 ASR opr DIR 37 dd 4 ASRA INH 47 1 ASRX Arithmetic Shift Right C (cid:21) – – (cid:21) (cid:21) (cid:21) INH 57 1 ASR opr,X IX1 67 ff 4 ASR opr,X b7 b0 IX 77 3 ASR opr,SP SP1 9E67 ff 5 BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3 DIR (b0) 11 dd 4 DIR (b1) 13 dd 4 DIR (b2) 15 dd 4 DIR (b3) 17 dd 4 BCLR n, opr Clear Bit n in M Mn ← 0 – – – – – – DIR (b4) 19 dd 4 DIR (b5) 1B dd 4 DIR (b6) 1D dd 4 DIR (b7) 1F dd 4 BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3 BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 – – – – – – REL 27 rr 3 BGE opr Branch if Greater Than or Equal To PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 – – – – – – REL 90 rr 3 (Signed Operands) BGT opr Branch if Greater Than (Signed PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 – – – – – – REL 92 rr 3 Operands) BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 – – – – – – REL 28 rr 3 BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 – – – – – – REL 29 rr 3 BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL 22 rr 3 MC68HC908JL16 Data Sheet, Rev. 1.1 172 Freescale Semiconductor

Instruction Set Summary Table 15-1. Instruction Set Summary (Sheet 2 of 6) SFoourrmce Operation Description oEnf fCeCctR dressde code erand cles V H I N Z C do p p y AM O O C Branch if Higher or Same BHS rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3 (Same as BCC) BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 – – – – – – REL 2F rr 3 BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 – – – – – – REL 2E rr 3 BIT #opr IMM A5 ii 2 BIT opr DIR B5 dd 3 BIT opr EXT C5 hh ll 4 BIT opr,X IX2 D5 ee ff 4 Bit Test (A) & (M) 0 – – (cid:21) (cid:21) – BIT opr,X IX1 E5 ff 3 BIT ,X IX F5 2 BIT opr,SP SP1 9EE5 ff 4 BIT opr,SP SP2 9ED5 ee ff 5 BLE opr Branch if Less Than or Equal To PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL 93 rr 3 (Signed Operands) BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3 BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL 23 rr 3 BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) =1 – – – – – – REL 91 rr 3 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 – – – – – – REL 2C rr 3 BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 – – – – – – REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 – – – – – – REL 2D rr 3 BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 – – – – – – REL 26 rr 3 BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 – – – – – – REL 2A rr 3 BRA rel Branch Always PC ← (PC) + 2 + rel – – – – – – REL 20 rr 3 DIR (b0) 01 dd rr 5 DIR (b1) 03 dd rr 5 DIR (b2) 05 dd rr 5 DIR (b3) 07 dd rr 5 BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 – – – – – (cid:21) DIR (b4) 09 dd rr 5 DIR (b5) 0B dd rr 5 DIR (b6) 0D dd rr 5 DIR (b7) 0F dd rr 5 BRN rel Branch Never PC ← (PC) + 2 – – – – – – REL 21 rr 3 DIR (b0) 00 dd rr 5 DIR (b1) 02 dd rr 5 DIR (b2) 04 dd rr 5 DIR (b3) 06 dd rr 5 BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 – – – – – (cid:21) DIR (b4) 08 dd rr 5 DIR (b5) 0A dd rr 5 DIR (b6) 0C dd rr 5 DIR (b7) 0E dd rr 5 DIR (b0) 10 dd 4 DIR (b1) 12 dd 4 DIR (b2) 14 dd 4 DIR (b3) 16 dd 4 BSET n,opr Set Bit n in M Mn ← 1 – – – – – – DIR (b4) 18 dd 4 DIR (b5) 1A dd 4 DIR (b6) 1C dd 4 DIR (b7) 1E dd 4 PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) BSR rel Branch to Subroutine – – – – – – REL AD rr 4 SP ← (SP) – 1 PC ← (PC) + rel CBEQ opr,rel PC ← (PC) + 3 + rel ? (A) – (M) = $00 DIR 31 dd rr 5 CBEQA #opr,rel PC ← (PC) + 3 + rel ? (A) – (M) = $00 IMM 41 ii rr 4 CBEQX #opr,rel PC ← (PC) + 3 + rel ? (X) – (M) = $00 IMM 51 ii rr 4 Compare and Branch if Equal – – – – – – CBEQ opr,X+,rel PC ← (PC) + 3 + rel ? (A) – (M) = $00 IX1+ 61 ff rr 5 CBEQ X+,rel PC ← (PC) + 2 + rel ? (A) – (M) = $00 IX+ 71 rr 4 CBEQ opr,SP,rel PC ← (PC) + 4 + rel ? (A) – (M) = $00 SP1 9E61 ff rr 6 CLC Clear Carry Bit C ← 0 – – – – – 0 INH 98 1 CLI Clear Interrupt Mask I ← 0 – – 0 – – – INH 9A 2 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 173

Central Processor Unit (CPU) Table 15-1. Instruction Set Summary (Sheet 3 of 6) SFoourrmce Operation Description oEnf fCeCctR dressde code erand cles V H I N Z C do p p y AM O O C CLR opr M ← $00 DIR 3F dd 3 CLRA A ← $00 INH 4F 1 CLRX X ← $00 INH 5F 1 CLRH Clear H ← $00 0 – – 0 1 – INH 8C 1 CLR opr,X M ← $00 IX1 6F ff 3 CLR ,X M ← $00 IX 7F 2 CLR opr,SP M ← $00 SP1 9E6F ff 4 CMP #opr IMM A1 ii 2 CMP opr DIR B1 dd 3 CMP opr EXT C1 hh ll 4 CMP opr,X IX2 D1 ee ff 4 Compare A with M (A) – (M) (cid:21) – – (cid:21) (cid:21) (cid:21) CMP opr,X IX1 E1 ff 3 CMP ,X IX F1 2 CMP opr,SP SP1 9EE1 ff 4 CMP opr,SP SP2 9ED1 ee ff 5 COM opr M ← (M) = $FF – (M) DIR 33 dd 4 COMA A ← (A) = $FF – (M) INH 43 1 COMX X ← (X) = $FF – (M) INH 53 1 Complement (One’s Complement) 0 – – (cid:21) (cid:21) 1 COM opr,X M ← (M) = $FF – (M) IX1 63 ff 4 COM ,X M ← (M) = $FF – (M) IX 73 3 COM opr,SP M ← (M) = $FF – (M) SP1 9E63 ff 5 CPHX #opr IMM 65 ii ii+1 3 Compare H:X with M (H:X) – (M:M + 1) (cid:21) – – (cid:21) (cid:21) (cid:21) CPHX opr DIR 75 dd 4 CPX #opr IMM A3 ii 2 CPX opr DIR B3 dd 3 CPX opr EXT C3 hh ll 4 CPX ,X IX2 D3 ee ff 4 Compare X with M (X) – (M) (cid:21) – – (cid:21) (cid:21) (cid:21) CPX opr,X IX1 E3 ff 3 CPX opr,X IX F3 2 CPX opr,SP SP1 9EE3 ff 4 CPX opr,SP SP2 9ED3 ee ff 5 DAA Decimal Adjust A (A)10 U – – (cid:21) (cid:21) (cid:21) INH 72 2 A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1 5 DBNZ opr,rel PC ← (PC) + 3 + rel ? (result) ≠ 0 DIR 3B dd rr 3 DBNZA rel PC ← (PC) + 2 + rel ? (result) ≠ 0 INH 4B rr 3 DBNZX rel Decrement and Branch if Not Zero PC ← (PC) + 2 + rel ? (result) ≠ 0 – – – – – – INH 5B rr 5 DBNZ opr,X,rel PC ← (PC) + 3 + rel ? (result) ≠ 0 IX1 6B ff rr 4 DBNZ X,rel PC ← (PC) + 2 + rel ? (result) ≠ 0 IX 7B rr 6 DBNZ opr,SP,rel PC ← (PC) + 4 + rel ? (result) ≠ 0 SP1 9E6B ff rr DEC opr M ← (M) – 1 DIR 3A dd 4 DECA A ← (A) – 1 INH 4A 1 DECX X ← (X) – 1 INH 5A 1 Decrement (cid:21) – – (cid:21) (cid:21) – DEC opr,X M ← (M) – 1 IX1 6A ff 4 DEC ,X M ← (M) – 1 IX 7A 3 DEC opr,SP M ← (M) – 1 SP1 9E6A ff 5 A ← (H:A)/(X) DIV Divide – – – – (cid:21) (cid:21) INH 52 7 H ← Remainder EOR #opr IMM A8 ii 2 EOR opr DIR B8 dd 3 EOR opr EXT C8 hh ll 4 EOR opr,X Exclusive OR M with A A ← (A ⊕ M) 0 – – (cid:21) (cid:21) – IX2 D8 ee ff 4 EOR opr,X IX1 E8 ff 3 EOR ,X IX F8 2 EOR opr,SP SP1 9EE8 ff 4 EOR opr,SP SP2 9ED8 ee ff 5 INC opr M ← (M) + 1 DIR 3C dd 4 INCA A ← (A) + 1 INH 4C 1 INCX X ← (X) + 1 INH 5C 1 Increment (cid:21) – – (cid:21) (cid:21) – INC opr,X M ← (M) + 1 IX1 6C ff 4 INC ,X M ← (M) + 1 IX 7C 3 INC opr,SP M ← (M) + 1 SP1 9E6C ff 5 MC68HC908JL16 Data Sheet, Rev. 1.1 174 Freescale Semiconductor

Instruction Set Summary Table 15-1. Instruction Set Summary (Sheet 4 of 6) SFoourrmce Operation Description oEnf fCeCctR dressde code erand cles V H I N Z C do p p y AM O O C JMP opr DIR BC dd 2 JMP opr EXT CC hh ll 3 JMP opr,X Jump PC ← Jump Address – – – – – – IX2 DC ee ff 4 JMP opr,X IX1 EC ff 3 JMP ,X IX FC 2 JSR opr DIR BD dd 4 PC ← (PC) + n (n = 1, 2, or 3) JSR opr EXT CD hh ll 5 Push (PCL); SP ← (SP) – 1 JSR opr,X Jump to Subroutine – – – – – – IX2 DD ee ff 6 Push (PCH); SP ← (SP) – 1 JSR opr,X IX1 ED ff 5 PC ← Unconditional Address JSR ,X IX FD 4 LDA #opr IMM A6 ii 2 LDA opr DIR B6 dd 3 LDA opr EXT C6 hh ll 4 LDA opr,X IX2 D6 ee ff 4 Load A from M A ← (M) 0 – – (cid:21) (cid:21) – LDA opr,X IX1 E6 ff 3 LDA ,X IX F6 2 LDA opr,SP SP1 9EE6 ff 4 LDA opr,SP SP2 9ED6 ee ff 5 LDHX #opr IMM 45 ii jj 3 Load H:X from M H:X ← (M:M + 1) 0 – – (cid:21) (cid:21) – LDHX opr DIR 55 dd 4 LDX #opr IMM AE ii 2 LDX opr DIR BE dd 3 LDX opr EXT CE hh ll 4 LDX opr,X IX2 DE ee ff 4 Load X from M X ← (M) 0 – – (cid:21) (cid:21) – LDX opr,X IX1 EE ff 3 LDX ,X IX FE 2 LDX opr,SP SP1 9EEE ff 4 LDX opr,SP SP2 9EDE ee ff 5 LSL opr DIR 38 dd 4 LSLA INH 48 1 LSLX Logical Shift Left C 0 (cid:21) – – (cid:21) (cid:21) (cid:21) INH 58 1 LSL opr,X (Same as ASL) IX1 68 ff 4 LSL ,X b7 b0 IX 78 3 LSL opr,SP SP1 9E68 ff 5 LSR opr DIR 34 dd 4 LSRA INH 44 1 LSRX Logical Shift Right 0 C (cid:21) – – 0 (cid:21) (cid:21) INH 54 1 LSR opr,X IX1 64 ff 4 LSR ,X b7 b0 IX 74 3 LSR opr,SP SP1 9E64 ff 5 MOV opr,opr DD 4E dd dd 5 (M) ← (M) MOV opr,X+ Destination Source DIX+ 5E dd 4 Move 0 – – (cid:21) (cid:21) – MOV #opr,opr IMD 6E ii dd 4 H:X ← (H:X) + 1 (IX+D, DIX+) MOV X+,opr IX+D 7E dd 4 MUL Unsigned multiply X:A ← (X) × (A) – 0 – – – 0 INH 42 5 NEG opr DIR 30 dd 4 M ← –(M) = $00 – (M) NEGA INH 40 1 A ← –(A) = $00 – (A) NEGX INH 50 1 Negate (Two’s Complement) X ← –(X) = $00 – (X) (cid:21) – – (cid:21) (cid:21) (cid:21) NEG opr,X IX1 60 ff 4 M ← –(M) = $00 – (M) NEG ,X IX 70 3 M ← –(M) = $00 – (M) NEG opr,SP SP1 9E60 ff 5 NOP No Operation None – – – – – – INH 9D 1 NSA Nibble Swap A A ← (A[3:0]:A[7:4]) – – – – – – INH 62 3 ORA #opr IMM AA ii 2 ORA opr DIR BA dd 3 ORA opr EXT CA hh ll 4 ORA opr,X IX2 DA ee ff 4 Inclusive OR A and M A ← (A) | (M) 0 – – (cid:21) (cid:21) – ORA opr,X IX1 EA ff 3 ORA ,X IX FA 2 ORA opr,SP SP1 9EEA ff 4 ORA opr,SP SP2 9EDA ee ff 5 PSHA Push A onto Stack Push (A); SP ← (SP) – 1 – – – – – – INH 87 2 PSHH Push H onto Stack Push (H); SP ← (SP) – 1 – – – – – – INH 8B 2 PSHX Push X onto Stack Push (X); SP ← (SP) – 1 – – – – – – INH 89 2 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 175

Central Processor Unit (CPU) Table 15-1. Instruction Set Summary (Sheet 5 of 6) SFoourrmce Operation Description oEnf fCeCctR dressde code erand cles V H I N Z C do p p y AM O O C PULA Pull A from Stack SP ← (SP + 1); Pull (A) – – – – – – INH 86 2 PULH Pull H from Stack SP ← (SP + 1); Pull (H) – – – – – – INH 8A 2 PULX Pull X from Stack SP ← (SP + 1); Pull (X) – – – – – – INH 88 2 ROL opr DIR 39 dd 4 ROLA INH 49 1 ROLX INH 59 1 Rotate Left through Carry C (cid:21) – – (cid:21) (cid:21) (cid:21) ROL opr,X IX1 69 ff 4 ROL ,X b7 b0 IX 79 3 ROL opr,SP SP1 9E69 ff 5 ROR opr DIR 36 dd 4 RORA INH 46 1 RORX Rotate Right through Carry C (cid:21) – – (cid:21) (cid:21) (cid:21) INH 56 1 ROR opr,X IX1 66 ff 4 ROR ,X b7 b0 IX 76 3 ROR opr,SP SP1 9E66 ff 5 RSP Reset Stack Pointer SP ← $FF – – – – – – INH 9C 1 SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) RTI Return from Interrupt SP ← (SP) + 1; Pull (X) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) INH 80 7 SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) SP ← SP + 1; Pull (PCH) RTS Return from Subroutine – – – – – – INH 81 4 SP ← SP + 1; Pull (PCL) SBC #opr IMM A2 ii 2 SBC opr DIR B2 dd 3 SBC opr EXT C2 hh ll 4 SBC opr,X IX2 D2 ee ff 4 Subtract with Carry A ← (A) – (M) – (C) (cid:21) – – (cid:21) (cid:21) (cid:21) SBC opr,X IX1 E2 ff 3 SBC ,X IX F2 2 SBC opr,SP SP1 9EE2 ff 4 SBC opr,SP SP2 9ED2 ee ff 5 SEC Set Carry Bit C ← 1 – – – – – 1 INH 99 1 SEI Set Interrupt Mask I ← 1 – – 1 – – – INH 9B 2 STA opr DIR B7 dd 3 STA opr EXT C7 hh ll 4 STA opr,X IX2 D7 ee ff 4 STA opr,X Store A in M M ← (A) 0 – – (cid:21) (cid:21) – IX1 E7 ff 3 STA ,X IX F7 2 STA opr,SP SP1 9EE7 ff 4 STA opr,SP SP2 9ED7 ee ff 5 STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – (cid:21) (cid:21) – DIR 35 dd 4 Enable Interrupts, Stop Processing, STOP I ← 0; Stop Processing – – 0 – – – INH 8E 1 Refer to MCU Documentation STX opr DIR BF dd 3 STX opr EXT CF hh ll 4 STX opr,X IX2 DF ee ff 4 STX opr,X Store X in M M ← (X) 0 – – (cid:21) (cid:21) – IX1 EF ff 3 STX ,X IX FF 2 STX opr,SP SP1 9EEF ff 4 STX opr,SP SP2 9EDF ee ff 5 SUB #opr IMM A0 ii 2 SUB opr DIR B0 dd 3 SUB opr EXT C0 hh ll 4 SUB opr,X IX2 D0 ee ff 4 Subtract A ← (A) – (M) (cid:21) – – (cid:21) (cid:21) (cid:21) SUB opr,X IX1 E0 ff 3 SUB ,X IX F0 2 SUB opr,SP SP1 9EE0 ff 4 SUB opr,SP SP2 9ED0 ee ff 5 MC68HC908JL16 Data Sheet, Rev. 1.1 176 Freescale Semiconductor

Opcode Map Table 15-1. Instruction Set Summary (Sheet 6 of 6) SFoourrmce Operation Description oEnf fCeCctR dressde code erand cles V H I N Z C do p p y AM O O C PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SWI Software Interrupt – – 1 – – – INH 83 9 SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte TAP Transfer A to CCR CCR ← (A) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) INH 84 2 TAX Transfer A to X X ← (A) – – – – – – INH 97 1 TPA Transfer CCR to A A ← (CCR) – – – – – – INH 85 1 TST opr DIR 3D dd 3 TSTA INH 4D 1 TSTX INH 5D 1 Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – (cid:21) (cid:21) – TST opr,X IX1 6D ff 3 TST ,X IX 7D 2 TST opr,SP SP1 9E6D ff 4 TSX Transfer SP to H:X H:X ← (SP) + 1 – – – – – – INH 95 2 TXA Transfer X to A A ← (X) – – – – – – INH 9F 1 TXS Transfer H:X to SP (SP) ← (H:X) – 1 – – – – – – INH 94 2 I bit ← 0; Inhibit CPU clocking WAIT Enable Interrupts; Wait for Interrupt – – 0 – – – INH 8F 1 until interrupted A Accumulator n Any bit C Carry/borrow bit opr Operand (one or two bytes) CCR Condition code register PC Program counter dd Direct address of operand PCH Program counter high byte dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte DD Direct to direct addressing mode REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer H Half-carry bit U Undefined H Index register high byte V Overflow bit hh ll High and low bytes of operand address in extended addressing X Index register low byte I Interrupt mask Z Zero bit ii Immediate operand byte & Logical AND IMD Immediate source to direct destination addressing mode | Logical OR IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX+ Indexed, no offset, post increment addressing mode # Immediate value IX+D Indexed with post increment to direct addressing mode « Sign extend IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX1+ Indexed, 8-bit offset, post increment addressing mode ? If IX2 Indexed, 16-bit offset addressing mode : Concatenated with M Memory location (cid:21) Set or cleared N Negative bit — Not affected 15.8 Opcode Map See Table 15-2. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 177

1 C 78 Table 15-2. Opcode Map en tr Bit Manipulation Branch Read-Modify-Write Control Register/Memory a DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX l P r MSB o 0 1 2 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F c LSB e s 5 4 3 4 1 1 4 5 3 7 3 2 3 4 4 5 3 4 2 s 0 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG NEG RTI BGE SUB SUB SUB SUB SUB SUB SUB SUB or 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX U 5 4 3 5 4 4 5 6 4 4 3 2 3 4 4 5 3 4 2 n 1 B3RCDLRIR0 2BCLDRIR0 2BRRNEL 3CBEDQIR 3CBEIMQAM 3CBEIMQXM 3CBIXE1Q+ 4CBESQP1 2CBEIXQ+ 1RTINSH 2 BLRTEL 2CMIMPM 2CMDPIR 3CMEPXT 3CMIXP2 4CMSPP2 2CMIXP1 3CMSPP1 1CMIXP it (C 5 4 3 5 7 3 2 3 2 3 4 4 5 3 4 2 P 2 BRSET1 BSET1 BHI MUL DIV NSA DAA BGT SBC SBC SBC SBC SBC SBC SBC SBC U 3 DIR 2 DIR 2 REL 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX ) 5 4 3 4 1 1 4 5 3 9 3 2 3 4 4 5 3 4 2 3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM COM SWI BLE CPX CPX CPX CPX CPX CPX CPX CPX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX 5 4 3 4 1 1 4 5 3 2 2 2 3 4 4 5 3 4 2 4 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR LSR TAP TXS AND AND AND AND AND AND AND AND M 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX C 5 4 3 4 3 4 3 4 1 2 2 3 4 4 5 3 4 2 6 5 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT BIT BIT 8 3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX H C 5 4 3 4 1 1 4 5 3 2 2 3 4 4 5 3 4 2 9 6 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR ROR PULA LDA LDA LDA LDA LDA LDA LDA LDA 0 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX 8 J 5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2 L1 7 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR ASR PSHA TAX AIS STA STA STA STA STA STA STA 6 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX D 5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2 a 8 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR EOR EOR ta 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX S 5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2 he 9 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC ADC ADC e 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX t, R A BRSE5T5 BSE4T5 BP3L DE4C DEC1A DEC1X DE4C DE5C DE3C PUL2H CL2I OR2A OR3A OR4A OR4A OR5A OR3A OR4A OR2A ev 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX . 1 5 4 3 5 3 3 5 6 4 2 2 2 3 4 4 5 3 4 2 .1 B BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD ADD ADD 3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 INH 3 IX1 4 SP1 2 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX 5 4 3 4 1 1 4 5 3 1 1 2 3 4 3 2 C BRSET6 BSET6 BMC INC INCA INCX INC INC INC CLRH RSP JMP JMP JMP JMP JMP 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 5 4 3 3 1 1 3 4 2 1 4 4 5 6 5 4 D BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST TST NOP BSR JSR JSR JSR JSR JSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 5 4 3 5 4 4 4 1 2 3 4 4 5 3 4 2 E BRSET7 BSET7 BIL MOV MOV MOV MOV STOP * LDX LDX LDX LDX LDX LDX LDX LDX F 3 DIR 2 DIR 2 REL 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX re 5 4 3 3 1 1 3 4 2 1 1 2 3 4 4 5 3 4 2 e F BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR CLR WAIT TXA AIX STX STX STX STX STX STX STX sc 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX a le S INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset MSB e IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset 0 High Byte of Opcode in Hexadecimal m DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with LSB ic EXT Extended IX2 Indexed, 16-Bit Offset Post Increment 5 Cycles ond DIXD+DDInidreecxte-dD-iDreircetct DIMIXD+DImirmecetd-Iinadtee-xDeidrect IX1+ PInodsetx Iendc,r e1m-Beyntet Offset with Low Byte of Opcode in Hexadecimal 0 3BRSDEITR0 ONupmcobdeer Mofn Beymteosn i/c Addressing Mode u *Pre-byte for stack pointer indexed instructions c to r

Chapter 16 Development Support 16.1 Introduction This section describes the break module, the monitor read-only memory (MON), and the monitor mode entry methods. 16.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. Features include: (cid:127) Accessible input/output (I/O) registers during the break Interrupt (cid:127) Central processor unit (CPU) generated break interrupts (cid:127) Software-generated break interrupts (cid:127) Computer operating properly (COP) disabling during break interrupts 16.2.1 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: (cid:127) A CPU-generated address (the address in the program counter) matches the contents of the break address registers. (cid:127) Software writes a logic one to the BRKA bit in the break status and control register. When a CPU generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 16-1 shows the structure of the break module. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 179

Development Support IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] CONTROL BKPT (TO SIM) 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] Figure 16-1. Break Module Block Diagram Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: SBSW Break Status Register R R R R R R R $FE00 Write: See note (BSR) Reset: 0 Read: Break Flag Control Register BCFE R R R R R R R $FE03 Write: (BFCR) Reset: 0 Read: Break Address High Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 $FE0C Register Write: (BRKH) Reset: 0 0 0 0 0 0 0 0 Read: Break Address low Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 $FE0D Register Write: (BRKL) Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 0 0 0 Break Status and Control BRKE BRKA $FE0E Register Write: (BRKSCR) Reset: 0 0 0 0 0 0 0 0 Note: Writing a logic 0 clears SBSW. =Unimplemented R =Reserved Figure 16-2. Break I/O Register Summary 16.2.2 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 16.2.6.4 Break Flag Control Register (BFCR) and see the Break Interrupts subsection for each module.) MC68HC908JL16 Data Sheet, Rev. 1.1 180 Freescale Semiconductor

Break Module (BRK) 16.2.3 CPU During Break Interrupts The CPU starts a break interrupt by: (cid:127) Loading the instruction register with the SWI instruction (cid:127) Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 16.2.4 TIM During Break Interrupts A break interrupt stops the timer counter. 16.2.5 COP During Break Interrupts The COP is disabled during a break interrupt when V is present on the RST pin. TST 16.2.6 Break Module Registers These registers control and monitor operation of the break module: (cid:127) Break status and control register (BRKSCR) (cid:127) Break address register high (BRKH) (cid:127) Break address register low (BRKL) (cid:127) Break status register (BSR) (cid:127) Break flag control register (BFCR) 16.2.6.1 Break Status and Control Register (BRKSCR) The break status and control register contains break module enable and status bits. Address: $FE0E Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 BRKE BRKA Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 16-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic zero to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic one to BRKA generates a break interrupt. Clear BRKA by writing a logic zero to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 181

Development Support 16.2.6.2 Break Address Registers The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: $FE0C Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: 0 0 0 0 0 0 0 0 Figure 16-4. Break Address Register High (BRKH) Address: $FE0D Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 16-5. Break Address Register Low (BRKL) 16.2.6.3 Break Status Register The break status register contains a flag to indicate that a break caused an exit from stop or wait mode. Address: $FE00 Bit 7 6 5 4 3 2 1 Bit 0 Read: SBSW R R R R R R R Write: Note(1) Reset: 0 R = Reserved 1. Writing a logic zero clears SBSW. Figure 16-6. Break Status Register (BSR) SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 16.2.6.4 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU is in a break state. MC68HC908JL16 Data Sheet, Rev. 1.1 182 Freescale Semiconductor

Break Module (BRK) Address: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read: BCFE R R R R R R R Write: Reset: 0 R = Reserved Figure 16-7. Break Flag Control Register (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break 16.2.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low-power-consumption standby modes. 16.2.7.1 Wait Mode If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if SBSW is set (see 4.6 Low-Power Modes). Clear the SBSW bit by writing logic zero to it. 16.2.7.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. See 4.7 SIM Registers. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 183

Development Support 16.3 Monitor Module (MON) This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. This mode is also used for programming and erasing of FLASH memory in the MCU. Monitor mode entry can be achieved without use of the higher test voltage, V , as long as vector addresses $FFFE and $FFFF are TST blank, thus reducing the hardware requirements for in-circuit programming. Features include: (cid:127) Normal user-mode pin functionality (cid:127) One pin dedicated to serial communication between monitor ROM and host computer (cid:127) Standard mark/space non-return-to-zero (NRZ) communication with host computer (cid:127) Execution of code in RAM or FLASH (cid:127) FLASH memory security feature(1) (cid:127) FLASH memory programming interface (cid:127) 959 bytes monitor ROM code size (cid:127) Monitor mode entry without high voltage, V , if reset vector is blank ($FFFE and $FFFF contain TST $FF) (cid:127) Standard monitor mode entry if high voltage, V , is applied to IRQ TST (cid:127) Resident routines for FLASH programming and EEPROM emulation 16.3.1 Functional Description The monitor ROM receives and executes commands from a host computer. Figure 16-8 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute host-computer code in RAM while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTB0 pin. A level-shifting and multiplexing interface is required between PTB0 and the host computer. PTB0 is used in a wired-OR configuration and requires a pull-up resistor. 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908JL16 Data Sheet, Rev. 1.1 184 Freescale Semiconductor

Monitor Module (MON) V DD HC908JL16 10 k RST 0.1 µF V DD V EXT OSC (50% DUTY) DD V OSC1 DD 0.1 µF V SS EXT OSC CONNECTION TO OSC1, WITH OSC2 UNCONNECTED, CAN REPLACE XTAL CIRCUIT. 9.8304MHz OSC1 20 pF M 0 1 OSC2 20 pF MAX232 V DD 1 16 C1+ VCC + + XTAL CIRCUIT 1 µF 1 µF 3 C1– GND 15 1 µF + 4 2 VTST A SW1 C2+ V+ (SEE NOTE 1) 1 µF + 6 VDD 1 k 8.5 V IRQ V– B V 5 DD C2– 1 µF 10 k + 10 k DB9 74HC125 2 7 10 6 5 PTB0 74HC125 3 8 9 2 3 4 VDD V DD 1 5 10 k 10 k C SW2 PTB1 (SEE NOTE 2) PTB3 NOTES: D PTB2 1. Monitor mode entry method: 10 k SW1: Position A — High voltage entry (V ) 10 k TST Bus clock depends on SW2. SW1: Position B — Reset vector must be blank ($FFFE = $FFFF = $FF) Bus clock = OSC1 ÷ 4. 2. Affects high voltage entry to monitor mode only (SW1 at position A): SW2: Position C — Bus clock = OSC1 ÷ 4 SW2: Position D — Bus clock = OSC1 ÷ 2 5. See Table17-4 for V voltage level requirements. TST Figure 16-8. Monitor Mode Circuit MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 185

Development Support 16.3.2 Entering Monitor Mode Table 16-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR. Communication at 9600 baud will be established provided one of the following sets of conditions is met: 1. If IRQ = V : TST – Clock on OSC1 is 4.9125MHz – PTB3 = low 2. If IRQ = V : TST – Clock on OSC1 is 9.8304MHz – PTB3 = high 3. If $FFFE and $FFFF are blank (contain $FF): – Clock on OSC1 is 9.8304MHz – IRQ = V DD Table 16-1. Monitor Mode Entry Requirements and Options $FFFE 3 2 1 0 IRQ and B B B B OSC1 Clock(1) Bus Frequency Comments T T T T $FFFF P P P P V (2) X 0 0 1 1 4.9152MHz 2.4576MHz High voltage entry to monitor TST mode. V (1) X 1 0 1 1 9.8304MHz 2.4576MHz 9600 baud communication on TST PTB0. COP disabled. Blank reset vector BLANK (low-voltage) entry to monitor VDD (contain X X X 1 9.8304MHz 2.4576MHz mode. $FF) 9600 baud communication on PTB0. COP disabled. NOT VDD BLANK X X X X X OSC1 ÷ 4 Enters User mode. 1. RC oscillator cannot be used for monitor mode; must use either external oscillator or XTAL oscillator circuit. 2. See Table17-4 for V voltage level requirements. TST If V is applied to IRQ and PTB3 is low upon monitor mode entry (Table 16-1 condition set 1), the bus TST frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with V applied to IRQ upon TST monitor mode entry (Table 16-1 condition set 2), the bus frequency is a divide-by-four of the clock input to OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if V is applied to IRQ. In this event, the OSCOUT frequency is equal to the TST 2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. Entering monitor mode with V on IRQ, the COP is disabled as long as V is applied to either IRQ or TST TST RST. (See Chapter 4 System Integration Module (SIM) for more information on modes of operation.) If entering monitor mode without high voltage on IRQ and reset vector being blank ($FFFE and $FFFF) (Table 16-1 condition set 3, where applied voltage is V ), then all port B pin requirements and conditions, DD including the PTB3 frequency divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit programming. Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the state of IRQ or the RST. MC68HC908JL16 Data Sheet, Rev. 1.1 186 Freescale Semiconductor

Monitor Module (MON) Figure 16-9. shows a simplified diagram of the monitor mode entry when the reset vector is blank and IRQ = V . An OSC1 frequency of 9.8304MHz is required for a baud rate of 9600. DD POR RESET NO IS VECTOR NORMAL USER BLANK? MODE YES MONITOR MODE EXECUTE MONITOR CODE NO POR TRIGGERED? YES Figure 16-9. Low-Voltage Monitor Mode Entry Flowchart Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes. (See 16.3.8 Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic zeros) to the host, indicating that it is ready to receive a command. The break signal also provides a timing reference to allow the host to determine the necessary baud rate. In monitor mode, the MCU uses different vectors for reset, SWI, and break interrupt. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. Table 16-2 is a summary of the vector differences between user mode and monitor mode. Table 16-2. Monitor Mode Vector Differences Functions Reset Reset Break Break SWI SWI Modes COP Vector Vector Vector Vector Vector Vector High Low High Low High Low User Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor Disabled(1) $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD Notes: 1. If the high voltage (V ) is removed from the IRQ pin or the RST pin, the SIM asserts its TST COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 187

Development Support When the host computer has completed downloading code into the MCU RAM, the host then sends a RUN command, which executes an RTI, which sends control to the address on the stack pointer. 16.3.3 Baud Rate The communication baud rate is dependant on oscillator frequency. The state of PTB3 also affects baud rate if entry to monitor mode is by IRQ = V . When PTB3 is high, the divide by ratio is 1024. If the PTB3 TST pin is at logic zero upon entry into monitor mode, the divide by ratio is 512. Table 16-3. Monitor Baud Rate Selection Monitor Mode OSC1 Clock PTB3 Baud Rate Entry By: Frequency 4.9152 MHz 0 9600 bps IRQ = VTST 9.8304 MHz 1 9600 bps 4.9152 MHz 1 4800 bps Blank reset vector, 9.8304 MHz X 9600 bps IRQ = VDD 4.9152 MHz X 4800 bps 16.3.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 16-10 and Figure 16-11.) NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT BIT Figure 16-10. Monitor Data Format NEXT START START $A5 BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT BIT START STOP BREAK BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT NEXT START BIT Figure 16-11. Sample Monitor Waveforms The data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. Transmit and receive baud rates must be identical. 16.3.5 Echoing As shown in Figure 16-12, the monitor ROM immediately echoes each received byte back to the PTB0 pin for error checking. SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA ECHO RESULT Figure 16-12. Read Transaction Any result of a command appears after the echo of the last byte of the command. MC68HC908JL16 Data Sheet, Rev. 1.1 188 Freescale Semiconductor

Monitor Module (MON) 16.3.6 Break Signal A start bit followed by nine low bits is a break signal. (See Figure 16-13.) When the monitor receives a break signal, it drives the PTB0 pin high for the duration of two bits before echoing the break signal. MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Figure 16-13. Break Transaction 16.3.7 Commands The monitor ROM uses the following commands: (cid:127) READ (read memory) (cid:127) WRITE (write memory) (cid:127) IREAD (indexed read) (cid:127) IWRITE (indexed write) (cid:127) READSP (read stack pointer) (cid:127) RUN (run user program) Table 16-4. READ (Read Memory) Command Description Read byte from memory Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA ECHO RESULT MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 189

Development Support Table 16-5. WRITE (Write Memory) Command Description Write byte to memory Operand Specifies 2-byte address in high byte:low byte order; low byte followed by data byte Data Returned None Opcode $49 Command Sequence SENT TO MONITOR WRITE WRITE ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA DATA ECHO Table 16-6. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand None Data Returned Returns contents of next two addresses Opcode $1A Command Sequence SENT TO MONITOR IREAD IREAD DATA DATA ECHO RESULT Table 16-7. IWRITE (Indexed Write) Command Description Write to last address accessed + 1 Operand Specifies single data byte Data Returned None Opcode $19 Command Sequence SENT TO MONITOR IWRITE IWRITE DATA DATA ECHO NOTE A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map. MC68HC908JL16 Data Sheet, Rev. 1.1 190 Freescale Semiconductor

Monitor Module (MON) Table 16-8. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR READSP READSP SP HIGH SP LOW ECHO RESULT Table 16-9. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence SENT TO MONITOR RUN RUN ECHO 16.3.8 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTB0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Figure 16-14.) NOTE Improved security function denies monitor mode entry if five or more of the eight security bytes are $00 (zero bytes). MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 191

Development Support Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE The MCU does not transmit a break character until after the host sends the eight security bytes. To determine whether the security code entered is correct, check to see if bit 6 of RAM address $60 is set. If it is, then the correct security code has been entered and FLASH can be accessed. V DD 4096 + 32 ICLK CYCLES RST 24 BUS CYCLES D N A E 1 E 2 E 8 MM T T T Y Y Y O B B B C FROM HOST PTB0 1 4 1 1 2 4 1 FROM MCU O O O O YTE 1 ECH YTE 2 ECH YTE 8 ECH BREAK MAND ECH B B B M O NOTES: C 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte. Figure 16-14. Monitor Mode Entry Timing If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). 16.3.9 ROM-Resident Routines Eight routines stored in the monitor ROM area (thus ROM-resident) are provided for FLASH memory manipulation. Six of the eight routines are intended to simplify FLASH program, erase, and load operations. The other two routines are intended to simplify the use of the FLASH memory as EEPROM. Table 16-10 shows a summary of the ROM-resident routines. MC68HC908JL16 Data Sheet, Rev. 1.1 192 Freescale Semiconductor

Monitor Module (MON) Table 16-10. Summary of ROM-Resident Routines Stack Used(1) Routine Name Routine Description Call Address (bytes) PRGRNGE Program a range of locations $FC06 11 ERARNGE Erase a page or the entire array $FCBE 7 LDRNGE Loads data from a range of locations $FF30 9 MON_PRGRNGE Program a range of locations in monitor mode $FF28 13 MON_ERARNGE Erase a page or the entire array in monitor mode $FF2C 9 Loads data from a range of locations in MON_LDRNGE $FF24 11 monitor mode Emulated EEPROM write. Data size ranges EE_WRITE $FD3F 24 from 2 to 15 bytes at a time. Emulated EEPROM read. Data size ranges EE_READ $FDD0 18 from 2 to 15 bytes at a time. 1. The listed stack size excludes the 2 bytes used by the calling instruction, JSR. The routines are designed to be called as stand-alone subroutines in the user program or monitor mode. The parameters that are passed to a routine are in the form of a contiguous data block, stored in RAM. The index register (H:X) is loaded with the address of the first byte of the data block (acting as a pointer), and the subroutine is called (JSR). Using the start address as a pointer, multiple data blocks can be used, any area of RAM can be used. A data block has the control and data bytes in a defined order, as shown in Figure 16-15. During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected. R A M FILE_PTR $XXXX BUS SPEED (BUS_SPD) ADDRESS AS POINTER DATA SIZE (DATASIZE) START ADDRESS HIGH (ADDRH) START ADDRESS LOW (ADDRL) DATA 0 DATA DATA 1 BLOCK DATA ARRAY DATA N Figure 16-15. Data Block Format for ROM-Resident Routines MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 193

Development Support The control and data bytes are described below. (cid:127) Bus speed — This one byte indicates the operating bus speed of the MCU. The value of this byte should be the nearest integer of the bus speed (in MHz) times 4, and should not be set to less than 4 (i.e. minimum bus speed is 1MHz). (cid:127) Data size — This one byte indicates the number of bytes in the data array that are to be manipulated. The maximum data array size is 128. Routines EE_WRITE and EE_READ are restricted to manipulate a data array between 2 to 15 bytes. Whereas routines ERARNGE and MON_ERARNGE do not manipulate a data array, thus, this data size byte has no meaning. (cid:127) Start address — These two bytes, high byte followed by low byte, indicate the start address of the FLASH memory to be manipulated. (cid:127) Data array — This data array contains data that are to be manipulated. Data in this array are programmed to FLASH memory by the programming routines: PRGRNGE, MON_PRGRNGE, EE_WRITE. For the read routines: LDRNGE, MON_LDRNGE, and EE_READ, data is read from FLASH and stored in this array. 16.3.9.1 PRGRNGE PRGRNGE is used to program a range of FLASH locations with data loaded into the data array. Table 16-11. PRGRNGE Routine Routine Name PRGRNGE Routine Description Program a range of locations Calling Address $FC06 Stack Used 11 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Start address high (ADDRH) Data Block Format Start address (ADDRL) Data 1 (DATA1) : Data N (DATAN) The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the number of bytes to be programmed is specified by DATASIZE. The maximum number of bytes that can be programmed in one routine call is 128 bytes (max. DATASIZE is 128). ADDRH:ADDRL do not need to be at a page boundary, the routine handles any boundary misalignment during programming. User software must ensure that the selected range is first erase. User software is also responsible for verifying programmed locations. The coding example below is to program 32 bytes of data starting at FLASH location $EF00, with a bus speed of 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. ORG RAM : FILE_PTR: BUS_SPD DS.B 1 ; Indicates 4x bus frequency DATASIZE DS.B 1 ; Data size to be programmed START_ADDR DS.W 1 ; FLASH start address DATAARRAY DS.B 32 ; Reserved data array MC68HC908JL16 Data Sheet, Rev. 1.1 194 Freescale Semiconductor

Monitor Module (MON) PRGRNGE EQU $FC06 FLASH_START EQU $EF00 ORG FLASH INITIALISATION: MOV #20,BUS_SPD MOV #32,DATASIZE LDHX #FLASH_START STHX START_ADDR RTS MAIN: BSR INITIALISATION : : LDHX #FILE_PTR JSR PRGRNGE 16.3.9.2 ERARNGE ERARNGE is used to erase a range of locations in FLASH. Table 16-12. ERARNGE Routine Routine Name ERARNGE Routine Description Erase a page or the entire array Calling Address $FCBE Stack Used 7 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Data Block Format Starting address (ADDRH) Starting address (ADDRL) There are two sizes of erase ranges: a page or the entire array. The ERARNGE will erase the page (64 consecutive bytes) in FLASH specified by the address ADDRH:ADDRL. This address can be any address within the page. Calling ERARNGE with ADDRH:ADDRL equal to $FFFF will erase the entire FLASH array (mass erase). Therefore, care must be taken when calling this routine to prevent an accidental mass erase. To avoid undesirable routine return addresses after a mass erase, the ERARNGE routine should not be called from code executed from FLASH memory. Load the code into an area of RAM before calling the ERARNGE routine. The ERARNGE routine uses neither a data array nor DATASIZE. The coding example below is to perform a page erase, from $EF00–$EF3F. The Initialization subroutine is the same as the coding example for PRGRNGE (see 16.3.9.1 PRGRNGE). ERARNGE EQU $FCBE MAIN: BSR INITIALISATION : : LDHX #FILE_PTR MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 195

Development Support JSR ERARNGE : 16.3.9.3 LDRNGE LDRNGE is used to load the data array in RAM with data from a range of FLASH locations. Table 16-13. LDRNGE Routine Routine Name LDRNGE Routine Description Loads data from a range of locations Calling Address $FF30 Stack Used 9 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Data Block Format Starting address (ADDRL) Data 1 : Data N The start location of FLASH from where data is retrieved is specified by the address ADDRH:ADDRL and the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can be retrieved in one routine call is 128 bytes. The data retrieved from FLASH is loaded into the data array in RAM. Previous data in the data array will be overwritten. User can use this routine to retrieve data from FLASH that was previously programmed. The coding example below is to retrieve 32 bytes of data starting from $EF00 in FLASH. The Initialization subroutine is the same as the coding example for PRGRNGE (see 16.3.9.1 PRGRNGE). LDRNGE EQU $FF30 MAIN: BSR INITIALIZATION : : LDHX #FILE_PTR JSR LDRNGE : MC68HC908JL16 Data Sheet, Rev. 1.1 196 Freescale Semiconductor

Monitor Module (MON) 16.3.9.4 MON_PRGRNGE In monitor mode, MON_PRGRNGE is used to program a range of FLASH locations with data loaded into the data array. Table 16-14. MON_PRGRNGE Routine Routine Name MON_PRGRNGE Routine Description Program a range of locations, in monitor mode Calling Address $FC28 Stack Used 13 bytes Bus speed Data size Starting address (high byte) Data Block Format Starting address (low byte) Data 1 : Data N The MON_PRGRNGE routine is designed to be used in monitor mode. It performs the same function as the PRGRNGE routine (see 16.3.9.1 PRGRNGE), except that MON_PRGRNGE returns to the main program via an SWI instruction. After a MON_PRGRNGE call, the SWI instruction will return the control back to the monitor code. 16.3.9.5 MON_ERARNGE In monitor mode, ERARNGE is used to erase a range of locations in FLASH. Table 16-15. MON_ERARNGE Routine Routine Name MON_ERARNGE Routine Description Erase a page or the entire array, in monitor mode Calling Address $FF2C Stack Used 9 bytes Bus speed Data size Data Block Format Starting address (high byte) Starting address (low byte) The MON_ERARNGE routine is designed to be used in monitor mode. It performs the same function as the ERARNGE routine (see 16.3.9.2 ERARNGE), except that MON_ERARNGE returns to the main program via an SWI instruction. After a MON_ERARNGE call, the SWI instruction will return the control back to the monitor code. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 197

Development Support 16.3.9.6 MON_LDRNGE In monitor mode, LDRNGE is used to load the data array in RAM with data from a range of FLASH locations. Table 16-16. ICP_LDRNGE Routine Routine Name MON_LDRNGE Routine Description Loads data from a range of locations, in monitor mode Calling Address $FF24 Stack Used 11 bytes Bus speed Data size Starting address (high byte) Data Block Format Starting address (low byte) Data 1 : Data N The MON_LDRNGE routine is designed to be used in monitor mode. It performs the same function as the LDRNGE routine (see 16.3.9.3 LDRNGE), except that MON_LDRNGE returns to the main program via an SWI instruction. After a MON_LDRNGE call, the SWI instruction will return the control back to the monitor code. 16.3.9.7 EE_WRITE EE_WRITE is used to write a set of data from the data array to FLASH. Table 16-17. EE_WRITE Routine Routine Name EE_WRITE Emulated EEPROM write. Data size ranges from 2 to 15 Routine Description bytes at a time. Calling Address $FD3F Stack Used 24 bytes Bus speed (BUS_SPD) Data size (DATASIZE)(1) Starting address (ADDRH)(2) Data Block Format Starting address (ADDRL)(1) Data 1 : Data N 1. The minimum data size is 2 bytes. The maximum data size is 15 bytes. 2. The start address must be a page boundary start address: $xx00, $xx40, $xx80, or $00C0. The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the number of bytes in the data array is specified by DATASIZE. The minimum number of bytes that can be programmed in one routine call is 2 bytes, the maximum is 15 bytes. ADDRH:ADDRL must always be the MC68HC908JL16 Data Sheet, Rev. 1.1 198 Freescale Semiconductor

Monitor Module (MON) start of boundary address (the page start address: $XX00, $XX40, $XX80, or $00C0) and DATASIZE must be the same size when accessing the same page. In some applications, the user may want to repeatedly store and read a set of data from an area of non-volatile memory. This can be easily implemented when EEPROM memory is used because the byte erase is allowed in EEPROM. On the other hand in FLASH memory, a minimum erase size is a page (64 bytes), so unused locations in a page will be wasted when it is used for data storage. The EE_WRITE routine is designed to emulate EEPROM using FLASH. This allows a FLASH page to implement data storage more efficiently. Each call of the EE_WRITE routine will automatically transfer the data in the data array (in RAM) to the next available blank locations in a page. Once the page is filled up with data, the EE_WRITE routine automatically erases the page and programs updated data in the same page. In a FLASH page, data is programmed to FLASH with in a block that consists of the data array and one boundary byte. The boundary byte contains the remaining number of bytes which can be programmed in the page (see Figure 16-16). F L A S H PAGE START $XX00, $XX40, $XX80, OR $XXC0 DATA ARRAY BOUNDARY ONE PAGE = 64 BYTES DATA ARRAY BOUNDARY DATA ARRAY BOUNDARY PAGE END Figure 16-16. EE_WRITE FLASH Memory Usage When using this routine to store a 3-byte data array, the FLASH page can be programmed 16 times before the an erase is required. In effect, the write/erase endurance is increased by 16 times. When a 15-byte data array is used, the write/erase endurance is increased by 4 times. Due to the FLASH page size limitation, the data array is limited from 2 bytes to 15 bytes. The coding example below uses the $EF00–$EE3F page for data storage. The data array size is 15 bytes, and the bus speed is 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 199

Development Support ORG RAM : FILE_PTR: BUS_SPD DS.B 1 ; Indicates 4x bus frequency DATASIZE DS.B 1 ; Data size to be programmed START_ADDR DS.W 1 ; FLASH page start address DATAARRAY DS.B 15 ; Reserved data array EE_WRITE EQU $FD3F FLASH_START EQU $EF00 ORG FLASH INITIALISATION: MOV #20,BUS_SPD MOV #15,DATASIZE LDHX #FLASH_START STHX START_ADDR RTS MAIN: BSR INITIALISATION : : LHDX #FILE_PTR JSR EE_WRITE NOTE The EE_WRITE routine is unable to check for incorrect data blocks, such as the FLASH page boundary address and data size. It is the responsibility of the user to ensure the starting address indicated in the data block is at the FLASH page boundary and the data size is 2 to 15. When the EE_WRITE routine detects a different data size from the size set up in the previous operation, the operation will not be executed. However in some situations, the routine cannot detect incorrect data size. The user must ensure that data size is same as the previous operation whenever this routine is executed. MC68HC908JL16 Data Sheet, Rev. 1.1 200 Freescale Semiconductor

Monitor Module (MON) 16.3.9.8 EE_READ EE_READ is used to load the data array in RAM with a set of data from FLASH. Table 16-18. EE_READ Routine Routine Name EE_READ Emulated EEPROM read. Data size ranges from 2 to 15 Routine Description bytes at a time. Calling Address $FDD0 Stack Used 18 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH)(1) Data Block Format Starting address (ADDRL)(1) Data 1 : Data N 1. The start address must be a page boundary start address: $xx00, $xx40, $xx80, or $00C0. The EE_READ routine reads data stored by the EE_WRITE routine. An EE_READ call will retrieve the last data written to a FLASH page and loaded into the data array in RAM. Same as EE_WRITE, the data size indicated by DATASIZE is 2 to 15, and the start address ADDRH:ADDRL must the FLASH page boundary address. The coding example below uses the data stored by the EE_WRITE coding example (see 16.3.9.7 EE_WRITE). It loads the 15-byte data set stored in the $EF00–$EE7F page to the data array in RAM. The initialization subroutine is the same as the coding example for EE_WRITE (see 16.3.9.7 EE_WRITE). EE_READ EQU $FDD0 MAIN: BSR INITIALIZATION : : LDHX FILE_PTR JSR EE_READ NOTE The EE_READ routine is unable to check for incorrect data blocks, such as the FLASH page boundary address and data size. It is the responsibility of the user to ensure the starting address indicated in the data block is at the FLASH page boundary and the data size is 2 to 15. When the EE_READ routine detects a different data size from the size setup in the previous operation, the operation will not be executed.However in some situations, the routine cannot detect incorrect data size. The user must ensure that data size is same as the previous operation whenever this routine is executed. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 201

Development Support MC68HC908JL16 Data Sheet, Rev. 1.1 202 Freescale Semiconductor

Chapter 17 Electrical Specifications 17.1 Introduction This section contains electrical and timing specifications. 17.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 17.5 5-V DC Electrical Characteristics and 17.8 3-V DC Electrical Characteristics for guaranteed operating conditions. Table 17-1. Absolute Maximum Ratings Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to +6.0 V Input voltage VIN VSS–0.3 to VDD +0.3 V Mode entry voltage, IRQ pin VTST VSS–0.3 to +8.5 V Maximum current per pin excluding VDD and VSS I ±25 mA Storage temperature TSTG –55 to +150 °C Maximum current out of VSS IMVSS 100 mA Maximum current into VDD IMVDD 100 mA 1. Voltages referenced to V . SS NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that V and V be constrained to the IN OUT range V ≤ (V or V ) ≤ V . Reliability of operation is enhanced if SS IN OUT DD unused inputs are connected to an appropriate logic voltage level (for example, either V or V .) SS DD MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 203

Electrical Specifications 17.3 Functional Operating Range Table 17-2. Operating Range Characteristic Symbol Value Unit T A Operating temperature range –40 to +85 °C (T to T ) L H 3 ±10% Operating voltage range VDD 5 ±10% V 17.4 Thermal Characteristics Table 17-3. Thermal Characteristics Characteristic Symbol Value Unit Thermal resistance 28-pin PDIP 70 28-pin SOIC θJA 70 °C/W 32-pin SDIP 70 32-pin LQFP 95 I/O pin power dissipation PI/O User determined W P = (I ×V ) + P = Power dissipation(1) PD D K/D(TD + 2D7D3 °C)I/O W J P x(T + 273 °C) D A Constant(2) K W/°C + P 2×θ D JA Average junction temperature TJ TA + (PD × θJA) °C 1. Power dissipation is a function of temperature. 2. K constant unique to the device. K can be determined for a known T and measured P . With this value of K, P and T A D D J can be determined for any value of T . A MC68HC908JL16 Data Sheet, Rev. 1.1 204 Freescale Semiconductor

5-V DC Electrical Characteristics 17.5 5-V DC Electrical Characteristics Table 17-4. DC Electrical Characteristics (5V) Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (I = –2.0mA) LOAD VOH VDD–0.8 — — V PTA0–PTA7, PTB0–PTB7, PTD0–PTD7, PTE0–PTE1 Output low voltage (I = 1.6mA) LOAD PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5, VOL — — 0.4 V PTE0–PTE1 Output low voltage (I = 25mA) LOAD VOL — — 0.5 V PTD6, PTD7 LED drives (V = 3V) OL IOL 28 38 46 mA PTA0–PTA5, PTA7, PTD2, PTD3, PTD6, PTD7 Input high voltage PTA0–PTA7, PTB0–PTB7, PTD0–PTD7, PTE0–PTE1, VIH 0.7 × VDD — VDD V RST, IRQ, OSC1 Input low voltage PTA0–PTA7, PTB0–PTB7, PTD0–PTD7, PTE0–PTE1, VIL VSS — 0.3 × VDD V RST, IRQ, OSC1 V supply current, f = 8MHz DD OP Run(3) XTAL oscillator option — 10 18 mA RC oscillator option — 8 16 mA Wait(4) XTAL oscillator option IDD — 4.5 10 mA RC oscillator option — 2.5 9.5 mA Stop(5) (–40°C to 85°C) — 150 220 µA XTAL or RC oscillator option (LVI enabled) — 1 5 µA XTAL or RC oscillator option (LVI disabled) Digital I/O ports Hi-Z leakage current IIL — — ± 10 µA Input current IIN — — ± 1 µA Capacitance COUT — — 12 pF Ports (as input or output) C — — 8 IN POR rearm voltage(6) VPOR 750 — — mV POR rise time ramp rate(7) RPOR 0.035 — — V/ms Monitor mode entry voltage VTST 1.5 × VDD — 8.5 V Pullup resistors(8) RST, IRQ, PTA0–PTA7, PTD6, PTD7 RPU 16 24 32 kΩ Table continued on next page MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 205

Electrical Specifications Table 17-4. DC Electrical Characteristics (5V) Characteristic(1) Symbol Min Typ(2) Max Unit Low-voltage inhibit, trip falling voltage VTRIPF 3.90 4.20 4.50 V Low-voltage inhibit, trip rising voltage VTRIPR 4.00 4.30 4.60 V Low-voltage inhibit reset/recovery hysteresis VHYS — 100 — mV 1. V = 4.5 to 5.5 Vdc, V = 0 Vdc, T = T to T , unless otherwise noted. DD SS A L H 2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only. 3. Run (operating) I measured using external square wave clock source (f = 8MHz). All inputs 0.2V from rail. No dc loads. DD OP Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects L run I . Measured with all modules enabled. DD 4. Wait I measured using external square wave clock source (f = 8MHz). All inputs 0.2V from rail. No dc loads. Less than DD OP 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects waitI . L DD 5. Stop I measured with OSC1 grounded; no port pins sourcing current. DD 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum V is not reached before the internal POR reset is released, RST must be driven low externally until minimum DD V is reached. DD 8. R is measured at V = 5.0V. PU DD 17.6 5-V Control Timing Table 17-5. Control Timing (5V) Characteristic(1) Symbol Min Max Unit Internal operating frequency fOP — 8 MHz RST input pulse width low(2) tIRL 750 — ns TIM2 external clock input fT2CLK — 4 MHz IRQ interrupt pulse width low (edge-triggered)(3) tILIH 100 — ns IRQ interrupt pulse period(3) tILIL Note(4) — tCYC 1. V = 4.5 to 5.5 Vdc, V = 0 Vdc, T = T to T ; timing shown with respect to 20% V and 70% V , unless otherwise DD SS A L H DD SS noted. 2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. 3. Values are based on characterization results, not tested in production. 4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t . CYC t RL RST t ILIL t ILIH IRQ Figure 17-1. RST and IRQ Timing MC68HC908JL16 Data Sheet, Rev. 1.1 206 Freescale Semiconductor

5-V Oscillator Characteristics 17.7 5-V Oscillator Characteristics Table 17-6. Oscillator Specifications (5V) Characteristic Symbol Min Typ Max Unit Internal oscillator clock frequency fICLK 50k(1) Hz External reference clock to OSC1 (2) fOSC dc — 32M Hz Crystal reference frequency (3)(4) fXTALCLK 1M — 32M Hz Crystal load capacitance (5) CL — — — Crystal fixed capacitance (3) C1 — 2 × CL — Crystal tuning capacitance (3) C2 — 2 × CL — Feedback bias resistor RB — 10 MΩ — Series resistor (3) fXTALCLK = 1MHz R — 20 — kΩ f = 4MHz S — 10 — kΩ XTALCLK f = 8MHz to 32MHz — 0 — kΩ XTALCLK External RC clock frequency fRCCLK 2M — 12M Hz RC oscillator external R REXT See Figure 17-2 Ω RC oscillator external C CEXT — 10 — pF 1. Typical value reflect average measurements at midpoint of voltage range, 25 °C only. See Figure 17-4 for plot. 2. No more than 10% duty cycle deviation from 50%. 3. Use fundamental mode only, do not use overtone crystals or overtone ceramic resonators. 4. Due to variations in electrical properties of external components such as, ESR and Load Capacitance, operation above 16MHz is not guaranteed for all crystals or ceramic resonators. Operation above 16 MHz requires that a Negative Resis- tance Margin (NRM) characterization and component optimization be performed by the crystal or ceramic resonator vendor for every different type of crystal or ceramic resonator which will be used. This characterization and optimization must be performed at the extremes of voltage and temperature which will be applied to the microcontroller in the application. The NRM must meet or exceed 10x the maximum ESR of the crystal or ceramic resonator for acceptable performance. 5. Consult crystal vendor data sheet. 14 12 C = 10 pF MCU EXT 10 5V @ 25°C OSC1 z) 8 H M (K CL 6 C y, fR VDD enc 4 REXT CEXT u q e C fr 2 R 0 0 10 20 30 40 50 Resistor, R (kΩ) EXT Figure 17-2. RC vs. Frequency (5V @25°C) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 207

Electrical Specifications 17.8 3-V DC Electrical Characteristics Table 17-7. DC Electrical Characteristics (3V) Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (I = –1.0 mA) LOAD VOH VDD–0.4 — — V PTA0–PTA7, PTB0–PTB7, PTD0–PTD7, PTE0–PTE1 Output low voltage (I = 0.8 mA) LOAD PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5, VOL — — 0.4 V PTE0–PTE1 Output low voltage (I = 20 mA) LOAD VOL — — 0.5 V PTD6, PTD7 LED drives (V = 1.8V) OL IOL 8 18 26 mA PTA0–PTA5, PTA7, PTD2, PTD3, PTD6, PTD7 Input high voltage PTA0–PTA7, PTB0–PTB7, PTD0–PTD7, PTE0–PTE1, VIH 0.7 × VDD — VDD V RST, IRQ, OSC1 Input low voltage PTA0–PTA7, PTB0–PTB7, PTD0–PTD7, VIL VSS — 0.3 × VDD V PTE0–PTE1,RST, IRQ, OSC1 V supply current, f = 4MHz DD OP Run(3) XTAL oscillator option — 4.5 10 mA RC oscillator option — 4 9 mA Wait(4) XTAL oscillator option IDD — 2 7 mA RC oscillator option — 1 6 mA Stop(5) (–40°C to 85°C) — 130 200 µA XTAL or RC oscillator option (LVI enabled) — 0.5 3 µA XTAL or RC oscillator option (LVI disabled) Digital I/O ports Hi-Z leakage current IIL — — ± 10 µA Input current IIN — — ± 1 µA Capacitance COUT — — 12 pF Ports (as input or output) C — — 8 IN POR rearm voltage(6) VPOR 750 — — mV POR rise time ramp rate(7) RPOR 0.035 — — V/ms Monitor mode entry voltage VTST 1.5 × VDD — 8.5 V Pullup resistors(8) RST, IRQ, PTA0–PTA7, PTD6, PTD7 RPU 16 24 32 kΩ Table continued on next page MC68HC908JL16 Data Sheet, Rev. 1.1 208 Freescale Semiconductor

3-V Control Timing Table 17-7. DC Electrical Characteristics (3V) Characteristic(1) Symbol Min Typ(2) Max Unit Low-voltage inhibit, trip falling voltage VTRIPF 2.40 2.55 2.70 V Low-voltage inhibit, trip rising voltage VTRIPR 2.475 2.625 2.775 V Low-voltage inhibit reset/recovery hysteresis VHYS — 75 — mV 1. V = 2.7 to 3.3 Vdc, V = 0 Vdc, T = T to T , unless otherwise noted. DD SS A L H 2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only. 3. Run (operating) I measured using external square wave clock source (f = 4MHz). All inputs 0.2V from rail. No dc loads. DD OP Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects L run I . Measured with all modules enabled. DD 4. Wait I measured using external square wave clock source (f = 4MHz). All inputs 0.2V from rail. No dc loads. Less than DD OP 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects waitI . L DD 5. Stop I measured with OSC1 grounded; no port pins sourcing current. DD 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum V is not reached before the internal POR reset is released, RST must be driven low externally until minimum DD V is reached. DD 8. R is measured at V = 5.0V. PU DD 17.9 3-V Control Timing Table 17-8. Control Timing (3V) Characteristic(1) Symbol Min Max Unit Internal operating frequency(2) fOP — 4 MHz RST input pulse width low(3) tIRL 1.5 — µs IRQ input pulse width low(3) tIIL 1.5 — µs TIM2 external clock input fT2CLK — 2 MHz 1. V = 2.7 to 3.3 Vdc, V = 0 Vdc, T = T to T ; timing shown with respect to 20% V and 70% V , unless otherwise DD SS A L H DD DD noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor- mation. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 209

Electrical Specifications 17.10 3-V Oscillator Characteristics Table 17-9. Oscillator Specifications (3V) Characteristic Symbol Min Typ Max Unit Internal oscillator clock frequency fICLK 45k(1) Hz External reference clock to OSC1 (2) fOSC dc — 16M Hz Crystal reference frequency (3)(4) fXTALCLK 1M — 16M Hz Crystal load capacitance (5) CL — — — Crystal fixed capacitance (3) C1 — 2 × CL — Crystal tuning capacitance (3) C2 — 2 × CL — Feedback bias resistor RB — 10 MΩ — Series resistor (3) fXTALCLK = 1MHz R — 20 — kΩ f = 4MHz S — 10 — kΩ XTALCLK f = 8MHz to 16MHz — 0 — kΩ XTALCLK External RC clock frequency fRCCLK 2M — 10M Hz RC oscillator external R REXT See Figure 17-3 Ω RC oscillator external C CEXT — 10 — pF 1. Typical value reflect average measurements at midpoint of voltage range, 25 °C only. See Figure 17-4 for plot. 2. No more than 10% duty cycle deviation from 50%. 3. Use fundamental mode only, do not use overtone crystals or overtone ceramic resonators. 4. Due to variations in electrical properties of external components such as, ESR and Load Capacitance, operation above 16MHz is not guaranteed for all crystals or ceramic resonators. Operation above 16 MHz requires that a Negative Resis- tance Margin (NRM) characterization and component optimization be performed by the crystal or ceramic resonator vendor for every different type of crystal or ceramic resonator which will be used. This characterization and optimization must be performed at the extremes of voltage and temperature which will be applied to the microcontroller in the application. The NRM must meet or exceed 10x the maximum ESR of the crystal or ceramic resonator for acceptable performance. 5. Consult crystal vendor data sheet. 14 12 C = 10 pF MCU EXT 10 3V @ 25°C OSC1 z) 8 H M (K CL 6 C y, fR VDD enc 4 REXT CEXT u q e C fr 2 R 0 0 10 20 30 40 50 Resistor, R (kΩ) EXT Figure 17-3. RC vs. Frequency (3V @25°C) MC68HC908JL16 Data Sheet, Rev. 1.1 210 Freescale Semiconductor

Typical Supply Currents 70 –40°C Hz) 60 k (K +25°C CL y, fI 50 c n ue +85°C q 40 e C fr S O 30 al n er Int 20 2 3 4 5 6 Supply Voltage, V (V) DD Figure 17-4. Internal Oscillator Frequency 17.11 Typical Supply Currents 10 8 XTAL oscillator option 6 5 V A) 3 V m (D 4 D I 2 0 0 1 2 3 4 5 6 7 8 9 f or f (MHz) OP BUS Figure 17-5. Typical Operating I (XTAL osc), DD with All Modules Turned On (25°C) 5 4 XTAL oscillator option 5 V 3 A) 3 V m (D 2 D I 1 0 0 1 2 3 4 5 6 7 8 9 f or f (MHz) OP BUS Figure 17-6. Typical Wait Mode I (XTAL osc), DD with All Modules Turned Off (25°C) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 211

Electrical Specifications 17.12 Timer Interface Module Characteristics Table 17-10. Timer Interface Module Characteristics (5V and 3V) Characteristic Symbol Min Max Unit Input capture pulse width tTIH, tTIL 1/fOP — Input clock pulse width (T2CLK pulse width) tLMIN, tHMIN (1/fOP) + 5ns — 17.13 ADC10 Characteristics Table 17-11. ADC10 Characteristics Characteristic Conditions Symbol Min Typ(1) Max Unit Comment Supply voltage Absolute VDD 2.7 — 5.5 V Supply Current VDD < 3.3 V (3.0 V Typ) — 55 — ALPC = 1 I (2) µA ALSMP = 1 VDD < 5.5 V (5.0 V Typ) DD — 75 — ADCO = 1 Supply current VDD < 3.3 V (3.0 V Typ) — 120 — ALPC = 1 I (2) µA ALSMP = 0 VDD < 5.5 V (5.0 V Typ) DD — 175 — ADCO = 1 Supply current VDD < 3.3 V (3.0 V Typ) — 140 — ALPC = 0 I (2) µA ALSMP = 1 VDD < 5.5 V (5.0 V Typ) DD — 180 — ADCO = 1 Supply current VDD < 3.3 V (3.0 V Typ) — 340 — ALPC = 0 I (2) µA ALSMP = 0 VDD < 5.5 V (5.0 V Typ) DD — 440 615 ADCO = 1 High speed (ALPC = 0) 0.40(3) — 2.00 ADC internal clock fADCK MHz tADCK = 1/fADCK Low power (ALPC = 1) 0.40(3) — 1.00 10-Bit Mode Short sample (ALSMP = 0) t 19 19 21 tADCK tBus =1/fBus Conversion time Long sample (ALSMP = 1) ADC 39 39 41 cycles cycles 8-Bit Mode Short sample (ALSMP = 0) t 16 16 18 tADCK tBus =1/fBus Conversion time Long sample (ALSMP = 1) ADC 36 36 38 cycles cycles Short sample (ALSMP = 0) 4 4 4 t Sample time tADS ADCK Long sample (ALSMP = 1) 24 24 24 cycles Input voltage VADIN VSS — VDD V Input capacitance CADIN — 7 10 pF Not tested Input impedance RADIN — 5 15 kΩ Not tested — Continued on next page MC68HC908JL16 Data Sheet, Rev. 1.1 212 Freescale Semiconductor

ADC10 Characteristics Table 17-11. ADC10 Characteristics Characteristic Conditions Symbol Min Typ(1) Max Unit Comment External to Analog source impedance RAS — — 10 kΩ MCU 10-bit mode 1.758 5 5.371 Ideal resolution (1 LSB) RES mV V /2N REFH 8-bit mode 7.031 20 21.48 10-bit mode 0 ±2.0 ±2.5 Includes Total unadjusted error 8-bit mode ETUE 0 ±0.7 ±1.0 LSB quantization 10-bit mode 0 ±0.5 — DNL LSB Differential non-linearity 8-bit mode 0 ±0.3 — Monotonicity and no-missing-codes guaranteed 10-bit mode 0 ±0.5 — Integral non-linearity INL LSB 8-bit mode 0 ±0.3 — 10-bit mode 0 ±0.5 — Zero-scale error EZS LSB VADIN = VSS 8-bit mode 0 ±0.3 — 10-bit mode 0 ±2.0 — Full-scale error EFS LSB VADIN = VDD 8-bit mode 0 ±0.3 — 10-bit mode — — ±0.5 8-bit mode is Quantization error 8-bit mode EQ — — ±0.5 LSB not truncated 10-bit mode 0 ±0.2 ±5 Pad leakage(4) Input leakage error EIL LSB 8-bit mode 0 ±0.1 ±1.2 * RAS Bandgap voltage input(5) VBG 1.17 1.245 1.32 V 1. Typical values assume V = 5.0 V, temperature = 25°C, f = 1.0 MHz unless otherwise stated. Typical values are for DD ADCK reference only and are not tested in production. 2. Incremental I added to MCU mode current. DD 3. Values are based on characterization results, not tested in production. 4. Based on typical input pad leakage current. 5. LVI must be enabled, (LVID = 0, in CONFIG1). Voltage input to ADCH4:0 = $1A, an ADC conversion on this channel allows user to determine supply voltage. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 213

Electrical Specifications 17.14 MMIIC Electrical Characteristics Table 17-12. MMIIC DC Electrical Characteristics Characteristic(1) Symbol Min Typ Max Unit Comments Input low VIL –0.5 — 0.8 V Data, clock input low. Input high VIH 2.1 — 5.5 V Data, clock input high. Data, clock output low; Output low VOL — — 0.4 V @I PULLUP,MAX Input leakage ILEAK — — ± 5 µA Input leakage current Current through pull-up resistor Pullup current IPULLUP 100 — 350 µA or current source. See note.(2) 1. V = 2.7 to 5.5Vdc, V = 0 Vdc, T = T to T , unless otherwise noted. DD SS A L H 2. The I (max) specification is determined primarily by the need to accommodate a maximum of 1.1kΩ equivalent se- PULLUP ries resistor of removable SMBus devices, such as the smart battery, while maintaining the V (max) of the bus. OL SDA SCL t t t t t t t HD.STA LOW HIGH SU.DAT HD.DAT SU.STA SU.STO Figure 17-7. MMIIC Signal Timings See Table 17-13 for MMIIC timing parameters. MC68HC908JL16 Data Sheet, Rev. 1.1 214 Freescale Semiconductor

MMIIC Electrical Characteristics Table 17-13. MMIIC Interface Input/Output Signal Timing Characteristic Symbol Min Typ Max Unit Comments Operating frequency fSMB 10 — 100 kHz MMIIC operating frequency Bus free time between STOP and Bus free time tBUF 4.7 — — µs START condition Hold time after (repeated) START Repeated start hold time. tHD.STA 4.0 — — µs condition. After this period, the first clock is generated. Repeated start setup time. tSU.STA 4.7 — — µs Repeated START condition setup time. Stop setup time tSU.STO 4.0 — — µs Stop condition setup time. Hold time tHD.DAT 300 — — ns Data hold time. Setup time tSU.DAT 250 — — ns Data setup time. Clock low time-out tTIMEOUT 25 — 35 ms Clock low time-out.(1) Clock low tLOW 4.7 — — µs Clock low period Clock high tHIGH 4.0 — — µs Clock high period.(2) Cumulative clock low extend time (slave Slave clock low extend time tLOW.SEXT — — 25 ms device)(3) Cumulative clock low extend time Master clock low extend time tLOW.MEXT — — 10 ms (master device) (4) Fall time tF — — 300 ns Clock/Data Fall Time(5) Rise time tR — — 1000 ns Clock/Data Rise Time(5) 1. Devices participating in a transfer will timeout when any clock low exceeds the value of T min. of 25ms. Devices TIMEOUT that have detected a timeout condition must reset the communication no later than T max of 35ms. The maximum TIMEOUT value specified must be adhered to by both a master and a slave as it incorporates the cumulative limit for both a master (10 ms) and a slave (25 ms). Software should turn-off the MMIIC module to release the SDA and SCL lines. 2. T provides a simple guaranteed method for devices to detect the idle conditions. HIGH MAX 3. T is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start LOW.SEXT to the stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 4. T is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as LOW.MEXT defined from start-to-ack, ack-to-ack, or ack-to-stop. 5. Rise and fall time is defined as follows: T = (V – 0.15) to (V + 0.15), T = 0.9×V to (V – 0.15). R ILMAX IHMIN F DD ILMAX MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 215

Electrical Specifications 17.15 Memory Characteristics Table 17-14. Memory Characteristics Characteristic Symbol Min Typ Max Unit RAM data retention voltage (1) V 1.3 — — V RDR FLASH program bus clock frequency — 1 — — MHz FLASH PGM/ERASE supply voltage (V ) V 2.7 — 5.5 V DD PGM/ERASE FLASH read bus clock frequency f (2) 0 — 8 M Hz Read FLASH page erase time <1 K cycles t 0.9 1 1.1 ms Erase >1 K cycles 3.6 4 5.5 FLASH mass erase time t 4 — — ms MErase FLASH PGM/ERASE to HVEN setup time t 10 — — µs NVS FLASH high-voltage hold time t 5 — — µs NVH FLASH high-voltage hold time (mass erase) t 100 — — µs NVHL FLASH program hold time t 5 — — µs PGS FLASH program time t 30 — 40 µs PROG FLASH return to read time t (3) 1 — — µs RCV FLASH cumulative program hv period t (4) — — 4 ms HV FLASH endurance(5) — 10 k 100 k — Cycles FLASH data retention time(6) — 15 100 — Years 1. Values are based on characterization results, not tested in production. 2. f is defined as the frequency range for which the FLASH memory can be read. Read 3. t is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing RCV HVEN to 0. 4. t is defined as the cumulative high voltage programming time to the same row before next erase. HV t must satisfy this condition: t + t + t + (t x 32) ≤ t maximum. HV NVS NVH PGS PROG HV 5. Typical endurance was evaluated for this product family. For additional information on how Freescale Semiconductor defines Typical Endurance, please refer to Engineering Bulletin EB619. 6. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines Typical Data Retention, please refer to Engineering Bulletin EB618. MC68HC908JL16 Data Sheet, Rev. 1.1 216 Freescale Semiconductor

Chapter 18 Ordering Information and Mechanical Specifications 18.1 Introduction This section contains order numbers for the MC68HC908JL16. Dimensions are given for: (cid:127) 28-pin plastic dual in-line package (PDIP) (cid:127) 28-pin small outline integrated circuit package (SOIC) (cid:127) 32-pin shrink dual in-line package (SDIP) (cid:127) 32-pin low-profile quad flat pack (LQFP) 18.2 MC Order Numbers Table 18-1. MC Order Numbers Operating MC Order Number Package Temperature Range MC908JL16CPE –40 to +85 °C 28-pin PDIP MC908JL16CDWE –40 to +85 °C 28-pin SOIC MC908JL16CSPE –40 to +85 °C 32-pin SDIP MC908JL16CFJE –40 to +85 °C 32-pin LQFP Temperature and package designators: C = –40 to +85 °C P = Plastic dual in-line package (PDIP) DW = Small outline integrated circuit package (SOIC) SP = Shrink dual in-line package (SDIP) FJ = Low-profile quad flat pack (LQFP) E = RoHS 18.3 Package Dimensions Refer to the following pages for detailed package dimensions. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor 217

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Ordering Information and Mechanical Specifications MC68HC908JL16 Data Sheet, Rev. 1.1 228 Freescale Semiconductor

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