MC68HC908AP64 MC68HC908AP32 MC68HC908AP16 MC68HC908AP8 Data Sheet M68HC08 Microcontrollers MC68HC908AP64 Rev. 4 01/2007 freescale.com

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MC68HC908AP64 MC68HC908AP32 MC68HC908AP16 MC68HC908AP8 Data Sheet Toprovidethemostup-to-dateinformation,therevisionofourdocumentsontheWorldWideWebwillbe the most current. Yourprinted copy may bean earlier revision. To verify youhave the latest information available, refer to: http://www.freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. ©Freescale Semiconductor, Inc., 2005, 2007. All rights reserved. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 3

Revision History Revision Page Date Description Level Number(s) 15.7.2 ADC Clock Control Register — Changed “The ADC clock should January 2007 4 be set to between 500kHz and 2MHz” to “The ADC clock should be set 254 to between 500kHz and 1MHz” Table22-4 . DC Electrical Characteristics (5V) — Updated VOL values. 299 Table22-6 . Oscillator Specifications (5V) andTable22-10 . Oscillator August 2005 3 Specifications (3V) — Corrected internal oscillator clock frequency, 301, 305 f . Updated crystal oscillator component values C , C , C , R , and ICLK L 1 2 B R . S Added MC68HC908AP16/AP8 information throughout. — Section 10. Monitor ROM (MON) — Corrected RAM address to $60. 167 October 2003 2.5 Section 24. Electrical Specifications — Added run and wait I data for DD 421 8MHz at 3V. August 2003 2.4 Section 24. Electrical Specifications — Updated stop IDD data. 417, 421 Removed MC68HC908AP16 references throughout. — Table 1-2 . Pin Functions — Added footnote for VREG. 30 5.3 Configuration Register 1 (CONFIG1) — Clarified LVIPWRD and 67 LVIREGD bits. Section8.ClockGeneratorModule(CGM),8.7.2StopMode—Updated 125 July 2003 2.3 BSC bit behavior. 10.5 ROM-Resident Routines — Corrected data size limits and control 168–193 byte size for EE_READ and EE_WRITE. Figure 12-2 . Timebase Control Register (TBCR) — Corrected register 207 address. Section 24. Electrical Specifications — Updated. 415 Updated for f = 125kHz and filter components NOM 101 in CGM section. May 2003 2.2 Updated electricals. 415 MC68HC908AP Family Data Sheet, Rev. 4 4 Freescale Semiconductor

List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Chapter 3 Configuration & Mask Option Registers (CONFIG & MOR). . . . . . . . . . . . . . . .49 Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Chapter 5 Oscillator (OSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Chapter 6 Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Chapter 7 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Chapter 8 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Chapter 9 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Chapter 10 Timebase Module (TBM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Chapter 11 Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . .155 Chapter 12 Infrared Serial Communications Interface Module (IRSCI) . . . . . . . . . . . . . .181 Chapter 13 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Chapter 14 Multi-Master IIC Interface (MMIIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 Chapter 15 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 Chapter 16 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 Chapter 17 External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 Chapter 18 Keyboard Interrupt Module (KBI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 Chapter 19 Computer Operating Properly (COP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 Chapter 20 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 Chapter 21 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 Chapter 22 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 Chapter 23 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 Chapter 24 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 5

List of Chapters MC68HC908AP Family Data Sheet, Rev. 4 6 Freescale Semiconductor

Table of Contents Chapter 1 General Description 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5 Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6 Power Supply Bypassing (VDD, VDDA, VSS, VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.7 Regulator Power Supply Configuration (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter 2 Memory 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4 Random-Access Memory (RAM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5.2 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.5.3 FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.5.4 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5.5 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5.6 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.5.7 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter 3 Configuration & Mask Option Registers (CONFIG & MOR) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3 Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4 Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5 Mask Option Register (MOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Chapter 4 Central Processor Unit (CPU) 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3.1 Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 7

Table of Contents 4.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.6 CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Chapter 5 Oscillator (OSC) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2.1 CGM Reference Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.2.2 TBM Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3 Internal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.4 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.5 X-tal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.6 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.6.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.6.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.6.3 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.6.4 CGM Oscillator Clock (CGMXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.6.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.6.6 Oscillator Clock to Time Base Module (OSCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.7 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.8 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Chapter 6 Clock Generator Module (CGM) 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.1 Oscillator Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.5 Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 MC68HC908AP Family Data Sheet, Rev. 4 8 Freescale Semiconductor

6.3.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.4 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.4.1 External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.4.2 PLL Analog Power Pin (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DDA 6.4.3 PLL Analog Ground Pin (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SSA 6.4.4 Oscillator Output Frequency Signal (CGMXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4.6 CGM VCO Clock Output (CGMVCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4.7 CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.5 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.5.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.5.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.5.3 PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.5.4 PLL VCO Range Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.5.5 PLL Reference Divider Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.7 Special Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.7.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.8 Acquisition/Lock Time Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.8.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.8.2 Parametric Influences on Reaction Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.8.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Chapter 7 System Integration Module (SIM) 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.2 SIM Bus Clock Control and Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.2.1 Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.2.2 Clock Start-up from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.2.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.3.1 External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.3.2.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.3.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.3.2.6 Monitor Mode Entry Module Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 9

Table of Contents 7.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.5.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.5.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.5.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.5.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.5.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.6 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.7.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.7.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Chapter 8 Monitor ROM (MON) 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.3.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.3.2 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.3.3 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.3.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.3.5 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.5 ROM-Resident Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.5.1 PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.5.2 ERARNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.5.3 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.5.4 MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.5.5 MON_ERARNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.5.6 EE_WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.5.7 EE_READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Chapter 9 Timer Interface Module (TIM) 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.4.1 TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.2 Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 MC68HC908AP Family Data Sheet, Rev. 4 10 Freescale Semiconductor

9.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.4.4 Pulse Width Modulation (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.4.4.3 PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.8 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.9.2 TIM Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 9.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Chapter 10 Timebase Module (TBM) 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.4 Timebase Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 10.6 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 10.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Chapter 11 Serial Communications Interface Module (SCI) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.4.1 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.4.2 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.4.2.2 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.4.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.4.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.4.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.4.3 Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 11

Table of Contents 11.4.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 11.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 11.4.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 11.4.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.4.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.5 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.6 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.7 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.7.1 TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.7.2 RxD (Receive Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.8.1 SCI Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.8.2 SCI Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.8.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.8.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.8.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.8.7 SCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Chapter 12 Infrared Serial Communications Interface Module (IRSCI) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 12.2 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 12.3 IRSCI Module Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 12.4 Infrared Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 12.4.1 Infrared Transmit Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 12.4.2 Infrared Receive Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 12.5 SCI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.5.1 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.5.2 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.5.2.2 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.5.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.5.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.5.2.5 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.5.3 Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 12.5.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 12.5.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 12.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 12.5.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.5.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.5.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 12.5.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 MC68HC908AP Family Data Sheet, Rev. 4 12 Freescale Semiconductor

12.5.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 12.6 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.7 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.8 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.8.1 PTC6/SCTxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.8.2 PTC7/SCRxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.9.1 IRSCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.9.2 IRSCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 12.9.3 IRSCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.9.4 IRSCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.9.5 IRSCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.9.6 IRSCI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.9.7 IRSCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.9.8 IRSCI Infrared Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Chapter 13 Serial Peripheral Interface Module (SPI) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13.3 Pin Name Conventions and I/O Register Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 13.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 13.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 13.5 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 13.5.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 13.5.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 13.5.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.5.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.6 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 13.7 Error Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 13.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 13.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 13.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 13.9 Resetting the SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 13.10 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13.11 SPI During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13.12 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.12.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.12.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.12.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.12.4 SS (Slave Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 13

Table of Contents 13.12.5 CGND (Clock Ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.13 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.13.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.13.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 13.13.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Chapter 14 Multi-Master IIC Interface (MMIIC) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 14.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.4 Multi-Master IIC System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.5 Multi-Master IIC Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 14.5.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 14.5.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 14.5.3 Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.5.4 Repeated START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.5.5 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.5.6 Arbitration Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.5.7 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.5.8 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.5.9 Packet Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.6 MMIIC I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.6.1 MMIIC Address Register (MMADR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.6.2 MMIIC Control Register 1 (MMCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 14.6.3 MMIIC Control Register 2 (MMCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 14.6.4 MMIIC Status Register (MMSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 14.6.5 MMIIC Data Transmit Register (MMDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 14.6.6 MMIIC Data Receive Register (MMDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 14.6.7 MMIIC CRC Data Register (MMCRCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 14.6.8 MMIIC Frequency Divider Register (MMFDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 14.7 Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 14.7.1 Data Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 14.8 SMBus Protocols with PEC and without PEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 14.8.1 Quick Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 14.8.2 Send Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 14.8.3 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 14.8.4 Write Byte/Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 14.8.5 Read Byte/Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 14.8.6 Process Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 14.8.7 Block Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 14.9 SMBus Protocol Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Chapter 15 Analog-to-Digital Converter (ADC) 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 MC68HC908AP Family Data Sheet, Rev. 4 14 Freescale Semiconductor

15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 15.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.3.5 Auto-Scan Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.3.6 Result Justification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 15.3.7 Data Register Interlocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 15.3.8 Monotonicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 15.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 15.5 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 15.6 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 15.6.1 ADC Voltage In (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 ADIN 15.6.2 ADC Analog Power Pin (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 DDA 15.6.3 ADC Analog Ground Pin (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 SSA 15.6.4 ADC Voltage Reference High Pin (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 REFH 15.6.5 ADC Voltage Reference Low Pin (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 REFL 15.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 15.7.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 15.7.2 ADC Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 15.7.3 ADC Data Register 0 (ADRH0 and ADRL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 15.7.4 ADC Auto-Scan Mode Data Registers (ADRL1–ADRL3) . . . . . . . . . . . . . . . . . . . . . . . . . 257 15.7.5 ADC Auto-Scan Control Register (ADASCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Chapter 16 Input/Output (I/O) Ports 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 16.2 Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 16.2.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 16.2.2 Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 16.2.3 Port-A LED Control Register (LEDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 16.3 Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 16.3.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 16.3.2 Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 16.4 Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 16.4.1 Port C Data Register (PTC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 16.4.2 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 16.5 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 16.5.1 Port D Data Register (PTD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 16.5.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Chapter 17 External Interrupt (IRQ) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 15

Table of Contents 17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 17.4 IRQ1 and IRQ2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 17.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 17.6 IRQ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 17.6.1 IRQ1 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 17.6.2 IRQ2 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Chapter 18 Keyboard Interrupt Module (KBI) 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 18.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 18.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 18.5 Keyboard Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 18.5.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 18.5.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 18.6 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 18.7 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Chapter 19 Computer Operating Properly (COP) 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 19.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 19.3 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.3.1 ICLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.3.3 COPCTL Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.3.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.3.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.3.6 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.3.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.3.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 19.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 19.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 19.6 Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 19.7 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 19.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 19.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 19.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Chapter 20 Low-Voltage Inhibit (LVI) 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 MC68HC908AP Family Data Sheet, Rev. 4 16 Freescale Semiconductor

20.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 20.3.1 Low V Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 DD 20.3.2 Low V Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 REG 20.3.3 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 20.3.4 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 20.3.5 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 20.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 20.5 LVI Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 20.6 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 20.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 20.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Chapter 21 Break Module (BRK) 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 21.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 21.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 21.3.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 21.3.2 CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 21.3.3 TIMI and TIM2 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 21.3.4 COP During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 21.4 Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 21.4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 21.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 21.5 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 21.5.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 21.5.2 Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 21.5.3 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 21.5.4 SIM Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Chapter 22 Electrical Specifications 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 22.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 22.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 22.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 22.5 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 22.6 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 22.7 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 22.8 5V ADC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 22.9 3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 22.10 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 22.11 3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 22.12 3V ADC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 17

Table of Contents 22.13 MMIIC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 22.14 CGM Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 22.15 5V SPI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 22.16 3V SPI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 22.17 Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Chapter 23 Mechanical Specifications 23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 23.2 48-Pin Low-Profile Quad Flat Pack (LQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 23.3 44-Pin Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 23.4 42-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Chapter 24 Ordering Information 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 24.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 MC68HC908AP Family Data Sheet, Rev. 4 18 Freescale Semiconductor

Chapter 1 General Description 1.1 Introduction The MC68HC908AP64 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontrollerunits(MCUs).AllMCUsinthefamilyusetheenhancedM68HC08centralprocessorunit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. Table 1-1. Summary of Device Variations RAM Size FLASH Memory Size Device (bytes) (bytes) MC68HC908AP64 2,048 62,368 MC68HC908AP32 2,048 32,768 MC68HC908AP16 1,024 16,384 MC68HC908AP8 1,024 8,192 1.2 Features Features of the MC68HC908AP64 include the following: • High-performance M68HC08 architecture • Fully upward-compatible object code with M6805, M146805, and M68HC05 Families • Maximum internal bus frequency: – 8-MHz at 5V or 3V operating voltage • Clock input options: – RC-oscillator – 32-kHz crystal-oscillator with 32MHz internal PLL • User program FLASH memory with security(1) feature – 62,368 bytes for MC68HC908AP64 – 32,768 bytes for MC68HC908AP32 – 16,384 bytes for MC68HC908AP16 – 8,192 bytes for MC68HC908AP8 • On-chip RAM – 2,048 bytes for MC68HC908AP64 and MC68HC908AP32 – 1,024 bytes for MC68HC908AP16 and MC68HC908AP8 • Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, and PWM capability on each channel 1.Nosecurityfeatureisabsolutelysecure.However,Freescale’sstrategyistomakereadingorcopyingtheFLASHdifficultfor unauthorized users. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 19

General Description • Timebase module • Serial communications interface module 1 (SCI) • Serial communications interface module 2 (SCI) with infrared (IR) encoder/decoder • Serial peripheral interface module (SPI) • System management bus (SMBus), version 1.0/1.1 (multi-master IIC bus) • 8-channel, 10-bit analog-to-digital converter (ADC) • IRQ1 external interrupt pin with integrated pullup • IRQ2 external interrupt pin with programmable pullup • 8-bit keyboard wakeup port with integrated pullup • 32 general-purpose input/output (I/O) pins: – 31 shared-function I/O pins – 8 LED drivers (sink) – 6 × 25mA open-drain I/O with pullup • Low-power design (fully static with stop and wait modes) • Master reset pin (with integrated pullup) and power-on reset • System protection features – Optional computer operating properly (COP) reset, driven by internal RC oscillator – Low-voltage detection with optional reset or interrupt – Illegal opcode detection with reset – Illegal address detection with reset • 48-pin low quad flat pack (LQFP), 44-pin quad flat pack (QFP), and 42-pin shrink dual-in-line package (SDIP) • Specific features of the MC68HC908AP64 in 42-pin SDIP are: – 30 general-purpose l/Os only – External interrupt on IRQ1 only Features of the CPU08 include the following: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit Index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply instruction • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908AP64. MC68HC908AP Family Data Sheet, Rev. 4 20 Freescale Semiconductor

MCU Block Diagram INTERNAL BUS M68HC08 CPU PTA7/ADC7‡ PTA6/ADC6‡ CPU ARITHMETIC/LOGIC 10-BIT ANALOG-TO-DIGITAL PTA5/ADC5‡ REGISTERS UNIT (ALU) CONVERTER MODULE DDRA PORTA PPTTAA43//AADDCC43‡‡ CONTROL AND STATUS REGISTERS — 96 BYTES PTA2/ADC2‡ TIMEBASE MODULE PTA1/ADC1‡ USER FLASH — (SEE TABLE) PTA0/ADC0‡ 2-CHANNEL TIMER INTERFACE USER RAM — (SEE TABLE) PTB7/T2CH1 MODULE 1 PTB6/T2CH0 MONITOR ROM — 959 BYTES PTB5/T1CH1 USER FLASH VECTOR SPACE — 48 BYTES 2-CHANNEML OTIDMUELRE I2NTERFACE DDRB PORTB PPTTBB34//RT1xCDH†0 PTB2/TxD† PTB1/SCL† OSCILLATORS AND SERIAL COMMUNICATIONS PTB0/SDA† CLOCK GENERATOR MODULE INTERFACE MODULE 1 INTERNAL OSCILLATOR PTC7/SCRxD† RC OSCILLATOR MULTI-MASTER IIC (SMBUS) PTC6/SCTxD† OSC1 INTERFACE MODULE PTC5/SPSCK CGMOXSFCC2 PHXA-TSAEL- LOOSCCKILELDA TLOOORP SERIAL COMMUNICATIONS DDRC PORTC PPTTCC43//SMSOSI PTC2/MISO INTERFACE MODULE 2 PTC1# (WITH INFRARED SYSTEM INTEGRATION MODULATOR/DEMODULATOR) PTC0/IRQ2 **# *RST MODULE PTD7/KBI7*** SERIAL PERIPHERAL *IRQ1 EXTERNAL INTERRUPT PTD6/KBI6*** INTERFACE MODULE **IRQ2 MODULE PTD5/KBI5*** COMPUTER OPERATING KEYBOARD INTERRUPT DDRD PORTD PPTTDD43//KKBBII43****** PROPERLY MODULE MODULE PTD2/KBI2*** PTD1/KBI1*** PTD0/KBI0*** POWER-ON RESET LOW-VOLTAGE INHIBIT MODULE MODULE VDD VDDA *Pin contains integrated pullup device. VSS **Pin contains configurable pullup device. VSSA POWER ***Pin contains integrated pullup device when configured as KBI. †Pin is open-drain when configured as output. VREG ‡LED direct sink pin. VREFH #Pin not bonded on 42-pin SDIP. ADC REFERENCE VREFL . USER RAM USER FLASH DEVICE (bytes) (bytes) MC68HC908AP64 2,048 62,368 MC68HC908AP32 2,048 32,768 MC68HC908AP16 1,024 16,384 MC68HC908AP8 1,024 8,192 Figure 1-1. MC68HC908AP64 Block Diagram MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 21

General Description 1.4 Pin Assignment 1 H 0 1 2 3 4 5 6 7 C 2C BI BI BI BI BI BI BI BI F T K K K K K K K K MX B7/ D0/ D1/ D2/ DA SA D3/ D4/ D5/ D6/ D7/ G T T T T D S T T T T T C P P P P V V P P P P P 8 7 4 3 7 6 5 4 3 2 1 0 9 8 PTB6/T2CH0 1 4 4 4 4 4 4 4 4 3 3 36 VREFH VREG 2 35 VREFL PTB5/T1CH1 3 34 NC VDD 4 33 NC OSC1 5 32 PTA0/ADC0 OSC2 6 31 NC VSS 7 30 PTA1/ADC1 PTB4/T1CH0 8 29 PTA2/ADC2 IRQ1 9 28 PTA3/ADC3 PTB3/RxD 10 27 PTA4/ADC4 RST 11 26 PTA5/ADC5 PTB2/TxD 12 4 5 6 7 8 9 0 1 2 3 25 PTA6/ADC6 1 1 1 1 1 1 2 2 2 2 3 4 1 2 PTB1/SCL PTB0/SDA TC7/SCRxD TC6/SCTxD TC5/SPSCK PTC4/SS PTC3/MOSI PTC2/MISO PTC1 PTC0/IRQ2 PTA7/ADC7 NC P P P NC: No connection Figure 1-2. 48-Pin LQFP Pin Assignments MC68HC908AP Family Data Sheet, Rev. 4 22 Freescale Semiconductor

Pin Assignment 1 H C 2C BI0 BI1 BI2 BI3 BI4 BI5 BI6 F T K K K K K K K MX B7/ D0/ D1/ D2/ DA SA D3/ D4/ D5/ D6/ G T T T T D S T T T T C P P P P V V P P P P 4 4 4 3 3 2 1 0 9 8 7 6 5 PTB6/T2CH0 1 4 4 4 4 3 3 3 3 3 33 PTD7/KBI7 VREG 2 32 VREFH PTB5/T1CH1 3 31 VREFL VDD 4 30 PTA0/ADC0 OSC1 5 29 PTA1/ADC1 OSC2 6 28 PTA2/ADC2 VSS 7 27 PTA3/ADC3 PTB4/T1CH0 8 26 PTA4/ADC4 IRQ1 9 25 PTA5/ADC5 PTB3/RxD 10 24 PTA6/ADC6 RST 11 3 4 5 6 7 8 9 0 1 23 PTA7/ADC7 1 1 1 1 1 1 1 2 2 2 2 1 2 PTB2/TxD PTB1/SCL PTB0/SDA TC7/SCRxD TC6/SCTxD TC5/SPSCK PTC4/SS PTC3/MOSI PTC2/MISO PTC1 PTC0/IRQ2 P P P Figure 1-3. 44-Pin QFP Pin Assignments MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 23

General Description PTD2/KBI2 1 42 VDDA PTD1/KBI1 2 41 VSSA PTD0/KBI0 3 40 PTD3/KBI3 PTB7/T2CH1 4 39 PTD4/KBI4 CGMXFC 5 38 PTD5/KBI5 PTB6/T2CH0 6 37 PTD6/KBI6 VREG 7 36 PTD7/KBI7 PTB5/T1CH1 8 35 VREFH VDD 9 34 VREFL OSC1 10 33 PTA0/ADC0 OSC2 11 32 PTA1/ADC1 VSS 12 31 PTA2/ADC2 PTB4/T1CH0 13 30 PTA3/ADC3 IRQ1 14 29 PTA4/ADC4 PTB3/RxD 15 28 PTA5/ADC5 RST 16 27 PTA6/ADC6 PTB2/TxD 17 26 PTA7/ADC7 PTB1/SCL 18 25 PTC2/MISO PTB0/SDA 19 24 PTC3/MOSI PTC7/SCRxD 20 23 PTC4/SS PTC6/SCTxD 21 22 PTC5/SPSCK Pins not available on 42-pin package Internal connection PTC0/IRQ2 Unconnected PTC1 Unconnected Figure 1-4. 42-Pin SDIP Pin Assignment MC68HC908AP Family Data Sheet, Rev. 4 24 Freescale Semiconductor

Pin Functions 1.5 Pin Functions Description of the pin functions are provided in Table 1-2. Table 1-2. Pin Functions VOLTAGE PIN NAME PIN DESCRIPTION IN/OUT LEVEL 4.5 to 5.5 VDD Power supply. In or 2.7 to 3.3 VSS Power supply ground. Out 0V VDDA Power supply for analog circuits. In VDD VSSA Power supply ground for analog circuits. Out VSS VREFH ADC input reference high. In VDDA VREFL ADC input reference low. Out VSSA Internal (2.5V) regulator output. VREG Require external capacitors for decoupling. Out 2.5V(1) Reset input, active low; with internal pullup and schmitt RST trigger input. In VDD External IRQ1 pin; with internal pullup and schmitt trigger input. In VDD IRQ1 Used for mode entry selection. In VDD to VTST OSC1 Crystal or RC oscillator input. In VREG Crystal OSC option: crystal oscillator output; inverted OSC1. Out VREG OSC2 RC OSC option: bus clock output. Out VREG Internal OSC option: bus clock output. Out VREG CGMXFC CGM external filter capacitor connection. In/Out Analog 8-bit general purpose I/O port. In/Out VDD PTA0/ADC0 : Pins as ADC inputs, ADC0–ADC7. In VREFH PTA7/ADC7 Each pin has high current sink for LED. Out VDD MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 25

General Description Table 1-2. Pin Functions VOLTAGE PIN NAME PIN DESCRIPTION IN/OUT LEVEL 8-bit general purpose I/O port; PTB0–PTB3 are open drain when configured as output. PTB4–PTB7 have schmitt trigger inputs. In/Out VDD PTB0 as SDA of MMIIC. In/Out VDD PTB0/SDA PTB1 as SCL of MMIIC. In/Out VDD PTB1/SCL PTB2/TxD PTB2 as TxD of SCI; open drain output. Out VDD PTB3/RxD PTB4/T1CH0 PTB3 as RxD of SCI. In VDD PTB5/T1CH1 PTB6/T2CH0 PTB4 as T1CH0 of TIM1. In/Out VDD PTB7/T2CH1 PTB5 as T1CH1 of TIM1. In/Out VDD PTB6 as T2CH0 of TIM2. In/Out VDD PTB7 as T2CH1 of TIM2. In/Out VDD 8-bit general purpose I/O port; PTC6 and PTC7 are open drain when configured as output. In/Out VDD PTC0 is shared withIRQ2 and has schmitt trigger input. In VDD PTC0/IRQ2 PTC1 PTC2 as MISO of SPI. In VDD PTC2/MISO PTC3/MOSI PTC3 as MOSI of SPI. Out VDD PTC4/SS PTC5/SPSCK PTC4 asSS of SPI. In VDD PTC6/SCTxD PTC7/SCRxD PTC5 as SPSCK of SPI. In/Out VDD PTC6 as SCTxD of IRSCI; open drain output. Out VDD PTC7 as SCRxD of IRSCI. In VDD PTD0/KBI0 8-bit general purpose I/O port with schmitt trigger inputs. In/Out VDD : PTD7/KBI7 Pins as keyboard interrupts (with pullup), KBI0–KBI7. In VDD 1. SeeChapter 22 Electrical Specifications for V tolerance. REG 1.6 Power Supply Bypassing (VDD, VDDA, VSS, VSSA) V and V are the power supply and ground pins, the MCU operates from a single power supply DD SS together with an on chip voltage regulator. FastsignaltransitionsonMCUpinsplacehigh.short-durationcurrentdemandsonthepowersupply.To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-5 shows. Place the bypass capacitors as close to the MCU power pins as possible. Use high-frequency-response ceramic capacitor for C , C are optional bulk current bypass BYPASS BULK capacitors for use in applications that require the port pins to source high current level. MC68HC908AP Family Data Sheet, Rev. 4 26 Freescale Semiconductor

Regulator Power Supply Configuration (VREG) V and V are the power supply and ground pins for the analog circuits of the MCU. These pins DDA SSA should be decoupled as per the digital power supply pins. MCU V V V V DD SS DDA SSA C1(a) C1(b) 0.1µF 0.1µF + + C2(a) C2(b) V V DD DD NOTE: Component values shown represent typical applications. Figure 1-5. Power Supply Bypassing 1.7 Regulator Power Supply Configuration (VREG) V istheoutputfromtheon-chipregulator.Allinternallogics,exceptfortheI/Opads,arepoweredby REG V output.V requiresanexternalceramicbypasscapacitorof100nFasFigure 1-6shows.Place REG REG the bypass capacitor as close to the V pin as possible. REG MCU V V REG SS C VREGBYPASS 100 nF Figure 1-6. Regulator Power Supply Bypassing MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 27

General Description MC68HC908AP Family Data Sheet, Rev. 4 28 Freescale Semiconductor

Chapter 2 Memory 2.1 Introduction The CPU08 can address 64k-bytes of memory space. The memory map, shown in Figure 2-1, includes: • 62,368 bytes of user FLASH — MC68HC908AP64 32,768 bytes of user FLASH — MC68HC908AP32 16,384 bytes of user FLASH — MC68HC908AP16 8,192 bytes of user FLASH — MC68HC908AP8 • 2,048 bytes of RAM — MC68HC908AP64 and MC68HC908AP32 1,024 bytes of RAM — MC68HC908AP16 and MC68HC908AP8 • 48 bytes of user-defined vectors • 959 bytes of monitor ROM 2.2 Input/Output (I/O) Section Most of the control, status, and data registers are in the zero page area of $0000–$005F. Additional I/O registers have these addresses: • $FE00; SIM break status register, SBSR • $FE01; SIM reset status register, SRSR • $FE02; Reserved • $FE03; SIM break flag control register, SBFCR • $FE04; interrupt status register 1, INT1 • $FE05; interrupt status register 2, INT2 • $FE06; interrupt status register 3, INT3 • $FE07; Reserved • $FE08; FLASH control register, FLCR • $FE09; FLASH block protect register, FLBPR • $FE0A; Reserved • $FE0B; Reserved • $FE0C; Break address register high, BRKH • $FE0D; Break address register low, BRKL • $FE0E; Break status and control register, BRKSCR • $FE0F; LVI Status register, LVISR • $FFCF; Mask option register, MOR (FLASH register) • $FFFF; COP control register, COPCTL 2.3 Monitor ROM The 959 bytes at addresses $FC00–$FDFF and $FE10–$FFCE are reserved ROM addresses that contain the instructions for the monitor functions. (See Chapter 8 Monitor ROM (MON).) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 29

Memory $0000 I/O Registers ↓ MC68HC908AP32 MC68HC908AP16 MC68HC908AP8 96 Bytes $005F $0060 $0060 RAM $0060 RAM $0060 RAM RAM 1,024 Bytes 1,024 Bytes ↓ 2,048 Bytes ↓ $045F $045F 2,048 Bytes Unimplemented Unimplemented (MC68HC908AP64) $085F $085F 1,024 Bytes 1,024 Bytes $0860 $0860 $0860 FLASH Memory $0860 FLASH Memory ↓ 8,192 Bytes $285F 16,384 Bytes $2860 FLASH Memory $485F ↓ 32,768 Bytes $4860 FLASH Memory $885F ↓ 62,368 Bytes $8860 Unimplemented (MC68HC908AP64) ↓ Unimplemented 54,176 Bytes ↓ 45,984 Bytes Unimplemented ↓ 29,600 Bytes $FBFF $FBFF $FBFF $FBFF $FC00 Monitor ROM 2 ↓ 512 Bytes $FDFF $FE00 SIM Break Status Register $FE01 SIM Reset Status Register $FE02 Reserved $FE03 SIM Break Flag Control Register $FE04 Interrupt Status Register 1 $FE05 Interrupt Status Register 2 $FE06 Interrupt Status Register 3 $FE07 Reserved $FE08 FLASH Control Register $FE09 FLASH Block Protect Register $FE0A Reserved $FE0B Reserved $FE0C Break Address Register High $FE0D Break Address Register Low $FE0E Break Status and Control Register $FE0F LVI Status Register $FE10 Monitor ROM 1 ↓ 447 Bytes $FFCE $FFCF Mask Option Register $FFD0 FLASH Vectors ↓ 48 Bytes $FFFF Figure 2-1. Memory Map MC68HC908AP Family Data Sheet, Rev. 4 30 Freescale Semiconductor

Monitor ROM Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: Port A Data Register PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 $0000 Write: (PTA) Reset: Unaffected byreset Read: Port B Data Register PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 $0001 Write: (PTB) Reset: Unaffected byreset Read: PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 $0002 Port C Data Register (PTC) Write: Reset: Unaffected byreset Read: PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 $0003 Port D Data Register (PTD) Write: Reset: Unaffected by reset Read: Data Direction Register A DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 $0004 Write: (DDRA) Reset: 0 0 0 0 0 0 0 0 Read: Data Direction Register B DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 $0005 Write: (DDRB) Reset: 0 0 0 0 0 0 0 0 Read: Data Direction Register C DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 $0006 Write: (DDRC) Reset: 0 0 0 0 0 0 0 0 Read: Data Direction Register D DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 $0007 Write: (DDRD) Reset: 0 0 0 0 0 0 0 0 Read: Unimplemented $0008 Write: Reset: Read: $0009 Unimplemented Write: Reset: Read: $000A Unimplemented Write: Reset: Read: $000B Unimplemented Write: Reset: Read: Port-A LED Control LEDA7 LEDA6 LEDA5 LEDA4 LEDA3 LEDA2 LEDA1 LEDA0 $000C Register Write: (LEDA) Reset: 0 0 0 0 0 0 0 0 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 9) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 31

Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: $000D Unimplemented Write: Reset: Read: $000E Unimplemented Write: Reset: Read: $000F Unimplemented Write: Reset: Read: SPI Control Register SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE $0010 Write: (SPCR) Reset: 0 0 1 0 1 0 0 0 Read: SPRF OVRF MODF SPTE SPI Status and Control ERRIE MODFEN SPR1 SPR0 $0011 Register Write: (SPSCR) Reset: 0 0 0 0 1 0 0 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 SPI Data Register $0012 Write: T7 T6 T5 T4 T3 T2 T1 T0 (SPDR) Reset: Unaffected by reset Read: SCI Control Register 1 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY $0013 Write: (SCC1) Reset: 0 0 0 0 0 0 0 0 Read: SCI Control Register 2 SCTIE TCIE SCRIE ILIE TE RE RWU SBK $0014 Write: (SCC2) Reset: 0 0 0 0 0 0 0 0 Read: R8 SCI Control Register 3 T8 DMARE DMATE ORIE NEIE FEIE PEIE $0015 Write: (SCC3) Reset: U U 0 0 0 0 0 0 Read: SCTE TC SCRF IDLE OR NF FE PE $0016 SCIStatusRegister1(SCS1) Write: Reset: 1 1 0 0 0 0 0 0 Read: 0 0 0 0 0 0 BKF RPF $0017 SCIStatusRegister2(SCS2) Write: Reset: 0 0 0 0 0 0 0 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 SCI Data Register $0018 Write: T7 T6 T5 T4 T3 T2 T1 T0 (SCDR) Reset: Unaffected by reset Read: 0 0 SCI Baud Rate Register SCP1 SCP0 R SCR2 SCR1 SCR0 $0019 Write: (SCBR) Reset: 0 0 0 0 0 0 0 0 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 9) MC68HC908AP Family Data Sheet, Rev. 4 32 Freescale Semiconductor

Monitor ROM Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 KEYF 0 Keyboard Status and Control IMASK MODE $001A Register Write: ACK (KBSCR) Reset: 0 0 0 0 0 0 0 0 Read: Keyboard Interrupt KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 $001B Enable Register Write: (KBIER) Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 IRQ2F 0 IRQ2StatusandControlReg- PUC0ENB IMASK2 MODE2 $001C ister Write: ACK2 (INTSCR2) Reset: 0 0 0 0 0 0 0 0 Read: STOP_ STOP_ STOP_ 0 0 Configuration Register 2 OSCCLK1 OSCCLK0 SCIBDSRC $001D Write: ICLKDIS RCLKEN XCLKEN (CONFIG2)† Reset: 0 0 0 0 0 0 0 0 † One-time writable register after each reset. Read: 0 0 0 0 IRQ1F 0 IRQ1StatusandControlReg- IMASK1 MODE1 $001E ister Write: ACK1 (INTSCR1) Reset: 0 0 0 0 0 0 0 0 Read: Configuration Register 1 COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD $001F Write: (CONFIG1)† Reset: 0 0 0 0 0 0 0 0 † One-time writable register after each reset. Read: TOF 0 0 Timer 1 Status and TOIE TSTOP PS2 PS1 PS0 $0020 Control Register Write: 0 TRST (T1SC) Reset: 0 0 1 0 0 0 0 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Timer 1 Counter $0021 Register High Write: (T1CNTH) Reset: 0 0 0 0 0 0 0 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Timer 1 Counter $0022 Register Low Write: (T1CNTL) Reset: 0 0 0 0 0 0 0 0 Read: Timer1CounterModuloReg- Bit 15 14 13 12 11 10 9 Bit 8 $0023 ister High Write: (T1MODH) Reset: 1 1 1 1 1 1 1 1 Read: Timer 1 Counter Modulo Bit 7 6 5 4 3 2 1 Bit 0 $0024 Register Low Write: (T1MODL) Reset: 1 1 1 1 1 1 1 1 Read: CH0F Timer1Channel0Statusand CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX $0025 Write: 0 Control Register (T1SC0) Reset: 0 0 0 0 0 0 0 0 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 9) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 33

Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: Timer 1 Channel 0 Bit 15 14 13 12 11 10 9 Bit 8 $0026 Register High Write: (T1CH0H) Reset: Indeterminate after reset Read: Timer 1 Channel 0 Bit 7 6 5 4 3 2 1 Bit 0 $0027 Register Low Write: (T1CH0L) Reset: Indeterminate after reset Read: CH1F 0 Timer1Channel1Statusand CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX $0028 Write: 0 Control Register (T1SC1) Reset: 0 0 0 0 0 0 0 0 Read: Timer 1 Channel 1 Bit 15 14 13 12 11 10 9 Bit 8 $0029 Register High Write: (T1CH1H) Reset: Indeterminate after reset Read: Timer 1 Channel 1 Bit 7 6 5 4 3 2 1 Bit 0 $002A Register Low Write: (T1CH1L) Reset: Indeterminate after reset Read: TOF 0 0 Timer 2 Status and TOIE TSTOP PS2 PS1 PS0 $002B Control Register Write: 0 TRST (T2SC) Reset: 0 0 1 0 0 0 0 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Timer 2 Counter $002C Register High Write: (T2CNTH) Reset: 0 0 0 0 0 0 0 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Timer 2 Counter $002D Register Low Write: (T2CNTL) Reset: 0 0 0 0 0 0 0 0 Read: Timer2CounterModuloReg- Bit 15 14 13 12 11 10 9 Bit 8 $002E ister High Write: (T2MODH) Reset: 1 1 1 1 1 1 1 1 Read: Timer 2 Counter Modulo Bit 7 6 5 4 3 2 1 Bit 0 $002F Register Low Write: (T2MODL) Reset: 1 1 1 1 1 1 1 1 Read: CH0F Timer2Channel0Statusand CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX $0030 Write: 0 Control Register (T2SC0) Reset: 0 0 0 0 0 0 0 0 Read: Timer 2 Channel 0 Bit 15 14 13 12 11 10 9 Bit 8 $0031 Register High Write: (T2CH0H) Reset: Indeterminate after reset Read: Timer 2 Channel 0 Bit 7 6 5 4 3 2 1 Bit 0 $0032 Register Low Write: (T2CH0L) Reset: Indeterminate after reset U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 9) MC68HC908AP Family Data Sheet, Rev. 4 34 Freescale Semiconductor

Monitor ROM Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: CH1F 0 Timer2Channel1Statusand CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX $0033 Write: 0 Control Register (T2SC1) Reset: 0 0 0 0 0 0 0 0 Read: Timer 2 Channel 1 Bit 15 14 13 12 11 10 9 Bit 8 $0034 Register High Write: (T2CH1H) Reset: Indeterminate after reset Read: Timer 2 Channel 1 Bit 7 6 5 4 3 2 1 Bit 0 $0035 Register Low Write: (T2CH1L) Reset: Indeterminate after reset Read: PLLF PLLIE PLLON BCS PRE1 PRE0 VPR1 VPR0 $0036 PLL Control Register (PCTL) Write: Reset: 0 0 1 0 0 0 0 0 Read: LOCK 0 0 0 0 PLL Bandwidth Control Reg- AUTO ACQ R $0037 ister Write: (PBWC) Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 0 PLL Multiplier Select MUL11 MUL10 MUL9 MUL8 $0038 Register High Write: (PMSH) Reset: 0 0 0 0 0 0 0 0 Read: PLL Multiplier Select MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 $0039 Register Low Write: (PMSL) Reset: 0 1 0 0 0 0 0 0 Read: PLL VCO Range Select VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0 $003A Register Write: (PMRS) Reset: 0 1 0 0 0 0 0 0 Read: 0 0 0 0 PLL Reference Divider RDS3 RDS2 RDS1 RDS0 $003B Select Register Write: (PMDS) Reset: 0 0 0 0 0 0 0 1 Read: $003C Unimplemented Write: Reset: Read: $003D Unimplemented Write: Reset: Read: $003E Unimplemented Write: Reset: Read: $003F Unimplemented Write: Reset: U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 35

Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 IRSCI Control Register 1 LOOPS ENSCI M WAKE ILTY PEN PTY $0040 Write: (IRSCC1) Reset: 0 0 0 0 0 0 0 0 Read: IRSCI Control Register 2 SCTIE TCIE SCRIE ILIE TE RE RWU SBK $0041 Write: (IRSCC2) Reset: 0 0 0 0 0 0 0 0 Read: R8 IRSCI Control Register 3 T8 DMARE DMATE ORIE NEIE FEIE PEIE $0042 Write: (IRSCC3) Reset: U U 0 0 0 0 0 0 Read: SCTE TC SCRF IDLE OR NF FE PE IRSCI Status Register 1 $0043 Write: (IRSCS1) Reset: 1 1 0 0 0 0 0 0 Read: BKF RPF IRSCI Status Register 2 $0044 Write: (IRSCS2) Reset: 0 0 0 0 0 0 0 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 IRSCI Data Register $0045 Write: T7 T6 T5 T4 T3 T2 T1 T0 (IRSCDR) Reset: Unaffected by reset Read: 0 IRSCI Baud Rate Register CKS SCP1 SCP0 R SCR2 SCR1 SCR0 $0046 Write: (IRSCBR) Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 IRSCI Infrared Control R R TNP1 TNP0 IREN $0047 Register Write: (IRSCIRCR) Reset: 0 0 0 0 0 0 0 0 MMIIC Address Register Read: MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD $0048 (MMADR) Write: Reset: 1 0 1 0 0 0 0 0 Read: 0 0 MMCRCBY 0 MMIIC Control Register 1 MMEN MMIEN MMTXAK REPSEN $0049 Write: MMCLRBB TE (MMCR1) Reset: 0 0 0 0 0 0 0 0 MMIIC Control Register 2 Read: MMALIF MMNAKIF MMBB 0 0 MMAST MMRW MMCRCEF $004A (MMCR2) Write: 0 0 Reset: 0 0 0 0 0 0 0 Unaffected MMIIC Status Register Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK MMCRCBF MMTXBE MMRXBF $004B (MMSR) Write: 0 0 Reset: 0 0 0 0 1 0 1 0 Read: MMIIC Data Transmit MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0 $004C Register Write: (MMDTR) Reset: 0 0 0 0 0 0 0 0 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 9) MC68HC908AP Family Data Sheet, Rev. 4 36 Freescale Semiconductor

Monitor ROM Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0 MMIIC Data Receive $004D Register Write: (MMDRR) Reset: 0 0 0 0 0 0 0 0 MMIIC CRC Data Register Read: MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0 $004E (MMCRDR) Write: Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 0 0 MMIIC Frequency Divider MMBR2 MMBR1 MMBR0 $004F Register Write: (MMFDR) Reset: 0 0 0 0 0 1 0 0 Read: R R R R R R R R $0050 Reserved Write: Reset: Read: TBIF 0 Timebase Control Register TBR2 TBR1 TBR0 TBIE TBON R $0051 (TBCR) Write: TACK Reset: 0 0 0 0 0 0 0 0 Read: $0052 Unimplemented Write: Reset: Read: $0053 Unimplemented Write: Reset: Read: $0054 Unimplemented Write: Reset: Read: $0055 Unimplemented Write: Reset: Read: $0056 Unimplemented Write: Reset: Read: COCO ADC Status and Control AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 $0057 Register Write: (ADSCR) Reset: 0 0 0 1 1 1 1 1 Read: 0 0 ADC Clock Control Register ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 $0058 Write: R (ADICLK) Reset: 0 0 0 0 0 0 0 0 Read: ADx ADx ADx ADx ADx ADx ADx ADx ADC Data Register High 0 $0059 Write: R R R R R R R R (ADRH0) Reset: 0 0 0 0 0 0 0 0 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 9) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 37

Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 ADC Data Register Low 0 Read: ADx ADx ADx ADx ADx ADx ADx ADx $005A (ADRL0) Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 ADC Data Register Low 1 Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 $005B (ADRL1) Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 $005C ADC Data Register Low 2 Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 (ADRL2) Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 ADC Data Register Low 3 Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 $005D (ADRL3) Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 Read: ADC Auto-scan Control AUTO1 AUTO0 ASCAN $005E Register Write: (ADASCR) Reset: 0 0 0 0 0 0 0 0 Read: $005F Unimplemented Write: Reset: Read: SBSW SIM Break Status Register R R R R R R R $FE00 Write: Note (SBSR) Reset: 0 Note: Writing a logic 0 clears SBSW. Read: POR PIN COP ILOP ILAD MODRST LVI 0 SIM Reset Status Register $FE01 Write: (SRSR) Reset: 1 0 0 0 0 0 0 0 Read: R R R R R R R R $FE02 Reserved Write: Reset: Read: SIM Break Flag Control Reg- BCFE R R R R R R R $FE03 ister Write: (SBFCR) Reset: 0 Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Interrupt Status Register1 $FE04 Write: R R R R R R R R (INT1) Reset: 0 0 0 0 0 0 0 0 Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Interrupt Status Register2 $FE05 Write: R R R R R R R R (INT2) Reset: 0 0 0 0 0 0 0 0 U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 9) MC68HC908AP Family Data Sheet, Rev. 4 38 Freescale Semiconductor

Monitor ROM Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 IF21 IF20 IF19 IF18 IF17 IF16 IF15 Interrupt Status Register3 $FE06 Write: R R R R R R R R (INT3) Reset: 0 0 0 0 0 0 0 0 Read: R R R R R R R R $FE07 Reserved Write: Reset: Read: 0 0 0 0 FLASH Control Register HVEN MASS ERASE PGM $FE08 Write: (FLCR) Reset: 0 0 0 0 0 0 0 0 Read: FLASH Block Protect BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 $FE09 Register Write: (FLBPR) Reset: 0 0 0 0 0 0 0 0 Read: R R R R R R R R $FE0A Reserved Write: Reset: Read: R R R R R R R R $FE0B Reserved Write: Reset: Read: Break Address Bit 15 14 13 12 11 10 9 Bit 8 $FE0C Register High Write: (BRKH) Reset: 0 0 0 0 0 0 0 0 Read: Break Address Bit 7 6 5 4 3 2 1 Bit 0 $FE0D Register Low Write: (BRKL) Reset: 0 0 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 Break Status and Control BRKE BRKA $FE0E Register Read: (BRKSCR) Write: 0 0 0 0 0 0 0 0 Reset: LVIOUT 0 0 0 0 0 0 0 $FE0F LVI Status Register (LVISR) Read: Write: 0 0 0 0 0 0 0 0 Read: Mask Option Register OSCSEL1 OSCSEL0 R R R R R R $FFCF Write: (MOR)# Erased: 1 1 1 1 1 1 1 1 Reset: U U U U U U U U Read: Low byte of reset vector COP Control Register $FFFF Write: Writing clears COP counter (any value) (COPCTL) Reset: Unaffected by reset # MOR is a non-volatile FLASH register; write by programming. U=Unaffected X=Indeterminate =Unimplemented R =Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 39

Memory Table 2-1. Vector Addresses Priority INT Flag Address Vector Lowest $FFD0 Reserved — $FFD1 Reserved $FFD2 TBM Vector (High) IF21 $FFD3 TBM Vector (Low) $FFD4 SCI2 (IRSCI) Transmit Vector (High) IF20 $FFD5 SCI2 (IRSCI) Transmit Vector (Low) $FFD6 SCI2 (IRSCI) Receive Vector (High) IF19 $FFD7 SCI2 (IRSCI) Receive Vector (Low) $FFD8 SCI2 (IRSCI) Error Vector (High) IF18 $FFD9 SCI2 (IRSCI) Error Vector (Low) $FFDA SPI Transmit Vector (High) IF17 $FFDB SPI Transmit Vector (Low) $FFDC SPI Receive Vector (High) IF16 $FFDD SPI Receive Vector (Low) $FFDE ADC Conversion Complete Vector (High) IF15 $FFDF ADC Conversion Complete Vector (Low) $FFE0 Keyboard Vector (High) IF14 $FFE1 Keyboard Vector (Low) $FFE2 SCI Transmit Vector (High) IF13 $FFE3 SCI Transmit Vector (Low) $FFE4 SCI Receive Vector (High) IF12 $FFE5 SCI Receive Vector (Low) $FFE6 SCI Error Vector (High) IF11 $FFE7 SCI Error Vector (Low) $FFE8 MMIIC Interrupt Vector (High) IF10 $FFE9 MMIIC Interrupt Vector (Low) $FFEA TIM2 Overflow Vector (High) IF9 $FFEB TIM2 Overflow Vector (Low) MC68HC908AP Family Data Sheet, Rev. 4 40 Freescale Semiconductor

Random-Access Memory (RAM) Table 2-1. Vector Addresses (Continued) Priority INT Flag Address Vector $FFEC TIM2 Channel 1 Vector (High) IF8 $FFED TIM2 Channel 1 Vector (Low) $FFEE TIM2 Channel 0 Vector (High) IF7 $FFEF TIM2 Channel 0 Vector (Low) $FFF0 TIM1 Overflow Vector (High) IF6 $FFF1 TIM1 Overflow Vector (Low) $FFF2 TIM1 Channel 1 Vector (High) IF5 $FFF3 TIM1 Channel 1 Vector (Low) $FFF4 TIM1 Channel 0 Vector (High) IF4 $FFF5 TIM1 Channel 0 Vector (Low) $FFF6 PLL Vector (High) IF3 $FFF7 PLL Vector (Low) $FFF8 IRQ2 Vector (High) IF2 $FFF9 IRQ2Vector (Low) $FFFA IRQ1 Vector (High) IF1 $FFFB IRQ1 Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — Highest $FFFF Reset Vector (Low) 2.4 Random-Access Memory (RAM) The following table shows the RAM size and address range: Device RAM Size (Bytes) Memory Address Range MC68HC908AP64 2,048 $0060–$085F MC68HC908AP32 MC68HC908AP16 1,024 $0060–$045F MC68HC908AP8 ThelocationofthestackRAMisprogrammable.The16-bitstackpointerallowsthestacktobeanywhere in the 64k-byte memory space. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 41

Memory NOTE For correct operation, the stack pointer must point only to RAM locations. Withinpagezeroare160bytesofRAM.BecausethelocationofthestackRAMisprogrammable,allpage zeroRAMlocationscanbeusedforI/Ocontrolanduserdataorcode.Whenthestackpointerismoved fromitsresetlocationat$00FF,directaddressingmodeinstructionscanaccessefficientlyallpagezero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE For M6805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Becarefulwhenusingnestedsubroutines.TheCPUmayoverwritedatain the RAM during a subroutine or during the interrupt stacking operation. 2.5 FLASH Memory This sub-section describes the operation of the embedded FLASH memory. This memory can be read, programmed,anderasedfromasingleexternalsupply.Theprogramanderaseoperationsareenabled through the use of an internal charge pump. The following table shows the FLASH memory size and address range: Device FLASH Size (Bytes) Memory Address Range MC68HC908AP64 62,368 $0860–$FBFF MC68HC908AP32 32,768 $0860–$885F MC68HC908AP16 16,384 $0860–$485F MC68HC908AP8 8,192 $0860–$285F 2.5.1 Functional Description The FLASH memory consists of an array for user memory plus a block of 48 bytes for user interrupt vectors and one byte for the mask option register. An erased bit reads as logic 1 and a programmed bit readsasalogic0.TheFLASHmemorypagesizeisdefinedas512bytes,andistheminimumsizethat can be erased in a page erase operation. Program and erase operations are facilitated through control bits in FLASH control register (FLCR). The address ranges for the FLASH memory are: • $0860–$FBFF; user memory, 62,368 / 32,768 / 16,384 / 8,192 bytes • $FFD0–$FFFF; user interrupt vectors, 48 bytes • $FFCF; mask option register Programming tools are available from Freescale. Contact your local Freescale representative for more information. NOTE A security feature prevents viewing of the FLASH contents.(1) MC68HC908AP Family Data Sheet, Rev. 4 42 Freescale Semiconductor

FLASH Memory 2.5.2 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operation. Address: $FE08 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 HVEN MASS ERASE PGM Write: Reset: 0 0 0 0 0 0 0 0 Figure 2-3. FLASH Control Register (FLCR) HVEN — High Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS — Mass Erase Control Bit Thisread/writebitconfiguresthememoryformasseraseoperationorpageeraseoperationwhenthe ERASE bit is set. 1 = Mass erase operation selected 0 = Page erase operation selected ERASE — Erase Control Bit Thisread/writebitconfiguresthememoryforeraseoperation.ERASEisinterlockedwiththePGMbit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation not selected PGM — Program Control Bit Thisread/writebitconfiguresthememoryforprogramoperation.PGMisinterlockedwiththeERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation not selected 2.5.3 FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory. A page consists of 512 consecutive bytes starting from addresses $X000, $X200, $X400, $X600, $X800, $XA00, $XC00, or $XE00. The 48-byteuserinterruptvectorscannotbeerasedbythepageeraseoperationbecauseofsecurityreasons. Mass erase is required to erase this page. 1. Set the ERASE bit and clear the MASS bit in the FLASH control register. 2. Write any data to any FLASH location within the page address range desired. 3. Wait for a time, t (5 µs). nvs 4. Set the HVEN bit. 5. Wait for a time t (20 ms). erase 1.Nosecurityfeatureisabsolutelysecure.However,Freescale’sstrategyistomakereadingorcopyingtheFLASHdifficultfor unauthorized users. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 43

Memory 6. Clear the ERASE bit. 7. Wait for a time, t (5 µs). nvh 8. Clear the HVEN bit. 9. After time, t (1 µs), the memory can be accessed in read mode again. rcv NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 2.5.4 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Write any data to any FLASH location within the FLASH memory address range. 3. Wait for a time, t (5 µs). nvs 4. Set the HVEN bit. 5. Wait for a time t (200 ms). (See NOTE below.) me 6. Clear the ERASE bit. 7. Wait for a time, t (100 µs). nvh1 8. Clear the HVEN bit. 9. After time, t (1 µs), the memory can be accessed in read mode again. rcv NOTE Due to the relatively long mass erase time, user should take care in the code to prevent a COP reset from happening while the HVEN bit is set. Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 2.5.5 FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes startingfromaddresses$XX00,$XX40,$XX80or$XXC0.Usethefollowingproceduretoprogramarow of FLASH memory. (Figure 2-4 shows a flowchart of the programming algorithm.) 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Write any data to any FLASH location within the address range of the row to be programmed. 3. Wait for a time, t (5 µs). nvs 4. Set the HVEN bit. 5. Wait for a time, t (10 µs). pgs 6. Write data to the FLASH location to be programmed. 7. Wait for time, t (20 µs to 40 µs). prog 8. Repeat steps 6 and 7 until all bytes within the row are programmed. 9. Clear the PGM bit. MC68HC908AP Family Data Sheet, Rev. 4 44 Freescale Semiconductor

FLASH Memory 10. Wait for time, t (5 µs). nvh 11. Clear the HVEN bit. 12. After time, t (1 µs), the memory can be accessed in read mode again. rcv This program sequence is repeated throughout the memory until all data is programmed. NOTE The time between each FLASH address change (step 6 to step 6), or the timebetweenthelastFLASHaddressedprogrammedtoclearingthePGM bit (step 6 to step 9), must not exceed the maximum programming time, t max. prog NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. 2.5.6 FLASH Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application,provisionismadetoprotectpagesofmemoryfromunintentionaleraseorprogramoperations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program operations. NOTE Themaskoptionregister($FFCF)andthe48bytesofuserinterruptvectors ($FFD0–$FFFF) are always protected, regardless of the value in the FLASH block protect register. A mass erase is required to erase these locations. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 45

Memory 1 Set PGM bit Algorithm for programming a row (64 bytes) of FLASH memory 2 Write any data to any FLASH address within the row address range desired 3 Wait for a time, t nvs 4 Set HVEN bit 5 Wait for a time, t pgs 6 Write data to the FLASH address to be programmed 7 Wait for a time, t prog Completed Y programming this row? N 9 NOTE: Clear PGM bit The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed 10 Wait for a time, t to clearing PGM bit (step 6 to step 9) nvh must not exceed the maximum programming time, t max. PROG 11 Clear HVEN bit This row program algorithm assumes the row/s to be programmed are initially erased. 12 Wait for a time, t rcv End of Programming Figure 2-4. FLASH Programming Flowchart MC68HC908AP Family Data Sheet, Rev. 4 46 Freescale Semiconductor

FLASH Memory 2.5.7 FLASH Block Protect Register The FLASH block protect register is implemented as an 8-bit I/O register. The value in this register determines the starting address of the protected range within the FLASH memory. Address: $FE09 Bit 7 6 5 4 3 2 1 Bit 0 Read: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 2-5. FLASH Block Protect Register (FLBPR) BPR[7:0] — FLASH Block Protect Bits BPR[7:1] represent bits [15:9] of a 16-bit memory address. Bits [8:0] are logic 0’s. 16-bit memory address Start address of FLASH block protect 0 0 0 0 0 0 0 0 0 BPR[7:1] BPR0 is used only for BPR[7:0] = $FF, for no block protection. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. Withthismechanism,theprotectstartaddresscanbeX000,X200,X400,X0600,X800,XA00,XC00, or XE00 (at page boundaries — 512 bytes) within the FLASH memory. Examples of protect start address: Table 2-2 FLASH Block Protect Range BPR[7:0] Protected Range $00 to $09 The entire FLASH memory is protected. $0A or $0B $0A00 to $FFFF (0000 101x) $0C or $0D $0C00 to $FFFF (0000 110x) and so on... $FA or $FB $FA00 to $FFFF (1111 1101x) $FC or $FD or $FE $FFCF to $FFFF $FF The entire FLASH memory isNOT protected.(1) 1. Except for the mask option register ($FFCF) and the 48-byte user vectors ($FFD0–$FFFF). These FLASH locations are always protected. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 47

Memory MC68HC908AP Family Data Sheet, Rev. 4 48 Freescale Semiconductor

Chapter 3 Configuration & Mask Option Registers (CONFIG & MOR) 3.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option register, MOR. The configuration registers enable or disable these options: • Computer operating properly module (COP) • COP timeout period (218 – 24 or 213 – 24 ICLK cycles) • Low-voltage inhibit (LVI) on V DD • LVI on V REG • LVI module reset • LVI module in stop mode • STOP instruction • Stop mode recovery time (32 ICLK or 4096 ICLK cycles) • Oscillator (internal, RC, and crystal) during stop mode • Serial communications interface clock source (CGMXCLK or f ) BUS The mask option register selects one of the following oscillator options: • Internal oscillator • RC oscillator • Crystal oscillator Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Configuration Register 2 Read: STOP_ STOP_ STOP_ 0 0 OSCCLK1 OSCCLK0 SCIBDSRC $001D (CONFIG2)† Write: ICLKDIS RCLKEN XCLKEN Reset: 0 0 0 0 0 0 0 0 Read: Configuration Register 1 COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD $001F Write: (CONFIG1)† Reset: 0 0 0 0 0 0 0 0 Mask-Option-Register Read: OSCSEL1 OSCSEL0 R R R R R R $FFCF (MOR)# Write: Erased: 1 1 1 1 1 1 1 1 † One-time writable register after each reset. # MOR is a non-volatile FLASH register; write by programming. = Unimplemented R =Reserved Figure 3-1. CONFIG and MOR Registers Summary MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 49

Configuration & Mask Option Registers (CONFIG & MOR) 3.2 Functional Description The configuration registers and the mask option register are used in the initialization of various options. These two types of registers are configured differently: • Configuration registers — Write-once registers after reset • Mask option register — FLASH register (write by programming) Theconfiguration registerscanbewrittenonce after eachreset. Allof the configurationregisterbits are cleared during reset. Since the various options affect the operation of the MCU, it is recommended that these registers be written immediately after reset. The configuration registers are located at $001D and $001F. The configuration registers may be read at anytime. NOTE The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset,theCONFIGregistersdefaulttopredeterminedsettingsasshownin Figure 3-2 and Figure 3-3. The mask option register (MOR) is used for selecting one of the three clock options for the MCU. The MOR is a byte located in FLASH memory, and is written to by a FLASH programming routine. 3.3 Configuration Register 1 (CONFIG1) Address: $001F Bit 7 6 5 4 3 2 1 Bit 0 Read: COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD Write: Reset: 0 0 0 0 0 0 0 0 Figure 3-2. Configuration Register 1 (CONFIG1) COPRS — COP Rate Select Bit COPRSselectstheCOPtimeoutperiod.ResetclearsCOPRS.(SeeChapter19ComputerOperating Properly (COP).) 1 = COP time out period = 213 – 24 ICLK cycles 0 = COP time out period = 218 – 24 ICLK cycles LVISTOP — LVI Enable in Stop Mode Bit When the LVIPWRD or LVIREGD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. (See Chapter 20 Low-Voltage Inhibit (LVI).) 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode NOTE If LVISTOP=0, set LVIRSTD=1 before entering stop mode. LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. (See Chapter 20 Low-Voltage Inhibit (LVI).) 1 = LVI module resets disabled 0 = LVI module resets enabled MC68HC908AP Family Data Sheet, Rev. 4 50 Freescale Semiconductor

Configuration Register 1 (CONFIG1) LVIPWRD — V LVI Circuit Disable Bit DD LVIPWRD disables the V LVI circuit. (See Chapter 20 Low-Voltage Inhibit (LVI).) DD 1 = V LVI circuit disabled DD 0 = V LVI circuit enabled DD LVIREGD — V LVI Circuit Disable Bit REG LVIREGD disables the V LVI circuit. (See Chapter 20 Low-Voltage Inhibit (LVI).) REG 1 = V LVI circuit disabled REG 0 = V LVI circuit enabled REG NOTE If LVIPWRD=1 and LVIREGD=1, set LVIRSTD=1 before entering stop mode. SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK cycle delay. 1 = Stop mode recovery after 32 ICLK cycles 0 = Stop mode recovery after 4096 ICLK cycles NOTE Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal oscillator, do not set the SSREC bit. When the LVI is disabled in stop mode (LVISTOP=0), the system stabilization time for long stop recovery (4096 ICLK cycles) gives a delay longerthantheLVI’sturn-ontime.ThereisnoperiodwheretheMCUisnot protectedfromalowpowercondition.However,whenusingtheshortstop recovery configuration option, the 32 ICLK delay is less than the LVI’s turn-on time and there exists a period in start-up where the LVI is not protecting the MCU. STOP — STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. (See Chapter 19 Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 51

Configuration & Mask Option Registers (CONFIG & MOR) 3.4 Configuration Register 2 (CONFIG2) Address: $001D Bit 7 6 5 4 3 2 1 Bit 0 Read: STOP_ STOP_ STOP_ 0 0 SCIBD- OSCCLK1 OSCCLK0 Write: ICLKDIS RCLKEN XCLKEN SRC Reset: 0 0 0 0 0 0 0 0 Figure 3-3. Configuration Register 2 (CONFIG2) STOP_ICLKDIS — Internal Oscillator Stop Mode Disable STOP_ICLKDIS disables the internal oscillator during stop mode. Setting the STOP_ICLKDIS bit disables the oscillator during stop mode. (See Chapter 5 Oscillator (OSC).) Reset clears this bit. 1 = Internal oscillator disabled during stop mode 0 = Internal oscillator enabled to operate during stop mode STOP_RCLKEN — RC Oscillator Stop Mode Enable Bit STOP_RCLKEN enables the RC oscillator to continue operating during stop mode. Setting the STOP_RCLKENbitallowstheoscillatortooperatecontinuouslyevenduringstopmode.Thisisuseful for driving the timebase module to allow it to generate periodic wake up while in stop mode. (See Chapter 5 Oscillator (OSC).) Reset clears this bit. 1 = RC oscillator enabled to operate during stop mode 0 = RC oscillator disabled during stop mode STOP_XCLKEN — X-tal Oscillator Stop Mode Enable Bit STOP_XCLKEN enables the crystal (x-tal) oscillator to continue operating during stop mode. Setting theSTOP_XCLKENbitallowsthex-taloscillatortooperatecontinuouslyevenduringstopmode.This is useful for driving the timebase module to allow it to generate periodic wake up while in stop mode. (See Chapter 5 Oscillator (OSC).) Reset clears this bit. 1 = X-tal oscillator enabled to operate during stop mode 0 = X-tal oscillator disabled during stop mode OSCCLK1, OSCCLK0 — Oscillator Output Control Bits OSCCLK1andOSCCLK0selectwhichoscillatoroutputtobedrivenoutasOSCCLKtothetimebase module (TBM). Reset clears these two bits. OSCCLK1 OSCCLK0 Timebase Clock Source 0 0 Internal oscillator (ICLK) 0 1 RC oscillator (RCCLK) 1 0 X-tal oscillator (XTAL) 1 1 Not used MC68HC908AP Family Data Sheet, Rev. 4 52 Freescale Semiconductor

Mask Option Register (MOR) SCIBDSRC — SCI Baud Rate Clock Source SCIBDSRCselectstheclocksourceusedforthestandardSCImodule(non-infraredSCI).Thesetting of this bit affects the frequency at which the SCI operates. 1 = Internal data bus clock, f , is used as clock source for SCI BUS 0 = Oscillator clock, CGMXCLK, is used as clock source for SCI 3.5 Mask Option Register (MOR) The mask option register (MOR) is used for selecting one of the three clock options for the MCU. The MOR is a byte located in FLASH memory, and is written to by a FLASH programming routine. Address: $FFCF Bit 7 6 5 4 3 2 1 Bit 0 Read: OSCSEL1 OSCSEL0 R R R R R R Write: Reset: Unaffected by reset Erased: 1 1 1 1 1 1 1 1 R =Reserved Figure 3-4. Mask Option Register (MOR) OSCSEL1, OSCSEL0 — Oscillator Selection Bits OSCSEL1 and OSCSEL0 select which oscillator is used for the MCU CGMXCLK clock. The erase state of these two bits is logic 1. These bits are unaffected by reset. (See Table 3-1). Bits 5–0 — Should be left as 1’s Table 3-1. CGMXCLK Clock Selection OSCSEL1 OSCSEL0 CGMXCLK OSC2 pin Comments 0 0 — — Not used 0 1 ICLK fBUS Internal oscillator generates the CGMXCLK. RC oscillator generates the CGMXCLK. 1 0 RCCLK fBUS Internal oscillator is available after each POR or reset. X-tal oscillator generates the CGMXCLK. Inverting 1 1 X-TAL Internal oscillator is available after each POR output of XTAL or reset. NOTE Theinternaloscillatorisafreerunningoscillatorandisavailableaftereach POR or reset. It is turned-off in stop mode by setting the STOP_ICLKDIS bit in CONFIG2. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 53

Configuration & Mask Option Registers (CONFIG & MOR) MC68HC908AP Family Data Sheet, Rev. 4 54 Freescale Semiconductor

Chapter 4 Central Processor Unit (CPU) 4.1 Introduction TheM68HC08CPU(centralprocessorunit)isanenhancedandfullyobject-code-compatibleversionof theM68HC05CPU.TheCPU08ReferenceManual(FreescaledocumentordernumberCPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 4.2 Features • Object code fully upward-compatible with M68HC05 Family • 16-bit stack pointer with stack manipulation instructions • 16-Bit index register with x-register manipulation instructions • 8-MHz CPU internal bus frequency • 64-Kbyte program/data memory space • 16 addressing modes • Memory-to-memory data moves without using accumulator • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • Enhanced binary-coded decimal (BCD) data handling • Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 55

Central Processor Unit (CPU) 4.3 CPU Registers Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR (A) 15 0 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 4-1. CPU Registers 4.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Unaffected by reset Figure 4-2. Accumulator (A) 4.3.2 Index Register The16-bitindexregisterallowsindexedaddressingofa64-Kbytememoryspace.Histheupperbyteof the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location. MC68HC908AP Family Data Sheet, Rev. 4 56 Freescale Semiconductor

CPU Registers Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X X = Indeterminate Figure 4-3. Index Register (H:X) 4.3.3 Stack Pointer Thestackpointerisa16-bitregisterthatcontainstheaddressofthenextlocationonthestack.Duringa reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significantbyteto$FFanddoesnotaffectthemostsignificantbyte.Thestackpointerdecrementsasdata is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an indexregistertoaccessdataonthestack.TheCPUusesthecontentsofthestackpointertodetermine the conditional address of the operand. Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Figure 4-4. Stack Pointer (SP) NOTE The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point onlyto RAM locations. 4.3.4 Program Counter Theprogramcounterisa16-bitregisterthatcontainstheaddressofthenextinstructionoroperandtobe fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. Duringreset,theprogramcounterisloadedwiththeresetvectoraddresslocatedat$FFFEand$FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 57

Central Processor Unit (CPU) Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 15 Read: Write: Reset: Loaded with Vector from $FFFE and $FFFF Figure 4-5. Program Counter (PC) 4.3.5 Condition Code Register The8-bitconditioncoderegistercontainstheinterruptmaskandfiveflagsthatindicatetheresultsofthe instructionjustexecuted.Bits6and5aresetpermanentlytologic1.Thefollowingparagraphsdescribe the functions of the condition code register. Bit 7 6 5 4 3 2 1 Bit 0 Read: V 1 1 H I N Z C Write: Reset: X 1 1 X 1 X X X X = Indeterminate Figure 4-6. Condition Code Register (CCR) V — Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H — Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I — Interrupt Mask Whentheinterruptmaskisset,allmaskableCPUinterruptsaredisabled.CPUinterruptsareenabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automaticallyaftertheCPUregistersaresavedonthestack,butbeforetheinterruptvectorisfetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. MC68HC908AP Family Data Sheet, Rev. 4 58 Freescale Semiconductor

Arithmetic/Logic Unit (ALU) After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interruptmaskfromthestack.Afteranyreset,theinterruptmaskissetandcanbeclearedonlybythe clear interrupt mask software instruction (CLI). N — Negative flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulatororwhenasubtractionoperationrequiresaborrow.Someinstructions—suchasbittest and branch, shift, and rotate — also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 4.4 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Freescale document order number CPU08RM/AD) for a descriptionoftheinstructionsandaddressingmodesandmoredetailaboutthearchitectureoftheCPU. 4.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 4.5.1 Wait Mode The WAIT instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock 4.5.2 Stop Mode The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exitfromstopmodebyexternalinterrupt,theIbitremainsclear.Afterexitbyreset,theIbitisset. • Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 59

Central Processor Unit (CPU) 4.6 CPU During Break Interrupts If a break module is present on the MCU, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. Areturn-from-interruptinstruction(RTI)inthebreakroutineendsthebreakinterruptandreturnstheMCU to normal operation if the break interrupt has been deasserted. 4.7 Instruction Set Summary Table 4-1 provides a summary of the M68HC08 instruction set. 4.8 Opcode Map The opcode map is provided in Table 4-2. Table 4-1. Instruction Set Summary SFoourrmce Operation Description V HEffCeICcNtR onZ C AddressMode Opcode Operand Cycles ADC #opr IMM A9 ii 2 ADCopr DIR B9 dd 3 ADCopr EXT C9 hh ll 4 ADCopr,X IX2 D9 ee ff 4 Add with Carry A← (A) + (M) + (C) o o – o o o ADCopr,X IX1 E9 ff 3 ADC ,X IX F9 2 ADCopr,SP SP1 9EE9 ff 4 ADCopr,SP SP2 9ED9 ee ff 5 ADD #opr IMM AB ii 2 ADDopr DIR BB dd 3 ADDopr EXT CB hh ll 4 ADDopr,X IX2 DB ee ff 4 Add without Carry A← (A) + (M) o o – o o o ADDopr,X IX1 EB ff 3 ADD ,X IX FB 2 ADDopr,SP SP1 9EEB ff 4 ADDopr,SP SP2 9EDB ee ff 5 AIS #opr Add Immediate Value (Signed) to SP SP← (SP) + (16 « M) – – – – – – IMM A7 ii 2 AIX #opr Add Immediate Value (Signed) to H:X H:X← (H:X) + (16 « M) – – – – – – IMM AF ii 2 MC68HC908AP Family Data Sheet, Rev. 4 60 Freescale Semiconductor

Opcode Map Table 4-1. Instruction Set Summary SFoourrmce Operation Description V HEffCeICcNtR onZ C AddressMode Opcode Operand Cycles AND #opr IMM A4 ii 2 ANDopr DIR B4 dd 3 ANDopr EXT C4 hh ll 4 ANDopr,X IX2 D4 ee ff 4 Logical AND A← (A) & (M) 0 – – o o – ANDopr,X IX1 E4 ff 3 AND ,X IX F4 2 ANDopr,SP SP1 9EE4 ff 4 ANDopr,SP SP2 9ED4 ee ff 5 ASLopr DIR 38 dd 4 ASLA INH 48 1 ASLX Arithmetic Shift Left INH 58 1 C 0 o – – o o o ASLopr,X (Same as LSL) IX1 68 ff 4 ASL ,X b7 b0 IX 78 3 ASLopr,SP SP1 9E68 ff 5 ASRopr DIR 37 dd 4 ASRA INH 47 1 ASRX Arithmetic Shift Right C o – – o o o INH 57 1 ASRopr,X IX1 67 ff 4 b7 b0 ASRopr,X IX 77 3 ASRopr,SP SP1 9E67 ff 5 BCCrel Branch if Carry Bit Clear PC← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3 DIR (b0) 11 dd 4 DIR (b1) 13 dd 4 DIR (b2) 15 dd 4 DIR (b3) 17 dd 4 BCLRn,opr Clear Bit n in M Mn← 0 – – – – – – DIR (b4) 19 dd 4 DIR (b5) 1B dd 4 DIR (b6) 1D dd 4 DIR (b7) 1F dd 4 BCSrel Branch if Carry Bit Set (Same as BLO) PC← (PC) + 2 +rel ? (C) = 1 – – – – – – REL 25 rr 3 BEQrel Branch if Equal PC← (PC) + 2 +rel ? (Z) = 1 – – – – – – REL 27 rr 3 BranchifGreaterThanorEqualTo BGEopr PC← (PC) + 2 +rel ? (N ⊕ V) = 0 – – – – – – REL 90 rr 3 (Signed Operands) Branch if Greater Than (Signed BGTopr PC← (PC) + 2 +rel ? (Z)| (N ⊕ V)=0 – – – – – – REL 92 rr 3 Operands) BHCCrel Branch if Half Carry Bit Clear PC← (PC) + 2 +rel ? (H) = 0 – – – – – – REL 28 rr 3 BHCSrel Branch if Half Carry Bit Set PC← (PC) + 2 +rel ? (H) = 1 – – – – – – REL 29 rr 3 BHIrel Branch if Higher PC← (PC) + 2 +rel ? (C) | (Z) = 0 – – – – – – REL 22 rr 3 Branch if Higher or Same BHSrel PC← (PC) + 2 +rel ? (C) = 0 – – – – – – REL 24 rr 3 (Same as BCC) BIHrel Branch ifIRQ Pin High PC← (PC) + 2 +rel ?IRQ = 1 – – – – – – REL 2F rr 3 BILrel Branch ifIRQ Pin Low PC← (PC) + 2 +rel ?IRQ = 0 – – – – – – REL 2E rr 3 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 61

Central Processor Unit (CPU) Table 4-1. Instruction Set Summary SFoourrmce Operation Description V HEffCeICcNtR onZ C AddressMode Opcode Operand Cycles BIT #opr IMM A5 ii 2 BITopr DIR B5 dd 3 BITopr EXT C5 hh ll 4 BITopr,X IX2 D5 ee ff 4 Bit Test (A) & (M) 0 – – o o – BITopr,X IX1 E5 ff 3 BIT ,X IX F5 2 BITopr,SP SP1 9EE5 ff 4 BITopr,SP SP2 9ED5 ee ff 5 Branch if Less Than or Equal To BLEopr PC←(PC)+2+rel?(Z)|(N⊕V)=1 – – – – – – REL 93 rr 3 (Signed Operands) BLOrel Branch if Lower (Same as BCS) PC← (PC) + 2 +rel ? (C) = 1 – – – – – – REL 25 rr 3 BLSrel Branch if Lower or Same PC← (PC) + 2 +rel ? (C) | (Z) = 1 – – – – – – REL 23 rr 3 BLTopr Branch if Less Than (Signed Operands) PC← (PC) + 2 +rel ? (N ⊕ V) = 1 – – – – – – REL 91 rr 3 BMCrel Branch if Interrupt Mask Clear PC← (PC) + 2 +rel ? (I) = 0 – – – – – – REL 2C rr 3 BMIrel Branch if Minus PC← (PC) + 2 +rel ? (N) = 1 – – – – – – REL 2B rr 3 BMSrel Branch if Interrupt Mask Set PC← (PC) + 2 +rel ? (I) = 1 – – – – – – REL 2D rr 3 BNErel Branch if Not Equal PC← (PC) + 2 +rel ? (Z) = 0 – – – – – – REL 26 rr 3 BPLrel Branch if Plus PC← (PC) + 2 +rel ? (N) = 0 – – – – – – REL 2A rr 3 BRArel Branch Always PC← (PC) + 2 +rel – – – – – – REL 20 rr 3 DIR (b0) 01 dd rr 5 DIR (b1) 03 dd rr 5 DIR (b2) 05 dd rr 5 DIR (b3) 07 dd rr 5 BRCLRn,opr,rel Branch if Bitn inM Clear PC← (PC) + 3 +rel ? (Mn) = 0 – – – – – o DIR (b4) 09 dd rr 5 DIR (b5) 0B dd rr 5 DIR (b6) 0D dd rr 5 DIR (b7) 0F dd rr 5 BRNrel Branch Never PC← (PC) + 2 – – – – – – REL 21 rr 3 DIR (b0) 00 dd rr 5 DIR (b1) 02 dd rr 5 DIR (b2) 04 dd rr 5 DIR (b3) 06 dd rr 5 BRSETn,opr,rel Branch if Bitn inM Set PC← (PC) + 3 +rel ? (Mn) = 1 – – – – – o DIR (b4) 08 dd rr 5 DIR (b5) 0A dd rr 5 DIR (b6) 0C dd rr 5 DIR (b7) 0E dd rr 5 DIR (b0) 10 dd 4 DIR (b1) 12 dd 4 DIR (b2) 14 dd 4 DIR (b3) 16 dd 4 BSETn,opr Set Bitnin M Mn← 1 – – – – – – DIR (b4) 18 dd 4 DIR (b5) 1A dd 4 DIR (b6) 1C dd 4 DIR (b7) 1E dd 4 MC68HC908AP Family Data Sheet, Rev. 4 62 Freescale Semiconductor

Opcode Map Table 4-1. Instruction Set Summary SFoourrmce Operation Description V HEffCeICcNtR onZ C AddressMode Opcode Operand Cycles PC← (PC) + 2; push (PCL) SP← (SP) – 1; push (PCH) BSRrel Branch to Subroutine – – – – – – REL AD rr 4 SP← (SP) – 1 PC← (PC) +rel CBEQ opr,rel PC←(PC)+3+rel?(A)–(M)=$00 DIR 31 dd rr 5 CBEQA #opr,rel PC←(PC)+3+rel?(A)–(M)=$00 IMM 41 ii rr 4 CBEQX #opr,rel PC←(PC)+3+rel?(X)–(M)=$00 IMM 51 ii rr 4 Compare and Branch if Equal – – – – – – CBEQ opr,X+,rel PC←(PC)+3+rel?(A)–(M)=$00 IX1+ 61 ff rr 5 CBEQX+,rel PC←(PC)+2+rel?(A)–(M)=$00 IX+ 71 rr 4 CBEQopr,SP,rel PC←(PC)+4+rel?(A)–(M)=$00 SP1 9E61 ff rr 6 CLC Clear Carry Bit C← 0 – – – – – 0 INH 98 1 CLI Clear Interrupt Mask I← 0 – – 0 – – – INH 9A 2 CLRopr M← $00 DIR 3F dd 3 CLRA A← $00 INH 4F 1 CLRX X← $00 INH 5F 1 CLRH Clear H← $00 0 – – 0 1 – INH 8C 1 CLRopr,X M← $00 IX1 6F ff 3 CLR ,X M← $00 IX 7F 2 CLRopr,SP M← $00 SP1 9E6F ff 4 CMP #opr IMM A1 ii 2 CMPopr DIR B1 dd 3 CMPopr EXT C1 hh ll 4 CMPopr,X IX2 D1 ee ff 4 Compare A with M (A) – (M) o – – o o o CMPopr,X IX1 E1 ff 3 CMP ,X IX F1 2 CMPopr,SP SP1 9EE1 ff 4 CMPopr,SP SP2 9ED1 ee ff 5 COMopr M← (M) = $FF – (M) DIR 33 dd 4 COMA A← (A) = $FF – (M) INH 43 1 COMX X← (X) = $FF – (M) INH 53 1 Complement (One’s Complement) 0 – – o o 1 COMopr,X M← (M) = $FF – (M) IX1 63 ff 4 COM ,X M← (M) = $FF – (M) IX 73 3 COMopr,SP M← (M) = $FF – (M) SP1 9E63 ff 5 CPHX #opr IMM 65 ii ii+1 3 Compare H:X withM (H:X) – (M:M + 1) o – – o o o CPHXopr DIR 75 dd 4 CPX #opr IMM A3 ii 2 CPXopr DIR B3 dd 3 CPXopr EXT C3 hh ll 4 CPX ,X IX2 D3 ee ff 4 Compare X withM (X) – (M) o – – o o o CPXopr,X IX1 E3 ff 3 CPXopr,X IX F3 2 CPXopr,SP SP1 9EE3 ff 4 CPXopr,SP SP2 9ED3 ee ff 5 DAA Decimal Adjust A (A) U – – o o o INH 72 2 10 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 63

Central Processor Unit (CPU) Table 4-1. Instruction Set Summary SFoourrmce Operation Description V HEffCeICcNtR onZ C AddressMode Opcode Operand Cycles A←(A)–1 or M←(M)–1 or X←(X)–1 5 DBNZopr,rel PC← (PC) + 3 +rel ? (result)≠ 0 DIR 3B dd rr 3 DBNZArel PC← (PC) + 2 +rel ? (result)≠ 0 INH 4B rr 3 DBNZXrel Decrement and Branch if Not Zero PC← (PC) + 2 +rel ? (result)≠ 0 – – – – – – INH 5B rr 5 DBNZopr,X,rel PC← (PC) + 3 + rel ? (result)≠ 0 IX1 6B ff rr 4 DBNZ X,rel PC← (PC) + 2 +rel ? (result)≠ 0 IX 7B rr 6 DBNZopr,SP,rel PC← (PC) + 4 +rel ? (result)≠ 0 SP1 9E6B ff rr DECopr M← (M) – 1 DIR 3A dd 4 DECA A← (A) – 1 INH 4A 1 DECX X← (X) – 1 INH 5A 1 Decrement o – – o o – DECopr,X M← (M) – 1 IX1 6A ff 4 DEC ,X M← (M) – 1 IX 7A 3 DECopr,SP M← (M) – 1 SP1 9E6A ff 5 A← (H:A)/(X) DIV Divide – – – – o o INH 52 7 H← Remainder EOR #opr IMM A8 ii 2 EORopr DIR B8 dd 3 EORopr EXT C8 hh ll 4 EORopr,X IX2 D8 ee ff 4 Exclusive OR M with A A← (A⊕ M) 0 – – o o – EORopr,X IX1 E8 ff 3 EOR ,X IX F8 2 EORopr,SP SP1 9EE8 ff 4 EORopr,SP SP2 9ED8 ee ff 5 INCopr M← (M) + 1 DIR 3C dd 4 INCA A← (A) + 1 INH 4C 1 INCX X← (X) + 1 INH 5C 1 Increment o – – o o – INCopr,X M← (M) + 1 IX1 6C ff 4 INC ,X M← (M) + 1 IX 7C 3 INCopr,SP M← (M) + 1 SP1 9E6C ff 5 JMPopr DIR BC dd 2 JMPopr EXT CC hh ll 3 JMPopr,X Jump PC← Jump Address – – – – – – IX2 DC ee ff 4 JMPopr,X IX1 EC ff 3 JMP ,X IX FC 2 JSRopr DIR BD dd 4 PC← (PC) +n (n = 1, 2, or 3) JSRopr EXT CD hh ll 5 Push (PCL); SP← (SP) – 1 JSRopr,X Jump to Subroutine – – – – – – IX2 DD ee ff 6 Push (PCH); SP← (SP) – 1 JSRopr,X IX1 ED ff 5 PC← Unconditional Address JSR ,X IX FD 4 LDA #opr IMM A6 ii 2 LDAopr DIR B6 dd 3 LDAopr EXT C6 hh ll 4 LDAopr,X IX2 D6 ee ff 4 Load A from M A← (M) 0 – – o o – LDAopr,X IX1 E6 ff 3 LDA ,X IX F6 2 LDAopr,SP SP1 9EE6 ff 4 LDAopr,SP SP2 9ED6 ee ff 5 LDHX #opr IMM 45 ii jj 3 Load H:X from M H:X←(M:M+ 1) 0 – – o o – LDHXopr DIR 55 dd 4 MC68HC908AP Family Data Sheet, Rev. 4 64 Freescale Semiconductor

Opcode Map Table 4-1. Instruction Set Summary SFoourrmce Operation Description V HEffCeICcNtR onZ C AddressMode Opcode Operand Cycles LDX #opr IMM AE ii 2 LDXopr DIR BE dd 3 LDXopr EXT CE hh ll 4 LDXopr,X IX2 DE ee ff 4 Load X from M X← (M) 0 – – o o – LDXopr,X IX1 EE ff 3 LDX ,X IX FE 2 LDXopr,SP SP1 9EEE ff 4 LDXopr,SP SP2 9EDE ee ff 5 LSLopr DIR 38 dd 4 LSLA INH 48 1 LSLX Logical Shift Left C 0 o – – o o o INH 58 1 LSLopr,X (Same as ASL) IX1 68 ff 4 b7 b0 LSL ,X IX 78 3 LSLopr,SP SP1 9E68 ff 5 LSRopr DIR 34 dd 4 LSRA INH 44 1 LSRX Logical Shift Right 0 C o – – 0 o o INH 54 1 LSRopr,X IX1 64 ff 4 b7 b0 LSR ,X IX 74 3 LSRopr,SP SP1 9E64 ff 5 MOVopr,opr DD 4E dd dd 5 (M) ←(M) MOVopr,X+ Destination Source DIX+ 5E dd 4 Move 0 – – o o – MOV #opr,opr IMD 6E ii dd 4 H:X← (H:X) + 1 (IX+D, DIX+) MOV X+,opr IX+D 7E dd 4 MUL Unsigned multiply X:A← (X)× (A) – 0 – – – 0 INH 42 5 NEGopr DIR 30 dd 4 M← –(M) = $00 – (M) NEGA INH 40 1 A← –(A) = $00 – (A) NEGX INH 50 1 Negate (Two’s Complement) X← –(X) = $00 – (X) o – – o o o NEGopr,X IX1 60 ff 4 M← –(M) = $00 – (M) NEG ,X IX 70 3 M← –(M) = $00 – (M) NEGopr,SP SP1 9E60 ff 5 NOP No Operation None – – – – – – INH 9D 1 NSA Nibble Swap A A← (A[3:0]:A[7:4]) – – – – – – INH 62 3 ORA #opr IMM AA ii 2 ORAopr DIR BA dd 3 ORAopr EXT CA hh ll 4 ORAopr,X IX2 DA ee ff 4 Inclusive ORA andM A← (A) | (M) 0 – – o o – ORAopr,X IX1 EA ff 3 ORA ,X IX FA 2 ORAopr,SP SP1 9EEA ff 4 ORAopr,SP SP2 9EDA ee ff 5 PSHA Push A onto Stack Push (A); SP←(SP) – 1 – – – – – – INH 87 2 PSHH Push H onto Stack Push (H); SP←(SP) – 1 – – – – – – INH 8B 2 PSHX Push X onto Stack Push (X); SP←(SP) – 1 – – – – – – INH 89 2 PULA Pull A from Stack SP←(SP + 1); Pull (A) – – – – – – INH 86 2 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 65

Central Processor Unit (CPU) Table 4-1. Instruction Set Summary SFoourrmce Operation Description V HEffCeICcNtR onZ C AddressMode Opcode Operand Cycles PULH Pull H from Stack SP←(SP + 1); Pull (H) – – – – – – INH 8A 2 PULX Pull X from Stack SP←(SP + 1); Pull (X) – – – – – – INH 88 2 ROLopr DIR 39 dd 4 ROLA INH 49 1 ROLX INH 59 1 Rotate Left through Carry C o – – o o o ROLopr,X IX1 69 ff 4 b7 b0 ROL ,X IX 79 3 ROLopr,SP SP1 9E69 ff 5 RORopr DIR 36 dd 4 RORA INH 46 1 RORX INH 56 1 Rotate Right through Carry C o – – o o o RORopr,X IX1 66 ff 4 b7 b0 ROR ,X IX 76 3 RORopr,SP SP1 9E66 ff 5 RSP Reset Stack Pointer SP← $FF – – – – – – INH 9C 1 SP← (SP) + 1; Pull (CCR) SP← (SP) + 1; Pull (A) RTI Return from Interrupt SP← (SP) + 1; Pull (X) o o o o o o INH 80 7 SP← (SP) + 1; Pull (PCH) SP← (SP) + 1; Pull (PCL) SP← SP + 1;Pull (PCH) RTS Return from Subroutine – – – – – – INH 81 4 SP← SP + 1; Pull (PCL) SBC #opr IMM A2 ii 2 SBCopr DIR B2 dd 3 SBCopr EXT C2 hh ll 4 SBCopr,X IX2 D2 ee ff 4 Subtract with Carry A← (A) – (M) – (C) o – – o o o SBCopr,X IX1 E2 ff 3 SBC ,X IX F2 2 SBCopr,SP SP1 9EE2 ff 4 SBCopr,SP SP2 9ED2 ee ff 5 SEC Set Carry Bit C← 1 – – – – – 1 INH 99 1 SEI Set Interrupt Mask I← 1 – – 1 – – – INH 9B 2 STAopr DIR B7 dd 3 STAopr EXT C7 hh ll 4 STAopr,X IX2 D7 ee ff 4 STAopr,X Store A in M M←(A) 0 – – o o – IX1 E7 ff 3 STA ,X IX F7 2 STAopr,SP SP1 9EE7 ff 4 STAopr,SP SP2 9ED7 ee ff 5 STHXopr Store H:X in M (M:M + 1)← (H:X) 0 – – o o – DIR 35 dd 4 STOP EnableIRQ Pin; Stop Processing I← 0; Stop Processing – – 0 – – – INH 8E 1 MC68HC908AP Family Data Sheet, Rev. 4 66 Freescale Semiconductor

Opcode Map Table 4-1. Instruction Set Summary SFoourrmce Operation Description V HEffCeICcNtR onZ C AddressMode Opcode Operand Cycles STXopr DIR BF dd 3 STXopr EXT CF hh ll 4 STXopr,X IX2 DF ee ff 4 STXopr,X Store X in M M←(X) 0 – – o o – IX1 EF ff 3 STX ,X IX FF 2 STXopr,SP SP1 9EEF ff 4 STXopr,SP SP2 9EDF ee ff 5 SUB #opr IMM A0 ii 2 SUBopr DIR B0 dd 3 SUBopr EXT C0 hh ll 4 SUBopr,X IX2 D0 ee ff 4 Subtract A← (A) – (M) o – – o o o SUBopr,X IX1 E0 ff 3 SUB ,X IX F0 2 SUBopr,SP SP1 9EE0 ff 4 SUBopr,SP SP2 9ED0 ee ff 5 PC← (PC) + 1; Push (PCL) SP← (SP) – 1; Push (PCH) SP← (SP) – 1; Push (X) SP← (SP) – 1; Push (A) SWI Software Interrupt – – 1 – – – INH 83 9 SP← (SP) – 1; Push (CCR) SP← (SP) – 1; I← 1 PCH← Interrupt Vector High Byte PCL← Interrupt Vector Low Byte TAP Transfer A to CCR CCR← (A) o o o o o o INH 84 2 TAX Transfer A to X X← (A) – – – – – – INH 97 1 TPA Transfer CCR to A A← (CCR) – – – – – – INH 85 1 TSTopr DIR 3D dd 3 TSTA INH 4D 1 TSTX INH 5D 1 Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – o o – TSTopr,X IX1 6D ff 3 TST ,X IX 7D 2 TSTopr,SP SP1 9E6D ff 4 TSX Transfer SP to H:X H:X← (SP) + 1 – – – – – – INH 95 2 TXA Transfer X to A A← (X) – – – – – – INH 9F 1 TXS Transfer H:X to SP (SP)← (H:X) – 1 – – – – – – INH 94 2 I← 0; Inhibit CPU clocking until WAIT Enable Interrupts; Wait for Interrupt – – 0 – – – INH 8F 1 interrupted MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 67

Central Processor Unit (CPU) Table 4-1. Instruction Set Summary SFoourrmce Operation Description V HEffCeICcNtR onZ C AddressMode Opcode Operand Cycles A Accumulator n Any bit C Carry/borrow bit opr Operand (one or two bytes) CCR Condition code register PC Program counter dd Direct address of operand PCH Program counter high byte dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte DD Direct to direct addressing mode REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer H Half-carry bit U Undefined H Index register high byte V Overflow bit hh ll High and low bytes of operand address in extended addressing X Index register low byte I Interrupt mask Z Zero bit ii Immediate operand byte & Logical AND IMD Immediate source to direct destination addressing mode | Logical OR ⊕ IMM Immediate addressing mode Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX+ Indexed, no offset, post increment addressing mode # Immediate value IX+D Indexed with post increment to direct addressing mode « Sign extend IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX1+ Indexed, 8-bit offset, post increment addressing mode ? If IX2 Indexed, 16-bit offset addressing mode : Concatenated with M Memory location o Set or cleared N Negative bit — Not affected MC68HC908AP Family Data Sheet, Rev. 4 68 Freescale Semiconductor

F re e Table 4-2. Opcode Map s c a Bit Manipulation Branch Read-Modify-Write Control Register/Memory le S DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX e MSB m 0 1 2 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F ic LSB on 5 4 3 4 1 1 4 5 3 7 3 2 3 4 4 5 3 4 2 d 0 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG NEG RTI BGE SUB SUB SUB SUB SUB SUB SUB SUB u 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX c to 5 4 3 5 4 4 5 6 4 4 3 2 3 4 4 5 3 4 2 r 1 BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ CBEQ RTS BLT CMP CMP CMP CMP CMP CMP CMP CMP 3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 4 SP1 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX 5 4 3 5 7 3 2 3 2 3 4 4 5 3 4 2 2 BRSET1 BSET1 BHI MUL DIV NSA DAA BGT SBC SBC SBC SBC SBC SBC SBC SBC 3 DIR 2 DIR 2 REL 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX 5 4 3 4 1 1 4 5 3 9 3 2 3 4 4 5 3 4 2 3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM COM SWI BLE CPX CPX CPX CPX CPX CPX CPX CPX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX 5 4 3 4 1 1 4 5 3 2 2 2 3 4 4 5 3 4 2 M 4 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR LSR TAP TXS AND AND AND AND AND AND AND AND C 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX 6 8 5 4 3 4 3 4 3 4 1 2 2 3 4 4 5 3 4 2 H 5 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT BIT BIT C 3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX 9 0 5 4 3 4 1 1 4 5 3 2 2 3 4 4 5 3 4 2 8A 6 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR ROR PULA LDA LDA LDA LDA LDA LDA LDA LDA P 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX F 5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2 a 7 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR ASR PSHA TAX AIS STA STA STA STA STA STA STA m 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX ily 5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2 D 8 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR EOR EOR a 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX ta 5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2 S 9 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC ADC ADC h 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX e e 5 4 3 4 1 1 4 5 3 2 2 2 3 4 4 5 3 4 2 t, R A 3BRSDEITR5 2BSEDTIR5 2 BPRLEL 2DEDCIR 1DECINAH 1DEICNXH 2DEIXC1 3DESCP1 1DEIXC 1PUILNHH 1 CLINIH 2ORIMAM 2ORDAIR 3OREAXT 3ORIXA2 4ORSAP2 2ORIXA1 3ORSAP1 1ORIXA e 5 4 3 5 3 3 5 6 4 2 2 2 3 4 4 5 3 4 2 v . 4 B B3RCDLRIR5 2BCLDRIR5 2 BMRIEL 3DBDNIZR 2DBNINZHA 2DBNINZHX 3DBINXZ1 4DBSNPZ1 2DBINXZ 1PSHINHH 1 SEINIH 2ADIMDM 2ADDDIR 3ADEDXT 3ADIXD2 4ADSDP2 2ADIXD1 3ADSDP1 1ADIXD 5 4 3 4 1 1 4 5 3 1 1 2 3 4 3 2 C BRSET6 BSET6 BMC INC INCA INCX INC INC INC CLRH RSP JMP JMP JMP JMP JMP 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 5 4 3 3 1 1 3 4 2 1 4 4 5 6 5 4 D BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST TST NOP BSR JSR JSR JSR JSR JSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 5 4 3 5 4 4 4 1 2 3 4 4 5 3 4 2 E BRSET7 BSET7 BIL MOV MOV MOV MOV STOP * LDX LDX LDX LDX LDX LDX LDX LDX 3 DIR 2 DIR 2 REL 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX 5 4 3 3 1 1 3 4 2 1 1 2 3 4 4 5 3 4 2 F BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR CLR WAIT TXA AIX STX STX STX STX STX STX STX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset MSB O IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset 0 High Byte of Opcode in Hexadecimal DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with LSB pc EXT Extended IX2 Indexed, 16-Bit Offset Post Increment 5 Cycles o DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with Low Byte of Opcode in Hexadecimal 0 BRSET0 Opcode Mnemonic de 6 *IXP+rDe-bInydtee xfoerd s-Dtaicrekc ptoinDteIXr i+ndDeixreecdt -iInnsdteruxcetdions Post Increment 3 DIR Number of Bytes / Addressing Mode Ma 9 p

Central Processor Unit (CPU) MC68HC908AP Family Data Sheet, Rev. 4 70 Freescale Semiconductor

Chapter 5 Oscillator (OSC) 5.1 Introduction The oscillator module consist of three types of oscillator circuits: • Internal oscillator • RC oscillator • 32.768kHz crystal (x-tal) oscillator The reference clock for the CGM and other MCU sub-systems is selected by programming the mask option register located at $FFCF. Thereferenceclockforthetimebasemodule(TBM)isselectedbythetwobits,OSCCLK1andOSCCLK0, in the CONFIG2 register. TheinternaloscillatorrunscontinuouslyafteraPORorreset,andisalwaysavailable.TheRCandcrystal oscillator cannot run concurrently; one is disabled while the other is selected; because the RC and x-tal circuits share the same OSC1 pin. NOTE The oscillator circuits are powered by the on-chip V regulator, REG therefore, the output swing on OSC1 and OSC2 is from V to V . SS REG Figure 5-1. shows the block diagram of the oscillator module. 5.2 Clock Selection Reference clocks are selectable for the following sub-systems: • CGMXCLKandCGMRCLK—Referenceclockforclockgeneratormodule(CGM)andotherMCU sub-systems other than TBM and COP. This is the main reference clock for the MCU. • OSCCLK — Reference clock for timebase module (TBM). MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 71

Oscillator (OSC) To CGM and others To CGM PLL To TBM CGMXCLK CGMRCLK OSCCLK MOR CONFIG2 OSCSEL1 OSCCLK1 MUX MUX OSCSEL0 OSCCLK0 X RC I X RC I To SIM (and COP) XCLK RCCLK ICLK X-TAL OSCILLATOR RC OSCILLATOR INTERNAL OSCILLATOR BUS CLOCK From SIM OSC1 OSC2 Figure 5-1. Oscillator Module Block Diagram 5.2.1 CGM Reference Clock Selection Theclockgeneratormodule(CGM)referenceclock(CGMXCLK)isthereferenceclockinputtotheMCU. It is selected by programming two bits in a FLASH memory location; themask option register (MOR), at $FFCF. See 3.5 Mask Option Register (MOR). Address: $FFCF Bit 7 6 5 4 3 2 1 Bit 0 Read: OSCSEL1 OSCSEL0 R R R R R R Write: Reset: Unaffected by reset Erased: 1 1 1 1 1 1 1 1 R =Reserved Figure 5-2. Mask Option Register (MOR) MC68HC908AP Family Data Sheet, Rev. 4 72 Freescale Semiconductor

Clock Selection Table 5-1. CGMXCLK Clock Selection OSCSEL1 OSCSEL0 CGMXCLK OSC2 Pin Comments 0 0 — — Not used 0 1 ICLK fBUS Internal oscillator generates the CGMXCLK. RC oscillator generates the CGMXCLK. 1 0 RCCLK fBUS Internal oscillator is available after each POR or reset. Inverting X-tal oscillator generates the CGMXCLK. 1 1 XCLK output of Internal oscillator is available after each POR or X-TAL reset. NOTE Theinternaloscillatorisafreerunningoscillatorandisavailableaftereach POR or reset. It is turned-off in stop mode by setting the STOP_ICLKDIS bit in CONFIG2. 5.2.2 TBM Reference Clock Selection The timebase module reference clock (OSCCLK) is selected by configuring two bits in the CONFIG2 register, at $001D. See Chapter 3 Configuration & Mask Option Registers (CONFIG & MOR). Address: $001D Bit 7 6 5 4 3 2 1 Bit 0 Read: STOP_ STOP_ STOP_ 0 0 SCIBD- OSCCLK1 OSCCLK0 Write: ICLKDIS RCLKEN XCLKEN SRC Reset: 0 0 0 0 0 0 0 0 Figure 5-3. Configuration Register 2 (CONFIG2) Table 5-2. Timebase Module Reference Clock Selection OSCCLK1 OSCCLK0 Timebase Clock Source 0 0 Internal oscillator (ICLK) 0 1 RC oscillator (RCCLK) 1 0 X-tal oscillator (XCLK) 1 1 Not used NOTE TheRCCLKorXCLKisonlyavailableifthatclockisselectedastheCGM reference clock, whereas the ICLK is always available. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 73

Oscillator (OSC) 5.3 Internal Oscillator The internal oscillator clock (ICLK), with a frequency of f , is a free running clock that requires no ICLK externalcomponents.ItcanbeselectedastheCGMXCLKfortheCGMandMCUsub-systems;andthe OSCCLKclockfortheTBM.TheICLKisalsothereferenceclockinputtothecomputeroperatingproperly (COP) module. Due to the simplicity of the internal oscillator, it does not have the accuracy and stability of the RC oscillatororthex-taloscillator.Therefore,theICLKisnotsuitablewhereanaccuratebusclockisrequired and it should not be used as the CGMRCLK to the CGM PLL. The internal oscillator by default is always available and is free running after POR or reset. It can be turned-off in stop mode by setting the STOP_ICLKDIS bit before executing the STOP instruction. Figure 5-4 shows the logical representation of components of the internal oscillator circuitry. From SIM To Clock Selection MUX From SIM and COP SIMOSCEN ICLK BUS CLOCK CONFIG2 EN STOP_ICLKDIS INTERNAL OSCILLATOR MCU OSC2 Figure 5-4. Internal Oscillator MC68HC908AP Family Data Sheet, Rev. 4 74 Freescale Semiconductor

RC Oscillator 5.4 RC Oscillator The RC oscillator circuit is designed for use with an external resistor and a capacitor. In its typical configuration, the RC oscillator requires two external components, one R and one C. Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance. The oscillator configuration uses two components: • C EXT • R EXT From SIM To Clock Selection MUX From SIM SIMOSCEN RCCLK BUS CLOCK CONFIG2 EN STOP_RCLKEN RC OSCILLATOR MCU OSC1 OSC2 SeeChapter 22 for component value requirements. V REG R C EXT EXT Figure 5-5. RC Oscillator 5.5 X-tal Oscillator The crystal (x-tal) oscillator circuit is designed for use with an external 32.768kHz crystal to provide an accurate clock source. In its typical configuration, the x-tal oscillator is connected in a Pierce oscillator configuration, as shown in Figure 5-6. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: • Crystal, X (32.768kHz) 1 • Fixed capacitor, C 1 • Tuning capacitor, C (can also be a fixed capacitor) 2 • Feedback resistor, R B • Series resistor, R (optional) S MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 75

Oscillator (OSC) From SIM To Clock Selection MUX SIMOSCEN XCLK CONFIG2 STOP_XCLKEN MCU OSC1 OSC2 R B R S X 1 SeeChapter 22 for component value requirements. 32.768kHz C C 1 2 Figure 5-6. Crystal Oscillator Theseriesresistor(R )isincludedinthediagramtofollowstrictPierceoscillatorguidelinesandmaynot S be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information. 5.6 I/O Signals The following paragraphs describe the oscillator I/O signals. 5.6.1 Crystal Amplifier Input Pin (OSC1) OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit. 5.6.2 Crystal Amplifier Output Pin (OSC2) When the x-tal oscillator is selected, OSC2 pin is the output of the crystal oscillator inverting amplifier. When the RC oscillator or internal oscillator is selected, OSC2 pin is the output of the internal bus clock. 5.6.3 Oscillator Enable Signal (SIMOSCEN) TheSIMOSCENsignalfromthesystemintegrationmodule(SIM)enables/disablesthex-taloscillator,the RC-oscillator, or the internal oscillator circuit. MC68HC908AP Family Data Sheet, Rev. 4 76 Freescale Semiconductor

Low Power Modes 5.6.4 CGM Oscillator Clock (CGMXCLK) TheCGMXCLKclockisoutputfromthex-taloscillator,RCoscillatorortheinternaloscillator.Thisclock drives to CGM and other MCU sub-systems. 5.6.5 CGM Reference Clock (CGMRCLK) This is buffered signal of CGMXCLK, it is used by the CGM as the phase-locked-loop (PLL) reference clock. 5.6.6 Oscillator Clock to Time Base Module (OSCCLK) TheOSCCLKisthereferenceclockthatdrivesthetimebasemodule.SeeChapter10TimebaseModule (TBM). 5.7 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. 5.7.1 Wait Mode The WAIT instruction has no effect on the oscillator module. CGMXCLK continues to drive to the clock generator module, and OSCCLK continues to drive the timebase module. 5.7.2 Stop Mode TheSTOPinstructiondisablesthex-talortheRCoscillatorcircuit,andhencetheCGMXCLKclockstops running.For continuousx-tal or RCoscillatoroperation instop mode,set theSTOP_XCLKEN (for x-tal) or STOP_RCLKEN (for RC) bit to logic 1 before entering stop mode. The internal oscillator clock continues operation in stop mode. It can be disabled by setting the STOP_ICLKDIS bit to logic 1 before entering stop mode. 5.8 Oscillator During Break Mode The oscillator continues to drive CGMXCLK when the device enters the break state. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 77

Oscillator (OSC) MC68HC908AP Family Data Sheet, Rev. 4 78 Freescale Semiconductor

Chapter 6 Clock Generator Module (CGM) 6.1 Introduction This section describes the clock generator module (CGM). The CGM generates the base clock signal, CGMOUT, which is based on either the oscillator clock divided by two or the divided phase-locked loop (PLL) clock, CGMPCLK, divided by two. CGMOUT is the clock from which the SIM derives the system clocks, including the bus clock, which is at a frequency of CGMOUT2. ThePLLisafrequencygeneratordesignedforusewithalowfrequencycrystal(typically32.768kHz)to generate a base frequency and dividing to a maximum bus frequency of 8MHz. 6.2 Features Features of the CGM include: • Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference • Low-frequency crystal operation with low-power operation and high-output frequency resolution • Programmable prescaler for power-of-two increases in frequency • Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation • Automatic bandwidth control mode for low-jitter operation • Automatic frequency lock detector • CPU interrupt on entry or exit from locked condition • Configuration register bit to allow oscillator operation during stop mode 6.3 Functional Description The CGM consists of three major sub-modules: • Oscillator module — The oscillator module generates the constant reference frequency clock, CGMRCLK (buffered CGMXCLK). • Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock, CGMVCLK, and the divided VCO clock, CGMPCLK. • Baseclockselectorcircuit—Thissoftware-controlledcircuitselectseitherCGMXCLKdividedby two or the divided VCO clock, CGMPCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 6-1 shows the structure of the CGM. Figure 6-2 is a summary of the CGM registers. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 79

Clock Generator Module (CGM) OSCILLATOR (OSC) MODULE OSC2 SeeChapter 5 Oscillator (OSC). ICLK To SIM (and COP) OSC1 INTERNAL OSCILLATOR OSCCLK To Timebase Module (TBM) RC OSCILLATOR MUX CGMXCLK OSCSEL[1:0] To ADC CRYSTAL OSCILLATOR CGMRCLK OSCCLK[1:0] SIMOSCEN From SIM PHASE-LOCKED LOOP (PLL) CGMRDV REFERENCE CGMRCLK A CGMOUT DIVIDER CLOCK BCS SELECT ÷ 2 B1S* To SIM CIRCUIT R RDS[3:0] *WHEN S = 1, SIMDIV2 VDDA CGMXFC VSSA CGMOUT = B From SIM VPR[1:0] VRS[7:0] 2E L CGMPCLK VOLTAGE PHASE LOOP CONTROLLED DETECTOR FILTER OSCILLATOR PLL ANALOG LOCK AUTOMATIC INTERRUPT CGMINT MODE DETECTOR CONTROL CONTROL To SIM LOCK AUTO ACQ PLLIE PLLF MUL[11:0] PRE[1:0] N 2P CGMVDV FREQUENCY FREQUENCY CGMVCLK DIVIDER DIVIDER Figure 6-1. CGM Block Diagram MC68HC908AP Family Data Sheet, Rev. 4 80 Freescale Semiconductor

Functional Description Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: PLLF PLL Control Register PLLIE PLLON BCS PRE1 PRE0 VPR1 VPR0 $0036 Write: (PTCL) Reset: 0 0 1 0 0 0 0 0 PLL Bandwidth Control Read: LOCK 0 0 0 0 AUTO ACQ R $0037 Register Write: (PBWC) Reset: 0 0 0 0 0 0 0 PLL Multiplier Select Read: 0 0 0 0 MUL11 MUL10 MUL9 MUL8 $0038 Register High Write: (PMSH) Reset: 0 0 0 0 0 0 0 0 PLL Multiplier Select Read: MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 $0039 Register Low Write: (PMSL) Reset: 0 1 0 0 0 0 0 0 PLL VCO Range Select Read: VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0 $003A Register Write: (PMRS) Reset: 0 1 0 0 0 0 0 0 PLL Reference Divider Read: 0 0 0 0 RDS3 RDS2 RDS1 RDS0 $003B Select Register Write: (PMDS) Reset: 0 0 0 0 0 0 0 1 =Unimplemented R =Reserved NOTES: 1. When AUTO = 0, PLLIE is forced clear and is read-only. 2. When AUTO = 0, PLLF and LOCK read as clear. 3. When AUTO = 1,ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. Figure 6-2. CGM I/O Register Summary 6.3.1 Oscillator Module The oscillator module provides two clock outputs CGMXCLK and CGMRCLK to the CGM module. CGMXCLKwhenselected,isdriventoSIMmoduletogeneratethesystembusclock.CGMRCLKisused by the phase-lock-loop to provide a higher frequency system bus clock. The oscillator module also providesthereferenceclockforthetimebasemodule(TBM).SeeChapter5Oscillator(OSC)fordetailed oscillator circuit description. See Chapter 10 Timebase Module (TBM) for detailed description on TBM. 6.3.2 Phase-Locked Loop Circuit (PLL) ThePLLisafrequencygeneratorthatcanoperateineitheracquisitionmodeortrackingmode,depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually. 6.3.3 PLL Circuits The PLL consists of these circuits: • Voltage-controlled oscillator (VCO) • Reference divider • Frequency pre-scaler • Modulo VCO frequency divider MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 81

Clock Generator Module (CGM) • Phase detector • Loop filter • Lock detector The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunitytoexternalnoise,includingsupplyandCGMXFCnoise.TheVCOfrequencyisboundtoarange from roughly one-half to twice the center-of-range frequency, f . Modulating the voltage on the VRS CGMXFC pin changes the frequency within this range. By design, f is equal to the nominal VRS center-of-range frequency, f , (125 kHz) times a linear factor, L, and a power-of-two factor, E, or NOM (L×2E)f . NOM CGMRCLKisthePLLreferenceclock,abufferedversionofCGMXCLK.CGMRCLKrunsatafrequency, f ,andisfedtothePLLthroughaprogrammablemoduloreferencedivider,whichdividesf bya RCLK RCLK factor, R. The divider’s output is the final reference clock, CGMRDV, running at a frequency, f = f /R. With an external crystal RDV RCLK (30kHz–100kHz), always set R = 1 for specified performance. With an external high-frequency clock source, use R to divide the external frequency to between 30kHz and 100kHz. TheVCO’soutputclock,CGMVCLK,runningatafrequency,f ,isfedbackthroughaprogrammable VCLK pre-scaler divider and a programmable modulo divider. The pre-scaler divides the VCO clock by a power-of-twofactorP(theCGMPCLK)andthemodulodividerreducestheVCOclockbyafactor,N.The dividers’outputistheVCOfeedbackclock,CGMVDV,runningatafrequency,f = f /(N × 2P).(See VDV VCLK 6.3.6 Programming the PLL for more information.) The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV.Acorrectionpulseisgeneratedbasedonthephasedifferencebetweenthetwosignals.The loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on thewidthanddirectionofthecorrectionpulse.Thefiltercanmakefastorslowcorrectionsdependingon itsmode,describedin6.3.4AcquisitionandTrackingModes.Thevalueoftheexternalcapacitorandthe reference frequency determines the speed of the corrections and the stability of the PLL. The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, f . The circuit determines the mode of the PLL and the lock condition based on RDV this comparison. 6.3.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCOfrequencyisfaroffthedesiredfrequency.Wheninacquisitionmode,theACQbitisclearin the PLL bandwidth control register. (See 6.5.2 PLL Bandwidth Control Register.) • Trackingmode—Intrackingmode,thefiltermakesonlysmallcorrectionstothefrequencyofthe VCO.PLLjitterismuchlowerintrackingmode,buttheresponsetonoiseisalsoslower.ThePLL enterstrackingmodewhentheVCOfrequencyisnearlycorrect,suchaswhenthePLLisselected as the base clock source. (See 6.3.8 Base Clock Selector Circuit.) The PLL is automatically in tracking mode when not in acquisition mode or when the ACQ bit is set. MC68HC908AP Family Data Sheet, Rev. 4 82 Freescale Semiconductor

Functional Description 6.3.5 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. Automatic mode is recommended for most users. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 6.5.2 PLL Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually) or at periodic intervals. In either case, when the LOCK bit is set,theVCOclockissafetouseasthesourceforthebaseclock.(See6.3.8BaseClockSelectorCircuit.) IftheVCOisselectedasthesourceforthebaseclockandtheLOCKbitisclear,thePLLhassuffereda severe noise hit and the software must take appropriate action, depending on the application. (See 6.6 Interrupts for information and precautions on using interrupts.) The following conditions apply when the PLL is in automatic bandwidth control mode: • The ACQ bit (See 6.5.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of the filter. (See 6.3.4 Acquisition and Tracking Modes.) • TheACQbitissetwhentheVCOfrequencyiswithinacertaintoleranceandisclearedwhenthe VCO frequency is out of a certain tolerance. (See 6.8 Acquisition/Lock Time Specifications for more information.) • The LOCK bit is a read-only indicator of the locked state of the PLL. • TheLOCKbitissetwhentheVCOfrequencyiswithinacertaintoleranceandisclearedwhenthe VCO frequency is out of a certain tolerance. (See 6.8 Acquisition/Lock Time Specifications for more information.) • CPUinterruptscanoccurifenabled(PLLIE=1)whenthePLL’slockconditionchanges,toggling the LOCK bit. (See 6.5.1 PLL Control Register.) The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not requireanindicatorofthelockconditionforproperoperation.Suchsystemstypicallyoperatewellbelow f . BUSMAX The following conditions apply when in manual mode: • ACQisawritablecontrolbitthatcontrolsthemodeofthefilter.BeforeturningonthePLLinmanual mode, the ACQ bit must be clear. • Before entering tracking mode (ACQ = 1), software must wait a given time, t (See 6.8 ACQ Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL control register (PCTL). • Softwaremustwaitagiventime,t ,afterenteringtrackingmodebeforeselectingthePLLasthe AL clock source to CGMOUT (BCS = 1). • The LOCK bit is disabled. • CPU interrupts from the CGM are disabled. 6.3.6 Programming the PLL The following procedure shows how to program the PLL. NOTE The round function in the following equations means that the real number should be rounded to the nearest integer number. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 83

Clock Generator Module (CGM) 1. Choose the desired bus frequency, f , or the desired VCO frequency, f ; and then BUSDES VCLKDES solve for the other. The relationship between f and f is governed by the equation: BUS VCLK f = 2P×f = 2P×4 × f VCLK CGMPCLK BUS where P is the power of two multiplier, and can be 0, 1, 2, or 3 2. Choose a practical PLL reference frequency, f , and the reference clock divider, R. Typically, RCLK the reference is 32.768kHz and R = 1. FrequencyerrorstothePLLarecorrectedatarateoff /R.Forstabilityandlocktimereduction, RCLK this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate. The relationship between the VCO frequency, f , and the reference frequency, f ,is VCLK RCLK P 2 N f = -----------(f ) VCLK R RCLK where N is the integer range multiplier, between 1 and 4095. In cases where desired bus frequency has some tolerance, choose f to a value determined RCLK either by other module requirements (such as modules which are clocked by CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See Chapter 22 Electrical Specifications. Choose the reference divider, R = 1. When the tolerance on the bus frequency is tight, choose f to an integer divisor of f , RCLK BUSDES and R = 1. If f cannot meet this requirement, use the following equation to solve for R with RCLK practical choices of f , and choose the f that gives the lowest R. RCLK RCLK ⎧⎛f ⎞ ⎛f ⎞⎫ R = round R ×⎨⎜--V----C----L---K---D----E----S--⎟ –integer⎜--V----C----L---K---D----E----S--⎟⎬ MAX ⎩⎝ f ⎠ ⎝ f ⎠⎭ RCLK RCLK 3. Calculate N: ⎛R×f ⎞ N = round⎜-------------V----C---L---K----D----E---S---⎟ ⎝ f ×2P ⎠ RCLK 4. Calculate and verify the adequacy of the VCO and bus frequencies f and f . VCLK BUS P 2 N f = -----------(f ) VCLK R RCLK f --V---C--L---K- f = BUS 2P×4 MC68HC908AP Family Data Sheet, Rev. 4 84 Freescale Semiconductor

Functional Description 5. Select the VCO’s power-of-two range multiplier E, according to this table: Frequency Range E 0 < fVCLK < 9,830,400 0 9,830,400≤ fVCLK < 19,660,800 1 19,660,800≤ fVCLK < 39,321,600 2 NOTE: Do not program E to a value of 3. 6. Select a VCO linear range multiplier, L, where f = 125kHz NOM ⎛ f ⎞ L = round⎜--------V----C---L----K-------⎟ ⎝2E×f ⎠ NOM 7. CalculateandverifytheadequacyoftheVCOprogrammedcenter-of-rangefrequency,f .The VRS center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL. f = (L×2E)f VRS NOM For proper operation, f ×2E f –f ≤--N----O----M---------------- VRS VCLK 2 8. Verify the choice of P, R, N, E, and L by comparing f to f and f . For proper VCLK VRS VCLKDES operation,f mustbewithintheapplication’stoleranceoff ,andf mustbeasclose VCLK VCLKDES VRS as possible to f VCLK. NOTE Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. 9. Program the PLL registers accordingly: a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P. b. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E. c. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N. d. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L. e. InthePLLreferencedividerselectregister(PMDS),programthebinarycodedequivalentof R. NOTE ThevaluesforP,E,N,L,andRcanonlybeprogrammedwhenthePLLis off (PLLON = 0). Table 6-1 provides numeric examples (numbers are in hexadecimal notation): MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 85

Clock Generator Module (CGM) Table 6-1. Numeric Examples CGMVCLK CGMPCLK fBUS fRCLK R N P E L 8.0 MHz 8.0 MHz 2.0 MHz 32.768 kHz 1 F5 0 0 40 9.8304 MHz 9.8304 MHz 2.4576 MHz 32.768 kHz 1 12C 0 1 27 10.0 MHz 10.0 MHz 2.5 MHz 32.768 kHz 1 132 0 1 28 16 MHz 16 MHz 4.0 MHz 32.768 kHz 1 1E9 0 1 40 19.6608 MHz 19.6608 MHz 4.9152 MHz 32.768 kHz 1 258 0 2 27 20 MHz 20 MHz 5.0 MHz 32.768 kHz 1 263 0 2 28 29.4912 MHz 29.4912 MHz 7.3728 MHz 32.768 kHz 1 384 0 2 3B 32 MHz 32 MHz 8.0 MHz 32.768 kHz 1 3D1 0 2 40 32 MHz 16 MHz 4.0 MHz 32.768 kHz 1 1E9 1 2 40 32 MHz 8 MHz 2.0 MHz 32.768 kHz 1 F5 2 2 40 32 MHz 4 MHz 1.0 MHz 32.768 kHz 1 7B 3 2 40 6.3.7 Special Programming Exceptions The programming method described in 6.3.6 Programming the PLL does not account for three possible exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for these exceptions: • A 0 value for R or N is interpreted exactly the same as a value of 1. • A 0 value for L disables the PLL and prevents its selection as the source for the base clock. (See 6.3.8 Base Clock Selector Circuit.) 6.3.8 Base Clock Selector Circuit Thiscircuitisusedtoselecteithertheoscillatorclock,CGMXCLK,orthedividedVCOclock,CGMPCLK, asthesourceofthebaseclock,CGMOUT.Thetwoinputclocksgothroughatransitioncontrolcircuitthat waitsuptothreeCGMXCLKcyclesandthreeCGMPCLKcyclestochangefromoneclocksourcetothe other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then dividedbytwotocorrectthedutycycle.Therefore,thebusclockfrequency,whichisone-halfofthebase clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMPCLK). The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The divided VCO clockcannotbeselectedasthebaseclocksourceifthePLLisnotturnedon.ThePLLcannotbeturned off if the divided VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selectionordeselectionofthedividedVCOclock.ThedividedVCOclockalsocannotbeselectedasthe base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent withtheoperationofthePLL,sothatthePLLwouldbedisabledandtheoscillatorclockwouldbeforced as the source of the base clock. MC68HC908AP Family Data Sheet, Rev. 4 86 Freescale Semiconductor

I/O Signals 6.3.9 CGM External Connections In its typical configuration, the CGM requires up to four external components. Figure 6-3 shows the external components for the PLL: • Bypass capacitor, C BYP • Filter network Care should be taken with PCB routing in order to minimize signal cross talk and noise. (See 6.8 Acquisition/Lock Time Specifications for routing information, filter network and its effects on PLL performance.) MCU CGMXFC V V SSA DDA V DD 1 kΩ 10 nF CBYP 0.1µF 0.22µF Note: Filter network in box can be replaced with a 0.47µF capacitor, but will degrade stability. Figure 6-3. CGM External Connections 6.4 I/O Signals The following paragraphs describe the CGM I/O signals. 6.4.1 External Filter Capacitor Pin (CGMXFC) TheCGMXFCpinisrequiredbytheloopfiltertofilteroutphasecorrections.Anexternalfilternetworkis connected to this pin. (See Figure 6-3.) NOTE Topreventnoiseproblems,thefilternetworkshouldbeplacedascloseto the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network. 6.4.2 PLL Analog Power Pin (V ) DDA V is a power pin used by the analog portions of the PLL. Connect the V pin to the same voltage DDA DDA potential as the V pin. DD NOTE Route V carefully for maximum noise immunity and place bypass DDA capacitors as close as possible to the package. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 87

Clock Generator Module (CGM) 6.4.3 PLL Analog Ground Pin (V ) SSA V is a ground pin used by the analog portions of the PLL. Connect the V pin to the same voltage SSA SSA potential as the V pin. SS NOTE Route V carefully for maximum noise immunity and place bypass SSA capacitors as close as possible to the package. 6.4.4 Oscillator Output Frequency Signal (CGMXCLK) CGMXCLKistheoscillatoroutputsignal.Itrunsatthefullspeedoftheoscillator,andisgenerateddirectly from the crystal oscillator circuit, the RC oscillator circuit, or the internal oscillator circuit. 6.4.5 CGM Reference Clock (CGMRCLK) CGMRCLKisabufferedversionofCGMXCLK,thisclockisthereferenceclockforthephase-locked-loop circuit. 6.4.6 CGM VCO Clock Output (CGMVCLK) CGMVCLK is the clock output from the VCO. 6.4.7 CGM Base Clock Output (CGMOUT) CGMOUTistheclockoutputoftheCGM.ThissignalgoestotheSIM,whichgeneratestheMCUclocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the divided VCO clock, CGMPCLK, divided by two. 6.4.8 CGM CPU Interrupt (CGMINT) CGMINT is the interrupt signal generated by the PLL lock detector. 6.5 CGM Registers The following registers control and monitor operation of the CGM: • PLL control register (PCTL) (See 6.5.1 PLL Control Register.) • PLL bandwidth control register (PBWC) (See 6.5.2 PLL Bandwidth Control Register.) • PLL multiplier select registers (PMSH and PMSL) (See 6.5.3 PLL Multiplier Select Registers.) • PLL VCO range select register (PMRS) (See 6.5.4 PLL VCO Range Select Register.) • PLL reference divider select register (PMDS) (See 6.5.5 PLL Reference Divider Select Register.) MC68HC908AP Family Data Sheet, Rev. 4 88 Freescale Semiconductor

CGM Registers 6.5.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 6 5 4 3 2 1 Bit 0 Read: PLLF PLLIE PLLON BCS PRE1 PRE0 VPR1 VPR0 Write: Reset: 0 0 1 0 0 0 0 0 =Unimplemented Figure 6-4. PLL Control Register (PCTL) PLLIE — PLL Interrupt Enable Bit Thisread/writebitenablesthePLLtogenerateaninterruptrequestwhentheLOCKbittoggles,setting thePLLflag,PLLF.WhentheAUTObitinthePLLbandwidthcontrolregister(PBWC)isclear,PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit. 1 = PLL interrupts enabled 0 = PLL interrupts disabled PLLF — PLL Interrupt Flag Bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register(PBWC)isclear.ClearthePLLFbitbyreadingthePLLcontrolregister.ResetclearsthePLLF bit. 1 = Change in lock condition 0 = No change in lock condition NOTE Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 6.3.8 Base Clock Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off BCS — Base Clock Select Bit This read/write bit selects either the oscillator output, CGMXCLK, or the divided VCO clock, CGMPCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMPCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. (See 6.3.8 Base Clock Selector Circuit.) Reset clears the BCS bit. 1 = CGMPCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 89

Clock Generator Module (CGM) NOTE PLLON and BCS have built-in protection that prevents the base clock selectorcircuitfromselectingtheVCOclockasthesourceofthebaseclock ifthePLLisoff.Therefore,PLLONcannotbeclearedwhenBCSisset,and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMPCLK requires two writes to the PLL control register. (See 6.3.8 Base Clock Selector Circuit.) PRE1 and PRE0 — Prescaler Program Bits These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See 6.3.3 PLL Circuits and 6.3.6 Programming the PLL.) PRE1 and PRE0 cannot be written when the PLLON bit is set. Reset clears these bits. These prescaler bits affects the relationship between the VCO clock and the final system bus clock. Table 6-2. PRE1 and PRE0 Programming PRE1 and PRE0 P Prescaler Multiplier 00 0 1 01 1 2 10 2 4 11 3 8 VPR1 and VPR0 — VCO Power-of-Two Range Select Bits Theseread/writebitscontroltheVCO’shardwarepower-of-tworangemultiplierEthat,inconjunction with L (See 6.3.3 PLL Circuits, 6.3.6 Programming the PLL, and 6.5.4 PLL VCO Range Select Register.)controlsthehardwarecenter-of-rangefrequency,f .VPR1:VPR0cannotbewrittenwhen VRS the PLLON bit is set. Reset clears these bits. Table 6-3. VPR1 and VPR0 Programming VCO Power-of-Two VPR1 and VPR0 E Range Multiplier 00 0 1 01 1 2 10 2 4 NOTE: Do not program E to a value of 3. MC68HC908AP Family Data Sheet, Rev. 4 90 Freescale Semiconductor

CGM Registers 6.5.2 PLL Bandwidth Control Register The PLL bandwidth control register (PBWC): • Selects automatic or manual (software-controlled) bandwidth control mode • Indicates when the PLL is locked • In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode • In manual operation, forces the PLL into acquisition or tracking mode Address: $0037 Bit 7 6 5 4 3 2 1 Bit 0 Read: LOCK 0 0 0 0 AUTO ACQ R Write: Reset: 0 0 0 0 0 0 0 =Unimplemented R =Reserved Figure 6-5. PLL Bandwidth Control Register (PBWCR) AUTO — Automatic Bandwidth Control Bit Thisread/writebitselectsautomaticormanualbandwidthcontrol.WheninitializingthePLLformanual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK — Lock Indicator Bit WhentheAUTObitisset,LOCKisaread-onlybitthatbecomessetwhentheVCOclock,CGMVCLK, islocked(runningattheprogrammedfrequency).WhentheAUTObitisclear,LOCKreadsaslogic0 and has no meaning. The write one function of this bit is reserved for test, so this bit must always be written a 0. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ — Acquisition Mode Bit WhentheAUTObitisset,ACQisaread-onlybitthatindicateswhetherthePLLisinacquisitionmode ortrackingmode.WhentheAUTObitisclear,ACQisaread/writebitthatcontrolswhetherthePLLis in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is storedinatemporarylocationandisrecoveredwhenmanualoperationresumes.Resetclearsthisbit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 91

Clock Generator Module (CGM) 6.5.3 PLL Multiplier Select Registers The PLL multiplier select registers (PMSH and PMSL) contain the programming information for the modulo feedback divider. Address: $0038 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 MUL11 MUL10 MUL9 MUL8 Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 6-6. PLL Multiplier Select Register High (PMSH) Address: $0039 Bit 7 6 5 4 3 2 1 Bit 0 Read: MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 Write: Reset: 0 1 0 0 0 0 0 0 Figure 6-7. PLL Multiplier Select Register Low (PMSL) MUL[11:0] — Multiplier Select Bits Theseread/writebitscontrolthemodulofeedbackdividerthatselectstheVCOfrequencymultiplierN. (See 6.3.3 PLL Circuits and 6.3.6 Programming the PLL.) A value of $0000 in the multiplier select registers configure the modulo feedback divider the same as a value of $0001. Reset initializes the registers to $0040 for a default multiply value of 64. NOTE The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). 6.5.4 PLL VCO Range Select Register The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO. Address: $003A Bit 7 6 5 4 3 2 1 Bit 0 Read: VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0 Write: Reset: 0 1 0 0 0 0 0 0 Figure 6-8. PLL VCO Range Select Register (PMRS) VRS[7:0] — VCO Range Select Bits Theseread/writebitscontrolthehardwarecenter-of-rangelinearmultiplierLwhich,inconjunctionwith E(See6.3.3PLLCircuits,6.3.6ProgrammingthePLL,and6.5.1PLLControlRegister.),controlsthe hardware center-of-range frequency, f . VRS[7:0] cannot be written when the PLLON bit in the VRS PCTL is set. (See 6.3.7 Special Programming Exceptions.)A value of $00 in the VCO range select MC68HC908AP Family Data Sheet, Rev. 4 92 Freescale Semiconductor

Interrupts register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 6.3.8 Base Clock Selector Circuit and 6.3.7 Special Programming Exceptions.). Reset initializes the register to $40 for a default range multiply value of 64. NOTE TheVCOrangeselectbitshavebuilt-inprotectionsuchthattheycannotbe written when the PLL is on (PLLON = 1) and such that the VCO clock cannot be selected as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The PLL VCO range select register must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock. 6.5.5 PLL Reference Divider Select Register The PLL reference divider select register (PMDS) contains the programming information for the modulo reference divider. Address: $003B Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 RDS3 RDS2 RDS1 RDS0 Write: Reset: 0 0 0 0 0 0 0 1 =Unimplemented Figure 6-9. PLL Reference Divider Select Register (PMDS) RDS[3:0] — Reference Divider Select Bits Theseread/writebitscontrolthemoduloreferencedividerthatselectsthereferencedivisionfactor,R. (See6.3.3PLLCircuitsand6.3.6ProgrammingthePLL.)RDS[3:0]cannotbewrittenwhenthePLLON bit in the PCTL is set. A value of $00 in the reference divider select register configures the reference dividerthesameasavalueof$01.(See6.3.7SpecialProgrammingExceptions.)Resetinitializesthe register to $01 for a default divide value of 1. NOTE The reference divider select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). NOTE The default divide value of 1 is recommended for all applications. 6.6 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interruptrequesteverytimetheLOCKbitchangesstate.ThePLLIEbitinthePLLcontrolregister(PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interruptsareenabledornot.WhentheAUTObitisclear,CPUinterruptsfromthePLLaredisabledand PLLF reads as logic 0. SoftwareshouldreadtheLOCKbitafteraPLLinterruptrequesttoseeiftherequestwasduetoanentry into lock or an exit from lock. When the PLL enters lock, the divided VCO clock, CGMPCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 93

Clock Generator Module (CGM) VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequencysensitive,interruptsshouldbedisabledtopreventPLLinterruptserviceroutinesfromimpeding software performance or from exceeding stack limitations. NOTE SoftwarecanselecttheCGMPCLKdividedbytwoastheCGMOUTsource evenifthePLLisnotlocked(LOCK=0).Therefore,softwareshouldmake sure the PLL is locked before setting the BCS bit. 6.7 Special Modes The WAIT instruction puts the MCU in low power-consumption standby modes. 6.7.1 Wait Mode TheWAITinstructiondoesnotaffecttheCGM.Beforeenteringwaitmode,softwarecandisengageand turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power. Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is immediatelyavailableatWAITexit.ThiswouldbethecasealsowhenthePLListowaketheMCUfrom wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. 6.7.2 Stop Mode The STOP instruction disables the PLL analog circuits and no clock will be driven out of the VCO. When entering stop mode with the VCO clock (CGMPCLK) selected, before executing the STOP instruction: 1. Settheoscillatorstopmodeenablebit(STOP_XCLKENinCONFIG2)ifcontinuosclockisrequired in stop mode. 2. Clear the BCS bit to select CGMXCLK as CGMOUT. On exit from stop mode: 1. Set the PLLON bit if cleared before entering stop mode. 2. Wait for PLL to lock by checking the LOCK bit. 3. Set BCS bit to select CGMPCLK as CGMOUT. 6.7.3 CGM During Break Interrupts Thesystemintegrationmodule(SIM)controlswhetherstatusbitsinothermodulescanbeclearedduring the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 7.7.3 SIM Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its defaultstate),softwarecanreadandwritethePLLcontrolregisterduringthebreakstatewithoutaffecting the PLLF bit. MC68HC908AP Family Data Sheet, Rev. 4 94 Freescale Semiconductor

Acquisition/Lock Time Specifications 6.8 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 6.8.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. Therefore, the reactiontimeisconstantinthisdefinition,regardlessofthesizeofthestepinput.Forexample,consider a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from 0Hz to 1MHz, the acquisition time is the time taken for the frequency to reach 1MHz ±50kHz. 50kHz = 5% of the 1MHz step input. If the system is operating at 1MHz and suffers a –100kHz noise hit, the acquisitiontimeisthetimetakentoreturnfrom900kHzto1MHz ±5kHz. 5kHz = 5%ofthe100kHzstep input. Other systems refer to acquisition and lock times as the time the system takes to reduce the error betweentheactualoutputandthedesiredoutputtowithinspecifiedtolerances.Therefore,theacquisition orlocktimevariesaccordingtotheoriginalerrorintheoutput.Minorerrorsmaynotevenberegistered. TypicalPLLapplicationsprefertousethisdefinitionbecausethesystemrequirestheoutputfrequencyto be within a certain tolerance of the desired frequency regardless of the size of the initial error. 6.8.2 Parametric Influences on Reaction Time Acquisitionandlocktimesaredesignedtobeasshortaspossiblewhilestillprovidingthehighestpossible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. ThemostcriticalparameterwhichaffectsthereactiontimesofthePLListhereferencefrequency,f . RDV ThisfrequencyistheinputtothephasedetectorandcontrolshowoftenthePLLmakescorrections.For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make thesecorrections.Thisparameterisunderusercontrolviathechoiceofcrystalfrequencyf andthe XCLK Rvalueprogrammed inthe referencedivider.(See6.3.3PLL Circuits,6.3.6Programming thePLL, and 6.5.5 PLL Reference Divider Select Register.) Another critical parameter is the external filter network. The PLL modifies the voltage on the VCO by adding or subtracting charge from capacitors in this network. Therefore, the rate at which the voltage changesforagivenfrequencyerror(thuschangeincharge)isproportionaltothecapacitance.Thesize ofthecapacitoralsoisrelatedtothestabilityofthePLL.Ifthecapacitoristoosmall,thePLLcannotmake smallenoughadjustmentstothevoltageandthesystemcannotlock.Ifthecapacitoristoolarge,thePLL may not be able to adjust the voltage in a reasonable time. (See 6.8.3 Choosing a Filter.) Also important is the operating voltage potential applied to V . The power supply potential alters the DDA characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 95

Clock Generator Module (CGM) Temperatureandprocessingalsocanaffectacquisitiontimebecausetheelectricalcharacteristicsofthe PLL change. The part operates as specified as long as these influences stay within the specified limits. Externalfactors,however,cancausedrasticchangesintheoperationofthePLL.Thesefactorsinclude noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 6.8.3 Choosing a Filter Asdescribedin6.8.2ParametricInfluencesonReactionTime,theexternalfilternetworkiscriticaltothe stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. Either of the filter networks in Figure 6-10 is recommended when using a 32.768kHz reference clock (CGMRCLK). Figure 6-10(a)isused forapplications requiringbetterstability.Figure 6-10(b)isused in low-cost applications where stability is not critical. CGMXFC CGMXFC 1 kΩ 10 nF 0.22µF 0.22µF VSSA VSSA (a) (b) Figure 6-10. PLL Filter MC68HC908AP Family Data Sheet, Rev. 4 96 Freescale Semiconductor

Chapter 7 System Integration Module (SIM) 7.1 Introduction Thissectiondescribesthesystemintegrationmodule(SIM).TogetherwiththeCPU,theSIMcontrolsall MCU activities. A block diagram of the SIM is shown in Figure 7-1. Figure 7-2 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: • Bus clock generation and control for CPU and peripherals: – Stop/wait/reset/break entry and recovery – Internal clock control • Master reset control, including power-on reset (POR) and COP timeout • Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation • CPU enable/disable timing • Modular architecture expandable to 128 interrupt sources Table 7-1 shows the internal signal names used in this section. Table 7-1. Signal Name Conventions Signal Name Description ICLK Internal oscillator clock CGMXCLK Selected oscillator clock from oscillator module CGMVCLK, CGMPCLK PLL output and the divided PLL output CGMPCLK-based or oscillator-based clock output from CGM module CGMOUT (Bus clock=CGMOUT÷ 2) IAB Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 97

System Integration Module (SIM) MODULE STOP MODULE WAIT STOP/WAIT CPU STOP (FROM CPU) CONTROL CPU WAIT (FROM CPU) SIMOSCEN (TO CGM, OSC) SIM COP CLOCK COUNTER ICLK (FROM OSC) CGMOUT (FROM CGM) ÷2 V CLOCK DD CLOCK GENERATORS INTERNAL CLOCKS CONTROL INTERNAL PULLUP DEVICE RESET LVI (FROM LVI MODULE) POR CONTROL PIN LOGIC MASTER ILLEGAL OPCODE (FROM CPU) RESET PIN CONTROL RESET ILLEGAL ADDRESS (FROM ADDRESS CONTROL MAP DECODERS) SIM RESET STATUS REGISTER COP (FROM COP MODULE) RESET INTERRUPT SOURCES INTERRUPT CONTROL AND PRIORITY DECODE CPU INTERFACE Figure 7-1. SIM Block Diagram Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: SBSW SIM Break Status Register R R R R R R R $FE00 Write: NOTE (SBSR) Reset: 0 0 0 0 0 0 0 0 Note: Writing a logic 0 clears SBSW. Read: POR PIN COP ILOP ILAD MODRST LVI 0 SIM Reset Status Register $FE01 Write: (SRSR) POR: 1 0 0 0 0 0 0 0 Read: SIM Break Flag Control BCFE R R R R R R R $FE03 Write: Register (SBFCR) Reset: 0 Figure 7-2. SIM I/O Register Summary MC68HC908AP Family Data Sheet, Rev. 4 98 Freescale Semiconductor

SIM Bus Clock Control and Generation Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Interrupt Status Register1 $FE04 Write: R R R R R R R R (INT1) Reset: 0 0 0 0 0 0 0 0 Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Interrupt Status Register2 $FE05 Write: R R R R R R R R (INT2) Reset: 0 0 0 0 0 0 0 0 Read: 0 IF21 IF20 IF19 IF18 IF17 IF16 IF15 Interrupt Status Register3 $FE06 Write: R R R R R R R R (INT3) Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 7-2. SIM I/O Register Summary 7.2 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The systemclocksaregeneratedfromanincomingclock,CGMOUT,asshowninFigure 7-3.Thisclockcan comefromeitheranexternaloscillatororfromtheon-chipPLL.(SeeChapter6ClockGeneratorModule (CGM).) OSC2 OSCCLK TO TBM OSCILLATOR (OSC) MODULE CGMXCLK OSC1 TO TIM, ADC ICLK SIM COUNTER SIMOSCEN STOP MODE CLOCK ENABLE SIGNALS FROM CONFIG2 CGMRCLK SYSTEM INTEGRATION MODULE IT12 TO REST OF MCU CGMOUT ÷ 2 BUS CLOCK IT23 GENERATORS TO REST PHASE-LOCKED LOOP (PLL) OF MCU PTB0 SIMDIV2 MONITOR MODE USER MODE CGMVCLK TO PWM Figure 7-3. CGM Clock Signals 7.2.1 Bus Timing Inusermode,theinternalbusfrequencyiseithertheoscillatoroutput(CGMXCLK)dividedbyfourorthe divided PLL output (CGMPCLK) divided by four. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 99

System Integration Module (SIM) 7.2.2 Clock Start-up from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 ICLK cycle POR timeouthascompleted.TheRSTpinisdrivenlowbytheSIMduringthisentireperiod.TheIBUSclocks start upon completion of the timeout. 7.2.3 Clocks in Stop Mode and Wait Mode Uponexitfromstopmodebyaninterrupt,break,orreset,theSIMallowsICLKtoclocktheSIMcounter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 ICLK cycles. (See 7.6.2 Stop Mode.) Inwaitmode,theCPUclocksareinactive.TheSIMalsoproducestwosetsofclocksforothermodules. Refertothewaitmodesubsectionofeachmoduletoseeifthemoduleisactiveorinactiveinwaitmode. Some modules can be programmed to be active in wait mode. 7.3 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • Illegal address All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 7.4 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 7.7 SIM Registers.) 7.3.1 External Pin Reset The RST pin circuit includes an internal pull-up device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimumof67ICLKcycles,assumingthatneitherthePORnortheLVIwasthesourceofthereset.See Table 7-2 for details. Figure 7-4 shows the relative timing. Table 7-2. PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR/LVI 4163 (4096 + 64 + 3) All others 67 (64 + 3) MC68HC908AP Family Data Sheet, Rev. 4 100 Freescale Semiconductor

Reset and System Initialization ICLK RST IAB PC VECT H VECT L Figure 7-4. External Reset Timing 7.3.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 ICLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 7-5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR (see Figure 7-6). NOTE For LVI or POR resets, the SIM cycles through 4096 + 32 ICLK cycles duringwhichtheSIMforcestheRSTpinlow.Theinternalresetsignalthen follows the sequence from the falling edge of RST shown in Figure 7-5. IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES ICLK IAB VECTOR HIGH Figure 7-5. Internal Reset Timing The COP reset is asynchronous to the bus clock. ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET LVI POR Figure 7-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 7.3.2.1 Power-On Reset WhenpowerisfirstappliedtotheMCU,thepower-onresetmodule(POR)generatesapulsetoindicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 ICLK cycles. Thirty-two ICLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 101

System Integration Module (SIM) At power-on, these events occur: • A POR pulse is generated. • The internal reset signal is asserted. • The SIM enables CGMOUT. • InternalclockstotheCPUandmodulesareheldinactivefor4096ICLKcyclestoallowstabilization of the oscillator. • The pin is driven low during the oscillator stabilization time. • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. OSC1 PORRST 4096 32 32 CYCLES CYCLES CYCLES ICLK CGMOUT RST IRST IAB $FFFE $FFFF Figure 7-7. POR Recovery 7.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internalresetandsetstheCOPbitintheSIMresetstatusregister(SRSR).TheSIMactivelypullsdown the RST pin for all internal reset sources. To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears theCOPcounterandbits12through5oftheSIMcounter.TheSIMcounteroutput,whichoccursatleast every 213 – 24 ICLK cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. The COP module is disabled if the RST pin or the IRQ1 pin is held at V while the MCU is in monitor TST mode. The COP module can be disabled only through combinational logic conditioned with the high voltagesignalontheRSTortheIRQ1pin.ThispreventstheCOPfrombecomingdisabledasaresultof external noise. During a break state, V on the RST pin disables the COP module. TST 7.3.2.3 Illegal Opcode Reset TheSIM decodes signalsfrom the CPUto detectillegal instructions.Anillegal instruction setsthe ILOP bit in the SIM reset status register (SRSR) and causes a reset. MC68HC908AP Family Data Sheet, Rev. 4 102 Freescale Semiconductor

SIM Counter Ifthestopenablebit,STOP,inthemaskoptionregisterislogic0,theSIMtreatstheSTOPinstructionas an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 7.3.2.4 Illegal Address Reset Anopcodefetchfromanunmappedaddressgeneratesanillegaladdressreset.TheSIMverifiesthatthe CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resettingtheMCU.Adatafetchfromanunmappedaddressdoesnotgenerateareset.TheSIMactively pulls down the RST pin for all internal reset sources. 7.3.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the V voltage falls to the DD LVI voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin TRIPF (RST)isheldlowwhiletheSIMcountercountsout4096+32ICLKcycles.Thirty-twoICLKcycleslater, theCPUisreleasedfromresettoallowtheresetvectorsequencetooccur.TheSIMactivelypullsdown the RST pin for all internal reset sources. 7.3.2.6 Monitor Mode Entry Module Reset ThemonitormodeentrymoduleresetassertsitsoutputtotheSIMwhenmonitormodeisenteredinthe conditionwheretheresetvectorsareblank($FF).(SeeChapter8MonitorROM(MON).)WhenMODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all internal reset sources. 7.4 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillatortimetostabilizebeforeenablingtheinternalbus(IBUS)clocks.TheSIMcounteralsoservesas a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the clock for the COP module. The SIM counter is 13 bits long and is clocked by the falling edge of CGMXCLK. 7.4.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit assertsthesignalPORRST.OncetheSIMisinitialized,itenablestheclockgenerationmodule(CGM)to drive the bus clock state machine. 7.4.2 SIM Counter During Stop Mode Recovery TheSIMcounteralsoisusedforstopmoderecovery.TheSTOPinstructionclearstheSIMcounter.After aninterrupt,break,orreset,theSIMsensesthestateoftheshortstoprecoverybit,SSREC,inthemask option register. If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillatorsthatdonotrequirelongstart-uptimesfromstopmode.Externalcrystalapplicationsshoulduse the full stop recovery time, that is, with SSREC cleared. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 103

System Integration Module (SIM) 7.4.3 SIM Counter and Reset States External reset has no effect on the SIM counter. (See 7.6.2 Stop Mode for details.) The SIM counter is free-runningafterallresetstates.(See7.3.2ActiveResetsfromInternalSourcesforcountercontroland internal reset recovery sequences.) 7.5 Exception Control Normal, sequential program execution can be changed in three different ways: • Interrupts: – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts 7.5.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interruptmask(Ibit)topreventadditionalinterrupts.Attheendofaninterrupt,theRTIinstructionrecovers the CPU register contents from the stack so that normal processing can resume. Figure 7-8 shows interrupt entry timing, and Figure 7-9 shows interrupt recovery timing. MODULE INTERRUPT I-BIT IAB DUMMY SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR IDB DUMMY PC – 1[7:0] PC – 1[15:8] X A CCR V DATA H V DATA L OPCODE R/W Figure 7-8. Interrupt Entry Timing MODULE INTERRUPT I-BIT IAB SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1 IDB CCR A X PC – 1[15:8] PC – 1[7:0] OPCODE OPERAND R/W Figure 7-9. Interrupt Recovery Timing Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitrationresultisaconstantthattheCPUusestodeterminewhichvectortofetch.Onceaninterruptis latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). (See Figure 7-10.) MC68HC908AP Family Data Sheet, Rev. 4 104 Freescale Semiconductor

Exception Control FROM RESET I BBIRT ESAEKT? YES INTERRUPT? NO YES I-BIT SET? NO IRQ1 YES INTERRUPT? NO STACK CPU REGISTERS SET I-BIT AS MANY INTERRUPTS LOAD PC WITH INTERRUPT VECTOR AS EXIST ON CHIP FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 7-10. Interrupt Processing 7.5.1.1 Hardware Interrupts Ahardwareinterruptdoesnotstopthecurrentinstruction.Processingofahardwareinterruptbeginsafter completionofthecurrentinstruction.Whenthecurrentinstructioniscomplete,theSIMchecksallpending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the correspondinginterruptenablebitisset,theSIMproceedswithinterruptprocessing;otherwise,thenext instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt isservicedfirst.Figure 7-11demonstrateswhathappenswhentwointerruptsarepending.Ifaninterrupt ispendinguponexitfromtheoriginalinterruptserviceroutine,thependinginterruptisservicedbeforethe LDA instruction is executed. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 105

System Integration Module (SIM) CLI BACKGROUND LDA#$FF ROUTINE INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Figure 7-11 Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. 7.5.1.2 SWI Instruction TheSWI instructionisa non-maskable instructionthat causes aninterruptregardless ofthe state ofthe interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. 7.5.2 Interrupt Status Registers Theflagsintheinterruptstatusregistersidentifymaskableinterruptsources.Table 7-3summarizesthe interruptsourcesandtheinterruptstatusregisterflagsthattheyset.Theinterruptstatusregisterscanbe useful for debugging. MC68HC908AP Family Data Sheet, Rev. 4 106 Freescale Semiconductor

Exception Control 7.5.2.1 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R =Reserved Figure 7-12. Interrupt Status Register 1 (INT1) IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Table 7-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0 and Bit 1 — Always read 0 7.5.2.2 Interrupt Status Register 2 Address: $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R =Reserved Figure 7-13. Interrupt Status Register 2 (INT2) IF14–IF7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from the sources shown in Table 7-3. 1 = Interrupt request present 0 = No interrupt request present 7.5.2.3 Interrupt Status Register 3 Address: $FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 IF21 IF20 IF19 IF18 IF17 IF16 IF15 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R =Reserved Figure 7-14. Interrupt Status Register 3 (INT3) IF21–IF15 — Interrupt Flags 21–15 These flags indicate the presence of an interrupt request from the source shown in Table 7-3. 1 = Interrupt request present 0 = No interrupt request present MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 107

System Integration Module (SIM) Table 7-3. Interrupt Sources INT Vector Priority Interrupt Source Flag Address Lowest $FFD0 — Reserved $FFD1 $FFD2 IF21 Timebase $FFD3 $FFD4 IF20 Infrared SCI Transmit $FFD5 $FFD6 IF19 Infrared SCI Receive $FFD7 $FFD8 IF18 Infrared SCI Error $FFD9 $FFDA IF17 SPI Transmit $FFDB $FFDC IF16 SPI Receive $FFDD $FFDE IF15 ADC Conversion Complete $FFDF $FFE0 IF14 Keyboard $FFE1 $FFE2 IF13 SCI Transmit $FFE3 $FFE4 IF12 SCI Receive $FFE5 $FFE6 IF11 SCI Error $FFE7 $FFE8 IF10 MMIIC $FFE9 $FFEA IF9 TIM2 Overflow $FFEB $FFEC IF8 TIM2 Channel 1 $FFED $FFEE IF7 TIM2 Channel 0 $FFEF $FFF0 IF6 TIM1 Overflow $FFF1 $FFF2 IF5 TIM1 Channel 1 $FFF3 $FFF4 IF4 TIM1 Channel 0 $FFF5 $FFF6 IF3 PLL $FFF7 $FFF8 IF2 IRQ2 $FFF9 $FFFA IF1 IRQ1 $FFFB $FFFC — SWI $FFFD $FFFE — Reset Highest $FFFF MC68HC908AP Family Data Sheet, Rev. 4 108 Freescale Semiconductor

Low-Power Modes 7.5.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 7.5.4 Break Interrupts The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (See Chapter 21 Break Module (BRK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. 7.5.5 Status Flag Protection in Break Mode TheSIMcontrolswhetherstatusflagscontainedinothermodulescanbeclearedduringbreakmode.The usercanselectwhetherflagsareprotectedfrombeingclearedbyproperlyinitializingthebreakclearflag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains clearedevenwhenbreakmodeisexited.Statusflagswitha2-stepclearingmechanism—forexample, a read of one register followed by the read or write of another — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal. 7.6 Low-Power Modes Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is describedinthefollowingsubsections.BothSTOPandWAITcleartheinterruptmask(I)inthecondition code register, allowing interrupts to occur. 7.6.1 Wait Mode Inwaitmode,theCPUclocksareinactivewhiletheperipheralclockscontinuetorun.Figure 7-15shows the timing for wait mode entry. AmodulethatisactiveduringwaitmodecanwakeuptheCPUwithaninterruptiftheinterruptisenabled. StackingfortheinterruptbeginsonecycleaftertheWAITinstructionduringwhichtheinterruptoccurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Waitmodealsocanbeexitedbyaresetorbreak.AbreakinterruptduringwaitmodesetstheSIMbreak stop/waitbit,SBSW,intheSIMbreakstatusregister(SBSR).IftheCOPdisablebit,COPD,inthemask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 109

System Integration Module (SIM) IAB WAIT ADDR WAIT ADDR + 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME SAME R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 7-15. Wait Mode Entry Timing Figure 7-16 and Figure 7-17 show the timing for WAIT recovery. IAB $6E0B $6E0C $00FF $00FE $00FD $00FC IDB $A6 $A6 $A6 $01 $0B $6E EXITSTOPWAIT NOTE: EXITSTOPWAIT =RST pin OR CPU interrupt OR break interrupt Figure 7-16. Wait Recovery from Interrupt or Break 32 32 CYCLES CYCLES IAB $6E0B RST VCT H RST VCT L IDB $A6 $A6 $A6 RST ICLK Figure 7-17. Wait Recovery from Internal Reset 7.6.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a modulecancauseanexitfromstopmode.Stackingforinterruptsbeginsaftertheselectedstoprecovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the clock generator module output (CGMOUT) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1).IfSSRECisset,stoprecoveryisreducedfromthenormaldelayof4096ICLKcyclesdown to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. NOTE External crystal applications should use the full stop recovery time by clearing the SSREC bit. MC68HC908AP Family Data Sheet, Rev. 4 110 Freescale Semiconductor

SIM Registers A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 7-18 shows stop mode entry timing. NOTE Tominimizestopcurrent,allpinsconfiguredasinputsshouldbedrivento a logic 1 or logic 0. CPUSTOP IAB STOP ADDR STOP ADDR + 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME SAME R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. Figure 7-18. Stop Mode Entry Timing STOP RECOVERY PERIOD ICLK INT/BREAK IAB STOP +1 STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 7-19. Stop Mode Recovery from Interrupt or Break 7.7 SIM Registers The SIM has three memory-mapped registers: • SIM Break Status Register (SBSR) — $FE00 • SIM Reset Status Register (SRSR) — $FE01 • SIM Break Flag Control Register (SBFCR) — $FE03 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 111

System Integration Module (SIM) 7.7.1 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop mode or wait mode. Address: $FE00 Bit 7 6 5 4 3 2 1 Bit 0 Read: SBSW R R R R R R R Write: Note Reset: 0 Note: Writing a logic 0 clears SBSW. R =Reserved Figure 7-20. SIM Break Status Register (SBSR) SBSW — Break Wait Bit Thisstatusbitissetwhenabreakinterruptcausesanexitfromwaitmodeorstopmode.ClearSBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSWcanbereadwithinthebreakinterruptroutine.Theusercanmodifythereturnaddressonthestack by subtracting 1 from it. The following code is an example. This code works if the H register has been pushed onto the stack in the break service routine software. This code should be executed at the end of the break service routine software. HIBYTE EQU 5 LOBYTE EQU 6 If not SBSW, do RTI BRCLR SBSW,SBSR, RETURN ;See if wait mode or stop mode was exited by ;break. TST LOBYTE,SP ;If RETURNLO is not zero, BNE DOLO ;then just decrement low byte. DEC HIBYTE,SP ;Else deal with high byte, too. DOLO DEC LOBYTE,SP ;Point to WAIT/STOP opcode. RETURN PULH ;Restore H register. RTI MC68HC908AP Family Data Sheet, Rev. 4 112 Freescale Semiconductor

SIM Registers 7.7.2 SIM Reset Status Register This register contains six flags that show the source of the last reset provided all previous reset status bitshavebeencleared.CleartheSIMresetstatusregisterbyreadingit.Apower-onresetsetsthePOR bit and clears all other bits in the register. Address: $FE01 Bit 7 6 5 4 3 2 1 Bit 0 Read: POR PIN COP ILOP ILAD MODRST LVI 0 Write: Reset: 1 0 0 0 0 0 0 0 =Unimplemented Figure 7-21. SIM Reset Status Register (SRSR) POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST — Monitor Mode Entry Module Reset Bit 1=Lastresetcausedbymonitormodeentrywhenvectorlocations$FFFEand$FFFFare$FFafter POR while IRQ1 = V DD 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 113

System Integration Module (SIM) 7.7.3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read: BCFE R R R R R R R Write: Reset: 0 R =Reserved Figure 7-22. SIM Break Flag Control Register (SBFCR) BCFE — Break Clear Flag Enable Bit Thisread/writebitenablessoftwaretoclearstatusbitsbyaccessingstatusregisterswhiletheMCUis in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break MC68HC908AP Family Data Sheet, Rev. 4 114 Freescale Semiconductor

Chapter 8 Monitor ROM (MON) 8.1 Introduction ThissectiondescribesthemonitorROM(MON)andthemonitormodeentrymethods.ThemonitorROM allows complete testing of the MCU through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, V , as long as vector addresses $FFFE TST and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. Inaddition,tosimplifyusercoding,routinesarealsostoredinthemonitorROMareaforFLASHmemory program /erase. 8.2 Features Features of the monitor ROM include: • Normal user-mode pin functionality • One pin dedicated to serial communication between monitor ROM and host computer • Standard mark/space non-return-to-zero (NRZ) communication with host computer • Execution of code in RAM or FLASH • FLASH memory security feature(1) • 959 bytes monitor ROM code size ($FC00–$FDFF and $FE10–$FFCE) • Monitormodeentrywithouthighvoltage,V ,ifresetvectorisblank($FFFEand$FFFFcontain TST $FF) • Standard monitor mode entry if high voltage, V , is applied to IRQ1 TST • Resident routines for in-circuit programming 8.3 Functional Description ThemonitorROMreceivesandexecutescommandsfromahostcomputer.Figure 8-1showsanexample circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shiftingandmultiplexinginterfaceisrequiredbetweenPTA0andthehostcomputer.PTA0isused in a wired-OR configuration and requires a pullup resistor. 1.Nosecurityfeatureisabsolutelysecure.However,Freescale’sstrategyistomakereadingorcopyingtheFLASHdifficultfor unauthorized users. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 115

Monitor ROM (MON) RST 0.1µF V HC908AP DD V DD 0.1µF VDDA V REFH V REG V REFL VREG VSS 4.9152MHz/9.8304MHz V (50% DUTY) SSA OSC1 CGMXFC 0.01µF 10k MUST BE USED IF SW2 IS AT POSITION C. 0.033µF CONNECT TO OSC1, WITH OSC2 UNCONNECTED. EXT OSC 4.9152MHz OSC1 6–30 pF 1M MAX232 V DD OSC2 1 16 C1+ VCC 6–30 pF + + 1µF 1µF 3 C1– GND 15 1µF + XTAL CIRCUIT 4 2 VTST C SW2 C2+ V+ (SEE NOTE 1) 1µF + 6 VDD 1k 8.5 V IRQ1 V– D 5 C2– 1µF VDD + 10 k 10k DB9 74HC125 2 7 10 6 5 PTA0 74HC125 3 8 9 2 3 4 VDD VDD 1 5 10k 10k A SW1 PTA1 (SEE NOTE 2) PTB0 NOTES: B PTA2 1. Monitor mode entry method: 10 k SW2: Position C — High voltage entry (V ); must use external OSC 10 k TST Bus clock depends on SW1 (note 2). SW2: Position D — Reset vector must be blank ($FFFE:$FFFF = $FF) Bus clock = 1.2288MHz. 2. Affects high voltage entry to monitor mode only (SW2 at position C): SW1: Position A — Bus clock = OSC1 4 SW1: Position B — Bus clock = OSC1 2 5. SeeTable22-4 for V voltage level requirements. TST Figure 8-1. Monitor Mode Circuit MC68HC908AP Family Data Sheet, Rev. 4 116 Freescale Semiconductor

Functional Description 8.3.1 Entering Monitor Mode Table 8-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If $FFFE and $FFFF do not contain $FF (programmed state): – The external clock is 4.9152 MHz with PTB0 low or 9.8304 MHz with PTB0 high – IRQ1 = V TST 2. If $FFFE and $FFFF both contain $FF (erased state): – The external clock is 9.8304 MHz – IRQ1 = V (this can be implemented through the internal IRQ1 pullup DD 3. If $FFFE and $FFFF both contain $FF (erased state): – The external clock is 32.768 kHz (crystal) – IRQ1 = V (this setting initiates the PLL to boost the external 32.768 kHz to an internal bus SS frequency of 2.4576 MHz If V is applied to IRQ1 and PTB0 is low upon monitor mode entry (above condition set 1), the bus TST frequency is a divide-by-two of the input clock. If PTB0 is high with V applied to IRQ1 upon monitor TST modeentry,thebusfrequencywillbeadivide-by-fouroftheinputclock.HoldingthePTB0pinlowwhen entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if V is applied TST toIRQ1.Inthisevent,theCGMOUTfrequencyisequaltotheCGMXCLKfrequency,andtheOSC1input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. If entering monitor mode without high voltage on IRQ1 (above condition set 2, where applied voltage is either V ), then all port A pin requirements and conditions, including the PTB0 frequency divisor DD selection,arenotineffect.Thisistoreducecircuitrequirementswhenperformingin-circuitprogramming. NOTE Iftheresetvectorisblankandmonitormodeisentered,thechipwillseean additional reset cycle after the initial POR reset. Once the part has been programmed, the traditional method of applying a voltage, V , to IRQ1 TST must be used to enter monitor mode. The COP module is disabled in monitor mode based on these conditions: • Ifmonitormodewasenteredasaresultoftheresetvectorbeingblank(aboveconditionset2 or 3), the COP is always disabled regardless of the state of IRQ1 or RST. • IfmonitormodewasenteredwithV onIRQ1(conditionset1),thentheCOPisdisabledaslong TST as V is applied to either IRQ1 or RST. TST The second condition states that as long as V is maintained on the IRQ1 pin after entering monitor TST mode,orifV isappliedtoRSTaftertheinitialresettogetintomonitormode(whenV wasapplied TST TST toIRQ1),thentheCOPwillbedisabled.Inthelattersituation,afterV isappliedtotheRSTpin,V TST TST can be removed from the IRQ1 pin in the interest of freeing the IRQ1 for normal functionality in monitor mode. Figure 8-2showsasimplifieddiagramofthemonitormodeentrywhentheresetvectorisblankandjust V voltageisappliedtotheIRQ1pin.Anexternaloscillatorof9.8304MHzisrequiredforabaudrateof DD 9600, as the internal bus frequency is automatically set to the external frequency divided by four. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 117

1 M 18 on Table 8-1. Monitor Mode Signal Requirements and Options ito r R Address O PTA0 External Bus Baud M IRQ1 RST $FFFE/ PTA2 PTA1 (1) PTB0 Clock(2) Frequency PLL COP Rate Comment (M $FFFF O N No operation until ) X GND X X X X X X 0 X Disabled 0 reset goes high PTA1 and PTA2 voltages only V DD 4.9152 2.4576 required if V (3) or X 0 1 1 0 OFF Disabled 9600 TST V MHz MHz IRQ1 = VTST; TST PTB0 determines M C frequency divider 6 8 H PTA1 and PTA2 C 9 voltages only 0 V 8AP Fa VTST(3) VoTDSrDT X 0 1 1 1 9M.8H30z4 2M.4H57z6 OFF Disabled 9600 rIPReTqQBu10ir e=dd eV tiTfeSrmT;ines m ily frequency divider D a Blank 9.8304 2.4576 External frequency ta VDD VDD "$FFFF" X X 1 X MHz MHz OFF Disabled 9600 always divided by 4 S h e PLL enabled e Blank 32.768 2.4576 t, R GND VDD "$FFFF" X X 1 X kHz MHz ON Disabled 9600 (BCS set) e in monitor mode v . 4 Enters user V DD Blank mode — will or VTST "$FFFF" X X X X X — OFF Enabled — encounter an illegal GND address reset VDD VDD F or or Not Blank X X X X X — OFF Enabled — Enters user mode re es GND VTST c a le 1. PTA0 = 1 if serial communication; PTA0 = 0 if parallel communication S 2. External clock is derived by a 32.768kHz crystal or a 4.9152/9.8304MHz off-chip oscillator. e m 3. Monitor mode entry by IRQ1= V , a 4.9152/9.8304 MHz off-chip oscillator must be used. The MCU internal crystal oscillator circuit is by- TST ic passed. o n d u c to r

Functional Description Enter monitor mode with pin configuration shown in Figure 8-1 by pulling RST low and then high. The risingedgeofRSTlatchesmonitormode.Oncemonitormodeislatched,thevaluesonthespecifiedpins can change. Once out of reset, the MCU waits for the host to send eight security bytes. (See 8.4 Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic 0’s) to the host, indicating that it is ready to receive a command. POR RESET IS VECTOR NO NORMAL USER BLANK? MODE YES MONITOR MODE EXECUTE MONITOR CODE POR NO TRIGGERED? YES Figure 8-2. Low-Voltage Monitor Mode Entry Flowchart In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. NOTE Exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (POR). Pulling RST low will not exit monitor mode in this situation. Table 8-2 summarizes the differences between user mode and monitor mode vectors. Table 8-2. Mode Differences (Vectors) Functions Modes Reset Reset Break Break SWI SWI Vector Vector Vector Vector Vector Vector High Low High Low High Low User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 119

Monitor ROM (MON) 8.3.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT BIT Figure 8-3. Monitor Data Format 8.3.3 Break Signal Astartbit(logic0)followedbyninelogic0bitsisabreaksignal.Whenthemonitorreceivesabreaksignal, it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal. MISSING STOP BIT 2-STOP BIT DELAYBEFORE ZERO ECHO 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Figure 8-4. Break Transaction 8.3.4 Baud Rate ThecommunicationbaudrateiscontrolledbythecrystalfrequencyandthestateofthePTB0pin(when IRQ1issettoV )uponentryintomonitormode.WhenPTB0ishigh,thedividebyratiois1024.Ifthe TST PTB0 pin is at logic 0 upon entry into monitor mode, the divide by ratio is 512. IfmonitormodewasenteredwithV onIRQ1,thenthedividebyratioissetat1024,regardlessofPTB0. DD This condition for monitor mode entry requires that the reset vector is blank. Table 8-3 lists external frequencies required to achieve a standard baud rate of 9600 BPS. Other standard baud rates can be accomplished using proportionally higher or lower frequency generators. If using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module can handle. Table 8-3. Monitor Baud Rate Selection External Internal Baud Rate IRQ1 PTB0 Frequency Frequency (BPS) 4.9152 MHz VTST 0 2.4576 MHz 9600 9.8304 MHz VTST 1 2.4576 MHz 9600 9.8304 MHz VDD X 2.4576 MHz 9600 32.768 kHz VSS X 2.4576 MHz 9600 MC68HC908AP Family Data Sheet, Rev. 4 120 Freescale Semiconductor

Functional Description 8.3.5 Commands The monitor ROM firmware uses these commands: • READ (read memory) • WRITE (write memory) • IREAD (indexed read) • IWRITE (indexed write) • READSP (read stack pointer) • RUN (run user program) ThemonitorROMfirmwareechoeseachreceivedbytebacktothePTA0pinforerrorchecking.An11-bit delayattheendofeachcommandallowsthehosttosendabreakcharactertocancelthecommand.A delay of two bit times occursbefore each echo and before READ, IREAD, or READSPdata is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE Wait one bit time after each echo before sending the next byte. FROM HOST ADDRESS ADDRESS ADDRESS ADDRESS READ READ DATA HIGH HIGH LOW LOW 4 1 4 1 4 1 3, 2 4 ECHO RETURN Notes: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte. Figure 8-5. Read Transaction FROM HOST ADDRESS ADDRESS ADDRESS ADDRESS WRITE WRITE DATA DATA HIGH HIGH LOW LOW 3 1 3 1 3 1 3 1 2, 3 ECHO Notes: 1 = Echo delay, 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte. Figure 8-6. Write Transaction A brief description of each monitor mode command is given in Table 8-4 through Table 8-9. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 121

Monitor ROM (MON) Table 8-4. READ (Read Memory) Command Description Readbyte from memory Operand 2-byte address in high-byte:low-byte order Data Returnscontents of specified address Returned Opcode $4A Command Sequence SENT TO MONITOR ADDRESS ADDRESS ADDRESS ADDRESS READ READ DATA HIGH HIGH LOW LOW ECHO RETURN Table 8-5. WRITE (Write Memory) Command Description Writebyte to memory 2-byte address in high-byte:low-byte order; Operand low byte followed by data byte Data None Returned Opcode $49 Command Sequence FROM HOST ADDRESS ADDRESS ADDRESS ADDRESS WRITE WRITE DATA DATA HIGH HIGH LOW LOW ECHO MC68HC908AP Family Data Sheet, Rev. 4 122 Freescale Semiconductor

Functional Description Table 8-6. IREAD (Indexed Read) Command Description Readnext 2 bytes in memory from last address accessed Operand 2-byte address in high byte:low byte order Data Returns contents of next two addresses Returned Opcode $1A Command Sequence FROM HOST IREAD IREAD DATA DATA ECHO RETURN Table 8-7. IWRITE (Indexed Write) Command Description Write tolast address accessed + 1 Operand Single data byte Data None Returned Opcode $19 Command Sequence FROM HOST IWRITE IWRITE DATA DATA ECHO A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 123

Monitor ROM (MON) Table 8-8. READSP (Read Stack Pointer) Command Description Readsstack pointer Operand None Data Returnsincremented stack pointer value(SP+1) in Returned high-byte:low-byte order Opcode $0C Command Sequence FROM HOST SP SP READSP READSP HIGH LOW ECHO RETURN Table 8-9. RUN (Run User Program) Command Description Executes PULH and RTI instructions Operand None Data None Returned Opcode $28 Command Sequence FROM HOST RUN RUN ECHO The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tellstheMCUtoexecutethePULHandRTIinstructions.BeforesendingtheRUNcommand,thehostcan modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6. MC68HC908AP Family Data Sheet, Rev. 4 124 Freescale Semiconductor

Security SP HIGH BYTE OF INDEX REGISTER SP + 1 CONDITION CODE REGISTER SP + 2 ACCUMULATOR SP + 3 LOW BYTE OF INDEX REGISTER SP + 4 HIGH BYTE OF PROGRAM COUNTER SP + 5 LOW BYTE OF PROGRAM COUNTER SP + 6 SP + 7 Figure 8-7. Stack Pointer at Monitor Mode Entry 8.4 Security AsecurityfeaturediscouragesunauthorizedreadingofFLASHlocationswhileinmonitormode.Thehost can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Donotleavelocations$FFF6–$FFFDblank.Forsecurityreasons,program locations $FFF6–$FFFD even if they are not used for vectors. Duringmonitormodeentry,theMCUwaitsafterthepower-onresetforthehosttosendtheeightsecurity bytesonpinPTA0.Ifthereceivedbytesmatchthoseatlocations$FFF6–$FFFD,thehostbypassesthe security feature and can read all FLASH locations and execute code from FLASH. Security remains bypasseduntilapower-onresetoccurs.Iftheresetwasnotapower-onreset,securityremainsbypassed and security code entry is not required. (See Figure 8-8.) V DD 4096 + 32 ICLK CYCLES RST 256 BUS CYCLES (MINIMUM) D N A E 1 E 2 E 8 MM T T T Y Y Y O B B B C FROM HOST PTA0 1 4 1 1 2 4 1 FROM MCU O O O O NOTES: YTE 1 ECH YTE 2 ECH YTE 8 ECH BREAK MAND ECH 1 = Echo delay, 2 bit times. B B B OM 2 = Data return delay, 2 bit times. C 4 = Wait 1 bit time before sending next byte. Figure 8-8. Monitor Mode Entry Timing MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 125

Monitor ROM (MON) Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE TheMCUdoesnottransmitabreakcharacteruntilafterthehostsendsthe eight security bits. To determine whether the security code entered is correct, check to see if bit 6 of RAM address $60 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should bereset by a power-on reset and brought up in monitor modetoattemptanotherentry.Afterfailingthesecuritysequence,theFLASHmodulecanalsobemass erasedbyexecutinganeraseroutinethatwasdownloadedintointernalRAM.Themasseraseoperation clears the security code locations so that all eight security bytes become $FF (blank). 8.5 ROM-Resident Routines Seven routines stored in the monitor ROM area (thus ROM-resident) are provided for FLASH memory manipulation. Five of the seven routines are intended to simplify FLASH program, erase, and load operations.TheothertworoutinesareintendedtosimplifytheuseoftheFLASHmemoryasEEPROM. Table 8-10 shows a summary of the ROM-resident routines. Table 8-10. Summary of ROM-Resident Routines Stack Used Routine Name Routine Description Call Address (bytes) PRGRNGE Program a range of locations $FC34 15 ERARNGE Erase a page or the entire array $FCE4 9 LDRNGE Loads data from a range of locations $FC00 7 Program a range of locations in monitor MON_PRGRNGE $FF24 17 mode Erase a page or the entire array in MON_ERARNGE $FF28 11 monitor mode Emulated EEPROM write. Data size EE_WRITE $FF36 30 ranges from 7 to 15 bytes at a time. Emulated EEPROM read. Data size EE_READ $FD5B 18 ranges from 7 to 15 bytes at a time. Theroutinesaredesignedtobecalledasstand-alonesubroutinesintheuserprogramormonitormode. The parameters that are passed to a routine are in the form of a contiguous data block, stored in RAM. Theindexregister(H:X)isloadedwiththeaddressofthefirstbyteofthedatablock(actingasapointer), andthesubroutineiscalled(JSR).Usingthestartaddressasapointer,multipledatablockscanbeused, any area of RAM be used. A data block has the control and data bytes in a defined order, as shown in Figure 8-9. MC68HC908AP Family Data Sheet, Rev. 4 126 Freescale Semiconductor

ROM-Resident Routines During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected. FILE_PTR R A M $XXXX BUS SPEED (BUS_SPD) ADDRESS AS POINTER DATA SIZE (DATASIZE) START ADDRESS HIGH (ADDRH) START ADDRESS LOW (ADDRL) DATA 0 DATA DATA 1 BLOCK DATA ARRAY DATA N Figure 8-9. Data Block Format for ROM-Resident Routines The control and data bytes are described below. • Busspeed—ThisonebyteindicatestheoperatingbusspeedoftheMCU.Thevalueofthisbyte shouldbeequalto4timesthebusspeed.E.g.,fora4MHzbus,thevalueis16($10).Thiscontrol byteisusefulwheretheMCUclocksourceisswitchedbetweenthePLLclockandthecrystalclock. • Data size — This one byte indicates the number of bytes in the data array that are to be manipulated. The maximum data array size is 255. Routines EE_WRITE and EE_READ are restricted to manipulate a data array between 7 to 15 bytes. Whereas routines ERARNGE and MON_ERARNGE do not manipulate a data array, thus, this data size byte has no meaning. • Startaddress—Thesetwobytes,highbytefollowedbylowbyte,indicatethestartaddressofthe FLASH memory to be manipulated. • Data array — This data array contains data that are to be manipulated. Data in this array are programmed to FLASH memory by the programming routines: PRGRNGE, MON_PRGRNGE, EE_WRITE.Forthereadroutines:LDRNGEandEE_READ,dataisreadfromFLASHandstored in this array. 8.5.1 PRGRNGE PRGRNGE is used to program a range of FLASH locations with data loaded into the data array. Table 8-11. PRGRNGE Routine Routine Name PRGRNGE Routine Description Program a range of locations Calling Address $FC34 Stack Used 15 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Start address high (ADDRH) Data Block Format Start address (ADDRL) Data 1 (DATA1) : Data N (DATAN) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 127

Monitor ROM (MON) The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the numberofbytesfromthislocationisspecifiedbyDATASIZE.Themaximumnumberofbytesthatcanbe programmed in one routine call is 255 bytes (max. DATASIZE is 255). ADDRH:ADDRLdonotneedtobeatapageboundary,theroutinehandlesanyboundarymisalignment during programming. A check tosee that all bytes in the specified range are erased isnot performed by this routine prior programming. Nor does this routine do a verification after programming, so there is no return confirmation that programming was successful. User must assure that the range specified is first erased. The coding example below isto program 64bytes of data starting at FLASH location $EE00, with a bus speed of 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. ORG RAM : FILE_PTR: BUS_SPD DS.B 1 ; Indicates 4x bus frequency DATASIZE DS.B 1 ; Data size to be programmed START_ADDR DS.W 1 ; FLASH start address DATAARRAY DS.B 64 ; Reserved data array PRGRNGE EQU $FC34 FLASH_START EQU $EE00 ORG FLASH INITIALISATION: MOV #20, BUS_SPD MOV #64, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS MAIN: BSR INITIALISATION : : LDHX #FILE_PTR JSR PRGRNGE MC68HC908AP Family Data Sheet, Rev. 4 128 Freescale Semiconductor

ROM-Resident Routines 8.5.2 ERARNGE ERARNGE is used to erase a range of locations in FLASH. Table 8-12. ERARNGE Routine Routine Name ERARNGE Routine Description Erase a page or the entire array Calling Address $FCE4 Stack Used 9 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Data Block Format Starting address (ADDRH) Starting address (ADDRL) Therearetwosizesoferaseranges:apageortheentirearray.TheERARNGEwillerasethepage(512 consecutivebytes)inFLASHspecifiedbytheaddressADDRH:ADDRL.Thisaddresscanbeanyaddress within the page. Calling ERARNGE with ADDRH:ADDRL equal to $FFFF will erase the entire FLASH array(masserase).Therefore,caremustbetakenwhencallingthisroutinetopreventanaccidentalmass erase. The ERARNGE routine do not use a data array. The DATASIZE byte is a dummy byte that is also not used. Thecodingexamplebelowistoperformapageerase,from$EE00–$EFFF.TheInitializationsubroutine is the same as the coding example for PRGRNGE (see 8.5.1 PRGRNGE). ERARNGE EQU $FCE4 MAIN: BSR INITIALISATION : : LDHX #FILE_PTR JSR ERARNGE : MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 129

Monitor ROM (MON) 8.5.3 LDRNGE LDRNGE is used to load the data array in RAM with data from a range of FLASH locations. Table 8-13. LDRNGE Routine Routine Name LDRNGE Routine Description Loads data from a range of locations Calling Address $FC00 Stack Used 7 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Data Block Format Starting address (ADDRL) Data 1 : Data N ThestartlocationofFLASHfromwheredataisretrievedisspecifiedbytheaddressADDRH:ADDRLand thenumberofbytesfromthislocationisspecifiedbyDATASIZE.Themaximumnumberofbytesthatcan beretrievedinoneroutinecallis255bytes.ThedataretrievedfromFLASHisloadedintothedataarray inRAM.Previousdatainthedataarraywillbeoverwritten.Usercanusethisroutinetoretrievedatafrom FLASH that was previously programmed. Thecodingexamplebelowistoretrieve64bytesofdatastartingfrom$EE00inFLASH.TheInitialization subroutine is the same as the coding example for PRGRNGE (see 8.5.1 PRGRNGE). LDRNGE EQU $FC00 MAIN: BSR INITIALIZATION : : LDHX #FILE_PTR JSR LDRNGE : MC68HC908AP Family Data Sheet, Rev. 4 130 Freescale Semiconductor

ROM-Resident Routines 8.5.4 MON_PRGRNGE Inmonitormode,MON_PRGRNGEisusedtoprogramarangeofFLASHlocationswithdataloadedinto the data array. Table 8-14. MON_PRGRNGE Routine Routine Name MON_PRGRNGE Routine Description Program a range of locations, in monitor mode Calling Address $FF24 Stack Used 17 bytes Bus speed Data size Starting address (high byte) Data Block Format Starting address (low byte) Data 1 : Data N TheMON_PRGRNGEroutineisdesignedtobeusedinmonitormode.Itperformsthesamefunctionas the PRGRNGE routine (see 8.5.1 PRGRNGE), except that MON_PRGRNGE returns to the main programvia anSWI instruction. AfteraMON_PRGRNGE call, theSWI instruction will returnthe control back to the monitor code. 8.5.5 MON_ERARNGE In monitor mode, ERARNGE is used to erase a range of locations in FLASH. Table 8-15. MON_ERARNGE Routine Routine Name MON_ERARNGE Routine Description Erase a page or the entire array, in monitor mode Calling Address $FF28 Stack Used 11 bytes Bus speed Data size Data Block Format Starting address (high byte) Starting address (low byte) TheMON_ERARNGEroutineisdesignedtobeusedinmonitormode.Itperformsthesamefunctionas theERARNGEroutine(see8.5.2ERARNGE),exceptthatMON_ERARNGEreturnstothemainprogram via an SWI instruction. After a MON_ERARNGE call, the SWI instruction will return the control back to the monitor code. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 131

Monitor ROM (MON) 8.5.6 EE_WRITE EE_WRITE is used to write a set of data from the data array to FLASH. Table 8-16. EE_WRITE Routine Routine Name EE_WRITE EmulatedEEPROMwrite.Datasizerangesfrom7to15bytesat Routine Description a time. Calling Address $FF36 Stack Used 30 bytes Bus speed (BUS_SPD) Data size (DATASIZE)(1) Starting address (ADDRH)(2) Data Block Format Starting address (ADDRL)(1) Data 1 : Data N 1. The minimum data size is 7 bytes. The maximum data size is 15 bytes. 2. The start address must be a page boundary start address. The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the numberofbytesinthedataarrayisspecifiedbyDATASIZE.Theminimumnumberofbytesthatcanbe programmedinoneroutinecallis7bytes,themaximumis15bytes.ADDRH:ADDRLmustalwaysbethe startofboundaryaddress(thepagestartaddress:$X000,$X200,$X400,$X600,$X800,$XA00,$XC00, or $XE00) and DATASIZE must be the same size when accessing the same page. In some applications, the user may want to repeatedly store and read a set of data from an area of non-volatile memory. This is easily possible when using an EEPROM array. As the write and erase operationscanbeexecutedonabytebasis.ForFLASHmemory,theminimumerasesizeisthepage— 512 bytes per page for MC68HC908AP64. If the data array size is less than the page size, writing and erasingtothesamepagecannotfullyutilizethepage.Unusedlocationsinthepagewillbewasted.The EE_WRITE routine is designed to emulate the properties similar to the EEPROM. Allowing a more efficient use of the FLASH page for data storage. WhentheuserdedicatesapageofFLASHfordatastorage,andthesizeofthedataarraydefined,each call of the EE_WRTIE routine will automatically transfer the data in the data array (in RAM) to the next blankblockoflocationsintheFLASHpage.Onceapageisfilledup,theEE_WRITEroutineautomatically erases the page, and starts reuse the page again. In the 512-byte page, an 9-byte control block is used by the routine to monitor the utilization of the page. In effect, only 503 bytes are used for data storage. (see Figure 8-10). The page control operations are transparent to the user. When using this routine to store a 8-byte data array, the FLASH page can be programmed 62 times before the an erase is required. In effect, the write/erase endurance is increased by 62 times. When a 15-bytedataarrayisused,thewrite/eraseenduranceisincreasedby33times.DuetotheFLASHpage size limitation, the data array is limited from 7 bytes to 15 bytes. MC68HC908AP Family Data Sheet, Rev. 4 132 Freescale Semiconductor

ROM-Resident Routines F L A S H PAGE BOUNDARY CONTROL: 9 BYTES DATA ARRAY DATA ARRAY DATA ARRAY ONE PAGE = 512 BYTES PAGE BOUNDARY Figure 8-10. EE_WRITE FLASH Memory Usage The coding example below uses the $EE00–$EFFF page for data storage. The data array size is 15 bytes,andthebusspeedis4.9152 MHz.ThecodingassumesthedatablockisalreadyloadedinRAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. ORG RAM : FILE_PTR: BUS_SPD DS.B 1 ; Indicates 4x bus frequency DATASIZE DS.B 1 ; Data size to be programmed START_ADDR DS.W 1 ; FLASH starting address DATAARRAY DS.B 15 ; Reserved data array EE_WRITE EQU $FF36 FLASH_START EQU $EE00 ORG FLASH INITIALISATION: MOV #20, BUS_SPD MOV #15, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS MAIN: BSR INITIALISATION : : LHDX #FILE_PTR JSR EE_WRITE NOTE The EE_WRITE routine is unable to check for incorrect data blocks, such astheFLASHpageboundaryaddressanddatasize.Itistheresponsibility of the user to ensure the starting address indicated in the data block is at theFLASHpageboundaryandthedatasizeis7to15.IftheFLASHpage is already programmed with a data array with a different size, the EE_WRITE call will be ignored. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 133

Monitor ROM (MON) 8.5.7 EE_READ EE_READ is used to load the data array in RAM with a set of data from FLASH. Table 8-17. EE_READ Routine Routine Name EE_READ EmulatedEEPROMread.Datasizerangesfrom7to15bytesat Routine Description a time. Calling Address $FD5B Stack Used 18 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH)(1) Data Block Format Starting address (ADDRL)(1) Data 1 : Data N 1. The start address must be a page boundary start address. The EE_READ routine reads data stored by the EE_WRITE routine. An EE_READ call will retrieve the lastdatawrittentoaFLASHpageandloadedintothedataarrayinRAM.SameasEE_WRITE,thedata size indicated by DATASIZE is 7 to 15, and the start address ADDRH:ADDRL must the FLASH page boundary address. The coding example below uses the data stored by the EE_WRITE coding example (see 8.5.6 EE_WRITE). It loads the 15-byte data set stored in the $EE00–$EFFF page to the data array in RAM. The initialization subroutine is the same as the coding example for EE_WRITE (see 8.5.6 EE_WRITE). EE_READ EQU $FD5B MAIN: BSR INITIALIZATION : : LDHX #FILE_PTR JSR EE_READ : NOTE TheEE_READroutineisunabletocheckforincorrectdatablocks,suchas theFLASHpageboundaryaddressanddatasize.Itistheresponsibilityof theusertoensurethestartingaddressindicatedinthedatablockisatthe FLASH page boundary and the data size is 7 to 15. If the FLASH page is programmed with a data array with a different size, the EE_READ call will be ignored. MC68HC908AP Family Data Sheet, Rev. 4 134 Freescale Semiconductor

Chapter 9 Timer Interface Module (TIM) 9.1 Introduction This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timingreferencewithInputcapture,outputcompare,andpulse-width-modulationfunctions.Figure 9-1is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2. 9.2 Features Features of the TIM include: • Two input capture/output compare channels: – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action • Buffered and unbuffered pulse-width-modulation (PWM) signal generation • Programmable TIM clock input with 7-frequency internal bus clock prescaler selection • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIM counter stop and reset bits 9.3 Pin Name Conventions The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are T[1,2]CH0(timerchannel0)andT[1,2]CH1(timerchannel1),where“1”isusedtoindicateTIM1and“2” isusedtoindicateTIM2.ThetwoTIMssharefourI/OpinswithfourI/Oportpins.Theexternalclockinput forTIM2issharedwiththeanADCchannelpin.ThefullnamesoftheTIMI/OpinsarelistedinTable 9-1. The generic pin names appear in the text that follows. Table 9-1. Pin Name Conventions TIM Generic Pin Names: T[1,2]CH0 T[1,2]CH1 TIM1 PTB4/T1CH0 PTB5/T1CH1 Full TIM Pin Names: TIM2 PTB6/T2CH0 PTB7/T2CH1 NOTE Referencestoeithertimer1ortimer2maybemadeinthefollowingtextby omitting the timer number. For example, TCH0 may refer generically to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 135

Timer Interface Module (TIM) 9.4 Functional Description Figure 9-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter thatcanoperateasafree-runningcounteroramoduloup-counter.TheTIMcounterprovidesthetiming reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL,controlthemodulovalueoftheTIMcounter.SoftwarecanreadtheTIMcountervalue at any time without affecting the counting sequence. The two TIM channels (per timer) are programmable independently as input capture or output compare channels. PRESCALER SELECT INTERNAL PRESCALER BUS CLOCK TSTOP PS2 PS1 PS0 TRST 16-BIT COUNTER TOF INTERRUPT LOGIC TOIE 16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 ELS0B ELS0A CH0MAX PORT T[1,2]CH0 LOGIC 16-BIT COMPARATOR TCH0H:TCH0L CH0F 16-BIT LATCH INTERRUPT LOGIC MS0A CH0IE MS0B TOV1 S CHANNEL 1 ELS0B ELS0A CH1MAX LPOOGRITC T[1,2]CH1 U B 16-BIT COMPARATOR L A N TCH1H:TCH1L CH1F R TE 16-BIT LATCH CH01IE INTERRUPT N I LOGIC MS0A CH1IE Figure 9-1. TIM Block Diagram Figure 9-2 summarizes the timer registers. NOTE Referencestoeithertimer1ortimer2maybemadeinthefollowingtextby omittingthetimernumber.Forexample,TSCmaygenericallyrefertoboth T1SC and T2SC. MC68HC908AP Family Data Sheet, Rev. 4 136 Freescale Semiconductor

Functional Description Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 TIM1 Status and Control Read: TOF 0 0 TOIE TSTOP PS2 PS1 PS0 $0020 Register Write: 0 TRST (T1SC) Reset: 0 0 1 0 0 0 0 0 TIM1 Counter Register Read: Bit 15 14 13 12 11 10 9 Bit 8 $0021 High Write: (T1CNTH) Reset: 0 0 0 0 0 0 0 0 TIM1 Counter Register Read: Bit 7 6 5 4 3 2 1 Bit 0 $0022 Low Write: (T1CNTL) Reset: 0 0 0 0 0 0 0 0 TIM Counter Modulo Read: Bit 15 14 13 12 11 10 9 Bit 8 $0023 Register High Write: (TMODH) Reset: 1 1 1 1 1 1 1 1 TIM1 Counter Modulo Read: Bit 7 6 5 4 3 2 1 Bit 0 $0024 Register Low Write: (T1MODL) Reset: 1 1 1 1 1 1 1 1 TIM1 Channel 0 Status Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX $0025 and Control Register Write: 0 (T1SC0) Reset: 0 0 0 0 0 0 0 0 TIM1 Channel 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 $0026 Register High Write: (T1CH0H) Reset: Indeterminate after reset TIM1 Channel 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 $0027 Register Low Write: (T1CH0L) Reset: Indeterminate after reset TIM1 Channel 1 Status Read: CH1F 0 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX $0028 and Control Register Write: 0 (T1SC1) Reset: 0 0 0 0 0 0 0 0 TIM1 Channel 1 Read: Bit 15 14 13 12 11 10 9 Bit 8 $0029 Register High Write: (T1CH1H) Reset: Indeterminate after reset TIM1 Channel 1 Read: Bit 7 6 5 4 3 2 1 Bit 0 $002A Register Low Write: (T1CH1L) Reset: Indeterminate after reset TIM2 Status and Control Read: TOF 0 0 TOIE TSTOP PS2 PS1 PS0 $002B Register Write: 0 TRST (T2SC) Reset: 0 0 1 0 0 0 0 0 TIM2 Counter Register Read: Bit 15 14 13 12 11 10 9 Bit 8 $002C High Write: (T2CNTH) Reset: 0 0 0 0 0 0 0 0 TIM2 Counter Register Read: Bit 7 6 5 4 3 2 1 Bit 0 $002D Low Write: (T2CNTL) Reset: 0 0 0 0 0 0 0 0 TIM2 Counter Modulo Read: Bit 15 14 13 12 11 10 9 Bit 8 $002E Register High Write: (T2MODH) Reset: 1 1 1 1 1 1 1 1 =Unimplemented Figure 9-2. TIM I/O Register Summary (Sheet 1 of 2) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 137

Timer Interface Module (TIM) Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 TIM2 Counter Modulo Read: Bit 7 6 5 4 3 2 1 Bit 0 $002F Register Low Write: (T2MODL) Reset: 1 1 1 1 1 1 1 1 TIM2 Channel 0 Status Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX $0030 and Control Register Write: 0 (T2SC0) Reset: 0 0 0 0 0 0 0 0 TIM2 Channel 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 $0031 Register High Write: (T2CH0H) Reset: Indeterminate after reset TIM2 Channel 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 $0032 Register Low Write: (T2CH0L) Reset: Indeterminate after reset TIM2 Channel 1 Status Read: CH1F 0 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX $0033 and Control Register Write: 0 (T2SC1) Reset: 0 0 0 0 0 0 0 0 TIM2 Channel 1 Read: Bit 15 14 13 12 11 10 9 Bit 8 $0034 Register High Write: (T2CH1H) Reset: Indeterminate after reset TIM2 Channel 1 Read: Bit 7 6 5 4 3 2 1 Bit 0 $0035 Register Low Write: (T2CH1L) Reset: Indeterminate after reset =Unimplemented Figure 9-2. TIM I/O Register Summary (Sheet 2 of 2) 9.4.1 TIM Counter Prescaler The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock ratesfromtheinternalbusclock.Theprescalerselectbits,PS[2:0],intheTIMstatusandcontrolregister select the TIM clock source. 9.4.2 Input Capture Withtheinputcapturefunction,theTIMcancapturethetimeatwhichanexternaleventoccurs.Whenan activeedgeoccursonthepinofaninputcapturechannel,theTIMlatchesthecontentsoftheTIMcounter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. 9.4.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 9.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 9.4.3 OutputCompare.Thepulsesareunbufferedbecausechangingtheoutputcomparevaluerequireswriting the new value over the old value currently in the TIM channel registers. MC68HC908AP Family Data Sheet, Rev. 4 138 Freescale Semiconductor

Functional Description An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counterreachestheoldvaluebutafterthecounterreachesthenewvaluepreventsanycompareduring that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output comparevaluemaycausethecomparetobemissed.TheTIMmaypassthenewvaluebeforeitiswritten. Usethefollowingmethodstosynchronizeunbufferedchangesintheoutputcomparevalueonchannelx: • Whenchangingtoasmallervalue,enablechannelxoutputcompareinterruptsandwritethenew value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. • Whenchangingtoalargeroutputcomparevalue,enableTIMoverflowinterruptsandwritethenew value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 9.4.3.2 Buffered Output Compare Channels0and1canbelinkedtoformabufferedoutputcomparechannelwhoseoutputappearsonthe TCH0 pin. The TIM channel registers of the linked pair alternately control the output. SettingtheMS0BbitinTIMchannel0statusandcontrolregister(TSC0)linkschannel0andchannel1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function,andTIMchannel1statusandcontrolregister(TSC1)isunused.WhiletheMS0Bbitisset,the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare valuestothecurrentlyactivechannelregisters.Usersoftwareshouldtrack the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares. 9.4.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. AsFigure 9-3shows,theoutputcomparevalueintheTIMchannelregistersdeterminesthepulsewidth ofthePWMsignal.Thetimebetweenoverflowandoutputcompareisthepulsewidth.ProgramtheTIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. The value in the TIM counter modulo registers and the selected prescaler output determines the frequencyofthePWMoutput.Thefrequencyofan8-bitPWMsignalisvariablein256increments.Writing MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 139

Timer Interface Module (TIM) $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See 9.9.1 TIM Status and Control Register. OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TCHx OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE Figure 9-3. PWM Period and Pulse Width The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 9.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 9.4.4 Pulse Width Modulation(PWM).Thepulsesareunbufferedbecausechangingthepulsewidthrequireswritingthenew pulse width value over the old value currently in the TIM channel registers. AnunsynchronizedwritetotheTIMchannelregisterstochangeapulsewidthvaluecouldcauseincorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: • Whenchangingtoashorterpulsewidth,enablechannelxoutputcompareinterruptsandwritethe newvalueintheoutputcompareinterruptroutine.Theoutputcompareinterruptoccursattheend of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. • Whenchangingtoalongerpulsewidth,enableTIMoverflowinterruptsandwritethenewvaluein theTIMoverflowinterruptroutine.TheTIMoverflowinterruptoccursattheendofthecurrentPWM period.Writingalargervalueinanoutputcompareinterruptroutine(attheendofthecurrentpulse) could cause two output compares to occur in the same PWM period. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cyclegenerationandremovestheabilityofthechanneltoself-correctinthe event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. MC68HC908AP Family Data Sheet, Rev. 4 140 Freescale Semiconductor

Functional Description 9.4.4.2 Buffered PWM Signal Generation Channels0and1canbelinkedtoformabufferedPWMchannelwhoseoutputappearsontheTCH0pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. SettingtheMS0BbitinTIMchannel0statusandcontrolregister(TSC0)linkschannel0andchannel1. TheTIMchannel0registersinitiallycontrolthepulsewidthontheTCH0pin.WritingtotheTIMchannel 1registersenablestheTIMchannel1registerstosynchronouslycontrolthepulsewidthatthebeginning ofthenextPWMperiod.Ateachsubsequentoverflow,theTIMchannelregisters(0or1)thatcontrolthe pulsewidtharetheoneswrittentolast.TSC0controlsandmonitorsthebufferedPWMfunction,andTIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE InbufferedPWMsignalgeneration,donotwritenewpulsewidthvaluesto the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 9.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write0:1(forunbufferedoutputcompareorPWMsignals)or1:0(forbufferedoutputcompare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 9-3.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 9-3.) NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cyclegenerationandremovestheabilityofthechanneltoself-correctinthe event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 141

Timer Interface Module (TIM) SettingMS0Blinkschannels0and1andconfiguresthemforbufferedPWMoperation.TheTIMchannel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output comparestrytoforcetheoutputtoastateitisalreadyinandhavenoeffect.Theresultisa0%dutycycle output. Settingthechannelxmaximumdutycyclebit(CHxMAX)andsettingtheTOVxbitgeneratesa100%duty cycle output. (See 9.9.4 TIM Channel Status and Control Registers.) 9.5 Interrupts The following TIM sources can generate interrupt requests: • TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. • TIMchannelflags(CH1F:CH0F)—TheCHxFbitissetwhenaninputcaptureoroutputcompare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM channel x status and control register. 9.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 9.6.1 Wait Mode TheTIMremainsactiveaftertheexecutionofaWAITinstruction.Inwaitmode,theTIMregistersarenot accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. IfTIMfunctionsarenotrequiredduringwaitmode,reducepowerconsumptionbystoppingtheTIMbefore executing the WAIT instruction. 9.6.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect registerconditionsorthestateoftheTIMcounter.TIMoperationresumeswhentheMCUexitsstopmode after an external interrupt. 9.7 TIM During Break Interrupts A break interrupt stops the TIM counter. Thesystemintegrationmodule(SIM)controlswhetherstatusbitsinothermodulescanbeclearedduring the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 21.5.4 SIM Break Flag Control Register.) MC68HC908AP Family Data Sheet, Rev. 4 142 Freescale Semiconductor

I/O Signals To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its defaultstate),softwarecanreadandwriteI/Oregistersduringthebreakstatewithoutaffectingstatusbits. Somestatusbitshavea2-stepread/writeclearingprocedure.Ifsoftwaredoesthefirststeponsuchabit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. 9.8 I/O Signals Port B shares four of its pins with the TIM. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0, and T2CH1 as described in 9.3 Pin Name Conventions. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins. 9.9 I/O Registers NOTE Referencestoeithertimer1ortimer2maybemadeinthefollowingtextby omittingthetimernumber.Forexample,TSCmaygenericallyrefertoboth T1SC AND T2SC. These I/O registers control and monitor operation of the TIM: • TIM status and control register (TSC) • TIM counter registers (TCNTH:TCNTL) • TIM counter modulo registers (TMODH:TMODL) • TIM channel status and control registers (TSC0, TSC1) • TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L) 9.9.1 TIM Status and Control Register The TIM status and control register (TSC): • Enables TIM overflow interrupts • Flags TIM overflows • Stops the TIM counter • Resets the TIM counter • Prescales the TIM counter clock Address: T1SC, $0020 and T2SC, $002B Bit 7 6 5 4 3 2 1 Bit 0 Read: TOF 0 0 TOIE TSTOP PS2 PS1 PS0 Write: 0 TRST Reset: 0 0 1 0 0 0 0 0 =Unimplemented Figure 9-4. TIM Status and Control Register (TSC) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 143

Timer Interface Module (TIM) TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete,thenwritinglogic0toTOFhasnoeffect.Therefore,aTOFinterruptrequestcannotbelost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST — TIM Reset Bit Settingthiswrite-onlybitresetstheTIMcounterandtheTIMprescaler.SettingTRSThasnoeffecton any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE SettingtheTSTOPandTRSTbitssimultaneouslystopstheTIMcounterat a value of $0000. PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 9-2 shows. Reset clears the PS[2:0] bits. Table 9-2. Prescaler Selection PS2 PS1 PS0 TIM Clock Source 0 0 0 Internalbus clock÷ 1 0 0 1 Internalbus clock÷2 0 1 0 Internalbus clock÷ 4 0 1 1 Internalbus clock÷8 1 0 0 Internalbus clock÷16 1 0 1 Internalbus clock÷32 1 1 0 Internalbus clock÷64 1 1 1 Not available MC68HC908AP Family Data Sheet, Rev. 4 144 Freescale Semiconductor

I/O Registers 9.9.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent readsofTCNTHdonotaffectthelatchedTCNTLvalueuntilTCNTLisread.ResetclearstheTIMcounter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. Address: T1CNTH, $0021 and T2CNTH, $002C Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: 0 0 0 0 0 0 0 0 Figure 9-5. TIM Counter Registers High (TCNTH) Address: T1CNTL, $0022 and T2CNTL, $002D Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 9-6. TIM Counter Registers Low (TCNTL) 9.9.3 TIM Counter Modulo Registers Theread/writeTIMmoduloregisterscontainthemodulovaluefortheTIMcounter.WhentheTIMcounter reachesthemodulovalue,theoverflowflag(TOF)becomesset,andtheTIMcounterresumescounting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers. Address: T1MODH, $0023 and T2MODH, $002E Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: 1 1 1 1 1 1 1 1 Figure 9-7. TIM Counter Modulo Register High (TMODH) Address: T1MODL, $0024 and T2MODL, $002F Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Reset: 1 1 1 1 1 1 1 1 Figure 9-8. TIM Counter Modulo Register Low (TMODL) NOTE Reset the TIM counter before writing to the TIM counter modulo registers. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 145

Timer Interface Module (TIM) 9.9.4 TIM Channel Status and Control Registers Each of the TIM channel status and control registers: • Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output compare, or PWM operation • Selects high, low, or toggling output on output compare • Selects rising edge, falling edge, or any edge as the active input capture trigger • Selects output toggling on TIM overflow • Selects 0% and 100% PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation Address: T1SC0, $0025 and T2SC0, $0030 Bit 7 6 5 4 3 2 1 Bit 0 Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write: 0 Reset: 0 0 0 0 0 0 0 0 Figure 9-9. TIM Channel 0 Status and Control Register (TSC0) Address: T1SC1, $0028 and T2SC1, $0033 Bit 7 6 5 4 3 2 1 Bit 0 Read: CH1F 0 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX Write: 0 Reset: 0 0 0 0 0 0 0 0 Figure 9-10. TIM Channel 1 Status and Control Register (TSC1) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x statusandcontrolregisterwithCHxFsetandthenwritingalogic0toCHxF.Ifanotherinterruptrequest occursbeforetheclearingsequenceiscomplete,thenwritinglogic0toCHxFhasnoeffect.Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and control registers. MC68HC908AP Family Data Sheet, Rev. 4 146 Freescale Semiconductor

I/O Registers SettingMS0Bdisablesthechannel1statusandcontrolregisterandrevertsTCH1togeneral-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA — Mode Select Bit A When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 9-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See Table 9-3. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE BeforechangingachannelfunctionbywritingtotheMSxBorMSxAbit,set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA — Edge/Level Select Bits Whenchannelxisaninputcapturechannel,theseread/writebitscontroltheactiveedge-sensinglogic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 9-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 9-3. Mode, Edge, and Level Selection MSxB:MSxA ELSxB:ELSxA Mode Configuration Pin underport control; X0 00 initial output level high Output preset Pin underport control; X1 00 initial output level low 00 01 Capture onrising edge only 00 10 Capture onfalling edge only Input capture Capture on rising or 00 11 falling edge 01 01 Toggle output on compare Outputcompare 01 10 Clearoutput on compare or PWM 01 11 Setoutput on compare 1X 01 Toggleoutput on compare Buffered output 1X 10 compare or Clearoutput on compare buffered PWM 1X 11 Setoutput on compare MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 147

Timer Interface Module (TIM) NOTE Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. TOVx — Toggle On Overflow Bit Whenchannelxisanoutputcomparechannel,thisread/writebitcontrolsthebehaviorofthechannel xoutputwhentheTIMcounteroverflows.Whenchannelxisaninputcapturechannel,TOVxhasno effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow 0 = Channel x pin does not toggle on TIM counter overflow NOTE When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 9-11 shows, the CHxMAX bit takes effect in the cycle afteritissetorcleared.Theoutputstaysatthe100%dutycycleleveluntilthecycleafterCHxMAXis cleared. OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD TCHx OUTPUT OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE COMPARE CHxMAX Figure 9-11. CHxMAX Latency 9.9.5 TIM Channel Registers These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. Ininputcapturemode(MSxB:MSxA=0:0),readingthehighbyteoftheTIMchannelxregisters(TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA ≠0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. MC68HC908AP Family Data Sheet, Rev. 4 148 Freescale Semiconductor

I/O Registers Address: T1CH0H, $0026 and T2CH0H, $0031 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: Indeterminate after reset Figure 9-12. TIM Channel 0 Register High (TCH0H) Address: T1CH0L, $0027 and T2CH0L $0032 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Reset: Indeterminate after reset Figure 9-13. TIM Channel 0 Register Low (TCH0L) Address: T1CH1H, $0029 and T2CH1H, $0034 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: Indeterminate after reset Figure 9-14. TIM Channel 1 Register High (TCH1H) Address: T1CH1L, $002A and T2CH1L, $0035 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Reset: Indeterminate after reset Figure 9-15. TIM Channel 1 Register Low (TCH1L) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 149

Timer Interface Module (TIM) MC68HC908AP Family Data Sheet, Rev. 4 150 Freescale Semiconductor

Chapter 10 Timebase Module (TBM) 10.1 Introduction This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectableratesusingacounterclockedbytheselectedOSCCLKclockfromtheoscillatormodule.This TBM version uses 18 divider stages, eight of which are user selectable. 10.2 Features Features of the TBM module include: • Software programmable 8s, 4s, 2s, 1s, 2ms, 1ms, 0.5ms, and 0.25ms periodic interrupt using 32.768-kHz OSCCLK clock • User selectable oscillator clock source enable during stop mode to allow periodic wake-up from stop 10.3 Functional Description This module can generate a periodic interrupt by dividing the oscillator clock frequency, OSCCLK. The counterisinitializedtoall0swhenTBONbitiscleared.Thecounter,showninFigure 10-1,startscounting whentheTBONbitisset.WhenthecounteroverflowsatthetapselectedbyTBR[2:0],theTBIFbitgets set. If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared by writing a 1 to the TACK bit. The first time the TBIF flag is set after enabling the timebase module, the interrupt is generated at approximately half of the overflow period. Subsequent events occur at the exact period. The reference clock OSCCLK is derived from the oscillator module, see 5.2.2 TBM Reference Clock Selection. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 151

Timebase Module (TBM) TBON OSCCLK ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 From OSC module (SeeChapter 5 Oscillator (OSC).) ÷ 8 ÷ 16 ÷ 32 ÷ 64 ÷ 2048 TBMINT ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 R2 R1 R0 CK B B B A T T T T ÷ 32768 ÷ 65536 ÷ 131072 ÷ 262144 TBIF TBIE 0 0 0 R 0 0 1 0 1 0 0 1 1 1 0 0 SEL 1 0 1 1 1 0 1 1 1 Figure 10-1. Timebase Block Diagram 10.4 Timebase Register Description The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the rate. Address: $0051 Bit 7 6 5 4 3 2 1 Bit 0 Read: TBIF 0 TBR2 TBR1 TBR0 TBIE TBON R Write: TACK Reset: 0 0 0 0 0 0 0 0 =Unimplemented R =Reserved Figure 10-2. Timebase Control Register (TBCR) TBIF — Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over. 1 = Timebase interrupt pending 0 = Timebase interrupt not pending MC68HC908AP Family Data Sheet, Rev. 4 152 Freescale Semiconductor

Timebase Register Description TBR[2:0] — Timebase Rate Selection These read/write bits are used to select the rate of timebase interrupts as shown in Table 10-1. NOTE Do not change TBR[2:0] bits while the timebase is enabled (TBON = 1). Table 10-1. Timebase Rate Selection for OSCCLK = 32.768-kHz Timebase Interrupt Rate TBR2 TBR1 TBR0 Divider Hz ms 0 0 0 262144 0.125 8000 0 0 1 131072 0.25 4000 0 1 0 65536 0.5 2000 0 1 1 32768 1 1000 1 0 0 64 512 ~2 1 0 1 32 1024 ~1 1 1 0 16 2048 ~0.5 1 1 1 8 4096 ~0.24 TACK — Timebase ACKnowledge The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a logic 0 to this bit has no effect. 1 = Clear timebase interrupt flag 0 = No effect TBIE — Timebase Interrupt Enabled This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the TBIE bit. 1 = Timebase interrupt enabled 0 = Timebase interrupt disabled TBON — Timebase Enabled This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption whenitsfunctionisnotnecessary.Thecountercanbeinitializedbyclearingandthensettingthisbit. Reset clears the TBON bit. 1 = Timebase enabled 0 = Timebase disabled and the counter initialized to 0’s MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 153

Timebase Module (TBM) 10.5 Interrupts ThetimebasemodulecaninterrupttheCPUonaregularbasiswitharatedefinedbyTBR[2:0].Whenthe timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt,thecounterchainoverflowwillgenerateaCPUinterruptrequest.Theinterruptvectorisdefined in Table 2-1 . Vector Addresses. Interrupts must be acknowledged by writing a logic 1 to the TACK bit. 10.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 10.6.1 Wait Mode ThetimebasemoduleremainsactiveafterexecutionoftheWAITinstruction.Inwaitmode,thetimebase register is not accessible by the CPU. Ifthetimebasefunctionsarenotrequiredduringwaitmode,reducethepowerconsumptionbystopping the timebase before enabling the WAIT instruction. 10.6.2 Stop Mode ThetimebasemodulemayremainactiveafterexecutionoftheSTOPinstructioniftheoscillatorhasbeen enabled to operate during stop mode through the stop mode oscillator enable bit (STOP_ICLKDIS, STOP_RCLKEN,orSTOP_XCLKEN)fortheselectedoscillatorintheCONFIG2register.Thetimebase module can be used in this mode to generate a periodic walk-up from stop mode. If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. In stop mode the timebase register is not accessible by the CPU. Ifthetimebasefunctionsarenotrequiredduringstopmode,reducethepowerconsumptionbystopping the timebase before enabling the STOP instruction. MC68HC908AP Family Data Sheet, Rev. 4 154 Freescale Semiconductor

Chapter 11 Serial Communications Interface Module (SCI) 11.1 Introduction The MC68HC908AP64 has two SCI modules: • SCI1 is a standard SCI module, and • SCI2 is an infrared SCI module. ThissectiondescribesSCI1,theserialcommunicationsinterface(SCI)module,whichallowshigh-speed asynchronous communications with peripheral devices and other MCUs. NOTE WhentheSCIisenabled,theTxDpinisanopen-drainoutputandrequires a pullup resistor to be connected for proper SCI operation. 11.2 Features Features of the SCI module include the following: • Full-duplex operation • Standard mark/space non-return-to-zero (NRZ) format • 32 programmable baud rates • Programmable 8-bit or 9-bit character length • Separately enabled transmitter and receiver • Separate receiver and transmitter CPU interrupt requests • Programmable transmitter output polarity • Two receiver wakeup methods: – Idle line wakeup – Address mark wakeup • Interrupt-driven operation with eight interrupt flags: – Transmitter empty – Transmission complete – Receiver full – Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection • Configuration register bit, SCIBDSRC, to allow selection of baud rate clock source MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 155

Serial Communications Interface Module (SCI) 11.3 Pin Name Conventions The generic names of the SCI I/O pins are: • RxD (receive data) • TxD (transmit data) SCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an SCI inputoroutputreflectsthenameofthesharedportpin.Table 11-1showsthefullnamesandthegeneric names of the SCI I/O pins. The generic pin names appear in the text of this section. Table 11-1. Pin Name Conventions Generic Pin Names: RxD TxD Full Pin Names: PTB3/RxD PTB2/TxD NOTE WhentheSCIisenabled,theTxDpinisanopen-drainoutputandrequires a pullup resistor to be connected for proper SCI operation. Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: SCI Control Register 1 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY $0013 Write: (SCC1) Reset: 0 0 0 0 0 0 0 0 Read: SCI Control Register 2 SCTIE TCIE SCRIE ILIE TE RE RWU SBK $0014 Write: (SCC2) Reset: 0 0 0 0 0 0 0 0 Read: R8 SCI Control Register 3 T8 DMARE DMATE ORIE NEIE FEIE PEIE $0015 Write: (SCC3) Reset: U U 0 0 0 0 0 0 Read: SCTE TC SCRF IDLE OR NF FE PE $0016 SCIStatusRegister1(SCS1) Write: Reset: 1 1 0 0 0 0 0 0 Read: BKF RPF $0017 SCIStatusRegister2(SCS2) Write: Reset: 0 0 0 0 0 0 0 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 SCI Data Register $0018 Write: T7 T6 T5 T4 T3 T2 T1 T0 (SCDR) Reset: Unaffected by reset Read: 0 0 SCI Baud Rate Register SCP1 SCP0 R SCR2 SCR1 SCR0 $0019 Write: (SCBR) Reset: 0 0 0 0 0 0 0 0 =Unimplemented R = Reserved U = Unaffected Figure 11-1. SCI I/O Register Summary MC68HC908AP Family Data Sheet, Rev. 4 156 Freescale Semiconductor

Functional Description 11.4 Functional Description Figure 11-2showsthestructureoftheSCImodule.TheSCIallowsfull-duplex,asynchronous,NRZserial communicationamongtheMCUandremotedevices,includingotherMCUs.Thetransmitterandreceiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC, of the CONFIG2 register ($001D). INTERNAL BUS SCI DATA SCI DATA REGISTER REGISTER R RxD SHIFRTE RCEEGIVISETER DMAINTERRUPTCONTROL TRANSMITTEINTERRUPTCONTROL RECEIVERINTERRUPTCONTROL ERRORINTERRUPTCONTROL SHITFRT ARNESGMISITTER TxD TXINV SCTIE R8 TCIE T8 SCRIE ILIE DMARE TE SCTE DMATE RE TC RWU SCRF OR ORIE SBK IDLE NF NEIE FE FEIE PE PEIE LOOPS LOOPS ENSCI WAKEUP RECEIVE FLAG TRANSMIT CONTROL CONTROL CONTROL CONTROL SCIBDSRC M FROM BKF CONFIG ENSCI WAKE RPF ILTY BUCSG MCLXOCCLKK ABSLX ÷4 SCPARLEE-R DBIVAIDUEDR PPETYN SL = 0 => X = A SL = 1 => X = B ÷ 16 DATA SELECTION CGMXCLK is from CGM module CONTROL Figure 11-2. SCI Module Block Diagram MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 157

Serial Communications Interface Module (SCI) 11.4.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 11-3. 8-BIT DATA FORMAT PARITY BIT M IN SCC1 CLEAR BIT NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT BIT 9-BIT DATA FORMAT PARITY BIT M IN SCC1 SET BIT NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP BIT BIT Figure 11-3. SCI Data Formats 11.4.2 Transmitter Figure 11-4 shows the structure of the SCI transmitter. The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC. Source selection values are shown in Figure 11-4. INTERNAL BUS PRE- BAUD ÷4 ÷16 SCI DATA REGISTER SCALER DIVIDER SCIBDSRC SCP1 FROM 11-BIT T CONFIG2 SCP0 OP TRANSMIT AR T SHIFT REGISTER T SCR1 S S H 8 7 6 5 4 3 2 1 0 L TxD SL SCR2 CGMXCLK A X BUS CLOCK B SCR0 B SSLL == 01 ==>> XX == AB UEST EST TXINV MS Q U E Q R E RRUPT VICE R M DR MITTER CPUINTE MITTER DMA SER PPETYN GENPAETRR8IATTYION LOAD FROM SC SHIFT ENABLE PREAMBLEALL 1s BREAKALL 0s S S AN AN DMATE TRANSMITTER TR TR DMATE CONTROL LOGIC SCTIE SCTE SCTE SBK DMATE SCTE LOOPS SCTIE SCTIE ENSCI TC TC TE TCIE TCIE Figure 11-4. SCI Transmitter MC68HC908AP Family Data Sheet, Rev. 4 158 Freescale Semiconductor

Functional Description 11.4.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. Thestate of the Mbit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 11.4.2.2 Character Transmission DuringanSCItransmission,thetransmitshiftregistershiftsacharacterouttotheTxDpin.TheSCIdata register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. EnabletheSCIbywritingalogic1totheenableSCIbit(ENSCI)inSCIcontrolregister1(SCC1). 2. Enablethetransmitterbywritingalogic1tothetransmitterenablebit(TE)inSCIcontrolregister 2 (SCC2). 3. Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing to the SCDR. 4. Repeat step 3 for each subsequent transmission. Atthe startof atransmission, transmitter control logic automaticallyloads thetransmit shiftregisterwith a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmitshiftregister.TheSCTEbitindicatesthattheSCDRcanacceptnewdatafromtheinternaldata bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt request. When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic 1.IfatanytimesoftwareclearstheENSCIbitinSCIcontrolregister1(SCC1),thetransmitterand receiver relinquish control of the port pin. 11.4.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads breakcharactersintothetransmitshiftregister.AftersoftwareclearstheSBKbit,theshiftregisterfinishes transmittingthelastbreakcharacterandthentransmitsatleastonelogic1.Theautomaticlogic1atthe end of a break character guarantees the recognition of the start bit of the next character. TheSCIrecognizesabreakcharacterwhenastartbitisfollowedbyeightorninelogic0databitsanda logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers: • Sets the framing error bit (FE) in SCS1 • Sets the SCI receiver full bit (SCRF) in SCS1 • Clears the SCI data register (SCDR) • Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • Maysettheoverrun(OR),noiseflag(NF),parityerror(PE),orreceptioninprogressflag(RPF)bits MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 159

Serial Communications Interface Module (SCI) 11.4.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. NOTE Whenqueueinganidlecharacter,returntheTEbittologic1beforethestop bit of the current character shifts out to the TxD pin. Setting TE after the stopbitappearsonTxDcausesdatapreviouslywrittentotheSCDRtobe lost. ToggletheTEbitforaqueuedidlecharacterwhentheSCTEbitbecomes set and just before writing the next byte to the SCDR. 11.4.2.5 Inversion of Transmitted Output The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at logic 1. (See 11.8.1 SCI Control Register 1.) 11.4.2.6 Transmitter Interrupts These conditions can generate CPU interrupt requests from the SCI transmitter: • SCItransmitterempty(SCTE)—TheSCTEbitinSCS1indicatesthattheSCDRhastransferred acharactertothetransmitshiftregister.SCTEcangenerateatransmitterCPUinterruptrequest. Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. • Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. 11.4.3 Receiver Figure 11-5 shows the structure of the SCI receiver. 11.4.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 11.4.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. Afteracompletecharactershiftsintothereceiveshiftregister,thedataportionofthecharactertransfers totheSCDR.TheSCIreceiverfullbit,SCRF,inSCIstatusregister1(SCS1)becomesset,indicatingthat MC68HC908AP Family Data Sheet, Rev. 4 160 Freescale Semiconductor

Functional Description the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. INTERNAL BUS SCIBDSRC SCR1 FROM CONFIG2 SCP1 SCR2 SCI DATA REGISTER SCP0 SCR0 SL CGMXCLK A X ÷4 PRE- BAUD ÷ 16 BUS CLOCK B SCALER DIVIDER P 11-BIT RT O A SL = 0 => X = A T RECEIVE SHIFT REGISTER T SL = 1 => X = B S S DATA RxD H 8 7 6 5 4 3 2 1 0 L RECOVERY ALL 0s BKF s 1 RPF ALL MSB T S E U Q M E T RWU RRUPT R QUEST REQUES WILATKYE WLAOKGEIUCP SIDCLREF PUINTE VICE RE RRUPT PEN PARITY R8 C R E CHECKING RROR MA SE PU INT PTY IDLE E D C ILIE ILIE DMARE SCRF SCRIE SCRIE DMARE SCRF SCRIE DMARE DMARE OR OR ORIE ORIE NF NF NEIE NEIE FE FE FEIE FEIE PE PE PEIE PEIE Figure 11-5. SCI Receiver Block Diagram MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 161

Serial Communications Interface Module (SCI) 11.4.3.3 Data Sampling ThereceiversamplestheRxDpinattheRTclockrate.TheRTclockisaninternalsignalwithafrequency 16timesthebaudrate.Toadjustforbaudratemismatch,theRTclockisresynchronizedatthefollowing times (see Figure 11-6): • After every start bit • After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samplesatRT8,RT9,andRT10returnsavalidlogic1andthemajorityofthenextRT8,RT9,and RT10 samples returns a valid logic 0) Tolocatethestartbit,datarecoverylogicdoesanasynchronoussearchforalogic0precededbythree logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. START BIT LSB RxD START BIT START BIT DATA SAMPLES QUALIFICATION VERIFICATION SAMPLING RT CLOCK 0 1 2 3 4 5 6 RT CLOCK 1 1 1 1 1 1 1 1 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 2 3 4 STATE RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT CLOCK RESET Figure 11-6. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 11-2 summarizes the results of the start bit verification samples. Table 11-2. Start Bit Verification RT3, RT5, and RT7 Start Bit Noise Flag Samples Verification 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 MC68HC908AP Family Data Sheet, Rev. 4 162 Freescale Semiconductor

Functional Description Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. Todeterminethevalueofadatabitandtodetectnoise,recoverylogictakessamplesatRT8,RT9,and RT10. Table 11-3 summarizes the results of the data bit samples. Table 11-3. Data Bit Recovery RT8, RT9, and RT10 Data Bit Noise Flag Samples Determination 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE TheRT8,RT9,andRT10samplesdonotaffectstartbitverification.Ifany or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. Toverifyastopbitandtodetectnoise,recoverylogictakessamplesatRT8,RT9,andRT10.Table 11-4 summarizes the results of the stop bit samples. Table 11-4. Stop Bit Recovery RT8, RT9, and RT10 Framing Noise Flag Samples Error Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 163

Serial Communications Interface Module (SCI) 11.4.3.4 Framing Errors Ifthedatarecoverylogicdoesnotdetectalogic1wherethestopbitshouldbeinanincomingcharacter, itsetstheframingerrorbit,FE,inSCS1.AbreakcharacteralsosetstheFEbitbecauseabreakcharacter has no stop bit. The FE bit is set at the same time that the SCRF bit is set. 11.4.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actualstopbit.Thenanoiseerroroccurs.Ifmorethanoneofthesamplesisoutsidethestopbit,aframing erroroccurs.Inmostapplications,thebaudratetoleranceismuchmorethanthedegreeofmisalignment that is likely to occur. Asthereceiversamplesanincomingcharacter,itresynchronizestheRTclockonanyvalidfallingedge withinthecharacter.Resynchronizationwithincharacterscorrectsmisalignmentsbetweentransmitterbit times and receiver bit times. Slow Data Tolerance Figure 11-7showshowmuchaslowreceivedcharactercanbemisalignedwithoutcausinganoiseerror oraframingerror.TheslowstopbitbeginsatRT8insteadofRT1butarrivesintimeforthestopbitdata samples at RT8, RT9, and RT10. MSB STOP RECEIVER RT CLOCK 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 T T T T T T T T T 1 1 1 1 1 1 1 R R R R R R R R R T T T T T T T R R R R R R R DATA SAMPLES Figure 11-7. Slow Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. WiththemisalignedcharactershowninFigure 11-7,thereceivercounts154RTcyclesatthepointwhen the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is 1----5---4-----–-----1---4---7--- ×100 = 4.54% 154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. WiththemisalignedcharactershowninFigure 11-7,thereceivercounts170RTcyclesatthepointwhen the count of the transmitting device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles. MC68HC908AP Family Data Sheet, Rev. 4 164 Freescale Semiconductor

Functional Description The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 1----7---0-----–-----1---6---3--- ×100 = 4.12% 170 Fast Data Tolerance Figure 11-8showshowmuchafastreceivedcharactercanbemisalignedwithoutcausinganoiseerror or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. STOP IDLE OR NEXT CHARACTER RECEIVER RT CLOCK 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 T T T T T T T T T 1 1 1 1 1 1 1 R R R R R R R R R T T T T T T T R R R R R R R DATA SAMPLES Figure 11-8. Fast Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. WiththemisalignedcharactershowninFigure 11-8,thereceivercounts154RTcyclesatthepointwhen the count of the transmitting device is 10 bit times × 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 1----5---4-----–-----1---6---0--- ×100 = 3.9˙0% 154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. WiththemisalignedcharactershowninFigure 11-8,thereceivercounts170RTcyclesatthepointwhen the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 1----7---0-----–-----1---7---6--- ×100 = 3.53% 170 11.4.3.6 Receiver Wakeup SothattheMCUcanignoretransmissionsintendedonlyforotherreceiversinmultiple-receiversystems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 165

Serial Communications Interface Module (SCI) Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: • Address mark — An address mark is a logic 1 in the most significant bit position of a received character.WhentheWAKEbitisset,anaddressmarkwakesthereceiverfromthestandbystate byclearingtheRWUbit.TheaddressmarkalsosetstheSCIreceiverfullbit,SCRF.Softwarecan then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. • Idleinputlinecondition—WhentheWAKEbitisclear,anidlecharacterontheRxDpinwakesthe receiverfromthestandbystatebyclearingtheRWUbit.Theidlecharacterthatwakesthereceiver does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit, ILTY,determineswhetherthereceiverbeginscountinglogic1sasidlecharacterbitsafterthestart bit or after the stop bit. NOTE With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately. 11.4.3.7 Receiver Interrupts The following sources can generate CPU interrupt requests from the SCI receiver: • SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has transferredacharactertotheSCDR.SCRFcangenerateareceiverCPUinterruptrequest.Setting the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU interrupts. • Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in fromtheRxDpin.Theidlelineinterruptenablebit,ILIE,inSCC2enablestheIDLEbittogenerate CPU interrupt requests. 11.4.3.8 Error Interrupts The following receiver error flags in SCS1 can generate CPU interrupt requests: • Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new characterbeforethepreviouscharacterwasreadfromtheSCDR.Thepreviouscharacterremains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. • Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break characters,includingstart,data,andstopbits.Thenoiseerrorinterruptenablebit,NEIE,inSCC3 enables NF to generate SCI error CPU interrupt requests. • Framingerror(FE)—TheFEbitinSCS1issetwhenalogic0occurswherethereceiverexpects astopbit.Theframingerrorinterruptenablebit,FEIE,inSCC3enablesFEtogenerateSCIerror CPU interrupt requests. • Parityerror(PE)—ThePEbitinSCS1issetwhentheSCIdetectsaparityerrorinincomingdata. Theparityerrorinterruptenablebit,PEIE,inSCC3enablesPEtogenerateSCIerrorCPUinterrupt requests. MC68HC908AP Family Data Sheet, Rev. 4 166 Freescale Semiconductor

Low-Power Modes 11.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 11.5.1 Wait Mode TheSCImoduleremainsactiveaftertheexecutionofaWAITinstruction.Inwaitmode,theSCImodule registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. Refer to 7.6 Low-Power Modes for information on exiting wait mode. 11.5.2 Stop Mode The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect SCI register states. SCI module operation resumes after an external interrupt. Becausetheinternalclockisinactiveduringstopmode,enteringstopmodeduringanSCItransmission or reception results in invalid data. Refer to 7.6 Low-Power Modes for information on exiting stop mode. 11.6 SCI During Break Module Interrupts Thesystemintegrationmodule(SIM)controlswhetherstatusbitsinothermodulescanbeclearedduring the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its defaultstate),softwarecanreadandwriteI/Oregistersduringthebreakstatewithoutaffectingstatusbits. Somestatusbitshavea2-stepread/writeclearingprocedure.Ifsoftwaredoesthefirststeponsuchabit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. 11.7 I/O Signals Port B shares two of its pins with the SCI module. The two SCI I/O pins are: • PTB2/TxD — Transmit data • PTB3/RxD — Receive data 11.7.1 TxD (Transmit Data) When the SCI is enabled (ENSCI=1), the PTB2/TxD pin becomes the serial data output, TxD, from the SCItransmitterregardlessofthestateoftheDDRB2bitindatadirectionregisterB(DDRB).TheTxDpin is an open-drain output and requires a pullup resistor to be connected for proper SCI operation. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 167

Serial Communications Interface Module (SCI) NOTE The PTB2/TxD pin is an open-drain pin when configured as an output. Therefore, when configured as a general purpose output pin (PTB2), a pullup resistor must be connected to this pin. 11.7.2 RxD (Receive Data) WhentheSCIisenabled(ENSCI=1),thePTB3/RxDpinbecomestheserialdatainput,RxD,totheSCI receiver regardless of the state of the DDRB3 bit in data direction register B (DDRB). NOTE The PTB3/RxD pin is an open-drain pin when configured as an output. Therefore, when configured as a general purpose output pin (PTB3), a pullup resistor must be connected to this pin. 11.8 I/O Registers These I/O registers control and monitor SCI operation: • SCI control register 1 (SCC1) • SCI control register 2 (SCC2) • SCI control register 3 (SCC3) • SCI status register 1 (SCS1) • SCI status register 2 (SCS2) • SCI data register (SCDR) • SCI baud rate register (SCBR) MC68HC908AP Family Data Sheet, Rev. 4 168 Freescale Semiconductor

I/O Registers 11.8.1 SCI Control Register 1 SCI control register 1: • Enables loop mode operation • Enables the SCI • Controls output polarity • Controls character length • Controls SCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type Address: $0013 Bit 7 6 5 4 3 2 1 Bit 0 Read: LOOPS ENSCI TXINV M WAKE ILTY PEN PTY Write: Reset: 0 0 0 0 0 0 0 0 Figure 11-9. SCI Control Register 1 (SCC1) LOOPS — Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the SCI,andthetransmitteroutputgoesintothereceiverinput.Boththetransmitterandthereceivermust be enabled to use loop mode. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled ENSCI — Enable SCI Bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = SCI enabled 0 = SCI disabled TXINV — Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted NOTE Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits. M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 11-5.) Theninthbitcanserveasanextrastopbit,asareceiverwakeupsignal,orasaparitybit.Resetclears the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 169

Serial Communications Interface Module (SCI) WAKE — Wakeup Condition Bit Thisread/writebitdetermineswhichconditionwakesuptheSCI:alogic1(addressmark)inthemost significant bit position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup ILTY — Idle Line Type Bit This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The countingbeginseitherafterthestartbitorafterthestopbit.Ifthecountbeginsafterthestartbit,then astringoflogic1sprecedingthestopbitmaycausefalserecognitionofanidlecharacter.Beginning thecountafterthestopbitavoidsfalseidlecharacterrecognition,butrequiresproperlysynchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit PEN — Parity Enable Bit Thisread/writebitenablestheSCIparityfunction.(SeeTable 11-5.)Whenenabled,theparityfunction inserts a parity bit in the most significant bit position. (See Figure 11-3.) Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled PTY — Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 11-5.) Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Table 11-5. Character Format Selection Control Bits Character Format Start Data Stop Character M PEN:PTY Parity Bits Bits Bits Length 0 0X 1 8 None 1 10 bits 1 0X 1 9 None 1 11 bits 0 10 1 7 Even 1 10 bits 0 11 1 7 Odd 1 10 bits 1 10 1 8 Even 1 11 bits 1 11 1 8 Odd 1 11 bits MC68HC908AP Family Data Sheet, Rev. 4 170 Freescale Semiconductor

I/O Registers 11.8.2 SCI Control Register 2 SCI control register 2: • Enables the following CPU interrupt requests: – Enables the SCTE bit to generate transmitter CPU interrupt requests – Enables the TC bit to generate transmitter CPU interrupt requests – Enables the SCRF bit to generate receiver CPU interrupt requests – Enables the IDLE bit to generate receiver CPU interrupt requests • Enables the transmitter • Enables the receiver • Enables SCI wakeup • Transmits SCI break characters Address: $0014 Bit 7 6 5 4 3 2 1 Bit 0 Read: SCTIE TCIE SCRIE ILIE TE RE RWU SBK Write: Reset: 0 0 0 0 0 0 0 0 Figure 11-10. SCI Control Register 2 (SCC2) SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt TCIE — Transmission Complete Interrupt Enable Bit Thisread/writebitenablestheTCbittogenerateSCItransmitterCPUinterruptrequests.Resetclears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests SCRIE — SCI Receive Interrupt Enable Bit Thisread/writebitenablestheSCRFbittogenerateSCIreceiverCPUinterruptrequests.Resetclears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt ILIE — Idle Line Interrupt Enable Bit Thisread/writebitenablestheIDLEbittogenerateSCIreceiverCPUinterruptrequests.Resetclears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 171

Serial Communications Interface Module (SCI) TE — Transmitter Enable Bit Settingthisread/writebitbeginsthetransmissionbysendingapreambleof10or11logic1sfromthe transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmissioninprogressbeforetheTxDreturnstotheidlecondition(logic1).Clearingandthensetting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled NOTE WritingtotheTEbitisnotallowedwhentheenableSCIbit(ENSCI)isclear. ENSCI is in SCI control register 1. RE — Receiver Enable Bit Settingthisread/writebitenablesthereceiver.ClearingtheREbitdisablesthereceiverbutdoesnot affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RWU — Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK — Send Break Bit Settingandthenclearingthisread/writebittransmitsabreakcharacterfollowedbyalogic1.Thelogic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted NOTE DonottoggletheSBKbitimmediatelyaftersettingtheSCTEbit.Toggling SBKbeforethepreamblebeginscausestheSCItosendabreakcharacter instead of a preamble. MC68HC908AP Family Data Sheet, Rev. 4 172 Freescale Semiconductor

I/O Registers 11.8.3 SCI Control Register 3 SCI control register 3: • Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted • Enables these interrupts: – Receiver overrun interrupts – Noise error interrupts – Framing error interrupts • Parity error interrupts Address: $0015 Bit 7 6 5 4 3 2 1 Bit 0 Read: R8 T8 DMARE DMATE ORIE NEIE FEIE PEIE Write: Reset: U U 0 0 0 0 0 0 =Unimplemented U=Unaffected Figure 11-11. SCI Control Register 3 (SCC3) R8 — Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset has no effect on the T8 bit. DMARE — DMA Receive Enable Bit CAUTION TheDMAmoduleisnotincludedonthisMCU.Writingalogic1toDMARE or DMATE may adversely affect MCU performance. 1=DMAnotenabledtoserviceSCIreceiverDMAservicerequestsgeneratedbytheSCRFbit(SCI receiver CPU interrupt requests enabled) 0=DMAnotenabledtoserviceSCIreceiverDMAservicerequestsgeneratedbytheSCRFbit(SCI receiver CPU interrupt requests enabled) DMATE — DMA Transfer Enable Bit CAUTION TheDMAmoduleisnotincludedonthisMCU.Writingalogic1toDMARE or DMATE may adversely affect MCU performance. 1 = SCTE DMA service requests enabled; SCTE CPU interrupt requests disabled 0 = SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled ORIE — Receiver Overrun Interrupt Enable Bit Thisread/writebitenablesSCIerrorCPUinterruptrequestsgeneratedbythereceiveroverrunbit,OR. 1 = SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 173

Serial Communications Interface Module (SCI) NEIE — Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = SCI error CPU interrupt requests from NE bit enabled 0 = SCI error CPU interrupt requests from NE bit disabled FEIE — Receiver Framing Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = SCI error CPU interrupt requests from FE bit enabled 0 = SCI error CPU interrupt requests from FE bit disabled PEIE — Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requestsgeneratedbytheparityerrorbit,PE.(See11.8.4SCIStatusRegister1.)ResetclearsPEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled 11.8.4 SCI Status Register 1 SCI status register 1 (SCS1) contains flags to signal these conditions: • Transfer of SCDR data to transmit shift register complete • Transmission complete • Transfer of receive shift register data to SCDR complete • Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error Address: $0016 Bit 7 6 5 4 3 2 1 Bit 0 Read: SCTE TC SCRF IDLE OR NF FE PE Write: Reset: 1 1 0 0 0 0 0 0 =Unimplemented Figure 11-12. SCI Status Register 1 (SCS1) SCTE — SCI Transmitter Empty Bit Thisclearable,read-onlybitissetwhentheSCDRtransfersacharactertothetransmitshiftregister. SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTEgeneratesanSCItransmitterCPUinterruptrequest.Innormaloperation,cleartheSCTEbitby reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register MC68HC908AP Family Data Sheet, Rev. 4 174 Freescale Semiconductor

I/O Registers TC — Transmission Complete Bit Thisread-onlybitissetwhentheSCTEbitisset,andnodata,preamble,orbreakcharacterisbeing transmitted.TCgeneratesanSCItransmitterCPUinterruptrequestiftheTCIEbitinSCC2isalsoset. TCisautomaticallyclearedwhendata,preambleorbreakisqueuedandreadytobesent.Theremay be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF — SCI Receiver Full Bit Thisclearable,read-onlybitissetwhenthedatainthereceiveshiftregistertransferstotheSCIdata register.SCRFcangenerateanSCIreceiverCPUinterruptrequest.WhentheSCRIEbitinSCC2is set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR IDLE — Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLEgeneratesanSCIreceiverCPUinterruptrequestiftheILIEbitinSCC2isalsoset.CleartheIDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receiveavalidcharacterthatsetstheSCRFbitbeforeanidleconditioncansettheIDLEbit.Also,after theIDLEbithasbeencleared,avalidcharactermustagainsettheSCRFbitbeforeanidlecondition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) OR — Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIEbitinSCC3isalsoset.Thedataintheshiftregisterislost,butthedataalreadyintheSCDRis notaffected.CleartheORbitbyreadingSCS1withORsetandthenreadingtheSCDR.Resetclears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun SoftwarelatencymayallowanoverruntooccurbetweenreadsofSCS1andSCDRintheflag-clearing sequence. Figure 11-13 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. Inapplicationsthataresubjecttosoftwarelatencyorinwhichitisimportanttoknowwhichbyteislost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register. NF — Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an SCI errorCPUinterruptrequestiftheNEIEbitinSCC3isalsoset.CleartheNFbitbyreadingSCS1and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 175

Serial Communications Interface Module (SCI) FE — Receiver Framing Error Bit Thisclearable,read-onlybitissetwhenalogic0isacceptedasthestopbit.FEgeneratesanSCIerror CPUinterruptrequestiftheFEIEbitinSCC3alsoisset.CleartheFEbitbyreadingSCS1withFEset and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected NORMAL FLAG CLEARING SEQUENCE 1 0 1 0 1 0 = = = = = = F F F F F F R R R R R R C C C C C C S S S S S S BYTE 1 BYTE 2 BYTE 3 BYTE 4 READ SCS1 READ SCS1 READ SCS1 SCRF = 1 SCRF = 1 SCRF = 1 OR = 0 OR = 0 OR = 0 READ SCDR READ SCDR READ SCDR BYTE 1 BYTE 2 BYTE 3 DELAYED FLAG CLEARING SEQUENCE 1 0 0 SCRF = 1 SCRF = OR = 1 SCRF = OR = 1 SCRF = 1OR = 1 SCRF = OR = 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 READ SCS1 READ SCS1 SCRF = 1 SCRF = 1 OR = 0 OR = 1 READ SCDR READ SCDR BYTE 1 BYTE 3 Figure 11-13. Flag Clearing Sequence PE — Receiver Parity Error Bit Thisclearable,read-onlybitissetwhentheSCIdetectsaparityerrorinincomingdata.PEgenerates anSCIerrorCPUinterruptrequestifthePEIEbitinSCC3isalsoset.ClearthePEbitbyreadingSCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected MC68HC908AP Family Data Sheet, Rev. 4 176 Freescale Semiconductor

I/O Registers 11.8.5 SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions: • Break character detected • Incoming data Address: $0017 Bit 7 6 5 4 3 2 1 Bit 0 Read: BKF RPF Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 11-14. SCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1, theFEandSCRFbitsarealsoset.In9-bitcharactertransmissions,theR8bitinSCC3iscleared.BKF doesnotgenerateaCPUinterruptrequest.ClearBKFbyreadingSCS2withBKFsetandthenreading theSCDR.Oncecleared,BKFcanbecomesetagainonlyafterlogic1sagainappearontheRxDpin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected RPF — Reception in Progress Flag Bit Thisread-onlybitissetwhenthereceiverdetectsalogic0duringtheRT1timeperiodofthestartbit search.RPFdoesnotgenerateaninterruptrequest.RPFisresetafterthereceiverdetectsfalsestart bits(usuallyfromnoiseorabaudratemismatch)orwhenthereceiverdetectsanidlecharacter.Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress 11.8.6 SCI Data Register The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register. Address: $0018 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset Figure 11-15. SCI Data Register (SCDR) R7/T7–R0/T0 — Receive/Transmit Data Bits ReadingtheSCDRaccessestheread-onlyreceiveddatabits,R7–R0.WritingtotheSCDRwritesthe data to be transmitted, T7–T0. Reset has no effect on the SCDR. NOTE Do not use read/modify/write instructions on the SCI data register. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 177

Serial Communications Interface Module (SCI) 11.8.7 SCI Baud Rate Register The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter. Address: $0019 6 5 4 3 2 1 Bit 0 Read: 0 0 SCP1 SCP0 R SCR2 SCR1 SCR0 Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented R =Reserved Figure 11-16. SCI Baud Rate Register (SCBR) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits Theseread/writebitsselectthebaudrateprescalerdivisorasshowninTable 11-6.ResetclearsSCP1 and SCP0. Table 11-6. SCI Baud Rate Prescaling SCP1 and SCP0 Prescaler Divisor (PD) 00 1 01 3 10 4 11 13 SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 11-7. Reset clears SCR2–SCR0. Table 11-7. SCI Baud Rate Selection SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Use this formula to calculate the SCI baud rate: SCI clock source baud rate = --------------------------------------------- 64×PD×BD where: SCI clock source = f or CGMXCLK BUS (selected by SCIBDSRC bit in CONFIG2 register) PD = prescaler divisor BD = baud rate divisor MC68HC908AP Family Data Sheet, Rev. 4 178 Freescale Semiconductor

I/O Registers Table 11-8 shows the SCI baud rates that can be generated with a 4.9152-MHz bus clock when f is BUS selected as SCI clock source. Table 11-8. SCI Baud Rate Selection Examples Prescaler SCR2, SCR1, Baud Rate Baud Rate SCP1 and SCP0 Divisor (PD) and SCR0 Divisor (BD) (fBUS = 4.9152 MHz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 179

Serial Communications Interface Module (SCI) MC68HC908AP Family Data Sheet, Rev. 4 180 Freescale Semiconductor

Chapter 12 Infrared Serial Communications Interface Module (IRSCI) 12.1 Introduction The MC68HC908AP64 has two SCI modules: • SCI1 is a standard SCI module, and • SCI2 is an infrared SCI module. This section describes SCI2, the infrared serial communications interface (IRSCI) module which allows high-speedasynchronouscommunicationswithperipheraldevicesandotherMCUs.ThisIRSCIconsists ofanSCImoduleforconventionalSCIfunctionsandasoftwareprogrammableinfraredencoder/decoder sub-module for encoding/decoding the serial data for connection to infrared LEDs in remote control applications. NOTE When the IRSCI is enabled, the SCTxD pin is an open-drain output and requires a pullup resistor to be connected for proper SCI operation. Features of the SCI module include the following: • Full duplex operation • Standard mark/space non-return-to-zero (NRZ) format • Programmable 8-bit or 9-bit character length • Separately enabled transmitter and receiver • Separate receiver and transmitter CPU interrupt requests • Two receiver wakeup methods: – Idle line wakeup – Address mark wakeup • Interrupt-driven operation with eight interrupt flags: – Transmitter empty – Transmission complete – Receiver full – Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection Features of the infrared (IR) sub-module include the following: • IR sub-module enable/disable for infrared SCI or conventional SCI on SCTxD and SCRxD pins • Software selectable infrared modulation/demodulation (3/16, 1/16 or 1/32 width pulses) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 181

Infrared Serial Communications Interface Module (IRSCI) 12.2 Pin Name Conventions The generic names of the IRSCI I/O pins are: • RxD (receive data) • TxD (transmit data) IRSCII/O(input/output)linesareimplementedbysharingparallelI/Oportpins.ThefullnameofanIRSCI inputoroutputreflectsthenameofthesharedportpin.Table 12-1showsthefullnamesandthegeneric names of the IRSCI I/O pins. The generic pin names appear in the text of this section. Table 12-1. Pin Name Conventions Generic Pin Names: RxD TxD Full Pin Names: PTC7/SCRxD PTC6/SCTxD NOTE When the IRSCI is enabled, the SCTxD pin is an open-drain output and requires a pullup resistor to be connected for proper SCI operation. Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 IRSCI Control Register 1 LOOPS ENSCI M WAKE ILTY PEN PTY $0040 Write: (IRSCC1) Reset: 0 0 0 0 0 0 0 0 Read: IRSCI Control Register 2 SCTIE TCIE SCRIE ILIE TE RE RWU SBK $0041 Write: (IRSCC2) Reset: 0 0 0 0 0 0 0 0 Read: R8 IRSCI Control Register 3 T8 DMARE DMATE ORIE NEIE FEIE PEIE $0042 Write: (IRSCC3) Reset: U U 0 0 0 0 0 0 Read: SCTE TC SCRF IDLE OR NF FE PE IRSCI Status Register 1 $0043 Write: (IRSCS1) Reset: 1 1 0 0 0 0 0 0 Read: BKF RPF IRSCI Status Register 2 $0044 Write: (IRSCS2) Reset: 0 0 0 0 0 0 0 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 IRSCI Data Register $0045 Write: T7 T6 T5 T4 T3 T2 T1 T0 (IRSCDR) Reset: Unaffected by reset Read: 0 IRSCI Baud Rate Register CKS SCP1 SCP0 R SCR2 SCR1 SCR0 $0046 Write: (IRSCBR) Reset: 0 0 0 0 0 0 0 0 IRSCI Infrared Control Read: 0 0 0 R R TNP1 TNP0 IREN $0047 Register Write: (IRSCIRCR) Reset: 0 0 0 0 0 0 0 0 =Unimplemented R = Reserved U = Unaffected Figure 12-1. IRSCI I/O Registers Summary MC68HC908AP Family Data Sheet, Rev. 4 182 Freescale Semiconductor

IRSCI Module Overview 12.3 IRSCI Module Overview The IRSCI consists of a serial communications interface (SCI) and a infrared interface sub-module as shown in Figure 12-2. INTERNAL BUS SCI_TxD SCTxD CGMXCLK SERIAL SCI_R32XCLK COMMUNICATIONS INFRARED INTERFACE MODULE SCI_R16XCLK SUB-MODULE BUS CLOCK (SCI) SCI_RxD SCRxD Figure 12-2. IRSCI Block Diagram The SCI module provides serial data transmission and reception, with a programmable baud rate clock based on the bus clock or the CGMXCLK. The infrared sub-module receives two clock sources from the SCI module: SCI_R16XCLK and SCI_R32XCLK.Bothreferenceclocksareusedtogeneratethenarrowpulsesduringdatatransmission. TheSCI_R16XCLKandSCI_R32XCLKareinternalclockswithfrequenciesthatare16and32timesthe baud rate respectively. Both SCI_R16XCLK and SCI_R32XCLK clocks are used for transmitting data. The SCI_R16XCLK clock is used only for receiving data. NOTE For proper SCI function (transmit or receive), the bus clock MUST be programmed to at least 32 times that of the selected baud rate. When the infrared sub-module is disabled, signals on the TxD and RxD pins pass through unchanged to the SCI module. 12.4 Infrared Functional Description Figure 12-3 shows the structure of the infrared sub-module. The infrared sub-module provides the capability of transmitting narrow pulses to an infrared LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI module. The infrared sub-module receives two clocks from the SCI. One of these two clocks is selected as the base clock to generate the 3/16, 1/16, or 1/32 bit width narrow pulses during transmission. The sub-module consists of two main blocks: the transmit encoder and the receive decoder. When transmittingdata,theSCIdatastreamisencodedbytheinfraredsub-module.Forevery"0"bit,anarrow "low" pulse is transmitted; no pulse is transmitted for "1" bits. When receiving data, the infrared pulses should be detected using an infrared photo diode for conversion to CMOS voltage levels before connecting to the RxD pin for the infrared decoder. The SCI data stream is reconstructed by stretching the "0" pulses. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 183

Infrared Serial Communications Interface Module (IRSCI) TNP[1:0] IREN TRANSMIT IR_TxD SCI_TxD ENCODER MUX SCTxD SCI_R32XCLK SCI_R16XCLK IR_RxD RECEIVE SCRxD DECODER SCI_RxD MUX Figure 12-3. Infrared Sub-Module Diagram 12.4.1 Infrared Transmit Encoder Theinfraredtransmitencoderconvertsthe"0"bitsintheserialdatastreamfromtheSCImoduletonarrow "low" pulses, to the TxD pin. The narrow pulse is sent with a duration of 1/32, 1/16, or 3/16 of a data bit width. When two consecutive zeros are sent, the two consecutive narrow pulses will be separated by a time equal to a data bit width. DATA BIT WIDTH DETERMINED BY BAUD RATE SCI DATA INFRARED SCI DATA PULSE WIDTH = 1/32, 1/16, OR 3/16 DATA BIT WIDTH Figure 12-4. Infrared SCI Data Example 12.4.2 Infrared Receive Decoder TheinfraredreceivedecoderconvertslownarrowpulsesfromtheRxDpintostandardSCIdatabits.The referenceclock,SCI_R16XCLK,clocksafourbitinternalcounterwhichcountsfrom0to15.Anincoming pulsestartstheinternalcounteranda"0"issentouttotheIR_RxDoutput.Subsequentincomingpulses are ignored when the counter count is between 0 and 7; IR_RxD remains "0". Once the counter passes 7, an incoming pulse will reset the counter; IR_RxD remains "0". When the counter reaches 15, the IR_RxDoutputreturnsto"1",thecounterstopsandwaitsforfurtherpulses.Apulseisinterpretedasjitter if it arrives shortly after the counter reaches 15; IR_RxD remains "1". MC68HC908AP Family Data Sheet, Rev. 4 184 Freescale Semiconductor

SCI Functional Description 12.5 SCI Functional Description Figure 12-5 shows the structure of the SCI. INTERNAL BUS SCI DATA SCI DATA REGISTER REGISTER R SCI_RxD SHIFRTE RCEEGIVISETER DMAINTERRUPTCONTROL TRANSMITTEINTERRUPTCONTROL RECEIVERINTERRUPTCONTROL ERRORINTERRUPTCONTROL SHITFRT ARNESGMISITTER SCI_TxD SCTIE R8 TCIE T8 SCRIE ILIE DMARE TE SCTE DMATE RE TC RWU SCRF OR ORIE SBK IDLE NF NEIE FE FEIE PE PEIE LOOPS LOOPS ENSCI WAKEUP RECEIVE FLAG TRANSMIT CONTROL CONTROL CONTROL CONTROL M BKF CKS ENSCI WAKE RPF ILTY CGMXCLK ASL BAUD RATE PEN BUS CLOCK B X GENERATOR PTY SL = 0 => X = A SL = 1 => X = B ÷16 DATA SELECTION SCI_R32XCLK CONTROL SCI_R16XCLK Figure 12-5. SCI Module Block Diagram MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 185

Infrared Serial Communications Interface Module (IRSCI) The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices,includingotherMCUs.ThetransmitterandreceiveroftheSCIoperateindependently,although theyusethesamebaudrategenerator.Duringnormaloperation,theCPUmonitorsthestatusoftheSCI, writes the data to be transmitted, and processes received data. NOTE For SCI operations, the IR sub-module is transparent to the SCI module. DataatgoingoutoftheSCItransmitteranddatagoingintotheSCIreceiver isalwaysinSCIformat.ItmakesnodifferencetotheSCImodulewhether the IR sub-module is enabled or disabled. NOTE This SCI module is a standard HC08 SCI module with the following modifications: • Acontrolbit,CKS,isaddedtotheSCIbaudratecontrolregistertoselectbetweentwoinputclocks for baud rate clock generation • The TXINV bit is removed from the SCI control register 1 12.5.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 12-6. 8-BIT DATA FORMAT PARITY BIT M IN IRSCC1 CLEAR BIT NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT BIT 9-BIT DATA FORMAT PARITY BIT M IN IRSCC1 SET BIT NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP BIT BIT Figure 12-6. SCI Data Formats 12.5.2 Transmitter Figure 12-7 shows the structure of the SCI transmitter. ThebaudrateclocksourcefortheSCIcanbeselectedbytheCKSbit,intheSCIbaudrateregister(see 12.9.7 IRSCI Baud Rate Register). 12.5.2.1 Character Length Thetransmittercanaccommodateeither8-bitor9-bitdata.ThestateoftheMbitinIRSCIcontrolregister 1(IRSCC1)determinescharacterlength.Whentransmitting9-bitdata,bitT8inIRSCIcontrolregister3 (IRSCC3) is the ninth bit (bit 8). MC68HC908AP Family Data Sheet, Rev. 4 186 Freescale Semiconductor

SCI Functional Description CKS INTERNAL BUS BUCSG MCLXOCCLKK ABSLX SCPARLEE-R DBIVAIDUEDR ÷16 SCI DATA REGISTER SL = 0 => X = A SL = 1 => X = B SCP1 11-BIT T SCP0 OP TRANSMIT AR T SHIFT REGISTER T SCR1 S S H 8 7 6 5 4 3 2 1 0 L SCI_TxD SCR2 SCR0 B ST ST MS E E U U Q Q UPT RE CE RE M DR R VI C ER ER PEN PARITY RS E MITTER CPU INT MITTER DMA S PTY GENETR8ATION LOAD FROM I SHIFT ENABL PREAMBLEALL 1s BREAKALL 0s S S AN AN DMATE TRANSMITTER TR TR DMATE CONTROL LOGIC SCTIE SCTE SCTE SBK DMATE SCTE LOOPS SCTIE SCTIE ENSCI TC TC TE TCIE TCIE Figure 12-7. SCI Transmitter 12.5.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The IRSCI data register (IRSCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in IRSCI control register 1 (IRSCC1). 2. Enablethetransmitterbywritingalogic1tothetransmitterenablebit(TE)inIRSCIcontrolregister 2 (IRSCC2). 3. Clear the SCI transmitter empty bit by first reading IRSCI status register 1 (IRSCS1) and then writing to the IRSCDR. 4. Repeat step 3 for each subsequent transmission. Atthe startof atransmission, transmitter control logic automaticallyloads thetransmit shiftregisterwith a preamble of logic 1s. After the preamble shifts out, control logic transfers the IRSCDR data into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 187

Infrared Serial Communications Interface Module (IRSCI) TheSCItransmitteremptybit,SCTE,inIRSCS1becomessetwhentheIRSCDRtransfersabytetothe transmit shift register. The SCTE bit indicates that the IRSCDR can accept new data from the internal data bus. If the SCI transmit interrupt enable bit, SCTIE, in IRSCC2 is also set, the SCTE bit generates a transmitter interrupt request. Whenthetransmitshiftregisterisnottransmittingacharacter,theTxDpingoestotheidlecondition,logic 1. If at any time software clears the ENSCI bit in IRSCI control register 1 (IRSCC1), the transmitter and receiver relinquish control of the port pins. 12.5.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in IRSCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character lengthdependsontheMbitinIRSCC1.AslongasSBKisatlogic1,transmitterlogiccontinuouslyloads breakcharactersintothetransmitshiftregister.AftersoftwareclearstheSBKbit,theshiftregisterfinishes transmittingthelastbreakcharacterandthentransmitsatleastonelogic1.Theautomaticlogic1atthe end of a break character guarantees the recognition of the start bit of the next character. TheSCIrecognizesabreakcharacterwhenastartbitisfollowedbyeightorninelogic0databitsanda logic 0 where the stop bit should be. Receiving a break character has the following effects on SCI registers: • Sets the framing error bit (FE) in IRSCS1 • Sets the SCI receiver full bit (SCRF) in IRSCS1 • Clears the SCI data register (IRSCDR) • Clears the R8 bit in IRSCC3 • Sets the break flag bit (BKF) in IRSCS2 • Maysettheoverrun(OR),noiseflag(NF),parityerror(PE),orreceptioninprogressflag(RPF)bits 12.5.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in IRSCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. NOTE Whenqueueinganidlecharacter,returntheTEbittologic1beforethestop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the IRSCDR to be lost. ToggletheTEbitforaqueuedidlecharacterwhentheSCTEbitbecomes set and just before writing the next byte to the IRSCDR. 12.5.2.5 Transmitter Interrupts The following conditions can generate CPU interrupt requests from the SCI transmitter: MC68HC908AP Family Data Sheet, Rev. 4 188 Freescale Semiconductor

SCI Functional Description • SCI transmitter empty (SCTE) — The SCTE bit in IRSCS1 indicates that the IRSCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, in IRSCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. • Transmissioncomplete(TC)—TheTCbitinIRSCS1indicatesthatthetransmitshiftregisterand theIRSCDRareemptyandthatnobreakoridlecharacterhasbeengenerated.Thetransmission complete interrupt enable bit, TCIE, in IRSCC2 enables the TC bit to generate transmitter CPU interrupt requests. 12.5.3 Receiver Figure 12-8 shows the structure of the SCI receiver. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 189

Infrared Serial Communications Interface Module (IRSCI) INTERNAL BUS SCR1 CKS SCP1 SCR2 SCI DATA REGISTER SCP0 SCR0 BUCSG MCLXOCCLKK ABSLX SCPARLEE-R DBIVAIDUEDR ÷ 16 P 11-BIT RT O A SL = 0 => X = A ST RECEIVE SHIFT REGISTER ST SL = 1 => X = B DATA SCI_RxD H 8 7 6 5 4 3 2 1 0 L RECOVERY ALL 0s BKF s 1 RPF ALL MSB T S E U Q M E T RWU RRUPT R QUEST REQUES WILATKYE WLAOKGEIUCP SIDCLREF PUINTE VICE RE RRUPT PEN PARITY R8 C R E CHECKING RROR MA SE PU INT PTY IDLE E D C ILIE ILIE DMARE SCRF SCRIE SCRIE DMARE SCRF SCRIE DMARE DMARE OR OR ORIE ORIE NF NF NEIE NEIE FE FE FEIE FEIE PE PE PEIE PEIE Figure 12-8. SCI Receiver Block Diagram 12.5.3.1 Character Length Thereceivercanaccommodateeither8-bitor9-bitdata.ThestateoftheMbitinIRSCIcontrolregister 1 (IRSCC1) determines character length. When receiving 9-bit data, bit R8 in IRSCI control register 2 (IRSCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). MC68HC908AP Family Data Sheet, Rev. 4 190 Freescale Semiconductor

SCI Functional Description 12.5.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data register (IRSCDR) is the read-only buffer between the internal data bus and the receive shift register. Afteracompletecharactershiftsintothereceiveshiftregister,thedataportionofthecharactertransfers to the IRSCDR. The SCI receiver full bit, SCRF, in IRSCI status register 1 (IRSCS1) becomes set, indicatingthatthereceivedbytecanberead.IftheSCIreceiveinterruptenablebit,SCRIE,inIRSCC2is also set, the SCRF bit generates a receiver CPU interrupt request. 12.5.3.3 Data Sampling ThereceiversamplestheRxDpinattheRTclockrate.TheRTclockisaninternalsignalwithafrequency 16timesthebaudrate.Toadjustforbaudratemismatch,theRTclockisresynchronizedatthefollowing times (see Figure 12-9): • After every start bit • After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samplesatRT8,RT9,andRT10returnsavalidlogic1andthemajorityofthenextRT8,RT9,and RT10 samples returns a valid logic 0) START BIT LSB SCI_RxD START BIT START BIT DATA SAMPLES QUALIFICATION VERIFICATION SAMPLING RT CLOCK RT CLOCK 1 1 1 1 1 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 STATE RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT CLOCK RESET Figure 12-9. Receiver Data Sampling Tolocatethestartbit,datarecoverylogicdoesanasynchronoussearchforalogic0precededbythree logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 12-2 summarizes the results of the start bit verification samples. Table 12-2. Start Bit Verification RT3, RT5, and RT7 Start Bit Noise Flag Samples Verification 000 Yes 0 001 Yes 1 010 Yes 1 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 191

Infrared Serial Communications Interface Module (IRSCI) Table 12-2. Start Bit Verification RT3, RT5, and RT7 Start Bit Noise Flag Samples Verification 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. Todeterminethevalueofadatabitandtodetectnoise,recoverylogictakessamplesatRT8,RT9,and RT10. Table 12-3 summarizes the results of the data bit samples. Table 12-3. Data Bit Recovery RT8, RT9, and RT10 Data Bit Noise Flag Samples Determination 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE TheRT8,RT9,andRT10samplesdonotaffectstartbitverification.Ifany or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. Toverifyastopbitandtodetectnoise,recoverylogictakessamplesatRT8,RT9,andRT10.Table 12-4 summarizes the results of the stop bit samples. Table 12-4. Stop Bit Recovery RT8, RT9, and RT10 Framing Noise Flag Samples Error Flag 000 1 0 001 1 1 MC68HC908AP Family Data Sheet, Rev. 4 192 Freescale Semiconductor

SCI Functional Description Table 12-4. Stop Bit Recovery RT8, RT9, and RT10 Framing Noise Flag Samples Error Flag 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 12.5.3.4 Framing Errors Ifthedatarecoverylogicdoesnotdetectalogic1wherethestopbitshouldbeinanincomingcharacter, it sets the framing error bit, FE, in IRSCS1. The FE flag is set at the same time that the SCRF bit is set. A break character that has no stop bit also sets the FE bit. 12.5.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actualstopbit.Thenanoiseerroroccurs.Ifmorethanoneofthesamplesisoutsidethestopbit,aframing erroroccurs.Inmostapplications,thebaudratetoleranceismuchmorethanthedegreeofmisalignment that is likely to occur. Asthereceiversamplesanincomingcharacter,itresynchronizestheRTclockonanyvalidfallingedge withinthecharacter.Resynchronizationwithincharacterscorrectsmisalignmentsbetweentransmitterbit times and receiver bit times. Slow Data Tolerance Figure 12-10showshowmuchaslowreceivedcharactercanbemisalignedwithoutcausinganoiseerror oraframingerror.TheslowstopbitbeginsatRT8insteadofRT1butarrivesintimeforthestopbitdata samples at RT8, RT9, and RT10. MSB STOP RECEIVER RT CLOCK 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 T T T T T T T T T 1 1 1 1 1 1 1 R R R R R R R R R T T T T T T T R R R R R R R DATA SAMPLES Figure 12-10. Slow Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. WiththemisalignedcharactershowninFigure 12-10,thereceivercounts154RTcyclesatthepointwhen the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 193

Infrared Serial Communications Interface Module (IRSCI) The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is 1----5---4-----–-----1---4---7--- ×100 = 4.54% 154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. WiththemisalignedcharactershowninFigure 12-10,thereceivercounts170RTcyclesatthepointwhen the count of the transmitting device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 1----7---0-----–-----1---6---3--- ×100 = 4.12% 170 Fast Data Tolerance Figure 12-11showshowmuchafastreceivedcharactercanbemisalignedwithoutcausinganoiseerror or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. STOP IDLE OR NEXT CHARACTER RECEIVER RT CLOCK 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 T T T T T T T T T 1 1 1 1 1 1 1 R R R R R R R R R T T T T T T T R R R R R R R DATA SAMPLES Figure 12-11. Fast Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. WiththemisalignedcharactershowninFigure 12-11,thereceivercounts154RTcyclesatthepointwhen the count of the transmitting device is 10 bit times × 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 1----5---4-----–-----1---6---0--- ×100 = 3.9˙0% 154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. WiththemisalignedcharactershowninFigure 12-11,thereceivercounts170RTcyclesatthepointwhen the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is MC68HC908AP Family Data Sheet, Rev. 4 194 Freescale Semiconductor

SCI Functional Description 1----7---0-----–-----1---7---6--- ×100 = 3.53% 170 12.5.3.6 Receiver Wakeup SothattheMCUcanignoretransmissionsintendedonlyforotherreceiversinmultiple-receiversystems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in IRSCC2 puts the receiver into a standby state during which receiver interrupts are disabled. DependingonthestateoftheWAKEbitinIRSCC1,eitheroftwoconditionsontheRxDpincanbringthe receiver out of the standby state: • Address mark — An address mark is a logic 1 in the most significant bit position of a received character.WhentheWAKEbitisset,anaddressmarkwakesthereceiverfromthestandbystate byclearingtheRWUbit.TheaddressmarkalsosetstheSCIreceiverfullbit,SCRF.Softwarecan then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. • Idleinputlinecondition—WhentheWAKEbitisclear,anidlecharacterontheRxDpinwakesthe receiverfromthestandbystatebyclearingtheRWUbit.Theidlecharacterthatwakesthereceiver does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit, ILTY,determineswhetherthereceiverbeginscountinglogic1sasidlecharacterbitsafterthestart bit or after the stop bit. NOTE Clearing the WAKE bit after the RxD pin has been idle may cause the receiver to wake up immediately. 12.5.3.7 Receiver Interrupts The following sources can generate CPU interrupt requests from the SCI receiver: • SCI receiver full (SCRF) — The SCRF bit in IRSCS1 indicates that the receive shift register has transferred a character to the IRSCDR. SCRF can generate a receiver interrupt request. Setting theSCIreceiveinterruptenablebit,SCRIE,inIRSCC2enablestheSCRFbittogeneratereceiver CPU interrupts. • Idleinput(IDLE)—TheIDLEbitinIRSCS1indicatesthat10or11consecutivelogic1sshiftedin from the RxD pin. The idle line interrupt enable bit, ILIE, in IRSCC2 enables the IDLE bit to generate CPU interrupt requests. 12.5.3.8 Error Interrupts The following receiver error flags in IRSCS1 can generate CPU interrupt requests: • Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the IRSCDR. The previous character remains in the IRSCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in IRSCC3 enables OR to generate SCI error CPU interrupt requests. • Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in IRSCC3 enables NF to generate SCI error CPU interrupt requests. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 195

Infrared Serial Communications Interface Module (IRSCI) • Framingerror(FE)—TheFEbitinIRSCS1issetwhenalogic0occurswherethereceiverexpects astopbit.Theframingerrorinterruptenablebit,FEIE,inIRSCC3enablesFEtogenerateSCIerror CPU interrupt requests. • Parity error (PE) — The PE bit in IRSCS1 is set when the SCI detects a parity error in incoming data.Theparityerrorinterruptenablebit,PEIE,inIRSCC3enablesPEtogenerateSCIerrorCPU interrupt requests. 12.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 12.6.1 Wait Mode TheSCImoduleremainsactiveaftertheexecutionofaWAITinstruction.Inwaitmode,theSCImodule registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. Refer to 7.6 Low-Power Modes for information on exiting wait mode. 12.6.2 Stop Mode The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect SCI register states. SCI module operation resumes after an external interrupt. Becausetheinternalclockisinactiveduringstopmode,enteringstopmodeduringanSCItransmission or reception results in invalid data. Refer to 7.6 Low-Power Modes for information on exiting stop mode. 12.7 SCI During Break Module Interrupts Thesystemintegrationmodule(SIM)controlswhetherstatusbitsinothermodulescanbeclearedduring interrupts generated by the break module. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its defaultstate),softwarecanreadandwriteI/Oregistersduringthebreakstatewithoutaffectingstatusbits. Somestatusbitshaveatwo-stepread/writeclearingprocedure.Ifsoftwaredoesthefirststeponsucha bitbeforethebreak,thebitcannotchangeduringthebreakstateaslongasBCFEisatlogic0.Afterthe break, doing the second step clears the status bit. 12.8 I/O Signals The two IRSCI I/O pins are: • PTC6/SCTxD — Transmit data • PTC7/SCRxD — Receive data MC68HC908AP Family Data Sheet, Rev. 4 196 Freescale Semiconductor

I/O Registers 12.8.1 PTC6/SCTxD (Transmit Data) ThePTC6/SCTxDpinistheserialdata(standardorinfrared)outputfromtheSCItransmitter.TheIRSCI shares the PTC6/SCTxD pin with portC. Whenthe IRSCI isenabled, the PTC6/SCTxD pinis an output regardless of the state of the DDRC6 bit in data direction register C (DDRC). NOTE The PTC6/SCTxD pin is an open-drain pin when configured as an output. Therefore, when configured as SCTxD or a general purpose output pin (PTC6), a pullup resistor must be connected to this pin. 12.8.2 PTC7/SCRxD (Receive Data) ThePTC7/SCRxDpinistheserialdatainputtotheIRSCIreceiver.TheIRSCIsharesthePTC7/SCRxD pin with port C. When the IRSCI is enabled, the PTC7/SCRxD pin is an input regardless of the state of the DDRC7 bit in data direction register C (DDRC). NOTE ThePTC7/SCRxD pinisanopen-drainpin whenconfigured asanoutput. Therefore, when configured as a general purpose output pin (PTC7), a pullup resistor must be connected to this pin. Table 12-5 shows a summary of I/O pin functions when the SCI is enabled. Table 12-5. SCI Pin Functions (Standard and Infrared) IRSCC1 IRSCIRCR IRSCC2 IRSCC2 TxD Pin RxD Pin [ENSCI] [IREN] [TE] [RE] 1 0 0 0 Hi-Z(1) Input ignored (terminate externally) 1 0 0 1 Hi-Z(1) Input sampled, pin should idle high 1 0 1 0 Output SCI (idle high) Input ignored (terminate externally) 1 0 1 1 Output SCI (idle high) Input sampled, pin should idle high 1 1 0 0 Hi-Z(1) Input ignored (terminate externally) 1 1 0 1 Hi-Z(1) Input sampled, pin should idle high 1 1 1 0 Output IR SCI (idle high) Input ignored (terminate externally) 1 1 1 1 Output IR SCI (idle high) Input sampled, pin should idle high 0 X X X Pins under port control (standard I/O port) 1. After completion of transmission in progress. 12.9 I/O Registers The following I/O registers control and monitor SCI operation: • IRSCI control register 1 (IRSCC1) • IRSCI control register 2 (IRSCC2) • IRSCI control register 3 (IRSCC3) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 197

Infrared Serial Communications Interface Module (IRSCI) • IRSCI status register 1 (IRSCS1) • IRSCI status register 2 (IRSCS2) • IRSCI data register (IRSCDR) • IRSCI baud rate register (IRSCBR) • IRSCI infrared control register (IRSCIRCR) 12.9.1 IRSCI Control Register 1 SCI control register 1: • Enables loop mode operation • Enables the SCI • Controls output polarity • Controls character length • Controls SCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type Address: $0040 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 LOOPS ENSCI M WAKE ILTY PEN PTY Write: Reset: 0 0 0 0 0 0 0 0 Figure 12-12. IRSCI Control Register 1 (IRSCC1) LOOPS — Loop Mode Select Bit This read/write bit enables loop mode operation for the SCI only. In loop mode the RxD pin is disconnectedfromtheSCI,andthetransmitteroutputgoesintothereceiverinput.Boththetransmitter andthereceivermustbeenabledtouseloopmode.Theinfraredencoder/decoderisnotintheloop. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled ENSCI — Enable SCI Bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = SCI enabled 0 = SCI disabled MC68HC908AP Family Data Sheet, Rev. 4 198 Freescale Semiconductor

I/O Registers M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 12-6.) Theninthbitcanserveasanextrastopbit,asareceiverwakeupsignal,orasaparitybit.Resetclears the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters WAKE — Wakeup Condition Bit Thisread/writebitdetermineswhichconditionwakesuptheSCI:alogic1(addressmark)inthemost significant bit position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup ILTY — Idle Line Type Bit This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The countingbeginseitherafterthestartbitorafterthestopbit.Ifthecountbeginsafterthestartbit,then astringoflogic1sprecedingthestopbitmaycausefalserecognitionofanidlecharacter.Beginning thecountafterthestopbitavoidsfalseidlecharacterrecognition,butrequiresproperlysynchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit PEN — Parity Enable Bit Thisread/writebitenablestheSCIparityfunction.(SeeTable12-6.)Whenenabled,theparityfunction inserts a parity bit in the most significant bit position. (See Figure 12-6.) Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled PTY — Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 12-6.) Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Table 12-6. Character Format Selection Control Bits Character Format Start Data Stop Character M PEN:PTY Parity Bits Bits Bits Length 0 0X 1 8 None 1 10 bits 1 0X 1 9 None 1 11 bits 0 10 1 7 Even 1 10 bits 0 11 1 7 Odd 1 10 bits 1 10 1 8 Even 1 11 bits 1 11 1 8 Odd 1 11 bits MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 199

Infrared Serial Communications Interface Module (IRSCI) 12.9.2 IRSCI Control Register 2 IRSCI control register 2: • Enables the following CPU interrupt requests: – Enables the SCTE bit to generate transmitter CPU interrupt requests – Enables the TC bit to generate transmitter CPU interrupt requests – Enables the SCRF bit to generate receiver CPU interrupt requests – Enables the IDLE bit to generate receiver CPU interrupt requests • Enables the transmitter • Enables the receiver • Enables SCI wakeup • Transmits SCI break characters Address: $0041 Bit 7 6 5 4 3 2 1 Bit 0 Read: SCTIE TCIE SCRIE ILIE TE RE RWU SBK Write: Reset: 0 0 0 0 0 0 0 0 Figure 12-13. IRSCI Control Register 2 (IRSCC2) SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt TCIE — Transmission Complete Interrupt Enable Bit Thisread/writebitenablestheTCbittogenerateSCItransmitterCPUinterruptrequests.Resetclears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests SCRIE — SCI Receive Interrupt Enable Bit Thisread/writebitenablestheSCRFbittogenerateSCIreceiverCPUinterruptrequests.Resetclears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt ILIE — Idle Line Interrupt Enable Bit Thisread/writebitenablestheIDLEbittogenerateSCIreceiverCPUinterruptrequests.Resetclears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests TE — Transmitter Enable Bit Settingthisread/writebitbeginsthetransmissionbysendingapreambleof10or11logic1sfromthe transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmissioninprogressbeforetheTxDreturnstotheidlecondition(logic1).Clearingandthensetting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled MC68HC908AP Family Data Sheet, Rev. 4 200 Freescale Semiconductor

I/O Registers NOTE WritingtotheTEbitisnotallowedwhentheenableSCIbit(ENSCI)isclear. ENSCI is in SCI control register 1. RE — Receiver Enable Bit Settingthisread/writebitenablesthereceiver.ClearingtheREbitdisablesthereceiverbutdoesnot affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RWU — Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. TheWAKEbitinIRSCC1determineswhetheranidleinputoranaddressmarkbringsthereceiverout of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK — Send Break Bit Settingandthenclearingthisread/writebittransmitsabreakcharacterfollowedbyalogic1.Thelogic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted NOTE DonottoggletheSBKbitimmediatelyaftersettingtheSCTEbit.Toggling SBKbeforethepreamblebeginscausestheSCItosendabreakcharacter instead of a preamble. 12.9.3 IRSCI Control Register 3 IRSCI control register 3: • Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted • Enables the following interrupts: – Receiver overrun interrupts – Noise error interrupts – Framing error interrupts – Parity error interrupts Address: $0042 Bit 7 6 5 4 3 2 1 Bit 0 Read: R8 T8 DMARE DMATE ORIE NEIE FEIE PEIE Write: Reset: U U 0 0 0 0 0 0 = Unimplemented U = Unaffected Figure 12-14. IRSCI Control Register 3 (IRSCC3) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 201

Infrared Serial Communications Interface Module (IRSCI) R8 — Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the IRSCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character.T8isloadedintothetransmitshiftregisteratthesametimethattheIRSCDRisloadedinto the transmit shift register. Reset has no effect on the T8 bit. DMARE — DMA Receive Enable Bit CAUTION TheDMAmoduleisnotincludedonthisMCU.Writingalogic1toDMARE or DMATE may adversely affect MCU performance. 1=DMAnotenabledtoserviceSCIreceiverDMAservicerequestsgeneratedbytheSCRFbit(SCI receiver CPU interrupt requests enabled) 0=DMAnotenabledtoserviceSCIreceiverDMAservicerequestsgeneratedbytheSCRFbit(SCI receiver CPU interrupt requests enabled) DMATE — DMA Transfer Enable Bit CAUTION TheDMAmoduleisnotincludedonthisMCU.Writingalogic1toDMARE or DMATE may adversely affect MCU performance. 1 = SCTE DMA service requests enabled; SCTE CPU interrupt requests disabled 0 = SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled ORIE — Receiver Overrun Interrupt Enable Bit Thisread/writebitenablesSCIerrorCPUinterruptrequestsgeneratedbythereceiveroverrunbit,OR. Reset clears ORIE. 1 = SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled NEIE — Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = SCI error CPU interrupt requests from NE bit enabled 0 = SCI error CPU interrupt requests from NE bit disabled FEIE — Receiver Framing Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = SCI error CPU interrupt requests from FE bit enabled 0 = SCI error CPU interrupt requests from FE bit disabled PEIE — Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the parity error bit, PE. (See 12.9.4 IRSCI Status Register 1.) Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled MC68HC908AP Family Data Sheet, Rev. 4 202 Freescale Semiconductor

I/O Registers 12.9.4 IRSCI Status Register 1 SCI status register 1 contains flags to signal these conditions: • Transfer of IRSCDR data to transmit shift register complete • Transmission complete • Transfer of receive shift register data to IRSCDR complete • Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error Address: $0043 Bit 7 6 5 4 3 2 1 Bit 0 Read: SCTE TC SCRF IDLE OR NF FE PE Write: Reset: 1 1 0 0 0 0 0 0 =Unimplemented Figure 12-15. IRSCI Status Register 1 (IRSCS1) SCTE — SCI Transmitter Empty Bit Thisclearable,read-onlybitissetwhentheIRSCDRtransfersacharactertothetransmitshiftregister. SCTEcangenerateanSCItransmitterCPUinterruptrequest.WhentheSCTIEbitinIRSCC2isset, SCTEgeneratesanSCItransmitterCPUinterruptrequest.Innormaloperation,cleartheSCTEbitby reading IRSCS1 with SCTE set and then writing to IRSCDR. Reset sets the SCTE bit. 1 = IRSCDR data transferred to transmit shift register 0 = IRSCDR data not transferred to transmit shift register TC — Transmission Complete Bit Thisread-onlybitissetwhentheSCTEbitisset,andnodata,preamble,orbreakcharacterisbeing transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in IRSCC2 is also set.TCisautomaticallyclearedwhendata,preambleorbreakisqueuedandreadytobesent.There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF — SCI Receiver Full Bit Thisclearable,read-onlybitissetwhenthedatainthereceiveshiftregistertransferstotheSCIdata register.SCRFcangenerateanSCIreceiverCPUinterruptrequest.WhentheSCRIEbitinIRSCC2 is set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading IRSCS1 with SCRF set and then reading the IRSCDR. Reset clears SCRF. 1 = Received data available in IRSCDR 0 = Data not available in IRSCDR IDLE — Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in IRSCC2 is also set. Clear the IDLEbitbyreadingIRSCS1withIDLEsetandthenreadingtheIRSCDR.Afterthereceiverisenabled, MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 203

Infrared Serial Communications Interface Module (IRSCI) it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also,aftertheIDLEbithasbeencleared,avalidcharactermustagainsettheSCRFbitbeforeanidle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) OR — Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the IRSCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIEbitinIRSCC3isalsoset.Thedataintheshiftregisterislost,butthedataalreadyintheIRSCDR isnotaffected.CleartheORbitbyreadingIRSCS1withORsetandthenreadingtheIRSCDR.Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun Software latency may allow an overrun to occur between reads of IRSCS1 and IRSCDR in the flag-clearingsequence.Figure 12-16showsthenormalflag-clearingsequenceandanexampleofan overruncausedbyadelayedflag-clearingsequence.ThedelayedreadofIRSCDRdoesnotclearthe OR bit because OR was not set when IRSCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the IRSCDR instead of byte 2. Inapplicationsthataresubjecttosoftwarelatencyorinwhichitisimportanttoknowwhichbyteislost due to an overrun, the flag-clearing routine can check the OR bit in a second read of IRSCS1 after reading the data register. NORMAL FLAG CLEARING SEQUENCE 1 0 1 0 1 0 = = = = = = F F F F F F R R R R R R C C C C C C S S S S S S BYTE 1 BYTE 2 BYTE 3 BYTE 4 READ IRSCS1 READ IRSCS1 READ IRSCS1 SCRF = 1 SCRF = 1 SCRF = 1 OR = 0 OR = 0 OR = 0 READ IRSCDR READ IRSCDR READ IRSCDR BYTE 1 BYTE 2 BYTE 3 DELAYED FLAG CLEARING SEQUENCE 1 0 0 SCRF = 1 SCRF = OR = 1 SCRF = OR = 1 SCRF = 1OR = 1 SCRF = OR = 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 READ IRSCS1 READ IRSCS1 SCRF = 1 SCRF = 1 OR = 0 OR = 1 READ IRSCDR READ IRSCDR BYTE 1 BYTE 3 Figure 12-16. Flag Clearing Sequence MC68HC908AP Family Data Sheet, Rev. 4 204 Freescale Semiconductor

I/O Registers NF — Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an SCI errorCPUinterruptrequestiftheNEIEbitinIRSCC3isalsoset.CleartheNFbitbyreadingIRSCS1 and then reading the IRSCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected FE — Receiver Framing Error Bit Thisclearable,read-onlybitissetwhenalogic0isacceptedasthestopbit.FEgeneratesanSCIerror CPU interrupt request if the FEIE bit in IRSCC3 also is set. Clear the FE bit by reading IRSCS1 with FE set and then reading the IRSCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected PE — Receiver Parity Error Bit Thisclearable,read-onlybitissetwhentheSCIdetectsaparityerrorinincomingdata.PEgenerates an SCI error CPU interrupt request if the PEIE bit in IRSCC3 is also set. Clear the PE bit by reading IRSCS1 with PE set and then reading the IRSCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected 12.9.5 IRSCI Status Register 2 IRSCI status register 2 contains flags to signal the following conditions: • Break character detected • Incoming data Address: $0044 Bit 7 6 5 4 3 2 1 Bit 0 Read: BKF RPF Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 12-17. IRSCI Status Register 2 (IRSCS2) BKF — Break Flag Bit Thisclearable,read-onlybitissetwhentheSCIdetectsabreakcharacterontheRxDpin.InIRSCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in IRSCC3 is cleared. BKFdoesnotgenerateaCPUinterruptrequest.ClearBKFbyreadingIRSCS2withBKFsetandthen reading the IRSCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 205

Infrared Serial Communications Interface Module (IRSCI) RPF — Reception in Progress Flag Bit Thisread-onlybitissetwhenthereceiverdetectsalogic0duringtheRT1timeperiodofthestartbit search.RPFdoesnotgenerateaninterruptrequest.RPFisresetafterthereceiverdetectsfalsestart bits(usuallyfromnoiseorabaudratemismatch)orwhenthereceiverdetectsanidlecharacter.Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress 12.9.6 IRSCI Data Register The IRSCI data register is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the IRSCI data register. Address: $0045 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset Figure 12-18. IRSCI Data Register (IRSCDR) R7/T7–R0/T0 — Receive/Transmit Data Bits ReadingtheIRSCDRaccessestheread-onlyreceiveddatabits,R7–R0.WritingtotheIRSCDRwrites the data to be transmitted, T7–T0. Reset has no effect on the IRSCDR. NOTE Do not use read/modify/write instructions on the IRSCI data register. 12.9.7 IRSCI Baud Rate Register The baud rate register selects the baud rate for both the receiver and the transmitter. Address: $0046 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 CKS SCP1 SCP0 R SCR2 SCR1 SCR0 Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented R =Reserved Figure 12-19. IRSCI Baud Rate Register (IRSCBR) CKS — Baud Clock Input Select This read/write bit selects the source clock for the baud rate generator. Reset clears the CKS bit, selecting CGMXCLK. 1 = Bus clock drives the baud rate generator 0 = CGMXCLK drives the baud rate generator SCP1 and SCP0 — SCI Baud Rate Prescaler Bits Theseread/writebitsselectthebaudrateprescalerdivisorasshowninTable 12-7.ResetclearsSCP1 and SCP0. MC68HC908AP Family Data Sheet, Rev. 4 206 Freescale Semiconductor

I/O Registers Table 12-7. SCI Baud Rate Prescaling SCP1 and SCP0 Prescaler Divisor (PD) 00 1 01 3 10 4 11 13 SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 12-8. Reset clears SCR2–SCR0. Table 12-8. IRSCI Baud Rate Selection SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Use this formula to calculate the SCI baud rate: SCI clock source baud rate = --------------------------------------------- 16×PD×BD where: SCI clock source = f or CGMXCLK BUS (selected by CKS bit) PD = prescaler divisor BD = baud rate divisor Table 12-9 shows the SCI baud rates that can be generated with a 4.9152-MHz bus clock when f is BUS selected as SCI clock source. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 207

Infrared Serial Communications Interface Module (IRSCI) Table 12-9. IRSCI Baud Rate Selection Examples Prescaler SCR2, SCR1, Baud Rate Baud Rate SCP1 and SCP0 Divisor (PD) and SCR0 Divisor (BD) (fBUS = 4.9152 MHz) 00 1 000 1 — 00 1 001 2 — 00 1 010 4 76800 00 1 011 8 38400 00 1 100 16 19200 00 1 101 32 9600 00 1 110 64 4800 00 1 111 128 2400 01 3 000 1 — 01 3 001 2 51200 01 3 010 4 25600 01 3 011 8 12800 01 3 100 16 6400 01 3 101 32 3200 01 3 110 64 1600 01 3 111 128 800 10 4 000 1 76800 10 4 001 2 38400 10 4 010 4 19200 10 4 011 8 9600 10 4 100 16 4800 10 4 101 32 2400 10 4 110 64 1200 10 4 111 128 600 11 13 000 1 23632 11 13 001 2 11816 11 13 010 4 5908 11 13 011 8 2954 11 13 100 16 1477 11 13 101 32 739 11 13 110 64 369 11 13 111 128 185 MC68HC908AP Family Data Sheet, Rev. 4 208 Freescale Semiconductor

I/O Registers 12.9.8 IRSCI Infrared Control Register The infrared control register contains the control bits for the infrared sub-module. • Enables the infrared sub-module • Selects the infrared transmitter narrow pulse width Address: $0047 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 R R TNP1 TNP0 IREN Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented R =Reserved Figure 12-20. IRSCI Infrared Control Register (IRSCIRCR) TNP1 and TNP0 — Transmitter Narrow Pulse Bits Theseread/writebitsselecttheinfraredtransmitternarrowpulsewidthasshowninTable12-10.Reset clears TNP1 and TNP0. Table 12-10. Infrared Narrow Pulse Selection TNP1 and TNP0 Prescaler Divisor (PD) 00 SCI transmits a 3/16 narrow pulse 01 SCI transmits a 1/16 narrow pulse 10 SCI transmits a 1/32 narrow pulse 11 IREN — Infrared Enable Bit This read/write bit enables the infrared sub-module for encoding and decoding the SCI data stream. When this bit is clear, the infrared sub-module is disabled. Reset clears the IREN bit. 1 = infrared sub-module enabled 0 = infrared sub-module disabled MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 209

Infrared Serial Communications Interface Module (IRSCI) MC68HC908AP Family Data Sheet, Rev. 4 210 Freescale Semiconductor

Chapter 13 Serial Peripheral Interface Module (SPI) 13.1 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 13.2 Features Features of the SPI module include the following: • Full-duplex operation • Master and slave modes • Double-buffered operation with separate transmit and receive registers • Four master mode frequencies (maximum = bus frequency ÷ 2) • Maximum slave mode frequency = bus frequency • Serial clock with programmable polarity and phase • Two separately enabled interrupts: – SPRF (SPI receiver full) – SPTE (SPI transmitter empty) • Mode fault error flag with CPU interrupt capability • Overflow error flag with CPU interrupt capability • Programmable wired-OR mode 13.3 Pin Name Conventions and I/O Register Addresses ThetextthatfollowsdescribestheSPI.TheSPII/OpinnamesareSS(slaveselect),SPSCK(SPIserial clock), CGND (clock ground), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. ThefullnamesoftheSPII/OpinsareshowninTable 13-1.Thegenericpinnamesappearinthetextthat follows. Table 13-1. Pin Name Conventions SPI Generic MISO MOSI SS SPSCK CGND Pin Names: Full SPI Pin Names: SPI PTC2/MISO PTC3/MOSI PTC4/SS PTC5/SPSCK VSS Figure 13-1 summarizes the SPI I/O registers. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 209

Serial Peripheral Interface Module (SPI) = Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE $0010 SPI Control Register (SPCR) Write: Reset: 0 0 1 0 1 0 0 0 SPI Status and Control Read: SPRF OVRF MODF SPTE ERRIE MODFEN SPR1 SPR0 $0011 Register Write: (SPSCR) Reset: 0 0 0 0 1 0 0 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 SPI Data Register $0012 Write: T7 T6 T5 T4 T3 T2 T1 T0 (SPDR) Reset: Unaffected by reset =Unimplemented R =Reserved Figure 13-1. SPI I/O Register Summary 13.4 Functional Description Figure 13-2 shows the structure of the SPI module. TheSPImoduleallowsfull-duplex,synchronous,serialcommunicationbetweentheMCUandperipheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt-driven. The following paragraphs describe the operation of the SPI module. 13.4.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE Configure the SPI modules as master or slave before enabling them. EnablethemasterSPIbeforeenablingtheslaveSPI.DisabletheslaveSPI before disabling the master SPI. (See 13.13.1 SPI Control Register.) OnlyamasterSPImodulecaninitiatetransmissions.SoftwarebeginsthetransmissionfromamasterSPI modulebywritingtothetransmitdataregister.Iftheshiftregisterisempty,thebyteimmediatelytransfers totheshiftregister,settingtheSPItransmitteremptybit,SPTE.ThebytebeginsshiftingoutontheMOSI pin under the control of the serial clock. (See Figure 13-3.) The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 13.13.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. AsthebyteshiftsoutontheMOSIpinofthemaster,anotherbyteshiftsinfromtheslaveonthemaster’s MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control registerwithSPRFsetandthenreadingtheSPIdataregister.WritingtotheSPIdataregisterclearsthe SPTE bit. MC68HC908AP Family Data Sheet, Rev. 4 210 Freescale Semiconductor

Functional Description INTERNAL BUS TRANSMIT DATA REGISTER CGMOUT ÷2 SHIFT REGISTER FROM SIM 7 6 5 4 3 2 1 0 MISO ÷2 MOSI CLOCK ÷8 RECEIVE DATA REGISTER DIVIDER ÷32 PIN ÷128 CONTROL LOGIC CLOCK SPSCK SPMSTR SPE SELECT CLOCK M LOGIC S SS SPR1 SPR0 SPMSTR CPHA CPOL RESERVED MODFEN SPWOM TRANSMITTER CPU INTERRUPT REQUEST ERRIE SPI SPTIE RESERVED CONTROL SPRIE RECEIVER/ERROR CPU INTERRUPT REQUEST R SPE SPRF SPTE OVRF MODF Figure 13-2. SPI Module Block Diagram MASTER MCU SLAVE MCU MISO MISO SHIFT REGISTER MOSI MOSI SHIFT REGISTER SPSCK SPSCK BAUD RATE SS SS GENERATOR V DD Figure 13-3. Full-Duplex Master-Slave Connections MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 211

Serial Peripheral Interface Module (SPI) 13.4.2 Slave Mode TheSPIoperatesinslavemodewhentheSPMSTRbitisclear.Inslavemode,theSPSCKpinistheinput fortheserialclockfromthemasterMCU.Beforeadatatransmissionoccurs,theSSpinoftheslaveSPI mustbeatlogic0.SSmustremainlowuntilthetransmissioniscomplete.(See13.7.2ModeFaultError.) InaslaveSPImodule,dataenterstheshiftregisterunderthecontroloftheserialclockfromthemaster SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register, andtheSPRFbitisset.Topreventanoverflowcondition,slavesoftwarethenmustreadthereceivedata register before another full byte enters the shift register. ThemaximumfrequencyoftheSPSCKforanSPIconfiguredasaslaveisthebusclockspeed(whichis twiceasfastasthefastestmasterSPSCKclockthatcanbegenerated).ThefrequencyoftheSPSCKfor an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controlsthespeedoftheSPSCKgeneratedbyanSPIconfiguredasamaster.Therefore,thefrequency oftheSPSCKforanSPIconfiguredasaslavecanbeanyfrequencylessthanorequaltothebusspeed. When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmitdataregister.Theslavemustwritetoitstransmitdataregisteratleastonebuscyclebeforethe masterstartsthenexttransmission.Otherwise,thebytealreadyintheslaveshiftregistershiftsoutonthe MISOpin.Datawrittentotheslaveshiftregisterduringatransmissionremainsinabufferuntiltheendof the transmission. When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is clear, the falling edge of SS starts a transmission. (See 13.5 Transmission Formats.) NOTE SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge. 13.5 Transmission Formats DuringanSPItransmission,dataissimultaneouslytransmitted(shiftedoutserially)andreceived(shifted in serially). A serial clock synchronizes shifting and sampling on the two serial data lines. A slave select lineallowsselectionofanindividualslaveSPIdevice;slavedevicesthatarenotselecteddonotinterfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate multiple-master bus contention. 13.5.1 Clock Phase and Polarity Controls Software can select any of four combinations of serial clock (SPSCK) phase and polarity using two bits in the SPI control register (SPCR). Theclock polarityis specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. Theclockphase(CPHA)controlbitselectsoneoftwofundamentallydifferenttransmissionformats.The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. NOTE BeforewritingtotheCPOLbitortheCPHAbit,disabletheSPIbyclearing the SPI enable bit (SPE). MC68HC908AP Family Data Sheet, Rev. 4 212 Freescale Semiconductor

Transmission Formats 13.5.2 Transmission Format When CPHA = 0 Figure 13-4 shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. TheMISOsignalistheoutputfromtheslave,andtheMOSIsignalistheoutputfromthemaster.TheSS lineistheslaveselectinputtotheslave.TheslaveSPIdrivesitsMISOoutputonlywhenitsslaveselect input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is notshownbutisassumedtobeinactive.TheSSpinofthemastermustbehighormustbereconfigured as general-purpose I/O not affecting the SPI. (See 13.7.2 Mode Fault Error.) When CPHA = 0, the first SPSCKedgeistheMSBcapturestrobe.Therefore,theslavemustbegindrivingitsdatabeforethefirst SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave’s SS pin must be toggled back to high and then low again between each byte transmitted as shown in Figure 13-5. SPSCK CYCLE # 1 2 3 4 5 6 7 8 FOR REFERENCE SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB FROM MASTER MISO MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB FROM SLAVE SS; TO SLAVE CAPTURE STROBE Figure 13-4. Transmission Format (CPHA = 0) MISO/MOSI BYTE 1 BYTE 2 BYTE 3 MASTERSS SLAVESS CPHA = 0 SLAVESS CPHA = 1 Figure 13-5. CPHA/SS Timing When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore,theSPIdataregisteroftheslavemustbeloadedwithtransmitdatabeforethefallingedgeof SS.Anydatawrittenafterthefallingedgeisstoredinthetransmitdataregisterandtransferredtotheshift register after the current transmission. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 213

Serial Peripheral Interface Module (SPI) 13.5.3 Transmission Format When CPHA = 1 Figure 13-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagramsincetheserialclock(SPSCK),masterin/slaveout(MISO),andmasterout/slavein(MOSI)pins are directlyconnected between the master and the slave.The MISOsignal isthe output from the slave, andtheMOSIsignalistheoutputfromthemaster.TheSSlineistheslaveselectinputtotheslave.The slaveSPIdrivesitsMISOoutputonlywhenitsslaveselectinput(SS)isatlogic0,sothatonlytheselected slavedrivestothemaster.TheSSpinofthemasterisnotshownbutisassumedtobeinactive.TheSS pinofthemastermustbehighormustbereconfiguredasgeneral-purposeI/OnotaffectingtheSPI.(See 13.7.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remainlowbetweentransmissions.Thisformatmaybepreferableinsystemshavingonlyonemasterand only one slave driving the MISO data line. SPSCK CYCLE # 1 2 3 4 5 6 7 8 FOR REFERENCE SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB FROM MASTER MISO FROM SLAVE MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ; SS TO SLAVE CAPTURE STROBE Figure 13-6. Transmission Format (CPHA = 1) WhenCPHA=1foraslave,thefirstedgeoftheSPSCKindicatesthebeginningofthetransmission.This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK.Anydatawrittenafterthefirstedgeisstoredinthetransmitdataregisterandtransferredtothe shift register after the current transmission. 13.5.4 Transmission Initiation Latency WhentheSPIisconfiguredasamaster(SPMSTR=1),writingtotheSPDRstartsatransmission.CPHA hasnoeffectonthedelaytothestartofthetransmission,butitdoesaffecttheinitialstateoftheSPSCK signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and thestartoftheSPItransmission.(SeeFigure 13-7.)TheinternalSPIclockinthemasterisafree-running derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and SPMSTRbitsareset.SPSCKedgesoccurhalfwaythroughthelowtimeoftheinternalMCUclock.Since the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower SPSCK. This uncertainty causes the variation in the initiation delay shown in Figure 13-7. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. MC68HC908AP Family Data Sheet, Rev. 4 214 Freescale Semiconductor

Queuing Transmission Data WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 6 BIT 5 SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE 1 2 3 NUMBER INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK SPSCK = INTERNAL CLOCK÷2; EARLIEST 2 POSSIBLE START POINTS WRITE LATEST TO SPDR BUS CLOCK EARLIEST SPSCK = INTERNAL CLOCK÷8; LATEST 8 POSSIBLE START POINTS WRITE TO SPDR BUS CLOCK EARLIEST SPSCK = INTERNAL CLOCK÷32; LATEST 32 POSSIBLE START POINTS WRITE TO SPDR BUS CLOCK EARLIEST SPSCK = INTERNAL CLOCK÷128; LATEST 128 POSSIBLE START POINTS Figure 13-7. Transmission Start Delay (Master) 13.6 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready toacceptnewdata.WritetothetransmitdataregisteronlywhentheSPTEbitishigh.Figure 13-8shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL = 1:0). MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 215

Serial Peripheral Interface Module (SPI) WRITE TO SPDR 1 3 8 SPTE 2 5 10 SPSCK CPHA:CPOL = 1:0 MOSI MSBBIT BIT BIT BIT BIT BITLSBMSBBIT BIT BIT BIT BIT BITLSBMSBBIT BIT BIT 6 5 4 3 2 1 6 5 4 3 2 1 6 5 4 BYTE 1 BYTE 2 BYTE 3 SPRF 4 9 READ SPSCR 6 11 READ SPDR 7 12 1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. 7 CPU READS SPDR, CLEARING SPRF BIT. 2 BYTE 1 TRANSFERS FROM TRANSMIT DATA 8 CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 3 AND CLEARING SPTE BIT. 9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT 3 CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2 REGISTER TO RECEIVE DATA REGISTER, SETTING AND CLEARING SPTE BIT. SPRF BIT. 4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT 10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO RECEIVE DATA REGISTER, SETTING REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. SPRF BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 5 BYTE 2 TRANSFERS FROM TRANSMIT DATA 12 CPU READS SPDR, CLEARING SPRF BIT. REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 6 CPU READS SPSCR WITH SPRF BIT SET. Figure 13-8. SPRF/SPTE CPU Interrupt Timing The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes betweentransmissionsasinasystemwithasingledatabuffer.Also,ifnonewdataiswrittentothedata buffer, the last value contained in the shift register is the next data word to be transmitted. Foranidlemasteroridleslavethathasnodataloadedintoitstransmitbuffer,theSPTEissetagainno more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur untilthetransmissioniscompleted.Thisimpliesthataback-to-backwritetothetransmitdataregisteris not possible. The SPTE indicates when the next write can occur. 13.7 Error Conditions The following flags signal SPI error conditions: • Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register. • Mode fault error (MODF) — The MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register. MC68HC908AP Family Data Sheet, Rev. 4 216 Freescale Semiconductor

Error Conditions 13.7.1 Overflow Error The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe occursinthemiddleofSPSCKcycle7.(SeeFigure 13-4andFigure 13-6.)Ifanoverflowoccurs,alldata received after the overflow and before the OVRF bit is cleared does not transfer to the receive data registeranddoesnotsettheSPIreceiverfullbit(SPRF).Theunreaddatathattransferredtothereceive dataregisterbeforetheoverflowoccurredcanstillberead.Therefore,anoverflowerroralwaysindicates the loss of data. Clear the overflow flag by reading the SPI status and control register and then reading the SPI data register. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 13-11.) ItisnotpossibletoenableMODForOVRFindividuallytogenerateareceiver/errorCPUinterruptrequest. However, leaving MODFEN low prevents MODF from being set. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 13-9 shows how it is possible to miss an overflow. The first part of Figure 13-9 shows how it is possible to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by thesecondtransmissionexample,theOVRFbitcanbesetinbetweenthetimethatSPSCRandSPDR are read. BYTE 1 BYTE 2 BYTE 3 BYTE 4 1 4 6 8 SPRF OVRF READ 2 5 SPSCR READ 3 7 SPDR 1 BYTE 1 SETS SPRF BIT. 5 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. 6 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. 3 CPU READS BYTE 1 IN SPDR, 7 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, CLEARING SPRF BIT. BUT NOT OVRF BIT. 4 BYTE 2 SETS SPRF BIT. 8 BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST. Figure 13-9. Missed Read of Overflow Condition Inthiscase,anoverflowcanbemissedeasily.SincenomoreSPRFinterruptscanbegenerateduntilthis OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To preventthis,eitherenabletheOVRFinterruptordoanotherreadoftheSPSCRfollowingthereadofthe SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissionscansettheSPRFbit.Figure 13-10illustratesthisprocess.Generally,toavoidthissecond SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 217

Serial Peripheral Interface Module (SPI) BYTE 1 BYTE 2 BYTE 3 BYTE 4 SPI RECEIVE 1 5 7 11 COMPLETE SPRF OVRF READ 2 4 6 9 12 14 SPSCR READ 3 8 10 13 SPDR 1 BYTE 1 SETS SPRF BIT. 8 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. 9 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 3 CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 4 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 5 BYTE 2 SETS SPRF BIT. 12 CPU READS SPSCR. 6 CPU READS SPSCR WITH SPRF BIT SET 13 CPU READS BYTE 4 IN SPDR, AND OVRF BIT CLEAR. CLEARING SPRF BIT. 7 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. Figure 13-10. Clearing SPRF When OVRF Interrupt Is Not Enabled 13.7.2 Mode Fault Error SettingtheSPMSTRbitselectsmastermodeandconfigurestheSPSCKandMOSIpinsasoutputsand the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pinsasinputsandtheMISOpinasanoutput.Themodefaultbit,MODF,becomessetanytimethestate of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR. To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if: • The SS pin of a slave SPI goes high during a transmission • The SS pin of a master SPI goes low at any time For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFENbitdoesnotcleartheMODFflagbutdoespreventMODFfrombeingsetagainafterMODFis cleared. MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 13-11.) ItisnotpossibletoenableMODForOVRFindividuallytogenerateareceiver/errorCPUinterruptrequest. However, leaving MODFEN low prevents MODF from being set. In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master SPI causes the following events to occur: • If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. • The SPE bit is cleared. • The SPTE bit is set. • The SPI state counter is cleared. • The data direction register of the shared I/O port regains control of port drivers. MC68HC908AP Family Data Sheet, Rev. 4 218 Freescale Semiconductor

Interrupts NOTE TopreventbuscontentionwithanothermasterSPIafteramodefaulterror, clearallSPIbitsofthedatadirectionregisterofthesharedI/Oportbefore enabling the SPI. Whenconfiguredasaslave(SPMSTR=0),theMODFflagissetifSSgoeshighduringatransmission. When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of the eighth data bit. When CPHA = 1, the transmission begins whentheSPSCKleavesitsidlelevelandSSisalreadylow.ThetransmissioncontinuesuntiltheSPSCK returns to its idle level following the shift of the last data bit. (See 13.5 Transmission Formats.) NOTE Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit hasnofunctionwhenSPE=0.ReadingSPMSTRwhenMODF = 1shows the difference between a MODF occurring when the SPI is a master and when it is a slave. WhenCPHA = 0,aMODFoccursifaslaveisselected(SSisatlogic0)and later unselected (SS is at logic 1) even if no SPSCK is sent to that slave. ThishappensbecauseSSatlogic0indicatesthestartofthetransmission (MISOdrivenoutwiththevalueofMSB)forCPHA = 0.WhenCPHA = 1,a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIEbitisset.TheMODFbitdoesnotcleartheSPEbitorresettheSPIinanyway.Softwarecanabort the SPI transmission by clearing the SPE bit of the slave. NOTE A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. TocleartheMODFflag,readtheSPSCRwiththeMODFbitsetandthenwritetotheSPCRregister.This entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared. 13.8 Interrupts Four SPI status flags can be enabled to generate CPU interrupt requests. Table 13-2. SPI Interrupts Flag Request SPTE SPItransmitter CPUinterrupt request Transmitterempty (SPTIE=1, SPE=1) SPRF SPIreceiverCPUinterrupt request Receiver full (SPRIE=1) OVRF SPIreceiver/error interrupt request (ERRIE=1) Overflow MODF SPIreceiver/error interrupt request (ERRIE=1) Mode fault MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 219

Serial Peripheral Interface Module (SPI) Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register. The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1). The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt requests, regardless of the state of the SPE bit. (See Figure 13-11.) Theerrorinterruptenablebit(ERRIE)enablesboththeMODFandOVRFbitstogenerateareceiver/error CPU interrupt request. The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests. NOT AVAILABLE SPTE SPTIE SPE SPI TRANSMITTER CPU INTERRUPT REQUEST R NOT AVAILABLE SPRIE SPRF SPI RECEIVER/ERROR CPU INTERRUPT REQUEST ERRIE MODF OVRF Figure 13-11. SPI Interrupt Request Generation The following sources in the SPI status and control register can generate CPU interrupt requests: • SPIreceiverfullbit(SPRF)—TheSPRFbitbecomesseteverytimeabytetransfersfromtheshift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI receiver/error CPU interrupt request. • SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the transmitdataregistertotheshiftregister.IftheSPItransmitinterruptenablebit,SPTIE,isalsoset, SPTE generates an SPTE CPU interrupt request. 13.9 Resetting the SPI Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following occurs: • The SPTE flag is set. • Any transmission currently in progress is aborted. MC68HC908AP Family Data Sheet, Rev. 4 220 Freescale Semiconductor

Low-Power Modes • The shift register is cleared. • The SPI state counter is cleared, making it ready for a new complete transmission. • All the SPI port logic is defaulted back to being general-purpose I/O. These items are reset only by a system reset: • All control bits in the SPCR register • All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0) • The status flags SPRF, OVRF, and MODF BynotresettingthecontrolbitswhenSPEislow,theusercanclearSPEbetweentransmissionswithout having to set all control bits again when SPE is set back high for the next transmission. By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set. 13.10 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 13.10.1 Wait Mode The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction. To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE). (See 13.8 Interrupts.) 13.10.2 Stop Mode The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset. 13.11 SPI During Break Interrupts Thesystemintegrationmodule(SIM)controlswhetherstatusbitsinothermodulescanbeclearedduring the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See Chapter 7 System Integration Module (SIM).) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its defaultstate),softwarecanreadandwriteI/Oregistersduringthebreakstatewithoutaffectingstatusbits. Somestatusbitshavea2-stepread/writeclearingprocedure.Ifsoftwaredoesthefirststeponsuchabit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 221

Serial Peripheral Interface Module (SPI) Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect. 13.12 I/O Signals The SPI module has five I/O pins and shares four of them with a parallel I/O port. They are: • MISO — Data received • MOSI — Data transmitted • SPSCK — Serial clock • SS — Slave select • CGND — Clock ground (internally connected to V ) SS The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-masterenvironment.TocommunicatewithI2Cperipherals,MOSIbecomesanopen-drainoutput when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to V . DD 13.12.1 MISO (Master In/Slave Out) MISOisoneofthetwoSPImodulepinsthattransmitsserialdata.Infullduplexoperation,theMISOpin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin. Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a high-impedance state. Whenenabled,theSPIcontrolsdatadirectionoftheMISOpinregardlessofthestateofthedatadirection register of the shared I/O port. 13.12.2 MOSI (Master Out/Slave In) MOSIisoneofthetwoSPImodulepinsthattransmitsserialdata.Infull-duplexoperation,theMOSIpin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. Whenenabled,theSPIcontrolsdatadirectionoftheMOSIpinregardlessofthestateofthedatadirection register of the shared I/O port. 13.12.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. MC68HC908AP Family Data Sheet, Rev. 4 222 Freescale Semiconductor

I/O Signals 13.12.4 SS (Slave Select) The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave,theSSisusedtoselectaslave.ForCPHA=0,theSSisusedtodefinethestartofatransmission. (See13.5TransmissionFormats.)Sinceitisusedtoindicatethestartofatransmission,theSSmustbe toggledhighandlowbetweeneachbytetransmittedfortheCPHA = 0format.However,itcanremainlow between transmissions for the CPHA = 1 format. See Figure 13-12. MISO/MOSI BYTE 1 BYTE 2 BYTE 3 MASTERSS SLAVESS CPHA = 0 SLAVESS CPHA = 1 Figure 13-12. CPHA/SS Timing WhenanSPIisconfiguredasaslave,theSSpinisalwaysconfiguredasaninput.Itcannotbeusedas ageneral-purposeI/OregardlessofthestateoftheMODFENcontrolbit.However,theMODFENbitcan still prevent the state of the SS from creating a MODF error. (See 13.13.2 SPI Status and Control Register.) NOTE A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-impedance state. The slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to preventmultiplemastersfromdrivingMOSIandSPSCK.(See13.7.2ModeFaultError.)Forthestateof theSSpintosettheMODFflag,theMODFENbitintheSPSCKregistermustbeset.IftheMODFENbit is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data directionregisterofthesharedI/Oport.WithMODFENhigh,itisaninput-onlypintotheSPIregardless of the state of the data direction register of the shared I/O port. The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register. (See Table 13-3.) Table 13-3. SPI Configuration SPE SPMSTR MODFEN SPI Configuration State ofSS Logic General-purpose I/O; 0 X(1) X Not enabled SS ignored by SPI 1 0 X Slave Input-only to SPI General-purpose I/O; 1 1 0 Master without MODF SS ignored by SPI 1 1 1 Master with MODF Input-only to SPI Note 1. X = Don’t care MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 223

Serial Peripheral Interface Module (SPI) 13.12.5 CGND (Clock Ground) CGNDisthegroundreturnfortheserialclockpin,SPSCK,andthegroundfortheportoutputbuffers.It is internally connected to V as shown in Table 13-1. SS 13.13 I/O Registers Three registers control and monitor SPI operation: • SPI control register (SPCR) • SPI status and control register (SPSCR) • SPI data register (SPDR) 13.13.1 SPI Control Register • Enables SPI module interrupt requests • Configures the SPI module as master or slave • Selects serial clock polarity and phase • Configures the SPSCK, MOSI, and MISO pins as open-drain outputs • Enables the SPI module Address: $0010 Bit 7 6 5 4 3 2 1 Bit 0 Read: SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE Write: Reset: 0 0 1 0 1 0 0 0 =Unimplemented R =Reserved Figure 13-13. SPI Control Register (SPCR) SPRIE — SPI Receiver Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled SPMSTR — SPI Master Bit This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode CPOL — Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 13-4 and Figure 13-6.) To transmit data between SPI modules, the SPI modules must have identical CPOL values. Reset clears the CPOL bit. CPHA — Clock Phase Bit This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure 13-4 and Figure 13-6.) To transmit data between SPI modules, the SPI modules must have identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between bytes. (See Figure 13-12.) Reset sets the CPHA bit. MC68HC908AP Family Data Sheet, Rev. 4 224 Freescale Semiconductor

I/O Registers SPWOM — SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins SPE — SPI Enable Thisread/writebitenablestheSPImodule.ClearingSPEcausesapartialresetoftheSPI.(See13.9 Resetting the SPI.) Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE— SPI Transmit Interrupt Enable Thisread/writebitenablesCPUinterruptrequestsgeneratedbytheSPTEbit.SPTEissetwhenabyte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit. 1 = SPTE CPU interrupt requests enabled 0 = SPTE CPU interrupt requests disabled 13.13.2 SPI Status and Control Register The SPI status and control register contains flags to signal these conditions: • Receive data register full • Failure to clear SPRF bit before next byte is received (overflow error) • Inconsistent logic level on SS pin (mode fault error) • Transmit data register empty The SPI status and control register also contains bits that perform these functions: • Enable error interrupts • Enable mode fault error detection • Select master SPI baud rate Address $0011 Bit 7 6 5 4 3 2 1 Bit 0 Read: SPRF OVRF MODF SPTE ERRIE MODFEN SPR1 SPR0 Write: Reset: 0 0 0 0 1 0 0 0 =Unimplemented Figure 13-14. SPI Status and Control Register (SPSCR) SPRF — SPI Receiver Full Bit Thisclearable,read-onlyflagisseteachtimeabytetransfersfromtheshiftregistertothereceivedata register.SPRFgeneratesaCPUinterruptrequestiftheSPRIEbitintheSPIcontrolregisterissetalso. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Reset clears the SPRF bit. 1 = Receive data register full 0 = Receive data register not full MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 225

Serial Peripheral Interface Module (SPI) ERRIE — Error Interrupt Enable Bit Thisread/writebitenablestheMODFandOVRFbitstogenerateCPUinterruptrequests.Resetclears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests OVRF — Overflow Bit Thisclearable,read-onlyflagissetifsoftwaredoesnotreadthebyteinthereceivedataregisterbefore thenextfullbyteenterstheshiftregister.Inanoverflowcondition,thebytealreadyinthereceivedata register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI statusandcontrolregisterwithOVRFsetandthenreadingthereceivedataregister.Resetclearsthe OVRF bit. 1 = Overflow 0 = No overflow MODF — Mode Fault Bit This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with theMODFENbitset.InamasterSPI,theMODFflagissetiftheSSpingoeslowatanytimewiththe MODFEN bit set. Clear the MODF bit by reading the SPI status and control register (SPSCR) with MODF set and then writing to the SPI control register (SPCR). Reset clears the MODF bit. 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level SPTE — SPI Transmitter Empty Bit This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register.SPTEgeneratesanSPTE CPUinterruptrequestiftheSPTIEbitintheSPIcontrolregisteris set also. NOTE Do not write to the SPI data register unless the SPTE bit is high. During an SPTE CPU interrupt, the CPU clears the SPTE bit by writing to the transmit data register. Reset sets the SPTE bit. 1 = Transmit data register empty 0 = Transmit data register not empty MODFEN — Mode Fault Enable Bit Thisread/writebit,whensetto1,allowstheMODFflagtobeset.IftheMODFflagisset,clearingthe MODFENdoesnotcleartheMODFflag.IftheSPIisenabledasamasterandtheMODFENbitislow, then the SS pin is available as a general-purpose I/O. If the MODFEN bit is set, then this pin is not available as a general-purpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of MODFEN. (See 13.12.4 SS (Slave Select).) If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI configuredasamaster.ForanenabledSPIconfiguredasaslave,havingMODFENlowonlyprevents the MODF flag from being set. It does not affect any other part of SPI operation. (See 13.7.2 Mode Fault Error.) SPR1 and SPR0 — SPI Baud Rate Select Bits Inmastermode,theseread/writebitsselectoneoffourbaudratesasshowninTable 13-4.SPR1and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. MC68HC908AP Family Data Sheet, Rev. 4 226 Freescale Semiconductor

I/O Registers Table 13-4. SPI Master Baud Rate Selection SPR1 and SPR0 Baud Rate Divisor (BD) 00 2 01 8 10 32 11 128 Use this formula to calculate the SPI baud rate: CGMOUT Baud rate = -------------------------- 2×BD where: CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor 13.13.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register.WritingtotheSPIdataregisterwritesdataintothetransmitdataregister.ReadingtheSPIdata register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values. (See Figure 13-2.) Address: $0012 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset Figure 13-15. SPI Data Register (SPDR) R7–R0/T7–T0 — Receive/Transmit Data Bits NOTE Donotuseread-modify-writeinstructionsontheSPIdataregistersincethe register read is not the same as the register written. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 227

Serial Peripheral Interface Module (SPI) MC68HC908AP Family Data Sheet, Rev. 4 228 Freescale Semiconductor

Chapter 14 Multi-Master IIC Interface (MMIIC) 14.1 Introduction The multi-master IIC (MMIIC) interface is a two wire, bidirectional serial bus which provides a simple, efficient way for data exchange between devices. The interface is designed for internal serial communication between the MCU and other IIC devices. It has hardware generated START and STOP signals; and byte by byte interrupt driven software algorithm. Thisbusissuitableforapplicationswhichneedfrequentcommunicationsoverashortdistancebetween anumberofdevices.Italsoprovidesaflexibilitythatallowsadditionaldevicestobeconnectedtothebus. Themaximumdatarateis100k-bps,andthemaximumcommunicationdistanceandnumberofdevices that can be connected is limited by a maximum bus capacitance of 400pF. This MMIIC interface is also SMBus (System Management Bus) version 1.0 and 1.1 compatible, with hardware cyclic redundancy code (CRC) generation, making it suitable for smart battery applications. 14.2 Features Features of the MMIC module include: • Full SMBus version 1.0/1.1 compliance • Multi-master IIC bus standard • Software programmable for one of eight different serial clock frequencies • Software controllable acknowledge bit generation • Interrupt driven byte by byte data transfer • Calling address identification interrupt • Arbitrationlossdetectionandno-ACKawarenessinmastermodeandautomaticmodeswitching from master to slave • Auto detection of R/W bit and switching of transmit or receive mode accordingly • Detection of START, repeated START, and STOP signals • Auto generation of START and STOP condition in master mode • Repeated start generation • Master clock generator with eight selectable baud rates • Automatic recognition of the received acknowledge bit • Busy detection • Software enabled 8-bit CRC generation/decoding MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 229

Multi-Master IIC Interface (MMIIC) 14.3 I/O Pins TheMMIICmoduleusestwoI/Opins,sharedwithstandardportI/Opins.ThefullnameoftheMMIICI/O pins are listed in Table 14-1. The generic pin name appear in the text that follows. The SDA and SDL pins are open-drain. When configured as general purpose output pins (PTB0 and PTB1), pullup resistors must be connected to these pins. Table 14-1. Pin Name Conventions MMIIC Generic Pin Names: Full MCU Pin Names: Pin Selected for MMIIC Function By: SDA PTB0/SDA MMEN bit in MMCR1 ($0049) SCL PTB1/SCL Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: MMIIC Address Register MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD $0048 Write: (MMADR) Reset: 1 0 1 0 0 0 0 0 Read: 0 0 0 MMIIC Control Register 1 MMEN MMIEN MMTXAK REPSEN MMCRCBYTE $0049 Write: MMCLRBB (MMCR1) Reset: 0 0 0 0 0 0 0 0 Read: MMALIF MMNAKIF MMBB 0 0 MMIIC Control Register 2 MMAST MMRW MMCRCEF $004A Write: 0 0 (MMCR2) Reset: 0 0 0 0 0 0 0 Unaffected Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK MMCRCBF MMTXBE MMRXBF MMIIC Status Register $004B Write: 0 0 (MMSR) Reset: 0 0 0 0 1 0 1 0 MMIIC Data Transmit Read: MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0 $004C Register Write: (MMDTR) Reset: 0 0 0 0 0 0 0 0 MMIIC Data Receive Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0 $004D Register Write: (MDDRR) Reset: 0 0 0 0 0 0 0 0 Read: MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0 MMIIC CRC Data Register $004E Write: (MMCRDR) Reset: 0 0 0 0 0 0 0 0 MMIIC Frequency Divider Read: 0 0 0 0 0 MMBR2 MMBR1 MMBR0 $004F Register Write: (MMFDR) Reset: 0 0 0 0 0 1 0 0 =Unimplemented Figure 14-1. MMIIC I/O Register Summary 14.4 Multi-Master IIC System Configuration Themulti-masterIICsystemusesaserialdatalineSDAandaserialclocklineSCLfordatatransfer.All devices connected to it must have open collector (drain) outputs and the logical-AND function is performed on both lines by two pull-up resistors. MC68HC908AP Family Data Sheet, Rev. 4 230 Freescale Semiconductor

Multi-Master IIC Bus Protocol 14.5 Multi-Master IIC Bus Protocol Normally a standard communication is composed of four parts: 1. START signal, 2. slave address transmission, 3. data transfer, and 4. STOP signal. These are described briefly in the following sections and illustrated in Figure 14-2. 9th clock pulse 9th clock pulse MSB LSB MSB LSB SCL 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 SDA ACK Data must be stable No ACK when SCL is HIGH START STOP signal signal MSB LSB MSB LSB SCL 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 SDA ACK No ACK START Repeated STOP signal START signal signal Figure 14-2. Multi-Master IIC Bus Transmission Signal Diagram 14.5.1 START Signal Whenthebusisfree,(i.e.nomasterdeviceisengagingthebus—bothSCLandSDAlinesareatlogic high) a master may initiate communication by sending a START signal. As shown in Figure 14-2, a START signal is defined as a high to low transition of SDA while SCL is high. This signal denotes the beginningofanewdatatransfer(eachdatatransfermaycontainseveralbytesofdata)andwakesupall slaves. 14.5.2 Slave Address Transmission The first byte transferred immediately after the START signal is the slave address transmitted by the master.Thisisa7-bitcallingaddressfollowedbyaR/W-bit.TheR/W-bitdictatestotheslavethedesired direction of the data transfer. A logic 0 indicates that the master wishes to transmit data to the slave; a logic 1 indicates that the master wishes to receive data from the slave. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 231

Multi-Master IIC Interface (MMIIC) OnlytheslavewithamatchedaddresswillrespondbysendingbackanacknowledgebitbypullingSDA low on the 9th clock cycle. (See Figure 14-2.) 14.5.3 Data Transfer Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in the direction specified by the R/W-bit sent by the calling master. Eachdatabyteis8bits.DatacanbechangedonlywhenSCLislowandmustbeheldstablewhenSCL is high as shown in Figure 14-2. The MSB is transmitted first and each byte has to be followed by an acknowledgebit.ThisissignalledbythereceivingdevicebypullingtheSDAlowonthe9thclockcycle. Therefore, one complete data byte transfer requires 9 clock cycles. Iftheslavereceiverdoesnotacknowledgethemaster,theSDAlineshouldbelefthighbytheslave.The mastercanthengenerateaSTOPsignaltoabortthedatatransferoraSTARTsignal(repeatedSTART) to commence a new transfer. If the master receiver does not acknowledge the slave transmitter after a byte has been transmitted, it meansan“endofdata”totheslave.TheslaveshouldreleasetheSDAlineforthemastertogeneratea STOP or START signal. 14.5.4 Repeated START Signal As shown in Figure 14-2, a repeated START signal is used to generate START signal without first generating a STOP to terminate the communication. This is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 14.5.5 STOP Signal ThemastercanterminatethecommunicationbygeneratingaSTOPsignaltofreethebus.However,the master may generate a START signal followed by a calling command without first generating a STOP signal. This is called repeat START. A STOP signal is defined as a low to high transition of SDA while SCL is at logic high (see Figure 14-2). 14.5.6 Arbitration Procedure Theinterfacecircuitisamulti-mastersystemwhichallowsmorethanonemastertobeconnected.Iftwo or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock. The clock low period is equal to the longest clock low period and the clock high period is equal to the shortest one among the masters. A data arbitration procedure determines the priority. A masterwilllosearbitrationifittransmitsalogic1whileanothertransmitsalogic 0.Thelosingmasterwill immediatelyswitchovertoslavereceivemodeandstopsitsdataandclockoutputs.Thetransitionfrom master to slave will not generate a STOP condition. Meanwhile a software bit will be set by hardware to indicates loss of arbitration. 14.5.7 Clock Synchronization Since wired-AND logic is performed on SCL line, a high to low transition on the SCL line will affect the devicesconnectedtothebus.Thedevicesstartcountingtheirlowperiodonceadevice’sclockhasgone low,itwillholdtheSCLlinelowuntiltheclockhighstateisreached.However,thechangeoflowtohigh MC68HC908AP Family Data Sheet, Rev. 4 232 Freescale Semiconductor

MMIIC I/O Registers inthisdeviceclockmaynotchangethestateoftheSCLlineifanotherdeviceclockisstillinitslowperiod. ThereforethesynchronizedclockSCLwillbeheldlowbythedevicewhichlastreleasesSCLtologichigh. Deviceswithshorterlowperiodsenterahighwaitstateduringthistime.Whenalldevicesconcernedhave countedofftheirlowperiod,thesynchronizedSCLlinewillbereleasedandgohigh,andalldeviceswill start counting their high periods. The first device to complete its high period will again pull the SCL line low. Figure 14-3 illustrates the clock synchronization waveforms. Start counting high period WAIT SCL1 SCL2 SCL Internal counter reset Figure 14-3. Clock Synchronization 14.5.8 Handshaking Theclocksynchronizationmechanismcanbeusedasahandshakeindatatransfer.Aslavedevicemay holdtheSCLlowaftercompletionofonebytedatatransferandwillhaltthebusclock,forcingthemaster clock into a wait state until the slave releases the SCL line. 14.5.9 Packet Error Code Thepacketerrorcode(PEC)fortheMMIICinterfaceisintheformacyclicredundancycode(CRC).The PEC is generated by hardware for every transmitted and received byte of data. The transmission of the generated PEC is controlled by user software. TheCRCdataregister,MMCRCDR,containsthegeneratedPECbyte,withthreeotherbitsintheMMIIC control registers and status register monitoring and controlling the PEC byte. 14.6 MMIIC I/O Registers These I/O registers control and monitor MMIIC operation: • MMIIC address register (MMADR) — $0048 • MMIIC control register 1 (MMCR1) — $0049 • MMIIC control register 2 (MMCR2) — $004A • MMIIC status register (MMSR) — $004B • MMIIC data transmit register (MMDTR) — $004C • MMIIC data receive register (MMDRR) — $004D • MMIIC CRC data register (MMCRCDR) — $004E • MMIIC frequency divide register (MMFDR) — $004F MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 233

Multi-Master IIC Interface (MMIIC) 14.6.1 MMIIC Address Register (MMADR) Address: $0048 Bit 7 6 5 4 3 2 1 Bit 0 Read: MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD Write: Reset: 1 0 1 0 0 0 0 0 Figure 14-4. MMIIC Address Register (MMADR) MMAD[7:1] — Multi-Master Address ThesesevenbitsrepresenttheMMIICinterface’sownspecificslaveaddresswheninslavemode,and the calling address when in master mode. Software must update MMAD[7:1] as the calling address whileenteringmastermodeandrestoreitsownslaveaddressaftermastermodeisrelinquished.This register is cleared as $A0 upon reset. MMEXTAD — Multi-Master Expanded Address This bit is set to expand the address of the MMIIC in slave mode. When set, the MMIIC will acknowledge the following addresses from a calling master: $MMAD[7:1], 0000000, and 0001100. Reset clears this bit. 1 = MMIIC responds to the following calling addresses: $MMAD[7:1], 0000000, and 0001100. 0 = MMIIC responds to address $MMAD[7:1] For example, when MMADR is configured as: MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD 1 1 0 1 0 1 0 1 The MMIIC module will respond to the calling address: Bit 7 6 5 4 3 2 Bit 1 1 1 0 1 0 1 0 or the general calling address: 0 0 0 0 0 0 0 or the calling address: Bit 7 6 5 4 3 2 Bit 1 0 0 0 1 1 0 0 Note that bit-0 of the 8-bit calling address is the MMRW bit from the calling master. MC68HC908AP Family Data Sheet, Rev. 4 234 Freescale Semiconductor

MMIIC I/O Registers 14.6.2 MMIIC Control Register 1 (MMCR1) Address: $0049 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 MMEN MMIEN MMTXAK REPSEN MMCRCBYTE Write: MMCLRBB Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 14-5. MMIIC Control Register 1 (MMCR1) MMEN — MMIIC Enable ThisbitissettoenabletheMulti-masterIICmodule.WhenMMEN = 0,moduleisdisabledandallflags will restore to its power-on default states. Reset clears this bit. 1 = MMIIC module enabled 0 = MMIIC module disabled MMIEN — MMIIC Interrupt Enable Whenthisbitisset,theMMTXIF,MMRXIF,MMALIF,andMMNAKIFflagsareenabledtogeneratean interruptrequesttotheCPU.WhenMMIENiscleared,thetheseflagsarepreventedfromgenerating an interrupt request. Reset clears this bit. 1 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will generate interrupt request to CPU 0=MMTXIF,MMRXIF,MMALIF,and/orMMNAKIFbitsetwillnotgenerateinterruptrequesttoCPU MMCLRBB — MMIIC Clear Busy Flag Writing a logic 1 to this write-only bit clears the MMBB flag. MMCLRBB always reads as a logic 0. Reset clears this bit. 1 = Clear MMBB flag 0 = No affect on MMBB flag MMTXAK — MMIIC Transmit Acknowledge Enable ThisbitissettodisabletheMMIICfromsendingoutanacknowledgesignaltothebusatthe9thclock bitafterreceiving8databits.WhenMMTXAKiscleared,anacknowledgesignalwillbesentatthe9th clock bit. Reset clears this bit. 1 = MMIIC does not send acknowledge signals at 9th clock bit 0 = MMIIC sends acknowledge signal at 9th clock bit REPSEN — Repeated Start Enable This bit is set to enable repeated START signal to be generated when in master mode transfer (MMAST = 1).TheREPSENbitisclearedbyhardwareafterthecompletionofrepeatedSTARTsignal or when the MMAST bit is cleared. Reset clears this bit. 1 = Repeated START signal will be generated if MMAST bit is set 0 = No repeated START signal will be generated MMCRCBYTE — MMIIC CRC Byte In receive mode, this bit is set by software to indicate that the next receiving byte will be the packet error checking (PEC) data. In master receive mode, after completion of CRC generation on the received PEC data, an acknowledge signal is sent if MMTXAK = 0; no acknowledge is sent If MMTXAK = 1. Inslavereceivemode,noacknowledgesignalissentifaCRCerrorisdetectedonthereceivedPEC data. If no CRC error is detected, an acknowledge signal is sent if MMTXAK = 0; no acknowledge is sent If MMTXAK = 1. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 235

Multi-Master IIC Interface (MMIIC) Undernormaloperation,theusersoftwareshouldclearMMTXAKbitbeforesettingMMCRCBYTEbit to ensure that an acknowledge signal is sent when no CRC error is detected. TheMMCRCBYTEbitshouldnotbesetintransmitmode.ThisbitisclearedbythenextSTARTsignal. Reset also clears this bit. 1 = Next receiving byte is the packet error checking (PEC) data 0 = Next receiving byte is not PEC data 14.6.3 MMIIC Control Register 2 (MMCR2) Address: $004A Bit 7 6 5 4 3 2 1 Bit 0 Read: MMALIF MMNAKIF MMBB 0 0 MMAST MMRW MMCRCEF Write: 0 0 Reset: 0 0 0 0 0 0 0 Unaffected =Unimplemented Figure 14-6. MMIIC Control Register 2 (MMCR2) MMALIF — Arbitration Loss Interrupt Flag ThisflagissetwhensoftwareattempttosetMMASTbuttheMMBBhasbeensetbydetectingthestart conditiononthelinesorwhentheMMIICistransmittinga"1"toSDAlinebutdetecteda"0"fromSDA line in master mode — an arbitration loss. This bit generates an interrupt request to the CPU if the MMIEN bit in MMCR1 is set. This bit is cleared by writing "0" to it or by reset. 1 = Lost arbitration in master mode 0 = No arbitration lost MMNAKIF — No AcKnowledge Interrupt Flag (Master Mode) Thisflagisonlysetinmastermode(MMAST = 1)whenthereisnoacknowledgebitdetectedafterone data byte or calling address is transferred. This flag also clears MMAST. MMNAKIF generates an interruptrequesttoCPUiftheMMIENbitinMMCR1isset.Thisbitisclearedbywriting"0"toitorby reset. 1 = No acknowledge bit detected 0 = Acknowledge bit detected MMBB — MMIIC Bus Busy Flag Thisflagissetafterastartconditionisdetected(busbusy),andisclearedwhenastopcondition(bus idle) is detected or the MMIIC is disabled. Reset clears this bit. 1 = Start condition detected 0 = Stop condition detected or MMIIC is disabled MMAST — MMIIC Master Control This bit is set to initiate a master mode transfer. In master mode, the module generates a start condition to the SDA and SCL lines, followed by sending the calling address stored in MMADR. When the MMAST bit is cleared by MMNAKIF set (no acknowledge) or by software, the module generates the stop condition to the lines after the current byte is transmitted. Ifanarbitrationlossoccurs(MMALIF=1),themodulerevertstoslavemodebyclearingMMAST,and releasing SDA and SCL lines immediately. This bit is cleared by writing "0" to it or by reset. 1 = Master mode operation 0 = Slave mode operation MC68HC908AP Family Data Sheet, Rev. 4 236 Freescale Semiconductor

MMIIC I/O Registers MMRW — MMIIC Master Read/Write Thisbitistransmittedoutasbit0ofthecallingaddresswhenthemodulesetstheMMASTbittoenter mastermode.TheMMRWbitdeterminesthetransferdirectionofthedatabytesthatfollows.Whenit is "1", the module is in master receive mode. When it is "0", the module is in master transmit mode. Reset clears this bit. 1 = Master mode receive 0 = Master mode transmit MMCRCEF — MMIIC CRC Error Flag This flag is set when a CRC error is detected, and cleared when no CRC error is detected. The MMCRCEF is only meaningful after receiving a PEC data. This flag is unaffected by reset. 1 = CRC error detected on PEC byte 0 = No CRC error detected on PEC byte 14.6.4 MMIIC Status Register (MMSR) Address: $004B Bit 7 6 5 4 3 2 1 Bit 0 Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK MMCRCBF MMTXBE MMRXBF Write: 0 0 Reset: 0 0 0 0 1 0 1 0 =Unimplemented Figure 14-7. MMIIC Status Register (MMSR) MMRXIF — MMIIC Receive Interrupt Flag Thisflagissetafterthedatareceiveregister(MMDRR)isloadedwithanewreceiveddata.Oncethe MMDRR is loaded with received data, no more received data can be loaded to the MMDRR register untiltheCPUreadsthedatafromtheMMDRRtoclearMMRXBFflag.MMRXIFgeneratesaninterrupt requesttoCPUiftheMMIENbitinMMCRisalsoset.Thisbitisclearedbywriting"0"toitorbyreset; or when the MMEN = 0. 1 = New data in data receive register (MMDRR) 0 = No data received MMTXIF — MMIIC Transmit Interrupt Flag This flag is set when data in the data transmit register (MMDTR) is downloaded to the output circuit, andthatnewdatacanbewrittentotheMMDTR.MMTXIFgeneratesaninterruptrequesttoCPUifthe MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or when the MMEN = 0. 1 = Data transfer completed 0 = Data transfer in progress MMATCH — MMIIC Address Match Flag Thisflagissetwhenthereceiveddatainthedatareceiveregister(MMDRR)isacallingaddresswhich matcheswiththeaddressoritsextendedaddresses(MMEXTAD = 1)specifiedintheaddressregister (MMADR). The MMATCH flag is set at the 9th clock of the calling address and will be cleared on the 9th clock of the next receiving data. Note: slave transmits do not clear MMATCH. 1 = Received address matches MMADR 0 = Received address does not match MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 237

Multi-Master IIC Interface (MMIIC) MMSRW — MMIIC Slave Read/Write Select This bit indicates the data direction when the module is in slave mode. It is updated after the calling addressisreceivedfromamasterdevice.MMSRW = 1whenthecallingmasterisreadingdatafrom themodule(slavetransmitmode).MMSRW = 0whenthemasteriswritingdatatothemodule(receive mode). 1 = Slave mode transmit 0 = Slave mode receive MMRXAK — MMIIC Receive Acknowledge Whenthisbitiscleared,itindicatesanacknowledgesignalhasbeenreceivedafterthecompletionof eightdatabitstransmissiononthebus.WhenMMRXAKisset,itindicatesnoacknowledgesignalhas beendetectedatthe9thclock;themodulewillreleasetheSDAlineforthemastertogenerateSTOP or repeated START condition. Reset sets this bit. 1 = No acknowledge signal received at 9th clock 0 = Acknowledge signal received at 9th clock MMCRCBF — CRC Data Buffer Full Flag This flag is set when the CRC data register (MMCRCDR) is loaded with a CRC byte for the current received or transmitted data. In transmit mode, after a byte of data has been sent (MMTXIF = 1), the MMCRCBF will be set when theCRCbytehasbeengeneratedandreadyintheMMCRCDR.ThecontentoftheMMCRCDRshould be copied to the MMDTR for transmission. In receive mode, the MMCRCBF is set when the CRC byte has been generated and ready in MMCRCDR, for the current byte of received data. The MMCRCBF bit is cleared when the CRC data register is read. Reset also clears this bit. 1 = Data ready in CRC data register (MMCRCDR) 0 = Data not ready in CRC data register (MMCRCDR) MMTXBE — MMIIC Transmit Buffer Empty Thisflagindicatesthestatusofthedatatransmitregister(MMDTR).WhentheCPUwritesthedatato theMMDTR,theMMTXBEflagwillbecleared.MMTXBEissetwhenMMDTRisemptiedbyatransfer of its data to the output circuit. Reset sets this bit. 1 = Data transmit register empty 0 = Data transmit register full MMRXBF — MMIIC Receive Buffer Full This flag indicates the status of the data receive register (MMDRR). When the CPU reads the data fromtheMMDRR,theMMRXBFflagwillbecleared.MMRXBFissetwhenMMDRRisfullbyatransfer of data from the input circuit to the MMDRR. Reset clears this bit. 1 = Data receive register full 0 = Data receive register empty 14.6.5 MMIIC Data Transmit Register (MMDTR) Address: $004C Bit 7 6 5 4 3 2 1 Bit 0 Read: MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 14-8. MMIIC Data Transmit Register (MMDTR) MC68HC908AP Family Data Sheet, Rev. 4 238 Freescale Semiconductor

MMIIC I/O Registers When the MMIIC module is enabled, MMEN = 1, data written into this register depends on whether module is in master or slave mode. In slave mode, the data in MMDTR will be transferred to the output circuit when: • themoduledetectsamatchedcallingaddress(MMATCH = 1),withthecallingmasterrequesting data (MMSRW = 1); or • the previous data in the output circuit has be transmitted and the receiving master returns an acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0). Ifthecallingmasterdoesnotreturnanacknowledgebit(MMRXAK = 1),themodulewillreleasetheSDA line for master to generate a STOP or repeated START condition. The data in the MMDTR will not be transferredtotheoutputcircuituntilthenextcallingfromamaster.Thetransmitbufferemptyflagremains cleared (MMTXBE = 0). In master mode, the data in MMDTR will be transferred to the output circuit when: • the module receives an acknowledge bit (MMRXAK = 0), after setting master transmit mode (MMRW = 0), and the calling address has been transmitted; or • the previous data in the output circuit has be transmitted and the receiving slave returns an acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0). If the slave does not return an acknowledge bit (MMRXAK = 1), the master will generate a STOP or repeated START condition. The data in the MMDTR will not be transferred to the output circuit. The transmit buffer empty flag remains cleared (MMTXBE = 0). The sequence of events for slave transmit and master transmit are illustrated in Figure 14-12. 14.6.6 MMIIC Data Receive Register (MMDRR) Address: $004D Bit 7 6 5 4 3 2 1 Bit 0 Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0 Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 14-9. MMIIC Data Receive Register (MMDRR) When the MMIIC module is enabled, MMEN = 1, data in this read-only register depends on whether module is in master or slave mode. In slave mode, the data in MMDRR is: • the calling address from the master when the address match flag is set (MMATCH = 1); or • the last data received when MMATCH = 0. In master mode, the data in the MMDRR is: • the last data received. WhentheMMDRRisreadbytheCPU,thereceivebufferfullflagiscleared(MMRXBF = 0),andthenext receiveddataisloadedtotheMMDRR.EachtimewhennewdataisloadedtotheMMDRR,theMMRXIF interrupt flag is set, indicating that new data is available in MMDRR. The sequence of events for slave receive and master receive are illustrated in Figure 14-12. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 239

Multi-Master IIC Interface (MMIIC) 14.6.7 MMIIC CRC Data Register (MMCRCDR) Address: $004E Bit 7 6 5 4 3 2 1 Bit 0 Read: MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0 Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 14-10. MMIIC CRC Data Register (MMCRCDR) WhentheMMIICmoduleisenabled,MMEN = 1,andtheCRCbufferfullflagisset(MMCRCBF = 1),data inthisread-onlyregistercontainsthegeneratedCRCbyteforthelastbyteofreceivedortransmitteddata. A CRC byte is generated for each received and transmitted data byte and loaded to the CRC data register. The MMCRCBF bit will be set to indicate the CRC byte is ready in the CRC data register. Reading the CRC data register clears the MMCRCBF bit. If the CRC data register is not read, the MMCRCBF bit will be cleared by hardware before the next CRC byte is loaded. 14.6.8 MMIIC Frequency Divider Register (MMFDR) Address: $004F Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 MMBR2 MMBR1 MMBR0 Write: Reset: 0 0 0 0 0 1 0 0 =Unimplemented Figure 14-11. MMIIC Frequency Divider Register (MMFDR) Thethreebitsinthefrequencydividerregister(MMFDR)selectsthedividertodividethebusclocktothe desired baud rate for the MMIIC data transfer. Table 14-2 shows the divider values for MMBR[2:0]. MC68HC908AP Family Data Sheet, Rev. 4 240 Freescale Semiconductor

Program Algorithm Table 14-2. MMIIC Baud Rate Selection MMIIC Baud Rates for Bus Clocks: MMBR2 MMBR1 MMBR0 Divider 8MHz 4MHz 2MHz 1MHz 0 0 0 20 400kHz 200kHz 100kHz 50kHz 0 0 1 40 200kHz 100kHz 50kHz 25kHz 0 1 0 80 100kHz 50kHz 25kHz 12.5kHz 0 1 1 160 50kHz 25kHz 12.5kHz 6.25kHz 1 0 0 320 25kHz 12.5kHz 6.25kHz 3.125kHz 1 0 1 640 12.5kHz 6.25kHz 3.125kHz 1.5625kHz 1 1 0 1280 6.25kHz 3.125kHz 1.5625kHz 0.78125kHz 1 1 1 2560 3.125kHz 1.5625kHz 0.78125kHz 0.3906kHz NOTE The frequency of the MMIIC baud rate is only guaranteed for 100kHz to 10kHz.Thedividerisavailablefortheflexibilityonbusfrequencyselection. 14.7 Program Algorithm WhentheMMIICmoduledetectsanarbitrationlossinmastermode,itreleasesbothSDAandSCLlines immediately.ButiftherearenofurtherSTOPconditionsdetected,themodulewillhangup.Therefore,it is recommended to have time-out software to recover from this condition. The software can start the time-outcounterbylookingattheMMBB(busbusy)flagandresetthecounteronthecompletionofone byte transmission. If a time-out has occurred, software can clear the MMEN bit (disable MMIIC module) to release the bus, and hence clear the MMBB flag. This is the only way to clear the MMBB flag by softwareifthemodulehangsupduetoanoSTOPconditionreceived.TheMMIICcanresumeoperation again by setting the MMEN bit. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 241

Multi-Master IIC Interface (MMIIC) 14.7.1 Data Sequence (a) Master Transmit Mode START Address 0 ACK TX Data1 ACK TX DataN ACK STOP MMTXBE=0 MMTXBE=1 MMTXBE=1 MMTXBE=1 MMNAKIF=1 MMRW=0 MMTXIF=1 MMTXIF=1 MMTXIF=1 MMAST=0 MMAST=1 Data2→ MMDTR Data3→ MMDTR DataN+2→ MMDTR MMTXBE=0 Data1→ MMDTR (b) Master Receive Mode START Address 1 ACK RX Data1 ACK RX DataN NAK STOP MMRXBF=0 Data1→ MMDRR DataN→ MMDRR MMNAKIF=1 MMRW=1 MMRXIF=1 MMRXIF=1 MMAST=0 MMAST=1 MMRXBF=1 MMRXBF=1 MMTXBE=0 (dummy data→ MMDTR) (c) Slave Transmit Mode START Address 1 ACK TX Data1 ACK TX DataN NAK STOP MMTXBE=1 MMRXIF=1 MMTXBE=1 MMTXBE=1 MMNAKIF=1 MMRXBF=0 MMRXBF=1 MMTXIF=1 MMTXIF=1 MMTXBE=0 MMATCH=1 Data2→ MMDTR DataN+2→ MMDTR MMSRW=1 Data1→ MMDTR (d) Slave Receive Mode START Address 0 ACK RX Data1 ACK RX DataN ACK STOP MMTXBE=0 MMRXIF=1 Data1→ MMDRR DataN→ MMDRR MMRXBF=0 MMRXBF=1 MMRXIF=1 MMRXIF=1 MMATCH=1 MMRXBF=1 MMRXBF=1 MMSRW=0 Shaded data packets indicate transmissions by the MCU Figure 14-12. Data Transfer Sequences for Master/Slave Transmit/Receive Modes MC68HC908AP Family Data Sheet, Rev. 4 242 Freescale Semiconductor

SMBus Protocols with PEC and without PEC 14.8 SMBus Protocols with PEC and without PEC FollowingisadescriptionofthevariousMMIICbusprotocolswithandwithoutapacketerrorcode(PEC). 14.8.1 Quick Command 1 7 1 1 1 START Slave Address RW ACK STOP Master to Slave Start Condition Stop Condition Slave to Master Command Bit Acknowledge Figure 14-13. Quick Command 14.8.2 Send Byte START Slave Address W ACK Command Code ACK STOP (a) Send Byte Protocol START Slave Address W ACK Command Code ACK PEC ACK STOP (b) Send Byte Protocol with PEC Figure 14-14. Send Byte 14.8.3 Receive Byte START Slave Address R ACK Data Byte NAK STOP (a) Receive Byte Protocol START Slave Address R ACK Data Byte ACK PEC NAK STOP (b) Receive Byte Protocol with PEC Figure 14-15. Receive Byte MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 243

Multi-Master IIC Interface (MMIIC) 14.8.4 Write Byte/Word START Slave Address W ACK Command Code ACK Data Byte ACK STOP (a) Write Byte Protocol START Slave Address W ACK Command Code ACK Data Byte ACK PEC ACK STOP (b) Write Byte Protocol with PEC START Slave Address W ACK Command Code ACK Data Byte Low ACK Data Byte High ACK STOP (c) Write Word Protocol START Slave Address W ACK Command Code ACK Data Byte Low ACK Data Byte High ACK PEC ACK STOP (d) Write Word Protocol with PEC Figure 14-16. Write Byte/Word 14.8.5 Read Byte/Word START Slave Address W ACK Command Code ACK START Slave Address R ACK Data Byte NAK STOP (a) Read Byte Protocol START Slave Address W ACK Command Code ACK START Slave Address R ACK Data Byte ACK PEC NAK STOP (b) Read Byte Protocol with PEC START Slave Address W ACK Command Code ACK START Slave Address R ACK Data Byte Low ACK Data Byte High NAK STOP (c) Read Word Protocol START Slave Address W ACK Command Code ACK START Slave Address R ACK Data Byte Low ACK Data Byte High ACK PEC NAK STOP (d) Read Word Protocol with PEC Figure 14-17. Read Byte/Word MC68HC908AP Family Data Sheet, Rev. 4 244 Freescale Semiconductor

SMBus Protocols with PEC and without PEC 14.8.6 Process Call START Slave Address W ACK Command Code ACK Data Byte Low ACK Data Byte High ACK START Slave Address R ACK Data Byte Low ACK Data Byte High NAK STOP (a) Process Call START Slave Address W ACK Command Code ACK Data Byte Low ACK Data Byte High ACK START Slave Address R ACK Data Byte Low ACK Data Byte High ACK STOP PEC NAK STOP (b) Process Call with PEC Figure 14-18. Process Call 14.8.7 Block Read/Write START Slave Address W ACK Command Code ACK Byte Count = N ACK Data Byte 1 ACK Data Byte 2 ACK Data Byte N ACK STOP (a) Block Read START Slave Address W ACK Command Code ACK Byte Count = N ACK Data Byte 1 ACK Data Byte 2 ACK Data Byte N ACK PEC ACK STOP (b) Block Read with PEC START Slave Address W ACK Command Code ACK START Slave Address R ACK Byte Count = N ACK DDaattaa BByyttee 11 ACK Data Byte 2 ACK Data Byte N NAK STOP (c) Block Write START Slave Address W ACK Command Code ACK START Slave Address R ACK Byte Count = N ACK Data Byte 1 ACK Data Byte 2 ACK Data Byte N ACK PEC NAK STOP (d) Block Write with PEC Figure 14-19. Block Read/Write MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 245

Multi-Master IIC Interface (MMIIC) 14.9 SMBus Protocol Implementation Shaded data packets indicate transmissions by the MCU MASTER MODE START Address 0 ACK Command ACK START Address 1 ACK RX Data1 ACK ACK RX DataN NAK STOP OPERATION: OPERATION: OPERATION: OPERATION: Prepare for repeated START Get ready to receive data Read received data Generate STOP FLAGS: FLAGS: FLAGS: FLAGS: MMTXIF set MMTXIF set MMRXIF set MMRXIF set MMRXAK clear MMRXAK clear ACTION: ACTION: ACTION: ACTION: Read Data1 from MMDRR Read DataN from MMDRR 1. Set MMRW Load dummy ($FF) to MMDTR 2. Set REPSEN 3. Clear MMTXAK 4. Load dummy ($FF) to MMDTR OPERATION: OPERATION: Read received data and prepare for STOP Prepare for Master mode FLAGS: ACTION: MMRXIF set 1. Load slave address to MMADR ACTION: 2. Clear MMRW 1. Set MMTXAK 3. Load command to MMDTR 2. Read Data(N-1) from MMDRR 4. Set MMAST 3. Clear MMAST SLAVE MODE START Address 0 ACK Command ACK START Address 1 ACK TX Data1 ACK ACK TX DataN NAK STOP OPERATION: OPERATION: OPERATION: OPERATION: Slave address match and Slave address match and Transmit data Last data sent check for data direction get ready to transmit data FLAGS: FLAGS: FLAGS: FLAGS: MMTXIF set MMTXIF set MMRXIF set MMRXIF set MMRXAK clear MMRXAK set MMATCH set MMATCH set MMSRW depends on 8th MMSRW depends on 8th ACTION: ACTION: bit of calling address byte bit of calling address byte Load Data3 to MMDTR Load dummy ($FF) to MMDTR ACTION: ACTION: 1. Check MMSRW Check MMSRW 2. Read Slave address OPERATION: OPERATION: OPERATION: Read and decode received command OPERATION: Last data is going to be sent Prepare for Slave mode FLAGS: Transmit data FLAGS: ACTION: MMRXIF set FLAGS: MMTXIF set 1. Load slave address to MMADR MMATCH clear MMTXIF set MMRXAK clear 2. Clear MMTXAK ACTION: ACTION: ACTION: 3. Clear MMAST Load Data1 to MMDTR Load Data2 to MMDTR Load dummy ($FF) to MMDTR Figure 14-20. SMBus Protocol Implementation MC68HC908AP Family Data Sheet, Rev. 4 246 Freescale Semiconductor

Chapter 15 Analog-to-Digital Converter (ADC) 15.1 Introduction This section describes the analog-to-digital converter (ADC). The ADC is a 8-channel 10-bit linear successive approximation ADC. 15.2 Features Features of the ADC module include: • Eight channels with multiplexed input • High impedance buffered input • Linear successive approximation with monotonicity • 10-bit resolution • Single or continuous conversion • Auto-scan conversion on four channels • Conversion complete flag or conversion complete interrupt • Selectable ADC clock • Conversion result justification – 8-bit truncated mode – Right justified mode – Left justified mode – Left justified sign mode Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 ADC Status and Control Read: COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 $0057 Register Write: (ADSCR) Reset: 0 0 0 1 1 1 1 1 ADC Clock Control Read: 0 0 ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 $0058 Register Write: R (ADICLK) Reset: 0 0 0 0 0 1 0 0 Read: ADx ADx ADx ADx ADx ADx ADx ADx ADC Data Register High 0 $0059 Write: R R R R R R R R (ADRH0) Reset: 0 0 0 0 0 0 0 0 Read: ADx ADx ADx ADx ADx ADx ADx ADx ADC Data Register Low 0 $005A Write: R R R R R R R R (ADRL0) Reset: 0 0 0 0 0 0 0 0 Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data Register Low 1 $005B Write: R R R R R R R R (ADRL1) Reset: 0 0 0 0 0 0 0 0 Figure 15-1. ADC I/O Register Summary MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 247

Analog-to-Digital Converter (ADC) Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data Register Low 2 $005C Write: R R R R R R R R (ADRL3) Reset: 0 0 0 0 0 0 0 0 Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data Register Low 3 $005D Write: R R R R R R R R (ADRL3) Reset: 0 0 0 0 0 0 0 0 ADC Auto-scan Control Read: 0 0 0 0 0 AUTO1 AUTO0 ASCAN $005E Register Write: (ADASCR) Reset: 0 0 0 0 0 0 0 0 =Unimplemented R =Reserved Figure 15-1. ADC I/O Register Summary 15.3 Functional Description TheADCprovideseightpinsforsamplingexternalsourcesatpinsPTA0/ADC0–PTA7/ADC7.Ananalog multiplexer allows the single ADC converter to select one of eight ADC channels as ADC voltage in (V ). V is converted by the successive approximation register-based analog-to-digital converter. ADIN ADIN When the conversion is completed, ADC places the result in the ADC data register, high and low byte (ADRH0 and ADRL0), and sets a flag or generates an interrupt. An additional three ADC data registers (ADRL1–ADRL3) are available to store the individual converted data for ADC channels ADC1–ADC3 when the auto-scan mode is enabled. Data from channel ADC0 is stored in ADRL0 in the auto-scan mode. Figure 15-2 shows the structure of the ADC module. 15.3.1 ADC Port I/O Pins PTA0–PTA7 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits,ADCH[4:0],definewhichADCchannel/portpinwillbeusedastheinputsignal.TheADCoverrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port data register or data direction register will not have any affect on the port pin that is selected by the ADC. Read of a portpinwhichisinusebytheADCwillreturnthepinconditionifthecorrespondingDDRbitisatlogic0. If the DDR bit is at logic 1, the value in the port data latch is read. 15.3.2 Voltage Conversion WhentheinputvoltagetotheADCequalsV ,theADCconvertsthesignalto$3FF(fullscale).Ifthe REFH inputvoltageequalsV ,theADCconvertsitto$000.InputvoltagesbetweenV andV area REFL REFH REFL straight-linelinearconversion.Allotherinputvoltageswillresultin$3FFifgreaterthanV and$000 REFH if less than V . REFL NOTE Input voltage should not exceed the analog supply voltages. MC68HC908AP Family Data Sheet, Rev. 4 248 Freescale Semiconductor

Functional Description INTERNAL DATA BUS READ DDRAx DISABLE WRITE DDRAx DDRAx RESET WRITE PTAx PTAx PTAx/ADCx READ PTAx ADC0–ADC7 (8CHANNELS) DISABLE ADC DATA REGISTERS ADRH0 ADRL0 ADRL1 ADRL2 VREFH ADRL3 VREFL ADC CONVERSION VOLTAGE IN INTERRUPT COMPLETE (VADIN) CHANNEL 10-BIT ADC LOGIC SELECT AIEN COCO ADCICLK MUX ASCAN CGMXCLK CLOCK GENERATOR BUS CLOCK ADCH[4:0] ADIV[2:0] ADICLK 2-BIT UP-COUNTER AUTO[1:0] Figure 15-2. ADC Block Diagram 15.3.3 Conversion Time Conversion starts after a write to the ADSCR. One conversion will take between 16 and 17 ADC clock cycles, therefore: 16 to17 ADCcycles Conversion time = ADC frequency Number ofbus cycles = conversion time× bus frequency MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 249

Analog-to-Digital Converter (ADC) The ADC conversion time is determined by the clock source chosen and the divide ratio selected. The clocksourceiseitherthebusclockorCGMXCLKandisselectablebytheADICLKbitlocatedintheADC clock register. The divide ratio is selected by the ADIV[2:0] bits. For example, if a 4MHz CGMXCLK is selected as the ADC input clock source, with a divide-by-four prescale, and the bus speed is set at 2MHz: 16 to17 ADCcycles Conversion time = = 16 to 17µs 4MHz÷ 4 Number of bus cycles = 16 µs× 2MHz = 32 to 34 cycles NOTE The ADC frequency must be between f minimum and f maximum ADIC ADIC to meet A/D specifications. (See 22.5 5V DC Electrical Characteristics.). SinceanADCcyclemaybecomprisedofseveralbuscycles(fourinthepreviousexample)andthestart ofaconversionisinitiatedbyabuscyclewritetotheADSCR,fromzerotofouradditionalbuscyclesmay occurbeforethestartoftheinitialADCcycle.ThisresultsinafractionalADCcycleandisrepresentedas the 17th cycle. 15.3.4 Continuous Conversion Inthecontinuousconversionmode,theADCcontinuouslyconvertstheselectedchannel,fillingtheADC dataregisterwithnewdataaftereachconversion.Datafromthepreviousconversionwillbeoverwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCObitissetaftereachconversionandcanbeclearedbywritingtotheADCstatusandcontrolregister or reading of the ADRL0 data register. 15.3.5 Auto-Scan Mode Inauto-scanmode,theADCinputchannelisselectedbythevalueofthe2-bitup-counter,insteadofthe channelselectbits,ADCH[4:0].ThevalueofthecounteralsodefinesthedataregisterADRLxtobeused tostoretheconversionresult.WhenASCANbitisset,awritetoADCstatusandcontrolregister(ADSCR) will reset the auto-scan up-counter and ADC conversion will start on the channel 0 up to the channel numberdefinedbytheintegervalueofAUTO[1:0].Afterachannelconversioniscompleted,dataisstored inADRLxandtheCOCO-bitwillbeset.Thecountervaluewillbeincrementedby1andanewconversion will start. This process will continue until the counter value reaches the value of AUTO[1:0]. When this happens,itindicatesthatthecurrentchannelisthelastchanneltobeconverted.Uponthecompletionon the last channel, the counter value will not be incremented and no further conversion will be performed. To start another auto-scan cycle, a write to ADSCR must be performed. NOTE Thesystem onlyprovides 8-bitdata storagein auto-scan code,usermust clear MODE[1:0] bits to select 8-bit truncation mode before entering auto-scan mode. It is recommended that user should disable the auto-scan function before switching channel and also before entering STOP mode. MC68HC908AP Family Data Sheet, Rev. 4 250 Freescale Semiconductor

Interrupts 15.3.6 Result Justification The conversion result may be formatted in four different ways. • Left justified • Right justified • Left justified sign data mode • 8-bit truncation All four of these modes are controlled using MODE0 and MODE1 bits located in the ADC clock control register (ADICLK). Left justification will place the eight most significant bits (MSB) in the corresponding ADC data register high(ADRH).Thismaybeusefuliftheresultistobetreatedasan8-bitresultwheretheleastsignificant two bits, located in the ADC data register low (ADRL) can be ignored. However, you must read ADRL after ADRH or else the interlocking will prevent all new conversions from being stored. RightjustificationwillplaceonlythetwoMSBsinthecorrespondingADCdataregisterhigh(ADRH)and theeightLSBbitsinADCdataregisterlow(ADRL).Thismodeofoperationtypicallyisusedwhena10-bit unsigned result is desired. Left justified sign data mode is similar to left justified mode with one exception. The MSB of the 10-bit result, AD9 located in ADRH is complemented. This mode of operation is useful when a result, represented as a signed magnitude from mid-scale, is needed. Finally,8-bittruncationmodewillplacetheeightMSBsinADCdataregisterlow(ADRL).ThetwoLSBs aredropped.Thismodeofoperationisusedwhencompatibilitywith8-bitADCdesignsarerequired.No interlocking between ADRH and ADRL is present. 15.3.7 Data Register Interlocking ReadingADRHinany10-bitmodelatchesthecontentsofADRLuntilADRLisread.UntilADRLisread allsubsequentADCresultswillbelost.ThisregisterinterlockingcanalsoberesetbyawritetotheADC status and control register, or ADC clock control register. A power-on reset or reset will also clear the interlocking. Note that an external conversion request will not reset the lock. 15.3.8 Monotonicity The conversion process is monotonic and has no missing codes. 15.4 Interrupts When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion or after an auto-scan conversion cycle. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled. The interrupt vector is defined in Table 2-1 . Vector Addresses. 15.5 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 251

Analog-to-Digital Converter (ADC) 15.5.1 Wait Mode TheADCcontinuesnormaloperationinwaitmode.AnyenabledCPUinterruptrequestfromtheADCcan bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits to logic 1’s before executing the WAIT instruction. 15.5.2 Stop Mode TheADCmoduleisinactiveaftertheexecutionofaSTOPinstruction.Anypendingconversionisaborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode. 15.6 I/O Signals The ADC module has eight channels shared with port A I/O pins. 15.6.1 ADC Voltage In (V ) ADIN V is the input voltage signal from one of the eight ADC channels to the ADC module. ADIN 15.6.2 ADC Analog Power Pin (V ) DDA TheADCanalogportionusesV asitspowerpin.ConnecttheV pintothesamevoltagepotential DDA DDA as V . External filtering may be necessary to ensure clean V for good results. DD DDA NOTE Route V carefully for maximum noise immunity and place bypass DDA capacitors as close as possible to the package. 15.6.3 ADC Analog Ground Pin (V ) SSA TheADCanalogportionusesV asitsgroundpin.ConnecttheV pintothesamevoltagepotential SSA SSA as V . SS 15.6.4 ADC Voltage Reference High Pin (V ) REFH V is the power supply for setting the reference voltage V . Connect the V pin to the same REFH REFH REFH voltagepotentialasV .TherewillbeafinitecurrentassociatedwithV (seeChapter22Electrical DDA REFH Specifications). NOTE Route V carefully for maximum noise immunity and place bypass REFH capacitors as close as possible to the package. 15.6.5 ADC Voltage Reference Low Pin (V ) REFL V isthelowerreferencesupplyfortheADC.ConnecttheV pintothesamevoltagepotentialas REFL REFL V . There will be a finite current associated with V (see Chapter 22 Electrical Specifications). SSA REFL MC68HC908AP Family Data Sheet, Rev. 4 252 Freescale Semiconductor

I/O Registers 15.7 I/O Registers These I/O registers control and monitor ADC operation: • ADC status and control register (ADSCR) — $0057 • ADC clock control register (ADICLK) — $0058 • ADC data register high:low 0 (ADRH0:ADRL0) — $0059:$005A • ADC data register low 1–3 (ADRL1–ADRL3) — $005B–$005D • ADC auto-scan control register (ADASCR) — $005E 15.7.1 ADC Status and Control Register Function of the ADC status and control register is described here. Address: $0057 Read: COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Write: Reset: 0 0 0 1 1 1 1 1 Figure 15-3. ADC Status and Control Register (ADSCR) COCO — Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the ADSCR is written, or whenever the ADC clock control register is written, or whenever the ADC data register low, ADRLx, is read. If the AIEN bit is logic 1, the COCO bit always read as logic 0. ADC interrupt will be generated at the end if an ADC conversion. Reset clears the COCO bit. 1 = Conversion completed (AIEN = 0) 0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN=1) AIEN — ADC Interrupt Enable Bit Whenthisbitisset,aninterruptisgeneratedattheendofanADCconversion.Theinterruptsignalis cleared when the data register, ADR0, is read or the ADSCR is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO — ADC Continuous Conversion Bit Whenset,theADCwillconvertsamplescontinuouslyandupdatetheADCdataregisterattheendof each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion This bit should not be set when auto-scan mode is enabled; i.e. when ASCAN=1. ADCH[4:0] — ADC Channel Select Bits ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels when not in auto-scan mode. The five channel select bits are detailed in Table 15-1. NOTE Careshouldbetakenwhenusingaportpinasbothananalogandadigital inputsimultaneouslytopreventswitchingnoisefromcorruptingtheanalog signal. Recovery from the disabled state requires one conversion cycle to stabilize. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 253

Analog-to-Digital Converter (ADC) Table 15-1. MUX Channel Select ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 ADC Channel Input Select 0 0 0 0 0 ADC0 PTA0 0 0 0 0 1 ADC1 PTA1 0 0 0 1 0 ADC2 PTA2 0 0 0 1 1 ADC3 PTA3 0 0 1 0 0 ADC4 PTA4 0 0 1 0 1 ADC5 PTA5 0 0 1 1 0 ADC6 PTA6 0 0 1 1 1 ADC7 PTA7 0 1 0 0 0 ADC8 ↓ ↓ ↓ ↓ ↓ ↓ Reserved 1 1 1 0 0 ADC28 1 1 1 0 1 ADC29 VREFH(see Note 2) 1 1 1 1 0 ADC30 VREFL(see Note 2) 1 1 1 1 1 ADC powered-off — NOTES: 1. If any unused channels are selected, the resulting ADC conversion will be unknown. 2.Thevoltagelevelssuppliedfrominternalreferencenodesasspecifiedinthetableareusedtoverifytheoperationof the ADC converter both in production test and for user applications. 15.7.2 ADC Clock Control Register The ADC clock control register (ADICLK) selects the clock frequency for the ADC. Address: $0058 Read: 0 0 ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 Write: R Reset: 0 0 0 0 0 1 0 0 =Unimplemented R =Reserved Figure 15-4. ADC Clock Control Register (ADICLK) ADIV[2:0] — ADC Clock Prescaler Bits ADIV2,ADIV1,andADIV0forma3-bitfieldwhichselectsthedivideratiousedbytheADCtogenerate the internal ADC clock. Table 15-2showstheavailableclockconfigurations.TheADCclockshouldbesettobetween500kHz and 1MHz. MC68HC908AP Family Data Sheet, Rev. 4 254 Freescale Semiconductor

I/O Registers Table 15-2. ADC Clock Divide Ratio ADIV2 ADIV1 ADIV0 ADC Clock Rate 0 0 0 ADC input clock÷ 1 0 0 1 ADC input clock÷ 2 0 1 0 ADC input clock÷ 4 0 1 1 ADC input clock÷ 8 1 X X ADC input clock÷ 16 X = don’t care ADICLK — ADC Input Clock Select Bit ADICLKselectseitherbusclockorCGMXCLKastheinputclocksourcetogeneratetheinternalADC clock. Reset selects CGMXCLK as the ADC clock source. If the external clock (CGMXCLK) is equal to or greater than 1MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at f , correct operation can be guaranteed. ADIC 1 = Internal bus clock 0 = External clock, CGMXCLK CGMXCLK or bus frequency f = ADIC ADIV[2:0] MODE1 and MODE0 — Modes of Result Justification MODE1 and MODE0 selects between four modes of operation. The manner in which the ADC conversionresultswillbeplacedintheADCdataregistersiscontrolledbythesemodesofoperation. Reset returns right-justified mode. Table 15-3. ADC Mode Select MODE1 MODE0 Justification Mode 0 0 8-bit truncated mode 0 1 Right justified mode 1 0 Left justified mode 1 1 Left justified sign data mode 15.7.3 ADC Data Register 0 (ADRH0 and ADRL0) The ADC data register 0 consist of a pair of 8-bit registers: high byte (ADRH0), and low byte (ADRL0). Thispairforma16-bitregistertostorethe10-bitADCresultfortheselectedADCresultjustificationmode. In8-bittruncatedmode,theADRL0holdstheeightmostsignificantbits(MSBs)ofthe10-bitresult.The ADRL0isupdatedeachtimeanADCconversioncompletes.In8-bittruncatedmode,ADRL0containsno interlocking with ADRH0. (See Figure 15-5 . ADRH0 and ADRL0 in 8-Bit Truncated Mode.) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 255

Analog-to-Digital Converter (ADC) Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 0 ADC Data Register High 0 $0059 Write: R R R R R R R R (ADRH0) Reset: 0 0 0 0 0 0 0 0 Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data Register Low 0 $005A Write: R R R R R R R R (ADRL0) Reset: 0 0 0 0 0 0 0 0 Figure 15-5. ADRH0 and ADRL0 in 8-Bit Truncated Mode In right justified mode the ADRH0 holds the two MSBs, and the ADRL0 holds the eight least significant bits (LSBs), of the 10-bit result. ADRH0 and ADRL0 are updated each time a single channel ADC conversion completes. Reading ADRH0 latches the contents of ADRL0. Until ADRL0 is read all subsequent ADC results will be lost. (See Figure 15-6 . ADRH0 and ADRL0 in Right Justified Mode.) Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 AD9 AD8 ADC Data Register High 0 $0059 Write: R R R R R R R R (ADRH0) Reset: 0 0 0 0 0 0 0 0 Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADC Data Register Low 0 $005A Write: R R R R R R R R (ADRL0) Reset: 0 0 0 0 0 0 0 0 Figure 15-6. ADRH0 and ADRL0 in Right Justified Mode In left justified mode the ADRH0 holds the eight most significant bits (MSBs), and the ADRL0 holds the two least significant bits (LSBs), of the 10-bit result. The ADRH0 and ADRL0 are updated each time a singlechannelADCconversioncompletes.ReadingADRH0latchesthecontentsofADRL0.UntilADRL0 is read all subsequent ADC results will be lost. (See Figure 15-7 . ADRH0 and ADRL0 in Left Justified Mode.) Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data Register High 0 $0059 Write: R R R R R R R R (ADRH0) Reset: 0 0 0 0 0 0 0 0 Read: AD1 AD0 0 0 0 0 0 0 ADC Data Register Low 0 $005A Write: R R R R R R R R (ADRL0) Reset: 0 0 0 0 0 0 0 0 Figure 15-7. ADRH0 and ADRL0 in Left Justified Mode InleftjustifiedsignmodetheADRH0holdstheeightMSBswiththeMSBcomplemented,andtheADRL0 holdsthetwoleastsignificantbits(LSBs),ofthe10-bitresult.TheADRH0andADRL0areupdatedeach timeasinglechannelADCconversioncompletes.ReadingADRH0latchesthecontentsofADRL0.Until ADRL0 is read all subsequent ADC results will be lost. (See Figure 15-8 ADRH0 and ADRL0 in Left Justified Sign Data Mode.) MC68HC908AP Family Data Sheet, Rev. 4 256 Freescale Semiconductor

I/O Registers Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADC Data Register High 0 $0059 Write: R R R R R R R R (ADRH0) Reset: 0 0 0 0 0 0 0 0 Read: AD1 AD0 0 0 0 0 0 0 ADC Data Register Low 0 $005A Write: R R R R R R R R (ADRL0) Reset: 0 0 0 0 0 0 0 0 Figure 15-8 ADRH0 and ADRL0 in Left Justified Sign Data Mode 15.7.4 ADC Auto-Scan Mode Data Registers (ADRL1–ADRL3) The ADC data registers 1 to 3 (ADRL1–ADRL3), are 8-bit registers for conversion results in 8-bit truncated mode, for channels ADC1 to ADC3, when the ADC is operating in auto-scan mode (MODE[1:0] = 00). Address: ADRL1, $005B; ADRL2, $005C; and ADRL3, $005D Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R =Reserved Figure 15-9. ADC Data Register Low 1 to 3 (ADRL1–ADRL3) 15.7.5 ADC Auto-Scan Control Register (ADASCR) The ADC auto-scan control register (ADASCR) enables and controls the ADC auto-scan function. Address: $005E Read: 0 0 0 0 0 AUTO1 AUTO0 ASCAN Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented R =Reserved Figure 15-10. ADC Scan Control Register (ADASCR) AUTO[1:0] — Auto-Scan Mode Channel Select Bits AUTO1andAUTO0forma2-bitfieldwhichisusedtodefinethenumberofauto-scanchannelsused when in auto-scan mode. Reset clears these bits. Table 15-4. Auto-scan Mode Channel Select AUTO1 AUTO0 Auto-Scan Channels 0 0 ADC0 only 0 1 ADC0 to ADC1 1 0 ADC0 to ADC2 1 1 ADC0 to ADC3 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 257

Analog-to-Digital Converter (ADC) ASCAN — Auto-scan Mode Enable Bit This bit enable/disable the auto-scan mode. Reset clears this bit. 1 = Auto-scan mode is enabled 0 = Auto-scan mode is disabled Auto-scan mode should not be enabled when ADC continuous conversion is enabled; i.e. when ADCO=1. MC68HC908AP Family Data Sheet, Rev. 4 258 Freescale Semiconductor

Chapter 16 Input/Output (I/O) Ports 16.1 Introduction Thirty-two(32)bidirectionalinput-output(I/O)pinsformfourparallelports.AllI/Opinsareprogrammable as inputs or outputs. NOTE ConnectanyunusedI/Opinstoanappropriatelogiclevel,eitherV orV . DD SS Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: Port A Data Register PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 $0000 Write: (PTA) Reset: Unaffected byreset Read: Port B Data Register PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 $0001 Write: (PTB) Reset: Unaffected byreset Read: PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 $0002 Port C Data Register (PTC) Write: Reset: Unaffected byreset Read: PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 $0003 Port D Data Register (PTD) Write: Reset: Unaffected by reset Read: Data Direction Register A DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 $0004 Write: (DDRA) Reset: 0 0 0 0 0 0 0 0 Read: Data Direction Register B DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 $0005 Write: (DDRB) Reset: 0 0 0 0 0 0 0 0 Read: Data Direction Register C DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 $0006 Write: (DDRC) Reset: 0 0 0 0 0 0 0 0 Read: Data Direction Register D DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 $0007 Write: (DDRD) Reset: 0 0 0 0 0 0 0 0 Port-A LED Control Read: LEDA7 LEDA6 LEDA5 LEDA4 LEDA3 LEDA2 LEDA1 LEDA0 $000C Register Write: (LEDA) Reset: 0 0 0 0 0 0 0 0 Figure 16-1. I/O Port Register Summary MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 259

Input/Output (I/O) Ports Table 16-1. Port Control Register Bits Summary Module Control Port Bit DDR Pin Module Register Control Bit 0 DDRA0 PTA0/ADC0 1 DDRA1 PTA1/ADC1 2 DDRA2 PTA2/ADC2 3 DDRA3 PTA3/ADC3 A ADC ADSCR ($0057) ADCH[4:0] 4 DDRA4 PTA4/ADC4 5 DDRA5 PTA5/ADC5 6 DDRA6 PTA6/ADC6 7 DDRA7 PTA7/ADC7 0 DDRB0 PTB0/SDA(1) MBUS MMCR1 ($0049) MMEN 1 DDRB1 PTB1/SCL(1) 2 DDRB2 PTB2/TxD(1) SCI SCC1 ($0013) ENSCI 3 DDRB3 PTB3/RxD(1) B 4 DDRB4 T1SC0 ($0025) ELS0B:ELS0A PTB4/T1CH0(2) TIM1 5 DDRB5 T1SC1 ($0028) ELS1B:ELS1A PTB5/T1CH1(2) 6 DDRB6 T2SC0 ($0030) ELS0B:ELS0A PTB6/T2CH0(2) TIM2 7 DDRB7 T2SC1 ($0033) ELS1B:ELS1A PTB7/T2CH1(2) 0 DDRC0 IRQ2 INTSCR2 ($001C) IMASK2 PTC0/IRQ2(2) 1 DDRC1 — — — PTC1 2 DDRC2 PTC2/MISO 3 DDRC3 PTC3/MOSI C SPI SPCR ($0010) SPE 4 DDRC4 PTC4/SS 5 DDRC5 PTC5/SPSCK 6 DDRC6 PTC6/SCTxD(1) IRSCI IRSCC1 ($0040) ENSCI 7 DDRC7 PTC7/SCRxD(1) 0 DDRD0 KBIE0 PTD0/KBI0(2) 1 DDRD1 KBIE1 PTD1/KBI1(2) 2 DDRD2 KBIE2 PTD2/KBI2(2) 3 DDRD3 KBIE3 PTD3/KBI3(2) D KBI KBIER ($001B) 4 DDRD4 KBIE4 PTD4/KBI4(2) 5 DDRD5 KBIE5 PTD5/KBI5(2) 6 DDRD6 KBIE6 PTD6/KBI6(2) 7 DDRD7 KBIE7 PTD7/KBI7(2) 1. Pin is open-drain when configured as output. Pullup resistor must be connected when configured as output. 2. Pin has schmitt trigger when configured as input. MC68HC908AP Family Data Sheet, Rev. 4 260 Freescale Semiconductor

Port A 16.2 Port A PortAisan8-bitspecial-functionportthatsharesallofitspinswiththeanalog-to-digitalconverter(ADC) module. Port A pins also have LED direct drive capability. 16.2.1 Port A Data Register (PTA) The port A data register contains a data latch for each of the eight port A pins. Address: $0000 Bit 7 6 5 4 3 2 1 Bit 0 Read: PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Write: Reset: Unaffected by reset Alternative Function: ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Additional Function: LED drive LED drive LED drive LED drive LED drive LED drive LED drive LED drive Figure 16-2. Port A Data Register (PTA) PTA[7:0] — Port A Data Bits Theseread/writebitsaresoftware-programmable.DatadirectionofeachportApinisunderthecontrol of the corresponding bit in data direction register A. Reset has no effect on port A data. ADC7–ADC0 — ADC Channels 7 to 0 ADC7–ADC0 are pins used for the input channels to the analog-to-digital converter module. The channelselectbits,ADCH[4:0],intheADCstatusandcontrolregisterdefinewhichportpinwillbeused as an ADC input and overrides any control from the port I/O logic. NOTE CaremustbetakenwhenreadingportAwhileapplyinganalogvoltagesto ADC7–ADC0 pins. If the appropriate ADC channel is not enabled, excessive current drain may occur if analog voltages are applied to the PTAx/ADCx pin, while PTA is read as a digital input. Those ports not selected as analog input channels are considered digital I/O ports. LED drive — Direct LED drive pins PTA7–PTA0 pins can be configured for direct LED drive. See 16.2.3 Port-A LED Control Register (LEDA). 16.2.2 Data Direction Register (DDRA) DatadirectionregisterAdetermineswhethereachportApinisaninputoranoutput.Writingalogic1to aDDRAbitenablestheoutputbufferforthecorrespondingportApin;alogic0disablestheoutputbuffer. Address: $0004 Bit 7 6 5 4 3 2 1 Bit 0 Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 16-3. Data Direction Register A (DDRA) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 261

Input/Output (I/O) Ports DDRA[7:0] — Data Direction Register A Bits Theseread/writebitscontrolportAdatadirection.ResetclearsDDRA[7:0],configuringallportApins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 16-4 shows the port A I/O logic. READ DDRA ($0004) WRITE DDRA ($0004) S DDRAx U RESET B A T A D WRITE PTA ($0000) AL PTAx PTAx N R E T N I READ PTA ($0000) Figure 16-4. Port A I/O Circuit WhenDDRAxisalogic1,readingaddress$0000readsthePTAxdatalatch.WhenDDRAxisalogic0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 16-2 summarizes the operation of the port A pins. Table 16-2. Port A Pin Functions Accesses to DDRA Accesses to PTA DDRA PTA Bit I/O Pin Mode Bit Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRA[7:0] Pin PTA[7:0](3) 1 X Output DDRA[7:0] PTA[7:0] PTA[7:0] 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. MC68HC908AP Family Data Sheet, Rev. 4 262 Freescale Semiconductor

Port B 16.2.3 Port-A LED Control Register (LEDA) Theport-ALEDcontrolregister(LEDA)controlsthedirectLEDdrivecapabilityonPTA7–PTA0pins.Each bitisindividuallyconfigurableandrequiresthatthedatadirectionregister,DDRA,bitbeconfiguredasan output. Address: $000C Bit 7 6 5 4 3 2 1 Bit 0 Read: LEDA7 LEDA6 LEDA5 LEDA4 LEDA3 LEDA2 LEDA1 LEDA0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 16-5. Port A LED Control Register (LEDA) LEDA[7:0] — Port A LED Drive Enable Bits Theseread/writebitsaresoftwareprogrammabletoenablethedirectLEDdriveonanoutputportpin. 1 = Corresponding port A pin is configured for direct LED drive, with 15mA current sinking capability 0 = Corresponding port A pin is configured for standard drive 16.3 Port B PortBisan8-bitspecial-functionportthatsharestwoofitspinswiththemulti-masterIIC(MMIIC)module, two of its pins with SCI module, and four of its pins with two timer interface (TIM1 and TIM2) modules. NOTE PTB3–PTB0 are open-drain pins when configured as outputs regardless whetherthepinsareusedasgeneralpurposeI/Opins,MMIICpins,orSCI pins. Therefore, when configured as general purpose output pins, MMIIC pins,orSCIpins(theTxDpin),pullupresistorsmustbeconnectedtothese pins. 16.3.1 Port B Data Register (PTB) The port B data register contains a data latch for each of the eight port B pins. Address: $0001 Bit 7 6 5 4 3 2 1 Bit 0 Read: PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 Write: Reset: Unaffected by reset Alternative Function: T2CH1 T2CH0 T1CH1 T1CH0 RxD TxD SCL SDA Figure 16-6. Port B Data Register (PTB) PTB[7:0] — Port B Data Bits Theseread/writebitsaresoftware-programmable.DatadirectionofeachportBpinisunderthecontrol of the corresponding bit in data direction register B. Reset has no effect on port B data. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 263

Input/Output (I/O) Ports SDA and SCL — Multi-Master IIC Data and Clock The SDA and SCL pins are multi-master IIC data and clock pins. Setting the MMEN bit in the MMIIC control register 1 (MMCR1) configures the PTB0/SDA and PTB1/SCL pins for MMIIC function and overrides any control from the port I/O logic. TxD and RxD — SCI Transmit and Receive Data TheTxDandRxDpinsareSCItransmitandreceivedatapins.SettingtheENSCIbitintheSCIcontrol register 1 (SCC1) configures the PTB2/TxD and PTB3/RxD pins for SCI function and overrides any control from the port I/O logic. T1CH0 and T1CH1 — Timer 1 Channel I/O The T1CH0 and T1CH1 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTB4/T1CH0–PTB5/T1CH1 pins are timer channel I/O pins or general-purpose I/O pins. T2CH0 and T2CH1 — Timer 2 Channel I/O The T2CH0 and T2CH1 pins are the TIM2 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTB6/T2CH0–PTB7/T2CH1 pins are timer channel I/O pins or general-purpose I/O pins. 16.3.2 Data Direction Register B (DDRB) DatadirectionregisterBdetermineswhethereachportBpinisaninputoranoutput.Writingalogic1to aDDRBbitenablestheoutputbufferforthecorrespondingportBpin;alogic0disablestheoutputbuffer. Address: $0005 Bit 7 6 5 4 3 2 1 Bit 0 Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 16-7. Data Direction Register B (DDRB) DDRB[7:0] — Data Direction Register B Bits Theseread/writebitscontrolportBdatadirection.ResetclearsDDRB[7:0],configuringallportBpins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 16-8 shows the port B I/O logic. MC68HC908AP Family Data Sheet, Rev. 4 264 Freescale Semiconductor

Port C READ DDRB ($0005) WRITE DDRB ($0005) S DDRBx U RESET B A T A D WRITE PTB ($0001) AL PTBx PTBx# N R E T N I READ PTB ($0001) # PTB3–PTB0 are open-drain pins when configured as outputs. PTB7–PTB4 have schmitt trigger inputs. Figure 16-8. Port B I/O Circuit WhenDDRBxisalogic1,readingaddress$0001readsthePTBxdatalatch.WhenDDRBxisalogic0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 16-3 summarizes the operation of the port B pins. Table 16-3. Port B Pin Functions Accesses to DDRB Accesses to PTB DDRB PTB Bit I/O Pin Mode Bit Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRB[7:0] Pin PTB[7:0](3) 1 X Output DDRB[7:0] PTB[7:0] PTB[7:0] 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. 16.4 Port C Port C is an 8-bit special-function port that shares one of its pins with the IRQ2, four of its pins with the SPI module, and two of its pins with the IRSCI module. 16.4.1 Port C Data Register (PTC) The port C data register contains a data latch for each of the eight port C pins. Address: $0002 Bit 7 6 5 4 3 2 1 Bit 0 Read: PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 Write: Reset: Unaffected by reset Alternative Function: SCRxD SCTxD SPSCK SS MOSI MISO IRQ2 Figure 16-9. Port C Data Register (PTC) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 265

Input/Output (I/O) Ports PTC[7:0] — Port C Data Bits Theseread/writebitsaresoftware-programmable.DatadirectionofeachportCpinisunderthecontrol of the corresponding bit in data direction register C. Reset has no effect on port C data. IRQ2 — IRQ2 input pin The PTC0/IRQ2 pin is always available as input pin to the IRQ2 module. Care must be taken to available unwanted interrupts when this pin is used as general purpose I/O. PTC0/IRQ2 pin has an internalpullup,andcanbedisabledbysettingthePUC0ENBbitintheIRQ2statusandcontrolregister (INTSCR2). MISO, MOSI, SS, and SPSCK — SPI Data I/O, Select, and Clock Pins ThesepinsaretheSPIdatain/out,select,andclockpins.SettingtheSPEbitintheSPIcontrolregister (SPCR)configuresPTC2/MISO,PTC3/MOSI,PTC4/SS,andPTC5/SPSCKpinsforSPIfunctionand overrides any control from the port I/O logic. SCTxD and SCRxD — IrSCI Transmit and Receive Data The SCTxD and SCRxD pins are IRSCI transmit and receive data pins. Setting the ENSCI bit in the IRSCI control register 1 (IRSCC1) configures the PTC6/SCTxD and PTC7/SCRxD pins for IRSCI function and overrides any control from the port I/O logic. 16.4.2 Data Direction Register C (DDRC) DatadirectionregisterCdetermineswhethereachportCpinisaninputoranoutput.Writingalogic1to aDDRCbitenablestheoutputbufferforthecorrespondingportCpin;alogic0disablestheoutputbuffer. Address: $0006 Bit 7 6 5 4 3 2 1 Bit 0 Read: DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 16-10. Data Direction Register C (DDRC) DDRC[7:0] — Data Direction Register C Bits Theseread/writebitscontrolportCdatadirection.ResetclearsDDRC[7:0],configuringallportCpins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input NOTE Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 16-11 shows the port C I/O logic. NOTE Forthosedevicespackagedina42-pinshrinkdualin-linepackage,PTC0 andPTC1arenotconnected.DDRC0andDDRC1shouldbesettoa1to configure PTC0 and PTC1 as outputs. MC68HC908AP Family Data Sheet, Rev. 4 266 Freescale Semiconductor

Port D READ DDRC ($0006) WRITE DDRC ($0006) S DDRCx U RESET B A T A D WRITE PTC ($0002) AL PTCx PTCx# N R E T N I READ PTC ($0002) # PTC0 has schmitt trigger input. Figure 16-11. Port C I/O Circuit WhenDDRCxisalogic1,readingaddress$0002readsthePTCxdatalatch.WhenDDRCxisalogic0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 16-4 summarizes the operation of the port C pins. Table 16-4. Port C Pin Functions Accesses to DDRC Accesses to PTC DDRC PTC Bit I/O Pin Mode Bit Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRC[7:0] Pin PTC[7:0](3) 1 X Output DDRC[7:0] PTC[7:0] PTC[7:0] 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. 16.5 Port D Port D is an 8-bit special function port that shares all of its pins with the keyboard interrupt module. 16.5.1 Port D Data Register (PTD) The port D data register contains a data latch for each of the eight port D pins. Address: $0003 Bit 7 6 5 4 3 2 1 Bit 0 Read: PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Write: Reset: Unaffected by reset Alternative Function: KBI7 KBI6 KBI5 KBI4 KBI3 KBI2 KBI1 KBI0 Figure 16-12. Port D Data Register (PTD) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 267

Input/Output (I/O) Ports PTD[7:0] — Port D Data Bits Theseread/writebitsaresoftwareprogrammable.DatadirectionofeachportDpinisunderthecontrol of the corresponding bit in data direction register D. Reset has no effect on port D data. KBI7–KBI0 — Keyboard Interrupt Inputs The keyboard interrupt enable bits, KBIE[7:0], in the keyboard interrupt enable register (KBIER), enable the port D pins as external interrupt pins. See Chapter 18 Keyboard Interrupt Module (KBI). 16.5.2 Data Direction Register D (DDRD) DatadirectionregisterDdetermineswhethereachportDpinisaninputoranoutput.Writingalogic1to aDDRDbitenablestheoutputbufferforthecorrespondingportDpin;alogic0disablestheoutputbuffer. Address: $0007 Bit 7 6 5 4 3 2 1 Bit 0 Read: DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 16-13. Data Direction Register D (DDRD) DDRD[7:0] — Data Direction Register D Bits Theseread/writebitscontrolportDdatadirection.ResetclearsDDRD[7:0],configuringallportDpins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 16-14 shows the port D I/O logic. READ DDRD ($0007) KBIEx WRITE DDRD ($0007) S DDRDx U RESET B A T A D WRITE PTD ($0003) AL PTDx PTDx# N R E T N I READ PTD ($0003) # PTD7–PTD0 have schmitt trigger inputs. Figure 16-14. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, readingaddress $0003 reads the voltage level on the pin.The data latchcan always bewritten, regardless of the state of its data direction bit. MC68HC908AP Family Data Sheet, Rev. 4 268 Freescale Semiconductor

Port D Table 16-5 summarizes the operation of the port D pins. Table 16-5. Port D Pin Functions Accesses to DDRD Accesses to PTD DDRD PTD Bit I/O Pin Mode Bit Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRD[7:0] Pin PTD[7:0](3) 1 X Output DDRD[7:0] PTD[7:0] PTD[7:0] 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 269

Input/Output (I/O) Ports MC68HC908AP Family Data Sheet, Rev. 4 270 Freescale Semiconductor

Chapter 17 External Interrupt (IRQ) 17.1 Introduction The external interrupt (IRQ) module provides two maskable interrupt inputs: IRQ1 and IRQ2. 17.2 Features Features of the IRQ module include: • A dedicated external interrupt pin, IRQ1 • An external interrupt pin shared with a port pin, PTC0/IRQ2 • Separate IRQ interrupt control bits for IRQ1 and IRQ2 • Hysteresis buffers • Programmable edge-only or edge and level interrupt sensitivity • Automatic interrupt acknowledge • Internal pullup resistor, with disable option on IRQ2 NOTE References to either IRQ1 or IRQ2 may be made in the following text by omitting the IRQ number. For example, IRQF may refer generically to IRQ1F and IRQ2F, and IMASK may refer to IMASK1 and IMASK2. Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 IRQ2 Status and Control Read: 0 0 0 IRQ2F 0 PUC0ENB IMASK2 MODE2 $001C Register Write: ACK2 (INTSCR2) Reset: 0 0 0 0 0 0 0 0 IRQ1 Status and Control Read: 0 0 0 0 IRQ1F 0 IMASK1 MODE1 $001E Register Write: ACK1 (INTSCR1) Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 17-1. External Interrupt I/O Register Summary 17.3 Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 17-2 and Figure 17-3 shows the structure of the IRQ module. InterruptsignalsontheIRQpinarelatchedintotheIRQlatch.Aninterruptlatchremainssetuntiloneof the following actions occurs: • Vectorfetch—Avectorfetchautomaticallygeneratesaninterruptacknowledgesignalthatclears the latch that caused the vector fetch. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 271

External Interrupt (IRQ) • Softwareclear—Softwarecanclearaninterruptlatchbywritingtotheappropriateacknowledge bitintheinterruptstatusandcontrolregister(INTSCR).Writingalogic1totheACKbitclearsthe IRQ latch. • Reset — A reset automatically clears the interrupt latch. The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge orfalling-edgeandlow-level-triggered.TheMODEbitintheINTSCRcontrolsthetriggeringsensitivityof the IRQ pin. Whenaninterruptpinisedge-triggeredonly,theinterruptremainssetuntilavectorfetch,softwareclear, or reset occurs. When an interrupt pin is both falling-edge and low-level-triggered, the interrupt remains set until both of the following occur: • Vector fetch or software clear • Return of the interrupt pin to logic 1 Thevectorfetchorsoftwareclearmayoccurbeforeoraftertheinterruptpinreturnstologic1.Aslongas the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low. Whenset,theIMASKbitintheINTSCRmaskallexternalinterruptrequests.Alatchedinterruptrequest is not presented to the interrupt priority logic unless the IMASK bit is clear. NOTE The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. RESET ACK1 TO CPU FOR VECTOR US FETCH BINILS/TBRIHUCTIONS B DECODER S S RE VDD D D L A INTERNAL VDD IRQ1F A PULLUP N INTER DEVICE D CLR Q SYNCHRONIZER IIRNQTE1RRUPT IRQ1 CK REQUEST IMASK1 MODE1 HIGH TO MODE VOLTAGE SELECT DETECT LOGIC Figure 17-2. IRQ1 Block Diagram MC68HC908AP Family Data Sheet, Rev. 4 272 Freescale Semiconductor

IRQ1 and IRQ2 Pins RESET ACK2 VECTOR US FETCH B DECODER S S V E DD R D D A L INTERNAL NA PULLUP R DEVICE NTE VDD IRQ2F I PUC0ENB CLR D Q SYNCHRONIZER IRQ2 INTERRUPT IRQ2 CK REQUEST IMASK2 MODE2 Figure 17-3. IRQ2 Block Diagram 17.4 IRQ1 and IRQ2 Pins A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. IftheMODEbitisset,theIRQpinisbothfalling-edge-sensitiveandlow-level-sensitive.WithMODEset, both of the following actions must occur to clear IRQ: • Vectorfetchorsoftwareclear—Avectorfetchgeneratesaninterruptacknowledgesignaltoclear thelatch.Softwaremaygeneratetheinterruptacknowledgesignalbywritingalogic1totheACK bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that polltheIRQpinandrequiresoftwaretocleartheIRQlatch.WritingtotheACKbitpriortoleaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does notaffectsubsequenttransitionsontheIRQpin.AfallingedgethatoccursafterwritingtotheACK bit another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at location defined in Table 2-1 . Vector Addresses. • Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, IRQ remains active. The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any order. The interruptrequestremainspendingaslongastheIRQpinisatlogic0.Aresetwillclearthelatchandthe MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ1 pin. NOTE The BIH and BIL instructions do not read the logic level on the IRQ2 pin. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 273

External Interrupt (IRQ) NOTE When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. The IRQ1 pin has a permanent internal pullup device connected, while the IRQ2 pin has an optional pullup device that can be enabled or disabled by the PUC0ENB bit in the INTSCR2 register. 17.5 IRQ Module During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during the break state. (See Chapter 21 Break Module (BRK).) ToallowsoftwaretocleartheIRQlatchduringabreakinterrupt,writealogic1totheBCFEbit.Ifalatch is cleared during the break state, it remains cleared when the MCU exits the break state. ToprotectCPUinterruptflagsduringthebreakstate,writealogic0totheBCFEbit.WithBCFEatlogic 0(itsdefaultstate),writingtotheACKbitintheIRQstatusandcontrolregisterduringthebreakstatehas no effect on the IRQ interrupt flags. 17.6 IRQ Registers Each IRQ is controlled and monitored by an status and control register. • IRQ1 Status and Control Register — $001E • IRQ2 Status and Control Register — $001C 17.6.1 IRQ1 Status and Control Register TheIRQ1statusandcontrolregister(INTSCR1)controlsandmonitorsoperationofIRQ1.TheINTSCR1 has the following functions: • Shows the state of the IRQ1 flag • Clears the IRQ1 latch • Masks IRQ1 interrupt request • Controls triggering sensitivity of the IRQ1 interrupt pin Address: $001E Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 IRQ1F 0 IMASK1 MODE1 Write: ACK1 Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 17-4. IRQ1 Status and Control Register (INTSCR1) IRQ1F — IRQ1 Flag Bit This read-only status bit is high when the IRQ1 interrupt is pending. 1 = IRQ1 interrupt pending 0 = IRQ1 interrupt not pending ACK1 — IRQ1 Interrupt Request Acknowledge Bit Writingalogic1tothiswrite-onlybitclearstheIRQ1latch.ACK1alwaysreadsaslogic0.Resetclears ACK1. MC68HC908AP Family Data Sheet, Rev. 4 274 Freescale Semiconductor

IRQ Registers IMASK1 — IRQ1 Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1. 1 = IRQ1 interrupt requests disabled 0 = IRQ1 interrupt requests enabled MODE1 — IRQ1 Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE1. 1 = IRQ1 interrupt requests on falling edges and low levels 0 = IRQ1 interrupt requests on falling edges only 17.6.2 IRQ2 Status and Control Register TheIRQ2statusandcontrolregister(INTSCR2)controlsandmonitorsoperationofIRQ2.TheINTSCR2 has the following functions: • Enables/disables the internal pullup device on IRQ2 pin • Shows the state of the IRQ2 flag • Clears the IRQ2 latch • Masks IRQ2 interrupt request • Controls triggering sensitivity of the IRQ2 interrupt pin Address: $001C Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 IRQ2F 0 PUC0ENB IMASK2 MODE2 Write: ACK2 Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 17-5. IRQ2 Status and Control Register (INTSCR2) PUC0ENB — IRQ2 Pin Pullup Enable Bit. Setting this bit to logic 1 disables the pullup on PTC0/IRQ2 pin. Reset clears this bit. 1 = IRQ2 pin internal pullup is disabled 0 = IRQ2 pin internal pullup is enabled IRQ2F — IRQ2 Flag Bit This read-only status bit is high when the IRQ2 interrupt is pending. 1 = IRQ2 interrupt pending 0 = IRQ2 interrupt not pending ACK2 — IRQ2 Interrupt Request Acknowledge Bit Writingalogic1tothiswrite-onlybitclearstheIRQ2latch.ACK2alwaysreadsaslogic0.Resetclears ACK2. IMASK2 — IRQ2 Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ2 interrupt requests. Reset clears IMASK2. 1 = IRQ2 interrupt requests disabled 0 = IRQ2 interrupt requests enabled MODE2 — IRQ2 Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ2 pin. Reset clears MODE2. 1 = IRQ2 interrupt requests on falling edges and low levels 0 = IRQ2 interrupt requests on falling edges only MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 275

External Interrupt (IRQ) MC68HC908AP Family Data Sheet, Rev. 4 276 Freescale Semiconductor

Chapter 18 Keyboard Interrupt Module (KBI) 18.1 Introduction Thekeyboardinterruptmodule(KBI)provideseightindependentlymaskableexternalinterruptswhichare accessibleviaPTD0–PTD7.Whenaportpinisenabledforkeyboardinterruptfunction,aninternal30kΩ pullup device is also enabled on the pin. 18.2 Features Features of the keyboard interrupt module include the following: • Eight keyboard interrupt pins with pullup devices • Separate keyboard interrupt enable bits and one keyboard interrupt mask • Programmable edge-only or edge- and level- interrupt sensitivity • Exit from low-lower modes Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Keyboard Status Read: 0 0 0 0 KEYF 0 IMASKK MODEK $001A and Control Register Write: ACKK (KBSCR) Reset: 0 0 0 0 0 0 0 0 Keyboard Interrupt Enable Read: KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 $001B Register Write: (KBIER) Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 18-1. KBI I/O Register Summary 18.3 I/O Pins The eight keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins are listed in Table 18-1. The generic pin name appear in the text that follows. Table 18-1. Pin Name Conventions KBI PinSelectedforKBIFunctionbyKBIEx Full MCU Pin Name Generic Pin Name Bit in KBIER KBI0–KBI7 PTD0/KBI0–PTD7/KBI7 KBIE0–KBIE7 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 277

Keyboard Interrupt Module (KBI) 18.4 Functional Description INTERNAL BUS VECTOR FETCH KBI0 DECODER ACKK V DD KEYF RESET . CLR D Q KBIE0 SYNCHRONIZER Keyboard . CK Interrupt TO PULLUP ENABLE Request . KEYBOARD IMASKK KBI7 INTERRUPT FF MODEK KBIE7 TO PULLUP ENABLE Figure 18-2. Keyboard Interrupt Block Diagram Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port D pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port D also enables its internal pull-up device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. Akeyboardinterruptislatchedwhenoneormorekeyboardpinsgoeslowafterallwerehigh.TheMODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. • Ifthekeyboardinterruptisedge-sensitiveonly,afallingedgeonakeyboardpindoesnotlatchan interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. • Ifthekeyboardinterruptisfallingedge-andlowlevel-sensitive,aninterruptrequestispresentas long as any keyboard pin is low. IftheMODEKbitisset,thekeyboardinterruptpinsarebothfallingedge-andlowlevel-sensitive,andboth of the following actions must occur to clear a keyboard interrupt request: • Vectorfetchorsoftwareclear—Avectorfetchgeneratesaninterruptacknowledgesignaltoclear theinterruptrequest.Softwaremaygeneratetheinterruptacknowledgesignalbywritingalogic1 to the ACKK bit in the keyboard status and control register KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also preventspuriousinterruptsduetonoise.SettingACKKdoesnotaffectsubsequenttransitionson thekeyboardinterruptpins.AfallingedgethatoccursafterwritingtotheACKKbitlatchesanother interruptrequest.Ifthekeyboardinterruptmaskbit,IMASKK,isclear,theCPUloadstheprogram counter with the vector address at locations $FFE0 and $FFE1. • Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. MC68HC908AP Family Data Sheet, Rev. 4 278 Freescale Semiconductor

Keyboard Interrupt Registers IftheMODEKbitisclear,thekeyboardinterruptpinisfalling-edge-sensitiveonly.WithMODEKclear,a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. Thekeyboardflagbit(KEYF)inthekeyboardstatusandcontrolregistercanbeusedtoseeifapending interrupt exists.The KEYFbitis not affected bythe keyboard interrupt mask bit(IMASKK) whichmakes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. NOTE Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboardinterruptpintobeaninput,overridingthedatadirectionregister. However, the data direction register bit must be a logic 0 for software to read the pin. 18.4.1 Keyboard Initialization Whenakeyboardinterruptpinisenabled,ittakestimefortheinternalpull-uptoreachalogic1.Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. EnabletheKBIpinsbysettingtheappropriateKBIExbitsinthekeyboardinterruptenableregister. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. Aninterruptsignalonanedge-triggeredpincanbeacknowledgedimmediatelyafterenablingthepin.An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDR bits in data direction register. 2. Write logic 1s to the appropriate data register bits. 3. EnabletheKBIpinsbysettingtheappropriateKBIExbitsinthekeyboardinterruptenableregister. 18.5 Keyboard Interrupt Registers Two registers control the operation of the keyboard interrupt module: • Keyboard Status and Control Register — $001A • Keyboard Interrupt Enable Register — $001B 18.5.1 Keyboard Status and Control Register • Flags keyboard interrupt requests • Acknowledges keyboard interrupt requests • Masks keyboard interrupt requests • Controls keyboard interrupt triggering sensitivity MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 279

Keyboard Interrupt Module (KBI) Address: $001A Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 KEYF 0 IMASKK MODEK Write: ACKK Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 18-3. Keyboard Status and Control Register (KBSCR) KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK — Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only 18.5.2 Keyboard Interrupt Enable Register The port-D keyboard interrupt enable register enables or disables each port-D pin to operate as a keyboard interrupt pin. Address: $001B Bit 7 6 5 4 3 2 1 Bit 0 Read: KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 18-4. Keyboard Interrupt Enable Register (KBIER) KBIE7–KBIE0 — Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin MC68HC908AP Family Data Sheet, Rev. 4 280 Freescale Semiconductor

Low-Power Modes 18.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 18.6.1 Wait Mode The keyboard interrupt module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 18.6.2 Stop Mode The keyboard interrupt module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 18.7 Keyboard Module During Break Interrupts Thesystemintegrationmodule(SIM)controlswhetherthekeyboardinterruptlatchcanbeclearedduring the break state. The BCFE bit in the SIM break flag control register (BFCR) enables software to clear status bits during the break state. Toallowsoftwaretoclearthekeyboardinterruptlatchduringabreakinterrupt,writealogic1totheBCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. Toprotectthelatchduringthebreakstate,writealogic0totheBCFEbit.WithBCFEatlogic0(itsdefault state),writingtothekeyboardacknowledgebit(ACKK)inthekeyboardstatusandcontrolregisterduring the break state has no effect. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 281

Keyboard Interrupt Module (KBI) MC68HC908AP Family Data Sheet, Rev. 4 282 Freescale Semiconductor

Chapter 19 Computer Operating Properly (COP) 19.1 Introduction Thecomputeroperatingproperly(COP)modulecontainsafree-runningcounterthatgeneratesaresetif allowedtooverflow.TheCOPmodulehelpssoftwarerecoverfromrunawaycode.PreventaCOPreset byclearingtheCOPcounterperiodically.TheCOPmodulecanbedisabledthroughtheCOPDbitinthe configuration register 1 (CONFIG1). 19.2 Functional Description Figure 19-1 shows the structure of the COP module. ICLK 12-BIT COP PRESCALER RESET CIRCUIT S 2 E 1 G – RESET STATUS REGISTER TA S 5 S E L G L A A T T AR R S OU STOP INSTRUCTION LE EA ME INTERNAL RESET SOURCES C CL TI P RESET VECTOR FETCH O C COPCTL WRITE COP CLOCK 6-BIT COP COUNTER COPEN (FROM SIM) COP DISABLE (COPD FROM CONFIG1) RESET CLEAR COPCTL WRITE COP COUNTER COP RATE SEL (COPRS FROM CONFIG1) Figure 19-1. COP Block Diagram TheCOPcounterisafree-running6-bitcounterprecededbya12-bitprescalercounter.Ifnotclearedby software, the COP counter overflows and generates an asynchronous reset after 218– 24 or 213– 24 ICLK cycles, depending on the state of the COP rate select bit, COPRS, in the CONFIG1 register. With a213– 24ICLKcycleoverflowoption,a88-kHzICLKgivesaCOPtimeoutperiodof~93ms.Writingany value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the prescaler. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 283

Computer Operating Properly (COP) NOTE ServicetheCOPimmediatelyafterresetandbeforeenteringorafterexiting STOPModetoguaranteethemaximumtimebeforethefirstCOPcounter overflow. ACOPresetpullstheRSTpinlowfor32ICLKcyclesandsetstheCOPbitintheSIMresetstatusregister (SRSR). Inmonitormode,theCOPisdisablediftheRSTpinortheIRQ1isheldatV .Duringthebreakstate, TST V on the RST pin disables the COP. TST NOTE PlaceCOPclearinginstructionsinthemainprogramandnotinaninterrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. 19.3 I/O Signals The following paragraphs describe the signals shown in Figure 19-1. 19.3.1 ICLK ICLK is the internal oscillator output signal. See Chapter 22 Electrical Specifications for ICLK frequency specification. 19.3.2 STOP Instruction The STOP instruction clears the COP prescaler. 19.3.3 COPCTL Write WritinganyvaluetotheCOPcontrolregister(COPCTL)(see19.4COPControlRegister)clearstheCOP counter and clears bits 12 through 5 of the prescaler. Reading the COP control register returns the low byte of the reset vector. 19.3.4 Power-On Reset The power-on reset (POR) circuit clears the COP prescaler 4096 ICLK cycles after power-up. 19.3.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. 19.3.6 Reset Vector Fetch Aresetvectorfetchoccurswhenthevectoraddressappearsonthedatabus.Aresetvectorfetchclears the COP prescaler. 19.3.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the CONFIG1 register. (See Figure 19-2 . Configuration Register 1 (CONFIG1).) MC68HC908AP Family Data Sheet, Rev. 4 284 Freescale Semiconductor

COP Control Register 19.3.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the CONFIG1 register. Address: $001F Bit 7 6 5 4 3 2 1 Bit 0 Read: COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD Write: Reset: 0 0 0 0 0 0 0 0 Figure 19-2. Configuration Register 1 (CONFIG1) COPRS — COP Rate Select Bit COPRS selects the COP time out period. Reset clears COPRS. 1 = COP time out period = 213 – 24 ICLK cycles 0 = COP time out period = 218 – 24 ICLK cycles COPD — COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled 19.4 COP Control Register TheCOPcontrolregisterislocatedataddress$FFFFandoverlapstheresetvector.Writinganyvalueto $FFFFclearstheCOPcounterandstartsanewtimeoutperiod.Readinglocation$FFFFreturnsthelow byte of the reset vector. Address: $FFFF Bit 7 6 5 4 3 2 1 Bit 0 Read: Low byte of reset vector Write: Clear COP counter Reset: Unaffected by reset Figure 19-3. COP Control Register (COPCTL) 19.5 Interrupts The COP does not generate CPU interrupt requests. 19.6 Monitor Mode WhenmonitormodeisenteredwithV ontheIRQ1pin,theCOPisdisabledaslongasV remains TST TST on the IRQ1 pin or the RST pin. When monitor mode is entered by having blank reset vectors and not having V on the IRQ1 pin, the COP is automatically disabled until a POR occurs. TST 19.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 285

Computer Operating Properly (COP) 19.7.1 Wait Mode TheCOPremainsactiveduringwaitmode.TopreventaCOPresetduringwaitmode,periodicallyclear the COP counter in a CPU interrupt routine. 19.7.2 Stop Mode Stop mode turns off the ICLK input to the COP and clears the COP prescaler. Service the COP immediatelybeforeenteringorafterexitingstopmodetoensureafullCOPtimeoutperiodafterentering or exiting stop mode. Topreventinadvertently turningoffthe COPwithaSTOPinstruction,aconfigurationoptionisavailable that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction is disabled, execution of a STOP instruction results in an illegal opcode reset. 19.8 COP Module During Break Mode The COP is disabled during a break interrupt when V is present on the RST pin. TST MC68HC908AP Family Data Sheet, Rev. 4 286 Freescale Semiconductor

Chapter 20 Low-Voltage Inhibit (LVI) 20.1 Introduction Thissectiondescribesthelow-voltageinhibit(LVI)module.TheLVImodulemonitorsthevoltageonthe V pinandV pin,andcanforcearesetwhenV voltagefallsbelowV ,orV voltagefalls DD REG DD TRIPF1 REG below V . TRIPF2 NOTE The V pin is the output of the internal voltage regulator and is REG guaranteed to meet operating specification as long as V is within the DD MCU operating voltage. The LVI feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application V voltage collapsing completely to an unsafe level. It is not DD intendedthatusersoperatethemicrocontrolleratlowerthanthespecified operating voltage, VDD. 20.2 Features Features of the LVI module include: • Independent voltage monitoring circuits for V and V DD REG • Independent disable for V and V LVI circuits DD REG • Programmable LVI reset • Programmable stop mode operation Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: LVIOUT 0 0 0 0 0 0 0 LVI Status Register $FE0F Write: (LVISR) Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 20-1. LVI I/O Register Summary 20.3 Functional Description Figure 20-2 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module containsindependentbandgapreferencecircuitandcomparatorformonitoringtheV voltageandthe DD V voltage. An LVI reset performs a MCU internal reset and drives the RST pin low to provide REG low-voltage protection to external peripheral devices. LVISTOP, LVIPWRD, LVIRSTD, and LVIREGD are in the CONFIG1 register. See Chapter 3 Configuration &Mask OptionRegisters(CONFIG &MOR)fordetails oftheLVIconfigurationbits.Once MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 287

Low-Voltage Inhibit (LVI) an LVI reset occurs, the MCU remains in reset until V rises above V and V rises above DD TRIPR1 REG V , which causes the MCU to exit reset. The output of the comparator controls the state of the TRIPR2 LVIOUT flag in the LVI status register (LVISR). AnLVIresetalsodrivestheRSTpinlowtoprovidelow-voltageprotectiontoexternalperipheraldevices. V DD STOP INSTRUCTION LVISTOP FROM CONFIG1 LVIPWRD FROM CONFIG1 FROM CONFIG1 LVIRSTD LOW VDD VDD> VTRIPR1 = 0 DETECTOR V ≤ V = 1 DD TRIPF1 LVI RESET V > V = 0 LOW V REG TRIPR2 REG DETECTOR V ≤ V = 1 REG TRIPF2 LVIOUT FROM CONFIG1 TO LVISR LVIREGD FROM CONFIG1 LVISTOP STOP INSTRUCTION V REG Figure 20-2. LVI Module Block Diagram 20.3.1 Low V Detector DD ThelowV detectorcircuitmonitorstheV voltageandforcesaLVIresetwhentheV voltagefalls DD DD DD below the trip voltage, V . The V LVI circuit can be disabled by the setting the LVIPWRD bit in TRIPF1 DD CONFIG1 register. 20.3.2 Low V Detector REG The low V detector circuit monitors the V voltage and forces a LVI reset when the V voltage REG REG REG fallsbelowthetripvoltage,V .TheV LVIcircuitcanbedisabledbythesettingtheLVIREGDbit TRIPF2 REG in CONFIG1 register. 20.3.3 Polled LVI Operation InapplicationsthatcanoperateatV levelsbelowtheV level,softwarecanmonitorV bypolling DD TRIPF1 DD theLVIOUTbit.IntheCONFIG1register,theLVIPWRDbitmustbeatlogic0toenabletheLVImodule, and the LVIRSTD bit must be at logic 1 to disable LVI resets. MC68HC908AP Family Data Sheet, Rev. 4 288 Freescale Semiconductor

LVI Status Register 20.3.4 Forced Reset Operation In applications that require V to remain above the V level, enabling LVI resets allows the LVI DD TRIPF1 moduletoresettheMCUwhenV fallsbelowtheV level.IntheCONFIG1register,theLVIPWRD DD TRIPF1 and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets. 20.3.5 Voltage Hysteresis Protection OncetheLVIhastriggered(byhavingV fallbelowV ),theLVIwillmaintainaresetconditionuntil DD TRIPF1 V rises above the rising trip point voltage, V . This prevents a condition in which the MCU is DD TRIPR1 continually entering and exiting reset if V is approximately equal to V . V is greater than DD TRIPF1 TRIPR1 V by the hysteresis voltage, V . TRIPF1 HYS 20.4 LVI Status Register TheLVIstatusregister(LVISR)indicatesiftheV voltagewasdetectedbelowV orV voltage DD TRIPF1 REG was detected below V . TRIPF2 Address: $FE0F Bit 7 6 5 4 3 2 1 Bit 0 Read: LVIOUT 0 0 0 0 0 0 0 Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 20-3. LVI Status Register LVIOUT — LVI Output Bit Thisread-onlyflagbecomessetwhentheV orV fallsbelowtheirrespectivetripvoltages.Reset DD REG clears the LVIOUT bit. Table 20-1. LVIOUT Bit Indication VDD, VREG LVIOUT V > V DD TRIPR1 and 0 V > V REG TRIPR2 V < V DD TRIPF1 or 1 V < V DD TRIPF2 V < V < V TRIPF1 DD TRIPR1 or Previous value V < V < V TRIPF2 REG TRIPR2 20.5 LVI Interrupts The LVI module does not generate interrupt requests. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 289

Low-Voltage Inhibit (LVI) 20.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 20.6.1 Wait Mode Ifenabled,theLVImoduleremainsactiveinwaitmode.Ifenabledtogenerateresets,theLVImodulecan generate a reset and bring the MCU out of wait mode. 20.6.2 Stop Mode If enabled in stop mode (LVISTOP = 1), the LVI module remains active in stop mode. If enabled to generate resets (LVIRSTD = 0), the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908AP Family Data Sheet, Rev. 4 290 Freescale Semiconductor

Chapter 21 Break Module (BRK) 21.1 Introduction This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 21.2 Features Features of the break module include: • Accessible input/output (I/O) registers during the break interrupt • CPU-generated break interrupts • Software-generated break interrupts • COP disabling during break interrupts Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: SBSW SIM Break Status Register R R R R R R R $FE00 Write: Note (SBSR) Reset: 0 SIM Break Flag Control Read: BCFE R R R R R R R $FE03 Register Write: (SBFCR) Reset: 0 Break Address Read: Bit 15 14 13 12 11 10 9 Bit 8 $FE0C Register High Write: (BRKH) Reset: 0 0 0 0 0 0 0 0 Break Address Read: Bit 7 6 5 4 3 2 1 Bit 0 $FE0D Register Low Write: (BRKL) Reset: 0 0 0 0 0 0 0 0 Break Status and Control Read: 0 0 0 0 0 0 BRKE BRKA $FE0E Register Write: (BRKSCR) Reset: 0 0 0 0 0 0 0 0 Note: Writing a logic 0 clears BW. =Unimplemented R =Reserved Figure 21-1. Break Module I/O Register Summary 21.3 Functional Description Whentheinternaladdressbusmatchesthevaluewritteninthebreakaddressregisters,thebreakmodule issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 291

Break Module (BRK) The following events can cause a break interrupt to occur: • ACPU-generatedaddress(theaddressintheprogramcounter)matchesthecontentsofthebreak address registers. • Software writes a logic 1 to the BRKA bit in the break status and control register. WhenaCPU-generatedaddressmatchesthecontentsofthebreakaddressregisters,thebreakinterrupt begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 21-2 shows the structure of the break module. IAB15–IAB8 BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB15–IAB0 CONTROL BREAK 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB7–IAB0 Figure 21-2. Break Module Block Diagram 21.3.1 Flag Protection During Break Interrupts TheBCFEbitintheSIMbreakflagcontrolregister(SBFCR)enablessoftwaretoclearstatusbitsduring the break state. 21.3.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 21.3.3 TIMI and TIM2 During Break Interrupts A break interrupt stops the timer counters. 21.3.4 COP During Break Interrupts The COP is disabled during a break interrupt when V is present on the RST pin. TST 21.4 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. MC68HC908AP Family Data Sheet, Rev. 4 292 Freescale Semiconductor

Break Module Registers 21.4.1 Wait Mode Ifenabled,thebreakmoduleisactiveinwaitmode.Inthebreakroutine,theusercansubtractonefrom the return address on the stack if SBSW is set. (see Chapter 7 System Integration Module (SIM)) Clear the BW bit by writing logic 0 to it. 21.4.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. 21.5 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • SIM break status register (SBSR) • SIM break flag control register (SBFCR) 21.5.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Address: $FE0E Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 BRKE BRKA Write: Reset: 0 0 0 0 0 0 0 0 =Unimplemented Figure 21-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKAgeneratesabreakinterrupt.ClearBRKAbywritingalogic0toitbeforeexitingthebreakroutine. Reset clears the BRKA bit. 1 = (When read) Break address match 0 = (When read) No break address match MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 293

Break Module (BRK) 21.5.2 Break Address Registers Thebreakaddressregisters(BRKHandBRKL)containthehighandlowbytesofthedesiredbreakpoint address. Reset clears the break address registers. Address: $FE0C Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: 0 0 0 0 0 0 0 0 Figure 21-4. Break Address Register High (BRKH) Address: $FE0D Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Reset: 0 0 0 0 0 0 0 0 Figure 21-5. Break Address Register Low (BRKL) 21.5.3 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode.Theflagisusefulinapplicationsrequiringareturntowaitmodeafterexitingfromabreakinterrupt. Address: $FE00 Bit 7 6 5 4 3 2 1 Bit 0 Read: SBSW R R R R R R R Write: Note Reset: 0 Note: Writing a logic 0 clears SBSW. R =Reserved Figure 21-6. SIM Break Status Register (SBSR) SBSW — Break Wait Bit Thisstatusbitissetwhenabreakinterruptcausesanexitfromwaitmodeorstopmode.ClearSBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSWcanbereadwithinthebreakinterruptroutine.Theusercanmodifythereturnaddressonthestack by subtracting 1 from it. The following code is an example. MC68HC908AP Family Data Sheet, Rev. 4 294 Freescale Semiconductor

Break Module Registers ;This code works if the H register has been pushed onto the stack in the break ;service routine software. This code should be executed at the end of the break ;service routine software. HIBYTE EQU 5 LOBYTE EQU 6 ; If not SBSW, do RTI BRCLR SBSW,SBSR, RETURN ;See if wait mode or stop mode was exited by ;break. TST LOBYTE,SP ;If RETURNLO is not zero, BNE DOLO ;then just decrement low byte. DEC HIBYTE,SP ;Else deal with high byte, too. DOLO DEC LOBYTE,SP ;Point to WAIT/STOP opcode. RETURN PULH ;Restore H register. RTI 21.5.4 SIM Break Flag Control Register TheSIMbreakflagcontrolregister(SBFCR)containsabitthatenablessoftwaretoclearstatusbitswhile the MCU is in a break state. Address: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read: BCFE R R R R R R R Write: Reset: 0 R =Reserved Figure 21-7. SIM Break Flag Control Register (SBFCR) BCFE — Break Clear Flag Enable Bit Thisread/writebitenablessoftwaretoclearstatusbitsbyaccessingstatusregisterswhiletheMCUis in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 295

Break Module (BRK) MC68HC908AP Family Data Sheet, Rev. 4 296 Freescale Semiconductor

Chapter 22 Electrical Specifications 22.1 Introduction This section contains electrical and timing specifications. 22.2 Absolute Maximum Ratings MaximumratingsaretheextremelimitstowhichtheMCUcanbeexposedwithoutpermanentlydamagingit. NOTE Thisdeviceisnotguaranteedtooperateproperlyatthemaximumratings. RefertoDCElectricalCharacteristicsforguaranteedoperatingconditions. Table 22-1. Absolute Maximum Ratings Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to +6.0 V Input voltage All pins (exceptIRQ1) VIN VSS–0.3 to VDD +0.3 V IRQ1 pin V –0.3 to 8.5 V SS Maximum current per pin excluding I ±25 mA V and V DD SS Maximum current out of VSS IMVSS 100 mA Maximum current into VDD IMVDD 100 mA Storage temperature TSTG –55 to +150 °C 1. Voltages referenced to V . SS NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that V and V be constrained to the IN OUT range V ≤ (V or V ) ≤ V . Reliability of operation is enhanced if SS IN OUT DD unused inputs are connected to an appropriate logic voltage level (for example, either V or V .) SS DD MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 297

Electrical Specifications 22.3 Functional Operating Range Table 22-2. Operating Range Characteristic Symbol Value Unit Operating temperature range TA –40 to +85 °C Operating voltage range VDD 2.7 to 5.5 V 22.4 Thermal Characteristics Table 22-3. Thermal Characteristics Characteristic Symbol Value Unit Thermal resistance 42-Pin SDIP θ 60 °C/W 44-Pin QFP JA 95 °C/W 48-Pin LQFP 80 °C/W I/O pin power dissipation PI/O User determined W P = (I ×V ) + P = Power dissipation(1) PD D K/D(TD + 2D7D3°C)I/O W J P x(T + 273°C) Constant(2) K D A W/°C + P 2×θ D JA Average junction temperature TJ TA + (PD× θJA) °C Maximum junction temperature TJM 100 °C 1. Power dissipation is a function of temperature. 2. K constant unique to the device. K can be determined for a known T and measuredP A D. With this value of K, P and T can be determined for any value of T . D J A MC68HC908AP Family Data Sheet, Rev. 4 298 Freescale Semiconductor

5V DC Electrical Characteristics 22.5 5V DC Electrical Characteristics Table 22-4. DC Electrical Characteristics (5V) Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (ILOAD = –12mA) PTA[0:7], PTB[4:7], PTC[0:5], PTD[0:7] VOH VDD–0.8 — — V (I = –15mA) PTA[0:7], PTB[4:7], PTC[0:5], PTD[0:7] V V –1.0 — — V LOAD OH DD Output low voltage (ILOAD = 6mA)PTA[0:7], PTB[4:7], PTC[0:5], PTD[0:7] VOL — — 0.4 V (ILOAD = 12mA) PTB[0:3], PTC[6:7] VOL — — 0.4 V (ILOAD = 15mA) PTA[0:7], PTB[4:7], PTC[0:5], PTD[0:7] VOL — — 0.8 V (ILOAD = 15mA) PTB[0:3], PTC[6:7] VOL — — 0.6 V (ILOAD = 15mA) as TxD, RxD, SCTxD, SCRxD VOLSCI — — 0.4 V (ILOAD = seeTable 22-12) as SDA, SCL VOLIIC — — 0.4 V LED sink current (V = 3V) OL IOL 9 15 25 mA PTA[0:7] Input high voltage PTA[0:7], PTB[0:7], PTC[0:7], PTD[0:7],RST,IRQ1 VIH 0.7×VDD — VDD V OSC1 0.7×V — V V REG REG Input low voltage PTA[0:7], PTB[0:7], PTC[0:7], PTD[0:7],RST,IRQ1 VIL VSS — 0.3×VDD V OSC1 V — 0.3×V V SS REG V supply current, f = 8 MHz DD OP Run(3) — 10 20 mA Wait(4) — 2.5 10 mA Stop (25°C) with OSC, TBM, and LVI modules on(5) — 0.8 1.8 mA I with OSC and TBM modules on(5) DD — 22 150 µA all modules off(6) — 20 125 µA Stop (0 to 85°C) with OSC, TBM, and LVI modules on(5) — 1 2.5 mA with OSC and TBM modules on(5) — 45 300 µA all modules off(6) — 42 250 µA Digital I/O ports Hi-Z leakage current IIL — — ±10 µA Input current IIN — — ±1 µA Capacitance COUT — — 12 pF Ports (as input or output) C — — 8 pF IN POR rearm voltage(7) VPOR 0 — 100 mV POR rise time ramp rate(8) RPOR 0.035 — — V/ms Monitor mode entry voltage VTST 1.4×VDD 8.5 V MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 299

Electrical Specifications Table 22-4. DC Electrical Characteristics (5V) Characteristic(1) Symbol Min Typ(2) Max Unit Pullup resistors(9) PTD[0:7] RPU1 21 27 39 kΩ RST,IRQ1,IRQ2 RPU2 21 27 39 kΩ Low-voltage inhibit, trip falling voltage1(10) VTRIPF1 2.25 2.45 2.65 V Low-voltage inhibit, trip rising voltage1(10) VTRIPR1 2.35 2.55 2.75 V Low-voltage inhibit, trip voltage2(10) VTRIPF2 2.25 2.45 2.65 V VREG(10), (11) VREG 2.25 2.50 2.75 V 1. V = 4.5 to 5.5 Vdc, V = 0 Vdc, T = T to T , unless otherwise noted. DD SS A L H 2. Typical values reflect average measurements at midpoint of voltage range, 25°C only. 3.Run(operating)I measuredusingexternal32MHzclocktoOSC1;allinputs0.2Vfromrail;nodcloads;lessthan100pF DD onalloutputs;C =20pFonOSC2;allportsconfiguredasinputs;OSC2capacitancelinearlyaffectsrunI ;measured L DD with all modules enabled. 4.WaitI measuredusingexternal32MHztoOSC1;allinputs0.2Vfromrail;nodcloads;lessthan100pFonalloutputs. DD C = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait I . L DD 5. STOP I measured using external 32.768kHz clock to OSC1; no port pins sourcing current. DD 6. STOP I measured with OSC1 grounded; no port pins sourcing current. DD 7. Maximum is highest voltage that POR is guaranteed. The rearm voltage is triggered by V . REG 8.IfminimumV isnotreachedbeforetheinternalPORresetisreleased,RSTmustbedrivenlowexternallyuntilminimum DD V is reached. DD 9. R andR are measured atV = 5.0V PU1 PU2 DD 10. Values are not affected by operating V ; they are the same for 3V and 5V. DD 11. Measured from V = V (Min) to 5.5 V. DD TRIPF1 22.6 5V Control Timing Table 22-5. Control Timing (5V) Characteristic(1) Symbol Min Max Unit Internal operating frequency(2) fOP — 8 MHz RST input pulse width low(3) tIRL 750 — ns 1. V = 4.5 to 5.5 Vdc, V = 0 Vdc; timing shown with respect to 20% V and 70% V , unless otherwise noted. DD SS DD DD 2.Somemodulesmayrequireaminimumfrequencygreaterthandcforproperoperation;seeappropriatetableforthisin- formation. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. MC68HC908AP Family Data Sheet, Rev. 4 300 Freescale Semiconductor

5V Oscillator Characteristics 22.7 5V Oscillator Characteristics Table 22-6. Oscillator Specifications (5V) Characteristic(1) Symbol Min Typ Max Unit Internal oscillator clock frequency fICLK 64k 88k(2) 104k Hz External reference clock to OSC1(3) fOSC dc 32M Hz Crystal reference frequency fXTALCLK 30 32.768 100 kHz Crystal load capacitance(4) CL — 12.5 — pF Crystal fixed capacitance(5) C1 — 15 — pF Crystal tuning capacitance(6) C2 — 15 — pF Feedback bias resistor RB 1 10 22 MΩ Series resistor RS 100 330 470 kΩ External RC clock frequency fRCCLK 7.6M Hz RC oscillator external R REXT SeeFigure22-1 Ω RC oscillator external C CEXT — 10 — pF 1. The oscillator circuit operates at V . REG 2. Typical value reflect average measurements at midpoint of voltage range, 25°C only. 3. No more than 10% duty cycle deviation from 50%. The max. frequency is limited by an EMC filter. 4. Crystal manufacturer value. 5. Capacitor on OSC1 pin. Does not include parasitic capacitance due to package, pin, and board. 6. Capacitor on OSC2 pin. Does not include parasitic capacitance due to package, pin, and board. ) z H (MK 8 CVEXT = = 5 1V0, @pF 25°C MCU L DD OSC1 C C 6 R y, f c 4 n V e REG u R C q 2 EXT EXT e r C f 0 R 0 10 20 30 40 50 Resistor, R (kΩ) EXT Figure 22-1. RC vs. Frequency MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 301

Electrical Specifications 22.8 5V ADC Electrical Characteristics Table 22-7. ADC Electrical Characteristics (5V) Characteristic(1) Symbol Min Max Unit Notes V isandedicatedpinandshould DDA Supply voltage VDDA 4.5 5.5 V be tied to VDDon the PCB with proper decoupling. Input range VADIN 0 VDDA V VADIN≤ VDDA Resolution BAD 10 10 bits Includes quantization. Absolute accuracy AAD — ±1.5 LSB ±0.5 LSB =±1 ADC step. ADC internal clock fADIC 500k 1.048M Hz tADIC = 1/fADIC Conversion range RAD VREFL VREFH V ADC voltage reference high VREFH — VDDA+ 0.1 V ADC voltage reference low VREFL VSSA– 0.1 — V t Conversion time tADC 16 17 ADIC cycles t Sample time tADS 5 — ADIC cycles Monotonicity MAD Guaranteed Zero input reading ZADI 000 001 HEX VADIN = VREFL Full-scale reading FADI 3FD 3FF HEX VADIN = VREFH Input capacitance CADI — 20 pF Not tested. Input impedance RADI 20M — Ω VREFH/VREFL IVREF — 1.6 mA Not tested. 1. V = 4.5 to 5.5 Vdc, V = 0 Vdc, T = T to T , unless otherwise noted. DD SS A L H MC68HC908AP Family Data Sheet, Rev. 4 302 Freescale Semiconductor

3V DC Electrical Characteristics 22.9 3V DC Electrical Characteristics Table 22-8. DC Electrical Characteristics (3V) Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (I = –4mA) LOAD PTA[0:7], PTB[4:7], PTC[0:5], PTD[0:7] VOH VDD–0.4 — — V Output low voltage (ILOAD = 4mA)PTA[0:7], PTB[4:7], PTC[0:5], PTD[0:7] VOL — — 0.4 V (ILOAD = 10mA) PTB[0:3], PTC[6:7] VOL — — 0.4 V (ILOAD = 10mA) as TxD, RxD, SCTxD, SCRxD VOLSCI — — 0.4 V (ILOAD = seeTable 22-12) as SDA, SCL VOLIIC — — 0.4 V LED sink current (V = 2V) OL IOL 3 7 15 mA PTA[0:7] Input high voltage PTA[0:7], PTB[0:7], PTC[0:7], PTD[0:7],RST,IRQ1 VIH 0.7×VDD — VDD V OSC1 0.7×V — V V REG REG Input low voltage PTA[0:7], PTB[0:7], PTC[0:7], PTD[0:7],RST,IRQ1 VIL VSS — 0.3×VDD V OSC1 V — 0.3×V V SS REG V supply current(3) DD Run(4) with f = 4 MHz — 6 10 mA OP — 7.5 10 mA with f = 8 MHz OP Wait(5) with fOP = 4 MHz IDD — 2 5 mA with f = 8 MHz — 2.9 5 mA OP Stop (25°C) with OSC, TBM, and LVI modules on(6) — 1.2 1.6 mA with OSC and TBM modules on(6) — 7 60 µA all modules off(7) — 5 50 µA Stop (0 to 85°C) with OSC, TBM, and LVI modules on(6) — 1.3 2.2 mA with OSC and TBM modules on(6) — 35 220 µA all modules off(7) — 30 200 µA Digital I/O ports Hi-Z leakage current IIL — — ±10 µA Input current IIN — — ±1 µA Capacitance COUT — — 12 pF Ports (as input or output) C — — 8 pF IN POR rearm voltage(8) VPOR 0 — 100 mV POR rise time ramp rate(9) RPOR 0.02 — — V/ms Monitor mode entry voltage VTST 1.4×VDD 8.5 V MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 303

Electrical Specifications Table 22-8. DC Electrical Characteristics (3V) Characteristic(1) Symbol Min Typ(2) Max Unit Pullup resistors(10) PTD[0:7] RPU1 21 27 39 kΩ RST,IRQ1,IRQ2 RPU2 21 27 39 kΩ Low-voltage inhibit, trip falling voltage1(11) VTRIPF1 2.25 2.45 2.65 V Low-voltage inhibit, trip rising voltage1(10) VTRIPR1 2.35 2.55 2.75 V Low-voltage inhibit, trip voltage2(10) VTRIPF2 2.25 2.45 2.65 V VREG(10), (12) VREG 2.25 2.50 2.75 V 1. V = 2.7 to 3.3 Vdc, V = 0 Vdc, T = T to T , unless otherwise noted. DD SS A L H 2. Typical values reflect average measurements at midpoint of voltage range, 25°C only. 3.AtV =3V,anon-chipchargepumpisactivatedfortheV regulator,thereforesomeI valueswillappearhigher DD REG DD than the I values at V = 5V. DD DD 4.Run(operating)I measuredusingexternal16MHz/32MHzclocktoOSC1;allinputs0.2Vfromrail;nodcloads;less DD than100pFonalloutputs;C =20pFonOSC2;allportsconfiguredasinputs;OSC2capacitancelinearlyaffectsrunI ; L DD measured with all modules enabled. 5.WaitI measuredusingexternal16MHz/32MHzclocktoOSC1;allinputs0.2Vfromrail;nodcloads;lessthan100pF DD on all outputs. C = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait I . L DD 6. STOP I measured with external 32.768kHz clock to OSC1; no port pins sourcing current. DD 7. STOP I measured with OSC1 grounded; no port pins sourcing current. DD 8. Maximum is highest voltage that POR is guaranteed. The rearm voltage is triggered by V . REG 9.IfminimumV isnotreachedbeforetheinternalPORresetisreleased,RSTmustbedrivenlowexternallyuntilminimum DD V is reached. DD 10. R andR are measured atV = 5.0V PU1 PU2 DD 11. Values are not affected by operating V ; they are the same for 3V and 5V. DD 12. Measured from V = V (Min) to 5.5 V. DD TRIPF1 22.10 3V Control Timing Table 22-9. Control Timing (3V) Characteristic(1) Symbol Min Max Unit Internal operating frequency(2) fOP — 8 MHz RST input pulse width low(3) tIRL 750 — ns 1. V = 2.7 to 3.3 Vdc, V = 0 Vdc; timing shown with respect to 20% V and 70% V , unless otherwise noted. DD SS DD DD 2.Somemodulesmayrequireaminimumfrequencygreaterthandcforproperoperation;seeappropriatetableforthisin- formation. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. MC68HC908AP Family Data Sheet, Rev. 4 304 Freescale Semiconductor

3V Oscillator Characteristics 22.11 3V Oscillator Characteristics Table 22-10. Oscillator Specifications (3V) Characteristic(1) Symbol Min Typ Max Unit Internal oscillator clock frequency fICLK 64k 88k(2) 104k Hz External reference clock to OSC1(3) fOSC dc 32M Hz Crystal reference frequency fXTALCLK 30 32.768 100 kHz Crystal load capacitance(4) CL — 12.5 — pF Crystal fixed capacitance(5) C1 — 15 — pF Crystal tuning capacitance(6) C2 — 15 — pF Feedback bias resistor RB 1 10 22 MΩ Series resistor RS 100 330 470 kΩ External RC clock frequency fRCCLK 7.6M Hz RC oscillator external R REXT SeeFigure22-1 Ω RC oscillator external C CEXT — 10 — pF 1. The oscillator circuit operates at V . REG 2. Typical value reflect average measurements at midpoint of voltage range, 25°C only. 3. No more than 10% duty cycle deviation from 50%. The max. frequency is limited by an EMC filter. 4. Crystal manufacturer value. 5. Capacitor on OSC1 pin. Does not include parasitic capacitance due to package, pin, and board. 6. Capacitor on OSC2 pin. Does not include parasitic capacitance due to package, pin, and board. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 305

Electrical Specifications 22.12 3V ADC Electrical Characteristics Table 22-11. ADC Electrical Characteristics (3V) Characteristic(1) Symbol Min Max Unit Notes V isandedicatedpinandshould DDA Supply voltage VDDA 2.7 3.3 V be tied to VDDon the PCB with proper decoupling. Input range VADIN 0 VDDA V VADIN≤ VDDA Resolution BAD 10 10 bits Includes quantization. Absolute accuracy AAD — ±1.5 LSB ±0.5 LSB =±1 ADC step. ADC internal clock fADIC 500k 1.048M Hz tADIC = 1/fADIC Conversion range RAD VREFL VREFH V ADC voltage reference high VREFH — VDDA+ 0.1 V ADC voltage reference low VREFL VSSA– 0.1 — V t Conversion time tADC 16 17 ADIC cycles t Sample time tADS 5 — ADIC cycles Monotonicity MAD Guaranteed Zero input reading ZADI 000 001 HEX VADIN = VREFL Full-scale reading FADI 3FD 3FF HEX VADIN = VREFH Input capacitance CADI — 20 pF Not tested. Input impedance RADI 20M — Ω VREFH/VREFL IVREF — 1.6 mA Not tested. 1. V = 2.7 to 3.3 Vdc, V = 0 Vdc, T = T to T , unless otherwise noted. DD SS A L H MC68HC908AP Family Data Sheet, Rev. 4 306 Freescale Semiconductor

MMIIC Electrical Characteristics 22.13 MMIIC Electrical Characteristics Table 22-12. MMIIC DC Electrical Characteristics Characteristic(1) Symbol Min Typ Max Unit Comments Input low VIL –0.5 — 0.8 V Data, clock input low. Input high VIH 2.1 — 5.5 V Data, clock input high. Data, clock output low; Output low VOL — — 0.4 V @I PULLUP,MAX Input leakage ILEAK — — ±5 µA Input leakage current Current through pull-up resistor Pullup current IPULLUP 100 — 350 µA or current source. See note.(2) 1. V = 2.7 to 5.5Vdc, V = 0 Vdc, T = T to T , unless otherwise noted. DD SS A L H 2.TheI (max)specificationisdeterminedprimarilybytheneedtoaccommodateamaximumof1.1kΩequivalentse- PULLUP ries resistor of removable SMBus devices, such as the smart battery, while maintaining the V (max) of the bus. OL SDA SCL t t t t t t t HD.STA LOW HIGH SU.DAT HD.DAT SU.STA SU.STO Figure 22-2. MMIIC Signal Timings See Table 22-13 for MMIIC timing parameters. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 307

Electrical Specifications Table 22-13. MMIIC Interface Input/Output Signal Timing Characteristic Symbol Min Typ Max Unit Comments Operating frequency fSMB 10 — 100 kHz MMIIC operating frequency Bus free time between STOP and Bus free time tBUF 4.7 — — µs START condition Hold time after (repeated) START Repeated start hold time. tHD.STA 4.0 — — µs condition. After this period, the first clock is generated. Repeated start setup time. tSU.STA 4.7 — — µs Repeated START condition setup time. Stop setup time tSU.STO 4.0 — — µs Stop condition setup time. Hold time tHD.DAT 300 — — ns Data hold time. Setup time tSU.DAT 250 — — ns Data setup time. Clock low time-out tTIMEOUT 25 — 35 ms Clock low time-out.(1) Clock low tLOW 4.7 — — µs Clock low period Clock high tHIGH 4.0 — — µs Clock high period.(2) Cumulativeclocklowextendtime(slave Slave clock low extend time tLOW.SEXT — — 25 ms device)(3) Cumulative clock low extend time Master clock low extend time tLOW.MEXT — — 10 ms (master device)(4) Fall time tF — — 300 ns Clock/Data Fall Time(5) Rise time tR — — 1000 ns Clock/Data Rise Time(5) 1.DevicesparticipatinginatransferwilltimeoutwhenanyclocklowexceedsthevalueofT min.of25ms.Devices TIMEOUT thathavedetectedatimeoutconditionmustresetthecommunicationnolaterthanT maxof35ms.Themaximum TIMEOUT valuespecifiedmustbeadheredtobybothamasterandaslaveasitincorporatesthecumulativelimitforbothamaster (10 ms) and a slave (25 ms). Software should turn-off the MMIIC module to release the SDA and SCL lines. 2. T provides a simple guaranteed method for devices to detect the idle conditions. HIGH MAX 3.T isthecumulativetimeaslavedeviceisallowedtoextendtheclockcyclesinonemessagefromtheinitialstart LOW.SEXT to the stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 4.T isthecumulativetimeamasterdeviceisallowedtoextenditsclockcycleswithineachbyteofamessageas LOW.MEXT defined from start-to-ack, ack-to-ack, or ack-to-stop. 5. Rise and fall time is defined as follows: T = (V – 0.15) to (V + 0.15), T = 0.9×V to (V – 0.15). R ILMAX IHMIN F DD ILMAX MC68HC908AP Family Data Sheet, Rev. 4 308 Freescale Semiconductor

CGM Electrical Specification 22.14 CGM Electrical Specification Table 22-14. CGM Electrical Specifications Characteristic Symbol Min Typ Max Unit Reference frequency fRDV 30 32.768 100 kHz Range nominal multiplies fNOM — 125 — kHz VCO center-of-range frequency fVRS 125k — 40M Hz VCO range linear range multiplier L 1 — 255 VCO power-of-two-range multiplier 2E 1 — 4 VCO multiply factor N 1 — 4095 VCO prescale multiplier 2P 1 — 8 Reference divider factor R 1 1 15 VCO operating frequency fVCLK 125k — 40M Hz Manual acquisition time tLOCK — — 50 ms Automatic lock time tLOCK — — 50 ms f × RCLK PLL jitter(1) fJ 0 — 0.025% ×2P Hz N/4 1. Deviation of average bus frequency over 2ms. N = VCO multiplier. MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 309

Electrical Specifications 22.15 5V SPI Characteristics Table 22-15. SPI Characteristics (5V) Diagram Characteristic(2) Symbol Min Max Unit Number(1) Operating frequency Master fOP(M) fOP/128 fOP/2 MHz Slave fOP(S) dc fOP MHz Cycle time 1 Master tCYC(M) 2 128 tCYC Slave t 1 — t CYC(S) CYC 2 Enable lead time tLead(S) 1 — tCYC 3 Enablelag time tLag(S) 1 — tCYC Clock (SPSCK)high time 4 Master tSCKH(M) tCYC –25 64 tCYC ns Slave tSCKH(S) 1/2 tCYC –25 — ns Clock (SPSCK) low time 5 Master tSCKL(M) tCYC –25 64 tCYC ns Slave tSCKL(S) 1/2 tCYC –25 — ns Datasetup time (inputs) 6 Master tSU(M) 30 — ns Slave t 30 — ns SU(S) Datahold time (inputs) 7 Master tH(M) 30 — ns Slave t 30 — ns H(S) Accesstime, slave(3) 8 CPHA = 0 tA(CP0) 0 40 ns CPHA = 1 tA(CP1) 0 40 ns 9 Disable time, slave(4) tDIS(S) — 40 ns Datavalid time, after enable edge 10 Master tV(M) — 50 ns Slave(5) tV(S) — 50 ns Data hold time, outputs, after enable edge 11 Master tHO(M) 0 — ns Slave t 0 — ns HO(S) 1. Numbers refer to dimensions inFigure22-3 andFigure22-4. 2. All timing is shown with respect to 20% V and 70% V , unless noted; 100 pF load on all SPI pins. DD DD 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins MC68HC908AP Family Data Sheet, Rev. 4 310 Freescale Semiconductor

3V SPI Characteristics 22.16 3V SPI Characteristics Table 22-16. SPI Characteristics (3V) Diagram Characteristic(2) Symbol Min Max Unit Number(1) Operating frequency Master fOP(M) fOP/128 fOP/2 MHz Slave fOP(S) dc fOP MHz Cycle time 1 Master tCYC(M) 2 128 tCYC Slave t 1 — t CYC(S) CYC 2 Enable lead time tLead(S) 1 — tCYC 3 Enablelag time tLag(S) 1 — tCYC Clock (SPSCK)high time 4 Master tSCKH(M) tCYC –25 64 tCYC ns Slave tSCKH(S) 1/2 tCYC –25 — ns Clock (SPSCK) low time 5 Master tSCKL(M) tCYC –25 64 tCYC ns Slave tSCKL(S) 1/2 tCYC –25 — ns Datasetup time (inputs) 6 Master tSU(M) 40 — ns Slave t 40 — ns SU(S) Datahold time (inputs) 7 Master tH(M) 40 — ns Slave t 40 — ns H(S) Accesstime, slave(3) 8 CPHA = 0 tA(CP0) 0 50 ns CPHA = 1 tA(CP1) 0 50 ns 9 Disable time, slave(4) tDIS(S) — 50 ns Datavalid time, after enable edge 10 Master tV(M) — 60 ns Slave(5) tV(S) — 60 ns Data hold time, outputs, after enable edge 11 Master tHO(M) 0 — ns Slave t 0 — ns HO(S) 1. Numbers refer to dimensions inFigure22-3 andFigure22-4. 2. All timing is shown with respect to 20% V and 70% V , unless noted; 100 pF load on all SPI pins. DD DD 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 311

Electrical Specifications SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT 5 NOTE CPOL = 0 4 SPSCK OUTPUT 5 NOTE CPOL = 1 4 6 7 MISO MSB IN BITS 6–1 LSB IN INPUT 11 10 11 MOSI MASTER MSB OUT BITS 6–1 MASTER LSB OUT OUTPUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin. a) SPI Master Timing (CPHA = 0) SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT 5 CPOL = 0 NOTE 4 SPSCK OUTPUT 5 CPOL = 1 NOTE 4 6 7 MISO INPUT MSB IN BITS 6–1 LSB IN 10 11 10 MOSI OUTPUT MASTER MSB OUT BITS 6–1 MASTER LSB OUT Note: This last clock edge is generated internally, but is not seen at the SPSCK pin. b) SPI Master Timing (CPHA = 1) Figure 22-3. SPI Master Timing MC68HC908AP Family Data Sheet, Rev. 4 312 Freescale Semiconductor

3V SPI Characteristics SS INPUT 1 3 SPSCK INPUT 55 CPOL = 0 4 2 SPSCK INPUT 5 CPOL = 1 4 8 9 MISO INPUT SLAVE MSB OUT BITS 6–1 SLAVE LSB OUT NOTE 6 7 10 11 11 MOSI OUTPUT MSB IN BITS 6–1 LSB IN Note: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPSCK INPUT 5 CPOL = 0 4 2 3 SPSCK INPUT 5 CPOL = 1 4 8 10 9 MISO OUTPUT NOTE SLAVE MSB OUT BITS 6–1 SLAVE LSB OUT 6 7 10 11 MOSI INPUT MSB IN BITS 6–1 LSB IN Note: Not defined but normally LSB of character previously transmitted b) SPI Slave Timing (CPHA = 1) Figure 22-4. SPI Slave Timing MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 313

Electrical Specifications 22.17 Memory Characteristics Table 22-17. Memory Characteristics Characteristic Symbol Min. Max. Unit Data retention voltage VRDR 1.3 — V Number of rows per page 8 Rows Number of bytes per page 512 Bytes Read bus clock frequency f (1) 32k 8M Hz read Page erase time t (2) 20 — ms erase Mass erase time t (3) 200 — ms me PGM/ERASE to HVEN setup time tnvs 5 — µs High-voltage hold time tnvh 5 — µs High-voltage hold time (mass erase) tnvh1 100 — µs Program hold time tpgs 10 — µs Program time tprog 20 40 µs Address/data setup time tads 20 — ns Address/data hold time tadh — 30 ns Recovery time t (4) 1 — µs rcv Cumulative HV period t (5) — 8 ms hv Row erase endurance(6) — 10k — Cycles Row program endurance(7) — 10k — Cycles Data retention time(8) — 10 — Years 1. f is defined as the frequency range for which the FLASH memory can be read. read 2.Ifthepageerasetimeislongerthant (Min.),thereisnoerase-disturb,butitreducestheenduranceoftheFLASH erase memory. 3. If the mass erase time is longer than t (Min.), there is no erase-disturb, but it reduces the endurance of the FLASH me memory. 4.ItisdefinedasthetimeitneedsbeforetheFLASHcanbereadafterturningoffthehighvoltagechargepump,byclearing HVEN to logic 0. 5.t isthecumulativehighvoltageprogrammingtimetothesamerowbeforenexterase,andthesameaddresscannotbe hv programmed twice before next erase. 6.TheminimumrowendurancevaluespecifieseachrowoftheFLASHmemoryisguaranteedtoworkforatleastthismany erase/program cycles. 7.TheminimumrowendurancevaluespecifieseachrowoftheFLASHmemoryisguaranteedtoworkforatleastthismany erase/program cycle. 8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. MC68HC908AP Family Data Sheet, Rev. 4 314 Freescale Semiconductor

Chapter 23 Mechanical Specifications 23.1 Introduction This section gives the dimensions for: • 48-pin plastic low-profile quad flat pack (case #932) • 44-pin plastic quad flat pack (case #824A) • 42-pin shrink dual in-line package (case #858) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 315

Mechanical Specifications 23.2 48-Pin Low-Profile Quad Flat Pack (LQFP) 4X NOTES: 0.200 AB T–U Z 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. DETAIL Y 2. CONTROLLING DIMENSION: MILLIMETER. 9 A P 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD A1 WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 48 37 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT 1 36 SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD T U PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE B V DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL AE AE NOT CAUSE THE D DIMENSION TO EXCEED B1 V1 0.350. 12 25 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 13 24 MILLIMETERS Z DIM MIN MAX A 7.000 BSC S1 A1 3.500 BSC T, U, Z B 7.000 BSC B1 3.500 BSC S C 1.400 1.600 DETAIL Y D 0.170 0.270 4X E 1.350 1.450 0.200 AC T–U Z F 0.170 0.230 G 0.500 BSC H 0.050 0.150 J 0.090 0.200 K 0.500 0.700 L 1° 5° AB G 0.080 AC M 12° REF N 0.090 0.160 P 0.250 BSC R 0.150 0.250 S 9.000 BSC S1 4.500 BSC V 9.000 BSC AD V1 4.500 BSC AC W 0.200 REF AA 1.000 REF BASE METAL M° TOP & BOTTOM R E N N J 0 LA 5 P 0.2 UGE C E GA F D 0.080 M AC T–U Z SECTION AE–AE H W L° DETAIL AD K AA Figure 23-1. 48-Pin LQFP (Case #932) MC68HC908AP Family Data Sheet, Rev. 4 316 Freescale Semiconductor

44-Pin Quad Flat Pack (QFP) 23.3 44-Pin Quad Flat Pack (QFP) B L B 33 23 34 22 –A–, –B–, –D– S S D D DETAIL A S S B B – – –A– –B– A A F H B C L B M A– V M BASE METAL 8) 2) 8) 0 0 0 0 0 0 0 (0. 5 (0. 0 (0. J N DETAIL A 0.2 0.0 0.2 D 44 12 0.20 (0.008) M C A–B S D S 1 11 SECTION B–B VIEW ROTATED 90° NOTES: –D– 1.DIMENSIONING AND TOLERANCING PER ANSI A Y14.5M, 1982. 2.CONTROLLING DIMENSION: MILLIMETER. 0.20 (0.008) M H A–B S D S 3.DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE 0.05 (0.002) A–B THE LEAD EXITS THE PLASTIC BODY AT THE S BOTTOM OF THE PARTING LINE. 4.DATUMS –A–, –B– AND –D– TO BE DETERMINED AT 0.20 (0.008) M C A–B S D S DATUM PLANE –H–. 5.DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –C–. 6.DIMENSIONS A AND B DO NOT INCLUDE MOLD M DETAIL C PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. C E –H– DATUM 7.PDRIMOETNRSUIOSINO ND. DAOLELOS WNAOBTL IEN CDLAUMDBEA RD APMRBOATRRUSION PLANE SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –C– 0.10 (0.004) DAMBAR CANNOT BE LOCATED ON THE LOWER SEATING H RADIUS OR THE FOOT. PLANE G M MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.90 10.10 0.390 0.398 B 9.90 10.10 0.390 0.398 M C 2.10 2.45 0.083 0.096 D 0.30 0.45 0.012 0.018 E 2.00 2.10 0.079 0.083 T F 0.30 0.40 0.012 0.016 G 0.80 BSC 0.031 BSC H — 0.25 — 0.010 DPLAATUNME –H– R J 0.13 0.23 0.005 0.009 K 0.65 0.95 0.026 0.037 L 8.00 REF 0.315 REF M 5° 10° 5° 10° K N 0.13 0.17 0.005 0.007 Q Q 0° 7° 0° 7° W R 0.13 0.30 0.005 0.012 X S 12.95 13.45 0.510 0.530 T 0.13 — 0.005 — U 0° — 0° — V 12.95 13.45 0.510 0.530 DETAIL C W 0.40 — 0.016 — X 1.6 REF 0.063 REF Figure 23-2. 44-Pin QFP (Case #824A) MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 317

Mechanical Specifications 23.4 42-Pin Shrink Dual In-Line Package (SDIP) –A– NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 42 22 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD –B– FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). INCHES MILLIMETERS 1 21 DIM MIN MAX MIN MAX L A 1.435 1.465 36.45 37.21 B 0.540 0.560 13.72 14.22 H C 0.155 0.200 3.94 5.08 C D 0.014 0.022 0.36 0.56 F 0.032 0.046 0.81 1.17 G 0.070 BSC 1.778 BSC H 0.300 BSC 7.62 BSC –T– J 0.008 0.015 0.20 0.38 SEATING K 0.115 0.135 2.92 3.43 PLANE N L 0.600 BSC 15.24 BSC F G M M 0° 15° 0° 15° D42 PL K J42 PL N 0.020 0.040 0.51 1.02 0.25 (0.010) M T A S 0.25 (0.010) M T B S Figure 23-3. 42-Pin SDIP (Case #858) MC68HC908AP Family Data Sheet, Rev. 4 318 Freescale Semiconductor

Chapter 24 Ordering Information 24.1 Introduction This section contains device ordering numbers. 24.2 MC Order Numbers Table 24-1. MC Order Numbers RAM Size FLASH Size Operating MC Order Number Package (bytes) (bytes) Temperature Range MC68HC908AP64CB 2,048 62,368 42-pin SDIP –40 to +85°C MC68HC908AP64CFB 2,048 62,368 44-pin QFP –40 to +85°C MC68HC908AP64CFA 2,048 62,368 48-pin LQFP –40 to +85°C MC68HC908AP32CB 2,048 32,768 42-pin SDIP –40 to +85°C MC68HC908AP32CFB 2,048 32,768 44-pin QFP –40 to +85°C MC68HC908AP32CFA 2,048 32,768 48-pin LQFP –40 to +85°C MC68HC908AP16CB 1,024 16,384 42-pin SDIP –40 to +85°C MC68HC908AP16CFB 1,024 16,384 44-pin QFP –40 to +85°C MC68HC908AP16CFA 1,024 16,384 48-pin LQFP –40 to +85°C MC68HC908AP8CB 1,024 8,192 42-pin SDIP –40 to +85°C MC68HC908AP8CFB 1,024 8,192 44-pin QFP –40 to +85°C MC68HC908AP8CFA 1,024 8,192 48-pin LQFP –40 to +85°C MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor 319

Ordering Information MC68HC908AP Family Data Sheet, Rev. 4 320 Freescale Semiconductor

None

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