MC74VHCT50A Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs The MC74VHCT50A is a hex noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation http://onsemi.com similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output. The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection 14−LEAD SOIC 14−LEAD TSSOP circuitry on this device allows overvoltage tolerance on the input, D SUFFIX DT SUFFIX CASE 751A CASE 948G allowing the device to be used as a logic−level translator from 3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high−voltage power supply. The MC74VHCT50A input structure provides protection when PIN CONNECTION AND voltages up to 7 V are applied, regardless of the supply voltage. This MARKING DIAGRAM (Top View) allows the MC74VHCT50A to be used to interface 5 V circuits to 3 V VCC A6 Y6 A5 Y5 A4 Y4 circuits. The output structures also provide protection when 14 13 12 11 10 9 8 V = 0 V. These input and output structures help prevent device CC destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. Features • High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V 1 2 3 4 5 6 7 • Low Power Dissipation: ICC = 2 (cid:2)A (Max) at TA = 25°C A1 Y1 A2 Y2 A3 Y3 GND • TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V IL IH For detailed package marking information, see the Marking • CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load Diagram section on page 4 of this data sheet. OH CC OL CC • Power Down Protection Provided on Inputs and Outputs • FUNCTION TABLE NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 A Input Y Output Qualified and PPAP Capable • L L These Devices are Pb−Free and are RoHS Compliant H H LOGIC DIAGRAM LOGIC SYMBOL 1 2 A1 Y1 ORDERING INFORMATION 1 A1 Y1 See detailed ordering and shipping information in the package 3 4 dimensions section on page 4 of this data sheet. A2 Y2 1 A2 Y2 5 6 A3 Y3 A3 1 Y3 Y = A 1 9 8 A4 Y4 A4 Y4 1 A5 Y5 11 10 A5 Y5 1 A6 Y6 13 12 A6 Y6 © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: March, 2014 − Rev. 9 MC74VHCT50A/D

MC74VHCT50A MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (cid:2)0.5 to (cid:3)7.0 V VIN DC Input Voltage (cid:2)0.5 (cid:4) VI (cid:4) (cid:3)7.0 V VOUT DC Output Voltage Output in HIGH or LOW State (cid:2)0.5 (cid:4) VO (cid:4) (cid:3)7.0 V IIK DC Input Diode Current (cid:2)20 mA IOK DC Output Diode Current (cid:5)20 mA IO DC Output Source/Sink Current (cid:5)25 mA ICC DC Supply Current per Supply Pin (cid:5)50 mA IGND DC Ground Current per Ground Pin (cid:5)50 mA TSTG Storage Temperature Range (cid:2)65 to (cid:3)150 (cid:2)C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 (cid:2)C TJ Junction Temperature under Bias (cid:3)150 (cid:2)C (cid:3)JA Thermal Resistance (Note 1) (cid:2)C/W SOIC 125 TSSOP 170 PD Power Dissipation in Still Air mW SOIC 500 TSSOP 450 VESD ESD Withstand Voltage Human Body Model (Note 2) > 2000 V Machine Model (Note 3) > 200 Charged Device Model (Note 4) 2000 ILatch−Up Latch−Up Performance Above VCC and Below GND at 85(cid:2)C (Note 5) (cid:5)300 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit DC Supply Voltage VCC 2.0 5.5 V DC Input Voltage VIN 0.0 5.5 V DC Output Voltage VCC = 0 VOUT 0.0 5.5 V High or Low State 0.0 VCC Operating Temperature Range TA −55 +125 °C Input Rise and Fall Time VCC = 3.3 V ± 0.3 V tr , tf 0 100 ns/V VCC = 5.0 V ± 0.5 V 0 20 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. TEST POINT 3.0V OUTPUT 50% A GND DEVICE UNDER tPLH tPHL TEST CL* VOH Y 50% VCC VOL *Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit http://onsemi.com 2

MC74VHCT50A DC ELECTRICAL CHARACTERISTICS VCC TA = 25°C TA ≤ 85°C TA ≤ 125°C Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit VIH Minimum High−Level 3.0 1.2 1.2 1.2 V Input Voltage 4.5 2.0 2.0 2.0 5.5 2.0 2.0 2.0 VIL Maximum Low−Level 3.0 0.53 0.53 0.53 V Input Voltage 4.5 0.8 0.8 0.8 5.5 0.8 0.8 0.8 VOH Minimum High−Level VIN = VIH or VIL 3.0 2.9 3.0 2.9 2.9 V Output Voltage IOH = −50 (cid:2)A 4.5 4.4 4.5 4.4 4.4 VIN = VIH or VIL VIN = VIH or VIL V IOH = −4 mA 3.0 2.58 2.48 2.34 IOH = −8 mA 4.5 3.94 3.80 3.66 VOL Maximum Low−Level VIN = VIH or VIL 3.0 0.0 0.1 0.1 0.1 V Output Voltage IOL = 50 (cid:2)A 4.5 0.0 0.1 0.1 0.1 VIN = VIH or VIL VIN = VIH or VIL V IOH = −4 mA 3.0 0.36 0.44 0.52 IOL = 8 mA 4.5 0.36 0.44 0.52 IIN Maximum Input VIN = 5.5 V or GND 0 to ±0.1 ±1.0 ±1.0 μA Leakage Current 5.5 ICC Maximum Quiescent VIN = VCC or GND 5.5 2.0 20 40 μA Supply Current ICCT Quiescent Supply Input: VIN = 3.4 V 5.5 1.35 1.50 1.65 mA Current IOFF Output Leakage VOUT = 5.5 V 0.0 0.5 5.0 10 μA Current Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎAÎC EÎLEÎCTRÎICAÎL CÎHAÎRACÎTEÎRISÎTICÎS (CÎload Î= 50Î pF, ÎInpuÎt tr =Î tf = Î3.0nÎs) ÎÎÎÎÎÎÎÎÎÎÎÎÎ TA = 25°C TA ≤ 85°C TA ≤ 125°C Symbol Parameter Test Conditions Min Typ Max Min Max Min Max Unit tPLH, Maximum VCC = 3.3 ± 0.3 V CL = 15 pF 5.5 7.9 1.0 9.5 ns tPHL Propogation Delay, CL = 50 pF 8.0 11.4 1.0 13.0 Input A to Y VCC = 5.0 ± 0.5 V CL = 15 pF 6.2 7.5 8.5 9.5 CL = 50 pF 7.0 8.5 9.5 10.5 CIN Maximum Input 5 10 10 10 pF Capacitance Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Note 6) 15 pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD (cid:2) VCC (cid:2) fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD (cid:2) VCC2 (cid:2) fin + ICC (cid:2) VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V) TA = 25°C Symbol Characteristic Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.8 1.0 V VOLV Quiet Output Minimum Dynamic VOL −0.8 −1.0 V VIHD Minimum High Level Dynamic Input Voltage 2.0 V VILD Maximum Low Level Dynamic Input Voltage 0.8 V http://onsemi.com 3

MC74VHCT50A ORDERING INFORMATION Device Package Shipping† MC74VHCT50ADR2G SOIC−14 2500 / Tape & Reel (Pb−Free) MC74VHCT50ADTR2G TSSOP−14 2500 / Tape & Reel NLVVHCT50ADTR2G* (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. MARKING DIAGRAMS (Top View) 14 13 12 11 10 9 8 14 13 12 11 10 9 8 VHCT VHCT50AG 50A AWLYWW* ALYW(cid:3) (cid:3) 1 2 3 4 5 6 7 1 2 3 4 5 6 7 14−LEAD SOIC 14−LEAD TSSOP D SUFFIX DT SUFFIX CASE 751A CASE 948G A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or (cid:3) = Pb−Free Package *See Applications Note #AND8004/D for date code and traceability information. http://onsemi.com 4

MC74VHCT50A PACKAGE DIMENSIONS SOIC−14 NB D SUFFIX CASE 751A−03 ISSUE K D A NOTES: B 1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.CONTROLLING DIMENSION: MILLIMETERS. 14 8 3.DIMENSION b DOES NOT INCLUDE DAMBAR A3 PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. H E 4.DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. L 5.MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 1 7 DETAIL A MILLIMETERS INCHES 0.25 M B M 13Xb DIM MIN MAX MIN MAX A 1.35 1.75 0.054 0.068 0.25 M C A S B S A1 0.10 0.25 0.004 0.010 A3 0.19 0.25 0.008 0.010 DETAIL A b 0.35 0.49 0.014 0.019 h A X 45(cid:2) DE 83..5850 84..7050 00..135307 00..135474 e 1.27 BSC 0.050 BSC H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 e A1 C SEATING M ML 0.04 0(cid:2) 1.72 5(cid:2) 0.010 6(cid:2) 0.047 9(cid:2) PLANE SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5

MC74VHCT50A PACKAGE DIMENSIONS TSSOP−14 CASE 948G ISSUE B 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER 0.10 (0.004) M T U S V S ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. N MOLD FLASH OR GATE BURRS SHALL NOT 0.25 (0.010) EXCEED 0.15 (0.006) PER SIDE. 14 8 4. DIMENSION B DOES NOT INCLUDE 2XL/2 INTERLEAD FLASH OR PROTRUSION. M INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. L B 5. DIMENSION K DOES NOT INCLUDE −U− N DAMBAR PROTRUSION. ALLOWABLE PIN 1 DAMBAR PROTRUSION SHALL BE 0.08 IDENT. F (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL 1 7 DETAIL E CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE 0.15 (0.006) T U S A K DETERMINED AT DATUM PLANE −W−. −V− K1 MILLIMETERS INCHES ÇÉÇÉÇÉ DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 J J1 ÇÉÇÉÇÉ B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 SECTION N−N F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 −W− J 0.09 0.20 0.004 0.008 C J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 0.10 (0.004) K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC −T− SEATING D G H DETAIL E M 0 (cid:2) 8 (cid:2) 0 (cid:2) 8 (cid:2) PLANE SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 14X 14X 0.36 1.26 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com MC74VHCT50A/D 6

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: MC74VHCT50ADR2G MC74VHCT50ADTR2G