MC74LCX573 Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout With 5 V−Tolerant Inputs and Outputs http://onsemi.com (3−State, Non−Inverting) MARKING The MC74LCX573 is a high performance, non−inverting octal DIAGRAMS transparent latch operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current 20 loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows LCX573 MC74LCX573 inputs to be safely driven from 5.0 V devices. AWLYYWWG SOIC−20 WB The MC74LCX573 contains 8 D−type latches with 3−state standard DW SUFFIX outputs. When the Latch Enable (LE) input is HIGH, data on the Dn CASE 751D 1 inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH−to−LOW transition LCX of LE. The 3−state standard outputs are controlled by the Output 573 Enable (OE) input. When OE is LOW, the standard outputs are TSSOP−20 ALYW(cid:2) (cid:2) enabled. When OE is HIGH, the standard outputs are in the high DT SUFFIX impedance state, but this does not interfere with new data entering into CASE 948E the latches. The LCX573 flow through design facilitates easy PC A = Assembly Location board layout. L, WL = Wafer Lot Y, YY = Year Features W, WW = Work Week • Designed for 2.3 to 3.6 V VCC Operation G or (cid:2) = Pb−Free Package • 5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic (Note: Microdot may be in either location) • Supports Live Insertion and Withdrawal • I Specification Guarantees High Impedance When V = 0 V OFF CC ORDERING INFORMATION • LVTTL Compatible See detailed ordering and shipping information in the package • dimensions section on page 3 of this data sheet. LVCMOS Compatible • 24 mA Balanced Output Sink and Source Capability • Near Zero Static Supply Current in All Three Logic States (10 (cid:2)A) Substantially Reduces System Power Requirements • Latchup Performance Exceeds 500 mA • ESD Performance: ♦ Human Body Model >2000 V ♦ Machine Model >200 V • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: January, 2013 − Rev. 12 MC74LCX573/D

MC74LCX573 1 OE 11 LE LE 19 2 Q O0 D0 D VCC O0 O1 O2 O3 O4 O5 O6 O7 LE 20 19 18 17 16 15 14 13 12 11 LE 18 3 Q O1 D1 D LE 17 4 Q O2 D2 D 1 2 3 4 5 6 7 8 9 10 OE D0 D1 D2 D3 D4 D5 D6 D7 GND LE 16 5 Q O3 Figure 1. Pinout (Top View) D3 D LE 15 PIN NAMES 6 Q O4 D4 D Pins Function OE Output Enable Input LE 14 LE Latch Enable Input 7 Q O5 D5 D D0−D7 Data Inputs O0−O7 3−State Latch Outputs LE 13 8 Q O6 D6 D LE 12 9 Q O7 D7 D Figure 2. Logic Diagram TRUTH TABLE Inputs Outputs OE LE Dn On Operating Mode L H H H Transparent (Latch Disabled); Read Latch L H L L L L h H Latched (Latch Enabled) Read Latch L L l L L L X NC Hold; Read Latch H L X Z Hold; Disabled Outputs H H H Z Transparent (Latch Disabled); Disabled Outputs H H L Z H L h Z Latched (Latch Enabled); Disabled Outputs H L l Z H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition L = Low Voltage Level l = Low Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition NC = No Change, State Prior to the Latch Enable High−to−Low Transition X = High or Low Voltage Level or Transitions are Acceptable Z = High Impedance State For ICC Reasons DO NOT FLOAT Inputs http://onsemi.com 2

MC74LCX573 MAXIMUM RATINGS Symbol Parameter Value Condition Units VCC DC Supply Voltage −0.5 to +7.0 V VI DC Input Voltage −0.5 ≤ VI ≤ +7.0 V VO DC Output Voltage −0.5 ≤ VO ≤ +7.0 Output in 3−State V −0.5 ≤ VO ≤ VCC + 0.5 Output in HIGH or LOW State (Note 1) V IIK DC Input Diode Current −50 VI< GND mA IOK DC Output Diode Current −50 VO < GND mA +50 VO > VCC mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range −65 to +150 °C MSL Moisture Sensitivity Level 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Units VCC Supply Voltage V Operating 2.0 2.5, 3.3 3.6 Data Retention Only 1.5 2.5, 3.3 3.6 VI Input Voltage 0 5.5 V VO Output Voltage V (HIGH or LOW State) 0 VCC (3−State) 0 5.5 IOH HIGH Level Output Current mA VCC = 3.0 V − 3.6 V −24 VCC = 2.7 V − 3.0 V −12 VCC = 2.3 V − 2.7 V −8 IOL LOW Level Output Current mA VCC = 3.0 V − 3.6 V +24 VCC = 2.7 V − 3.0 V +12 VCC = 2.3 V − 2.7 V +8 TA Operating Free−Air Temperature −55 +125 °C (cid:3)t/(cid:3)V Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V 0 10 ns/V ORDERING INFORMATION Device Package Shipping† MC74LCX573DWG SOIC−20 38 Units / Rail (Pb−Free) MC74LCX573DWR2G SOIC−20 1000 Tape & Reel (Pb−Free) MC74LCX573DTG TSSOP−20 75 Units / Rail (Pb−Free) MC74LCX573DTR2G TSSOP−20 2500 Tape & Reel (Pb−Free) NLV74LCX573DTR2G* TSSOP−20 2500 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 3

MC74LCX573 DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C TA = −55°C to +125°C Symbol Characteristic Condition Min Max Min Max Units VIH HIGH Level Input 2.3 V ≤ VCC ≤ 2.7 V 1.7 1.7 V Voltage (Note 2) 2.7 V ≤ VCC ≤ 3.6 V 2.0 2.0 VIL LOW Level Input 2.3 V ≤ VCC ≤ 2.7 V 0.7 0.7 V Voltage (Note 2) 2.7 V ≤ VCC ≤ 3.6 V 0.8 0.8 VOH HIGH Level Out- 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 (cid:2)A VCC−0.2 VCC−0.2 V put Voltage VCC = 2.3 V; IOH = −8 mA 1.8 1.8 VCC = 2.7 V; IOH = −12 mA 2.2 2.2 VCC = 3.0 V; IOH = −18 mA 2.4 2.4 VCC = 3.0 V; IOH = −24 mA 2.2 2.2 VOL LOW Level Out- 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 (cid:2)A 0.2 0.2 V put Voltage VCC = 2.3 V; IOL = 8 mA 0.6 0.6 VCC = 2.7 V; IOL = 12 mA 0.4 0.4 VCC = 3.0 V; IOL = 16 mA 0.4 0.4 VCC = 3.0 V; IOL = 24 mA 0.55 0.60 IOZ 3−State Output VCC = 3.6 V, VIN = VIH or VIL, ±5 ±5 (cid:2)A Current VOUT = 0 to 5.5 V IOFF Power Off Leak- VCC = 0, VIN = 5.5 V or VOUT = 5.5 V 10 10 (cid:2)A age Current IIN Input Leakage VCC = 3.6 V, VIN = 5.5 V or GND ±5 ±5 (cid:2)A Current ICC Quiescent Supply VCC = 3.6 V, VIN = 5.5 V or GND 10 10 (cid:2)A Current (cid:3)ICC Increase in ICC 2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 500 500 (cid:2)A per Input 2. These values of VI are used to test DC electrical characteristics only. AC CHARACTERISTICS tR = tF = 2.5 ns; RL = 500 (cid:4) Limits TA = −55°C to +125°C VCC = 3.3 V ± 0.3 V VCC = 2.7 V VCC = 2.5 V ± 0.2 V CL = 50 pF CL = 50 pF CL = 30 pF Symbol Parameter Waveform Min Max Min Max Min Max Units tPLH Propagation Delay 1 1.5 8.0 1.5 9.0 1.5 9.6 ns tPHL Dn to On 1.5 8.0 1.5 9.0 1.5 9.6 tPLH Propagation Delay 3 1.5 8.5 1.5 9.5 1.5 10.5 ns tPHL LE to On 1.5 8.5 1.5 9.5 1.5 10.5 tPZH Output Enable Time to HIGH 2 1.5 8.5 1.5 9.5 1.5 10.5 ns tPZL and LOW Level 1.5 8.5 1.5 9.5 1.5 10.5 tPHZ Output Disable Time From 2 1.5 6.5 1.5 7.0 1.5 7.8 ns tPLZ High and Low Level 1.5 6.5 1.5 7.0 1.5 7.8 ts Setup TIme, HIGH or LOW 3 2.5 2.5 4.0 Dn to LE th Hold TIme, HIGH or LOW 3 1.5 1.5 2.0 Dn to LE tw LE Pulse Width, HIGH 3 3.3 3.3 4.0 tOSHL Output−to−Output Skew 1.0 ns tOSLH (Note 3) 1.0 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 4

MC74LCX573 DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol Characteristic Condition Min Typ Max Units VOLP Dynamic LOW Peak Voltage VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V 0.8 V (Note 4) VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V 0.6 V VOLV Dynamic LOW Valley Voltage VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V −0.8 V (Note 4) VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V −0.6 V 4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. CAPACITIVE CHARACTERISTICS Symbol Parameter Condition Typical Units CIN Input Capacitance VCC = 3.3 V, VI = 0 V or VCC 7 pF CI/O Input/Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 8 pF CPD Power Dissipation Capacitance 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 25 pF VCC OE Vmi Vmi VCC 0 V Vmi Vmi tPZH tPHZ Dn VOH 0 V On Vmo VHZ tPLH tPHL VOH Vmo Vmo tPZL tPLZ On VOL On Vmo WAVEFORM 1 − PROPAGATION DELAYS VLZ tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns VOL WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns 2.7 V Dn 1.5 V 0 V VCC ts th Symbol 3.3 V ± 0.3 V 2.7 V 2.5 V ± 0.2 V 2.7 V LE 1.5 V tw 1.5 V Vmi 1.5 V 1.5 V VCC/2 Vmo 1.5 V 1.5 V VCC/2 0 V tPLH, tPHL VHZ VOL + 0.3 V VOL + 0.3 V VOL + 0.15 V VOH VLZ VOL − 0.3 V VOL − 0.3 V VOL − 0.15 V On 1.5 V VOL WAVEFORM 3 − LE to On PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted Figure 3. AC Waveforms http://onsemi.com 5

MC74LCX573 VCC 6 V OPEN PULSE DUT R1 GND GENERATOR RT CL RL Test Switch tPLH, tPHL Open tPZL, tPLZ 6 V at VCC = 3.3 ±0.3 V 6 V at VCC = 2.5 ±0.2 V Open Collector/Drain tPLH and tPHL 6 V tPZH, tPHZ GND CL= 50 pF at VCC = 3.3 ±0.3 V or equivalent (includes jig and probe capacitance) CL= 30 pF at VCC = 2.5 ±0.2 V or equivalent (includes jig and probe capacitance) RL= R1 = 500 (cid:4) or equivalent RT= ZOUT of pulse generator (typically 50 (cid:4)) Figure 4. Test Circuit http://onsemi.com 6

MC74LCX573 PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE G D A (cid:2) NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. M 20 11 2. INTERPRET DIMENSIONS AND TOLERANCES B PER ASME Y14.5M, 1994. (cid:3) 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD H M 45 PROTRUSION. 10X 0.25 E hX 45.. MDPRIAMOXEITMNRSUUIMOS INMO NOB .LD ADOL PELROSO WNTAORBTUL ISENI COPLNRU O0DT.1ER5 UD PSAEIMORBN SAIRDE. SHALL BE 0.13 TOTAL IN EXCESS OF B 1 10 DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS 20X B B DIM MIN MAX A 2.35 2.65 0.25 M T A S B S A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 12.65 12.95 E 7.40 7.60 A e 1.27 BSC H 10.05 10.55 L h 0.25 0.75 SEATING L 0.50 0.90 18X e A1 TPLANE C (cid:2) 0 (cid:3) 7 (cid:3) http://onsemi.com 7

MC74LCX573 PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE C 20X K REF K NOTES: 1. DIMENSIONING AND TOLERANCING PER 0.15 (0.006) T U S 0.10 (0.004) M T U S V S K1 ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. ÍÍÍÍ 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 20 11 J JÍ1 ÍÍÍ MOLD FLASH OR GATE BURRS SHALL NOT 2X L/2 EXCEED 0.15 (0.006) PER SIDE. ÍÍÍÍ 4. DIMENSION B DOES NOT INCLUDE B SECTION N−N INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL L −U− NOT EXCEED 0.25 (0.010) PER SIDE. PIN 1 5. DIMENSION K DOES NOT INCLUDE DAMBAR IDENT 0.25 (0.010) PROTRUSION. ALLOWABLE DAMBAR N PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN 1 10 EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. M 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 0.15 (0.006) T U S 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. A N MILLIMETERS INCHES −V− DIM MIN MAX MIN MAX F A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 DETAIL E C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 −W− G 0.65 BSC 0.026 BSC C H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 D G H K 0.19 0.30 0.007 0.012 DETAIL E K1 0.19 0.25 0.007 0.010 0.100 (0.004) ML 06 (cid:3).40 BSC8 (cid:3) 00 (cid:3).252 BSC8 (cid:3) −T− SEATING PLANE SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 16X 0.36 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8

MC74LCX573 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com MC74LCX573/D 9

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: MC74LCX573DTG MC74LCX573DTR2G MC74LCX573DWG MC74LCX573DWR2G