ÎÎÎÎÎÎÎÎÎÎ MC74HCT573A ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS http://onsemi.com The MC74HCT573A is identical in pinout to the LS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High−Speed CMOS inputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes SOIC−20 TSSOP−20 low, data meeting the setup and hold times becomes latched. DW SUFFIX DT SUFFIX The Output Enable input does not affect the state of the latches, but CASE 751D CASE 948E when Output Enable is high, all device outputs are forced to the high−impedance state. Thus, data may be latched even when the PIN ASSIGNMENT outputs are not enabled. OUTPUT The HCT573A is identical in function to the HCT373A but has the ENABLE 1 20 VCC Data Inputs on the opposite side of the package from the outputs to D0 2 19 Q0 D1 3 18 Q1 facilitate PC board layout. D2 4 17 Q2 D3 5 16 Q3 Features D4 6 15 Q4 • Output Drive Capability: 15 LSTTL Loads D5 7 14 Q5 • TTL/NMOS−Compatible Input Levels D6 8 13 Q6 • D7 9 12 Q7 Outputs Directly Interface to CMOS, NMOS and TTL GND 10 11 LATCH • Operating Voltage Range: 4.5 to 5.5 V ENABLE • Low Input Current: 10 (cid:2)A MARKING DIAGRAMS • In Compliance with the Requirements Defined by JEDEC Standard No. 7A 20 20 • Chip Complexity: 234 FETs or 58.5 Equivalent Gates HCT ♦ Improved Propagation Delays HCT573A 573A AWLYYWWG ALYW(cid:2) ♦ 50% Lower Quiescent Power (cid:2) • These Devices are Pb−Free and are RoHS Compliant 1 1 SOIC−20 TSSOP−20 LOGIC DIAGRAM A = Assembly Location WL, L = Wafer Lot 2 19 D0 Q0 YY, Y = Year 3 18 WW, W = Work Week D1 Q1 4 17 G or (cid:2) = Pb−Free Package D2 Q2 DATA D3 5 16 Q3 NONINVERTING (Note: Microdot may be in either location) INPUTS 6 15 OUTPUTS D4 Q4 ORDERING INFORMATION 7 14 D5 Q5 Device Package Shipping† 8 13 D6 Q6 MC74HCT573ADWR2G SOIC−20 1000 / 9 12 D7 Q7 (Pb−Free) Tape & Reel 11 MC74HCT573ADTR2G TSSOP−20 2500 / LATCH ENABLE (Pb−Free) Tape & Reel 1 PIN 20 = VCC OUTPUT ENABLE PIN 10 = GND †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: September, 2014 − Rev. 13 MC74HCT573A/D

MC74HCT573A FUNCTION TABLE Inputs Output Output Latch Enable Enable D Q L H H H L H L L L L X No Change H X X Z X = Don’t Care Z = High Impedance Design Criteria Value Units Internal Gate Count* 58.5 ea Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 (cid:2)W Speed Power Product 0.0075 pJ *Equivalent to a two−input NAND gate. MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protection circuitry to guard against damage VCC DC Supply Voltage (Referenced to GND) –0.5 to + 7.0 V due to high static voltages or electric Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V fields. However, precautions must be taken to avoid applications of any Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V voltage higher than maximum rated Iin DC Input Current, per Pin ±20 mA voltages to this high−impedance cir- Iout DC Output Current, per Pin ±25 mA cVuoiutt. Fshoor upldro pbeer coopnesrtartaioinne, dV tino athned ICC DC Supply Current, VCC and GND Pins ±50 mA range GND (cid:2) (Vin or Vout) (cid:2) VCC. Unused inputs must always be PD Power Dissipation in Still Air SOIC Package† 500 mW tied to an appropriate logic voltage TSSOP Package† 450 level (e.g., either GND or VCC). Tstg Storage Temperature –65 to +150 (cid:3)C Unused outputs must be left open. TL Lead Temperature, 1 mm from Case for 10 Seconds (cid:3)C (TSSOP or SOIC Package) 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/(cid:3)C from 65(cid:3) to 125(cid:3)C TSSOP Package: −6.1 mW/°C from 65(cid:3) to 125(cid:3)C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types –55 +125 (cid:3)C tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. http://onsemi.com 2

MC74HCT573A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC –55 to Symbol Parameter Test Conditions V 25(cid:3)C ≤ 85(cid:3)C ≤ 125(cid:3)C Unit VIH Minimum High−Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 2.0 2.0 2.0 V Voltage |Iout| ≤ 20 (cid:2)A 5.5 2.0 2.0 2.0 VIL Maximum Low−Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 0.8 0.8 0.8 V Voltage |Iout| ≤ 20 (cid:2)A 5.5 0.8 0.8 0.8 VOH Minimum High−Level Output Vin = VIH or VIL 4.5 4.4 4.4 4.4 V Voltage |Iout| ≤ 20 (cid:2)A 5.5 5.4 5.4 5.4 Vin = VIH or VIL |Iout| ≤ 6.0 mA 4.5 3.98 3.84 3.7 VOL Maximum Low−Level Output Vin = VIH or VIL 4.5 0.1 0.1 0.1 V Voltage |Iout| ≤ 20 (cid:2)A 5.5 0.1 0.1 0.1 Vin = VIH or VIL |Iout| ≤ 6.0 mA 4.5 0.26 0.33 0.4 Iin Maximum Input Leakage Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 (cid:2)A Current IOZ Maximum Three−State Output in High−Impedance State 5.5 ±0.5 ±5.0 ±10 (cid:2)A Leakage Current Vin = VIL or VIH Vout = VCC or GND ICC Maximum Quiescent Supply Vin = VCC or GND 5.5 4.0 40 160 (cid:2)A Current (per Package) Iout ≤ 0 (cid:2)A ΔICC Additional Quiescent Supply Vin = 2.4 V, Any One Input ≥ –55(cid:3)C 25(cid:3)C to 125(cid:3)C Current Vin = VCC or GND, Other Inputs lout = 0 (cid:2)A 5.5 2.9 2.4 mA AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit –55 to Symbol Parameter 25(cid:3)C ≤ 85(cid:3)C ≤ 125(cid:3)C Unit tPLH, Maximum Propagation Delay, Input D to Output Q 30 38 45 ns tPHL (Figures 1 and 5) tPLH Maximum Propagation Delay, Latch Enable to Q 30 38 45 ns tPHL (Figures 2 and 5) TPLZ, Maximum Propagation Delay, Output Enable to Q 28 35 42 ns TPHZ (Figures 3 and 6) tTZL, Maximum Propagation Delay, Output Enable to Q 28 35 42 ns tTZH (Figures 3 and 6) tTLH, Maximum Output Transition Time, any Output 12 15 18 ns tTHL (Figures 1 and 5) Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum Three−State Output Capacitance 15 15 15 pF (Output in High−Impedance State) Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Enabled Output)* 48 pF *Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎTÎIMIÎNGÎ REQÎUIÎREMÎENÎTS Î(VCCÎ = 5Î.0 V α10Î%, CÎL = 5Î0 pFÎ, InpÎut trÎ = tf Î= 6.0Î ns)ÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit –55 to 25(cid:3)C ≤ 85(cid:3)C ≤ 125(cid:3)C Symbol Parameter Fig. Min Max Min Max Min Max Unit tsu Minimum Setup Time, Input D to Latch Enable 4 10 13 15 ns th Minimum Hold Time, Latch Enable to Input D 4 5.0 5.0 5.0 ns tw Minimum Pulse Width, Latch Enable 2 15 19 22 ns tr, tf Maximum Input Rise and Fall Times 1 500 500 500 ns http://onsemi.com 3

MC74HCT573A SWITCHING WAVEFORMS 3.0 V LATCH tr tf ENABLE 1.3 V 3.0 V 2.7 V GND INPUT D 1.3 V 0.3 V GND tw tPLH tPHL 90% Q 1.3 V tPLH tPHL 10% tTLH tTHL Q 1.3 V Figure 1. Figure 2. OUTPUT 3.0 V ENABLE 1.3 V VALID 3.0 V GND tPZL tPLZ INPUT D 1.3 V HIGH GND Q 1.3 V IMPEDANCE tSU th 10% VOL 3.0 V tPZH tPHZ LATCH 1.3 V 90% VOH ENABLE GND Q 1.3 V HIGH IMPEDANCE Figure 3. Figure 4. TEST POINT EXPANDED LOGIC DIAGRAM 2 OUTPUT D0 D 19 Q Q0 DEVICE LE UNDER 3 TEST CL* D1 D Q 18Q1 LE 4 D2 D 17 Q Q2 LE *Includes all probe and jig capacitance 5 D3 D 16 Q Q3 Figure 5. Test Circuit LE 6 D4 D 15 Q Q4 LE 7 D5 D 14 TEST POINT Q Q5 LE OUTPUT 1 kΩ CTEOSNTNINEGCT tP TLOZ AVNCDC WtPZHLE.N D6 8 D Q 13Q6 DEVICE CONNECT TO GND WHEN LE UNDER TESTING tPHZ AND tPZH. 9 TEST CL* D7 D 12 Q Q7 LE 11 LATCH ENABLE *Includes all probe and jig capacitance 1 OUTPUT ENABLE Figure 6. Test Circuit http://onsemi.com 4

MC74HCT573A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE C NOTES: 20X K REF K 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 0.15 (0.006) T U S 0.10 (0.004) M T U S V S ÍÍKÍ1 Í 2. CONTROLLING DIMENSION: MILLIMETER. ÍÍÍÍ 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE 2X L/2 20 11 J JÍ1 ÍÍÍ BSHUARLRLS N. OMTO ELDXC FELEADS H0 .O15R ( G0.A0T06E) BPUERRR SSIDE. 4. DIMENSION B DOES NOT INCLUDE B SECTION N−N INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION L −U− SHALL NOT EXCEED 0.25 (0.010) PER SIDE. PIN 1 0.25 (0.010) 5. DIMENSION K DOES NOT INCLUDE IDENT N DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 1 10 (0.003) TOTAL IN EXCESS OF THE K M DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR 0.15 (0.006) T U S REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE A N DETERMINED AT DATUM PLANE −W−. −V− F MILLIMETERS INCHES DIM MIN MAX MIN MAX DETAIL E A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 −W− D 0.05 0.15 0.002 0.006 C F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC G H 0.27 0.37 0.011 0.015 D H J 0.09 0.20 0.004 0.008 DETAIL E J1 0.09 0.16 0.004 0.006 0.100 (0.004) K 0.19 0.30 0.007 0.012 −T− SPELAATNIENG KML1 00.61 (cid:3).940 BSC08.2 (cid:3)5 0.0000 (cid:3).2752 B0S.C081 (cid:3)0 SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 16X 0.36 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5

MC74HCT573A PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G D NOTES: A (cid:2) 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD 20 11 M PROTRUSION. B 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. (cid:3) 5. DIMENSION B DOES NOT INCLUDE DAMBAR H M 45 PROTRUSION. ALLOWABLE PROTRUSION 10X 0.25 E hX SDCHIOMANELDNLI STBIIOEO NN0.. 1A3T TMOATXAILM IUNM E MXCATEESRSI AOLF B 1 10 MILLIMETERS DIM MIN MAX A 2.35 2.65 B A1 0.10 0.25 20X B B 0.35 0.49 C 0.23 0.32 0.25 M T A S B S D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 A L 0.50 0.90 L (cid:2) 0 (cid:3) 7 (cid:3) SEATING 18X e A1 TPLANE C ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com MC74HCT573A/D 6