MC74HCT14A Hex Schmitt-Trigger Inverter with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS http://onsemi.com The MC74HCT14A may be used as a level converter for interfacing TTL or NMOS outputs to high−speed CMOS inputs. The HCT14A is useful to “square up” slow input rise and fall times. Due to the hysteresis voltage of the Schmitt trigger, the HCT14A finds applications in noisy environments. SOIC−14 NB TSSOP−14 D SUFFIX DT SUFFIX Features CASE 751A CASE 948G • Output Drive Capability: 10 LSTTL Loads PIN ASSIGNMENT • TTL/NMOS−Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL A1 1 14 VCC • Operating Voltage Range: 4.5 to 5.5 V Y1 2 13 A6 • Low Input Current: 1.0 (cid:2)A A2 3 12 Y6 • In Compliance With the JEDEC Standard No. 7.0 A Requirements Y2 4 11 A5 • Chip Complexity: 72 FETs or 18 Equivalent Gates A3 5 10 Y5 • NLV Prefix for Automotive and Other Applications Requiring Y3 6 9 A4 Unique Site and Control Change Requirements; AEC−Q100 GND 7 8 Y4 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free and are RoHS Compliant MARKING DIAGRAMS LOGIC DIAGRAM 14 14 HCT HCT14AG 14A 1 2 AWLYWW ALYW(cid:2) A1 Y1 (cid:2) 1 1 3 4 SOIC−14 NB TSSOP−14 A2 Y2 A = Assembly Location L, WL = Wafer Lot 5 6 A3 Y3 Y, YY = Year W, WW = Work Week G or (cid:2) = Pb−Free Package 9 8 (Note: Microdot may be in either location) A4 Y4 FUNCTION TABLE 11 10 A5 Y5 Input Output A Y 13 12 L H A6 Y6 H L Y = A PIN 14 = VCC ORDERING INFORMATION PIN 7 = GND See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: October, 2014 − Rev. 14 MC74HCT14A/D

MC74HCT14A MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V VI DC Input Voltage (Referenced to GND) −0.5 to VCC + 0.5 V VO DC Output Voltage (Referenced to GND) −0.5 to VCC + 0.5 V IIK DC Input Diode Current ±20 mA IOK DC Output Diode Current ±25 mA IO DC Output Sink Current ±25 mA ICC DC Supply Current per Supply Pin ±50 mA IGND DC Ground Current per Ground Pin ±50 mA TSTG Storage Temperature Range −65 to +150 (cid:3)C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 (cid:3)C TJ Junction Temperature under Bias +150 (cid:3)C (cid:3)JA Thermal Resistance SOIC 125 (cid:3)C/W TSSOP 170 PD Power Dissipation in Still Air at 85(cid:3)C SOIC 500 mW TSSOP 450 MSL Moisture Sensitivity Level 1 FR Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in VESD ESD Withstand Voltage Human Body Model (Note 1) > 4000 V Machine Model (Note 2) > 300 Charged Device Model (Note 3) > 1000 ILatchup Latchup Performance Above VCC and Below GND at 85(cid:3)C (Note 4) ±300 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22−A114−A. 2. Tested to EIA/JESD22−A115−A. 3. Tested to JESD22−C101−A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V VI, VO DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types −55 +125 (cid:3)C tr, tf Input Rise and Fall Time (Figure 1) − (Note 5) ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 5. No Limit when VI (cid:2) 50% VCC, ICC > 1 mA. 6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level. http://onsemi.com 2

MC74HCT14A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Temperature Limit VCC (cid:2)55(cid:2)C to 25(cid:2)C (cid:3)85(cid:2)C (cid:3)125(cid:2)C Symbol Parameter Test Conditions Volts Min Max Min Max Min Max Unit VT(cid:3)max Maximum Positive−Going VO = 0.1 V or VCC – 0.1 V 4.5 1.9 1.9 1.9 V Input Threshold Voltage |Iout| ≤ 20 (cid:2)A 5.5 2.1 2.1 2.1 VT(cid:3)min Minimum Positive−Going VO = 0.1 V or VCC – 0.1 V 4.5 1.2 1.2 1.2 V Input Threshold Voltage |Iout| ≤ 20 (cid:2)A 5.5 1.4 1.4 1.4 VT(cid:4)max Maximum Negative−Going VO = 0.1 V or VCC – 0.1 V 4.5 1.2 1.2 1.2 Input Threshold Voltage |Iout| ≤ 20 (cid:2)A 5.5 1.4 1.4 1.4 VT(cid:4)min Minimum Negative−Going VO = 0.1 V or VCC – 0.1 V 4.5 0.5 0.5 0.5 Input Threshold Voltage |Iout| ≤ 20 (cid:2)A 5.5 0.6 0.6 0.6 VH max Maximum Hysteresis VO = 0.1 V or VCC – 0.1 V 4.5 1.4 1.4 1.4 Voltage |Iout| ≤ 20 (cid:2)A 5.5 1.5 1.5 1.5 VH min Minimum Hysteresis VO = 0.1 V or VCC – 0.1 V 4.5 0.4 0.4 0.4 Voltage |Iout| ≤ 20 (cid:2)A 5.5 0.4 0.4 0 4 VOH Minimum High−Level VI < VT(cid:4)min 4.5 4.4 4.4 4.4 V Output Voltage |Iout| ≤ 20 (cid:2)A 5.5 5.4 5.4 5.4 VI < VT(cid:4)min 4.5 3.98 3.84 3.7 |Iout| ≤ 4.0 mA VOL Maximum Low−Level VI ≥ VT(cid:3)max 4.5 0.1 0.1 0.1 V Output Voltage |Iout| ≤ 20 (cid:2)A 5.5 0.1 0.1 0.1 VI ≥ VT(cid:3)max 4.5 0.26 0.33 0.4 |Iout| ≤ 4.0 mA IIK Maximum Input VI = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 (cid:2)A Leakage Current ICC Maximum Quiescent VI = VCC or GND 5.5 1.0 10 40 (cid:2)A Supply Current Iout = 0 (cid:2)A (per package) (cid:5)(cid:2)55(cid:2)C 25(cid:2)C to 125(cid:2)C (cid:4)ICC Additional Quiescent VI = 2.4 V, Any One Input 5.5 2.9 2.4 mA Supply Current VI = VCC or GND, Other Inputs lout = 0 (cid:2)A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. AC CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns) Guaranteed Limit (cid:2)55(cid:2)C to 25(cid:2)C (cid:3)85(cid:2)C (cid:3)125(cid:2)C Symbol Parameter Test Conditions Figures Min Max Min Max Min Max Unit tPLH, Maximum Propagation VCC = 5.0 V ±10% 1 & 2 32 40 48 ns tPHL Delay, Input A to Output CL = 50 pF, Input tr = tf = 6.0 ns Y (L to H) tTLH, Maximum Output VCC = 5.0 V ±10% 1 & 2 15 19 22 ns tTHL Transition Time, Any CL = 50 pF, Input tr = tf = 6.0 ns Output Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance, per Inverter (Note 7) 32 pF 7. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. http://onsemi.com 3

MC74HCT14A tf tr 3 V INPUT A 2.7 V 1.3 V 0.3 V GND tPLH tPHL 90% 1.3 V OUTPUT Y 10% tTLH tTHL Figure 1. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance. Figure 2. Test Circuit ORDERING INFORMATION Device Package Shipping† MC74HCT14ADG SOIC−14 NB 55 Units / Rail NLV74HCT14ADG* (Pb−Free) MC74HCT14ADR2G SOIC−14 NB 2500 / Tape & Reel NLV74HCT14ADR2G* (Pb−Free) MC74HCT14ADTR2G TSSOP−14 2500 / Tape & Reel (Pb−Free) NLV74HCT14ADTR2G* †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 4

MC74HCT14A PACKAGE DIMENSIONS TSSOP−14 CASE 948G ISSUE B 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER 0.10 (0.004) M T U S V S ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. N MOLD FLASH OR GATE BURRS SHALL NOT 0.25 (0.010) EXCEED 0.15 (0.006) PER SIDE. 2XL/2 14 8 4I.NTDEIMRLEENASDIO FNL ABS DHO OERS PNROOT TINRCULSUIODNE. M INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. L B 5. DIMENSION K DOES NOT INCLUDE −U− N DAMBAR PROTRUSION. ALLOWABLE PIN 1 DAMBAR PROTRUSION SHALL BE 0.08 IDENT. F (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL 1 7 DETAIL E CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE 0.15 (0.006) T U S A K DETERMINED AT DATUM PLANE −W−. −V− ÇÇK1Ç MILLIMETERS INCHES DIM MIN MAX MIN MAX ÇÉÇÉÇÉ A 4.90 5.10 0.193 0.200 J J1 B 4.30 4.50 0.169 0.177 ÇÉÇÉÇÉ C −−− 1.20 −−− 0.047 SECTION N−N D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 −W− J 0.09 0.20 0.004 0.008 C J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 0.10 (0.004) K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC −T− SEATING D G H DETAIL E M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) PLANE SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 14X 0.36 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5

MC74HCT14A PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE K D A NOTES: B 1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.CONTROLLING DIMENSION: MILLIMETERS. 14 8 3.DIMENSION b DOES NOT INCLUDE DAMBAR A3 PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. H E 4.DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. L 5.MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 1 7 DETAIL A MILLIMETERS INCHES 0.25 M B M 13Xb DIM MIN MAX MIN MAX A 1.35 1.75 0.054 0.068 0.25 M C A S B S A1 0.10 0.25 0.004 0.010 A3 0.19 0.25 0.008 0.010 DETAIL A b 0.35 0.49 0.014 0.019 h A D 8.55 8.75 0.337 0.344 X 45(cid:3) E 3.80 4.00 0.150 0.157 e 1.27 BSC 0.050 BSC H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 e A1 C SEATING M ML 0.04 0(cid:3) 1.72 5(cid:3) 0.001 6(cid:3) 0.074 9(cid:3) PLANE SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com MC74HCT14A/D 6

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