MC74HC4051A, MC74HC4052A, MC74HC4053A Analog Multiplexers/ Demultiplexers www.onsemi.com High−Performance Silicon−Gate CMOS The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog SOIC−16 WIDE SOIC−16 multiplexers/demultiplexers control analog voltages that may vary DW SUFFIX D SUFFIX across the complete power supply range (from VCC to VEE). CASE 751G CASE 751B The HC4051A, HC4052A and HC4053A are identical in pinout to the metal−gate MC14051AB, MC14052AB and MC14053AB. The Channel−Select inputs determine which one of the Analog 1 Inputs/Outputs is to be connected, by means of an analog switch, to the TSSOP−16 QFN16 Common Output/Input. When the Enable pin is HIGH, all analog DT SUFFIX MN SUFFIX switches are turned off. CASE 948F CASE 485AW The Channel−Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL MARKING DIAGRAMS outputs. 16 16 These devices have been designed so that the ON resistance (R ) is on more linear over input voltage than R of metal−gate CMOS analog HC405xA HC405xAG on AWLYWWG AWLYWW switches. For a multiplexer/demultiplexer with injection current protection, 1 see HC4851A and HC4852A. 1 SOIC−16 SOIC−16 WIDE Features 16 • Fast Switching and Propagation Speeds HC40 4051 • Low Crosstalk Between Switches 5xA ALYW(cid:2) • Diode Protection on All Inputs/Outputs ALY(cid:2)W(cid:2) (cid:2) • Analog Power Supply Range (V − V ) = 2.0 to 12.0 V 1 QFN16 CC EE • TSSOP−16 Digital (Control) Power Supply Range (V − GND) = 2.0 to 6.0 V CC • Improved Linearity and Lower ON Resistance Than Metal−Gate x = 1, 2 or 3 Counterparts A = Assembly Location • WL, L = Wafer Lot Low Noise YY, Y = Year • In Compliance with the Requirements of JEDEC Standard No. 7A WW, W = Work Week • G or (cid:2) = Pb−Free Package Chip Complexity: HC4051A − 184 FETs or 46 Equivalent Gates (Note: Microdot may be in either location) HC4052A − 168 FETs or 42 Equivalent Gates HC4053A − 156 FETs or 39 Equivalent Gates • NLV Prefix for Automotive and Other Applications Requiring ORDERING INFORMATION Unique Site and Control Change Requirements; AEC−Q100 See detailed ordering and shipping information in the package Qualified and PPAP Capable dimensions section on page 13 of this data sheet. • These Devices are Pb−Free, Halogen Free/BFR−Free and are RoHS Compliant This document contains information on some products that are still under development. ON Semiconductor reserves the right to change or discontinue these products without notice. © Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: May, 2019 − Rev. 10 MC74HC4051A/D

MC74HC4051A, MC74HC4052A, MC74HC4053A FUNCTION TABLE − MC74HC4051A LOGIC DIAGRAM Control Inputs MC74HC4051A Select Single−Pole, 8−Position Plus Common Off Enable C B A ON Channels L L L L X0 13 X0 L L L H X1 14 X1 L L H L X2 X215 3 X COMMON L L H H X3 ANALOG 12 OUTPUT/ L H L L X4 INPUTS/ X3 MULTIPLEXER/ INPUT L H L H X5 OUTPUTS X4 1 DEMULTIPLEXER L H H L X6 5 X5 L H H H X7 X6 2 H X X X NONE 4 X7 X = Don’t Care 11 A CHSAENLENCETL B10 Pinout: MC74HC4051A (Top View) INPUTS C 9 VCC X2 X1 X0 X3 A B C 6 ENABLE 16 15 14 13 12 11 10 9 PIN 16 = VCC PIN 7 = VEE PIN 8 = GND 1 2 3 4 5 6 7 8 X4 X6 X X7 X5 Enable VEE GND FUNCTION TABLE − MC74HC4052A LOGIC DIAGRAM Control Inputs MC74HC4052A Double−Pole, 4−Position Plus Common Off Select Enable B A ON Channels 12 X0 L L L Y0 X0 14 X1 13 L L H Y1 X1 15 X SWITCH X X2 L H L Y2 X2 11 L H H Y3 X3 X3 ANALOG COMMON H X X NONE INPUTS/OUTPUTS 1 OUTPUTS/INPUTS Y0 X = Don’t Care Y1 5 Y SWITCH 3 Y 2 Y2 4 Y3 Pinout: MC74HC4052A (Top View) 10 CHANNEL‐SINEPLEUCTST AB 9 PIN 16 = VCC VCC X2 X1 X X0 X3 A B PIN 7 = VEE 16 15 14 13 12 11 10 9 PIN 8 = GND 6 ENABLE 1 2 3 4 5 6 7 8 Y0 Y2 Y Y3 Y1 Enable VEE GND www.onsemi.com 2

MC74HC4051A, MC74HC4052A, MC74HC4053A FUNCTION TABLE − MC74HC4053A Control Inputs LOGIC DIAGRAM MC74HC4053A Select Triple Single−Pole, Double−Position Plus Common Off Enable C B A ON Channels L L L L Z0 Y0 X0 12 L L L H Z0 Y0 X1 X0 14 13 X SWITCH X L L H L Z0 Y1 X0 X1 L L H H Z0 Y1 X1 L H L L Z1 Y0 X0 2 L H L H Z1 Y0 X1 Y0 15 COMMON ANALOG 1 Y SWITCH Y L H H L Z1 Y1 X0 INPUTS/OUTPUTS Y1 OUTPUTS/INPUTS L H H H Z1 Y1 X1 H X X X NONE 5 Z0 4 3 Z SWITCH Z X = Don’t Care Z1 11 A CHANNEL‐SELECT B10 PIN 16 = VCC INPUTS 9 PIN 7 = VEE Pinout: MC74HC4053A (Top View) C PIN 8 = GND ENABLE 6 VCC Y X X1 X0 A B C 16 15 14 13 12 11 10 9 NOTE: This device allows independent control of each switch. Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch and Input C controls the Z−Switch 1 2 3 4 5 6 7 8 Y1 Y0 Z1 Z Z0 Enable VEE GND MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protection circuitry to guard against damage VCC Positive DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V due to high static voltages or electric (Referenced to VEE) –0.5 to +14.0 fields. However, precautions must VEE Negative DC Supply Voltage (Referenced to GND) –7.0 to +5.0 V be taken to avoid applications of any voltage higher than maximum rated VIS Analog Input Voltage VEE − 0.5 to V voltages to this high−impedance cir- VCC + 0.5 cuit. For proper operation, Vin and Vin Digital Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V Vout should be constrained to the I DC Current, Into or Out of Any Pin ±25 mA range GND (cid:2) (Vin or Vout) (cid:2) VCC. Unused inputs must always be PD Power Dissipation in Still Air, SOIC Package† 500 mW tied to an appropriate logic voltage TSSOP Package† 450 level (e.g., either GND or VCC). Unused outputs must be left open. Tstg Storage Temperature Range –65 to +150 (cid:3)C TL Lead Temperature, 1 mm from Case for 10 Seconds (cid:3)C SOIC or TSSOP Package 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/(cid:3)C from 65(cid:3) to 125(cid:3)C TSSOP Package: −6.1 mW/(cid:3)C from 65(cid:3) to 125(cid:3)C www.onsemi.com 3

MC74HC4051A, MC74HC4052A, MC74HC4053A RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC Positive DC Supply Voltage (Referenced to GND) 2.0 6.0 V (Referenced to VEE) 2.0 12.0 VEE Negative DC Supply Voltage, Output (Referenced to GND) −6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch 1.2 V TA Operating Temperature Range, All Package Types –55 +125 (cid:3)C tr, tf Input Rise/Fall Time VCC = 2.0 V 0 1000 ns (Channel Select or Enable Inputs) VCC = 3.0 V 0 600 VCC = 4.5 V 0 500 VCC = 6.0 V 0 400 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. *For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Guaranteed Limit VCC Symbol Parameter Condition V −55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High−Level Input Voltage, Ron = Per Spec 2.0 1.50 1.50 1.50 V Channel−Select or Enable Inputs 3.0 2.10 2.10 2.10 4.5 3.15 3.15 3.15 6.0 4.20 4.20 4.20 VIL Maximum Low−Level Input Voltage, Ron = Per Spec 2.0 0.5 0.5 0.5 V Channel−Select or Enable Inputs 3.0 0.9 0.9 0.9 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 Iin Maximum Input Leakage Current, Vin = VCC or GND, 6.0 ±0.1 ±1.0 ±1.0 (cid:2)A Channel−Select or Enable Inputs VEE = − 6.0 V ICC Maximum Quiescent Supply Channel Select, Enable and (cid:2)A Current (per Package) VIS = VCC or GND; VEE = GND 6.0 1 10 20 VIO = 0 V VEE = − 6.0 6.0 4 40 80 www.onsemi.com 4

MC74HC4051A, MC74HC4052A, MC74HC4053A DC CHARACTERISTICS — Analog Section Guaranteed Limit Symbol Parameter Condition VCC VEE −55 to 25°C ≤85°C ≤125°C Unit Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to 4.5 0.0 190 240 280 (cid:3) VEE; IS ≤ 2.0 mA 4.5 − 4.5 120 150 170 (Figures 1, 2) 6.0 − 6.0 100 125 140 Vin = VIL or VIH; VIS = VCC or 4.5 0.0 150 190 230 VEE (Endpoints); IS ≤ 2.0 mA 4.5 − 4.5 100 125 140 (Figures 1, 2) 6.0 − 6.0 80 100 115 (cid:4)Ron Maximum Difference in “ON” Vin = VIL or VIH; 4.5 0.0 30 35 40 (cid:3) Resistance Between Any Two VIS = 1/2 (VCC − VEE); 4.5 − 4.5 12 15 18 Channels in the Same Package IS ≤ 2.0 mA 6.0 − 6.0 10 12 14 Ioff Maximum Off−Channel Leakage Vin = VIL or VIH; (cid:2)A Current, Any One Channel VIO = VCC − VEE; 6.0 − 6.0 0.1 0.5 1.0 Switch Off (Figure 3) Maximum Off−ChannelHC4051A Vin = VIL or VIH; 6.0 − 6.0 0.2 2.0 4.0 Leakage Current, HC4052A VIO = VCC − VEE; 6.0 − 6.0 0.1 1.0 2.0 Common Channel HC4053A Switch Off (Figure 4) 6.0 − 6.0 0.1 1.0 2.0 Ion Maximum On−ChannelHC4051A Vin = VIL or VIH; 6.0 − 6.0 0.2 2.0 4.0 (cid:2)A Leakage Current, HC4052A Switch−to−Switch = 6.0 − 6.0 0.1 1.0 2.0 Channel−to−Channel HC4053A VCC − VEE; (Figure 5) 6.0 − 6.0 0.1 1.0 2.0 AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC Symbol Parameter V −55 to 25°C ≤85°C ≤125°C Unit tPLH, Maximum Propagation Delay, Channel−Select to Analog Output 2.0 270 320 350 ns tPHL (Figure 9) 3.0 90 110 125 4.5 59 79 85 6.0 45 65 75 tPLH, Maximum Propagation Delay, Analog Input to Analog Output 2.0 40 60 70 ns tPHL (Figure 10) 3.0 25 30 32 4.5 12 15 18 6.0 10 13 15 tPLZ, Maximum Propagation Delay, Enable to Analog Output 2.0 160 200 220 ns tPHZ (Figure 11) 3.0 70 95 110 4.5 48 63 76 6.0 39 55 63 tPZL, Maximum Propagation Delay, Enable to Analog Output 2.0 245 315 345 ns tPZH (Figure 11) 3.0 115 145 155 4.5 49 69 83 6.0 39 58 67 Cin Maximum Input Capacitance, Channel−Select or Enable Inputs 10 10 10 pF CI/O Maximum Capacitance Analog I/O 35 35 35 pF (All Switches Off) Common O/I: HC4051A 130 130 130 HC4052A 80 80 80 HC4053A 50 50 50 Feed−through 1.0 1.0 1.0 Typical @ 25°C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Figure 13)* HC4051A 45 pF HC4052A 80 HC4053A 45 *Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. www.onsemi.com 5

MC74HC4051A, MC74HC4052A, MC74HC4053A ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Limit* VCC VEE Symbol Parameter Condition V V 25°C Unit BW Maximum On−Channel Bandwidth fin = 1MHz Sine Wave; Adjust fin Voltage ‘51 ‘52 ‘53 MHz or Minimum Frequency Response to Obtain 0dBm at VOS; Increase fin 2.25 −2.25 80 95 120 (Figure 6) Frequency Until dB Meter Reads −3dB; RL = 50(cid:3), CL = 10pF 46..5000 −−46..5000 8800 9955 112200 − Off−Channel Feed−through fin = Sine Wave; Adjust fin Voltage to 2.25 −2.25 −50 dB Isolation (Figure 7) Obtain 0dBm at VIS 4.50 −4.50 −50 fin = 10kHz, RL = 600(cid:3), CL = 50pF 6.00 −6.00 −50 2.25 −2.25 −40 4.50 −4.50 −40 fin = 1.0MHz, RL = 50(cid:3), CL = 10pF 6.00 −6.00 −40 − Feedthrough Noise. Vin ≤ 1MHz Square Wave (tr = tf = 6ns); 2.25 −2.25 25 mVPP Channel−Select Input to Common Adjust RL at Setup so that IS = 0A; 4.50 −4.50 105 I/O (Figure 8) Enable = GND RL = 600(cid:3), CL = 50pF 6.00 −6.00 135 2.25 −2.25 35 4.50 −4.50 145 RL = 10k(cid:3), CL = 10pF 6.00 −6.00 190 − Crosstalk Between Any Two fin = Sine Wave; Adjust fin Voltage to 2.25 −2.25 −50 dB Switches (Figure 12) Obtain 0dBm at VIS 4.50 −4.50 −50 (Test does not apply to HC4051A) fin = 10kHz, RL = 600(cid:3), CL = 50pF 6.00 −6.00 −50 2.25 −2.25 −60 4.50 −4.50 −60 fin = 1.0MHz, RL = 50(cid:3), CL = 10pF 6.00 −6.00 −60 THD Total Harmonic Distortion fin = 1kHz, RL = 10k(cid:3), CL = 50pF % (Figure 14) THD = THDmeasured − THDsource VIS = 4.0VPP sine wave 2.25 −2.25 0.10 VIS = 8.0VPP sine wave 4.50 −4.50 0.08 VIS = 11.0VPP sine wave 6.00 −6.00 0.05 *Limits not tested. Determined by design and verified by qualification. 300 180 160 S) 250 S) M M 140 H H O O E ( 200 E ( 120 C 125°C C 125°C N N A A 100 ESIST 150 25°C ESIST 80 25°C N R 100 -(cid:3)55°C N R 60 O O , on , on 40 -(cid:3)55°C R 50 R 20 0 0 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1a. Typical On Resistance, V − V = 2.0 V Figure 1b. Typical On Resistance, V − V = 3.0 V CC EE CC EE www.onsemi.com 6

MC74HC4051A, MC74HC4052A, MC74HC4053A 120 105 S) 100 S) 90 M M OH OH 75 125°C CE ( 80 125°C CE ( N N 60 STA 60 STA 25°C ESI 25°C ESI 45 ON R 40 ON R -(cid:3)55°C , n -(cid:3)55°C , n 30 o o R R 20 15 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1c. Typical On Resistance, V − V = 4.5 V Figure 1d. Typical On Resistance, V − V = 6.0 V CC EE CC EE 80 60 70 MS) MS) 50 125°C H 60 H O O NCE ( 50 125°C NCE ( 40 25°C A A ST 40 ST 30 ON RESI 30 25°C ON RESI 20 -(cid:3)55°C , n 20 -(cid:3)55°C , n o o R R 10 10 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 10 11 12 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1e. Typical On Resistance, V − V = 9.0 V Figure 1f. Typical On Resistance, V − V = 12.0 V CC EE CC EE PLOTTER PROGRAMMABLE POWER MINI COMPUTER DC ANALYZER SUPPLY - + VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND VEE Figure 2. On Resistance Test Set−Up www.onsemi.com 7

MC74HC4051A, MC74HC4052A, MC74HC4053A VCC VCC VEE 16 VCC VEE ANALOG I/O 16 VCC OFF OFF VCC A NC OFF COMMON O/I VCC OFF COMMON O/I VIH 6 VIH 6 7 7 8 8 VEE VEE Figure 3. Maximum Off Channel Leakage Current, Figure 4. Maximum Off Channel Leakage Current, Any One Channel, Test Set−Up Common Channel, Test Set−Up VCC A 16 VCC 0.1(cid:2)F 1V6CC VOS dB ON fin ON METER VEE OFF COMMON O/I N/C CL* RL VCC ANALOG I/O VIL 6 6 7 7 8 8 VEE VEE *Includes all probe and jig capacitance Figure 5. Maximum On Channel Leakage Current, Figure 6. Maximum On Channel Bandwidth, Channel to Channel, Test Set−Up Test Set−Up VIS VCC VOS VCC 0.1(cid:2)F 16 dB RL 16 fin OFF METER ON/OFF COMMON O/I TEST RL CL* RL ANALOG I/O OFF/ON RL CL* POINT RL 6 6 7 7 VCC 8 Vin ≤1 MHz 8 11 VEE CHANNEL SELECT VCC tr = tf = 6 ns VEE CHANNEL SELECT VIL or VIH GND *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 7. Off Channel Feedthrough Isolation, Figure 8. Feedthrough Noise, Channel Select to Test Set−Up Common Out, Test Set−Up www.onsemi.com 8

MC74HC4051A, MC74HC4052A, MC74HC4053A VCC VCC 16 VCC CHANNEL 50% ANALOG I/O ON/OFF COMMON O/I TEST SELECT POINT OFF/ON GND CL* tPLH tPHL 6 ANALOG 50% 7 OUT 8 CHANNEL SELECT *Includes all probe and jig capacitance Figure 9a. Propagation Delays, Channel Select Figure 9b. Propagation Delay, Test Set−Up Channel to Analog Out Select to Analog Out VCC 16 ANALOG I/O COMMON O/I VCC ON TEST ANALOG POINT IN 50% CL* GND tPLH tPHL 6 7 ANALOG 8 50% OUT *Includes all probe and jig capacitance Figure 10a. Propagation Delays, Analog In Figure 10b. Propagation Delay, Test Set−Up to Analog Out Analog In to Analog Out tf tr POSITION 1 WHEN TESTING tPHZ AND tPZH 90% VCC 1 POSITION 2 WHEN TESTING tPLZ AND tPZL ENABLE 50% 2 10% VCC GND VCC 16 1k(cid:3) tPZL tPLZ HIGH 1 ANALOG I/O IMPEDANCE TEST ON/OFF ANALOG 50% 2 POINT OUT 10% CL* VOL tPZH tPHZ ENABLE 90% VOH 6 ANALOG 7 50% OUT 8 HIGH IMPEDANCE Figure 11a. Propagation Delays, Enable to Figure 11b. Propagation Delay, Test Set−Up Analog Out Enable to Analog Out www.onsemi.com 9

MC74HC4051A, MC74HC4052A, MC74HC4053A VCC VIS A VCC 16 16 RL VOS fin ON ON/OFF COMMON O/I ANALOG I/O NC 0.1(cid:2)F OFF/ON OFF VEE RL RL CL* RL CL* 6 VCC 7 6 VEE 8 11 7 8 CHANNEL SELECT *Includes all probe and jig capacitance Figure 12. Crosstalk Between Any Two Figure 13. Power Dissipation Capacitance, Switches, Test Set−Up Test Set−Up 0 VIS VCC VOS -(cid:3)10 FUNDAMENTAL FREQUENCY 0.1(cid:2)F 16 TO -(cid:3)20 fin ON DISTORTION -(cid:3)30 RL CL* METER -(cid:3)40 dB -(cid:3)50 DEVICE -(cid:3)60 6 SOURCE -(cid:3)70 7 8 -(cid:3)80 VEE *Includes all probe and jig capacitance -(cid:3)90 -100 1.0 2.0 3.125 FREQUENCY (kHz) Figure 14a. Total Harmonic Distortion, Test Set−Up Figure 14b. Plot, Harmonic Distortion APPLICATIONS INFORMATION The Channel Select and Enable control pins should be at outputs to V or GND through a low value resistor helps CC V or GND logic levels. V being recognized as a logic minimize crosstalk and feed−through noise that may be CC CC high and GND being recognized as a logic low. In this picked up by an unused switch. example: Although used here, balanced supplies are not a V = +5V = logic high requirement. The only constraints on the power supplies are CC GND = 0V = logic low that: The maximum analog voltage swings are determined by VCC − GND = 2 to 6 volts the supply voltages VCC and VEE. The positive peak analog VEE − GND = 0 to −6 volts voltage should not exceed VCC. Similarly, the negative peak VCC − VEE = 2 to 12 volts analog voltage should not go below VEE. In this example, and VEE ≤ GND the difference between V and V is ten volts. Therefore, When voltage transients above V and/or below V are CC EE CC EE using the configuration of Figure 15, a maximum analog anticipated on the analog channels, external Germanium or signal of ten volts peak−to−peak can be controlled. Unused Schottky diodes (D ) are recommended as shown in Figure x analog inputs/outputs may be left floating (i.e., not 16. These diodes should be able to absorb the maximum connected). However, tying unused analog inputs and anticipated current surges during clipping. www.onsemi.com 10

MC74HC4051A, MC74HC4052A, MC74HC4053A +5V VCC VCC VCC +5V 16 +5V Dx 16 Dx ANALOG ANALOG ON ON/OFF SIGNAL SIGNAL -5V -5V Dx Dx VEE VEE 6 11 TO EXTERNAL CMOS 7 10 CIRCUITRY 0 to 5V 7 8 9 DIGITAL SIGNALS 8 -5V VEE Figure 15. Application Example Figure 16. External Germanium or Schottky Clipping Diodes +5V +5V 16 16 +5V +5V +5V +5V ANALOG ANALOG ANALOG ANALOG ON/OFF ON/OFF SIGNAL SIGNAL SIGNAL SIGNAL VEE +5V VEE VEE VEE * R R R +5V 6 11 6 11 LSTTL/NMOS LSTTL/NMOS 7 10 7 10 CIRCUITRY CIRCUITRY 8 9 8 9 VEE * 2K ≤ R ≤ 10K VEE HCT BUFFER a. Using Pull−Up Resistors b. Using HCT Interface Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs 11 LEVEL 13 A X0 SHIFTER 14 X1 10 LEVEL 15 B X2 SHIFTER 12 X3 9 LEVEL 1 C X4 SHIFTER 5 X5 6 LEVEL 2 ENABLE X6 SHIFTER 4 X7 3 X Figure 18. Function Diagram, HC4051A www.onsemi.com 11

MC74HC4051A, MC74HC4052A, MC74HC4053A 10 LEVEL 12 A X0 SHIFTER 14 X1 9 LEVEL 15 B X2 SHIFTER 11 X3 13 X 6 LEVEL 1 ENABLE Y0 SHIFTER 5 Y1 2 Y2 4 Y3 3 Y Figure 19. Function Diagram, HC4052A 11 LEVEL 13 A X1 SHIFTER 12 X0 14 X 10 LEVEL 1 B Y1 SHIFTER 2 Y0 15 Y 9 LEVEL 3 C Z1 SHIFTER 5 Z0 4 Z 6 LEVEL ENABLE SHIFTER Figure 20. Function Diagram, HC4053A www.onsemi.com 12

MC74HC4051A, MC74HC4052A, MC74HC4053A ORDERING INFORMATION Device Package Shipping† MC74HC4051ADG 48 Units / Rail SOIC−16 MC74HC4051ADR2G 2500 Units / Tape & Reel (Pb−Free) NLV74HC4051ADR2G* 2500 Units / Tape & Reel MC74HC4051ADWG 48 Units / Rail SOIC−16 WIDE MC74HC4051ADWR2G 1000 Units / Tape & Reel (Pb−Free) NLVHC4051ADWR2G* 1000 Units / Tape & Reel MC74HC4051ADTG 96 Units / Rail TSSOP−16 MC74HC4051ADTR2G 2500 Units / Tape & Reel (Pb−Free) NLVHC4051ADTR2G* 2500 Units / Tape & Reel NLVHC4051AMNTWG* QFN16 3000 Units / Tape & Reel (In Development) (Pb−Free) MC74HC4052ADG 48 Units / Rail SOIC−16 MC74HC4052ADR2G 2500 Units / Tape & Reel (Pb−Free) NLV74HC4052ADR2G* 2500 Units / Tape & Reel MC74HC4052ADWG 48 Units / Rail SOIC−16 WIDE MC74HC4052ADWR2G (Pb−Free) 1000 Units / Tape & Reel MC74HC4052ADTG 96 Units / Rail MC74HC4052ADTR2G 2500 Units / Tape & Reel TSSOP−16 NLV74HC4052ADTRG* (Pb−Free) 2500 Units / Tape & Reel NLVHC4052ADTR2G* 2500 Units / Tape & Reel NLVHC4052AMNTWG* QFN16 3000 Units / Tape & Reel (In Development) (Pb−Free) MC74HC4053ADG 48 Units / Rail SOIC−16 MC74HC4053ADR2G 2500 Units / Tape & Reel (Pb−Free) NLV74HC4053ADR2G* 2500 Units / Tape & Reel MC74HC4053ADWG 48 Units / Rail NLV74HC4053ADWRG* 1000 Units / Tape & Reel SOIC−16 WIDE MC74HC4053ADWR2G (Pb−Free) 1000 Units / Tape & Reel NLV74HC4053ADWR2G* 1000 Units / Tape & Reel MC74HC4053ADTG 96 Units / Rail TSSOP−16 MC74HC4053ADTR2G 2500 Units / Tape & Reel (Pb−Free) NLVHC4053ADTR2G* 2500 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 13

MC74HC4051A, MC74HC4052A, MC74HC4053A PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B 16X K REF NOTES: 0.10 (0.004) M T U S V S 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 0.15 (0.006) T U S K 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD K1 FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT 16 9 ÇÉÇÉÇÉ EXCEED 0.15 (0.006) PER SIDE. 2XL/2 J1 4. DIMENSION B DOES NOT INCLUDE ÇÉÇÉÇÉ INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL B SECTION N−N NOT EXCEED 0.25 (0.010) PER SIDE. L −U− J 5D.ADMIMBAERN SPIROONT KR UDSOIEOSN N. AOLTL OINWCALUBLDEE DAMBAR PROTRUSION SHALL BE 0.08 PIN 1 (0.003) TOTAL IN EXCESS OF THE K IDENT. N DIMENSION AT MAXIMUM MATERIAL 1 8 0.25 (0.010) CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. M 7. DIMENSION A AND B ARE TO BE 0.15 (0.006) T U S DETERMINED AT DATUM PLANE −W−. A N MILLIMETERS INCHES −V− DIM MIN MAX MIN MAX F A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 DETAIL E C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC C −W− H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 0.10 (0.004) K 0.19 0.30 0.007 0.012 −T− SEATING H DETAIL E K1 0.19 0.25 0.007 0.010 PLANE D G ML 06 .(cid:3) 4 0 BSC8 (cid:3) 00. 2(cid:3) 52 BS8C (cid:3) SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 16X 0.36 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 14

MC74HC4051A, MC74HC4052A, MC74HC4053A PACKAGE DIMENSIONS SOIC−16 WB CASE 751G−03 ISSUE D D A (cid:2) NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 16 9 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. M 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. B 5. DIMENSION B DOES NOT INCLUDE DAMBAR H8X 5M E (cid:3)X 45 PPERRXCOOETTSRRSUU SSOIIFOO NNTH. SAEHL BAL LODLWI MBAEEB N0LS.E1I 3OD NTAO MATBTA AMLR AINXIMUM 0.2 h MATERIAL CONDITION. MILLIMETERS DIM MIN MAX 1 8 A 2.35 2.65 A1 0.10 0.25 16XB B B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 0.25 M T A S B S E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 A q 0 (cid:3) 7 (cid:3) L 14X C e A1 T SEATING PLANE SOLDERING FOOTPRINT* 16X0.58 11.00 1 16X 1.62 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 15

MC74HC4051A, MC74HC4052A, MC74HC4053A PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −A− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. −B− P8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION 1 8 0.25 (0.010) M B S SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX G A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F K R X 45(cid:3) F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 C K 0.10 0.25 0.004 0.009 M 0 (cid:3) 7 (cid:3) 0 (cid:3) 7 (cid:3) −T− SEATING P 5.80 6.20 0.229 0.244 PLANE M J R 0.25 0.50 0.010 0.019 D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X1.12 1 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 16

MC74HC4051A, MC74HC4052A, MC74HC4053A PACKAGE DIMENSIONS QFN16, 2.5x3.5, 0.5P CASE 485AW ISSUE O NOTES: D A 1. DIMENSIONING AND TOLERANCING PER B L L ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. ÉÉÉ 3. DIMENSIONS b APPLIES TO PLATED RPEINF EORNEEN CE ÉÉÉ L1 T0.E1R5 MAINNDA L0 .A30N DM MIS FMREOAMS UTREERDM IBNEATLW. EEN 4. COPLANARITY APPLIES TO THE EXPOSED ÉÉÉ DETAIL A PAD AS WELL AS THE TERMINALS. ALTERNATE TERMINAL MILLIMETERS ÉÉÉ E CONSTRUCTIONS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF EXPOSEDÇ Cu ÇÇMOLD CMPD b 0.20 0.30 2X 0.15 C D 2.50 BSC ÇÉÇÉÇÉ D2 0.85 1.15 E 3.50 BSC 2X 0.15 C TOP VIEW DETAIL B Ee2 1.805.50 BS2C.15 A ALTERNATE K 0.20 --- DETAIL B CONSTRUCTIONS L 0.35 0.45 0.10 C (A3) L1 --- 0.15 A1 16X 0.08 C NOTE 4 SIDE VIEW C SPELAATNIENG SOLDERING FOOTPRINT* 0.15 C A B 3.80 D2 2.10 16X L K 8 0.50 10 0.15 C A B PITCH DETAIL A 2.80 1.10 E2 1 16Xb PACKAGE 2 0.10 C A B 16X 16X OUTLINE 15 0.60 0.30 0.05 C 1 NOTE 3 DIMENSIONS: MILLIMETERS e e/2 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and BOTTOM VIEW Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada For additional information, please contact your local Email: orderlit@onsemi.com Sales Representative ◊ www.onsemi.com MC74HC4051A/D 17

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: MC74HC4051ADG MC74HC4051ADR2G MC74HC4051ADTG MC74HC4051ADTR2G MC74HC4051ADWG MC74HC4051ADWR2G MC74HC4052ADG MC74HC4052ADR2G MC74HC4052ADTG MC74HC4052ADTR2G MC74HC4052ADWG MC74HC4052ADWR2G MC74HC4053ADG MC74HC4053ADR2G MC74HC4053ADTG MC74HC4053ADTR2G MC74HC4053ADWG MC74HC4053ADWR2G