MC74HC374A Octal 3-State Non-Inverting D Flip-Flop High−Performance Silicon−Gate CMOS The MC74HC374A is identical in pinout to the LS374. The device www.onsemi.com inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Data meeting the setup time is clocked to the outputs with the rising edge of the clock. The Output Enable input does not affect the states of the flip−flops, but when Output Enable is high, the outputs are forced SOIC−20 TSSOP−20 to the high−impedance state; thus, data may be stored even when the DW SUFFIX DT SUFFIX outputs are not enabled. CASE 751D CASE 948E The HC374A is identical in function to the HC574A which has the PIN ASSIGNMENT input pins on the opposite side of the package from the output. This device is similar in function to the HC534A which has inverting OUTPUT ENABLE 1 20 VCC outputs. Q0 2 19 Q7 D0 3 18 D7 Features D1 4 17 D6 • Output Drive Capability: 15 LSTTL Loads Q1 5 16 Q6 • Outputs Directly Interface to CMOS, NMOS, and TTL Q2 6 15 Q5 • D2 7 14 D5 Operating Voltage Range: 2.0 to 6.0 V D3 8 13 D4 • Low Input Current: 1.0 (cid:2)A Q3 9 12 Q4 • High Noise Immunity Characteristic of CMOS Devices GND 10 11 CLOCK • In Compliance with the Requirements Defined by JEDEC Standard MARKING DIAGRAMS No. 7A • Chip Complexity: 266 FETs or 66.5 Equivalent Gates 20 20 • NLV Prefix for Automotive and Other Applications Requiring HC374A HC 374A Unique Site and Control Change Requirements; AEC−Q100 AWLYYWWG ALYW(cid:2) Qualified and PPAP Capable (cid:2) • These Devices are Pb−Free and are RoHS Compliant 1 1 SOIC−20 TSSOP−20 A = Assembly Location LOGIC DIAGRAM WL, L = Wafer Lot D0 3 2 Q0 YWYW, Y, W == YWeoarrk Week D1 4 5 Q1 G or (cid:2) = Pb−Free Package 7 6 (Note: Microdot may be in either location) D2 Q2 DATA D3 8 9 Q3 NONINVERTING FUNCTION TABLE INPUTS 13 D4 12 OUTPUTS Inputs Output Q4 14 Output D5 15 Q5 Enable Clock D Q 17 D6 16 18 Q6 L H H D7 L L L 19 11 Q7 L L,H, X No Change CLOCK H X X Z X = don’t care PIN 20 = VCC Z = high impedance 1 PIN 10 = GND OUTPUT ENABLE ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: October, 2017 − Rev. 15 MC74HC374A/D

MC74HC374A MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protection circuitry to guard against damage VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V due to high static voltages or electric Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V fields. However, precautions must be taken to avoid applications of any Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V voltage higher than maximum rated Iin DC Input Current, per Pin ±20 mA voltages to this high−impedance cir- Iout DC Output Current, per Pin ±35 mA cVuoiutt. Fshoor upldro pbeer coopnesrtartaioinne, dV tino athned ICC DC Supply Current, VCC and GND Pins ±75 mA range GND (cid:2) (Vin or Vout) (cid:2) VCC. Unused inputs must always be PD Power Dissipation in Still Air, SOIC Package† 500 mW tied to an appropriate logic voltage TSSOP Package† 450 level (e.g., either GND or VCC). Tstg Storage Temperature –65 to +150 (cid:3)C Unused outputs must be left open. TL Lead Temperature, 1 mm from Case for 10 Seconds (cid:3)C (SOIC, SSOP or TSSOP Package) 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/(cid:3)C from 65(cid:3) to 125(cid:3)C TSSOP Package: −6.1 mW/(cid:3)C from 65(cid:3) to 125(cid:3)C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types –55 +125 (cid:3)C tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns (Figure 1) VCC = 4.5 V 0 500 VCC = 6.0 V 0 400 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC –55 to Symbol Parameter Test Conditions V 25(cid:3)C (cid:2) 85(cid:3)C (cid:2) 125(cid:3)C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V 2.0 1.50 1.50 1.50 V |Iout| (cid:2) 20 (cid:2)A 3.0 2.10 2.10 2.10 4.5 3.15 3.15 3.15 6.0 4.20 4.20 4.20 VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V 2.0 0.50 0.50 0.50 V |Iout| (cid:2) 20 (cid:2)A 3.0 0.90 0.90 0.90 4.5 1.35 1.35 1.35 6.0 1.80 1.80 1.80 VOH Minimum High−Level Output Vin = VIH or VIL 2.0 1.90 1.90 1.90 V Voltage |Iout| (cid:2) 20 (cid:2)A 4.5 4.40 4.40 4.40 6.0 5.90 5.90 5.90 Vin = VIH or VIL |Iout| (cid:2) 2.4 mA 3.0 2.48 2.34 2.20 |Iout| (cid:2) 6.0 mA 4.5 2.98 3.84 3.70 V |Iout| (cid:2) 7.8 mA 6.0 5.48 5.34 5.20 VOL Maximum Low−Level Output Vin = VIH or VIL 2.0 0.10 0.10 0.10 V Voltage |Iout| (cid:2) 20 (cid:2)A 4.5 0.10 0.10 0.10 6.0 0.10 0.10 0.10 Vin = VIH or VIL |Iout| (cid:2) 2.4 mA 3.0 0.26 0.33 0.40 |Iout| (cid:2) 6.0 mA 4.5 0.26 0.33 0.40 V |Iout| (cid:2) 7.8 mA 6.0 0.26 0.33 0.40 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 (cid:2)A www.onsemi.com 2

MC74HC374A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (continued) Guaranteed Limit VVCCCC –55 to SSyymmbbooll PPaarraammeetteerr TTeesstt CCoonnddiittiioonnss VV 25(cid:3)C (cid:2) 85(cid:3)C (cid:2) 125(cid:3)C UUnniitt IOZ Maximum Three−State Output in High−Impedance State 6.0 ±0.5 ±5.0 ±10 (cid:2)A Leakage Current Vin = VIL or VIH Vout = VCC or GND ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 (cid:2)A Current (per Package) Iout = 0 (cid:2)A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit VCC –55 to Symbol Parameter V 25(cid:3)C (cid:2) 85(cid:3)C (cid:2) 125(cid:3)C Unit fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 6 5 4 MHz 3.0 15 10 8 4.5 30 24 20 6.0 35 28 24 tPLH Maximum Propagation Delay, Input Clock to Q 2.0 125 155 190 ns tPHL (Figures 1 and 5) 3.0 80 110 130 4.5 25 31 38 6.0 21 26 32 tPLZ Maximum Propagation Delay, Output Enable to Q 2.0 150 190 225 ns tPHZ (Figures 3 and 6) 3.0 100 125 150 4.5 30 38 45 6.0 26 33 38 tPZL Maximum Propagation Delay, Output Enable to Q 2.0 150 190 225 ns tPZH (Figures 3 and 6) 3.0 100 125 150 4.5 30 38 45 6.0 26 33 38 tTLH Maximum Output Transition Time, Any Output 2.0 75 95 110 ns tTHL (Figures 1 and 5) 3.0 27 32 36 4.5 15 19 22 6.0 13 16 19 Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum Three−State Output Capacitance 15 15 15 pF (Output in High−Impedance State) Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Enabled Output)* 34 pF *Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. www.onsemi.com 3

MC74HC374A TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit –55 to 25(cid:3)C (cid:2) 85(cid:3)C (cid:2) 125(cid:3)C VCC Symbol Parameter Figure Volts Min Max Min Max Min Max Unit tsu Minimum Setup Time, Data to Clock 3 2.0 50 65 75 ns 3.0 40 50 60 4.5 10 13 15 6.0 9 11 13 th Minimum Hold Time, Clock to Data 3 2.0 5.0 5.0 5.0 ns 3.0 5.0 5 0 5.0 4.5 5.0 5.0 5.0 6.0 5.0 5.0 5.0 tw Minimum Pulse Width, Clock 1 2.0 60 75 90 ns 3.0 23 27 32 4.5 12 15 18 6.0 10 13 15 tr, tf Maximum Input Rise and Fall Times 1 2.0 1000 1000 1000 ns 3.0 800 800 800 4.5 500 500 500 6.0 400 400 400 SWITCHING WAVEFORMS tr tf VCC 90% VCC OUTPUT 50% ENABLE CLOCK 50% GND 10% GND tPZL tPLZ HIGH tW IMPEDANCE 1/fmax Q 50% 10% tPLH tPHL VOL 90% tPZH tPHZ Q 50% 90% VOH Q 10% 50% HIGH tTLH tTHL IMPEDANCE Figure 1. Figure 2. VALID VCC DATA 50% GND tsu th VCC CLOCK 50% GND Figure 3. www.onsemi.com 4

MC74HC374A TEST CIRCUITS TEST POINT TEST POINT OUTPUT OUTPUT 1 k(cid:3) CTEOSNTNINEGCT tP TLOZ AVNCDC WtPZHLE.N DEVICE DEVICE CONNECT TO GND WHEN UNDER UNDER TESTING tPHZ AND tPZH. TEST CL* TEST CL* *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 4. Figure 5. D0 D1 D2 D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 D Q D Q D Q D Q D Q D Q D Q D Q C C C C C C C C 11 Clock Output 1 Enable 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Figure 6. Expanded Logic Diagram ORDERING INFORMATION Device Package Shipping† MC74HC374ADWG SOIC−20 WIDE 38 Units / Rail (Pb−Free) NLV74HC374ADWG* SOIC−20 WIDE 38 Units / Rail (Pb−Free) MC74HC374ADWR2G SOIC−20 WIDE 1000 Tape & Reel (Pb−Free) NLV74HC374ADWR2G* SOIC−20 WIDE 1000 Tape & Reel (Pb−Free) MC74HC374ADTG TSSOP−20 75 Units / Rail (Pb−Free) MC74HC374ADTR2G TSSOP−20 2500 Tape & Reel (Pb−Free) NLV74HC374ADTR2G* TSSOP−20 2500 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 5

MC74HC374A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E ISSUE C NOTES: 20X K REF K 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 0.15 (0.006) T U S 0.10 (0.004) M T U S V S K1 2. CONTROLLING DIMENSION: ÍÍÍÍ MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE ÍÍÍÍ MOLD FLASH, PROTRUSIONS OR GATE 20 11 J J1 BURRS. MOLD FLASH OR GATE BURRS 2X L/2 ÍÍÍÍ SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE B SECTION N−N INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION L −U− SHALL NOT EXCEED 0.25 (0.010) PER SIDE. PIN 1 0.25 (0.010) 5. DIMENSION K DOES NOT INCLUDE IDENT N DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 1 10 (0.003) TOTAL IN EXCESS OF THE K M DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR 0.15 (0.006) T U S REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE A N DETERMINED AT DATUM PLANE −W−. −V− F MILLIMETERS INCHES DIM MIN MAX MIN MAX DETAIL E A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 −W− D 0.05 0.15 0.002 0.006 C F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC G H 0.27 0.37 0.011 0.015 D H J 0.09 0.20 0.004 0.008 DETAIL E J1 0.09 0.16 0.004 0.006 0.100 (0.004) K 0.19 0.30 0.007 0.012 −T− SPELAATNIENG KML1 00.61 (cid:3).940 BSC08.2 (cid:3)5 0.0000 (cid:3).2752 B0S.C081 (cid:3)0 SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 16X 0.36 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 6

MC74HC374A PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE H D NOTES: A (cid:2) 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD 20 11 M PROTRUSION. B 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. (cid:3) 5. DIMENSION B DOES NOT INCLUDE DAMBAR H M 45 PROTRUSION. ALLOWABLE PROTRUSION 10X 0.25 E hX SDCHIOMANELDNLI STBIIOEO NN0.. 1A3T TMOATXAILM IUNM E MXCATEESRSI AOLF B 1 10 MILLIMETERS DIM MIN MAX A 2.35 2.65 B A1 0.10 0.25 20X B B 0.35 0.49 C 0.23 0.32 0.25 M T A S B S D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 A L 0.50 0.90 L (cid:2) 0 (cid:3) 7 (cid:3) SEATING 18X e A1 TPLANE C RECOMMENDED SOLDERING FOOTPRINT* 20X 20X 1.30 0.52 20 11 11.00 1 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative ◊ www.onsemi.com MC74HC374A/D 7

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