MC74HC245A Octal 3-State Noninverting Bus Transceiver High−Performance Silicon−Gate CMOS The MC74HC245A is identical in pinout to the LS245. The device http://onsemi.com inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. The HC245A is a 3−state noninverting transceiver that is used for 2−way asynchronous communication between data buses. The device has an active−low Output Enable pin, which is used to place the I/O SOIC−20 TSSOP−20 ports into high−impedance states. The Direction control determines DW SUFFIX DT SUFFIX whether data flows from A to B or from B to A. CASE 751D CASE 948E Features • PIN ASSIGNMENT Output Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • DIRECTION 1 20 VCC Operating Voltage Range: 2.0 to 6.0 V OUTPUT • Low Input Current: 1 (cid:2)A A1 2 19 ENABLE • High Noise Immunity Characteristic of CMOS Devices A2 3 18 B1 • In Compliance with the Requirements Defined by JEDEC Standard A3 4 17 B2 No. 7A • A4 5 16 B3 Chip Complexity: 308 FETs or 77 Equivalent Gates • NLV Prefix for Automotive and Other Applications Requiring A5 6 15 B4 Unique Site and Control Change Requirements; AEC−Q100 A6 7 14 B5 Qualified and PPAP Capable • A7 8 13 B6 These Devices are Pb−Free, Halogen Free and are RoHS Compliant A8 9 12 B7 LOGIC DIAGRAM GND 10 11 B8 2 18 A1 B1 3 17 A2 B2 MARKING DIAGRAMS 4 16 A3 B3 20 5 15 A A4 B4 B 20 DATA 6 14 DATA HC PORT A5 B5 PORT HC245A 245A A6 7 13 B6 AWLYYWWG ALYW(cid:2) (cid:2) 8 12 A7 B7 9 11 1 1 A8 B8 SOIC−20 TSSOP−20 1 A = Assembly Location DIRECTION 19 WL, L = Wafer Lot OUTPUT YY, Y = Year ENABLE PIN 10 = GND WW, W = Work Week PIN 20 = VCC G or (cid:2) = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: November, 2014 − Rev. 16 MC74HC245A/D

MC74HC245A FUNCTION TABLE Control Inputs Output Enable Direction Operation L L Data Transmitted from Bus B to Bus A L H Data Transmitted from Bus A to Bus B H X Buses Isolated (High−Impedance State) X = don’t care MAXIMUM RATINGS (Note 1) Symbol Parameter Value Unit VCC DC Supply Voltage −0.5 to +7.0 V VIN DC Input Voltage −0.5 to VCC + 0.5 V VOUT DC Output Voltage (Note 2) −0.5 to VCC + 0.5 V IIK DC Input Diode Current ±20 mA IOK DC Output Diode Current ±35 mA IOUT DC Output Sink Current ±35 mA ICC DC Supply Current per Supply Pin ±75 mA IGND DC Ground Current per Ground Pin ±75 mA TSTG Storage Temperature Range −65 to +150 (cid:3)C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 (cid:3)C TJ Junction Temperature Under Bias +150 (cid:3)C (cid:3)JA Thermal Resistance SOIC 96 (cid:3)C/W TSSOP 128 PD Power Dissipation in Still Air at 85(cid:3)C SOIC 500 mW TSSOP 450 MSL Moisture Sensitivity Level 1 FR Flammability Rating Oxygen Index: 30% to 35% UL 94 V−0 @ 0.125 in VESD ESD Withstand Voltage Human Body Model (Note 3) (cid:2)2000 V Machine Model (Note 4) (cid:2)200 Charged Device Model (Note 5) (cid:2)1000 ILATCHUP Latchup Performance Above VCC and Below GND at 85(cid:3)C (Note 6) ±300 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 20 ounce copper trace with no air flow. 2. IO absolute maximum rating must observed. 3. Tested to EIA/JESD22−A114−A. 4. Tested to EIA/JESD22−A115−A. 5. Tested to JESD22−C101−A. 6. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types –55 +125 (cid:3)C tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns (Figure 1) VCC = 4.5 V 0 500 VCC = 6.0 V 0 400 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. http://onsemi.com 2

MC74HC245A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC –55 to Symbol Parameter Test Conditions V 25(cid:3)C (cid:3) 85(cid:3)C (cid:3) 125(cid:3)C Unit VIH Minimum High−Level Input Voltage Vout = VCC – 0.1 V 2.0 1.5 1.5 1.5 V |Iout| (cid:3) 20 (cid:2)A 3.0 2.1 2.1 2.1 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 VIL Maximum Low−Level Input Voltage Vout = 0.1 V 2.0 0.5 0.5 0.5 V |Iout| (cid:3) 20 (cid:2)A 3.0 0.9 0.9 0.9 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 VOH Minimum High−Level Output Vin = VIH 2.0 1.9 1.9 1.9 V Voltage |Iout| (cid:3) 20 (cid:2)A 4.5 4.4 4.4 4.4 6.0 5.9 5.9 5.9 Vin = VIH |Iout| (cid:3) 2.4 mA 3.0 2.48 2.34 2.2 |Iout| (cid:3) 6.0 mA 4.5 3.98 3.84 3.7 |Iout| (cid:3) 7.8 mA 6.0 5.48 5.34 5.2 VOL Maximum Low−Level Output Vin = VIL 2.0 0.1 0.1 0.1 V Voltage |Iout| (cid:3) 20 (cid:2)A 4.5 0.1 0.1 0.1 6.0 0.1 0.1 0.1 Vin = VIL |Iout| (cid:3) 2.4 mA 3.0 0.26 0.33 0.4 |Iout| (cid:3) 6.0 mA 4.5 0.26 0.33 0.4 |Iout| (cid:3) 7.8 mA 6.0 0.26 0.33 0.4 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 (cid:2)A IOZ Maximum Three−State Leakage Output in High−Impedance State 6.0 ±0.5 ±5.0 ±10 (cid:2)A Current Vin = VIL or VIH Vout = VCC or GND ICC Maximum Quiescent Supply Cur- Vin = VCC or GND 6.0 4.0 40 160 (cid:2)A rent (per Package) Iout = 0 (cid:2)A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC –55 to Symbol Parameter V 25(cid:3)C (cid:3) 85(cid:3)C (cid:3) 125(cid:3)C Unit tPLH, Maximum Propagation Delay, 2.0 75 95 110 ns tPHL A to B, B to A 3.0 55 70 80 (Figures 1 and 3) 4.5 15 19 22 6.0 13 16 19 tPLZ, Maximum Propagation Delay, 2.0 110 140 165 ns tPHZ Direction or Output Enable to A or B 3.0 90 110 130 (Figures 2 and 4) 4.5 22 28 33 6.0 19 24 28 tPZL, Maximum Propagation Delay, 2.0 110 140 165 ns tPZH Output Enable to A or B 3.0 90 110 130 (Figures 2 and 4) 4.5 22 28 33 6.0 19 24 28 tTLH, Maximum Output Transition Time, 2.0 60 75 90 ns tTHL Any Output 3.0 23 27 32 (Figures 1 and 3) 4.5 12 15 18 6.0 10 13 15 Cin Maximum Input Capacitance (Pin 1 or Pin 19) − 10 10 10 pF Cout Maximum Three−State I/O Capacitance − 15 15 15 pF (I/O in High−Impedance State) Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Transceiver Channel) (Note 7) 40 pF 7. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. http://onsemi.com 3

MC74HC245A ORDERING INFORMATION Device Package Shipping† MC74HC245ADWG SOIC−20 WIDE 38 Units / Rail (Pb−Free) NLV74HC245ADWG* SOIC−20 WIDE 38 Units / Rail (Pb−Free) MC74HC245ADWR2G SOIC−20 WIDE 1000 Tape & Reel (Pb−Free) NLV74HC245ADWR2G* SOIC−20 WIDE 1000 Tape & Reel (Pb−Free) MC74HC245ADTG TSSOP−20 75 Units / Rail (Pb−Free) NLV74HC245ADTG* TSSOP−20 75 Units / Rail (Pb−Free) MC74HC245ADTR2G TSSOP−20 2500 Tape & Reel (Pb−Free) NLV74HC245ADTR2G* TSSOP−20 2500 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. VCC DIRECTION 50% GND VCC tr tf OUTPUT 50% AI NOPRU BT 5900%% VCC ENABLE tPZL tPLZ GHINGDH 10% GND IMPEDANCE 50% tPLH tPHL A OR B OUTPUT 5900%% tPZH tPHZ 10% VOL B OR A 10% 90% VOH A OR B 50% HIGH tTLH tTHL IMPEDANCE Figure 1. Switching Waveform Figure 2. Switching Waveform TEST POINT TEST POINT OUTPUT OUTPUT 1 k(cid:4) CTEOSNTNINEGC TtP TLOZ AVNCDC WtPZHLE.N DEVICE DEVICE CONNECT TO GND WHEN UNDER UNDER TESTING tPHZ AND tPZH. TEST CL* TEST CL* *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit http://onsemi.com 4

MC74HC245A 2 A1 18 B1 3 A2 17 B2 4 A3 16 B3 5 A4 A 15 B4 B DATA DATA PORT PORT 6 A5 14 B5 7 A6 13 B6 8 A7 12 B7 9 A8 11 B8 1 DIRECTION 19 OUTPUT ENABLE Figure 5. Expanded Logic Diagram http://onsemi.com 5

MC74HC245A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE C NOTES: 20X K REF K 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 0.15 (0.006) T U S 0.10 (0.004) M T U S V S ÍÍKÍ1 Í 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE ÍÍÍÍ MOLD FLASH, PROTRUSIONS OR GATE 20 11 J J1 BURRS. MOLD FLASH OR GATE BURRS 2X L/2 ÍÍÍÍ SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE B SECTION N−N INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION L −U− SHALL NOT EXCEED 0.25 (0.010) PER SIDE. PIN 1 0.25 (0.010) 5. DIMENSION K DOES NOT INCLUDE IDENT N DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 1 10 (0.003) TOTAL IN EXCESS OF THE K M DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR 0.15 (0.006) T U S REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE A N DETERMINED AT DATUM PLANE −W−. −V− F MILLIMETERS INCHES DIM MIN MAX MIN MAX DETAIL E A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 −W− D 0.05 0.15 0.002 0.006 C F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC G H 0.27 0.37 0.011 0.015 D H J 0.09 0.20 0.004 0.008 DETAIL E J1 0.09 0.16 0.004 0.006 0.100 (0.004) K 0.19 0.30 0.007 0.012 −T− SPELAATNIENG KML1 00.61 (cid:3).940 BSC08.2 (cid:3)5 0.0000 (cid:3).2752 B0S.C081 (cid:3)0 SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 16X 0.36 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6

MC74HC245A PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G D NOTES: A (cid:2) 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD 20 11 M PROTRUSION. B 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. (cid:3) 5. DIMENSION B DOES NOT INCLUDE DAMBAR H M 45 PROTRUSION. ALLOWABLE PROTRUSION 10X 0.25 E hX SDCHIOMANELDNLI STBIIOEO NN0.. 1A3T TMOATXAILM IUNM E MXCATEESRSI AOLF B 1 10 MILLIMETERS DIM MIN MAX A 2.35 2.65 B A1 0.10 0.25 20X B B 0.35 0.49 C 0.23 0.32 0.25 M T A S B S D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 A L 0.50 0.90 L (cid:2) 0 (cid:3) 7 (cid:3) SEATING 18X e A1 TPLANE C ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com MC74HC245A/D 7

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: MC74HC245ADTG MC74HC245ADTR2G MC74HC245ADWG MC74HC245ADWR2G