MC74HC165A 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High−Performance Silicon−Gate CMOS www.onsemi.com The MC74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup MARKING DIAGRAMS resistors, they are compatible with LSTTL outputs. This device is an 8−bit shift register with complementary outputs 16 from the last stage. Data may be loaded into the register either in PDIP−16 16 MC74HC165AN parallel or in serial form. When the Serial Shift/Parallel Load input is N SUFFIX AWLYYWWG CASE 648 low, the data is loaded asynchronously in parallel. When the Serial 1 Shift/Parallel Load input is high, the data is loaded serially on the 1 rising edge of either Clock or Clock Inhibit (see the Function Table). 16 The 2−input NOR clock may be used either by combining two SOIC−16 independent clock sources or by designating one of the clock inputs to HC165AG 16 D SUFFIX act as a clock inhibit. CASE 751B AWLYWW 1 1 Features • Output Drive Capability: 10 LSTTL Loads 16 • Outputs Directly Interface to CMOS, NMOS, and TTL TSSOP−16 HC • Operating Voltage Range: 2.0 to 6.0 V 16 DT SUFFIX 165A ALYW(cid:2) • Low Input Current: 1 (cid:2)A 1 CASE 948F (cid:2) • High Noise Immunity Characteristic of CMOS Devices 1 • In Compliance with the Requirements Defined by JEDEC Standard No. 7A QFN16 165A • MN SUFFIX ALYW(cid:2) Chip Complexity: 286 FETs or 71.5 Equivalent Gates 1 CASE 485AW (cid:2) • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 A = Assembly Lo- Qualified and PPAP Capable cation • These Devices are Pb−Free, Halogen Free and are RoHS Compliant L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or (cid:2) = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: October, 2014 − Rev. 9 MC74HC165A/D

MC74HC165A SERIAL SHIFT/ PASREARLIALLE LS HLOIFATD/ 1 16 VCC PARALLEL LOAD VCC 1 16 CLOCK 2 15 CLOCK INHIBIT CLOCK 2 15 CLOCK INHIBIT E 3 14 D E 3 14 D F 4 13 C F 4 13 C GND G 5 12 B G 5 12 B H 6 11 A H 6 11 A QH 7 10 SA QH 7 10 SA 8 9 GND 8 9 QH GND QH Figure 1. Pin Assignments 11 A 12 B C 13 9 QH SERIAL PARALLEL 14 DATA INDPAUTTAS DE 3 7 QH OUTPUTS 4 F 5 G SERIAL H 6 PIN 16 = VCC DATA SA 10 PIN 8 = GND INPUT SERIAL SHIFT/ 1 PARALLEL LOAD CLOCK 2 15 CLOCK INHIBIT Figure 2. Logic Diagram FUNCTION TABLE Inputs Internal Stages Output Serial Shift/ Clock Parallel Load Clock Inhibit SA A − H QA QB QH Operation L X X X a … h a b h Asynchronous Parallel Load H L L X L QAn QGn Serial Shift via Clock H L H X H QAn QGn H L L X L QAn QGn Serial Shift via Clock Inhibit H L H X H QAn QGn H X H X X No Change Inhibited Clock H H X X X H L L X X No Change No Clock X = don’t care QAn − QGn = Data shifted from the preceding stage www.onsemi.com 2

MC74HC165A MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protection circuitry to guard against damage VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V due to high static voltages or electric Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must be taken to avoid applications of any Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V voltage higher than maximum rated Iin DC Input Current, per Pin ±20 mA voltages to this high−impedance cir- Iout DC Output Current, per Pin ±25 mA cVuoiutt. Fshoor upldro pbeer coopnesrtartaioinne, dV tino athned ICC DC Supply Current, VCC and GND Pins ±50 mA range GND (cid:2) (Vin or Vout) (cid:2) VCC. Unused inputs must always be PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage SOIC Package† 500 level (e.g., either GND or VCC). TSSOP Package† 450 Unused outputs must be left open. Tstg Storage Temperature – 65 to + 150 (cid:3)C TL Lead Temperature, 1 mm from Case for 10 Seconds (cid:3)C (Plastic DIP, SOIC or TSSOP Package) 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating — Plastic DIP: – 10 mW/(cid:3)C from 65(cid:3) to 125(cid:3)C SOIC Package: – 7 mW/(cid:3)C from 65(cid:3) to 125(cid:3)C TSSOP Package: − 6.1 mW/(cid:3)C from 65(cid:3) to 125(cid:3)C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to 0 VCC V GND) TA Operating Temperature, All Package Types – 55 + 125 (cid:3)C tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns (Figure 1) VCC = 3.0 V 0 600 VCC = 4.5 V 0 500 VCC = 6.0 V 400 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V – 55 to 25(cid:3)C (cid:2) 85(cid:3)C (cid:2) 125(cid:3)C Unit VIH Minimum High−Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V Voltage |Iout| (cid:2) 20 (cid:2)A 3.0 2.1 2.1 2.1 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 VIL Maximum Low−Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V Voltage |Iout| (cid:2) 20 (cid:2)A 3.0 0.9 0.9 0.9 4.5 1.35 1.35 1.35 6.0 1.80 1.80 1.80 VOH Minimum High−Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V Voltage |Iout| (cid:2) 20 (cid:2)A 4.5 4.4 4.4 4.4 6.0 5.9 5.9 5.9 Vin = VIH or VIL |Iout| (cid:2) 2.4 mA 3.0 2.48 2.34 2.20 V |Iout| (cid:2) 4.0 mA 4.5 3.98 3.84 3.70 |Iout| (cid:2) 5.2 mA 6.0 5.48 5.34 5.20 www.onsemi.com 3

MC74HC165A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VVCCCC SSyymmbbooll PPaarraammeetteerr TTeesstt CCoonnddiittiioonnss VV – 55 to 25(cid:3)C (cid:2) 85(cid:3)C (cid:2) 125(cid:3)C UUnniitt VOL Maximum Low−Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V Voltage |Iout| (cid:2) 20 (cid:2)A 4.5 0.1 0.1 0.1 6.0 0.1 0.1 0.1 Vin = VIH or VIL |Iout| (cid:2) 2.4 mA 3.0 0.26 0.33 0.40 |Iout| (cid:2) 4.0 mA 4.5 0.26 0.33 0.40 |Iout| (cid:2) 5.2 mA 6.0 0.26 0.33 0.40 Iin Maximum Input Leakage Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 (cid:2)A Current ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 (cid:2)A Current (per Package) Iout = 0 (cid:2)A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC Symbol Parameter V – 55 to 25(cid:3)C (cid:2) 85(cid:3)C (cid:2) 125(cid:3)C Unit fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 6 4.8 4 MHz (Figures 1 and 8) 3.0 18 17 15 4.5 30 24 20 6.0 35 28 24 tPLH, Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH 2.0 150 190 225 ns tPHL (Figures 1 and 8) 3.0 52 63 65 4.5 30 38 45 6.0 26 33 38 tPLH, Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH 2.0 175 220 265 ns tPHL (Figures 2 and 8) 3.0 58 70 72 4.5 35 44 53 6.0 30 37 45 tPLH, Maximum Propagation Delay, Input H to QH or QH 2.0 150 190 225 ns tPHL (Figures 3 and 8) 3.0 52 63 65 4.5 30 38 45 6.0 26 33 38 tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns tTHL (Figures 1 and 8) 3.0 27 32 36 4.5 15 19 22 6.0 13 16 19 Cin Maximum Input Capacitance − 10 10 10 pF Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* 40 pF *Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. www.onsemi.com 4

MC74HC165A TIMING REQUIREMENTS (Input tr = tf = 6 ns) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol Parameter V – 55 to 25(cid:3)C (cid:2) 85(cid:3)C (cid:2) 125(cid:3)C Unit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load 2.0 75 95 110 ns ÎÎÎÎÎÎ(FigÎure 4Î) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ3.0ÎÎÎÎ30ÎÎÎÎ40ÎÎÎÎ55ÎÎÎÎ 4.5 15 19 22 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 6.0 13 16 19 ÎÎtsÎu ÎÎMÎinimÎum SÎetupÎ TimÎe, InÎput ÎSA tÎo ClÎock (Îor CÎlockÎ InhiÎbit) ÎÎÎÎÎ2.0ÎÎÎÎ75ÎÎÎÎ95ÎÎÎÎ110ÎÎÎnsÎ ÎÎÎÎÎÎ(FigÎure 5Î) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ3.0ÎÎÎÎ30ÎÎÎÎ40ÎÎÎÎ55ÎÎÎÎ 4.5 15 19 22 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ6.0ÎÎÎÎÎÎÎÎ13ÎÎÎÎÎÎÎÎ16ÎÎÎÎÎÎÎÎ19ÎÎÎÎÎÎÎÎ ÎÎtsÎu ÎÎMÎinimuÎm SÎetupÎ TimeÎ, SeÎrial SÎhift/PÎaraÎllel LoÎad tÎo CloÎck (Îor CÎlock ÎInhibÎÎit) Î2.0ÎÎÎÎ75ÎÎÎÎ95ÎÎÎÎ110ÎÎÎnsÎ (Figure 6) 3.0 30 40 55 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 4.5 15 19 22 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ6.0ÎÎÎÎÎÎÎÎ13ÎÎÎÎÎÎÎÎ16ÎÎÎÎÎÎÎÎ19ÎÎÎÎÎÎÎÎ ÎÎtsÎu ÎÎMÎinimÎum SÎetupÎ TimÎe, CÎlockÎ to CÎlockÎ InhiÎbit ÎÎÎÎÎÎÎÎ2.0ÎÎÎÎ75ÎÎÎÎ95ÎÎÎÎ110ÎÎÎnsÎ (Figure 7) 3.0 30 40 55 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 4.5 15 19 22 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ6.0ÎÎÎÎÎÎÎÎ13ÎÎÎÎÎÎÎÎ16ÎÎÎÎÎÎÎÎ19ÎÎÎÎÎÎÎÎ ÎÎtÎh ÎÎMÎinimÎum HÎold ÎTimeÎ, SeÎrial SÎhiftÎ/ParaÎllel ÎLoadÎ to PÎaraÎllel DÎata ÎInpuÎÎts Î2.0ÎÎÎÎ5 ÎÎÎÎ5ÎÎÎÎ5 ÎÎÎnsÎ (Figure 4) 3.0 5 5 5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4.5ÎÎÎÎ5 ÎÎÎÎ5ÎÎÎÎ5 ÎÎÎÎ 6.0 5 5 5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎtÎh ÎÎMÎinimÎum HÎold ÎTimeÎ, ClÎock (Îor CÎlockÎ InhiÎbit) tÎo InpÎut SÎA ÎÎÎÎÎ2.0ÎÎÎÎ5 ÎÎÎÎ5ÎÎÎÎ5 ÎÎÎnsÎ (Figure 5) 3.0 5 5 5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4.5ÎÎÎÎ5 ÎÎÎÎ5ÎÎÎÎ5 ÎÎÎÎ 6.0 5 5 5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎtÎh ÎÎMÎinimuÎm HÎold TÎime,Î CloÎck (oÎr CloÎck InÎhibitÎ) to SÎeriaÎl ShifÎt/ParÎallel ÎLoadÎÎÎ2.0ÎÎÎÎ5 ÎÎÎÎ5ÎÎÎÎ5 ÎÎÎnsÎ (Figure 6) 3.0 5 5 5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4.5ÎÎÎÎ5 ÎÎÎÎ5ÎÎÎÎ5 ÎÎÎÎ 6.0 5 5 5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ trec Minimum Recovery Time, Clock to Clock Inhibit 2.0 75 95 110 ns ÎÎÎÎÎÎ(FigÎure 7Î) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ3.0ÎÎÎÎ30ÎÎÎÎ40ÎÎÎÎ55ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4.5ÎÎÎÎ15ÎÎÎÎ19ÎÎÎÎ22ÎÎÎÎ 6.0 13 16 19 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tw Minimum Pulse Width, Clock (or Clock Inhibit) 2.0 70 90 100 ns ÎÎÎÎÎÎ(FigÎure 1Î) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ3.0ÎÎÎÎ27ÎÎÎÎ32ÎÎÎÎ36ÎÎÎÎ 4.5 15 19 22 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 6.0 13 16 19 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tw Minimum Pulse width, Serial Shift/Parallel Load 2.0 70 90 100 ns ÎÎÎÎÎÎ(FigÎure 2Î) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ3.0ÎÎÎÎ27ÎÎÎÎ32ÎÎÎÎ36ÎÎÎÎ 4.5 15 19 22 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 6.0 13 16 19 ÎÎtr,Î tf ÎÎMÎaximÎum ÎInpuÎt RisÎe anÎd FaÎll TimÎesÎÎÎÎÎÎÎÎÎÎ2.0ÎÎÎ1Î000ÎÎÎÎ100Î0 ÎÎ1Î000ÎÎÎnsÎ ÎÎÎÎÎÎ(FigÎure 1Î) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ3.0ÎÎÎÎ800ÎÎÎÎ800ÎÎÎÎ800ÎÎÎÎ 4.5 500 500 500 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ6.0ÎÎÎÎ400ÎÎÎÎ400ÎÎÎÎ400ÎÎÎÎ www.onsemi.com 5

MC74HC165A PIN DESCRIPTIONS INPUTS is applied to this pin, data at the Parallel Data inputs are asynchronously loaded into each of the eight internal stages. A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6) Parallel Data inputs. Data on these inputs are Clock, Clock Inhibit (Pins 2, 15) asynchronously entered in parallel into the internal Clock inputs. These two clock inputs function identically. flip−flops when the Serial Shift/Parallel Load input is low. Either may be used as an active−high clock inhibit. However, to avoid double clocking, the inhibit input should SA (Pin 10) go high only while the clock input is high. Serial Data input. When the Serial Shift/Parallel Load The shift register is completely static, allowing Clock input is high, data on this pin is serially entered into the first rates down to DC in a continuous or intermittent mode. stage of the shift register with the rising edge of the Clock. OUTPUTS CONTROL INPUTS Q , Q (Pins 9, 7) H H Serial Shift/Parallel Load (Pin 1) Complementary Shift Register outputs. These pins are the Data−entry control input. When a high level is applied to noninverted and inverted outputs of the eighth stage of the this pin, data at the Serial Data input (SA) are shifted into the shift register. register with the rising edge of the Clock. When a low level ORDERING INFORMATION Device Package Shipping† MC74HC165ANG PDIP−16 500 Units / Rail (Pb−Free) MC74HC165ADG SOIC−16 48 Units / Rail (Pb−Free) MC74HC165ADR2G SOIC−16 2500 Units / Reel (Pb−Free) NLV74HC165ADR2G* SOIC−16 2500 Units / Reel (Pb−Free) MC74HC165ADTR2G TSSOP−16 2500 Units / Reel (Pb−Free) NLV74HC165ADTR2G* TSSOP−16 2500 Units / Reel (Pb−Free) MC74HC165AMNTWG QFN16 3000 Units / Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 6

MC74HC165A SWITCHING WAVEFORMS tr tf CLOCK 90% VCC OR CLOCK INHIBIT 50% tw 10% GND VCC tw SERIAL SHIFT/ 50% 50% PARALLEL LOAD 1/fmax GND tPLH tPHL tPLH tPHL QH OR QH 509%0% QH OR QH 50% 10% tTLH tTHL Figure 3. Serial−Shirt Mode Figure 4. Parallel−Load Mode VALID tr tf VCC INPUT H 90% VCC INPUTS A-H 50% GND 50% 10% GND tsu th tPLH tPHL 90% VCC QH OR QH 50% SERIAL SHIFT/ 10% PARALLEL LOAD GND tTLH tTHL ASYNCHRONOUS PARALLEL LOAD (LEVEL SENSITIVE) Figure 5. Parallel−Load Mode Figure 6. Parallel−Load Mode VALID SERIAL SHIFT/ VCC VCC PARALLEL LOAD 50% INPUT SA 50% GND GND tsu th tsu th CLOCK VCC CLOCK VCC OR CLOCK INHIBIT 50% 50% GND OR CLOCK INHIBIT GND Figure 7. Serial−Shift Mode Figure 8. Serial−Shift Mode TEST POINT CLOCK INHIBIT CLOCK 2 INHIBITED VCC DEVICE OUTPUT 50% UNDER GND TEST CL* tsu trec VCC CLOCK 50% GND *Includes all probe and jig capacitance Figure 9. Serial−Shift, Clock−Inhibit Mode Figure 10. Test Circuit www.onsemi.com 7

MC74HC165A EXPANDED LOGIC DIAGRAM A B C F G H 11 12 13 4 5 6 SERIAL SHIFT/ 1 9 PARALLEL LOAD QH 10 7 SERIAL DATA D QA D QB D QC D QF D QG D QH QH INPUT SA C C C C C C C C C C C C 2 CLOCK CLOCK15 INHIBIT TIMING DIAGRAM CLOCK CLOCK INHIBIT SA SERIAL SHIFT/ PARALLEL LOAD A H B L C H PARALLEL D L DATA INPUTS E H F L G H H H QH H H L H L H L H QH L L H L H L H L CLOCK INHIBIT SERIAL-SHIFT MODE MODE PARALLEL LOAD www.onsemi.com 8

MC74HC165A PACKAGE DIMENSIONS PDIP−16 CASE 648−08 ISSUE U NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. D A 2. CONTROLLING DIMENSION: INCHES. 16 9 E 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- H AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. E1 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE 1 8 c LEADS UNCONSTRAINED. NOTE 8 TOP VIEW b2 B WITH LEEANDSD C VOINESWTRAINED 78.. DLPEAAACTDUKSAM,G PWEL HACENORENE TH TO IHSUE RC LOISEI NAODCPSITD IEEOXNNITTA WLT H(IRTEHO B UTONHDDEY EB.DO OTTRO SMQ OUFA RTEHE NOTE 5 CORNERS). A2 e/2 A INCHES MILLIMETERS DIM MIN MAX MIN MAX NOTE 3 A −−−− 0.210 −−− 5.33 L A1 0.015 −−−− 0.38 −−− A2 0.115 0.195 2.92 4.95 b 0.014 0.022 0.35 0.56 b2 0.060 TYP 1.52 TYP A1 C SPELAATNIENG M CD 00..070385 00..071745 108.2.607 109.3.669 D1 D1 0.005 −−−− 0.13 −−− e eB E 0.300 0.325 7.62 8.26 16Xb END VIEW E1 0.240 0.280 6.10 7.11 e 0.100 BSC 2.54 BSC NOTE 6 0.010 M C A M B M eB −−−− 0.430 −−− 10.92 SIDE VIEW L 0.115 0.150 2.92 3.81 M −−−− 10° −−− 10° www.onsemi.com 9

MC74HC165A PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −A− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. −B− P8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION 1 8 0.25 (0.010) M B S SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX G A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 F D 0.35 0.49 0.014 0.019 K R X 45(cid:3) F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 C K 0.10 0.25 0.004 0.009 M 0 (cid:3) 7 (cid:3) 0 (cid:3) 7 (cid:3) −T− SEATING P 5.80 6.20 0.229 0.244 PLANE M J R 0.25 0.50 0.010 0.019 D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X1.12 1 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS www.onsemi.com 10

MC74HC165A PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B 16X K REF NOTES: 0.10 (0.004) M T U S V S 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 0.15 (0.006) T U S K 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD K1 FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT 16 9 ÇÉÇÉÇÉ EXCEED 0.15 (0.006) PER SIDE. 2XL/2 J1 4. DIMENSION B DOES NOT INCLUDE ÇÉÇÉÇÉ INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL B SECTION N−N NOT EXCEED 0.25 (0.010) PER SIDE. L −U− J 5D.ADMIMBAERN SPIROONT KR UDSOIEOSN N. AOLTL OINWCALUBLDEE DAMBAR PROTRUSION SHALL BE 0.08 PIN 1 (0.003) TOTAL IN EXCESS OF THE K IDENT. N DIMENSION AT MAXIMUM MATERIAL 1 8 0.25 (0.010) CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. M 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. 0.15 (0.006) T U S A N MILLIMETERS INCHES −V− DIM MIN MAX MIN MAX F A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 DETAIL E C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC C −W− H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 0.10 (0.004) K 0.19 0.30 0.007 0.012 −T− SEATING H DETAIL E K1 0.19 0.25 0.007 0.010 PLANE D G ML 06 .(cid:3) 4 0 BSC8 (cid:3) 00. 2(cid:3) 52 BS8C (cid:3) SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 16X 0.36 1.26 DIMENSIONS: MILLIMETERS www.onsemi.com 11

MC74HC165A PACKAGE DIMENSIONS QFN16, 2.5x3.5, 0.5P CASE 485AW ISSUE O NOTES: D A 1. DIMENSIONING AND TOLERANCING PER B L L ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS b APPLIES TO PLATED PIN ONE ÉÉÉ L1 TERMINAL AND IS MEASURED BETWEEN REFERENCE 0.15 AND 0.30 MM FROM TERMINAL. ÉÉÉ 4. COPLANARITY APPLIES TO THE EXPOSED DETAIL A PAD AS WELL AS THE TERMINALS. ÉÉÉ ALTERNATE TERMINAL MILLIMETERS CONSTRUCTIONS E DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF EXPOSED Cu MOLD CMPD b 0.20 0.30 2X 0.15 C ÇÉÇÉÇÉ D 2.50 BSC D2 0.85 1.15 2X 0.15 C TOP VIEW ÉDEÉTAIÉL B EEe2 1.380.5.5500 BBSSC2C.15 A ALTERNATE K 0.20 --- DETAIL B CONSTRUCTIONS L 0.35 0.45 0.10 C (A3) L1 --- 0.15 A1 16X 0.08 C NOTE 4 SIDE VIEW C SPELAATNIENG SOLDERING FOOTPRINT* 0.15 C A B 3.80 D2 2.10 16X L K 8 0.50 10 0.15 C A B PITCH DETAIL A 2.80 1.10 E2 1 16Xb PACKAGE 2 0.10 C A B 16X 16X OUTLINE 15 0.60 0.30 0.05 C 1 NOTE 3 DIMENSIONS: MILLIMETERS e e/2 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and BOTTOM VIEW Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative www.onsemi.com MC74HC165AD 12

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