56F8356/56F8156 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8356 Rev. 13 01/2007 freescale.com

Document Revision History Version History Description of Change Rev 1.0 Initial Public Release Rev 2.0 Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO). Added “Typical Min” values to Table10-18. Editing grammar, spelling, consistency of language throughout family. Updated values in Regulator Parameters Table10-9, External Clock Operation Timing Requirements Table10-13, SPI Timing Table10-18, ADC Parameters Table10-24, and IO Loading Coefficients at 10MHz Table10-25. Rev 3.0 Added Part 4.8, added the word “access” to FM Error Interrupt in Table4-5, documenting only Typ. numbers for LVI in Table10-6, updated EMI numbers and writeup in Part 10.8. Rev 4.0 Updated numbers in Table10-7 and Table10-8 with more recent data, Corrected typo in Table10-3 in Pd characteristics. Rev 5.0 Replace any reference to Flash Interface Unit with Flash Memory Module; corrected thermal numbers for 144 LQFP in Table10-3; removed unneccessary notes in Table10-12; corrected temperature range in Table10-14; added ADC calibration information to Table10-24 and new graphs in Figure10-22 Rev 6.0 Adding/clarifing notes to Table4-4 to help clarify independent program flash blocks and other Program Flash modes, clarification to Table10-23, corrected Digital Input Current Low (pull-up enabled) numbers in Table10-5. Removed text and Table 10-2; replaced with note to Table10-1. Rev 7.0 Added 56F8156 information; edited to indicate differences in 56F8356 and 56F8156. Refor- matted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of electrical tables for consistency throughout family. Clarified I/O power description in Table2-2, added note to Table10-7 and clarified Section12.3. Rev 8.0 Added output voltage maximum value and note to clarify in Table10-1; also removed overall life expectancy note, since life expectancy is dependent on customer usage and must be determined by reliability engineering. Clarified value and unit measure for Maximum allowed P in Table10-3. Corrected note about average value for Flash Data Retention in Table10-4. D Added new RoHS-compliant orderable part numbers in Table13-1. Rev 9.0 Updated Table10-24 to reflect new value for maximum Uncalibrated Gain Error Rev 10.0 Deleted RSTO from Pin Group 2 (listed after Table10-1). Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in Table10-4. Added RoHS-compliance and “pb-free” language to back cover. Rev 11.0 Added information/corrected state during reset in Table2-2. Clarified external reference crys- tal frequency for PLL in Table10-14 by increasing maximum value to 8.4MHz.. Rev 12.0 Replaced “Tri-stated” with an explanation in State During Reset column in Table2-2. Rev. 13 • Added the following note to the description of the TMS signal in Table2-2: Note: Always tie the TMS pin to V through a 2.2K resistor. DD • Added the following note to the description of the TRST signal in Table2-2: Note: For normal operation, connect TRST directly to V . If the design is to be used in a debugging SS environment, TRST may be tied to V through a 1K resistor. SS Please see http://www.freescale.com for the most current data sheet revision. 56F8356 Technical Data, Rev. 13 2 Freescale Semiconductor Preliminary

56F8356/56F8156 General Description Note: Features in italics are NOT available in the 56F8156 device. • Up to 60 MIPS at 60MHz core frequency • Temperature Sensor • DSP and MCU functionality in a unified, • Up to two Quadrature Decoders C-efficient architecture • Optional on-chip regulator • Access up to 1MB of off-chip program and data memory • FlexCAN module • Chip Select Logic for glueless interface to ROM and • Two Serial Communication Interfaces (SCIs) SRAM • Up to two Serial Peripheral Interfaces (SPIs) • 256KB of Program Flash • Up to four general-purpose Quad Timers • 4KB of Program RAM • Computer Operating Properly (COP) / Watchdog • 8KB of Data Flash • JTAG/Enhanced On-Chip Emulation (OnCE™) for • 16KB of Data RAM unobtrusive, real-time debugging • 16KB of Boot Flash • Up to 62 GPIO lines • Up to two 6-channel PWM modules • 144-pin LQFP Package • Four 4-channel, 12-bit ADCs RSTO EMI_MEOXDTEBOOT VPP VCAP VODCDR_DVISss VDDA VSSA RESET 5 2 4 7 5 2 6 PWM Outputs JTAG/ Digital Reg Analog Reg 3 Current Sense Inputs PWMA EOPonrCtE 16-Bit Low Voltage 3 Fora uGltP IInOpCuts 56800E Core Supervisor 3 6 PCWurMre nOt uStepnustse Inputs PWMB HaPrrdowgararem aL nCodoonptinrogl lUernit GenAedradtrioesns U nit T1h6r exe 1 166 +-Db 3iat6t aI n- >Ap u3L6tU -RBeitg MisAteCrs Man iUpBunitli attion or GPIOD Four 36-bit Accumulators 4 Fault Inputs PAB 4 PDB AD0 CDBR 4 AD1 ADCA CDBW 5 VREF Memory R/W Control 44 AADD01 ADCB P1r22o8KgKr xa x m1 16 M6 R eFAmlaMosrhy XXXAADBBB122 AdEdSxrwetesitrscn haBlu s 628 AAA068---1575 oo orr rGG GPPPIIOOIOAEA82-0-13-37 4 TDEQQTeMuuicGmPQaaoPedd_duIrrrSeOa aaArEdttC uu0 Norr oeerS rE 4D8 KK8aK txax x F 11M l16a6e6 s FR mhBl aAoosMroyht PPCCADDDBBBBRW SyCstoenmtr oBlus External BusInterface Unit E xBtuesrn Sawl Ditcahta 79 DGDWR07DPR--I61O 5oB ro0 rG oGPr PIAOI1OF6F90-1-85 4 DecQodueard 1 or IPBus Bridge (IPBB) Bus Control 2 GPIOD0-1 or CS2-3 Timer B or PS or CS0 or GPIOD8 SPI1 or GQPuIaOdC Decoding DePveicriep Sheerleaclts RCWon trol IPAB IPWDB IPRDB DS or CS1 or GPIOD9 1 Timer C or GPIOE Peripherals Quad Clock 2 Timer D or resets PLL GPIOE 2 FlexCAN System P SGPPII0O oEr SGCPII1O oDr SGCPII0O oEr WaCtcOhPd/og CInotnetrrroulpletr InMteogdrautlieon OR GeCnleorcaktor OCS XETXATLAL 4 2 2 IRQA IRQB CLKO CLKMODE 56F8356 / 56F8156 Block Diagram 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 3 Preliminary

Table of Contents Part 1 Overview . . . . . . . . . . . . . . . . . . . . . . . .5 7.2 Flash Access Blocking Mechanisms. . . .127 1.1 56F8356/56F8156 Features . . . . . . . . . . . .5 Part 8 General Purpose Input/Output 1.2 Device Description. . . . . . . . . . . . . . . . . . . .7 1.3 Award-Winning Development (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Environment . . . . . . . . . . . . . . . . . . . .9 8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . .130 1.4 Architecture Block Diagram. . . . . . . . . . . .10 8.2 Memory Maps. . . . . . . . . . . . . . . . . . . . .130 1.5 Product Documentation. . . . . . . . . . . . . . .14 8.3 Configuration. . . . . . . . . . . . . . . . . . . . . .130 1.6 Data Sheet Conventions . . . . . . . . . . . . . .14 Part 9 Joint Test Action Group (JTAG) . . 136 Part 2 Signal/Connection Descriptions. . . .15 9.1 56F8356 Information. . . . . . . . . . . . . . . .136 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .15 2.2 Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . .18 Part 10 Specifications . . . . . . . . . . . . . . . . 136 10.1 General Characteristics. . . . . . . . . . . . . .136 Part 3 On-Chip Clock Synthesis (OCCS). . .38 10.2 DC Electrical Characteristics. . . . . . . . . .140 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .38 10.3 AC Electrical Characteristics. . . . . . . . . .145 3.2 External Clock Operation. . . . . . . . . . . . . .38 10.4 Flash Memory Characteristics. . . . . . . . .145 3.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . .40 10.5 External Clock Operation Timing . . . . . .146 10.6 Phase Locked Loop Timing. . . . . . . . . . .146 Part 4 Memory Map . . . . . . . . . . . . . . . . . . . .40 10.7 Crystal Oscillator Timing. . . . . . . . . . . . .147 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .40 10.8 External Memory Interface Timing . . . . .147 4.2 Program Map. . . . . . . . . . . . . . . . . . . . . . .42 10.9 Reset, Stop, Wait, Mode Select, and 4.3 Interrupt Vector Table . . . . . . . . . . . . . . . .43 Interrupt Timing . . . . . . . . . . . . . . .150 4.4 Data Map. . . . . . . . . . . . . . . . . . . . . . . . . .47 10.10 Serial Peripheral Interface (SPI) 4.5 Flash Memory Map . . . . . . . . . . . . . . . . . .47 Timing. . . . . . . . . . . . . . . . . . . . . . .153 4.6 EOnCE Memory Map. . . . . . . . . . . . . . . . .49 10.11 Quad Timer Timing. . . . . . . . . . . . . . . . .157 4.7 Peripheral Memory Mapped Registers . . .50 10.12 Quadrature Decoder Timing . . . . . . . . . .158 4.8 Factory Programmed Memory. . . . . . . . . .77 10.13 Serial Communication Interface (SCI) Timing. . . . . . . . . . . . . . . . . . . . . . .159 Part 5 Interrupt Controller (ITCN). . . . . . . . .77 10.14 Controller Area Network (CAN) Timing. .159 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .77 10.15 JTAG Timing. . . . . . . . . . . . . . . . . . . . . .160 5.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . .77 10.16 Analog-to-Digital Converter (ADC) 5.3 Functional Description. . . . . . . . . . . . . . . .78 Parameters. . . . . . . . . . . . . . . . . . .161 5.4 Block Diagram. . . . . . . . . . . . . . . . . . . . . .80 10.17 Equivalent Circuit for ADC Inputs . . . . . .164 5.5 Operating Modes. . . . . . . . . . . . . . . . . . . .80 10.18 Power Consumption . . . . . . . . . . . . . . . .165 5.6 Register Descriptions. . . . . . . . . . . . . . . . .80 5.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Part 11 Packaging . . . . . . . . . . . . . . . . . . . 167 11.1 56F8356 Package and Pin-Out Part 6 System Integration Module (SIM) . .109 Information . . . . . . . . . . . . . . . . . . .167 6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . .109 11.2 56F8156 Package and Pin-Out 6.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . .109 Information . . . . . . . . . . . . . . . . . . .169 6.3 Operating Modes. . . . . . . . . . . . . . . . . . .110 6.4 Operating Mode Register. . . . . . . . . . . . .110 Part 12 Design Considerations. . . . . . . . . 174 6.5 Register Descriptions. . . . . . . . . . . . . . . .111 12.1 Thermal Design Considerations . . . . . . .174 6.6 Clock Generation Overview. . . . . . . . . . .125 12.2 Electrical Design Considerations . . . . . .175 6.7 Power-Down Modes Overview . . . . . . . .125 12.3 Power Distribution and I/O Ring 6.8 Stop and Wait Mode Disable Function . .126 Implementation. . . . . . . . . . . . . . . .176 6.9 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Part 13 Ordering Information . . . . . . . . . . 177 Part 7 Security Features . . . . . . . . . . . . . . .127 7.1 Operation with Security Enabled. . . . . . .127 56F8356 Technical Data, Rev. 13 4 Freescale Semiconductor Preliminary

56F8356/56F8156 Features Part 1 Overview 1.1 56F8356/56F8156 Features 1.1.1 Core • Efficient 16-bit 56800E family controller engine with dual Harvard architecture • Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency • Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • Four 36-bit accumulators, including extension bits • Arithmetic and logic multi-bit shifter • Parallel instruction set with unique DSP addressing modes • Hardware DO and REP loops • Three internal address buses • Four internal data buses • Instruction set supports both DSP and controller functions • Controller style addressing modes and instructions for compact code • Efficient C compiler and local variable support • Software subroutine and interrupt stack with depth limited only by memory • JTAG/EOnCE debug programming interface 1.1.2 Differences Between Devices Table 1-1 outlines the key differences between the 56F8356 and 56F8156 devices. Table 1-1 Device Differences Feature 56F8356 56F8156 Guaranteed Speed 60MHz/60 MIPS 40MHz/40 MIPS Program RAM 4KB Not Available Data Flash 8KB Not Available PWM 2 x 6 1 x 6 CAN 1 Not Available Quad Timer 4 2 Quadrature Decoder 2 x 4 1 x 4 Temperature Sensor 1 Not Available Dedicated GPIO — 5 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 5 Preliminary

1.1.3 Memory Note: Features in italics ae NOT available in the 56F8156 device. • Harvard architecture permits as many as three simultaneous accesses to program and data memory • Flash security protection feature • On-chip memory, including a low-cost, high-volume Flash solution — 256KB of Program Flash — 4KB of Program RAM — 8KB of Data Flash — 16KB of Data RAM — 16KB of Boot Flash • Off-chip memory expansion capabilities programmable for 0 - 30 wait states — Access up to 1MB of program memory or 1MB of data memory — Chip select logic for glueless interface to ROM and SRAM • EEPROM emulation capability 1.1.4 Peripheral Circuits Note: Features in italics are NOT available in the 56F8156 device. • Pulse Width Modulator: — In the 56F8356, two Pulse Width Modulator modules, each with six PWM outputs, three Current Sense inputs, and three Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned modes — In the 56F8156, one Pulse Width Modulator module with six PWM outputs, three Current Sense inputs, and three Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned modes • Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, channels 2 and 3 • Quadrature Decoder: — In the 56F8356, two four-input Quadrature Decoders or two additional Quad Timers — In the 56F8156, one four-input Quadrature Decoder, which works in conjunction with Quad Timer A • Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the on-chip temperature • Quad Timer: — In the 56F8356, four dedicated general-purpose Quad Timers totaling three dedicated pins: Timer C with one pin and Timer D with two pins — In the 56F8156, two Quad Timers; Timer A and Timer C both work in conjunction with GPIO • Optional on-chip regulator • FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive 56F8356 Technical Data, Rev. 13 6 Freescale Semiconductor Preliminary

Device Description • Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) • Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO lines) — In the 56F8356, SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B — In the 56F8156, SPI1 can alternately be used only as GPIO • Computer Operating Properly (COP) / Watchdog timer • Two dedicated external interrupt pins • 62 General Purpose I/O (GPIO) pins • External reset input pin for hardware reset • External reset output pin for system reset • Integrated low-voltage interrupt module • JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging • Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock 1.1.5 Energy Information • Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs • On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled • On-chip regulators for digital and analog circuitry to lower cost and reduce noise • Wait and Stop modes available • ADC smart power management • Each peripheral can be individually disabled to save power 1.2 Device Description The 56F8356 and 56F8156 are members of the 56800E core-based family of controllers. Each combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8356 and 56F8156 are well-suited for many applications. The devices include many peripherals that are especially useful for motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control (56F8156 only), engine management, noise suppression, remote utility metering, industrial control for power, lighting, and automation applications. The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications. The 56F8356 and 56F8156 support program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide two external dedicated interrupt lines and up to 62 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 7 Preliminary

1.2.1 56F8356 Features The 56F8356 controller includes 256KB of Program Flash and 8KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 16KB of Data RAM. It also supports program execution from external memory. A total of 16KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F8356 is the inclusion of two Pulse Width Modulator (PWM) modules. These modules each incorporate three complementary, individually programmable PWM signal output pairs (each module is also capable of supporting six independent PWM functions, for a total of 12 PWM outputs) to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM modules provide reference outputs to synchronize the Analog-to-Digital Converters through two channels of Quad Timer C. The 56F8356 incorporates two Quadrature Decoders capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder can be programmed with a time-out value to alert when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and four Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A Flex Controller Area Network (FlexCAN) interface (CAN Version 2.0 B-compliant) and an internal interrupt controller are a part of the 56F8356. 1.2.2 56F8156 Features The 56F8156 controller includes 256KB of Program Flash, programmable through the JTAG port, with 16KB of Data RAM. It also supports program execution from external memory. A total of 16KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program Flash memory areas, which can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot Flash page erase size is 512 bytes. and the Boot Flash memory can also be either bulk or page erased. 56F8356 Technical Data, Rev. 13 8 Freescale Semiconductor Preliminary

Award-Winning Development Environment A key application-specific feature of the 56F8156 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters through two channels of Quad Timer C. The 56F8156 incorporates a Quadrature Decoder capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder can be programmed with a time-out value to alert when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and two Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An internal interrupt controller are a part of the 56F8156. 1.3 Award-Winning Development Environment Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 9 Preliminary

1.4 Architecture Block Diagram Note: Features in italics are NOT available in the 56F8156 device and are shaded in the following figures. The 56F8356/56F8156 architecture is shown in Figure 1-1 and Figure 1-2. Figure1-1 illustrates how the 56800E system buses communicate with internal memories, the external memory interface and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. The figures do not show the on-board regulator and power and ground signals. They also do not show the multiplexing between peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection Descriptions, to see which signals are multiplexed with those of other peripherals. Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its conversions. In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer C input channel as indicated. The timer can then be used to introduce a controllable delay before generating its output signal. The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals. 56F8356 Technical Data, Rev. 13 10 Freescale Semiconductor Preliminary

Architecture Block Diagram 5 JTAG / EOnCE Boot Flash pdb_m[15:0] Program pab[20:0] Flash Program cdbw[31:0] RAM 56800E 17 Address CHIP TAP EMI 16 Data Controller 6 Control TAP Linking Data RAM xab1[23:0] xab2[23:0] External Data Flash JTAG Port cdbr_m[31:0] xdb2_m[15:0] To Flash IPBus Control Logic Bridge Flash Module NOT available on the 56F8156 device. IPBus Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Module(FM). Flash control is accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the Flash memories. Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 11 Preliminary

To/From IPBus Bridge Interrupt CLKGEN Controller (OSC/PLL) Low Voltage Interrupt Timer A POR & LVI 4 System POR Quadrature Decoder 0 RESET SIM 2 Timer D COP Reset Timer B COP 2 4 Quadrature Decoder 1 FlexCAN SPI 1 12 PWMA SYNC Output GPIOA 13 PWMB GPIOB SYNC Output GPIOC ch3i ch2i Timer C 1 GPIOD ch3o ch2o GPIOE GPIOF 8 ADCB 4 SPI0 ADCA 8 2 SCI0 1 TEMP_SENSE 2 SCI1 Note: ADCA and ADCB use the same voltage reference circuit with V , V , V , REFH REFP REFMID NOT available on the 56F8156 device. IPBus V , and V pins. REFN REFLO Figure 1-2 Peripheral Subsystem 56F8356 Technical Data, Rev. 13 12 Freescale Semiconductor Preliminary

Architecture Block Diagram Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus. cdbw[31:0] Primary core data bus for memory writes. Addressed via xab1 bus. xab1[23:0] Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O. Secondary Data Memory Interface xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads. xab2[23:0] Secondary data address bus used for the second of two simultaneous accesses. Capable of addressing only words. Data is returned on xdb2_m. Peripheral Interface Bus IPBus [15:0] Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate as the Primary Data Memory and therefore generates no delays when accessing the processor. Write data is obtained from cdbw. Read data is provided to cdbr_m. 1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 13 Preliminary

1.5 Product Documentation The documents in Table 1-3 are required for a complete description and proper design with the 56F8356/56F8156 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com. Table 1-3 Chip Documentation Topic Description Order Number DSP56800E Detailed description of the 56800E family architecture, DSP56800ERM Reference Manual and 16-bit controller core processor and the instruction set 56F8300 Peripheral Detailed description of peripherals of the 56F8300 MC56F8300UM User Manual devices 56F8300 SCI/CAN Detailed description of the SCI/CAN Bootloaders MC56F83xxBLUM Bootloader User 56F8300 family of devices Manual 56F8356/56F8156 Electrical and timing specifications, pin descriptions, MC56F8356 Technical Data Sheet and package descriptions (this document) Errata Details any chip issues that might be present MC56F8356E MC56F8156E 1.6 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) signal is high or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high. Examples: Signal/Symbol Logic State Signal State Voltage1 PIN True Asserted V /V IL OL PIN False Deasserted V /V IH OH PIN True Asserted V /V IH OH PIN False Deasserted V /V IL OL 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56F8356 Technical Data, Rev. 13 14 Freescale Semiconductor Preliminary

Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8356 and 56F8156 are organized into functional groups, as detailed in Table2-1 and as illustrated in Figure2-1. In Table 2-2, each table row describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Number of Pins in Package Functional Group 56F8356 56F8156 Power (V or V ) 9 9 DD DDA Power Option Control 1 1 Ground (V or V ) 6 6 SS SSA Supply Capacitors1 & V 6 6 PP PLL and Clock 4 4 Address Bus 17 17 Data Bus 16 16 Bus Control 6 6 Interrupt and Program Control 6 6 Pulse Width Modulator (PWM) Ports 25 13 Serial Peripheral Interface (SPI) Port 0 4 4 Serial Peripheral Interface (SPI) Port 1 — 4 Quadrature Decoder Port 02 4 4 Quadrature Decoder Port 13 4 — Serial Communications Interface (SCI) Ports 4 4 CAN Ports 2 — Analog to Digital Converter (ADC) Ports 21 21 Quad Timer Module Ports 3 1 JTAG/Enhanced On-Chip Emulation (EOnCE) 5 5 Temperature Sense 1 — Dedicated GPIO — 5 1. If the on-chip regulator is disabled, the V pins serve as 2.5V V power inputs CAP DD_CORE 2. Alternately, can function as Quad Timer pins or GPIO 3. Pins in this section can function as Quad Timer, SPI #1, or GPIO 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 15 Preliminary

V Power DD_IO 7 Power VDDA_ADC PHASEA0 (TA0, GPIOC4) Quadrature 1 1 Power VDDA_OSC_PLL 1 1 PHASEB0 (TA1, GPIOC5) Dore Qcoudaedr 0 Ground VSS 5 1 INDEX0 (TA2, GPIOC6) Timer A or Ground VSSA_ADC 1 HOME0 (TA3, GPIOC7) GPIO 1 OCR_DIS 1 56F8356 SCLK0 (GPIOE4) 1 SPI0 or SOupthpelyr VCVAP11 -& V VCAP42 4 1 MOSI0 (GPIOE5) GPIO Ports PP PP 2 1 MISO0 (GPIOE6) SS0 (GPIOE7) 1 CLKMODE 1 PLL EXTAL 1 PHASEA1(TB0, SCLK1, GPIOC0) Quadrature and 1 XTAL Decoder 1 or Clock CLKO 1 1 PHASEB1 (TB1, MOSI1, GPIOC1) Quad Timer B 1 INDEX1 (TB2, MISO1, GPIOC2) 1 or SPI 1 or 1 HOME1 (TB3, SS1, GPIOC3) GPIO A0 - A5 (GPIOA8 - 13) External 6 A6 - A7 (GPIOE2 - 3) Address 2 PWMA0 - 5 6 or GBPuIOs A8 - A15G (PGIOPIBO0A (0A -1 67)) 81 33 IFSAAU0L T- A2 0( G- P2IOC8 - 10) PGWPIMOA or External D0 - D6 (GPIOF9 - 15) PWMB0 - 5 7 6 PWMB or Data Bus ISB0 - 2 (GPIOD10 - 12) D7 - D15 (GPIOF0 - 8) 3 GPIO or GPIO 9 FAULTB0 - 3 4 RD 8 ANA0 - 7 ADCA 1 V External WR 5 REF ADCB 1 ANB0 - 7 Bus PS / CS0 (GPIOD8) 8 1 Control or DS / CS1 (GPIOD9) GPIO 1 TEMP_SENSE Temperature GPIOD0 - 1 (CS2 - 3) 1 Sensor 2 CAN_RX 1 FlexCAN CAN_TX SCI 0 or TXD0 (GPIOE0) 1 1 GPIO RXD0 (GPIOE1) 1 TC0 (GPIOE8) 1 QUAD SCI 1 TXD1 (GPIOD6) 1 TD0 - 1 (GPIOE10 - 11) TIMER C and or GPIO RXD1 (GPIOD7) 1 2 D or GPIO IRQA TCK 1 1 IRQB JTAG/ TMS 1 1 EOnCE TDI 1 EXTBOOT INTERRUPT/ 1 Port TDO 1 1 EMI_MODE PCROONGTRROALM TRST RESET 1 1 RSTO 1 Figure 2-1 56F8356 Signals Identified by Functional Group1 (144-pin LQFP) 1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. 56F8356 Technical Data, Rev. 13 16 Freescale Semiconductor Preliminary

Introduction V Power DD_IO 7 PHASEA0 (TA0, GPIOC4) Quadrature Power VDDA_ADC 1 1 PHASEB0 (TA1, GPIOC5) Decoder 0 Power VDDA_OSC_PLL 1 or Quad 1 INDEX0 (TA2, GPIOC6) Ground VSS 5 11 HOME0 (TA3, GPIOC7) TGiPmIeOr A or Ground VSSA_ADC 1 OCR_DIS 56F8356 1 SCLK0 (GPIOE4) 1 MOSI0 (GPIOE5) SPI0 or Other VCAP1 - VCAP4 1 GPIO Supply V 1 & V 2 4 1 MISO0 (GPIOE6) Ports PP PP 2 SS0 (GPIOE7) 1 CLKMODE 1 (SCLK1, GPIOC0) PLL EXTAL 1 1 Claoncdk XTAL 1 1 (MOSI1, GPIOC1) SPI 1 or CLKO (MISO1, GPIOC2) GPIO 1 1 (SS1, GPIOC3) 1 A0 - A5 (GPIOA8 - 13) External 6 A6 - A7 (GPIOE2 - 3) Address 2 Bus A8 - A15 (GPIOA0 - 7) 8 3 (GPIOC8 - 10) GPIO or GPIO GPIOB0 (A16) 1 PWMB0 - 5 6 PWMB or External D0 - D6 (GPIOF9 - 15) 7 3 ISB0 - 2 (GPIOD10 - 12) GPIO Data Bus FAULTB0 - 3 D7 - D15 (GPIOF0 - 8) 4 or GPIO 9 RD 8 ANA0 - 7 ADCA 1 V 5 REF ADCB WR External 1 ANB0 - 7 8 Bus PS / CS0 (GPIOD8) 1 Control or DS / CS1 (GPIOD9) GPIO 1 GPIOD0 - 1 (CS2 - 3) 2 SCI 0 or TXD0 (GPIOE0) 1 GPIO RXD0 (GPIOE1) 1 1 TC0 (GPIOE8) QUAD TIMER C or SCI 1 TXD1 (GPIOD6) 1 2 TD0 - 1 (GPIOE10 - 11) GPIO or GPIO RXD1 (GPIOD7) 1 IRQA 1 TCK 1 1 IRQB JTAG/ TMS 1 1 EXTBOOT INTERRUPT/ EOnPCoErt TTDDOI 1 1 EMI_MODE PCROONGTRROALM 1 RESET TRST 1 1 RSTO 1 Figure 2-2 56F8156 Signals Identified by Functional Group1 (144-pin LQFP) 1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 17 Preliminary

2.2 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other states show the reset condition of the alternate function, which you get if the alternate pin function is selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the pin, it will become an input if no other registers are changed. Table 2-2 Signal and Package Information for the 144-Pin LQFP State Signal Name Pin No. Type During Signal Description Reset V 1 Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface DD_IO and also the Processor core throught the on-chip voltage V 16 regulator, if it is enabled. DD_IO V 31 DD_IO V 38 DD_IO V 66 DD_IO V 84 DD_IO V 119 DD_IO V 102 Supply ADC Power — This pin supplies 3.3V power to the ADC modules. DDA_ADC It must be connected to a clean analog power supply. V 80 Supply Oscillator and PLL Power — This pin supplies 3.3V power to the DDA_OSC_PLL OSC and to the internal regulator that in turn supplies the Phase Locked Loop. It must be connected to a clean analog power supply. V 27 Supply V — These pins provide ground for chip logic and I/O drivers. SS SS V 37 SS V 63 SS V 69 SS V 144 SS V 103 Supply ADC Analog Ground — This pin supplies an analog ground to the SSA_ADC ADC modules. 56F8356 Technical Data, Rev. 13 18 Freescale Semiconductor Preliminary

Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset OCR_DIS 79 Input Input On-Chip Regulator Disable — Tie this pin to V to enable the on-chip regulator SS Tie this pin to V to disable the on-chip regulator DD This pin is intended to be a static DC signal from power-up to shut down. Do not try to toggle this pin for power savings during operation. V 1 51 Supply Supply V 1 - 4 — When OCR_DIS is tied to V (regulator enabled), CAP CAP SS connect each pin to a 2.2μF or greater bypass capacitor in order to VCAP2 128 bypass the core logic voltage regulator, required for proper chip operation. When OCR_DIS is tied to V (regulator disabled), DD V 3 83 CAP these pins become V and should be connected to a DD_CORE regulated 2.5V power supply. V 4 15 CAP V 1 125 Input Input V 1 - 2 — These pins should be left unconnected as an open PP PP circuit for normal functionality. V 2 2 PP CLKMODE 87 Input Input Clock Input Mode Selection — This input determines the function of the XTAL and EXTAL pins. 1 = External clock input on XTAL is used to directly drive the input clock of the chip. The EXTAL pin should be grounded. 0 = A crystal or ceramic resonator should be connected between XTAL and EXTAL. EXTAL 82 Input Input External Crystal Oscillator Input — This input can be connected to an 8MHz external crystal. Tie this pin low if XTAL is driven by an external clock source. XTAL 81 Input/ Chip-driven Crystal Oscillator Output — This output connects the internal Output crystal oscillator output to an external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to GND. The input clock can be selected to provide the clock directly to the core. This input clock can also be selected as the input clock for the on-chip PLL. CLKO 3 Output In reset, Clock Output — This pin outputs a buffered clock signal. Using output is the SIM CLKO Select Register (SIM_CLKOSR), this pin can be disabled programmed as any of the following: disabled, CLK_MSTR (system clock), IPBus clock, oscillator output, prescaler clock and postscaler clock. Other signals are also available for test purposes. See Part 6.5.7 for details. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 19 Preliminary

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset A0 138 Output In reset, Address Bus — A0 - A5 specify six of the address lines for output is external program or data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus control enabled register (BCR), A0 - A5 and EMI control signals are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. (GPIOA8) Input/ Port A GPIO — These six GPIO pins can be individually Output programmed as input or output pins. A1 10 (GPIOA9) After reset, the default state is Address Bus. A2 11 To deactivate the internal pull-up resistor, clear the appropriate (GPIOA10) GPIO bit in the GPIOA_PUR register. A3 12 Example: GPIOA8, clear bit 8 in the GPIOA_PUR register. (GPIOA11) A4 13 (GPIOA12) A5 14 (GPIOA13) A6 17 Output In reset, Address Bus — A6 - A7 specify two of the address lines for output is external program or data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus control enabled register (BCR), A6 - A7 and EMI control signals are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. (GPIOE2) Schmitt Port E GPIO — These two GPIO pins can be individually Input/ programmed as input or output pins. A7 18 Output After reset, the default state is Address Bus. (GPIOE3) To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOE_PUR register. Example: GPIOE2, clear bit 2 in the GPIOE_PUR register. 56F8356 Technical Data, Rev. 13 20 Freescale Semiconductor Preliminary

Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset A8 19 Output In reset, Address Bus— A8 - A15 specify eight of the address lines for output is external program or data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus control enabled register (BCR), A8 - A15 and EMI control signals are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. (GPIOA0) Schmitt Port A GPIO — These eight GPIO pins can be individually Input/ programmed as input or output pins. A9 20 Output (GPIOA1) After reset, the default state is Address Bus. A10 21 To deactivate the internal pull-up resistor, clear the appropriate (GPIOA2) GPIO bit in the GPIOA_PUR register. A11 22 Example: GPIOA0, clear bit 0 in the GPIOA_PUR register. (GPIOA3) A12 23 (GPIOA4) A13 24 (GPIOA5) A14 25 (GPIOA6) A15 26 (GPIOA7) 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 21 Preliminary

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset GPIOB0 33 Schmitt Input, Port B GPIO — This GPIO pin can be programmed as an input or Input/ pull-up output pin. Output enabled (A16) Output Address Bus — A16 specifies one of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A16 and EMI control signals are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. After reset, the start-up state of GPIOB0 (GPIO or address) is determined as a function of EXTBOOT, EMI_MODE and the Flash security setting. See Table4-4 for further information on when this pin is configured as an address pin at reset. In all cases, this state may be changed by writing to GPIOB_PER. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOB_PUR register. D0 59 Input/ In reset, Data Bus — D0 - D6 specify part of the data for external program or Output output is data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus control enabled register (BCR), D0 - D6 are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. (GPIOF9) Input/ Port F GPIO — These seven GPIO pins can be individually Output programmed as input or output pins. D1 60 (GPIOF10) At reset, these pins default to the EMI Data Bus function. D2 72 To deactivate the internal pull-up resistor, clear the appropriate (GPIOF11) GPIO bit in the GPIOF_PUR register. D3 75 Example: GPIOF9, clear bit 9 in the GPIOF_PUR register. (GPIOF12) D4 76 (GPIOF13) D5 77 (GPIOF14) D6 78 (GPIOF15) 56F8356 Technical Data, Rev. 13 22 Freescale Semiconductor Preliminary

Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset D7 28 Input/ In reset, Data Bus — D7 - D14 specify part of the data for external program Output output is or data memory accesses. disabled, pull-up is Most designs will want to change the DRV state to DRV = 1 instead of enabled using the default setting. (GPIOF0) Input/ Port F GPIO — These eight GPIO pins can be individually Output programmed as input or output pins. D8 29 (GPIOF1) At reset, these pins default to Data Bus functionality. D9 30 To deactivate the internal pull-up resistor, clear the appropriate (GPIOF2) GPIO bit in the GPIOF_PUR register. D10 32 Example: GPIOF0, clear bit 0 in the GPIOF_PUR register. (GPIOF3) D11 133 (GPIOF4) D12 134 (GPIOF5) D13 135 (GPIOF6) D14 136 (GPIOF7) D15 137 Input/ In reset, Data Bus — D15 specifies part of the data for external program or Output output is data memory accesses. disabled, pull-up is Most designs will want to change the DRV state to DRV = 1 instead of enabled using the default setting. (GPIOF8) Input/ Port F GPIO — This GPIO pin can be individually programmed as Output an input or output pin. At reset, this pin defaults to the Data Bus function. To deactivate the internal pull-up resistor, clear bit 8 in the GPIOF_PUR register. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 23 Preliminary

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset RD 45 Output In reset, Read Enable — RD is asserted during external memory read output is cycles. When RD is asserted low, pins D0 - D15 become inputs disabled, and an external device is enabled onto the data bus. When RD is pull-up is deasserted high, the external data is latched inside the device. enabled When RD is asserted, it qualifies the A0 - A16, PS, DS, and CSn pins. RD can be connected directly to the OE pin of a Static RAM or ROM. Depending upon the state of the DRV bit in the EMI bus control register (BCR), RD is tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. To deactivate the internal pull-up resistor, set the CTRL bit in the SIM_PUDR register. WR 44 Output In reset, Write Enable — WR is asserted during external memory write output is cycles. When WR is asserted low, pins D0 - D15 become outputs disabled, and the device puts data on the bus. When WR is deasserted high, pull-up is the external data is latched inside the external device. When WR is enabled asserted, it qualifies the A0 - A16, PS, DS, and CSn pins. WR can be connected directly to the WE pin of a static RAM. Depending upon the state of the DRV bit in the EMI bus control register (BCR), WR is tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. To deactivate the internal pull-up resistor, set the CTRL bit in the SIM_PUDR register. PS 46 Output In reset, Program Memory Select — This signal is actually CS0 in the output is EMI, which is programmed at reset for compatibility with the (CS0) disabled, 56F80x PS signal. PS is asserted low for external program pull-up is memory access. enabled Depending upon the state of the DRV bit in the EMI bus control register (BCR), CS0 is tri-stated when the external bus is inactive. CS0 resets to provide the PS function as defined on the 56F80x devices. (GPIOD8) Input/ Port D GPIO — This GPIO pin can be individually programmed as Output an input or output pin. To deactivate the internal pull-up resistor, clear bit 8 in the GPIOD_PUR register. 56F8356 Technical Data, Rev. 13 24 Freescale Semiconductor Preliminary

Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset DS 47 Output In reset, Data Memory Select — This signal is actually CS1 in the EMI, output is which is programmed at reset for compatibility with the 56F80x DS (CS1) disabled, signal. DS is asserted low for external data memory access. pull-up is enabled Depending upon the state of the DRV bit in the EMI bus control register (BCR), DS is tri-stated when the external bus is inactive. CS1 resets to provide the DS function as defined on the 56F80x devices. (GPIOD9) Input/ Port D GPIO — This GPIO pin can be individually programmed as Output an input or output pin. To deactivate the internal pull-up resistor, clear bit 9 in the GPIOD_PUR register. GPIOD0 48 Input/ Input, Port D GPIO — These two GPIO pins can be individually Output pull-up programmed as input or output pins. enabled (CS2) Output Chip Select — CS2 - CS3 may be programmed within the EMI module to act as chip selects for specific areas of the external GPIOD1 49 memory map. (CS3) Depending upon the state of the DRV bit in the EMI bus control register (BCR), A0–A16 and EMI control signals are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. At reset, these pins are configured as GPIO. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOD_PUR register. Example: GPIOD0, clear bit 0 in the GPIOD_PUR register. TXD0 4 Output In reset, Transmit Data — SCI0 transmit data output output is (GPIOE0) Input/ disabled, Port E GPIO — This GPIO pin can be individually programmed as Output pull-up is an input or output pin. enabled After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOE_PUR register. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 25 Preliminary

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset RXD0 5 Input Input, Receive Data — SCI0 receive data input pull-up (GPIOE1) Input/ enabled Port E GPIO — This GPIO pin can be individually programmed as Output an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOE_PUR register. TXD1 42 Output In reset, Transmit Data — SCI1 transmit data output output is (GPIOD6) Input/ disabled, Port D GPIO — This GPIO pin can be individually programmed as Output pull-up is an input or output pin. enabled After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 6 in the GPIOD_PUR register. RXD1 43 Input Input, Receive Data — SCI1 receive data input pull-up (GPIOD7) Input/ enabled Port D GPIO — This GPIO pin can be individually programmed as Output an input or output pin. After reset, the default state is SCI input. To deactivate the internal pull-up resistor, clear bit 7 in the GPIOD_PUR register. TCK 121 Schmitt Input, Test Clock Input — This input pin provides a gated clock to Input pulled low synchronize the test logic and shift serial data to the JTAG/EOnCE internally port. The pin is connected internally to a pull-down resistor. TMS 122 Schmitt Input, Test Mode Select Input — This input pin is used to sequence the Input pulled high JTAG TAP controller’s state machine. It is sampled on the rising internally edge of TCK and has an on-chip pull-up resistor. To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register. Note: Always tie the TMS pin to V through a 2.2K resistor. DD TDI 123 Schmitt Input, Test Data Input — This input pin provides a serial input data Input pulled high stream to the JTAG/EOnCE port. It is sampled on the rising edge internally of TCK and has an on-chip pull-up resistor. To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register. 56F8356 Technical Data, Rev. 13 26 Freescale Semiconductor Preliminary

Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset TDO 124 Output In reset, Test Data Output — This tri-stateable output pin provides a serial output is output data stream from the JTAG/EOnCE port. It is driven in the disabled, shift-IR and shift-DR controller states, and changes on the falling pull-up is edge of TCK. enabled TRST 120 Schmitt Input, Test Reset — As an input, a low signal on this pin provides a reset Input pulled high signal to the JTAG TAP controller. To ensure complete hardware internally reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware device reset is required and the JTAG/EOnCE module must not be reset. In this case, assert RESET, but do not assert TRST. To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register. Note: For normal operation, connect TRST directly to V . If the SS design is to be used in a debugging environment, TRST may be tied to V through a 1K resistor. SS PHASEA0 139 Schmitt Input, Phase A — Quadrature Decoder 0, PHASEA input Input pull-up enabled (TA0) Schmitt TA0 — Timer A, Channel 0 Input/ Output (GPIOC4) Schmitt Port C GPIO — This GPIO pin can be individually programmed as Input/ an input or output pin. Output After reset, the default state is PHASEA0. To deactivate the internal pull-up resistor, clear bit 4 of the GPIOC_PUR register. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 27 Preliminary

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset PHASEB0 140 Schmitt Input, Phase B — Quadrature Decoder 0, PHASEB input Input pull-up enabled (TA1) Schmitt TA1 — Timer A, Channel Input/ Output (GPIOC5) Schmitt Port C GPIO — This GPIO pin can be individually programmed as Input/ an input or output pin. Output After reset, the default state is PHASEB0. To deactivate the internal pull-up resistor, clear bit 5 of the GPIOC_PUR register. INDEX0 141 Schmitt Input, Index — Quadrature Decoder 0, INDEX input Input pull-up enabled (TA2) Schmitt TA2 — Timer A, Channel 2 Input/ Output (GPOPC6) Schmitt Port C GPIO — This GPIO pin can be individually programmed as Input/ an input or output pin. Output After reset, the default state is INDEX0. To deactivate the internal pull-up resistor, clear bit 6 of the GPIOC_PUR register. HOME0 142 Schmitt Input, Home — Quadrature Decoder 0, HOME input Input pull-up enabled (TA3) Schmitt TA3 — Timer A, Channel 3 Input/ Output (GPIOC7) Schmitt Port C GPIO — This GPIO pin can be individually programmed as Input/ an input or output pin. Output After reset, the default state is HOME0. To deactivate the internal pull-up resistor, clear bit 7 of the GPIOC_PUR register. 56F8356 Technical Data, Rev. 13 28 Freescale Semiconductor Preliminary

Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset SCLK0 130 Schmitt Input, SPI 0 Serial Clock — In the master mode, this pin serves as an Input/ pull-up output, clocking slaved listeners. In slave mode, this pin serves as Output enabled the data clock input. (GPIOE4) Schmitt Port E GPIO — This GPIO pin can be individually programmed as Input/ an input or output pin. Output After reset, the default state is SCLK0. To deactivate the internal pull-up resistor, clear bit 4 in the GPIOE_PUR register. MOSI0 132 Input/ In reset, SPI 0 Master Out/Slave In — This serial data pin is an output from Output output is a master device and an input to a slave device. The master device disabled, places data on the MOSI line a half-cycle before the clock edge pull-up is the slave device uses to latch the data. enabled (GPIOE5) Input/ Port E GPIO — This GPIO pin can be individually programmed as Output an input or output pin. After reset, the default state is MOSI0. To deactivate the internal pull-up resistor, clear bit 5 in the GPIOE_PUR register. MISO0 131 Input/ Input, SPI 0 Master In/Slave Out — This serial data pin is an input to a Output pull-up master device and an output from a slave device. The MISO line of enabled a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. (GPIOE6) Input/ Port E GPIO — This GPIO pin can be individually programmed as Output an input or output pin. After reset, the default state is MISO0. To deactivate the internal pull-up resistor, clear bit 6 in the GPIOE_PUR register. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 29 Preliminary

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset SS0 129 Input Input, SPI 0 Slave Select — SS0 is used in slave mode to indicate to the pull-up SPI module that the current transfer is to be received. enabled (GPIOE7) Input/ Port E GPIO — This GPIO pin can be individually programmed as Output input or output pin. After reset, the default state is SS0. To deactivate the internal pull-up resistor, clear bit 7 in the GPIOE_PUR register. PHASEA1 6 Schmitt Input, Phase A1 — Quadrature Decoder 1, PHASEA input for decoder 1. Input pull-up enabled (TB0) Schmitt TB0 — Timer B, Channel 0 Input/ Output (SCLK1) Schmitt SPI 1 Serial Clock — In the master mode, this pin serves as an Input/ output, clocking slaved listeners. In slave mode, this pin serves as Output the data clock input. To activate the SPI function, set the PHSA_ALT bit in the SIM_GPS register. For details, see Part 6.5.8. (GPIOC0) Schmitt Port C GPIO — This GPIO pin can be individually programmed as Input/ an input or output pin. Output In the 56F8356, the default state after reset is PHASEA1. In the 56F8156, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOC_PUR register. 56F8356 Technical Data, Rev. 13 30 Freescale Semiconductor Preliminary

Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset PHASEB1 7 Schmitt Input, Phase B1 — Quadrature Decoder 1, PHASEB input for decoder 1. Input pull-up enabled (TB1) Schmitt TB1 — Timer B, Channel 1 Input/ Output (MOSI1) Schmitt SPI 1 Master Out/Slave In — This serial data pin is an output from Input/ a master device and an input to a slave device. The master device Output places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. To activate the SPI function, set the PHSB_ALT bit in the SIM_GPS register. For details, see Part 6.5.8. (GPIOC1) Schmitt Port C GPIO — This GPIO pin can be individually programmed as Input/ an input or output pin. Output In the 56F8356, the default state after reset is PHASEB1. In the 56F8156, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOC_PUR register. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 31 Preliminary

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset INDEX1 8 Schmitt Input, Index1 — Quadrature Decoder 1, INDEX input Input pull-up enabled (TB2) Schmitt TB2 — Timer B, Channel 2 Input/ Output (MISO1) Schmitt SPI 1 Master In/Slave Out — This serial data pin is an input to a Input/ master device and an output from a slave device. The MISO line of Output a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. To activate the SPI function, set the INDEX_ALT bit in the SIM_GPS register. For details, see Part 6.5.8. (GPIOC2) Schmitt Port C GPIO — This GPIO pin can be individually programmed as Input/ an input or output pin. Output In the 56F8356, the default state after reset is INDEX1. In the 56F8156, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 2 in the GPIOC_PUR register. HOME1 9 Schmitt Input, Home — Quadrature Decoder 1, HOME input Input pull-up enabled (TB3) Schmitt TB3 — Timer B, Channel 3 Input/ Output (SS1) Schmitt SPI 1 Slave Select — In the master mode, this pin is used to Input arbitrate multiple masters. In slave mode, this pin is used to select the slave. To activate the SPI function, set the HOME_ALT bit in the SIM_GPS register. For details, see Part 6.5.8. (GPIOC3) Schmitt Port C GPIO — This GPIO pin can be individually programmed as Input/ an input or output pin. Output In the 56F8356, the default state after reset is HOME1. In the 56F8156, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 3 in the GPIOC_PUR register. 56F8356 Technical Data, Rev. 13 32 Freescale Semiconductor Preliminary

Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset PWMA0 62 Output In reset, PWMA0 - 5 — These are six PWMA outputs. output is PWMA1 64 disabled, pull-up is PWMA2 65 enabled PWMA3 67 PWMA4 68 PWMA5 70 ISA0 113 Schmitt Input, ISA0 - 2 — These three input current status pins are used for Input pull-up top/bottom pulse width correction in complementary channel enabled operation for PWMA. (GPIOC8) Schmitt Port C GPIO — These GPIO pins can be individually programmed Input/ as input or output pins. ISA1 114 Output (GPIOC9) In the 56F8356, these pins default to ISA functionality after reset. ISA2 115 In the 56F8156, the default state is not one of the functions offered (GPIOC10) and must be reconfigured. To deactivate the internal pull-up resistor, clear the appropriate bit of the GPIOC_PUR register. For details, see Part 6.5.8. FaultA0 71 Schmitt Input, FaultA0 - 2 — These three fault input pins are used for disabling Input pull-up selected PWMA outputs in cases where fault conditions originate FaultA1 73 enabled off-chip. FaultA2 74 To deactivate the internal pull-up resistor, set the PWMA0 bit in the SIM_PUDR register. For details, see Part 6.5.8. PWMB0 34 Output In reset, PWMB0 - 5 — Six PWMB output pins. output is PWMB1 35 disabled, pull-up is PWMB2 36 enabled PWMB3 39 PWMB4 40 PWMB5 41 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 33 Preliminary

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset ISB0 50 Schmitt Input, ISB0 - 2 — These three input current status pins are used for Input pull-up top/bottom pulse width correction in complementary channel enabled operation for PWMB. (GPIOD10) Schmitt Port D GPIO — These GPIO pins can be individually programmed Input/ as input or output pins. ISB1 52 Output (GPIOD11) At reset, these pins default to ISB functionality. ISB2 53 To deactivate the internal pull-up resistor, clear the appropriate bit (GPIOD12) of the GPIOD_PUR register. For details, see Part 6.5.8. FaultB0 56 Schmitt Input, FaultB0 - 3 — These four fault input pins are used for disabling Input pull-up selected PWMB outputs in cases where fault conditions originate FaultB1 57 enabled off-chip. FaultB2 58 To deactivate the internal pull-up resistor, set the PWMB bit in the SIM_PUDR register. For details, see Part 6.5.8. FaultB3 61 ANA0 88 Input Analog ANA0 - 3 — Analog inputs to ADC A, channel 0 Input ANA1 89 ANA2 90 ANA3 91 ANA4 92 Input Analog ANA4 - 7 — Analog inputs to ADC A, channel 1 Input ANA5 93 ANA6 94 ANA7 95 V 101 Input Analog V — Analog Reference Voltage High. V must be less REFH REFH REFH Input than or equal toV DDA_ADC. V 100 Input/ Analog V , V & V — Internal pins for voltage reference REFP REFP REFMID REFN Output Input/ which are brought off-chip so they can be bypassed. Connect to a VREFMID 99 Output 0.1μF low ESR capacitor. V 98 REFN V 97 Input Analog V — Analog Reference Voltage Low. This should normally REFLO REFLO Input be connected to a low-noise V . SS 56F8356 Technical Data, Rev. 13 34 Freescale Semiconductor Preliminary

Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset ANB0 104 Input Analog ANB0 - 3 — Analog inputs to ADC B, channel 0 Input ANB1 105 ANB2 106 ANB3 107 ANB4 108 Input Analog ANB4 - 7 — Analog inputs to ADC B, channel 1 Input ANB5 109 ANB6 110 ANB7 111 TEMP_SENSE 96 Output Analog Temperature Sense Diode — This signal connects to an on-chip Output diode that can be connected to one of the ADC inputs and used to monitor the temperature of the die. Must be bypassed with a 0.01μF capacitor. CAN_RX 127 Schmitt Input, FlexCAN Receive Data — This is the CAN input. This pin has an Input pull-up internal pull-up resistor. enabled To deactivate the internal pull-up resistor, set the CAN bit in the SIM_PUDR register. CAN_TX 126 Open Open FlexCAN Transmit Data — CAN output with internal pull-up Drain Drain enable at reset. * Output Output * Note: If a pin is configured as open drain output mode, internal pull-up will automatically be disabled when it outputs low. Internal pull-up will be enabled unless it has been manually disabled by clearing the corresponding bit in the PUREN register of the GPIO module, when it outputs high. If a pin is configured as push-pull output mode, internal pull-up will automatically be disabled, whether it outputs low or high. TC0 118 Schmitt Input, TC0 — Timer C, Channel 0 Input/ pull-up Output enabled (GPIOE8) Schmitt Port E GPIO — This GPIO pin can be individually programmed as Input/ an input or output pin. Output At reset, this pin defaults to timer functionality. To deactivate the internal pull-up resistor, clear bit 8 of the GPIOE_PUR register. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 35 Preliminary

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset TD0 116 Schmitt Input, TD0 - 1 — Timer D, Channels 0 and 1 Input/ pull-up Output enabled (GPIOE10) Schmitt Port E GPIO — These GPIO pins can be individually programmed Input/ as input or output pins. TD1 117 Output (GPIOE11) At reset, these pins default to Timer functionality. To deactivate the internal pull-up resistor, clear the appropriate bit of the GPIOE_PUR register. See Part 6.5.6 for details. IRQA 54 Schmitt Input, External Interrupt Request A and B — The IRQA and IRQB Input pull-up inputs are asynchronous external interrupt requests during Stop IRQB 55 enabled and Wait mode operation. During other operating modes, they are synchronized external interrupt requests, which indicate an external device is requesting service. They can be programmed to be level-sensitive or negative-edge triggered. To deactivate the internal pull-up resistor, set the IRQ bit in the SIM_PUDR register. See Part 6.5.6 for details. RESET 86 Schmitt Input, Reset — This input is a direct hardware reset on the processor. Input pull-up When RESET is asserted low, the device is initialized and placed enabled in the reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and the JTAG/EOnCE module must not be reset. In this case, assert RESET but do not assert TRST. Note: The internal Power-On Reset will assert on initial power-up. To deactivate the internal pull-up resistor, set the RESET bit in the SIM_PUDR register. See Part 6.5.6 for details. RSTO 85 Output Output Reset Output — This output reflects the internal reset state of the chip. 56F8356 Technical Data, Rev. 13 36 Freescale Semiconductor Preliminary

Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State Signal Name Pin No. Type During Signal Description Reset EXTBOOT 112 Schmitt Input, External Boot — This input is tied to V to force the device to DD Input pull-up boot from off-chip memory (assuming that the on-chip Flash enabled memory is not in a secure state). Otherwise, it is tied to ground. For details, see Table4-4. Note: When this pin is tied low, the customer boot software should disable the internal pull-up resistor by setting the XBOOT bit of the SIM_PUDR; see Part 6.5.6. EMI_MODE 143 Schmitt Input, External Memory Mode — The EMI_MODE input is internally tied Input pull-up low (to V ). This device will boot from internal flash memory SS enabled under normal operation. This function is also affected by EXTBOOT and the Flash security mode. For details, see Table4-4. If a 20-bit address bus is not desired, then this pin is tied to ground. Note: When this pin is tied low, the customer boot software should disable the internal pull-up resistor by setting the EMI_MODE bit of the SIM_PUDR; see Part 6.5.6. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 37 Preliminary

Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the specific OCCS block diagram to reference from the OCCS chapter of the 56F8300 Peripheral User Manual. CLKMODE XTAL ZSRC Crystal X OSC U M Prescaler CLK EXTAL SYS_CLK2 X Source to SIM U PLLCID PLLDB PLLCOD M F E PLL Prescaler FR x (1 to 128) FOUT ÷2 FOUT/2 Postscaler Postscaler CLK ÷ (1,2,4,8) ÷ (1,2,4,8) C K S C O A _ B Bus R D Bus Interface & Control T E Interface S E M F Lock LCK Detector Loss of Loss of Reference Reference Clock Interrupt Clock Detector Figure 3-1 OCCS Block Diagram 3.2 External Clock Operation The system clock can be derived from an external crystal, ceramic resonator, or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic resonator must be connected between the EXTAL and XTAL pins. 3.2.1 Crystal Oscillator The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 10-15. A recommended crystal oscillator circuit is shown in Figure 3-2. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal 56F8356 Technical Data, Rev. 13 38 Freescale Semiconductor Preliminary

External Clock Operation parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL EXTAL XTAL Sample External Crystal Parameters: Rz Rz Rz = 750 KΩ CLKMODE = 0 Note: If the operating temperature range is limited to below 85oC (105oC junction), then R = 10 Meg Ω z CL1 CL2 Figure 3-2 Connecting to a Crystal Oscillator Note: The OCCS_COHL bit must be set to 1 when a crystal oscillator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 Peripheral User Manual. 3.2.2 Ceramic Resonator (Default) It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Figure 3-3. Refer to the supplier’s recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 39 Preliminary

Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 2 Terminal 3 Terminal Sample External Ceramic Resonator Parameters: EXTAL XTAL EXTAL XTAL R = 750 KΩ R R z z z CL1 CL2 CLKMODE = 0 C1 C2 Figure 3-3 Connecting a Ceramic Resonator Note: The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 Peripheral User Manual. 3.2.3 External Clock Source The recommended method of connecting an external clock is given in Figure 3-4. The external clock source is connected to XTAL and the EXTAL pin is grounded. Set OCCS_COHL bit high when using an external clock source as well. Note: When using an external clocking source XTAL EXTAL with this configuration, the input “CLKMODE” should be high and the COHL bit in the OSCTL External VSS register should be set to 1. Clock Figure 3-4 Connecting an External Clock Register 3.3 Registers When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the register definitions without the internal Relaxation Oscillator, since the 56F8356/56F8156 devices do NOT contain this oscillator. Part 4 Memory Map 4.1 Introduction The 56F8356 and 56F8156 devices are 16-bit motor-control chips based on the 56800E core. These parts use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM and Flash memories are used in both spaces. 56F8356 Technical Data, Rev. 13 40 Freescale Semiconductor Preliminary

Introduction This section provides memory maps for: • Program Address Space, including the Interrupt Vector Table • Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for each device are summarized in Table 4-1. Flash memories’ restrictions are identified in the “Use Restrictions” column of Table 4-1. Note: Data Flash and Program RAM are NOT available on the 56F8156 device. Table 4-1 Chip Memory Configurations On-Chip Memory 56F8356 56F8156 Use Restrictions Program Flash 256KB 256KB Erase / Program via Flash interface unit and word writes to CDBW Data Flash 8KB — Erase / Program via Flash interface unit and word writes to CDBW. Data Flash can be read via either CDBR or XDB2, but not by both simultaneously Program RAM 4KB — None 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 41 Preliminary

Table 4-1 Chip Memory Configurations On-Chip Memory 56F8356 56F8156 Use Restrictions Data RAM 16KB 16KB None Program Boot Flash 16KB 16KB Erase / Program via Flash Interface unit and word to CDBW 4.2 Program Map The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program memory map. At reset, these bits are set as indicated in Table 4-2. Table 4-4 shows the memory map configurations that are possible at reset. After reset, the OMR MA bit can be changed and will have an effect on the P-space memory map, as shown in Table4-3. Changing the OMR MB bit will have no effect. Table 4-2 OMR MB/MAL Value at Reset OMR MB = OMR MA = Flash Secured Chip Operating Mode EXTBOOT Pin State1, 2 0 0 Mode 0 – Internal Boot; EMI is configured to use 16 address lines; Flash Memory is secured; external P-space is not allowed; the EOnCE is disabled 0 1 Not valid; cannot boot externally if the Flash is secured and will actually configure to 00 state 1 0 Mode 0 – Internal Boot; EMI is configured to use 16 address lines 1 1 Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is determined by the state of the EMI_MODE pin 1. This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset. 2. Changing MB in software will not affect Flash memory security. Table 4-3 Changing OMR MA Value During Normal Operation OMR MA Chip Operating Mode 0 Use internal P-space memory map configuration 1 Use external P-space memory map configuration – If MB = 0 at reset, changing this bit has no effect. The device’s external memory interface (EMI) can operate much like the 56F80x family’s EMI, or it can be operated in a mode similar to that used on other products in the 56800E family. Initially, CS0 and CS1 are configured as PS and DS, in a mode compatible with earlier 56800 devices. Eighteen address lines are required to shadow the first 192K of internal program space when booting externally for development purposes. Therefore, the entire complement of on-chip memory cannot be 56F8356 Technical Data, Rev. 13 42 Freescale Semiconductor Preliminary

Interrupt Vector Table accessed using a 16-bit 56800-compatible address bus. To address this situation, the EMI_MODE pin can be used to configure four GPIO pins as Address[19:16] upon reset (only one of these pins [A16] is usable in the 56F8356/56F8156). The EMI_MODE pin also affects the reset vector address, as provided in Table 4-4. Additional pins must be configured as address or chip select signals to access addresses at P:$10 0000 and above. Note: Program RAM is NOT available on the 56F8156 device. Table 4-4 Program Memory Map at Reset Mode 0 (MA = 0) Mode 11 (MA = 1) Begin/End Internal Boot External Boot Address Internal Boot EMI_MODE = 02,3 EMI_MODE = 14 16-Bit External Address Bus 16-Bit External Address Bus 20-Bit External Address Bus P:$1F FFFF External Program Memory5 External Program Memory5 External Program Memory5 P:$10 0000 P:$0F FFFF P:$03 0000 P:$02 FFFF On-Chip Program RAM P:$02 F800 4KB P:$02 F7FF Reserved P:$02 2000 116KB External Program RAM P:$02 1FFF Boot Flash Boot Flash P:$02 0000 16KB 16KB COP Reset Address = 02 00026 COP Reset Address = 02 0002 (Not Used for Boot in this Mode) Boot Location = 02 00006 Boot Location = 02 0000 P:$01 FFFF Internal Program Flash7 Internal Program Flash P:$01 0000 128KB 128KB P:$00 FFFF Internal Program Flash7 External Program RAM P:$00 0000 128KB COP Reset Address = 00 0002 Boot Location = 00 0000 1. If Flash Security Mode is enabled, EXTBOOT Mode 1 cannot be used. See Security Features, Part 7. 2. This mode provides maximum compatibility with 56F80x parts while operating externally. 3. “EMI_MODE =0” when EMI_MODE pin is tied to ground at boot up. 4. “EMI_MODE =1” when EMI_MODE pin is tied to V at boot up. DD 5. Not accessible in reset configuration, since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip selects) pins must be reconfigured before this external memory is accessible. 6. Booting from this external address allows prototyping of the internal Boot Flash. 7. Two independent program flash blocks allow one to be programmed/erased while executing from another. Each block must have its own mass erase. 4.3 Interrupt Vector Table Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 43 Preliminary

organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The priority of an interrupt can be assigned to different levels, as indicated, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part 5.6.12 for the reset value of the VBA. In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the 56F8156 device. Table 4-5 Interrupt Vector Table Contents1 Vector Priority Vector Base Peripheral Interrupt Function Number Level Address + Reserved for Reset Overlay2 Reserved for COP Reset Overlay2 core 2 3 P:$04 Illegal Instruction core 3 3 P:$06 SW Interrupt 3 core 4 3 P:$08 HW Stack Overflow core 5 3 P:$0A Misaligned Long Word Access core 6 1-3 P:$0C OnCE Step Counter core 7 1-3 P:$0E OnCE Breakpoint Unit 0 Reserved core 9 1-3 P:$12 OnCE Trace Buffer core 10 1-3 P:$14 OnCE Transmit Register Empty core 11 1-3 P:$16 OnCE Receive Register Full Reserved core 14 2 P:$1C SW Interrupt 2 core 15 1 P:$1E SW Interrupt 1 core 16 0 P:$20 SW Interrupt 0 core 17 0-2 P:$22 IRQA core 18 0-2 P:$24 IRQB Reserved LVI 20 0-2 P:$28 Low-Voltage Detector (power sense) 56F8356 Technical Data, Rev. 13 44 Freescale Semiconductor Preliminary

Interrupt Vector Table Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Priority Vector Base Peripheral Interrupt Function Number Level Address + PLL 21 0-2 P:$2A PLL FM 22 0-2 P:$2C FM Access Error Interrupt FM 23 0-2 P:$2E FM Command Complete FM 24 0-2 P:$30 FM Command, data and address Buffers Empty Reserved FLEXCAN 26 0-2 P:$34 FLEXCAN Bus Off FLEXCAN 27 0-2 P:$36 FLEXCAN Error FLEXCAN 28 0-2 P:$38 FLEXCAN Wake Up FLEXCAN 29 0-2 P:$3A FLEXCAN Message Buffer Interrupt GPIOF 30 0-2 P:$3C GPIOF GPIOE 31 0-2 P:$3E GPIOE GPIOD 32 0-2 P:$40 GPIOD GPIOC 33 0-2 P:$42 GPIOC GPIOB 34 0-2 P:$44 GPIOB GPIOA 35 0-2 P:$46 GPIOA Reserved SPI1 38 0-2 P:$4C SPI 1 Receiver Full SPI1 39 0-2 P:$4E SPI 1 Transmitter Empty SPI0 40 0-2 P:$50 SPI 0 Receiver Full SPI0 41 0-2 P:$52 SPI 0 Transmitter Empty SCI1 42 0-2 P:$54 SCI 1 Transmitter Empty SCI1 43 0-2 P:$56 SCI 1 Transmitter Idle Reserved SCI1 45 0-2 P:$5A SCI 1 Receiver Error SCI1 46 0-2 P:$5C SCI 1 Receiver Full DEC1 47 0-2 P:$5E Quadrature Decoder #1 Home Switch or Watchdog DEC1 48 0-2 P:$60 Quadrature Decoder #1 INDEX Pulse DEC0 49 0-2 P:$62 Quadrature Decoder #0 Home Switch or Watchdog DEC0 50 0-2 P:$64 Quadrature Decoder #0 INDEX Pulse Reserved 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 45 Preliminary

Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Priority Vector Base Peripheral Interrupt Function Number Level Address + TMRD 52 0-2 P:$68 Timer D, Channel 0 TMRD 53 0-2 P:$6A Timer D, Channel 1 TMRD 54 0-2 P:$6C Timer D, Channel 2 TMRD 55 0-2 P:$6E Timer D, Channel 3 TMRC 56 0-2 P:$70 Timer C, Channel 0 TMRC 57 0-2 P:$72 Timer C, Channel 1 TMRC 58 0-2 P:$74 Timer C, Channel 2 TMRC 59 0-2 P:$76 Timer C, Channel 3 TMRB 60 0-2 P:$78 Timer B, Channel 0 TMRB 61 0-2 P:$7A Timer B, Channel 1 TMRB 62 0-2 P:$7C Timer B, Channel 2 TMRB 63 0-2 P:$7E Timer B, Channel 3 TMRA 64 0-2 P:$80 Timer A, Channel 0 TMRA 65 0-2 P:$82 Timer A, Channel 1 TMRA 66 0-2 P:$84 Timer A, Channel 2 TMRA 67 0-2 P:$86 Timer A, Channel 3 SCI0 68 0-2 P:$88 SCI 0 Transmitter Empty SCI0 69 0-2 P:$8A SCI 0 Transmitter Idle Reserved SCI0 71 0-2 P:$8E SCI 0 Receiver Error SCI0 72 0-2 P:$90 SCI 0 Receiver Full ADCB 73 0-2 P:$92 ADC B Conversion Compete / End of Scan ADCA 74 0-2 P:$94 ADC A Conversion Complete / End of Scan ADCB 75 0-2 P:$96 ADC B Zero Crossing or Limit Error ADCA 76 0-2 P:$98 ADC A Zero Crossing or Limit Error PWMB 77 0-2 P:$9A Reload PWM B PWMA 78 0-2 P:$9C Reload PWM A PWMB 79 0-2 P:$9E PWM B Fault PWMA 80 0-2 P:$A0 PWM A Fault core 81 - 1 P:$A2 SW Interrupt LP 56F8356 Technical Data, Rev. 13 46 Freescale Semiconductor Preliminary

Data Map 1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. If the VBA is set to $0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are the chip reset addresses; therefore, these locations are not interrupt vectors. 2. 4.4 Data Map Note: Data Flash is NOT available on the 56F8156 device. Table 4-6 Data Memory Map1 Begin/End EX = 02 EX = 1 Address X:$FF FFFF EOnCE EOnCE X:$FF FF00 256 locations allocated 256 locations allocated X:$FF FEFF External Memory External Memory X:$01 0000 X:$00 FFFF On-Chip Peripherals On-Chip Peripherals X:$00 F000 4096 locations allocated 4096 locations allocated X:$00 EFFF External Memory External Memory X:$00 3000 X:$00 2FFF On-Chip Data Flash X:$00 2000 8KB X:$00 1FFF On-Chip Data RAM X:$00 0000 16KB3 1. All addresses are 16-bit Word addresses, not byte addresses. 2. In the Operating Mode Register (OMR). 3. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle long-word operations. 4.5 Flash Memory Map Figure 4-1 illustrates the Flash Memory (FM) map on the system bus. The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 47 Preliminary

on the Data Memory buses and is controlled separately by its own set of banked registers. The top nine words of the Program Memory Flash are treated as special memory locations. The content of these words is used to control the operation of the Flash Controller. Because these words are part of the Flash Memory content, their state is maintained during power-down and reset. During chip initialization, the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual. These configuration parameters are located between $01_FFF7 and $01_FFFF. Program Memory Data Memory BOOT_FLASH_START + $1FFF 16KB FM_BASE + $14 Banked Registers Boot Unbanked Registers BOOT_FLASH_START = $20_0000 FM_BASE + $00 PROG_FLASH_START + $01_FFFF Configure Field FM_PROG_MEM_TOP = $01_FFFF PROG_FLASH_START + $01_FFF7 PROG_FLASH_START + $01_FFF6 DATA_FLASH_START + $0FFF 128KB 8KB Program DATA_FLASH_START + $0000 Note: Data Flash is BLOCK 1 Odd (2 Bytes) $01_0003 BLOCK 1 Even (2 Bytes) $01_0002 NOT available in the BLOCK 1 Odd (2 Bytes) $01_0001 56F8156 device. PROG_FLASH_START + $01_0000 BLOCK 1 Even (2 Bytes) $01_0000 PROG_FLASH_START + $00_FFFF 128KB Program BLOCK 0 Odd (2 Bytes) $00_0003 BLOCK 0 Even (2 Bytes) $00_0002 BLOCK 0 Odd (2 Bytes) $00_0001 BLOCK 0 Even (2 Bytes) $00_0000 PROG_FLASH_START = $00_0000 Figure 4-1 Flash Array Memory Maps Table 4-7 shows the page and sector sizes used within each Flash memory block on the chip. Note: Data Flash is NOT available in the 56F8156 device. Table 4-7. Flash Memory Partitions Flash Size Sectors Sector Size Page Size Program Flash 256KB 16 8K x 16 bits 512 x 16 bits Data Flash 8KB 16 256 x 16 bits 256 x 16 bits Boot Flash 16KB 4 2K x 16 bits 256 x 16 bits Please see 56F8300 Peripheral User Manual for additional Flash information. 56F8356 Technical Data, Rev. 13 48 Freescale Semiconductor Preliminary

EOnCE Memory Map 4.6 EOnCE Memory Map Table 4-8 EOnCE Memory Map Address Register Acronym Register Name Reserved X:$FF FF8A OESCR External Signal Control Register Reserved X:$FF FF8E OBCNTR Breakpoint Unit [0] Counter Reserved X:$FF FF90 OBMSK (32 bits) Breakpoint 1 Unit [0] Mask Register X:$FF FF91 — Breakpoint 1 Unit [0] Mask Register X:$FF FF92 OBAR2 (32 bits) Breakpoint 2 Unit [0] Address Register X:$FF FF93 — Breakpoint 2 Unit [0] Address Register X:$FF FF94 OBAR1 (24 bits) Breakpoint 1 Unit [0] Address Register X:$FF FF95 — Breakpoint 1 Unit [0] Address Register X:$FF FF96 OBCR (24 bits) Breakpoint Unit [0] Control Register X:$FF FF97 — Breakpoint Unit [0] Control Register X:$FF FF98 OTB (21-24 bits/stage) Trace Buffer Register Stages X:$FF FF99 — Trace Buffer Register Stages X:$FF FF9A OTBPR (8 bits) Trace Buffer Pointer Register X:$FF FF9B OTBCR Trace Buffer Control Register X:$FF FF9C OBASE (8 bits) Peripheral Base Address Register X:$FF FF9D OSR Status Register X:$FF FF9E OSCNTR (24 bits) Instruction Step Counter X:$FF FF9F — Instruction Step Counter :X:$FF FFA0 OCR (bits) Control Register Reserved X:$FF FFFC OCLSR (8 bits) Core Lock / Unlock Status Register X:$FF FFFD OTXRXSR (8 bits) Transmit and Receive Status and Control Register X:$FF FFFE OTX / ORX (32 bits) Transmit Register / Receive Register X:$FF FFFF OTX1 / ORX1 Transmit Register Upper Word Receive Register Upper Word 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 49 Preliminary

4.7 Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read/written using word accesses only. Table 4-9 summarizes base addresses for the set of peripherals on the 56F8356 and 56F8156 devices. Peripherals are listed in order of the base address. The following tables list all of the peripheral registers required to control or access the peripherals. Note: Features in italics are NOT available in the 56F8156 device. Table 4-9 Data Memory Peripheral Base Address Map Summary Peripheral Prefix Base Address Table Number External Memory Interface EMI X:$00 F020 4-10 Timer A TMRA X:$00 F040 4-11 Timer B TMRB X:$00 F080 4-12 Timer C TMRC X:$00 F0C0 4-13 Timer D TMRD X:$00 F100 4-14 PWM A PWMA X:$00 F140 4-15 PWM B PWMB X:$00 F160 4-16 Quadrature Decoder 0 DEC0 X:$00 F180 4-17 Quadrature Decoder 1 DEC1 X:$00 F190 4-18 ITCN ITCN X:$00 F1A0 4-19 ADC A ADCA X:$00 F200 4-20 ADC B ADCB X:$00 F240 4-21 Temperature Sensor TSENSOR X:$00 F270 4-22 SCI #0 SCI0 X:$00 F280 4-23 SCI #1 SCI1 X:$00 F290 4-24 SPI #0 SPI0 X:$00 F2A0 4-25 SPI #1 SPI1 X:$00 F2B0 4-26 COP COP X:$00 F2C0 4-27 PLL, OSC CLKGEN X:$00 F2D0 4-28 GPIO Port A GPIOA X:$00 F2E0 4-29 GPIO Port B GPIOB X:$00 F300 4-30 GPIO Port C GPIOC X:$00 F310 4-31 GPIO Port D GPIOD X:$00 F320 4-32 56F8356 Technical Data, Rev. 13 50 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral Prefix Base Address Table Number GPIO Port E GPIOE X:$00 F330 4-33 GPIO Port F GPIOF X:$00 F340 4-34 SIM SIM X:$00 F350 4-35 Power Supervisor LVI X:$00 F360 4-36 FM FM X:$00 F400 4-37 FlexCAN FC X:$00 F800 4-38 Table 4-10 External Memory Integration Registers Address Map (EMI_BASE = $00 F020) Register Acronym Address Offset Register Description Reset Value CSBAR 0 $0 Chip Select Base Address Register 0 0x0004 = 64K when EXT_BOOT=0 or EMI_MODE= 0 0x0008 = 1M when EMI_MODE=1 (Selects entire program space for CS0) Note that A17-A19 are not available in the package CSBAR 1 $1 Chip Select Base Address Register 1 0x0004 = 64K when EMI_MODE=0 0x0008 = 1M when EMI_MODE=1 (Selects A0-A19 addressable data space for CS1) Note that A17-A19 are not available in the package CSBAR 2 $2 Chip Select Base Address Register 2 CSBAR 3 $3 Chip Select Base Address Register 3 CSBAR 4 $4 Chip Select Base Address Register 4 CSBAR 5 $5 Chip Select Base Address Register 5 CSBAR 6 $6 Chip Select Base Address Register 6 CSBAR 7 $7 Chip Select Base Address Register 7 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 51 Preliminary

Table 4-10 External Memory Integration Registers Address Map (Continued) (EMI_BASE = $00 F020) Register Acronym Address Offset Register Description Reset Value CSOR 0 $8 Chip Select Option Register 0 0x5FCB programmed for chip select for program space, word wide, read and write, 11 waits CSOR 1 $9 Chip Select Option Register 1 0x5FAB programmed for chip select for data space, word wide, read and write, 11 waits CSOR 2 $A Chip Select Option Register 2 CSOR 3 $B Chip Select Option Register 3 CSOR 4 $C Chip Select Option Register 4 CSOR 5 $D Chip Select Option Register 5 CSOR 6 $E Chip Select Option Register 6 CSOR 7 $F Chip Select Option Register 7 CSTC 0 $10 Chip Select Timing Control Register 0 CSTC 1 $11 Chip Select Timing Control Register 1 CSTC 2 $12 Chip Select Timing Control Register 2 CSTC 3 $13 Chip Select Timing Control Register 3 CSTC 4 $14 Chip Select Timing Control Register 4 CSTC 5 $15 Chip Select Timing Control Register 5 CSTC 6 $16 Chip Select Timing Control Register 6 CSTC 7 $17 Chip Select Timing Control Register 7 BCR $18 Bus Control Register 0x016B sets the default number of wait states to 11 for both read and write accesses Table 4-11 Quad Timer A Registers Address Map (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA0_CMP1 $0 Compare Register 1 TMRA0_CMP2 $1 Compare Register 2 TMRA0_CAP $2 Capture Register TMRA0_LOAD $3 Load Register TMRA0_HOLD $4 Hold Register TMRA0_CNTR $5 Counter Register TMRA0_CTRL $6 Control Register 56F8356 Technical Data, Rev. 13 52 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA0_SCR $7 Status and Control Register TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comparator Load Register 2 TMRA0_COMSCR $A Comparator Status and Control Register Reserve TMRA1_CMP1 $10 Compare Register 1 TMRA1_CMP2 $11 Compare Register 2 TMRA1_CAP $12 Capture Register TMRA1_LOAD $13 Load Register TMRA1_HOLD $14 Hold Register TMRA1_CNTR $15 Counter Register TMRA1_CTRL $16 Control Register TMRA1_SCR $17 Status and Control Register TMRA1_CMPLD1 $18 Comparator Load Register 1 TMRA1_CMPLD2 $19 Comparator Load Register 2 TMRA1_COMSCR $1A Comparator Status and Control Register Reserved TMRA2_CMP1 $20 Compare Register 1 TMRA2_CMP2 $21 Compare Register 2 TMRA2_CAP $22 Capture Register TMRA2_LOAD $23 Load Register TMRA2_HOLD $24 Hold Register TMRA2_CNTR $25 Counter Register TMRA2_CTRL $26 Control Register TMRA2_SCR $27 Status and Control Register TMRA2_CMPLD1 $28 Comparator Load Register 1 TMRA2_CMPLD2 $29 Comparator Load Register 2 TMRA2_COMSCR $2A Comparator Status and Control Register Reserved TMRA3_CMP1 $30 Compare Register 1 TMRA3_CMP2 $31 Compare Register 2 TMRA3_CAP $32 Capture Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 53 Preliminary

Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA3_LOAD $33 Load Register TMRA3_HOLD $34 Hold Register TMRA3_CNTR $35 Counter Register TMRA3_CTRL $36 Control Register TMRA3_SCR $37 Status and Control Register TMRA3_CMPLD1 $38 Comparator Load Register 1 TMRA3_CMPLD2 $39 Comparator Load Register 2 TMRA3_COMSC $3A Comparator Status and Control Register Table 4-12 Quad Timer B Registers Address Map (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8156 device Register Acronym Address Offset Register Description TMRB0_CMP1 $0 Compare Register 1 TMRB0_CMP2 $1 Compare Register 2 TMRB0_CAP $2 Capture Register TMRB0_LOAD $3 Load Register TMRB0_HOLD $4 Hold Register TMRB0_CNTR $5 Counter Register TMRB0_CTRL $6 Control Register TMRB0_SCR $7 Status and Control Register TMRB0_CMPLD1 $8 Comparator Load Register 1 TMRB0_CMPLD2 $9 Comparator Load Register 2 TMRB0_COMSCR $A Comparator Status and Control Register Reserved TMRB1_CMP1 $10 Compare Register 1 TMRB1_CMP2 $11 Compare Register 2 TMRB1_CAP $12 Capture Register TMRB1_LOAD $13 Load Register TMRB1_HOLD $14 Hold Register TMRB1_CNTR $15 Counter Register TMRB1_CTRL $16 Control Register 56F8356 Technical Data, Rev. 13 54 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-12 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8156 device Register Acronym Address Offset Register Description TMRB1_SCR $17 Status and Control Register TMRB1_CMPLD1 $18 Comparator Load Register 1 TMRB1_CMPLD2 $19 Comparator Load Register 2 TMRB1_COMSCR $1A Comparator Status and Control Register Reserved TMRB2_CMP1 $20 Compare Register 1 TMRB2_CMP2 $21 Compare Register 2 TMRB2_CAP $22 Capture Register TMRB2_LOAD $23 Load Register TMRB2_HOLD $24 Hold Register TMRB2_CNTR $25 Counter Register TMRB2_CTRL $26 Control Register TMRB2_SCR $27 Status and Control Register TMRB2_CMPLD1 $28 Comparator Load Register 1 TMRB2_CMPLD2 $29 Comparator Load Register 2 TMRB2_COMSCR $2A Comparator Status and Control Register Reserved TMRB3_CMP1 $30 Compare Register 1 TMRB3_CMP2 $31 Compare Register 2 TMRB3_CAP $32 Capture Register TMRB3_LOAD $33 Load Register TMRB3_HOLD $34 Hold Register TMRB3_CNTR $35 Counter Register TMRB3_CTRL $36 Control Register TMRB3_SCR $37 Status and Control Register TMRB3_CMPLD1 $38 Comparator Load Register 1 TMRB3_CMPLD2 $39 Comparator Load Register 2 TMRB3_COMSCR $3A Comparator Status and Control Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 55 Preliminary

Table 4-13 Quad Timer C Registers Address Map (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC0_CMP1 $0 Compare Register 1 TMRC0_CMP2 $1 Compare Register 2 TMRC0_CAP $2 Capture Register TMRC0_LOAD $3 Load Register TMRC0_HOLD $4 Hold Register TMRC0_CNTR $5 Counter Register TMRC0_CTRL $6 Control Register TMRC0_SCR $7 Status and Control Register TMRC0_CMPLD1 $8 Comparator Load Register 1 TMRC0_CMPLD2 $9 Comparator Load Register 2 TMRC0_COMSCR $A Comparator Status and Control Register Reserved TMRC1_CMP1 $10 Compare Register 1 TMRC1_CMP2 $11 Compare Register 2 TMRC1_CAP $12 Capture Register TMRC1_LOAD $13 Load Register TMRC1_HOLD $14 Hold Register TMRC1_CNTR $15 Counter Register TMRC1_CTRL $16 Control Register TMRC1_SCR $17 Status and Control Register TMRC1_CMPLD1 $18 Comparator Load Register 1 TMRC1_CMPLD2 $19 Comparator Load Register 2 TMRC1_COMSCR $1A Comparator Status and Control Register Reserved TMRC2_CMP1 $20 Compare Register 1 TMRC2_CMP2 $21 Compare Register 2 TMRC2_CAP $22 Capture Register TMRC2_LOAD $23 Load Register TMRC2_HOLD $24 Hold Register TMRC2_CNTR $25 Counter Register TMRC2_CTRL $26 Control Register 56F8356 Technical Data, Rev. 13 56 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-13 Quad Timer C Registers Address Map (Continued) (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC2_SCR $27 Status and Control Register TMRC2_CMPLD1 $28 Comparator Load Register 1 TMRC2_CMPLD2 $29 Comparator Load Register 2 TMRC2_COMSCR $2A Comparator Status and Control Register Reserved TMRC3_CMP1 $30 Compare Register 1 TMRC3_CMP2 $31 Compare Register 2 TMRC3_CAP $32 Capture Register TMRC3_LOAD $33 Load Register TMRC3_HOLD $34 Hold Register TMRC3_CNTR $35 Counter Register TMRC3_CTRL $36 Control Register TMRC3_SCR $37 Status and Control Register TMRC3_CMPLD1 $38 Comparator Load Register 1 TMRC3_CMPLD2 $39 Comparator Load Register 2 TMRC3_COMSCR $3A Comparator Status and Control Register Table 4-14 Quad Timer D Registers Address Map (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8156 device Register Acronym Address Offset Register Description TMRD0_CMP1 $0 Compare Register 1 TMRD0_CMP2 $1 Compare Register 2 TMRD0_CAP $2 Capture Register TMRD0_LOAD $3 Load Register TMRD0_HOLD $4 Hold Register TMRD0_CNTR $5 Counter Register TMRD0_CTRL $6 Control Register TMRD0_SCR $7 Status and Control Register TMRD0_CMPLD1 $8 Comparator Load Register 1 TMRD0_CMPLD2 $9 Comparator Load Register 2 TMRD0_COMSCR $A Comparator Status and Control Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 57 Preliminary

Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8156 device Register Acronym Address Offset Register Description Reserved TMRD1_CMP1 $10 Compare Register 1 TMRD1_CMP2 $11 Compare Register 2 TMRD1_CAP $12 Capture Register TMRD1_LOAD $13 Load Register TMRD1_HOLD $14 Hold Register TMRD1_CNTR $15 Counter Register TMRD1_CTRL $16 Control Register TMRD1_SCR $17 Status and Control Register TMRD1_CMPLD1 $18 Comparator Load Register 1 TMRD1_CMPLD2 $19 Comparator Load Register 2 TMRD1_COMSCR $1A Comparator Status and Control Register Reserved TMRD2_CMP1 $20 Compare Register 1 TMRD2_CMP2 $21 Compare Register 2 TMRD2_CAP $22 Capture Register TMRD2_LOAD $23 Load Register TMRD2_HOLD $24 Hold Register TMRD2_CNTR $25 Counter Register TMRD2_CTRL $26 Control Register TMRD2_SCR $27 Status and Control Register TMRD2_CMPLD1 $28 Comparator Load Register 1 TMRD2_CMPLD2 $29 Comparator Load Register 2 TMRD2_COMSCR $2A Comparator Status and Control Register Reserved TMRD3_CMP1 $30 Compare Register 1 TMRD3_CMP2 $31 Compare Register 2 TMRD3_CAP $32 Capture Register TMRD3_LOAD $33 Load Register TMRD3_HOLD $34 Hold Register TMRD3_CNTR $35 Counter Register 56F8356 Technical Data, Rev. 13 58 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8156 device Register Acronym Address Offset Register Description TMRD3_CTRL $36 Control Register TMRD3_SCR $37 Status and Control Register TMRD3_CMPLD1 $38 Comparator Load Register 1 TMRD3_CMPLD2 $39 Comparator Load Register 2 TMRD3_COMSCR $3A Comparator Status and Control Register Table 4-15 Pulse Width Modulator A Registers Address Map (PWMA_BASE = $00 F140) PWMA is NOT available in the 56F8156 device Register Acronym Address Offset Register Description PWMA_PMCTL $0 Control Register PWMA_PMFCTL $1 Fault Control Register PWMA_PMFSA $2 Fault Status Acknowledge Register PWMA_PMOUT $3 Output Control Register PWMA_PMCNT $4 Counter Register PWMA_PWMCM $5 Counter Modulo Register PWMA_PWMVAL0 $6 Value Register 0 PWMA_PWMVAL1 $7 Value Register 1 PWMA_PWMVAL2 $8 Value Register 2 PWMA_PWMVAL3 $9 Value Register 3 PWMA_PWMVAL4 $A Value Register 4 PWMA_PWMVAL5 $B Value Register 5 PWMA_PMDEADTM $C Dead Time Register PWMA_PMDISMAP1 $D Disable Mapping Register 1 PWMA_PMDISMAP2 $E Disable Mapping Register 2 PWMA_PMCFG $F Configure Register PWMA_PMCCR $10 Channel Control Register PWMA_PMPORT $11 Port Register PWMA_PMICCR $12 PWM Internal Correction Control Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 59 Preliminary

Table 4-16 Pulse Width Modulator B Registers Address Map (PWMB_BASE = $00 F160) Register Acronym Address Offset Register Description PWMB_PMCTL $0 Control Register PWMB_PMFCTL $1 Fault Control Register PWMB_PMFSA $2 Fault Status Acknowledge Register PWMB_PMOUT $3 Output Control Register PWMB_PMCNT $4 Counter Register PWMB_PWMCM $5 Counter Modulo Register PWMB_PWMVAL0 $6 Value Register 0 PWMB_PWMVAL1 $7 Value Register 1 PWMB_PWMVAL2 $8 Value Register 2 PWMB_PWMVAL3 $9 Value Register 3 PWMB_PWMVAL4 $A Value Register 4 PWMB_PWMVAL5 $B Value Register 5 PWMB_PMDEADTM $C Dead Time Register PWMB_PMDISMAP1 $D Disable Mapping Register 1 PWMB_PMDISMAP2 $E Disable Mapping Register 2 PWMB_PMCFG $F Configure Register PWMB_PMCCR $10 Channel Control Register PWMB_PMPORT $11 Port Register PWMB_PMICCR $12 PWM Internal Correction Control Register Table 4-17 Quadrature Decoder 0 Registers Address Map (DEC0_BASE = $00 F180) Register Acronym Address Offset Register Description DEC0_DECCR $0 Decoder Control Register DEC0_FIR $1 Filter Interval Register DEC0_WTR $2 Watchdog Time-out Register DEC0_POSD $3 Position Difference Counter Register 56F8356 Technical Data, Rev. 13 60 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-17 Quadrature Decoder 0 Registers Address Map (Continued) (DEC0_BASE = $00 F180) Register Acronym Address Offset Register Description DEC0_POSDH $4 Position Difference Counter Hold Register DEC0_REV $5 Revolution Counter Register DEC0_REVH $6 Revolution Hold Register DEC0_UPOS $7 Upper Position Counter Register DEC0_LPOS $8 Lower Position Counter Register DEC0_UPOSH $9 Upper Position Hold Register DEC0_LPOSH $A Lower Position Hold Register DEC0_UIR $B Upper Initialization Register DEC0_LIR $C Lower Initialization Register DEC0_IMR $D Input Monitor Register Table 4-18 Quadrature Decoder 1 Registers Address Map (DEC1_BASE = $00 F190) Quadrature Decoder 1 is NOT available in the 56F8156 device Register Acronym Address Offset Register Description DEC1_DECCR $0 Decoder Control Register DEC1_FIR $1 Filter Interval Register DEC1_WTR $2 Watchdog Time-out Register DEC1_POSD $3 Position Difference Counter Register DEC1_POSDH $4 Position Difference Counter Hold Register DEC1_REV $5 Revolution Counter Register DEC1_REVH $6 Revolution Hold Register DEC1_UPOS $7 Upper Position Counter Register DEC1_LPOS $8 Lower Position Counter Register DEC1_UPOSH $9 Upper Position Hold Register DEC1_LPOSH $A Lower Position Hold Register DEC1_UIR $B Upper Initialization Register DEC1_LIR $C Lower Initialization Register DEC1_IMR $D Input Monitor Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 61 Preliminary

Table 4-19 Interrupt Control Registers Address Map (ITCN_BASE = $00 F1A0) Register Acronym Address Offset Register Description IPR 0 $0 Interrupt Priority Register 0 IPR 1 $1 Interrupt Priority Register 1 IPR 2 $2 Interrupt Priority Register 2 IPR 3 $3 Interrupt Priority Register 3 IPR 4 $4 Interrupt Priority Register 4 IPR 5 $5 Interrupt Priority Register 5 IPR 6 $6 Interrupt Priority Register 6 IPR 7 $7 Interrupt Priority Register 7 IPR 8 $8 Interrupt Priority Register 8 IPR 9 $9 Interrupt Priority Register 9 VBA $A Vector Base Address Register FIM0 $B Fast Interrupt Match Register 0 FIVAL0 $C Fast Interrupt Vector Address Low 0 Register FIVAH0 $D Fast Interrupt Vector Address High 0 Register FIM1 $E Fast Interrupt Match Register 1 FIVAL1 $F Fast Interrupt Vector Address Low 1 Register FIVAH1 $10 Fast Interrupt Vector Address High 1 Register IRQP 0 $11 IRQ Pending Register 0 IRQP 1 $12 IRQ Pending Register 1 IRQP 2 $13 IRQ Pending Register 2 IRQP 3 $14 IRQ Pending Register 3 IRQP 4 $15 IRQ Pending Register 4 IRQP 5 $16 IRQ Pending Register 5 Reserved ICTL $1D Interrupt Control Register Table 4-20 Analog-to-Digital Converter Registers Address Map (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_CR 1 $0 Control Register 1 56F8356 Technical Data, Rev. 13 62 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_CR 2 $1 Control Register 2 ADCA_ZCC $2 Zero Crossing Control Register ADCA_LST 1 $3 Channel List Register 1 ADCA_LST 2 $4 Channel List Register 2 ADCA_SDIS $5 Sample Disable Register ADCA_STAT $6 Status Register ADCA_LSTAT $7 Limit Status Register ADCA_ZCSTAT $8 Zero Crossing Status Register ADCA_RSLT 0 $9 Result Register 0 ADCA_RSLT 1 $A Result Register 1 ADCA_RSLT 2 $B Result Register 2 ADCA_RSLT 3 $C Result Register 3 ADCA_RSLT 4 $D Result Register 4 ADCA_RSLT 5 $E Result Register 5 ADCA_RSLT 6 $F Result Register 6 ADCA_RSLT 7 $10 Result Register 7 ADCA_LLMT 0 $11 Low Limit Register 0 ADCA_LLMT 1 $12 Low Limit Register 1 ADCA_LLMT 2 $13 Low Limit Register 2 ADCA_LLMT 3 $14 Low Limit Register 3 ADCA_LLMT 4 $15 Low Limit Register 4 ADCA_LLMT 5 $16 Low Limit Register 5 ADCA_LLMT 6 $17 Low Limit Register 6 ADCA_LLMT 7 $18 Low Limit Register 7 ADCA_HLMT 0 $19 High Limit Register 0 ADCA_HLMT 1 $1A High Limit Register 1 ADCA_HLMT 2 $1B High Limit Register 2 ADCA_HLMT 3 $1C High Limit Register 3 ADCA_HLMT 4 $1D High Limit Register 4 ADCA_HLMT 5 $1E High Limit Register 5 ADCA_HLMT 6 $1F High Limit Register 6 ADCA_HLMT 7 $20 High Limit Register 7 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 63 Preliminary

Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_OFS 0 $21 Offset Register 0 ADCA_OFS 1 $22 Offset Register 1 ADCA_OFS 2 $23 Offset Register 2 ADCA_OFS 3 $24 Offset Register 3 ADCA_OFS 4 $25 Offset Register 4 ADCA_OFS 5 $26 Offset Register 5 ADCA_OFS 6 $27 Offset Register 6 ADCA_OFS 7 $28 Offset Register 7 ADCA_POWER $29 Power Control Register ADCA_CAL $2A ADC Calibration Register Table 4-21 Analog-to-Digital Converter Registers Address Map (ADCB_BASE = $00 F240) Register Acronym Address Offset Register Description ADCB_CR 1 $0 Control Register 1 ADCB_CR 2 $1 Control Register 2 ADCB_ZCC $2 Zero Crossing Control Register ADCB_LST 1 $3 Channel List Register 1 ADCB_LST 2 $4 Channel List Register 2 ADCB_SDIS $5 Sample Disable Register ADCB_STAT $6 Status Register ADCB_LSTAT $7 Limit Status Register ADCB_ZCSTAT $8 Zero Crossing Status Register ADCB_RSLT 0 $9 Result Register 0 ADCB_RSLT 1 $A Result Register 1 ADCB_RSLT 2 $B Result Register 2 ADCB_RSLT 3 $C Result Register 3 ADCB_RSLT 4 $D Result Register 4 ADCB_RSLT 5 $E Result Register 5 ADCB_RSLT 6 $F Result Register 6 ADCB_RSLT 7 $10 Result Register 7 ADCB_LLMT 0 $11 Low Limit Register 0 56F8356 Technical Data, Rev. 13 64 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) (ADCB_BASE = $00 F240) Register Acronym Address Offset Register Description ADCB_LLMT 1 $12 Low Limit Register 1 ADCB_LLMT 2 $13 Low Limit Register 2 ADCB_LLMT 3 $14 Low Limit Register 3 ADCB_LLMT 4 $15 Low Limit Register 4 ADCB_LLMT 5 $16 Low Limit Register 5 ADCB_LLMT 6 $17 Low Limit Register 6 ADCB_LLMT 7 $18 Low Limit Register 7 ADCB_HLMT 0 $19 High Limit Register 0 ADCB_HLMT 1 $1A High Limit Register 1 ADCB_HLMT 2 $1B High Limit Register 2 ADCB_HLMT 3 $1C High Limit Register 3 ADCB_HLMT 4 $1D High Limit Register 4 ADCB_HLMT 5 $1E High Limit Register 5 ADCB_HLMT 6 $1F High Limit Register 6 ADCB_HLMT 7 $20 High Limit Register 7 ADCB_OFS 0 $21 Offset Register 0 ADCB_OFS 1 $22 Offset Register 1 ADCB_OFS 2 $23 Offset Register 2 ADCB_OFS 3 $24 Offset Register 3 ADCB_OFS 4 $25 Offset Register 4 ADCB_OFS 5 $26 Offset Register 5 ADCB_OFS 6 $27 Offset Register 6 ADCB_OFS 7 $28 Offset Register 7 ADCB_POWER $29 Power Control Register ADCB_CAL $2A ADC Calibration Register Table 4-22 Temperature Sensor Register Address Map (TSENSOR_BASE = $00 F270) Temperature Sensor is NOT available in the 56F8156 device Register Acronym Address Offset Register Description TSENSOR_CNTL $0 Control Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 65 Preliminary

Table 4-23 Serial Communication Interface 0 Registers Address Map (SCI0_BASE = $00 F280) Register Acronym Address Offset Register Description SCI0_SCIBR $0 Baud Rate Register SCI0_SCICR $1 Control Register Reserved SCI0_SCISR $3 Status Register SCI0_SCIDR $4 Data Register Table 4-24 Serial Communication Interface 1 Registers Address Map (SCI1_BASE = $00 F290) Register Acronym Address Offset Register Description SCI1_SCIBR $0 Baud Rate Register SCI1_SCICR $1 Control Register Reserved SCI1_SCISR $3 Status Register SCI1_SCIDR $4 Data Register Table 4-25 Serial Peripheral Interface 0 Registers Address Map (SPI0_BASE = $00 F2A0) Register Acronym Address Offset Register Description SPI0_SPSCR $0 Status and Control Register SPI0_SPDSR $1 Data Size Register SPI0_SPDRR $2 Data Receive Register SPI0_SPDTR $3 Data Transmitter Register 56F8356 Technical Data, Rev. 13 66 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-26 Serial Peripheral Interface 1 Registers Address Map (SPI1_BASE = $00 F2B0) Register Acronym Address Offset Register Description SPI1_SPSCR $0 Status and Control Register SPI1_SPDSR $1 Data Size Register SPI1_SPDRR $2 Data Receive Register SPI1_SPDTR $3 Data Transmitter Register Table 4-27 Computer Operating Properly Registers Address Map (COP_BASE = $00 F2C0) Register Acronym Address Offset Register Description COPCTL $0 Control Register COPTO $1 Time Out Register COPCTR $2 Counter Register Table 4-28 Clock Generation Module Registers Address Map (CLKGEN_BASE = $00 F2D0) Register Acronym Address Offset Register Description PLLCR $0 Control Register PLLDB $1 Divide-By Register PLLSR $2 Status Register Reserved SHUTDOWN $4 Shutdown Register OSCTL $5 Oscillator Control Register Table 4-29 GPIOA Registers Address Map (GPIOA_BASE = $00 F2E0) Register Acronym Address Offset Register Description Reset Value GPIOA_PUR $0 Pull-up Enable Register 0 x 3FFF GPIOA_DR $1 Data Register 0 x 0000 GPIOA_DDR $2 Data Direction Register 0 x 0000 GPIOA_PER $3 Peripheral Enable Register 0 x 3FFF GPIOA_IAR $4 Interrupt Assert Register 0 x 0000 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 67 Preliminary

Table 4-29 GPIOA Registers Address Map (Continued) (GPIOA_BASE = $00 F2E0) Register Acronym Address Offset Register Description Reset Value GPIOA_IENR $5 Interrupt Enable Register 0 x 0000 GPIOA_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOA_IPR $7 Interrupt Pending Register 0 x 0000 GPIOA_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOA_PPMODE $9 Push-Pull Mode Register 0 x 3FFF GPIOA_RAWDATA $A Raw Data Input Register — Table 4-30 GPIOB Registers Address Map (GPIOB_BASE = $00F300) Register Acronym Address Offset Register Description Reset Value GPIOB_PUR $0 Pull-up Enable Register 0 x 00FF GPIOB_DR $1 Data Register 0 x 0000 GPIOB_DDR $2 Data Direction Register 0 x 0000 GPIOB_PER $3 Peripheral Enable Register 0 x 000F for 20-bit EMI address at reset. 0 x 0000 for all other cases. See Table4-4 for details. GPIOB_IAR $4 Interrupt Assert Register 0 x 0000 GPIOB_IENR $5 Interrupt Enable Register 0 x 0000 GPIOB_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOB_IPR $7 Interrupt Pending Register 0 x 0000 GPIOB_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOB_PPMODE $9 Push-Pull Mode Register 0 x 00FF GPIOB_RAWDATA $A Raw Data Input Register — Table 4-31 GPIOC Registers Address Map (GPIOC_BASE = $00 F310) Register Acronym Address Offset Register Description Reset Value GPIOC_PUR $0 Pull-up Enable Register 0 x 07FF GPIOC_DR $1 Data Register 0 x 0000 GPIOC_DDR $2 Data Direction Register 0 x 0000 GPIOC_PER $3 Peripheral Enable Register 0 x 07FF 56F8356 Technical Data, Rev. 13 68 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-31 GPIOC Registers Address Map (Continued) (GPIOC_BASE = $00 F310) Register Acronym Address Offset Register Description Reset Value GPIOC_IAR $4 Interrupt Assert Register 0 x 0000 GPIOC_IENR $5 Interrupt Enable Register 0 x 0000 GPIOC_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOC_IPR $7 Interrupt Pending Register 0 x 0000 GPIOC_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOC_PPMODE $9 Push-Pull Mode Register 0 x 07FF GPIOC_RAWDATA $A Raw Data Input Register — Table 4-32 GPIOD Registers Address Map (GPIOD_BASE = $00 F320) Register Acronym Address Offset Register Description Reset Value GPIOD_PUR $0 Pull-up Enable Register 0 x 1FFF GPIOD_DR $1 Data Register 0 x 0000 GPIOD_DDR $2 Data Direction Register 0 x 0000 GPIOD_PER $3 Peripheral Enable Register 0 x 1FC0 GPIOD_IAR $4 Interrupt Assert Register 0 x 0000 GPIOD_IENR $5 Interrupt Enable Register 0 x 0000 GPIOD_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOD_IPR $7 Interrupt Pending Register 0 x 0000 GPIOD_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOD_PPMODE $9 Push-Pull Mode Register 0 x 1FFF GPIOD_RAWDATA $A Raw Data Input Register — Table 4-33 GPIOE Registers Address Map (GPIOE_BASE = $00 F330) Register Acronym Address Offset Register Description Reset Value GPIOE_PUR $0 Pull-up Enable Register 0 x 3FFF GPIOE_DR $1 Data Register 0 x 0000 GPIOE_DDR $2 Data Direction Register 0 x 0000 GPIOE_PER $3 Peripheral Enable Register 0 x 3FFF GPIOE_IAR $4 Interrupt Assert Register 0 x 0000 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 69 Preliminary

Table 4-33 GPIOE Registers Address Map (Continued) (GPIOE_BASE = $00 F330) Register Acronym Address Offset Register Description Reset Value GPIOE_IENR $5 Interrupt Enable Register 0 x 0000 GPIOE_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOE_IPR $7 Interrupt Pending Register 0 x 0000 GPIOE_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOE_PPMODE $9 Push-Pull Mode Register 0 x 3FFF GPIOE_RAWDATA $A Raw Data Input Register — Table 4-34 GPIOF Registers Address Map (GPIOF_BASE = $00 F340) Register Acronym Address Offset Register Description Reset Value GPIOF_PUR $0 Pull-up Enable Register 0 x FFFF GPIOF_DR $1 Data Register 0 x 0000 GPIOF_DDR $2 Data Direction Register 0 x 0000 GPIOF_PER $3 Peripheral Enable Register 0 x FFFF GPIOF_IAR $4 Interrupt Assert Register 0 x 0000 GPIOF_IENR $5 Interrupt Enable Register 0 x 0000 GPIOF_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOF_IPR $7 Interrupt Pending Register 0 x 0000 GPIOF_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOF_PPMODE $9 Push-Pull Mode Register 0 x FFFF GPIOF_RAWDATA $A Raw Data Input Register — 56F8356 Technical Data, Rev. 13 70 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-35 System Integration Module Registers Address Map (SIM_BASE = $00 F350) Register Acronym Address Offset Register Description SIM_CONTROL $0 Control Register SIM_RSTSTS $1 Reset Status Register SIM_SCR0 $2 Software Control Register 0 SIM_SCR1 $3 Software Control Register 1 SIM_SCR2 $4 Software Control Register 2 SIM_SCR3 $5 Software Control Register 3 SIM_MSH_ID $6 Most Significant Half JTAG ID SIM_LSH_ID $7 Least Significant Half JTAG ID SIM_PUDR $8 Pull-up Disable Register Reserved SIM_CLKOSR $A Clock Out Select Register SIM_GPS $B Quad Decoder 1 / Timer B / SPI 1 Select Register SIM_PCE $C Peripheral Clock Enable Register SIM_ISALH $D I/O Short Address Location High Register SIM_ISALL $E I/O Short Address Location Low Register Table 4-36 Power Supervisor Registers Address Map (LVI_BASE = $00 F360) Register Acronym Address Offset Register Description LVI_CONTROL $0 Control Register LVI_STATUS $1 Status Register Table 4-37 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FMCLKD $0 Clock Divider Register FMMCR $1 Module Control Register Reserved FMSECH $3 Security High Half Register FMSECL $4 Security Low Half Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 71 Preliminary

Table 4-37 Flash Module Registers Address Map (Continued) (FM_BASE = $00 F400) Register Acronym Address Offset Register Description Reserved Reserved FMPROT $10 Protection Register (Banked) FMPROTB $11 Protection Boot Register (Banked) Reserved FMUSTAT $13 User Status Register (Banked) FMCMD $14 Command Register (Banked) Reserved Reserved FMOPT 0 $1A 16-Bit Information Option Register 0 Hot temperature ADC reading of Temp Sense; value set during factory test FMOPT 1 $1B 16-Bit Information Option Register 1 Not used FMOPT 2 $1C 16-Bit Information Option Register 2 Room temperature ADC reading of Temp Sense; value set during factory test Table 4-38 FlexCAN Registers Address Map (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8156 device Register Acronym Address Offset Register Description FCMCR $0 Module Configuration Register Reserved FCCTL0 $3 Control Register 0 Register FCCTL1 $4 Control Register 1 Register FCTMR $5 Free-Running Timer Register FCMAXMB $6 Maximum Message Buffer Configuration Register Reserved FCRXGMASK_H $8 Receive Global Mask High Register FCRXGMASK_L $9 Receive Global Mask Low Register FCRX14MASK_H $A Receive Buffer 14 Mask High Register FCRX14MASK_L $B Receive Buffer 14 Mask Low Register FCRX15MASK_H $C Receive Buffer 15 Mask High Register 56F8356 Technical Data, Rev. 13 72 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8156 device Register Acronym Address Offset Register Description FCRX15MASK_L $D Receive Buffer 15 Mask Low Register Reserved FCSTATUS $10 Error and Status Register FCIMASK1 $11 Interrupt Masks 1 Register FCIFLAG1 $12 Interrupt Flags 1 Register FCR/T_ERROR_CNTRS $13 Receive and Transmit Error Counters Register Reserved Reserved Reserved FCMB0_CONTROL $40 Message Buffer 0 Control / Status Register FCMB0_ID_HIGH $41 Message Buffer 0 ID High Register FCMB0_ID_LOW $42 Message Buffer 0 ID Low Register FCMB0_DATA $43 Message Buffer 0 Data Register FCMB0_DATA $44 Message Buffer 0 Data Register FCMB0_DATA $45 Message Buffer 0 Data Register FCMB0_DATA $46 Message Buffer 0 Data Register Reserved FCMSB1_CONTROL $48 Message Buffer 1 Control / Status Register FCMSB1_ID_HIGH $49 Message Buffer 1 ID High Register FCMSB1_ID_LOW $4A Message Buffer 1 ID Low Register FCMB1_DATA $4B Message Buffer 1 Data Register FCMB1_DATA $4C Message Buffer 1 Data Register FCMB1_DATA $4D Message Buffer 1 Data Register FCMB1_DATA $4E Message Buffer 1 Data Register Reserved FCMB2_CONTROL $50 Message Buffer 2 Control / Status Register FCMB2_ID_HIGH $51 Message Buffer 2 ID High Register FCMB2_ID_LOW $52 Message Buffer 2 ID Low Register FCMB2_DATA $53 Message Buffer 2 Data Register FCMB2_DATA $54 Message Buffer 2 Data Register FCMB2_DATA $55 Message Buffer 2 Data Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 73 Preliminary

Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8156 device Register Acronym Address Offset Register Description FCMB2_DATA $56 Message Buffer 2 Data Register Reserved FCMB3_CONTROL $58 Message Buffer 3 Control / Status Register FCMB3_ID_HIGH $59 Message Buffer 3 ID High Register FCMB3_ID_LOW $5A Message Buffer 3 ID Low Register FCMB3_DATA $5B Message Buffer 3 Data Register FCMB3_DATA $5C Message Buffer 3 Data Register FCMB3_DATA $5D Message Buffer 3 Data Register FCMB3_DATA $5E Message Buffer 3 Data Register Reserved FCMB4_CONTROL $60 Message Buffer 4 Control / Status Register FCMB4_ID_HIGH $61 Message Buffer 4 ID High Register FCMB4_ID_LOW $62 Message Buffer 4 ID Low Register FCMB4_DATA $63 Message Buffer 4 Data Register FCMB4_DATA $64 Message Buffer 4 Data Register FCMB4_DATA $65 Message Buffer 4 Data Register FCMB4_DATA $66 Message Buffer 4 Data Register Reserved FCMB5_CONTROL $68 Message Buffer 5 Control / Status Register FCMB5_ID_HIGH $69 Message Buffer 5 ID High Register FCMB5_ID_LOW $6A Message Buffer 5 ID Low Register FCMB5_DATA $6B Message Buffer 5 Data Register FCMB5_DATA $6C Message Buffer 5 Data Register FCMB5_DATA $6D Message Buffer 5 Data Register FCMB5_DATA $6E Message Buffer 5 Data Register Reserved FCMB6_CONTROL $70 Message Buffer 6 Control / Status Register FCMB6_ID_HIGH $71 Message Buffer 6 ID High Register FCMB6_ID_LOW $72 Message Buffer 6 ID Low Register FCMB6_DATA $73 Message Buffer 6 Data Register FCMB6_DATA $74 Message Buffer 6 Data Register FCMB6_DATA $75 Message Buffer 6 Data Register 56F8356 Technical Data, Rev. 13 74 Freescale Semiconductor Preliminary

Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8156 device Register Acronym Address Offset Register Description FCMB6_DATA $76 Message Buffer 6 Data Register Reserved FCMB7_CONTROL $78 Message Buffer 7 Control / Status Register FCMB7_ID_HIGH $79 Message Buffer 7 ID High Register FCMB7_ID_LOW $7A Message Buffer 7 ID Low Register FCMB7_DATA $7B Message Buffer 7 Data Register FCMB7_DATA $7C Message Buffer 7 Data Register FCMB7_DATA $7D Message Buffer 7 Data Register FCMB7_DATA $7E Message Buffer 7 Data Register Reserved FCMB8_CONTROL $80 Message Buffer 8 Control / Status Register FCMB8_ID_HIGH $81 Message Buffer 8 ID High Register FCMB8_ID_LOW $82 Message Buffer 8 ID Low Register FCMB8_DATA $83 Message Buffer 8 Data Register FCMB8_DATA $84 Message Buffer 8 Data Register FCMB8_DATA $85 Message Buffer 8 Data Register FCMB8_DATA $86 Message Buffer 8 Data Register Reserved FCMB9_CONTROL $88 Message Buffer 9 Control / Status Register FCMB9_ID_HIGH $89 Message Buffer 9 ID High Register FCMB9_ID_LOW $8A Message Buffer 9 ID Low Register FCMB9_DATA $8B Message Buffer 9 Data Register FCMB9_DATA $8C Message Buffer 9 Data Register FCMB9_DATA $8D Message Buffer 9 Data Register FCMB9_DATA $8E Message Buffer 9 Data Register Reserved FCMB10_CONTROL $90 Message Buffer 10 Control / Status Register FCMB10_ID_HIGH $91 Message Buffer 10 ID High Register FCMB10_ID_LOW $92 Message Buffer 10 ID Low Register FCMB10_DATA $93 Message Buffer 10 Data Register FCMB10_DATA $94 Message Buffer 10 Data Register FCMB10_DATA $95 Message Buffer 10 Data Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 75 Preliminary

Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8156 device Register Acronym Address Offset Register Description FCMB10_DATA $96 Message Buffer 10 Data Register Reserved FCMB11_CONTROL $98 Message Buffer 11 Control / Status Register FCMB11_ID_HIGH $99 Message Buffer 11 ID High Register FCMB11_ID_LOW $9A Message Buffer 11 ID Low Register FCMB11_DATA $9B Message Buffer 11 Data Register FCMB11_DATA $9C Message Buffer 11 Data Register FCMB11_DATA $9D Message Buffer 11 Data Register FCMB11_DATA $9E Message Buffer 11 Data Register Reserved FCMB12_CONTROL $A0 Message Buffer 12 Control / Status Register FCMB12_ID_HIGH $A1 Message Buffer 12 ID High Register FCMB12_ID_LOW $A2 Message Buffer 12 ID Low Register FCMB12_DATA $A3 Message Buffer 12 Data Register FCMB12_DATA $A4 Message Buffer 12 Data Register FCMB12_DATA $A5 Message Buffer 12 Data Register FCMB12_DATA $A6 Message Buffer 12 Data Register Reserved FCMB13_CONTROL $A8 Message Buffer 13 Control / Status Register FCMB13_ID_HIGH $A9 Message Buffer 13 ID High Register FCMB13_ID_LOW $AA Message Buffer 13 ID Low Register FCMB13_DATA $AB Message Buffer 13 Data Register FCMB13_DATA $AC Message Buffer 13 Data Register FCMB13_DATA $AD Message Buffer 13 Data Register FCMB13_DATA $AE Message Buffer 13 Data Register Reserved FCMB14_CONTROL $B0 Message Buffer 14 Control / Status Register FCMB14_ID_HIGH $B1 Message Buffer 14 ID High Register FCMB14_ID_LOW $B2 Message Buffer 14 ID Low Register FCMB14_DATA $B3 Message Buffer 14 Data Register 56F8356 Technical Data, Rev. 13 76 Freescale Semiconductor Preliminary

Factory Programmed Memory Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8156 device Register Acronym Address Offset Register Description FCMB14_DATA $B4 Message Buffer 14 Data Register FCMB14_DATA $B5 Message Buffer 14 Data Register FCMB14_DATA $B6 Message Buffer 14 Data Register Reserved FCMB15_CONTROL $B8 Message Buffer 15 Control / Status Register FCMB15_ID_HIGH $B9 Message Buffer 15 ID High Register FCMB15_ID_LOW $BA Message Buffer 15 ID Low Register FCMB15_DATA $BB Message Buffer 15 Data Register FCMB15_DATA $BC Message Buffer 15 Data Register FCMB15_DATA $BD Message Buffer 15 Data Register FCMB15_DATA $BE Message Buffer 15 Data Register Reserved 4.8 Factory Programmed Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program. The Serial Bootloader application can be used to load a user application into the Program and Data Flash (NOT available in the 56F8156) memories of the device. The 56F83xx SCI/CAN Bootloader User Manual (MC56F83xxBLUM) provides detailed information on this firmware. An application note, Production Flash Programming (AN1973), details how the Serial Bootloader program can be used to perform production Flash programming of the on-board Flash memories as well as other potential methods. Like all the Flash memory blocks, the Boot Flash can be erased and programmed by the user. The Serial Bootloader application is programmed as an aid to the end user, but is not required to be used or maintained in the Boot Flash memory. Part 5 Interrupt Controller (ITCN) 5.1 Introduction The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to service this interrupt. 5.2 Features The ITCN module design includes these distinctive features: 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 77 Preliminary

• Programmable priority levels for each IRQ • Two programmable Fast Interrupts • Notification to SIM module to restart clocks out of Wait and Stop modes • Drives initial address on the address bus after reset For further information, see Table 4-5, Interrupt Vector Table Contents. 5.3 Functional Description The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82 interrupt sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. Within a given priority level, zero is the highest priority, while number 81 is the lowest. 5.3.1 Normal Interrupt Handling Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the vector number to determine the vector address. In this way, an offset is generated into the vector table for each interrupt. 5.3.2 Interrupt Nesting Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition SR[9]1 SR[8]1 Permitted Exceptions Masked Exceptions 0 0 Priorities 0, 1, 2, 3 None 0 1 Priorities 1, 2, 3 Priority 0 1 0 Priorities 2, 3 Priorities 0, 1 1 1 Priority 3 Priorities 0, 1, 2 1. Core status register bits indicating current interrupt mask within the core. Table 5-2 Interrupt Priority Encoding Current Interrupt Required Nested IPIC_LEVEL[1:0]1 Priority Level Exception Priority 00 No Interrupt or SWILP Priorities 0, 1, 2, 3 01 Priority 0 Priorities 1, 2, 3 10 Priority 1 Priorities 2, 3 11 Priorities 2 or 3 Priority 3 56F8356 Technical Data, Rev. 13 78 Freescale Semiconductor Preliminary

Functional Description 1. See IPIC field definition in Part 5.6.30.2 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does. A fast interrupt is defined (to the ITCN) by: 1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers 2. Setting the FIMn register to the appropriate vector number 3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts its fast interrupt handling. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 79 Preliminary

5.4 Block Diagram any0 Priority Level 0 Level 82 -> 7 7 Priority INT1 2 -> 4 Encoder Decode INT VAB CONTROL IPIC any3 Level 3 Priority IACK Level 82 -> 7 7 Priority SR[9:8] Encoder PIC_EN INT82 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ITCN is in this mode by default. • Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA and IRQB signals automatically become low-level sensitive in these modes even if the control register bits are set to make them falling-edge sensitive. This is because there is no clock available to detect the falling edge. A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA and IRQB can wake it up. 5.6 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the 56F8356 Technical Data, Rev. 13 80 Freescale Semiconductor Preliminary

Register Descriptions system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers. Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F1A0) Register Base Address + Register Name Section Location Acronym IPR0 $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.2 IPR2 $2 Interrupt Priority Register 2 5.6.3 IPR3 $3 Interrupt Priority Register 3 5.6.4 IPR4 $4 Interrupt Priority Register 4 5.6.5 IPR5 $5 Interrupt Priority Register 5 5.6.6 IPR6 $6 Interrupt Priority Register 6 5.6.7 IPR7 $7 Interrupt Priority Register 7 5.6.8 IPR8 $8 Interrupt Priority Register 8 5.6.9 IPR9 $9 Interrupt Priority Register 9 5.6.10 VBA $A Vector Base Address Register 5.6.11 FIM0 $B Fast Interrupt 0 Match Register 5.6.12 FIVAL0 $C Fast Interrupt 0 Vector Address Low Register 5.6.13 FIVAH0 $D Fast Interrupt 0 Vector Address High Register 5.6.14 FIM1 $E Fast Interrupt 1 Match Register 5.6.15 FIVAL1 $F Fast Interrupt 1 Vector Address Low Register 5.6.16 FIVAH1 $10 Fast Interrupt 1 Vector Address High Register 5.6.17 IRQP0 $11 IRQ Pending Register 0 5.6.18 IRQP1 $12 IRQ Pending Register 1 5.6.19 IRQP2 $13 IRQ Pending Register 2 5.6.20 IRQP3 $14 IRQ Pending Register 3 5.6.21 IRQP4 $15 IRQ Pending Register 4 5.6.22 IRQP5 $16 IRQ Pending Register 5 5.6.23 Reserved $17 ICTL $1D Interrupt Control Register 5.6.30 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 81 Preliminary

Add. Register Offset Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 $0 IPR0 BKPT_U0 IPL STPCNT IPL W R 0 0 0 0 0 0 0 0 0 0 $1 IPR1 RX_REG IPL TX_REG IPL TRBUF IPL W R 0 0 $2 IPR2 FMCBE IPL FMCC IPL FMERR IPL LOCK IPL LVI IPL IRQB IPL IRQA IPL W R GPIOD GPIOE GPIOF 0 0 $3 IPR3 FCMSGBUF IPL FCWKUP IPL FCERR IPL FCBOFF IPL W IPL IPL IPL R SPI1_RCV 0 0 0 0 GPIOA GPIOB GPIOC $4 IPR4 SPI0_RCV IPL SPI1_XMIT IPL W IPL IPL IPL IPL R SCI1_RCV 0 0 $5 IPR5 DEC1_XIRQ IPL DEC1_HIRQ IPL SCI1_RERR IPL SCI1_TIDL IPL SCI1_XMIT IPL SPI0_XMIT IPL W IPL R 0 0 $6 IPR6 TMRC0 IPL TMRD3 IPL TMRD2 IPL TMRD1 IPL TMRD0 IPL DEC0_XIRQ IPL DEC0_HIRQ IPL W R $7 IPR7 TMRA0 IPL TMRB3 IPL TMRB2 IPL TMRB1 IPL TMRB0 IPL TMRC3 IPL TMRC2 IPL TMRC1 IPL W R 0 0 $8 IPR8 SCI0_RCV IPL SCI0_RERR IPL SCI0_TIDL IPL SCI0_XMIT IPL TMRA3 IPL TMRA2 IPL TMRA1 IPL W R PWMA_RL $9 IPR9 PWMA F IPL PWMB F IPL PWMB_RL IPL ADCA_ZC IPL ABCB_ZC IPL ADCA_CC IPL ADCB_CC IPL W IPL R 0 0 0 VECTOR BASE ADDRESS $A VBA W R 0 0 0 0 0 0 0 0 0 $B VBA0 FAST INTERRUPT 0 W R FAST INTERRUPT 0 $C FIVAL0 W VECTOR ADDRESS LOW R 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 $D FIVAH0 W VECTOR ADDRESS HIGH R 0 0 0 0 0 0 0 0 0 $E FIM1 FAST INTERRUPT 1 W R FAST INTERRUPT 1 $F FIVAL1 W VECTOR ADDRESS LOW R 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 $10 FIVAH1 W VECTOR ADDRESS HIGH R PENDING [16:2] 1 $11 IRQP0 W R PENDING [32:17] $12 IRQP1 W R PENDING [48:33] $13 IRQP2 W R PENDING [64:49] $14 IRQP3 W R PENDING [80:65] $15 IRQP4 W PEND- R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ING $16 IRQP5 [81] W Reserved $1D ICTL R INT IPIC VAB INT_DIS 1 SITRAQTBE SITRAQTAE IRQB IRQA EDG EDG W = Reserved Figure 5-2 ITCN Register Map Summary 56F8356 Technical Data, Rev. 13 82 Freescale Semiconductor Preliminary

Register Descriptions 5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 0 BKPT_U0 IPL STPCNT IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.1.2 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)— Bits13–12 This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 1 • 10 = IRQ is priority level 2 • 11 = IRQ is priority level 3 5.6.1.3 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 1 • 10 = IRQ is priority level 2 • 11 = IRQ is priority level 3 5.6.1.4 Reserved—Bits 9–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 RX_REG IPL TX_REG IPL TRBUF IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-4 Interrupt Priority Register 1 (IPR1) 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 83 Preliminary

5.6.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 1 • 10 = IRQ is priority level 2 • 11 = IRQ is priority level 3 5.6.2.3 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 1 • 10 = IRQ is priority level 2 • 11 = IRQ is priority level 3 5.6.2.4 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 1 • 10 = IRQ is priority level 2 • 11 = IRQ is priority level 3 56F8356 Technical Data, Rev. 13 84 Freescale Semiconductor Preliminary

Register Descriptions 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 FMCBE IPL FMCC IPL FMERR IPL LOCK IPL LVI IPL IRQB IPL IRQA IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-5 Interrupt Priority Register 2 (IPR2) 5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.3.2 Flash Memory Command Complete Priority Level (FMCC IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.3.3 Flash Memory Error Interrupt Priority Level (FMERR IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 85 Preliminary

• 11 = IRQ is priority level 2 5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.3.6 Reserved—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.3.7 External IRQ B Interrupt Priority Level (IRQB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.3.8 External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 56F8356 Technical Data, Rev. 13 86 Freescale Semiconductor Preliminary

Register Descriptions • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.4 Interrupt Priority Register 3 (IPR3) Base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 GPIOD GPIOE GPIOF FCMSGBUF IPL FCWKUP IPL FCERR IPL FCBOFF IPL Write IPL IPL IPL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-6 Interrupt Priority Register 3 (IPR3) 5.6.4.1 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.4.2 GPIOE Interrupt Priority Level (GPIOE IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.4.3 GPIOF Interrupt Priority Level (GPIOF IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 87 Preliminary

5.6.4.4 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.4.5 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.4.6 FlexCAN Error Interrupt Priority Level (FCERR IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.4.7 FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.4.8 Reserved—Bits 1–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F8356 Technical Data, Rev. 13 88 Freescale Semiconductor Preliminary

Register Descriptions 5.6.5 Interrupt Priority Register 4 (IPR4) Base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 SPI0_RCV SPI1_XMIT SPI1_RCV GPIOA GPIOB GPIOC Write IPL IPL IPL IPL IPL IPL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.5.2 SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.5.3 SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 89 Preliminary

• 11 = IRQ is priority level 2 5.6.5.4 Reserved—Bits 9–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.5.5 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.5.6 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.5.7 GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6 Interrupt Priority Register 5 (IPR5) Base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 DEC1_XIRQ DEC1_HIRQ SCI1_RCV SCI1_RERR SCI1_TIDL SCI1_XMIT SPI0_XMIT Write IPL IPL IPL IPL IPL IPL IPL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-8 Interrupt Priority Register 5 (IPR5) 5.6.6.1 Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. 56F8356 Technical Data, Rev. 13 90 Freescale Semiconductor Preliminary

Register Descriptions They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6.2 Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC1_HIRQ IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6.3 SCI 1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6.4 SCI 1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6.5 Reserved—Bits 7–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 91 Preliminary

5.6.6.6 SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6.7 SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6.8 SPI 0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.7 Interrupt Priority Register 6 (IPR6) Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 DEC0_XIRQ DEC0_HIRQ TMRC0 IPL TMRD3 IPL TMRD2 IPL TMRD1 IPL TMRD0 IPL Write IPL IPL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-9 Interrupt Priority Register 6 (IPR6) 56F8356 Technical Data, Rev. 13 92 Freescale Semiconductor Preliminary

Register Descriptions 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.7.2 Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.7.3 Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.7.4 Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 93 Preliminary

5.6.7.5 Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.7.6 Reserved—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.7.7 Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.7.8 Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 56F8356 Technical Data, Rev. 13 94 Freescale Semiconductor Preliminary

Register Descriptions 5.6.8 Interrupt Priority Register 7 (IPR7) Base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TMRA0 IPL TMRB3 IPL TMRB2 IPL TMRB1 IPL TMRB0 IPL TMRC3 IPL TMRC2 IPL TMRC1 IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-10 Interrupt Priority Register (IPR7) 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.8.2 Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.8.3 Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.8.4 Timer B, Channel 1 Interrupt Priority Level (TMRB1 IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 95 Preliminary

• 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.8.5 Timer B, Channel 0 Interrupt Priority Level (TMRB0 IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.8.6 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.8.7 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.8.8 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 56F8356 Technical Data, Rev. 13 96 Freescale Semiconductor Preliminary

Register Descriptions 5.6.9 Interrupt Priority Register 8 (IPR8) Base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 SCI0_RCV SCI0_RERR SCI0_TIDL SCI0_XMIT TMRA3 IPL TMRA2 IPL TMRA1 IPL Write IPL IPL IPL IPL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-11 Interrupt Priority Register 8 (IPR8) 5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.9.3 Reserved—Bits 11–10 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 97 Preliminary

5.6.9.5 SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.9.6 Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.9.7 Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 56F8356 Technical Data, Rev. 13 98 Freescale Semiconductor Preliminary

Register Descriptions 5.6.10 Interrupt Priority Register 9 (IPR9) Base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PWMA_RL ADCA_CC ADCB_CC PWMA_F IPL PWMB_F IPL PWM_RL IPL ADCA_ZC IPL ABCB_ZC IPL Write IPL IPL IPL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-12 Interrupt Priority Register 9 (IPR9) 5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA_F IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.10.2 PWM B Fault Interrupt Priority Level (PWMB_F IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.10.4 Reload PWM B Interrupt Priority Level (PWMB_RL IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 99 Preliminary

• 11 = IRQ is priority level 2 5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level ADCA_ZC IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.10.6 ADC B Zero Crossing or Limit Error Interrupt Priority Level (ADCB_ZC IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.10.7 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.10.8 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 56F8356 Technical Data, Rev. 13 100 Freescale Semiconductor Preliminary

Register Descriptions 5.6.11 Vector Base Address Register (VBA) Base + $A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 VECTOR BASE ADDRESS Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-13 Vector Base Address Register (VBA) 5.6.11.1 Reserved—Bits 15–13 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)— Bits 12–0 The contents of this register determine the location of the Vector Address Table. The value in this register is used as the upper 13 bits of the interrupt Vector Address Bus (VAB[20:0]). The lower eight bits are determined based upon the highest-priority interrupt. They are then appended onto VBA before presenting the full VAB to the 56800E core; see Part 5.3.1 for details. 5.6.12 Fast Interrupt 0 Match Register (FIM0) Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-14 Fast Interrupt 0 Match Register (FIM0) 5.6.12.1 Reserved—Bits 15–7 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0 This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table4-5. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 101 Preliminary

5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0) Base + $C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read FAST INTERRUPT 0 Write VECTOR ADDRESS LOW RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0) Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 Write VECTOR ADDRESS HIGH RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0) 5.6.14.1 Reserved—Bits 15–5 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 5.6.15 Fast Interrupt 1 Match Register (FIM1) Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-17 Fast Interrupt 1 Match Register (FIM1) 5.6.15.1 Reserved—Bits 15–7 This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing. 5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0 This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service 56F8356 Technical Data, Rev. 13 102 Freescale Semiconductor Preliminary

Register Descriptions routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table4-5. 5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1) Base + $F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read FAST INTERRUPT 1 Write VECTOR ADDRESS LOW RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1) 5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0 The lower 16 bits of vector address are used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1) Base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 Write VECTOR ADDRESS HIGH RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1) 5.6.17.1 Reserved—Bits 15–5 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0 The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.18 IRQ Pending 0 Register (IRQP0) Base + $11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING [16:2] 1 Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-20 IRQ Pending 0 Register (IRQP0) 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 103 Preliminary

5.6.18.1 IRQ Pending (PENDING)—Bits 16–2 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number 5.6.18.2 Reserved—Bit 0 This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.19 IRQ Pending 1 Register (IRQP1) $Base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING [32:17] Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-21 IRQ Pending 1 Register (IRQP1) 5.6.19.1 IRQ Pending (PENDING)—Bits 32–17 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number 5.6.20 IRQ Pending 2 Register (IRQP2) Base + $13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING [48:33] Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-22 IRQ Pending 2 Register (IRQP2) 5.6.20.1 IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number 56F8356 Technical Data, Rev. 13 104 Freescale Semiconductor Preliminary

Register Descriptions 5.6.21 IRQ Pending 3 Register (IRQP3) Base + $14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING [64:49] Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-23 IRQ Pending 3 Register (IRQP3) 5.6.21.1 IRQ Pending (PENDING)—Bits 64–49 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number 5.6.22 IRQ Pending 4 Register (IRQP4) Base + $15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING [80:65] Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-24 IRQ Pending 4 Register (IRQP4) 5.6.22.1 IRQ Pending (PENDING)—Bits 80–65 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number 5.6.23 IRQ Pending 5 Register (IRQP5) Base + $16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEND- Read 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ING [81] Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-25 IRQ Pending Register 5 (IRQP5) 5.6.23.1 Reserved—Bits 96–82 This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 105 Preliminary

5.6.23.2 IRQ Pending (PENDING)—Bit 81 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number 5.6.24 Reserved—Base + 17 5.6.25 Reserved—Base + 18 5.6.26 Reserved—Base + 19 5.6.27 Reserved—Base + 1A 5.6.28 Reserved—Base + 1B 5.6.29 Reserved—Base + 1C 5.6.30 ITCN Control Register (ICTL) Base + $1D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read INT IPIC VAB 1 IRQB STATE IRQA STATE IRQB IRQA INT_DIS Write EDG EDG RESET 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 Figure 5-26 ITCN Control Register (ICTL) 5.6.30.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. • 0 = No interrupt is being sent to the 56800E core • 1 = An interrupt is being sent to the 56800E core 5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13 These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. • 00 = Required nested exception priority levels are 0, 1, 2, or 3 • 01 = Required nested exception priority levels are 1, 2, or 3 • 10 = Required nested exception priority levels are 2 or 3 56F8356 Technical Data, Rev. 13 106 Freescale Semiconductor Preliminary

Register Descriptions • 11 = Required nested exception priority level is 3 5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6 This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5 This bit allows all interrupts to be disabled. • 0 = Normal operation (default) • 1 = All interrupts disabled 5.6.30.5 Reserved—Bit 4 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.30.6 IRQB State Pin (IRQB STATE)—Bit 3 This read-only bit reflects the state of the external IRQB pin. 5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2 This read-only bit reflects the state of the external IRQA pin. 5.6.30.8 IRQB Edge Pin (IRQB Edg)—Bit 1 This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and Wait modes, it is automatically level-sensitive. • 0 = IRQB interrupt is a low-level sensitive (default) • 1 = IRQB interrupt is falling-edge sensitive 5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0 This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait modes, it is automatically level-sensitive. • 0 = IRQA interrupt is a low-level sensitive (default) • 1 = IRQA interrupt is falling-edge sensitive 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 107 Preliminary

5.7 Resets 5.7.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released. 5.7.2 ITCN After Reset After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled, except the core IRQs with fixed priorities: • Illegal Instruction • SW Interrupt 3 • HW Stack Overflow • Misaligned Long Word Access • SW Interrupt 2 • SW Interrupt 1 • SW Interrupt 0 • SW Interrupt LP These interrupts are enabled at their fixed priority levels. 56F8356 Technical Data, Rev. 13 108 Freescale Semiconductor Preliminary

Overview Part 6 System Integration Module (SIM) 6.1 Overview The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The system integration module is responsible for the following functions: • Reset sequencing • Clock generation & distribution • Stop/Wait control • Pull-up enables for selected peripherals • System status registers • Registers for software access to the JTAG ID of the chip • Enforcing Flash security These are discussed in more detail in the sections that follow. 6.2 Features The SIM has the following features: • Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory • Power-saving clock gating for peripheral • Three power modes (Run, Wait, Stop) to control power utilization — Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation — Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be explicitly done — Wait mode shuts down the 56800E core and unnecessary system clock operation — Run mode supports full part operation • Controls to enable/disable the 56800E core WAIT and STOP instructions • Calculates base delay for reset extension based upon POR or RESET operations. Reset delay will be either 3 x 32 clocks (phased release of reset) for reset, except for POR, which is 221 clock cycles • Controls reset sequencing after reset • Software-initiated reset • Four 16-bit registers reset only by a Power-On Reset usable for general purpose software control • System Control Register • Registers for software access to the JTAG ID of the chip 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 109 Preliminary

6.3 Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — POR and RESET operation The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the RESET pin is asserted. — COP reset and software reset operation The 56800E core and all peripherals are reset. The MA bit within the OMR is not changed. This allows the software to determine the boot mode (internal or external boot) to be used on the next reset. • Run Mode This is the primary mode of operation for this device. In this mode, the 56800E controls chip operation. • Debug Mode The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and PWMs, continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor from being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details. • Wait Mode In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped. Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other peripherals continue to run. • Stop Mode When in Stop mode, the 56800E core, memory, and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode. 6.4 Operating Mode Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NL CM XP SD R SA EX 0 MB MA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X Figure 6-1 OMR The reset state for MB and MA will depend on the Flash secured state. See Part 4.2 and Part 7 for detailed information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. For all other bits, see the DSP56800E Reference Manual. Note: The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR. 56F8356 Technical Data, Rev. 13 110 Freescale Semiconductor Preliminary

Register Descriptions 6.5 Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F350) Address Offset Address Acronym Register Name Section Location Base + $0 SIM_CONTROL Control Register 6.5.1 Base + $1 SIM_RSTSTS Reset Status Register 6.5.2 Base + $2 SIM_SCR0 Software Control Register 0 6.5.3 Base + $3 SIM_SCR1 Software Control Register 1 6.5.3 Base + $4 SIM_SCR2 Software Control Register 2 6.5.3 Base + $5 SIM_SCR3 Software Control Register 3 6.5.3 Base + $6 SIM_MSH_ID Most Significant Half of JTAG ID 6.5.4 Base + $7 SIM_LSH_ID Least Significant Half of JTAG ID 6.5.5 Base + $8 SIM_PUDR Pull-up Disable Register 6.5.6 Reserved Base + $A SIM_CLKOSR CLKO Select Register 6.5.7 Base + $B SIM_GPS GPIO Peripheral Select Register 6.5.7 Base + $C SIM_PCE Peripheral Clock Enable Register 6.5.8 Base + $D SIM_ISALH I/O Short Address Location High Register 6.5.9 Base + $E SIM_ISALL I/O Short Address Location Low Register 6.5.10 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 111 Preliminary

Add. Register Offset Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIM_ R 0 0 0 0 0 0 0 0 0 EMI_ ONCE SW STOP_ WAIT_ $0 CONTROL W MODE EBL0 RST DISABLE DISABLE SIM_ R 0 0 0 0 0 0 0 0 0 0 0 0 $1 SWR COPR EXTR POR RSTSTS W R $2 SIM_SCR0 FIELD W R $3 SIM_SCR1 FIELD W R $4 SIM_SCR2 FIELD W R $5 SIM_SCR3 FIELD W SIM_MSH_ R 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 $6 ID W R 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 $7 SIM_LSH_ID W R 0 PWMA EMI_ PWMA 0 0 0 0 0 $8 SIM_PUDR CAN RESET IRQ XBOOT PWMB CTRL JTAG W 0 1 MODE 0 Reserved SIM_ R 0 0 0 0 0 0 $A A23 A22 A21 A20 CLKDIS CLKOSEL CLKOSR W R 0 0 0 0 0 0 0 0 0 0 0 0 $B SIM_GPS C3 C2 C1 C0 W R PWM PWM $C SIM_PCE EMI ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI1 SCI0 SPI1 SPI0 W B A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 $D SIM_ISALH ISAL[23:22] W R $E SIM_ISALL ISAL[21:6] W = Reserved Figure 6-2 SIM Register Map Summary 6.5.1 SIM Control Register (SIM_CONTROL) Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 EMI_ ONCE SW STOP_ WAIT_ Write MODE EBL RST DISABLE DISABLE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-3 SIM Control Register (SIM_CONTROL) 6.5.1.1 Reserved—Bits 15–7 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F8356 Technical Data, Rev. 13 112 Freescale Semiconductor Preliminary

Register Descriptions 6.5.1.2 EMI_MODE (EMI_MODE)—Bit 6 This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset. In addition, this pin can be used as a general purpose input pin after reset. • 0 = External address bits [19:16] are initially programmed as GPIO • 1 = When booted with EXTBOOT = 1, A[19:16] are initially programmed as address. If EXTBOOT is 0, they are initialized as GPIO. 6.5.1.3 OnCE Enable (OnCE EBL)—Bit 5 • 0 = OnCE clock to 56800E core enabled when core TAP is enabled • 1 = OnCE clock to 56800E core is always enabled 6.5.1.4 Software Reset (SW RST)—Bit 4 This bit is always read as 0. Writing a 1 to this bit will cause the part to reset. 6.5.1.5 Stop Disable (STOP_DISABLE)—Bits 3–2 • 00 - Stop mode will be entered when the 56800E core executes a STOP instruction • 01 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be reprogrammed in the future • 10 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be changed by resetting the device • 11 - Same operation as 10 6.5.1.6 Wait Disable (WAIT_DISABLE)—Bits 1–0 • 00 - Wait mode will be entered when the 56800E core executes a WAIT instruction • 01 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be reprogrammed in the future • 10 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then only be changed by resetting the device • 11 - Same operation as 10 6.5.2 SIM Reset Status Register (SIM_RSTSTS) Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this register. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 113 Preliminary

Base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 0 SWR COPR EXTR POR Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-4 SIM Reset Status Register (SIM_RSTSTS) 6.5.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.2.2 Software Reset (SWR)—Bit 5 When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.3 COP Reset (COPR)—Bit 4 When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.4 External Reset (EXTR)—Bit 3 If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit position will clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external RESET pin being asserted low. 6.5.2.5 Power-On Reset (POR)—Bit 2 When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be cleared only by software or by another type of reset. Writing a 0 to this bit will set the bit, while writing a 1 to the bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a Power-On Reset. 6.5.2.6 Reserved—Bits 1–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.3 SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3) Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality. 56F8356 Technical Data, Rev. 13 114 Freescale Semiconductor Preliminary

Register Descriptions Base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read FIELD Write POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-5 SIM Software Control Register 0 (SIM_SCR0) 6.5.3.1 Software Control Data 1 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources (RESET pin, software reset, and COP reset). 6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F4. Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 Write RESET 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID) 6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID) This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $601D. Base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 Write RESET 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID) 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 115 Preliminary

6.5.6 SIM Pull-up Disable Register (SIM_PUDR) Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See Table 2-2 to identify which pins can deactivate the internal pull-up resistor. Base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 EMI_ 0 0 0 0 0 PWMA1 CAN RESET IRQ XBOOT PWMB PWMA0 CTRL JTAG Write MODE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR) 6.5.6.1 Reserved—Bit 15 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.2 PWMA1—Bit 14 This bit controls the pull-up resistors on the FAULTA3 pin. 6.5.6.3 CAN—Bit 13 This bit controls the pull-up resistors on the CAN_RX pin. 6.5.6.4 EMI_MODE—Bit 12 This bit controls the pull-up resistors on the EMI_MODE pin. 6.5.6.5 RESET—Bit 11 This bit controls the pull-up resistors on the RESET pin. 6.5.6.6 IRQ—Bit 10 This bit controls the pull-up resistors on the IRQA and IRQB pins. 6.5.6.7 XBOOT—Bit 9 This bit controls the pull-up resistors on the EXTBOOT pin. 6.5.6.8 PWMB—Bit 8 This bit controls the pull-up resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3 pins. 6.5.6.9 PWMA0—Bit 7 This bit controls the pull-up resistors on the FAULTA0, FAULTA1, and FAULTA2 pins. 6.5.6.10 Reserved—Bit 6 56F8356 Technical Data, Rev. 13 116 Freescale Semiconductor Preliminary

Register Descriptions This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.11 CTRL—Bit 5 This bit controls the pull-up resistors on the WR and RD pins. 6.5.6.12 Reserved—Bit 4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.13 JTAG—Bit 3 This bit controls the pull-up resistors on the TRST, TMS and TDI pins. 6.5.6.14 Reserved—Bits 2 - 0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.7 CLKO Select Register (SIM_CLKOSR) The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are for test purposes only, and are subject to significant unspecified latencies at high frequencies. The upper four bits of the GPIOB register can function as GPIO, A[23:20], or as additional clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed to operate as peripheral outputs, then the choice between A[23:20] and additional clock outputs is done here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as A[23:20]. This can be changed by altering A[23:20], as shown in Figure 6-9. Base + $A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 CLK A23 A22 A21 A20 CLKOSEL Write DIS RESET 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Figure 6-9 CLKO Select Register (SIM_CLKOSR) 6.5.7.1 Reserved—Bits 15–10 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.7.2 Alternate GPIOB Peripheral Function for A23 (A23)—Bit 9 • 0 = Peripheral output function of GPIOB7 is defined to be A23 • 1 = Peripheral output function of GPIOB7 is defined to be the oscillator_clock (MSTR_OSC, see Figure3-4) 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 117 Preliminary

6.5.7.3 Alternate GPIOB Peripheral Function for A22 (A22)—Bit 8 • 0 = Peripheral output function of GPIOB6 is defined to be A22 • 1 = Peripheral output function of GPIOB6 is defined to be SYS_CLK2 6.5.7.4 Alternate GPIOB Peripheral Function for A21 (A21)—Bit 7 • 0 = Peripheral output function of GPIOB5 is defined to be A21 • 1 = Peripheral output function of GPIOB5 is defined to be SYS_CLK 6.5.7.5 Alternate GPIOB Peripheral Function for A20 (A20)—Bit 6 • 0 = Peripheral output function of GPIOB4 is defined to be A20 • 1 = Peripheral output function of GPIOB4 is defined to be the prescaler_clock (FREF, see Figure3-4) 6.5.7.6 Clockout Disable (CLKDIS)—Bit 5 • 0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL • 1 = CLKOUT is tri-stated 6.5.7.7 CLockout Select (CLKOSEL)—Bits 4–0 Selects clock to be muxed out on the CLKO pin. • 00000 = SYS_CLK (from OCCS - DEFAULT) • 00001 = Reserved for factory test—56800E clock • 00010 = Reserved for factory test—XRAM clock • 00011 = Reserved for factory test—PFLASH odd clock • 00100 = Reserved for factory test—PFLASH even clock • 00101 = Reserved for factory test—BFLASH clock • 00110 = Reserved for factory test—DFLASH clock • 00111 = Oscillator output • 01000 = F (from OCCS) out • 01001 = Reserved for factory test—IPB clock • 01010 = Reserved for factory test—Feedback (from OCCS, this is path to PLL) • 01011 = Reserved for factory test—Prescaler clock (from OCCS) • 01100 = Reserved for factory test—Postscaler clock (from OCCS) • 01101 = Reserved for factory test—SYS_CLK2 (from OCCS) • 01110 = Reserved for factory test—SYS_CLK_DIV2 • 01111 = Reserved for factory test—SYS_CLK_D • 10000 = ADCA clock • 10001 = ADCB clock 6.5.8 GPIO Peripheral Select Register (SIM_GPS) The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate peripherals for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B (NOT available in the 56F8156 56F8356 Technical Data, Rev. 13 118 Freescale Semiconductor Preliminary

Register Descriptions device); these peripherals work together. The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad Timer B, or as SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown in Figure 6-10 and Table 6-2. When GPIOC[3:0] are programmed to operate as peripheral I/O, then the choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and in conjunction with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function of GPIOC[3:0] to be programmed as decoder functions. This can be changed by altering the appropriate controls in the indicated registers. GPIOC_PER Register GPIO Controlled 0 I/O Pad Control 1 SIM_ GPS Register Quad Timer Controlled 0 SPI Controlled 1 Figure 6-10 Overall Control of Pads Using SIM_GPS Control Table 6-2 Control of Pads Using SIM_GPS Control 1 Control Registers R R rer Pin Function GPIOC_PE GPIOC_DT SIM_GPS Quad TimeCR RegistOEN bits Comments S GPIO Input 0 0 — — GPIO Output 0 1 — — Quad Timer Input / 1 — 0 0 See the “Switch Matrix for Inputs to the Timer” Quad Decoder Input 2 table in the 56F8300 Peripheral User Manual for the definition of the timer inputs based on Quad Timer Output / 1 — 0 1 the Quad Decoder Mode configuration. Quad Decoder Input 3 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 119 Preliminary

Table 6-2 Control of Pads Using SIM_GPS Control 1 Control Registers R R rer Pin Function GPIOC_PE GPIOC_DT SIM_GPS Quad TimeCR RegistOEN bits Comments S SPI input 1 — 1 — See SPI controls for determining the direction of each of the SPI pins. SPI output 1 — 1 — 1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is used for each pin. 2. Reset configuration 3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins. Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 0 C3 C2 C1 C0 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-11 GPIO Peripheral Select Register (SIM_GPS) 6.5.8.1 Reserved—Bits 15–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.8.2 GPIOC3 (C3)—Bit 3 This bit selects the alternate function for GPIOC3. • 0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the 56F8300 Peripheral User Manual) • 1 = SS1 6.5.8.3 GPIOC2 (C2)—Bit 2 This bit selects the alternate function for GPIOC2. • 0 = INDEX1/TB2 (default) • 1 = MISO1 6.5.8.4 GPIOC1 (C1)—Bit 1 This bit selects the alternate function for GPIOC1. • 0 = PHASEB1/TB1 (default) • 1 = MOSI1 56F8356 Technical Data, Rev. 13 120 Freescale Semiconductor Preliminary

Register Descriptions 6.5.8.5 GPIOC0 (C0)—Bit 0 This bit selects the alternate function for GPIOC0. • 0 = PHASEA1/TB0 (default) • 1 = SCLK1 6.5.9 Peripheral Clock Enable Register (SIM_PCE) The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip. Base + $C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read EMI ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI 1 SCI 0 SPI 1 SPI 0 PWMB PWMA Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6-12 Peripheral Clock Enable Register (SIM_PCE) 6.5.9.1 External Memory Interface Enable (EMI)—Bit 15 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.2 Analog-to-Digital Converter B Enable (ADCB)—Bit 14 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.3 Analog-to-Digital Converter A Enable (ADCA)—Bit 13 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.4 FlexCAN Enable (CAN)—Bit 12 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.5 Decoder 1 Enable (DEC1)—Bit 11 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 121 Preliminary

• 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.6 Decoder 0 Enable (DEC0)—Bit 10 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.7 Quad Timer D Enable (TMRD)—Bit 9 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 Quad Timer C Enable (TMRC)—Bit 8 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.9 Quad Timer B Enable (TMRB)—Bit 7 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.10 Quad Timer A Enable (TMRA)—Bit 6 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.11 Serial Communications Interface 1 Enable (SCI1)—Bit 5 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.12 Serial Communications Interface 0 Enable (SCI0)—Bit 4 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled 56F8356 Technical Data, Rev. 13 122 Freescale Semiconductor Preliminary

Register Descriptions • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.15 Pulse Width Modulator B Enable (PWMB)—1 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.16 Pulse Width Modulator A Enable (PWMA)—0 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL) The I/O Short Address Location registers are used to specify the memory referenced via the I/O short address mode. The I/O short address mode allows the instruction to specify the lower six bits of address; the upper address bits are not directly controllable. This register set allows limited control of the full address, as shown in Figure6-13. Note: If this register is set to something other than the top of memory (EOnCE register space) and the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions will be affected. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 123 Preliminary

“Hard Coded” Address Portion Instruction Portion 6 Bits from I/O Short Address Mode Instruction 16 Bits from SIM_ISALL Register 2 bits from SIM_ISALH Register Full 24-Bit for Short I/O Address Figure 6-13 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register to its previous contents prior to returning from interrupt. Note: The default value of this register set points to the EOnCE registers. Note: The pipeline delay between setting this register set and using short I/O addressing with the new value is three cycles. Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ISAL[23:22] Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6-14 I/O Short Address Location High Register (SIM_ISALH) 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of the “hard coded” I/O short address. Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read ISAL[21:6] Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL) 56F8356 Technical Data, Rev. 13 124 Freescale Semiconductor Preliminary

Clock Generation Overview 6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.6 Clock Generation Overview The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL) to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible means to manage power consumption. Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may be shut down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused. Clock enables provide the means to disable individual clocks. Some peripherals provide further controls to disable unused subfunctions. Refer to the Part 3 On-Chip Clock Synthesis (OCCS), and the 56F8300 Peripheral User Manual for further details. 6.7 Power-Down Modes Overview The 56F8356/56F8156 devices operate in one of three power-down modes, as shown in Table 6-3. Table 6-3 Clock Operation in Power-Down Modes Mode Core Clocks Peripheral Clocks Description Run Active Active Device is fully functional Wait Core and memory Active Peripherals are active and can product interrupts if they clocks disabled have not been masked off. Interrupts will cause the core to come out of its suspended state and resume normal operation. Typically used for power-conscious applications. Stop System clocks continue to be generated in The only possible recoveries from Stop mode are: the SIM, but most are gated prior to 1. CAN traffic (1st message will be lost) reaching memory, core and peripherals. 2. Non-clocked interrupts 3. COP reset 4. External reset 5. Power-on reset All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK= 60MHz. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 125 Preliminary

6.8 Stop and Wait Mode Disable Function Permanent Disable D Q D-FLOP C 56800E Reprogrammable STOP_DIS Disable D Q D-FLOP Clock C Select R Note: Wait disable circuit Reset is similar Figure 6-16 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E system clock must be set equal to the prescaler output. Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those instructions, write to the SIM control register (SIM_CONTROL), described in Part 6.5.1. This procedure can be on either a permanent or temporary basis. Permanently assigned applications last only until their next reset. 6.9 Resets The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin and the Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within the SIM itself by writing to the SIM_CONTROL register and the COP reset. Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is sequenced to permit proper operation of the device. A POR reset is first extended for 221 clock cycles to permit stabilization of the clock source, followed by a 32 clock window in which SIM clocking is initiated. It is 56F8356 Technical Data, Rev. 13 126 Freescale Semiconductor Preliminary

Operation with Security Enabled then followed by a 32 clock window in which peripherals are released to implement Flash security, and, finally, followed by a 32 clock window in which the core is initialized. After completion of the described reset sequence, application code will begin execution. Resets may be asserted asynchronously, but are always released internally on a rising edge of the system clock. Part 7 Security Features The 56F8356/56F8156 offer security features intended to prevent unauthorized users from reading the contents of the Flash memory (FM) array. The Flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the Flash array. However, part of the security must lie with the user’s code. An extreme example would be user’s code that dumps the contents of the internal program, as this code would defeat the purpose of security. At the same time, the user may also wish to put a “backdoor” in his program. As an example, the user downloads a security key through the SCI, allowing access to a programming routine that updates parameters stored in another section of the Flash. 7.1 Operation with Security Enabled Once the user has programmed the Flash with his application code, the device can be secured by programming the security bytes located in the FM configuration field, which occupies a portion of the FM array. These non-volatile bytes will keep the part secured through reset and through power-down of the device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory section in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state of security. When Flash security mode is enabled in accordance with the method described in the Flash Memory module specification, the device will disable external P-space accesses restricting code execution to internal memory, disable EXTBOOT = 1 mode, and disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected. 7.2 Flash Access Blocking Mechanisms The 56F8356/56F8156 have several operating functional and test modes. Effective Flash security must address operating mode selection and anticipate modes in which the on-chip Flash can be compromised and read without explicit user permission. Methods to block these are outlined in the next subsections. 7.2.1 Forced Operating Mode Selection At boot time, the SIM determines in which functional modes the device will operate. These are: • Internal Boot Mode • External Boot Mode 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 127 Preliminary

• Secure Mode When Flash security is enabled as described in the Flash Memory module specification, the device will boot in internal boot mode, disable all access to external P-space, and start executing code from the Boot Flash at address 0x02_0000. This security affords protection only to applications in which the device operates in internal Flash security mode. Therefore, the security feature cannot be used unless all executing code resides on-chip. When security is enabled, any attempt to override the default internal operating mode by asserting the EXTBOOT pin in conjunction with reset will be ignored. 7.2.2 Disabling EOnCE Access On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability and access to the ID register. Proper implementation of Flash security requires that no access to the EOnCE port is provided when security is enabled. The 56800E core has an input which disables reading of internal memory via the JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the FM security bytes. 7.2.3 Flash Lockout Recovery If a user inadvertently enables Flash security on the device, a built-in lockout recovery mechanism can be used to reenable access to the device. This mechanism completely reases all on-chip Flash, thus disabling Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory configuration (.cfg) files. Add, or uncomment the following configuration command: unlock_flash_on_connect 1 For more information, please see CodeWarrior MC56F83xx/DSP5685x Family Targeting Manual. The LOCKOUT_RECOVERY instruction will have an associated 7-bit Data Register (DR) that is used to control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control the period of the clock used for timed events in the FM erase algorithm. This register must be set with appropriate values before the lockout sequence can begin. Refer to the JTAG section of the 56F8300 Peripheral User Manual for more details on setting this register value. The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides down the system clock for timed events, as illustrated in Figure7-1. FM_CLKDIV[6] will map to the PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values. 56F8356 Technical Data, Rev. 13 128 Freescale Semiconductor Preliminary

Flash Access Blocking Mechanisms Flash Memory SYS_CLK input DIVIDER 2 clock 7 FMCLKD 7 7 FM_CLKDIV JTAG FM_ERASE Figure 7-1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow. EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[6] = 0. Using the following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively. (SYS_CLK) (2) 150[kHz] < < 200[kHz] (DIV + 1) EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8= FM_CLKDIV[6] = 1. Using the following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of 181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A, respectively. (SYS_CLK) (2)(8) 150[kHz] < < 200[kHz] (DIV + 1) Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence has completed. For details, see the JTAG Section in the 56F8300 Peripheral User Manual. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 129 Preliminary

Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured operation. 7.2.4 Product Analysis The recommended method of unsecuring a programmed device for product analysis of field failures is via the backdoor key access. The customer would need to supply Technical Support with the backdoor key and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows backdoor key access must be set. An alternative method for performing analysis on a secured hybrid controller would be to mass-erase and reprogram the Flash with the original code, but modify the security bytes. To insure that a customer does not inadvertently lock himself out of the device during programming, it is recommended that he program the backdoor access key first, his application code second, and the security bytes within the FM configuration field last. Part 8 General Purpose Input/Output (GPIO) 8.1 Introduction This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip-specific information. This information supercedes the generic information in the 56F8300 Peripheral User Manual. 8.2 Memory Maps The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR and GPIOx_PER registers change from port to port. Tables 4-29 through 4-34 define the actual reset values of these registers. 8.3 Configuration There are six GPIO ports defined on the 56F8356/56F8156. The width of each port and the associated peripheral function is shown in Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is shown in Table 8-3. 56F8356 Technical Data, Rev. 13 130 Freescale Semiconductor Preliminary

Configuration Table 8-1 56F8356 GPIO Ports Configuration Available GPIO Port Pins in Peripheral Function Reset Function Port Width 56F8356 A 14 14 14 pins - EMI Address pins EMI Address B 8 1 1 pin - EMI Address pin EMI Address 7 pins - EMI Address pins - Not available in this package N/A C 11 11 4 pins -DEC1 / TMRB / SPI1 DEC1 / TMRB 4 pins -DEC0 / TMRA DEC0 / TMRA 3 pins -PWMA current sense PWMA current sense D 13 9 2 pins - EMI CSn EMI Chip Selects 4 pins - EMI CSn - Not available in this package N/A 2 pins - SCI1 SCI1 2 pins - EMI CSn EMI Chip Selects 3 pins -PWMB current sense PWMB current sense E 14 11 2 pins - SCI0 SCI0 2 pins - EMI Address pins EMI Address 4 pins - SPI0 SPI0 1 pin - TMRC TMRC 1 pin - TMRC - Not available in this package N/A 2 pins - TMRD TMRD 2 pins - TMRD - Not available in this package N/A F 16 16 16 pins - EMI Data EMI Data Table 8-2 56F8156 GPIO Ports Configuration Available GPIO Port Pins in Peripheral Function Reset Function Port Width 56F8156 A 14 14 14 pins - EMI Address pins EMI Address B 8 1 1 pin - EMI Address pin EMI Address 7 pins - EMI Address pins - Not available in this package N/A C 11 11 4 pins - SPI1 SPI1 4 pins - DEC0 / TMRA DEC0 / TMRA 3 pins - Dedicated GPIO GPIO D 13 9 2 pins - EMI CSn EMI Chip Selects 4 pins - EMI CSn - Not available in this package N/A 2 pins - SCI1 SCI1 2 pins - EMI CSn EMI Chip Selects 3 pins - PWMB current sense PWMB current sense 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 131 Preliminary

Table 8-2 56F8156 GPIO Ports Configuration Available GPIO Port Pins in Peripheral Function Reset Function Port Width 56F8156 E 14 11 2 pins - SCI0 SCI0 2 pins - EMI Address pins EMI Address 4 pins - SPI0 SPI0 1 pin - TMRC TMRC 1 pin - TMRC - Not available in this package N/A 2 pins - Dedicated GPIO GPIO 2 pins - TMRD - Not available in this package N/A F 16 16 16 pins - EMI Data EMI Data 56F8356 Technical Data, Rev. 13 132 Freescale Semiconductor Preliminary

Configuration Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device Reset GPIO Port GPIO Bit Functional Signal Package PIn Function 0 Peripheral A8 19 1 Peripheral A9 20 2 Peripheral A10 21 3 Peripheral A11 22 4 Peripheral A12 23 5 Peripheral A13 24 6 Peripheral A14 25 GPIOA 7 Peripheral A15 26 8 Peripheral A0 138 9 Peripheral A1 10 10 Peripheral A2 11 11 Peripheral A3 12 12 Peripheral A4 13 13 Peripheral A5 14 0 GPIO1 A16 33 1 N/A 2 N/A 3 N/A GPIOB 4 N/A 5 N/A 6 N/A 7 N/A 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 133 Preliminary

Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device Reset GPIO Port GPIO Bit Functional Signal Package PIn Function 1This is a function of the EMI_MODE, EXTBOOT and Flash security settings at reset. 0 Peripheral PhaseA1 / TB0 / SCLK11 6 1 Peripheral PhaseB1 / TB1 / MOSI11 7 2 Peripheral INDEX1 / TB2 / MISO11 8 3 Peripheral HOME1 / TB3 / SS11 9 4 Peripheral PHASEA0 / TA0 139 GPIOC 5 Peripheral PHASEB0 / TA1 140 6 Peripheral INDEX0 / TA2 141 7 Peripheral HOME0 / TA3 142 8 Peripheral ISA0 113 9 Peripheral ISA1 114 10 Peripheral ISA2 115 56F8356 Technical Data, Rev. 13 134 Freescale Semiconductor Preliminary

Configuration Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device Reset GPIO Port GPIO Bit Functional Signal Package PIn Function 0 GPIO CS2 48 1 GPIO CS3 49 2 N/A 3 N/A 4 N/A 5 N/A GPIOD 6 Peripheral TXD1 42 7 Peripheral RXD1 43 8 Peripheral PS / CS0 46 9 Peripheral DS / CS1 47 10 Peripheral ISB0 50 11 Peripheral ISB1 52 12 Peripheral ISB2 53 0 Peripheral TXD0 4 1 Peripheral RXD0 5 2 Peripheral A6 17 3 Peripheral A7 18 4 Peripheral SCLK0 130 5 Peripheral MOSI0 132 6 Peripheral MISO0 131 GPIOE 7 Peripheral SS0 129 8 Peripheral TC0 118 9 N/A 10 Peripheral TD0 116 11 Peripheral TD1 117 12 N/A 13 N/A 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 135 Preliminary

Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device Reset GPIO Port GPIO Bit Functional Signal Package PIn Function 0 Peripheral D7 28 1 Peripheral D8 29 2 Peripheral D9 30 3 Peripheral D10 32 4 Peripheral D11 133 5 Peripheral D12 134 6 Peripheral D13 135 7 Peripheral D14 136 GPIOF 8 Peripheral D15 137 9 Peripheral D0 59 10 Peripheral D1 60 11 Peripheral D2 72 12 Peripheral D3 75 13 Peripheral D4 76 14 Peripheral D5 77 15 Peripheral D6 78 1. See Part 6.5.8 to determine how to select peripherals from this set; DEC1 is the selected peripheral at reset. Part 9 Joint Test Action Group (JTAG) 9.1 56F8356 Information Please contact your Freescale marketing representative or authorized distributor for device/package-specific BSDL information. Part 10 Specifications 10.1 General Characteristics The 56F8356/56F8156 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture 56F8356 Technical Data, Rev. 13 136 Freescale Semiconductor Preliminary

General Characteristics of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels combined with the ability to receive 5V levels without damage. Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Note: All specifications meet both Automotive and Industrial requirements unless individual specifications are listed. Note: The 56F8156 device is guaranteed to 40MHz and specified to meet Industrial requirements only. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Note: The 56F8156 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8156 device. Table 10-1 Absolute Maximum Ratings (V = V = 0) SS SSA_ADC Characteristic Symbol Notes Min Max Unit Supply voltage V - 0.3 4.0 V DD_IO ADC Supply Voltage VDDA_ADC, VREFH VREFH must be less than or equal - 0.3 4.0 V to VDDA_ADC Oscillator / PLL Supply Voltage V - 0.3 4.0 V DDA_OSC_PLL Internal Logic Core Supply Voltage V OCR_DIS is High - 0.3 3.0 V DD_CORE Input Voltage (digital) V Pin Groups 1, 2, 5, 6, 9, 10 -0.3 6.0 V IN Input Voltage (analog) V Pin Groups 11, 12, 13 -0.3 4.0 V INA Output Voltage V Pin Groups 1, 2, 3, 4, 5, 6, 7, 8 -0.3 4.0 V OUT 6.01 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 137 Preliminary

Table 10-1 Absolute Maximum Ratings (Continued) (V = V = 0) SS SSA_ADC Characteristic Symbol Notes Min Max Unit Output Voltage (open drain) V Pin Group 4 -0.3 6.0 V OD Ambient Temperature (Automotive) T -40 125 °C A Ambient Temperature (Industrial) T -40 105 °C A Junction Temperature (Automotive) T -40 150 °C J Junction Temperature (Industrial) T -40 125 °C J Storage Temperature (Automotive) T -55 150 °C STG Storage Temperature (Industrial) T -55 150 °C STG 1. If corresponding GPIO pin is configured as open drain. Note: Pins in italics are NOT available in the 56F8156 device. Pin Group 1: TXD0-1, RXD0-1, SS0, MISO0, MOSI0 Pin Group 2: PHASEA0, PHASEA1, PHASEB0, PHASEB1, INDEX0, INDEX1, HOME0, HOME1, ISB0-2, ISA0-2, TC0, SCLK0 Pin Group 3: RSTO, TDO Pin Group 4: CAN_TX Pin Group 5: A0-5, D0-15, GPIOD0-1, PS, DS Pin Group 6: A6-15, GPIOB0, TD0-1 Pin Group 7: CLKO, WR, RD Pin Group 8: PWMA0-5, PWMB0-5 Pin Group 9: IRQA, IRQB, RESET, EXTBOOT, TRST, TMS, TDI, CAN_RX, EMI_MODE, FAULTA0-3, FAULTB0-3 Pin Group 10: TCK Pin Group 11: XTAL, EXTAL Pin Group 12: ANA0-7, ANB0-7 Pin Group 13: OCR_DIS, CLKMODE Table 10-2 56F8356/56F8156 ElectroStatic Discharge (ESD) Protection Characteristic Min Typ Max Unit ESD for Human Body Model (HBM) 2000 — — V ESD for Machine Model (MM) 200 — — V ESD for Charge Device Model (CDM) 500 — — V 56F8356 Technical Data, Rev. 13 138 Freescale Semiconductor Preliminary

General Characteristics Table 10-3 Thermal Characteristics6 Value Characteristic Comments Symbol Unit Notes 144-pin LQFP Junction to ambient R 47.1 °C/W 2 θJA Natural convection Junction to ambient (@1m/sec) R 43.8 °C/W 2 θJMA Junction to ambient Four layer board (2s2p) R 40.8 °C/W 1,2 θJMA Natural convection (2s2p) Junction to ambient (@1m/sec) Four layer board (2s2p) R 39.2 °C/W 1,2 θJMA Junction to case R 11.8 °C/W 3 θJC Junction to center of case Ψ 1 °C/W 4, 5 JT I/O pin power dissipation P User-determined W I/O Power dissipation P P = (I x V + P ) W D D DD DD I/O Maximum allowed PD PDMAX (TJ - TA) / RθJA7 W 1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p ther- mal test board. 2. Junction to ambient thermal resistance, Theta-JA (R ) was simulated to be equivalent to the JEDEC specification JESD51-2 θJA in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p, where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. 3. Junction to case thermal resistance, Theta-JC (R ), was simulated to be equivalent to the measured values using the cold θJC plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. Thermal Characterization Parameter, Psi-JT (Ψ ), is the "resistance" from junction to reference point thermocouple on top cen- JT ter of case as defined in JESD51-2. Ψ is a useful value to use to estimate junction temperature in steady-state customer en- JT vironments. 5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. See Part 12.1 for more details on thermal design considerations. 7. TJ = Junction temperature TA = Ambient temperature Note: The 56F8156 device is guaranteed to 40MHz and specified to meet Industrial requirements only. Table 10-4 Recommended Operating Conditions (V = 0V, V = V = 0V V = V = V ) REFLO SS SSA_ADC , DDA DDA_ADC DDA_OSC_PLL Characteristic Symbol Notes Min Typ Max Unit Supply voltage V 3 3.3 3.6 V DD_IO 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 139 Preliminary

Table 10-4 Recommended Operating Conditions (V = 0V, V = V = 0V V = V = V ) REFLO SS SSA_ADC , DDA DDA_ADC DDA_OSC_PLL Characteristic Symbol Notes Min Typ Max Unit ADC Supply Voltage V V must be less than 3 3.3 3.6 V DDA_ADC, REFH V or equal to V REFH DDA_ADC Oscillator / PLL Supply Voltage V 3 3.3 3.6 V DDA_OSC_PLL Internal Logic Core Supply V OCR_DIS is High 2.25 2.5 2.75 V DD_CORE Voltage Device Clock Frequency FSYSCLK 0 — 60 MHz Input High Voltage (digital) V Pin Groups 1, 2, 5, 6, 9, 10 2 — 5.5 V IN Input High Voltage (analog) V Pin Group 13 2 — V +0.3 V IHA DDA Input High Voltage (XTAL/EXTAL, V Pin Group 11 V -0.8 — V +0.3 V IHC DDA DDA XTAL is not driven by an external clock) Input high voltage (XTAL/EXTAL, V Pin Group 11 2 — V +0.3 V IHC DDA XTAL is driven by an external clock) Input Low Voltage V Pin Groups -0.3 — 0.8 V IL 1, 2, 5, 6, 9, 10, 11, 13 Output High Source Current I Pin Groups 1, 2, 3 — — -4 mA OH V = 2.4V (V min.) OH OH Pin Groups 5, 6, 7 — — -8 Pin Group 8 — — -12 Output Low Sink Current I Pin Groups 1, 2, 3, 4 — — 4 mA OL V = 0.4V (V max) OL OL Pin Groups 5, 6, 7 — — 8 Pin Group 8 — — 12 Ambient Operating Temperature T -40 — 125 °C A (Automotive) Ambient Operating Temperature T -40 — 105 °C A (Industrial) Flash Endurance (Automotive) N T = -40°Cto 125°C 10,000 — — Cycles F A (Program Erase Cycles) Flash Endurance (Industrial) N T = -40°Cto 105°C 10,000 — — Cycles F A (Program Erase Cycles) Flash Data Retention T T <= 85°Cavg 15 — — Years R J Note: Total chip source or sink current cannot exceed 200mA See Pin Groups in Table10-1 10.2 DC Electrical Characteristics Note: The 56F8156 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8156 device. 56F8356 Technical Data, Rev. 13 140 Freescale Semiconductor Preliminary

DC Electrical Characteristics Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Table10-4 Characteristic Symbol Notes Min Typ Max Unit Test Conditions Output High Voltage V 2.4 — — V I = I OH OH OHmax Output Low Voltage V — — 0.4 V I = I OL OL OLmax Digital Input Current High I Pin Groups 1, 2, 5, 6, 9 — 0 +/- 2.5 μA V = 3.0V to 5.5V IH IN pull-up enabled or disabled Digital Input Current High I Pin Group10 40 80 160 μA V = 3.0V to 5.5V IH IN with pull-down Analog Input Current High I Pin Group 13 — 0 +/- 2.5 μA V = V IHA IN DDA ADC Input Current High I Pin Group 12 — 0 +/- 3.5 μA V = V IHADC IN DDA Digital Input Current Low I Pin Groups 1, 2, 5, 6, 9 -200 -100 -50 μA V = 0V IL IN pull-up enabled Digital Input Current Low I Pin Groups 1, 2, 5, 6, 9 — 0 +/- 2.5 μA V = 0V IL IN pull-up disabled Digital Input Current Low I Pin Group 10 — 0 +/- 2.5 μA V = 0V IL IN with pull-down Analog Input Current Low I Pin Group 13 — 0 +/- 2.5 μA V = 0V ILA IN ADC Input Current Low I Pin Group 12 — 0 +/- 3.5 μA V = 0V ILADC IN EXTAL Input Current Low I — 0 +/- 2.5 μA V = V or 0V EXTAL IN DDA clock input XTAL Input Current Low I CLKMODE = High — 0 +/- 2.5 μA V = V or 0V XTAL IN DDA clock input CLKMODE = Low — — 200 μA V = V or 0V IN DDA Output Current I Pin Groups — 0 +/- 2.5 μA V = 3.0V to 5.5V OZ OUT High Impedance State 1, 2, 3, 4, 5, 6, 7, 8 or 0V Schmitt Trigger Input V Pin Groups 2, 6, 9,10 — 0.3 — V — HYS Hysteresis Input Capacitance C — 4.5 — pF — INC (EXTAL/XTAL) Output Capacitance C — 5.5 — pF — OUTC (EXTAL/XTAL) Input Capacitance C — 6 — pF — IN Output Capacitance C — 6 — pF — OUT See Pin Groups in Table10-1 RES = (VREFH - VREFLO) X 1 212 m 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 141 Preliminary

Table 10-6 Power on Reset Low Voltage Parameters Characteristic Symbol Min Typ Max Units POR Trip Point POR 1.75 1.8 1.9 V LVI, 2.5 volt Supply, trip point1 VEI2.5 — 2.14 — V LVI, 3.3 volt supply, trip point2 VEI3.3 — 2.7 — V Bias Current I — 110 130 μA bias 1. When V drops below V , an interrupt is generated. DD_CORE EI2.5 2. When V drops below V , an interrupt is generated. DD_CORE EI3.3 Table 10-7 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Enabled (OCR_DIS = Low) Mode IDD_IO1 IDD_ADC IDD_OSC_PLL Test Conditions RUN1_MAC 155mA 50mA 2.5mA • 60MHz Device Clock • All peripheral clocks are enabled • All peripherals running • Continuous MAC instructions with fetches from Data RAM • ADC powered on and clocked Wait3 91mA 70μA 2.5mA • 60MHz Device Clock • All peripheral clocks are enabled • ADC powered off Stop1 6mA 0μA 155μA • 8MHz Device Clock • All peripheral clocks are off • ADC powered off • PLL powered off Stop2 5.1mA 0μA 145μA • External Clock is off • All peripheral clocks are off • ADC powered off • PLL powered off 1. No Output Switching 2. Includes Processor Core current supplied by internal voltage regulator 56F8356 Technical Data, Rev. 13 142 Freescale Semiconductor Preliminary

DC Electrical Characteristics Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) Mode IDD_Core IDD_IO1 IDD_ADC IDD_OSC_PLL Test Conditions RUN1_MAC 150mA 13μA 50mA 2.5mA • 60MHz Device Clock • All peripheral clocks are enabled • All peripherals running • Continuous MAC instructions with fetches from Data RAM • ADC powered on and clocked Wait3 86mA 13μA 70μA 2.5mA • 60MHz Device Clock • All peripheral clocks are enabled • ADC powered off Stop1 900μA 13μA 0μA 155μA • 8MHz Device Clock • All peripheral clocks are off • ADC powered off • PLL powered off Stop2 100μA 13μA 0μA 145μA • External Clock is off • All peripheral clocks are off • ADC powered off • PLL powered off 1. No Output Switching Table 10-9. Regulator Parameters Characteristic Symbol Min Typical Max Unit Unloaded Output Voltage V 2.25 — 2.75 V RNL (0mA Load) Loaded Output Voltage V 2.25 — 2.75 V RL (200 mA load) Line Regulation @ 250 mA load V 2.25 — 2.75 V R (V 33 ranges from 3.0 to 3.6) DD Short Circuit Current Iss — — 700 mA (output shorted to ground) Bias Current I — 5.8 7 mA bias Power-down Current I — 0 2 μA pd Short-Circuit Tolerance T — — 30 minutes RSC (output shorted to ground) 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 143 Preliminary

Table 10-10. PLL Parameters Characteristics Symbol Min Typical Max Unit PLL Start-up time T 0.3 0.5 10 ms PS Resonator Start-up time T 0.1 0.18 1 ms RS Min-Max Period Variation T 120 — 200 ps PV Peak-to-Peak Jitter T — — 175 ps PJ Bias Current I — 1.5 2 mA BIAS Quiescent Current, power-down mode I — 100 150 μA PD 10.2.1 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8156 device. Table 10-11 Temperature Sense Parametrics Characteristics Symbol Min Typical Max Unit Slope (Gain)1 m — 7.762 — mV/°C Room Trim Temp. 1, 2 TRT 24 26 28 °C Hot Trim Temp. (Industrial)1,2 THT 122 125 128 °C Hot Trim Temp. (Automotive)1,2 THT 147 150 153 °C Output Voltage @ V — 1.370 — V TS0 V = 3.3V, T =0°C1 DDA_ADC J Supply Voltage V 3.0 3.3 3.6 V DDA_ADC Supply Current - OFF I — — 10 μA DD-OFF Supply Current - ON I — — 250 μA DD-ON Accuracy3,1 from -40°C to 150°C TACC -6.7 0 6.7 °C Using V = mT + V TS TS0 Resolution4, 5,1 RES — 0.104 — °C / bit 1. Includes the ADC conversion of the analog Temperature Sense voltage. 2. The ADC is not calibrated for the conversion of the Temperature Sensor trim value stored in the Flash Memory at FMOPT0 and FMOPT1. 3. See Application Note, AN1980, for methods to increase accuracy. 4. Assuming a 12-bit range from 0V to 3.3V. 5. Typical resolution calculated using equation, 56F8356 Technical Data, Rev. 13 144 Freescale Semiconductor Preliminary

AC Electrical Characteristics 10.3 AC Electrical Characteristics Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure10-1. V Low High IH 90% Input Signal Midpoint1 50% 10% V Fall Time IL Rise Time Note: The midpoint is V + (V – V )/2. IL IH IL Figure 10-1 Input Signal Measurement References Figure 10-2 shows the definitions of the following signal states: • Active state, when a bus or signal is driven, and enters a low impedance state • Tri-stated, when a bus or signal is placed in a high impedance state • Data Valid state, when a signal level has reached V or V OL OH • Data Invalid state, when a signal level is in transition between V and V OL OH Data1 Valid Data2 Valid Data3 Valid Data1 Data2 Data3 Data Data Invalid State Tri-stated Data Active Data Active Figure 10-2 Signal States 10.4 Flash Memory Characteristics Table 10-12 Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time1 Tprog 20 — — μs Erase time2 Terase 20 — — ms Mass erase time Tme 100 — — ms 1. There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual for details. Program time is per 16-bit word in Flash memory. Two words at a time can be programmed within the Pro- gram Flash module, as it contains two interleaved memories. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 145 Preliminary

2. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes. 10.5 External Clock Operation Timing Table 10-13 External Clock Operation Timing Requirements1 Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)2 fosc 0 — 120 MHz Clock Pulse Width3 tPW 3.0 — — ns External clock input rise time4 trise — — 10 ns External clock input fall time5 tfall — — 10 ns 1. Parameters listed are guaranteed by design. 2. See Figure10-3 for details on using the recommended connection of an external clock driver. 3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function. 4. External clock input rise time is measured from 10% to 90%. 5. External clock input fall time is measured from 90% to 10%. V IH External 90% 90% 50% 50% Clock 10% 10% tPW tPW tfall trise VIL Note: The midpoint is V + (V – V )/2. IL IH IL Figure 10-3 External Clock Timing 10.6 Phase Locked Loop Timing Table 10-14 PLL Timing Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 fosc 4 8 8.4 MHz PLL output frequency2 (fOUT) fop 160 — 260 MHz PLL stabilization time3 -40° to +125°C tplls — 1 10 ms 1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f /2), please refer to the OCCS chapter in OUT the 56F8300 Peripheral User Manual. 56F8356 Technical Data, Rev. 13 146 Freescale Semiconductor Preliminary

Crystal Oscillator Timing 3. This is the minimum time required after the PLL set up is changed to ensure reliable operation. 10.7 Crystal Oscillator Timing Table 10-15 Crystal Oscillator Parameters Characteristic Symbol Min Typ Max Unit Crystal Start-up time T 4 5 10 ms CS Resonator Start-up time T 0.1 0.18 1 ms RS Crystal ESR R — — 120 ohms ESR Crystal Peak-to-Peak Jitter T 70 — 250 ps D Crystal Min-Max Period Variation T 0.12 — 1.5 ns PV Resonator Peak-to-Peak Jitter T — — 300 ps RJ Resonator Min-Max Period Variation T — — 300 ps RP Bias Current, high-drive mode I — 250 290 μA BIASH Bias Current, low-drive mode I — 80 110 μA BIASL Quiescent Current, power-down mode I — 0 1 μA PD 10.8 External Memory Interface Timing The External Memory Interface is designed to access static memory and peripheral devices. Figure 10-4 shows sample timing and parameters that are detailed in Table10-16. The timing of each parameter consists of both a fixed delay portion and a clock related portion, as well as user controlled wait states. The equation: t = D + P * (M + W) should be used to determine the actual time of each parameter. The terms in this equation are defined as: t = Parameter delay time D = Fixed portion of the delay, due to on-chip path delays P = Period of the system clock, which determines the execution rate of the part (i.e., when the device is operating at 60MHz, P = 16.67 ns) M = Fixed portion of a clock period inherent in the design; this number is adjusted to account for possible derating of clock duty cycle W = Sum of the applicable wait state controls. The “Wait State Controls” column of Table10-16 shows the applicable controls for each parameter and the EMI chapter of the 56F8300 Peripheral User Manual details what each wait state field controls. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 147 Preliminary

When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects prescaler clock and prescaler set to ÷ 1), the EMI quadrature clock is generated using both edges of the EXTAL clock input. In this situation only, parameter values must be adjusted for the duty cycle at XTAL. DCAOE and DCAEO are used to make this duty cycle adjustment where needed. DCAOE and DCAEO are calculated as follows: DCAOE = 0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1 = 0.0 all other cases DCAEO = MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1 = 0.0 all other cases Example of DCAOE and DCAEO calculation Assuming prescaler is set for ÷ 1 and prescaler clock is selected by ZSRC, if XTAL duty cycle ranges between 45% and 60% high: DCAOE = .50 - .60 = - 0.1 DCAEO = .45 - .50 = - 0.05 The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column of Table 10-16 to make the appropriate selection. A0-Axx,CS t ARDD t RDA t ARDA tRD tRDRD RD t WR tAWR tWAC tWRWR tWRRD tRDWR WR t t t RDD DWR DOH t t t DOS AD DRD D0-D15 Data Out Data In Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 10-4 External Memory Interface Timing 56F8356 Technical Data, Rev. 13 148 Freescale Semiconductor Preliminary

External Memory Interface Timing Note: When multiple lines are given for the same wait state configuration, calculate each and then select the smallest or most negative. Table 10-16 External Memory Interface Timing Wait States Wait States Characteristic Symbol D M Unit Configuration Controls WWS=0 -1.477 0.50 Address Valid to WR Asserted tAWR WWSS ns WWS>0 -1.564 0.75 + DCAOE WWS=0 -0.186 0.25 + DCAOE WR Width Asserted to WR tWR WWS ns Deasserted WWS>0 -0.256 0 WWS=0 -9.568 0.25 + DCAEO Data Out Valid to WR Asserted WWS=0 -1.721 0.00 tDWR WWSS ns WWS>0 -9.227 0.50 WWS>0 -1.808 0.25 + DCAOE Valid Data Out Hold Time after WR tDOH -2.287 0.25 + DCAEO WWSH ns Deasserted -1.622 0.25 + DCAOE Valid Data Out Set-Up Time to tDOS WWS,WWSS ns WR Deasserted -9.041 0.50 t Valid Address after WR WAC -3.918 0.25 + DCAEO WWSH ns Deasserted RD Deasserted to Address tRDA -2.229 0.00 RWSH ns Invalid Address Valid to RD Deasserted tARDD -1.887 1.00 RWSS,RWS ns Valid Input Data Hold after RD tDRD 0.00 N/A1 — ns Deasserted RD Assertion Width tRD 0.212 1.00 RWS ns -14.427 1.00 Address Valid to Input Data tAD RWSS,RWS ns Valid -19.751 1.25 + DCAOE Address Valid to RD Asserted tARDA -2.121 0.00 RWSS ns -12.306 1.00 RD Asserted to Input Data Valid tRDD RWSS,RWS ns -17.630 1.25 + DCAOE WR Deasserted to RD Asserted tWRRD -1.923 0.25 + DCAEO WWSH,RWSS ns 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 149 Preliminary

Table 10-16 External Memory Interface Timing (Continued) Wait States Wait States Characteristic Symbol D M Unit Configuration Controls RWSS,RWSH RD Deasserted to RD Asserted tRDRD -0.2342 0.00 MDAR3, 4 ns WWS=0 -1.279 0.75 + DCAEO WR Deasserted to WR Asserted tWRWR WWSS, WWSH ns WWS>0 -0.938 1.00 RD Deasserted to WR Asserted tRDWR WWWWSS>=00 -00..005426 0.75 +0 .D50C AOE RWSMHD, AWRW3 SS, ns 1. N/A since device captures data before it deasserts RD 2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads. 3. Substitute BMDAR for MDAR if there is no chip select 4. MDAR is acive in this calculation only when the chip select changes. 10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 Typical Typical Characteristic Symbol Unit See Figure Min Max RESET Assertion to Address, Data and Control t — 21 ns 10-5 RAZ Signals High Impedance Minimum RESET Assertion Duration t 16T — ns 10-5 RA RESET Deassertion to First External Address t 63T 64T ns 10-5 RDA Output3 Edge-sensitive Interrupt Request Width t 1.5T — ns 10-6 IRW IRQA, IRQB Assertion to External Data Memory t 18T — ns 10-7 IDM Access Out Valid, caused by first instruction execution in the interrupt service routine t 14T — IDM - FAST IRQA, IRQB Assertion to General Purpose Output t 18T — ns 10-7 IG Valid, caused by first instruction execution in the interrupt service routine t 14T — IG - FAST Delay from IRQA Assertion (exiting Wait) to t 22T — ns 10-8 IRI External Data Memory Access4 t 18T — IRI -FAST Delay from IRQA Assertion to External Data t 22T — ns 10-9 IF Memory Access (exiting Stop) t 18T — IF - FAST 56F8356 Technical Data, Rev. 13 150 Freescale Semiconductor Preliminary

Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 (Continued) Typical Typical Characteristic Symbol Unit See Figure Min Max IRQA Width Assertion to Recover from Stop t 1.5T — ns 10-9 IW State5 1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T=16.67ns. At 8MHz (used during Reset and Stop modes), T = 125ns. 2. Parameters listed are guaranteed by design. 3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 221T. 4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 5. The interrupt instruction fetch is visible on the pins only in Mode 3. RESET t RA t t RAZ RDA A0–A15, First Fetch D0–D15 Figure 10-5 Asynchronous Reset Timing IRQA, IRQB t IRW Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive) 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 151 Preliminary

A0–A15 First Interrupt Instruction Execution t IDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin t IG IRQA, IRQB b) General Purpose I/O Figure 10-7 External Level-Sensitive Interrupt Timing IRQA , IRQB t IRI A0–A15 First Interrupt Vector Instruction Fetch Figure 10-8 Interrupt from Wait State Timing t IW IRQA t IF A0–A15 First Instruction Fetch Not IRQA Interrupt Vector Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing 56F8356 Technical Data, Rev. 13 152 Freescale Semiconductor Preliminary

Serial Peripheral Interface (SPI) Timing 10.10 Serial Peripheral Interface (SPI) Timing Table 10-18 SPI Timing1 Characteristic Symbol Min Max Unit See Figure Cycle time t 10-10, 10-11, C Master 50 — ns 10-12, 10-13 Slave 50 — ns Enable lead time t 10-13 ELD Master — — ns Slave 25 — ns Enable lag time t 10-13 ELG Master — — ns Slave 100 — ns Clock (SCK) high time t 10-10, 10-11, CH Master 17.6 — ns 10-12, 10-13 Slave 25 — ns Clock (SCK) low time t 10-13 CL Master 24.1 — ns Slave 25 — ns Data set-up time required for inputs t 10-10, 10-11, DS Master 20 — ns 10-12, 10-13 Slave 0 — ns Data hold time required for inputs t 10-10, 10-11, DH Master 0 — ns 10-12, 10-13 Slave 2 — ns Access time (time to data active from t 10-13 A high-impedance state) 4.8 15 ns Slave Disable time (hold time to high-impedance state) t 10-13 D Slave 3.7 15.2 ns Data Valid for outputs t 10-10, 10-11, DV Master — 4.5 ns 10-12, 10-13 Slave (after enable edge) — 20.4 ns Data invalid t 10-10, 10-11, DI Master 0 — ns 10-12 Slave 0 — ns Rise time t 10-10, 10-11, R Master — 11.5 ns 10-12, 10-13 Slave — 10.0 ns 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 153 Preliminary

Table 10-18 SPI Timing1 (Continued) Characteristic Symbol Min Max Unit See Figure Fall time t 10-10, 10-11, F Master — 9.7 ns 10-12, 10-13 Slave — 9.0 ns 1. Parameters listed are guaranteed by design. SS SS is held High on master (Input) t C t R t F SCLK (CPOL = 0) tCL (Output) t CH t F t R t SCLK (CPOL = 1) CL (Output) tDH tCH t DS MISO MSB in Bits 14–1 LSB in (Input) tDI tDV tDI(ref) MOSI Master MSB out Bits 14–1 Master LSB out (Output) t t F R Figure 10-10 SPI Master Timing (CPHA = 0) 56F8356 Technical Data, Rev. 13 154 Freescale Semiconductor Preliminary

Serial Peripheral Interface (SPI) Timing SS SS is held High on master (Input) t C t F t R t CL SCLK (CPOL = 0) (Output) t CH t F t CL SCLK (CPOL = 1) (Output) t CH t DS tR tDH MISO MSB in Bits 14–1 LSB in (Input) tDV(ref) tDI tDV tDI(ref) MOSI Master MSB out Bits 14– 1 Master LSB out (Output) t t F R Figure 10-11 SPI Master Timing (CPHA = 1) 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 155 Preliminary

SS (Input) t C t F t ELG t CL t R SCLK (CPOL = 0) (Input) t CH t ELD t CL SCLK (CPOL = 1) (Input) t tA CH tR tF t D MISO Slave MSB out Bits 14–1 Slave LSB out (Output) tDS tDV tDI tDI t DH MOSI MSB in Bits 14–1 LSB in (Input) Figure 10-12 SPI Slave Timing (CPHA = 0) 56F8356 Technical Data, Rev. 13 156 Freescale Semiconductor Preliminary

Quad Timer Timing SS (Input) t t F C t R t SCLK (CPOL = 0) CL (Input) t CH t ELG t ELD t CL SCLK (CPOL = 1) (Input) t t DV CH t R t A tF tD MISO Slave MSB out Bits 14–1 Slave LSB out (Output) t t DS DV t DI t DH MOSI MSB in Bits 14–1 LSB in (Input) Figure 10-13 SPI Slave Timing (CPHA = 1) 10.11 Quad Timer Timing Table 10-19 Timer Timing1, 2 Characteristic Symbol Min Max Unit See Figure Timer input period P 2T + 6 — ns 10-14 IN Timer input high / low period P 1T + 3 — ns 10-14 INHL Timer output period P 1T - 3 — ns 10-14 OUT Timer output high / low period P 0.5T - 3 — ns 10-14 OUTHL 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns. 2. Parameters listed are guaranteed by design. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 157 Preliminary

Timer Inputs P P P INHL INHL IN Timer Outputs POUT POUTHL POUTHL Figure 10-14 Timer Timing 10.12 Quadrature Decoder Timing Table 10-20 Quadrature Decoder Timing1, 2 Characteristic Symbol Min Max Unit See Figure Quadrature input period P 4T + 12 — ns 10-15 IN Quadrature input high / low period P 2T + 6 — ns 10-15 HL Quadrature phase period P 1T + 3 — ns 10-15 PH 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns. 2. Parameters listed are guaranteed by design. P P P P PH PH PH PH Phase A (Input) P HL P IN P HL Phase B P (Input) HL P P IN HL Figure 10-15 Quadrature Decoder Timing 56F8356 Technical Data, Rev. 13 158 Freescale Semiconductor Preliminary

Serial Communication Interface (SCI) Timing 10.13 Serial Communication Interface (SCI) Timing Table 10-21 SCI Timing1 Characteristic Symbol Min Max Unit See Figure Baud Rate2 BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-16 TXD4 Pulse Width TXDPW 0.965/BR 1.04/BR ns 10-17 1. Parameters listed are guaranteed by design. 2. f is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8356 device and MAX 40MHz for the 56F8156 device. 3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. RXD SCI receive data pin (Input) RXDPW Figure 10-16 RXD Pulse Width TXD SCI receive data pin TXD (Input) PW Figure 10-17 TXD Pulse Width 10.14 Controller Area Network (CAN) Timing Note: CAN is NOT available in the 56F8156 device. Table 10-22 CAN Timing1 Characteristic Symbol Min Max Unit See Figure Baud Rate BR — 1 Mbps — CAN Bus Wake Up detection T 5 — μs 10-18 WAKEUP 1. Parameters listed are guaranteed by design 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 159 Preliminary

CAN_RX CAN receive data pin T (Input) WAKEUP Figure 10-18 Bus Wake Up Detection 10.15 JTAG Timing Table 10-23 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK frequency of operation using f DC SYS_CLK/8 MHz 10-19 OP EOnCE1 TCK frequency of operation not f DC SYS_CLK/4 MHz 10-19 OP using EOnCE1 TCK clock pulse width t 50 — ns 10-19 PW TMS, TDI data set-up time t 5 — ns 10-20 DS TMS, TDI data hold time t 5 — ns 10-20 DH TCK low to TDO data valid t — 30 ns 10-20 DV TCK low to TDO tri-state t — 30 ns 10-20 TS TRST assertion time tTRST 2T2 — ns 10-21 1. TCK frequency of operation must be less than 1/8 the processor rate. 2. T = processor clock period (nominally 1/60MHz) 1/f OP tPW tPW V IH V V TCK M M (Input) V IL V = V + (V – V )/2 M IL IH IL Figure 10-19 Test Clock Input Timing Diagram 56F8356 Technical Data, Rev. 13 160 Freescale Semiconductor Preliminary

Analog-to-Digital Converter (ADC) Parameters TCK (Input) t t DS DH TDI TMS Input Data Valid (Input) t DV TDO Output Data Valid (Output) t TS TDO (Output) t DV TDO Output Data Valid (Output) Figure 10-20 Test Access Port Timing Diagram TRST (Input) t TRST Figure 10-21 TRST Timing Diagram 10.16 Analog-to-Digital Converter (ADC) Parameters Table 10-24 ADC Parameters Characteristic Symbol Min Typ Max Unit Input voltages V V — V V ADIN REFL REFH Resolution R 12 — 12 Bits ES Integral Non-Linearity1 INL — +/- 2.4 +/- 3.2 LSB2 Differential Non-Linearity DNL — +/- 0.7 < +1 LSB2 Monotonicity GUARANTEED ADC internal clock f 0.5 — 5 MHz ADIC Conversion range R V — V V AD REFL REFH ADC channel power-up time tADPU 5 6 16 tAIC cycles3 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 161 Preliminary

Table 10-24 ADC Parameters (Continued) Characteristic Symbol Min Typ Max Unit ADC reference circuit power-up time4 tVREF — — 25 ms Conversion time tADC — 6 — tAIC cycles3 Sample time tADS — 1 — tAIC cycles3 Input capacitance C — 5 — pF ADI Input injection current5, per pin IADI — — 3 mA Input injection current, total I — — 20 mA ADIT V current I — 1.2 3 mA REFH VREFH ADC A current I — 25 — mA ADCA ADC B current I — 25 — mA ADCB Quiescent current I — 0 10 μA ADCQ Uncalibrated Gain Error (ideal = 1) E — +/- .004 +/- .015 — GAIN Uncalibrated Offset Voltage V — +/- 15 +/- 35 mV OFFSET Calibrated Absolute Error6 AECAL — See Figure10-22 — LSBs Calibration Factor 17 CF1 — 0.010380 — — Calibration Factor 27 CF2 — -31.7 — — Crosstalk between channels — — -60 — dB Common Mode Voltage V — (V - V ) / 2 — V common REFH REFLO Signal-to-noise ratio SNR — 64.6 — db Signal-to-noise plus distortion ratio SINAD — 59.1 — db Total Harmonic Distortion THD — 60.6 — db Spurious Free Dynamic Range SFDR — 61.1 — db Effective Number Of Bits8 ENOB — 9.6 — Bits 1. INL measured from V = .1V to V = .9V in REFH in REFH 10% to 90% Input Signal Range 2. LSB = Least Significant Bit 3. ADC clock cycles 4. Assumes each voltage reference pin is bypassed with 0.1μF ceramic capacitors to ground 5. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible. 6. Absolute error includes the effects of both gain error and offset error. 7. Please see the 56F8300 Peripheral User’s Manual for additional information on ADC calibration. 8. ENOB = (SINAD - 1.76)/6.02 56F8356 Technical Data, Rev. 13 162 Freescale Semiconductor Preliminary

Analog-to-Digital Converter (ADC) Parameters Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC = 0.60V and 2.70V in Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error. The data was taken on 14 parts: three each from three processing corner lots and two from the fourth processing corner lot, as well as three from one nominally processed lot, each at three temperatures: -40°C, 27°C, and 150°C (giving the 42 data points shown above), for two input DC voltages: 0.60V and 2.70V. The data indicates that for the given population of parts, calibration significantly reduced (by as much as 28%) the collective variation (spread) of the absolute error of the population. It also significantly reduced (by as much as 80%) the mean (average) of the absolute error and thereby brought it significantly closer to the ideal value of zero. Although not guaranteed, it is believed that calibration will produce results similar to those shown above for any population of parts including those which represent processing and temperature extremes. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 163 Preliminary

10.17 Equivalent Circuit for ADC Inputs Figure 10-23 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to V - V / 2, while the other charges to the analog input voltage. When the REFH REFH switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended analog input is switched to a differential voltage centered about V - V / 2. The switches switch REFH REFH on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, V and the ADC clock frequency. REF Analog Input 3 4 S1 C1 S3 S/H (V - V ) / 2 REFH REFLO 1 2 S2 C2 C1 = C2 = 1pF 1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf 2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf 56F8356 Technical Data, Rev. 13 164 Freescale Semiconductor Preliminary

Power Consumption 3. Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms 4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected to it at sampling time; 1pf Figure 10-23 Equivalent Circuit for A/D Loading 10.18 Power Consumption This section provides additional detail which can be used to optimize power consumption for a given application. Power consumption is given by the following equation: Total power = A: internal [static component] +B: internal [state-dependent component] +C: internal [dynamic component] +D: external [dynamic component] +E: external [static] A, the internal [static component], is comprised of the DC bias currents for the oscillator, PLL, leakage current, and voltage references. These sources operate independently of processor state or operating frequency. B, the internal [state-dependent component], reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, Flash memory and the ADCs. C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic. D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two of the IO cell types used on the device reveal that the power-versus-load curve does have a non-zero Y-intercept. Table 10-25 IO Loading Coefficients at 10MHz Intercept Slope PDU08DGZ_ME 1.3 0.11mW / pF PDU04DGZ_ME 1.15mW 0.11mW / pF Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. Table 10-25 provides coefficients for calculating power dissipated in the IO cells as a function of capacitive load. In these cases: TotalPower = Σ((Intercept +Slope*Cload)*frequency/10MHz) 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 165 Preliminary

where: • Summation is performed over all output pins with capacitive loads • TotalPower is expressed in mW • Cload is expressed in pF Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. The one possible exception to this is if the chip is using the external address and data buses at a rate approaching the maximum system rate. In this case, power from these buses can be significant. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of 8 PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible. 56F8356 Technical Data, Rev. 13 166 Freescale Semiconductor Preliminary

56F8356 Package and Pin-Out Information Part 11 Packaging 11.1 56F8356 Package and Pin-Out Information This section contains package and pin-out information for the 56F8356. This device comes in a 144-pin Low-profile Quad Flat Pack (LQFP). Figure11-1 shows the package outline for the 144-pin LQFP, Figure 11-3 shows the mechanical parameters for this package, and Table 11-1 lists the pin-out for the 144-pin LQFP. E VSSEMI_MODHOME0INDEX0PHASEB0PHASEA0A0D15D14D13D12D11MOSI0MISO0SCLK0SS0V2CAPCAN_RXCAN_TXVIPPTDOTDITMSTCKTRSTVDD_IOTC0TD1TD0ISA2ISA1ISA0EXTBOOTANB7ANB6ANB5 Orientation Mark VDD_IO ANB4 VPP2 ANB3 CLKO Pin 1 109 ANB2 TXD0 ANB1 RXD0 ANB0 PHASEA1 VSSA_ADC PHINADSEEXB11 VVDRDEAFH_ADC HOMEAA121 VVVRRREEEFFFPNMID A3 VREFLO A4 Temp_Sense A5 ANA7 VCAP4 ANA6 VDD_IO ANA5 A6 ANA4 A7 ANA3 A8 ANA2 A9 ANA1 A10 ANA0 A11 CLKMODE A12 RESET A13 RSTO AAV11S5S4 EVVXCDADTP_AI3OL D7 XTAL D8 VDDA_OSC_PLL D9 OCR_DIS VDD_IO D6 D10 D5 GPIOB0 D4 PWMB0 37 73 D3 PWMB1 FAULTA2 PWMB2 FAULTA1 S O34511RDSS010112AB0120130 S12 O34 S502 VSVDD_IWMBWMBWMBTXDRXDWRPDPIODPIODISBVCAPISBISBIRQIRQULTBULTBULTBDDULTBWMAVSWMAWMAVDD_IWMAWMAVSWMAULTAD PPP GG AAA AP PP PP PA FFF F F Figure 11-1 Top View, 56F8356 144-Pin LQFP Package 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 167 Preliminary

Table 11-1 56F8356 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Name 1 V 37 V 73 FAULTA1 109 ANB5 DD_IO SS 2 V 2 38 V 74 FAULTA2 110 ANB6 PP DD_IO 3 CLKO 39 PWMB3 75 D3 111 ANB7 4 TXD0 40 PWMB4 76 D4 112 EXTBOOT 5 RXD0 41 PWMB5 77 D5 113 ISA0 6 PHASEA1 42 TXD1 78 D6 114 ISA1 7 PHASEB1 43 RXD1 79 OCR_DIS 115 ISA2 8 INDEX1 44 WR 80 V 116 TD0 DDA_OSC_PLL 9 HOME1 45 RD 81 XTAL 117 TD1 10 A1 46 PS 82 EXTAL 118 TC0 11 A2 47 DS 83 V 3 119 V CAP DD_IO 12 A3 48 GPIOD0 84 V 120 TRST DD_IO 13 A4 49 GPIOD1 85 RSTO 121 TCK 14 A5 50 ISB0 86 RESET 122 TMS 15 V 4 51 V 1 87 CLKMODE 123 TDI CAP CAP 16 V 52 ISB1 88 ANA0 124 TDO DD_IO 17 A6 53 ISB2 89 ANA1 125 V 1 PP 18 A7 54 IRQA 90 ANA2 126 CAN_TX 19 A8 55 IRQB 91 ANA3 127 CAN_RX 20 A9 56 FAULTB0 92 ANA4 128 V 2 CAP 21 A10 57 FAULTB1 93 ANA5 129 SS0 22 A11 58 FAULTB2 94 ANA6 130 SCLK0 23 A12 59 D0 95 ANA7 131 MISO0 24 A13 60 D1 96 TEMP_SENSE 132 MOSI0 25 A14 61 FAULTB3 97 V 133 D11 REFLO 56F8356 Technical Data, Rev. 13 168 Freescale Semiconductor Preliminary

56F8156 Package and Pin-Out Information Table 11-1 56F8356 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Name 26 A15 62 PWMA0 98 V 134 D12 REFN 27 V 63 V 99 V 135 D13 SS SS REFMID 28 D7 64 PWMA1 100 V 136 D14 REFP 29 D8 65 PWMA2 101 V 137 D15 REFH 30 D9 66 V 102 V 138 A0 DD_IO DDA_ADC 31 V 67 PWMA3 103 V 139 PHASEA0 DD_IO SSA_ADC 32 D10 68 PWMA4 104 ANB0 140 PHASEB0 33 GPIOB0 69 V 105 ANB1 141 INDEX0 SS 34 PWMB0 70 PWMA5 106 ANB2 142 HOME0 35 PWMB1 71 FAULTA0 107 ANB3 143 EMI_MODE 36 PWMB2 72 D2 108 ANB4 144 V SS 11.2 56F8156 Package and Pin-Out Information This section contains package and pin-out information for the 56F8156. This device comes in a 144-pin Low-profile Quad Flat Pack (LQFP). Figure11-1 shows the package outline for the 144-pin LQFP, Figure 11-3 shows the mechanical parameters for this package, and Table 11-1 lists the pin-out for the 144-pin LQFP. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 169 Preliminary

E VSSEMI_MODHOME0INDEX0PHASEB0PHASEA0A0D15D14D13D12D11MOSI0MISO0SCLK0SS0V2CAPNCNCVIPPTDOTDITMSTCKTRSTVDD_IOTC0GPIOE11GPIOE10GPIOC10GPIOC9GPIOC8EXTBOOTANB7ANB6ANB5 Orientation Mark VDD_IO ANB4 VPP2 ANB3 CLKO Pin 1 109 ANB2 TXD0 ANB1 RXD0 ANB0 SCLK1 VSSA_ADC MMIOSSOI11 VVDRDEAFH_ADC SSAA121 VVVRRREEEFFFPNMID A3 VREFLO A4 NC A5 ANA7 VCAP4 ANA6 VDD_IO ANA5 A6 ANA4 A7 ANA3 A8 ANA2 A9 ANA1 A10 ANA0 A11 CLKMODE A12 RESET A13 RSTO AAV11S5S4 EVVXCDADTP_AI3OL D7 XTAL D8 VDDA_OSC_PLL D9 OCR_DIS VDD_IO D6 D10 D5 GPIOB0 D4 PWMB0 37 73 D3 PWMB1 NC PWMB2 NC S O34511RDSS010112AB012013C SCC OCC SCC2 VSVDD_IWMBWMBWMBTXDRXDWRPDPIODPIODISBVCAPISBISBIRQIRQULTBULTBULTBDDULTBNVSNNVDD_INNVSNND PPP GG AAA A FFF F Figure 11-2 Top View, 56F8156 144-Pin LQFP Package Table 11-2 56F8156 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Name 1 V 37 V 73 NC 109 ANB5 DD_IO SS 2 V 2 38 V 74 NC 110 ANB6 PP DD_IO 56F8356 Technical Data, Rev. 13 170 Freescale Semiconductor Preliminary

56F8156 Package and Pin-Out Information Table 11-2 56F8156 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Name 3 CLKO 39 PWMB3 75 D3 111 ANB7 4 TXD0 40 PWMB4 76 D4 112 EXTBOOT 5 RXD0 41 PWMB5 77 D5 113 GPIOC8 6 SCLK1 42 TXD1 78 D6 114 GPIOC9 7 MOSI1 43 RXD1 79 OCR_DIS 115 GPIOC10 8 MISO1 44 WR 80 V 116 GPIOE10 DDA_OSC_PLL 9 SS1 45 RD 81 XTAL 117 GPIOE11 10 A1 46 PS 82 EXTAL 118 TC0 11 A2 47 DS 83 V 3 119 V CAP DD_IO 12 A3 48 GPIOD0 84 V 120 TRST DD_IO 13 A4 49 GPIOD1 85 RSTO 121 TCK 14 A5 50 ISB0 86 RESET 122 TMS 15 V 4 51 V 1 87 CLKMODE 123 TDI CAP CAP 16 V 52 ISB1 88 ANA0 124 TDO DD_IO 17 A6 53 ISB2 89 ANA1 125 V 1 PP 18 A7 54 IRQA 90 ANA2 126 NC 19 A8 55 IRQB 91 ANA3 127 NC 20 A9 56 FAULTB0 92 ANA4 128 V 2 CAP 21 A10 57 FAULTB1 93 ANA5 129 SS0 22 A11 58 FAULTB2 94 ANA6 130 SCLK0 23 A12 59 D0 95 ANA7 131 MISO0 24 A13 60 D1 96 NC 132 MOSI0 25 A14 61 FAULTB3 97 V 133 D11 REFLO 26 A15 62 NC 98 V 134 D12 REFN 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 171 Preliminary

Table 11-2 56F8156 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Name 27 V 63 V 99 V 135 D13 SS SS REFMID 28 D7 64 NC 100 V 136 D14 REFP 29 D8 65 NC 101 V 137 D15 REFH 30 D9 66 V 102 V 138 A0 DD_IO DDA_ADC 31 V 67 NC 103 V 139 PHASEA0 DD_IO SSA_ADC 32 D10 68 NC 104 ANB0 140 PHASEB0 33 GPIOB0 69 V 105 ANB1 141 INDEX0 SS 34 PWMB0 70 NC 106 ANB2 142 HOME0 35 PWMB1 71 NC 107 ANB3 143 EMI_MODE 36 PWMB2 72 D2 108 ANB4 144 V SS 56F8356 Technical Data, Rev. 13 172 Freescale Semiconductor Preliminary

56F8156 Package and Pin-Out Information 4X 0.20 H B-C D 4X 36 TIPS 0.20 A B-C D PIN 1 144 109 INDEX 1 108 A 4X e/2 A E1 B C C L 4 5 X 3 E 7 X=B, C or D 140X e E1/2 VIEW A E/2 VIEW A 36 73 37 72 D NOTES: D1/2 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER D/2 ASME Y14.5M, 1994. D1 4 5 3. DATUMS B, C AND D TO BE DETERMINED AT DATUM H. D 7 4. THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE SIZE BY A MAXIMUM OF 0.1 mm. TOP VIEW 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD VIEW B PROTRUSIONS. THE MAXIMUM ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE H A 8X θ2 0.1 A 144X MMAISXMIMATUCMH B.ODY SIZE DIMENSIONS INCLUDING MOLD 6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. PROTRUSIONS SHALL NOT CAUSE SEATING THE LEAD WIDTH TO EXCEED 0.35. MINIMUM SPACE PLANE BETWEEN PROTRUSION AND AN ADJACENT LEAD SHALL BE 0.07 mm. SIDE VIEW 7. DIMENSIONS D AND E TO BE DETERMINED AT THE A SEATING PLANE, DATUM A. MILLIMETERS PLATING DIM MIN MAX A --- 1.60 c b1 c1 A1 0.05 0.15 A2 A2 1.35 1.45 b 0.17 0.27 0.05 b1 0.17 0.23 R2 c 0.09 0.20 θ1 c1 0.09 0.16 D 22.00 BSC R1 D1 20.00 BSC 6 BASE e 0.50 BSC b METAL 0.25 E 22.00 BSC E1 20.00 BSC 0.08 M A B-C D GAGE PLANE L 0.45 0.75 L1 1.00 REF SECTION A-A L2 0.50 REF (ROTATED 90 ° ) R1 0.13 0.20 144 PLACES L2 R2 0.13 --- A1 S 0.25 REF L θ θ 0 ° 7 ° S θ 1 0 ° --- θ 2 12 ° REF L1 VIEW B Figure 11-3 144-pin LQFP Mechanical Information 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 173 Preliminary

Please see www.freescale.com for the most current case outline. Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature, T , can be obtained from the equation: J T = T + (R P ) J A θJΑ x D where: T = Ambient temperature for the package (oC) A R = Junction-to-ambient thermal resistance (oC/W) θJΑ P = Power dissipation in the package (W) D The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single-layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: R R R θJΑ = θJC + θCΑ where: R = Package junction-to-ambient thermal resistance °C/W θJA R = Package junction-to-case thermal resistance °C/W θJC R = Package case-to-ambient thermal resistance °C/W θCA R is device-related and cannot be influenced by the user. The user controls the thermal environment to θJC change the case-to-ambient thermal resistance, R . For instance, the user can change the size of the heat θCA sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (Ψ ) can be used to determine the junction temperature with a JT measurement of the temperature at the top center of the package case using the following equation: T = T + (Ψ x P ) J T JT D 56F8356 Technical Data, Rev. 13 174 Freescale Semiconductor Preliminary

Electrical Design Considerations where: T = Thermocouple temperature on top of package (oC) T Ψ = Thermal characterization parameter (oC)/W JT P = Power dissipation in package (W) D The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. 12.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct device operation: • Provide a low-impedance path from the board power supply to each V pin on the device, and from the DD board ground to each V (GND) pin SS • The minimum bypass requirement is to place six 0.01–0.1μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the V /V pairs, including V /V Ceramic and tantalum capacitors tend to provide better DD SS DDA SSA. performance tolerances. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 175 Preliminary

• Ensure that capacitor leads and associated printed circuit traces that connect to the chip V and V (GND) DD SS pins are less than 0.5 inch per capacitor lead • Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V and V DD SS • Bypass the V and V layers of the PCB with approximately 100μF, preferably with a high-grade DD SS capacitor such as a tantalum capacitor • Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V and V circuits. DD SS • Take special care to minimize noise levels on the V , V and V pins REF DDA SSA • Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. Designs that do not require debugging functionality, such as consumer products, should tie these pins together. • Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an interface to this port to allow in-circuit Flash programming 12.3 Power Distribution and I/O Ring Implementation Figure 12-1 illustrates the general power control incorporated in the 56F8356/56F8156. This chip contains two internal power regulators. One of them is powered from the V pin and cannot DDA_OSC_PLL be turned off. This regulator controls power to the internal clock generation circuitry. The other regulator is powered from the V pins and provides power to all of the internal digital logic of the core, all DD_IO peripherals and the internal memories. This regulator can be turned off, if an external V voltage DD_CORE is externally applied to the V pins. CAP In summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is enabled. If the regulator is not enabled, a dual supply 3.3V/2.5V configuration can also be used. Notes: • Flash, RAM and internal logic are powered from the core regulator output • V 1 and V 2 are not connected in the customer system PP PP • All circuitry, analog and digital, shares a common V bus SS 56F8356 Technical Data, Rev. 13 176 Freescale Semiconductor Preliminary

Power Distribution and I/O Ring Implementation V DDA_OSC_PLL V V DD DDA_ADC V V REFH CAP REG REG VREFP I/O ADC VREFMID CORE V REFN OSC V REFLO V V SS SSA_ADC Figure 12-1 Power Management Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 13-1 Ordering Information Ambient Supply Pin Frequency Part Package Type Temperature Order Number Voltage Count (MHz) Range MC56F8356 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 144 60 -40° to + 105° C MC56F8356VFV60 MC56F8356 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 144 60 -40° to + 125° C MC56F8356MFV60 MC56F8156 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 144 40 -40° to + 105° C MC56F8156VFV MC56F8356 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 144 60 -40° to + 105° C MC56F8356VFVE* MC56F8356 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 144 60 -40° to + 125° C MC56F8356MFVE* MC56F8156 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 144 40 -40° to + 105° C MC56F8156VFVE* *This package is RoHS compliant. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor 177 Preliminary

How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) RoHS-compliant and/or Pb-free versions of Freescale products have the support@freescale.com functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see Japan: http://www.freescale.com or contact your Freescale sales representative. Freescale Semiconductor Japan Ltd. Headquarters For information on Freescale’s Environmental Products program, go to ARCO Tower 15F http://www.freescale.com/epp. 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan Information in this document is provided solely to enable system and 0120 191014 or +81 3 5437 9125 software implementers to use Freescale Semiconductor products. There are support.japan@freescale.com no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, 2 Dai King Street representation or guarantee regarding the suitability of its products for any Tai Po Industrial Estate particular purpose, nor does Freescale Semiconductor assume any liability Tai Po, N.T., Hong Kong arising out of the application or use of any product or circuit, and specifically +800 2666 8080 disclaims any and all liability, including without limitation consequential or support.asia@freescale.com incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different For Literature Requests Only: applications and actual performance may vary over time. All operating Freescale Semiconductor Literature Distribution Center parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does P.O. Box 5405 not convey any license under its patent rights nor the rights of others. Denver, Colorado 80217 Freescale Semiconductor products are not designed, intended, or authorized 1-800-441-2447 or 303-675-2140 for use as components in systems intended for surgical implant into the body, Fax: 303-675-2150 or other applications intended to support or sustain life, or for any other LDCForFreescaleSemiconductor@hibbertgroup.com application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005, 2006. All rights reserved. MC56F8356 Rev. 13 01/2007

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