Freescale Semiconductor Document Number: MC56F8006 Technical Data Rev. 4, 06/2011 MC56F8006/MC56F8002 48-pin LQFP 32-pin LQFP Case: 932-03 Case: 873A-03 7 x 7 mm2 7 x 7 mm2 MC56F8006/MC56F8002 28-pin SOIC Case: 751F-05 Digital Signal Controller 7.5 x 18 mm2 32-pin PSDIP Case: 1376-02 9 x 28.5 mm2 This document applies to parts marked with 2M53M. RAM. Program flash memory can be independently bulk The 56F8006/56F8002 is a member of the 56800E core-based erased or erased in small pages of 512 bytes (256 words). family of digital signal controllers (DSCs). It combines, on a On-chip features include: single chip, the processing power of a DSP and the • Up to 32 MIPS at 32 MHz core frequency functionality of a microcontroller with a flexible set of • DSP and MCU functionality in a unified, C-efficient peripherals to create a cost-effective solution. Because of its architecture low cost, configuration flexibility, and compact program • On-chip memory code, the 56F8006/56F8002 is well-suited for many – 56F8006: 16 KB (8K x 16) flash memory applications. It includes many peripherals that are especially – 56F8002: 12 KB (6K x 16) flash memory useful for cost-sensitive applications, including: – 2 KB (1K x 16) unified data/program RAM • Industrial control • One 6-channel PWM module • Home appliances • Two 28-channel, 12-bit analog-to-digital converters • Smart sensors (ADCs) • Fire and security systems • Two programmable gain amplifiers (PGA) with gain up to • Switched-mode power supply and power management 32x • Power metering • Three analog comparators • Motor control (ACIM, BLDC, PMSM, SR, and stepper) • One programmable interval timer (PIT) • Handheld power tools • One high-speed serial communication interface (SCI) with • Arc detection LIN slave functionality • Medical device/equipment • One serial peripheral interface (SPI) • Instrumentation • One 16-bit dual timer (2 x 16 bit timers) • Lighting ballast • One programmable delay block (PDB) The 56800E core is based on a dual Harvard-style architecture • One SMBus compatible inter-integrated circuit (I2C) port consisting of three execution units operating in parallel, allowing • One real time counter (RTC) as many as six operations per instruction cycle. The MCU-style • Computer operating properly (COP)/watchdog programming model and optimized instruction set allow • Two on-chip relaxation oscillators — 1 kHz and 8 MHz straightforward generation of efficient, compact DSP and control (400 kHz at standby mode) code. The instruction set is also highly efficient for C compilers • Crystal oscillator to enable rapid development of optimized control applications. • Integrated power-on reset (POR) and low-voltage interrupt The 56F8006/56F8002 supports program execution from internal (LVI) module memories. Two data operands can be accessed from the on-chip • JTAG/enhanced on-chip emulation (OnCE™) for data RAM per instruction cycle. The 56F8006/56F8002 also unobtrusive, real-time debugging offers up to 40 general-purpose input/output (GPIO) lines, • Up to 40 GPIO lines depending on peripheral configuration. • 28-pin SOIC, 32-pin LQFP, 32-pin PSDIP, and 48-pin LQFP packages The 56F8006/56F8002 digital signal controller includes up to 16KB of program flash and 2KB of unified data/program Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ©Freescale Semiconductor, Inc., 2009–2011. All rights reserved.

Table of Contents 1 MC56F8006/MC56F8002 Family Configuration. . . . . . . . . . . .3 8.1 General Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 41 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 42 3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8.3 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 43 3.1 56F8006/56F8002 Features . . . . . . . . . . . . . . . . . . . . . .4 8.4 Recommended Operating Conditions. . . . . . . . . . . . . 45 3.2 Award-Winning Development Environment. . . . . . . . . . .8 8.5 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . 46 3.3 Architecture Block Diagram. . . . . . . . . . . . . . . . . . . . . . .9 8.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . 51 3.4 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . .11 8.7 Flash Memory Characteristics. . . . . . . . . . . . . . . . . . . 53 4 Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . .11 8.8 External Clock Operation Timing. . . . . . . . . . . . . . . . . 53 4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 8.9 Phase Locked Loop Timing. . . . . . . . . . . . . . . . . . . . . 54 4.2 Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 8.10 Relaxation Oscillator Timing . . . . . . . . . . . . . . . . . . . . 54 4.3 56F8006/56F8002 Signal Pins . . . . . . . . . . . . . . . . . . .17 8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing. 56 5 Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 8.12 External Oscillator (XOSC) Characteristics. . . . . . . . . 56 5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 8.13 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . 57 5.2 Program Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 8.14 COP Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 8.15 PGA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.4 Interrupt Vector Table and Reset Vector. . . . . . . . . . . .31 8.16 ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.5 Peripheral Memory-Mapped Registers. . . . . . . . . . . . .32 8.17 HSCMP Specifications . . . . . . . . . . . . . . . . . . . . . . . . 68 5.6 EOnCE Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .33 8.18 Optimize Power Consumption. . . . . . . . . . . . . . . . . . . 68 6 General System Control Information . . . . . . . . . . . . . . . . . . .34 9 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 9.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . 70 6.2 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 9.2 Electrical Design Considerations. . . . . . . . . . . . . . . . . 71 6.3 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 9.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4 On-chip Clock Synthesis. . . . . . . . . . . . . . . . . . . . . . . .34 10 Package Mechanical Outline Drawings. . . . . . . . . . . . . . . . . 73 6.5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 10.1 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.6 System Integration Module (SIM) . . . . . . . . . . . . . . . . .37 10.2 32-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.7 PWM, PDB, PGA, and ADC Connections. . . . . . . . . . .38 10.3 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.8 Joint Test Action Group (JTAG)/Enhanced On-Chip 10.4 32-Pin PSDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Emulator (EOnCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 AppendixA 7.1 Operation with Security Enabled. . . . . . . . . . . . . . . . . .40 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.2 Flash Access Lock and Unlock Mechanisms . . . . . . . .40 AppendixB 7.3 Product Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Peripheral Register Memory Map and Reset Value . . . . . . . 86 8 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 2 Freescale Semiconductor

MC56F8006/MC56F8002 Family Configuration 1 MC56F8006/MC56F8002 Family Configuration MC56F8006/MC56F8002 device comparison in Table1. Table1. MC56F8006 Series Device Comparison MC56F8006 MC56F8002 Feature 28-pin 32-pin 48-pin 28-pin Flash memory size (Kbytes) 16 12 RAM size (Kbytes) 2 Analog comparators (ACMP) 3 Analog-to-digital converters (ADC) 2 Unshielded ADC inputs 6 7 7 6 Shielded ADC inputs 9 11 17 9 Total number of ADC input pins1 15 18 24 15 Programmable gain amplifiers (PGA) 2 Pulse-width modulator (PWM) outputs 6 PWM fault inputs 3 4 4 3 Inter-integrated circuit (IIC) 1 Serial peripheral interface (SPI) 1 High speed serial communications interface (SCI) 1 Programmable interrupt timer (PIT) 1 Programmable delay block (PDB) 1 16-bit multi-purpose timers (TMR) 2 Real-time counter (RTC) 1 Computer operating properly (COP) timer Yes Phase-locked loop (PLL) Yes 1 kHz on-chip oscillator Yes 8 MHz (400 kHz at standby mode) on-chip ROSC Yes Crystal oscillator Yes Power management controller (PMC) Yes IEEE 1149.1 Joint Test Action Group (JTAG) interface Yes Enhanced on-chip emulator (EOnCE) IEEE 1149.1 Joint Yes Test Action Group (JTAG) interface 1 Some ADC inputs share the same pin. See Table4. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 3

Block Diagram 2 Block Diagram Figure1 shows a top-level block diagram of the MC56F8006/MC56F8002 digital signal controller. Package options for this family are described later in this document. Italics indicate a 56F8002 device parameter. RESET VDD VSS VDDA VSSA 4 3 3 PWM JTAG/EOnCE Digital Reg Analog Reg 6 PWM Outputs Port or GPIOD Low-Voltage PMC Supervisor 3 Fault Inputs 16-Bit 56800E Core Program Controller Address Data ALU 16 x 16 + 36  36-Bit MAC Bit and Hardware Generation Unit Three 16-bit Input Registers Manipulation Looping Unit Four 36-bit Accumulators Unit programmable delay block PAB PDB CDBR 24 Total ADCA CDBW PGA/ADC R/W Control ADCB Memory XDB2 XAB1 Flash Memory XAB2 2 CMP0 CMP 16Kbytes flash PAB System Bus or 12Kbytes flash Control 2 CMP1GPIOD PCDDBBR Unified Data / CDBW Program RAM PIT 2 CMP2 2KB GPIO are IPBus Bridge Note: All pins 40 muxed with are muxed with all other func other peripheral pins. pins. Power 4 Dual GP Timer Management RTC Controller SPI SCI I2C Interrupt System Clock ROSC WaCtOchPd/og Controller InMteogdrautlieon Generator* OSC 4 2 2 2 Crystal Oscillator Figure1. MC56F8006/MC56F8002 Block Diagram 3 Overview 3.1 56F8006/56F8002 Features 3.1.1 Core • Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture • As many as 32 million instructions per second (MIPS) at 32 MHz core frequency • 155 basic instructions in conjunction with up to 20 address modes • Single-cycle 16  16-bit parallel multiplier-accumulator (MAC) • Four 36-bit accumulators, including extension bits • 32-bit arithmetic and logic multi-bit shifter MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 4 Freescale Semiconductor

Overview • Parallel instruction set with unique DSP addressing modes • Hardware DO and REP loops • Three internal address buses • Four internal data buses • Instruction set supports DSP and controller functions • Controller-style addressing modes and instructions for compact code • Efficient C compiler and local variable support • Software subroutine and interrupt stack with depth limited only by memory • JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging 3.1.2 Operation Range • 1.8V to 3.6V operation (power supplies and I/O) • From power-on-reset: approximately 1.9 V to 3.6 V • Ambient temperature operating range: — –40 °C to 125 °C 3.1.3 Memory • Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory • Flash security and protection that prevent unauthorized users from gaining access to the internal flash • On-chip memory — 16KB of program flash for 56F8006 and 12KB of program flash for 56F8002 — 2KB of unified data/program RAM • EEPROM emulation capability using flash 3.1.4 Interrupt Controller • Five interrupt priority levels — Three user programmable priority levels for each interrupt source: Level 0, 1, 2 — Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3 instruction. Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, EOnCE trace buffer — Lowest-priority software interrupt: level LP • Allow nested interrupt that higher priority level interrupt request can interrupt lower priority interrupt subroutine • The masking of interrupt priority level is managed by the 56800E core • One programmable fast interrupt that can be assigned to any interrupt source • Notification to system integration module (SIM) to restart clock out of wait and stop states • Ability to relocate interrupt vector table 3.1.5 Peripheral Highlights • One multi-function, six-output pulse width modulator (PWM) module — Up to 96 MHz PWM operating clock — 15 bits of resolution — Center-aligned and edge-aligned PWM signal mode — Phase shifting PWM pulse generation MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 5

Overview — Four programmable fault inputs with programmable digital filter — Double-buffered PWM registers — Separate deadtime insertions for rising and falling edges — Separate top and bottom pulse-width correction by means of software — Asymmetric PWM output within both Center Aligned and Edge Aligned operation — Separate top and bottom polarity control — Each complementary PWM signal pair allows selection of a PWM supply source from: – PWM generator – Internal timers – Analog comparator outputs • Two independent 12-bit analog-to-digital converters (ADCs) — 2 x 14 channel external inputs plus seven internal inputs — Support simultaneous and software triggering conversions — ADC conversions can be synchronized by PWM and PDB modules — Sampling rate up to 400 KSPS for 10- or 12-bit conversion result; 470 KSPS for 8-bit conversion result — Two 16-word result registers • Two programmable gain amplifier (PGAs) — Each PGA is designed to amplify and convert differential signals to a single-ended value fed to one of the ADC inputs — 1X, 2X, 4X, 8X, 16X, or 32X gain — Software and hardware triggers are available — Integrated sample/hold circuit — Includes additional calibration features: – Offset calibration eliminates any errors in the internal reference used to generate the VDDA/2 output center point – Gain calibration can be used to verify the gain of the overall datapath – Both features require software correction of the ADC result • Three analog comparators (CMPs) — Selectable input source includes external pins, internal DACs — Programmable output polarity — Output can drive timer input, PWM fault input, PWM source, external pin output, and trigger ADCs — Output falling and rising edge detection able to generate interrupts • One dual channel 16-bit multi-purpose timer module (TMR) — Two independent 16-bit counter/timers with cascading capability — Up to 96 MHz operating clock — Each timer has capture and compare and quadrature decoder capability — Up to 12 operating modes — Four external inputs and two external outputs • One serial communication interface (SCI) with LIN slave functionality — Up to 96 MHz operating clock — Full-duplex or single-wire operation — Programmable 8- or 9- bit data format — Two receiver wakeup methods: – Idle line – Address mark MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 6 Freescale Semiconductor

Overview — 1/16 bit-time noise detection • One serial peripheral interface (SPI) — Full-duplex operation — Master and slave modes — Programmable length transactions (2 to 16 bits) — Programmable transmit and receive shift order (MSB as first or last bit transmitted) — Maximum slave module frequency = module clock frequency/2 • One inter-integrated Circuit (I2C) port — Operates up to 400kbps — Supports master and slave operation — Supports 10-bit address mode and broadcasting mode — Supports SMBus, Version 2 • One 16-bit programmable interval timer (PIT) — 16 bit counter with programmable counter modulo — Interrupt capability • One 16-bit programmable delay block (PDB) — 16 bit counter with programmable counter modulo and delay time — Counter is initiated by positive transition of internal or external trigger pulse — Supports two independently controlled delay pulses used to synchronize PGA and ADC conversions with input trigger event — Two PDB outputs can be ORed together to schedule two conversions from one input trigger event — PDB outputs can be can be used to schedule precise edge placement for a pulsed output that generates the control signal for the CMP windowing comparison — Supports continuous or single shot mode — Bypass mode supported • Computer operating properly (COP)/watchdog timer capable of selecting different clock sources — Programmable prescaler and timeout period — Programmable wait, stop, and partial powerdown mode operation — Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected — Choice of clock sources from four sources in support of EN60730 and IEC61508: – On-chip relaxation oscillator – External crystal oscillator/external clock source – System clock (IPBus up to 32MHz) – On-chip low power 1 kHz oscillator • Real-timer counter (RTC) — 8-bit up-counter — Three software selectable clock sources – External crystal oscillator/external clock source – On-chip low-power 1kHz oscillator – System bus (IPBus up to 32MHz) — Can signal the device to exit power down mode • Phase lock loop (PLL) provides a high-speed clock to the core and peripherals — Provides 3x system clock to PWM and dual timer and SCI — Loss of lock interrupt — Loss of reference clock interrupt MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 7

Overview • Clock sources — On-chip relaxation oscillator with two user selectable frequencies: 400 kHz for low speed mode, 8 MHz for normal operation — On-chip low-power 1 kHz oscillator can be selected as clock source to the RTC and/or COP — External clock: crystal oscillator, ceramic resonator, and external clock source • Power management controller (PMC) — On-chip regulator for digital and analog circuitry to lower cost and reduce noise — Integrated power-on reset (POR) — Low-voltage interrupt with a user selectable trip voltage of 1.81 V or 2.31 V — User selectable brown-out reset — Run, wait, and stop modes — Low-power run, wait, and stop modes — Partial power down mode • Up to 40 general-purpose I/O (GPIO) pins — Individual control for each pin to be in peripheral or GPIO mode — Individual input/output direction control for each pin in GPIO mode — Hysteresis and configurable pullup device on all input pins — Configurable slew rate and drive strength and optional input low pass filters on all output pins — 20mA sink/source current • JTAG/EOnCE debug programming interface for real-time debugging — IEEE 1149.1 Joint Test Action Group (JTAG) interface — EOnCE interface for real-time debugging 3.1.6 Power Saving Features • Three low power modes — Low-speed run, wait, and stop modes: 200 kHz IP bus clock provided by ROSC — Low-power run, wait, and stop modes: clock provided by external 32–38.4 kHz crystal — Partial power down mode • Low power external oscillator can be used in any low-power mode to provide accurate clock to active peripherals • Low power real time counter for use in run, wait, and stop modes with internal and external clock sources • 32 s typical wakeup time from partial power down modes • Each peripheral can be individually disabled to save power 3.2 Award-Winning Development Environment Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit, and development system cards support concurrent engineering. Together, PE, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. A full set of programmable peripherals — PWM, PGAs, ADCs, SCI, SPI, I2C, PIT, timers, and analog comparators — supports various applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as general-purpose input/outputs (GPIOs). MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 8 Freescale Semiconductor

Overview 3.3 Architecture Block Diagram The 56F8006/56F8002’s architecture is shown in Figure2 and Figure3. Figure2 illustrates how the 56800E system buses communicate with internal memories and the IPBus interface and the internal connections among each unit of the 56800E core. Figure3 shows the peripherals and control blocks connected to the IPBus bridge. Please see the system integration module (SIM) section in the MC56F8006 Reference Manual for information about which signals are multiplexed with those of other peripherals. DSP56800E Core Program Control Unit ALU1 ALU2 Address PC Generation LA Instruction Unit LA2 R0 Decoder (AGU) HWS0 R1 HWS1 Interrupt R2 FIRA M01 Program Unit R3 OMR N3 R4 Memory SR R5 Looping LC N Unit LC2 SP FISR XAB1 XAB2 PAB Data/ Program PDB RAM CDBW CDBR XDB2 A2 A1 A0 Bit- B2 B1 B0 IPBus Manipulation C2 C1 C0 Interface Unit D2 D1 D0 Y1 Y Data Enhanced Y0 OnCE™ Arithmetic X0 Logic Unit (ALU) JTAG TAP MAC and ALU Multi-Bit Shifter Figure2. 56800E Core Block Diagram MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 9

Overview IPBus Bridge RTC GPIOA7 GPIOA6 COP GPIOA5 A SCylosctekm Second Clcok source Crystal rt GGPPIIOOAA43 o OCCS COSC P GPIOA2 ROSC GPIOA1 GPIOA0 RESTE SIM GPIOB7 GPIOB6 GPIOB5 PMC B GPIOB4 1KHz rt GPIOB3 o INTC P GPIOB2 GPIOB1 GPIOB0 SPI GPIOC7 SCI GPIOC6 GPIOC5 I2C C GPIOC4 rt GPIOC3 Dual Timer (TMR) Po GPIOC2 X GPIOC1 U GPIOC0 PWM M PWM Synch O PWM Input Mux PI G GPIOD3 D GPIOD2 CMP0 rt GPIOD1 o GPIOD0 P CMP1 CMP2 GPIOE7 GPIOE6 GPIOE5 PDB E GPIOE4 Trigger A ort GPIOE3 P GPIOE2 GPIOE1 ADCA PreTrigger A GPIOE0 ANA15 PGA0 GPIOF3 Trigger B F GPIOF2 rt GPIOF1 ADCB PreTrigger B Po GPIOF0 ANB15 PGA1 Figure3. Peripheral Subsystem MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 10 Freescale Semiconductor

Signal/Connection Descriptions 3.4 Product Documentation The documents listed in Table2 are required for a complete description and proper design with the 56F8006/56F8002. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com. Table2. 56F8006/56F8002 Device Documentation Topic Description Order Number DSP56800E Reference Detailed description of the 56800E family architecture, DSP56800ERM Manual 16-bit digital signal controller core processor, and the instruction set 56F800x Peripheral Detailed description of peripherals of the 56F8006 and MC56F8006RM Reference Manual 56F8002 devices 56F80x Serial Bootloader Detailed description of the Serial Bootloader in the TBD User Guide 56F800x family of devices 56F8006/56F8002 Electrical and timing specifications, pin descriptions, and MC56F8006 Technical Data Sheet package descriptions (this document) 56F8006/56F8002 Errata Details any chip issues that might be present MC56F8006E 4 Signal/Connection Descriptions 4.1 Introduction The input and output signals of the 56F8006/56F8002 are organized into functional groups, as detailed in Table3. Table4 summarizes all device pins. In Table4, each table row describes the signal or signals present on a pin, sorted by pin number. Table3. Functional Group Pin Allocations Number of Pins Number of Pins Number of Pins Number of Pins Functional Group in 28 SOIC in 32 LQFP in 32 PSDIP in 48 LQFP Power Inputs (V , V ) 2 2 2 4 DD DDA Ground (V , V ) 3 3 3 4 SS SSA Reset1 1 1 1 1 Pulse Width Modulator (PWM) Ports1 10 12 12 12 Serial Peripheral Interface (SPI) Ports1 5 7 7 7 Serial Communications Interface 0 (SCI) Ports1 4 5 5 5 Inter-Integrated Circuit Interface (I2C) Ports1 6 7 7 7 Analog-to-Digital Converter (ADC) Inputs1 16 18 18 24 High Speed Analog Comparator Inputs1 13 15 15 25 Programmable Gain Amplifiers (PGA)1 4 4 4 4 Dual Timer Module (TMR) Ports1 8 10 10 10 Programmable Delay Block (PDB)1 — — — 1 Clock1 5 5 5 5 JTAG/Enhanced On-Chip Emulation (EOnCE1) 4 4 4 4 1 Pins may be shared with other peripherals. See Table4. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 11

Signal/Connection Descriptions In Table4, peripheral pins in bold identify reset state. Table4. 56F8006/56F8002 Pins Pin Number Peripherals Pin Name Power 28 32 32 48 GPIO I2C SCI SPI ADC PGA COMP Dual PWM and JTAG Misc. SOICLQFPPSDIPLQFP Timer Ground 26 1 29 1 GPIOB6/RXD/SDA/ANA13 B6 SDA RXD ANA131 CMP0_P2 CLKIN and CMP0_P2/CLKIN 27 2 30 2 GPIOB1/SS/SDA/ANA12 B1 SDA SS ANA121 CMP2_P3 andCMP2_P3 3 31 3 GPIOB7/TXD/SCL/ANA11 B7 SCL TXD ANA111 CMP2_M3 and CMP2_M3 4 32 4 GPIOB5/T1/FAULT3/SCLK B5 SCLK T1 FAULT3 5 GPIOE0 E0 6 GPIOE1/ANB9 and E1 ANB91 CMP0_P1 CMP0_P1 28 5 1 7 ANB8 and PGA1+ and C4 ANB81 PGA1+ CMP0_M2 CMP0_M2/GPIOC4 8 GPIOE2/ANB7 and E2 ANB71 CMP0_M1 CMP0_M1 1 6 2 9 ANB6 and PGA1– and C5 ANB61 PGA1– CMP0_P4 CMP0_P4/GPIOC5 10 GPIOC7/ANB5 and C7 ANB51 CMP1_M2 CMP1_M2 2 7 3 11 ANB4 and C6 ANB41 CMP1_P1 PWM2 CMP1_P1/GPIOC6/PWM2 3 8 4 12 VDDA VDDA 4 9 5 13 VSSA VSSA 14 GPIOE3/ANA10 and E3 ANA101 CMP2_M1 CMP2_M1 5 10 6 15 ANA9 and PGA0– and C2 ANA91 PGA0– CMP2_P4 CMP2_P4/GPIOC2 16 GPIOE5/ANA8 and E5 ANA81 CMP2_P1 CMP2_P1 6 11 7 17 ANA7 and PGA0+ and C1 ANA71 PGA0+ CMP2_M2 CMP2_M2/GPIOC1 18 GPIOE4/ANA6 and E4 ANA61 CMP2_P2 CMP2_P2 7 12 8 19 ANA5 and C0 ANA51 CMP1_M1 FAULT0 CMP1_M1/GPIOC0/FAULT0 8 13 9 20 VSS VSS 21 VDD VDD 9 14 10 22 TCK/GPIOD2/ANA4 and D2 ANA41 CMP1_P2, TCK CMP1_P2/CMP2_OUT CMP2_OUT 10 15 11 23 RESET/GPIOA7 A7 RESET 11 16 12 24 GPIOB3/MOSI/TIN3/ANA3 B3 MOSI ANA31 CMP1_OUT TIN3 PWM5 and and ANB3/PWM5/CMP1_OUT ANB31 17 13 25 GPIOB2/MISO/TIN2/ANA2 B2 MISO ANA2 CMP0_OUT TIN2 and ANB2/CMP0_OUT and ANB2 12 18 14 26 GPIOA6/FAULT0/ANA1 and A6 SCL TXD ANA1 FAULT0 CLKO_1 ANB1/SCL/TXD/CLKO_1 and ANB1 13 19 15 27 GPIOB4/T0/CLKO_0/MISO/ B4 SDA RXD MISO ANA0 T0 CLKO_0 SDA/RXD/ANA0 and ANB0 and ANB0 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 12 Freescale Semiconductor

Signal/Connection Descriptions Table4. 56F8006/56F8002 Pins (continued) Pin Number Peripherals Pin Name Power 28 32 32 48 GPIO I2C SCI SPI ADC PGA COMP Dual PWM and JTAG Misc. SOICLQFPPSDIPLQFP Timer Ground 28 GPIOE6 E6 14 20 16 29 GPIOA5/PWM5/FAULT2 or A5 TIN3 PWM5, EXT_SYNC/TIN3 FAULT2 or EXT_ SYNC 30 VSS VSS 31 VDD VDD 15 21 17 32 GPIOB0/SCLK/SCL/ANB13/ B0 SCL SCLK ANB13 T1 PWM3 PWM3/T1 16 22 18 33 GPIOA4/PWM4/SDA/FAULT1 A4 SDA TIN2 PWM4, /TIN2 FAULT1 34 GPIOE7/CMP1_M3 E7 CMP1_M3 23 19 35 GPIOA2/PWM2 A2 PWM2 17 24 20 36 GPIOA3/PWM3/TXD/EXTAL A3 TXD PWM3 EXTAL 18 25 21 37 GPIOF0/XTAL F0 XTAL 19 26 22 38 VDD VDD 20 27 23 39 VSS VSS 40 GPIOF1/CMP1_P3 F1 CMP1_P3 41 GPIOF2/CMP0_M3 F2 CMP0_M3 42 GPIOF3/CMP0_P3 F3 CMP0_P3 21 28 24 43 GPIOA1/PWM1 A1 PWM1 22 29 25 44 GPIOA0/PWM0 A0 PWM0 23 30 26 45 TDI/GPIOD0/ANB12/SS/ D0 SS ANB12 CMP0_OUT TIN2 TDI TIN2/CMP0_OUT 46 GPIOC3/EXT_TRIGGER C3 EXT_ TRGGER 24 31 27 47 TMS/GPIOD3/ANB11/T1/ D3 ANB11 CMP1_OUT T1 TMS CMP1_OUT 25 32 28 48 TDO/GPIOD1/ANB10/T0/ D1 ANB10 CMP2_OUT T0 TDO CMP2_OUT 1 Shielded ADC input. 4.2 Pin Assignment MC56F8006 and MC56F8002 28-pin small outline IC (28SOIC) assignment is shown in Figure4; MC56F8006 32-pin low-profile quad flat pack (32LQFP) is shown in Figure5; MC56F8006 32-pin plastic shrink dual in-line package (PSDIP) is shown in Figure6; MC56F8006 48-pin low-profile quad flat pack (48LQFP) is shown in Figure7. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 13

Signal/Connection Descriptions ANB6 & PGA1– & CMP0_P4/GPIOC5 1 28 ANB8 & PGA1+ & CMP0_M2/GPIOC4 ANB4 & CMP1_P1/GPIOC6/PWM2 2 27 GPIOB1/SS/SDA/ANA12 & CMP2_P3 VDDA 3 26 GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN VSSA 4 25 TDO/GPIOD1/ANB10/T0/CMP2_OUT ANA9 & PGA0– & CMP2_P4/GPIOC2 5 24 TMS/GPIOD3/ANB11/T1/CMP1_OUT ANA7 & PGA0+ & CMP2_M2/GPIOC1 6 23 TDI/GPIOD0/ANB12/SS/TIN2/CMP0_OUT ANA5 and CMP1_M1/GPIOC0/FAULT0 7 22 GPIOA0/PWM0 VSS 8 21 GPIOA1/PWM1 TCK/GPIOD2/ANA4 & CMP1_P2/CMP2_OUT 9 20 VSS RESET/GPIOA7 10 19 VDD GPIOB3/MOSI/TIN3/ANA3 & ANB3/PWM5/CMP1_OUT 11 18 GPIOF0/XTAL GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1 12 17 GPIOA3/PWM3/TXD/EXTAL GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0 13 16 GPIOA4/PWM4/SDA/FAULT1/TIN2 GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3 14 15 GPIOB0/SCLK/SCL/ANB13/PWM3/T1 Figure4. Top View, MC56F8006/MC56F8002 28-Pin SOIC Package MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 14 Freescale Semiconductor

Signal/Connection Descriptions T U O _ 0 P T T M U U C 2_O 1_O N2/ CMP CMP S/TI T0/ T1/ 2/S 0/ 1/ 1 1 1 B B B N N N A OD1/A OD3/A OD0/ PWM0 PWM1 XTAL TDO/GPI TMS/GPI TDI/GPI GPIOA0/ GPIOA1/ VSS VDD GPIOF0/ 2 1 0 9 8 7 6 5 3 3 3 2 2 2 2 2 GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN 1 24 GPIOA3/PWM3/TXD/EXTAL GPIOB1/SS/SDA/ANA12 & CMP2_P3 2 23 GPIOA2/PWM2 ORIENTATION GPIOB7/TXD/SCL/ANA11 & CMP2_M3 3 MARK 22 GPIOA4/PWM4/SDA/FAULT1/TIN2 GPIOB5/T1/FAULT3/SCLK 4 21 GPIOB0/SCLK/SCL/ANB13/PWM3/T1 ANB8 and PGA1+ & CMP0_M2/GPIOC4 5 20 GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3 ANB6 and PGA1– & CMP0_P4/GPIOC5 6 19 GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0 ANB4 & CMP1_P1/GPIOC6/PWM2 7 18 GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1 VDDA 8 0 1 2 3 4 5 617 GPIOB2/MISO/TIN2/ANA2 & ANB2/CMP0_OUT 9 1 1 1 1 1 1 1 VSSA ANA9 and PGA0– & CMP2_P4/GPIOC2 ANA7 and PGA0+ & CMP2_M2/GPIOC1 ANA5 and CMP1_M1/GPIOC0/FAULT0 VSS K/GPIOD2/ANA4 & CMP1_P2/CMP2_OUT RESET/GPIOA7 SI/TIN3/ANA3 & ANB3/PWM5/CMP1_OUT C O T M 3/ B O PI G Figure5. Top View, MC56F8006 32-Pin LQFP Package MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 15

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(cid:39)(cid:48)(cid:41)(cid:47)(cid:34)(cid:16)(cid:15)(cid:51)(cid:35)(cid:44)(cid:43)(cid:15)(cid:51)(cid:35)(cid:44)(cid:15)(cid:33)(cid:46)(cid:34)(cid:17)(cid:19)(cid:15)(cid:48)(cid:55)(cid:45)(cid:19)(cid:15)(cid:52)(cid:17) Figure6. Top View, MC56F8006 32-Pin PSDIP Package MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 16 Freescale Semiconductor

Signal/Connection Descriptions T U O T T _ U U 0 O O P _ _ M 2 1 C MP MP N2/ NB10/T0/C NB11/T1/C RIGGER B12/SS/TI P3 M3 P3 TDO/GPIOD1/A TMS/GPIOD3/A GPIOC3/EXT_T TDI/GPIOD0/AN GPIOA0/PWM0 GPIOA1/PWM1 GPIOF3/CMP0_ GPIOF2/CMP0_ GPIOF1/CMP1_ VSSVDDGPIOF0/XTAL 8 7 6 5 4 3 2 1 0 9 8 7 4 4 4 4 4 4 4 4 4 3 3 3 GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN 1 36 GPIOA3/PWM3/TXD/EXTAL GPIOB1/SS/SDA/ANA12 & CMP2_P3 2 35 GPIOA2/PWM2 GPIOB7/TXD/SCL/ANA11 & CMP2_M3 3 34 GPIOE7/CMP1_M3 GPIOB5/T1/FAULT3/SCLK 4 Orientation Mark 33 GPIOA4/PWM4/SDA/FAULT1/TIN2 GPIOE0 5 32 GPIOB0/SCLK/SCL/ANB13/PWM3/T1 GPIOE1/ANB9 & CMP0_P1 6 31 VDD ANB8 and PGA1+ & CMP0_M2/GPIOC4 7 30 Vss GPIOE2/ANB7 & CMP0_M1 8 29 GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3 ANB6 and PGA1– & CMP0_P4/GPIOC5 9 28 GPIOE6 GPIOC7/ANB5 & CMP1_M2 10 27 GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0 ANB4 & CMP1_P1/GPIOC6/PWM2 11 26 GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1 VDDA 12 25 GPIOB2/MISO/TIN2/ANA2 & ANB2/CMP0_OUT 3 4 5 6 7 8 9 0 1 2 3 4 1 1 1 1 1 1 1 2 2 2 2 2 VSSA GPIOE3/ANA10 & CMP2_M1 ANA9 and PGA0– & CMP2_P4/GPIOC2 GPIOE5/ANA8 & CMP2_P1 ANA7 & PGA0+ & CMP2_M2/GPIOC1 GPIOE4/ANA6 & CMP2_P2 ANA5 & CMP1_M1/GPIOC0/FAULT0 VSSVDD GPIOD2/ANA4 & CMP1_P2/CMP2_OUT RESET/GPIOA7TIN3/ANA3 & ANB3/PWM5/CMP1_OUT K/ SI/ C O T M 3/ B O PI G Figure7. Top View, MC56F8006 48-Pin LQFP Package 4.3 56F8006/56F8002 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed via the GPIO module’s peripheral enable registers (GPIO_x_PER) and SIM module’s (GPS_xn) GPIO peripheral select registers. If CLKIN or XTAL is selected as device external clock input, the CLK_MOD bit in the OCCS oscillator control register (OSCTL) needs to be set too. EXT_SEL bit in OSCTL selects CLKIN or XTAL. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 17

Signal/Connection Descriptions Table5. 56F8006/56F8002 Signal and Package Information 32 State Signal 28 32 48 PSDI Type During Signal Description Name SOIC LQFP LQFP P Reset V 21 Supply Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface. DD V 31 DD V 19 26 22 38 DD V 8 13 9 20 Supply Supply I/O Ground — These pins provide ground for chip I/O interface. SS V 30 SS V 20 27 23 39 SS V 3 8 4 12 Supply Supply Analog Power — This pin supplies 3.3V power to the analog DDA modules. It must be connected to a clean analog power supply. V 4 9 5 13 Supply Supply Analog Ground — This pin supplies an analog ground to the analog SSA modules. It must be connected to a clean power supply. RESET 10 15 11 23 Input Input, Reset — This input is a direct hardware reset on the processor. internal When RESET is asserted low, the device is initialized and placed in pullup the reset state. A Schmitt-trigger input is used for noise immunity. enabled The internal reset signal is deasserted synchronous with the internal clocks after a fixed number of internal clocks. (GPIOA7) Input/ Port A GPIO — This GPIO pin can be individually programmed as Output an input or output pin. RESET functionality is disabled in this mode and the chip can be reset only via POR, COP reset, or software reset. After reset, the default state is RESET. GPIOA0 22 29 25 44 Input/ Input, Port A GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup enabled (PWM0) Output PWM0 — The PWM channel 0. After reset, the default state is GPIOA0. GPIOA1 21 28 24 43 Input/ Input, Port A GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup enabled (PWM1) Output PWM1 — The PWM channel 1. After reset, the default state is GPIOA1. GPIOA2 23 19 35 Input/ Input, Port A GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup enabled (PWM2) Output PWM2 — The PWM channel 2. After reset, the default state is GPIOA2. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 18 Freescale Semiconductor

Signal/Connection Descriptions Table5. 56F8006/56F8002 Signal and Package Information (continued) 32 State Signal 28 32 48 PSDI Type During Signal Description Name SOIC LQFP LQFP P Reset GPIOA3 17 24 20 36 Input/ Input, Port A GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup enabled (PWM3) Output PWM3 — The PWM channel 3. (TXD) Output TXD — The SCI transmit data output or transmit/receive in single wire operation. (EXTAL) Analog EXTAL — External Crystal Oscillator Input. This input can be Input connected to a 32.768 kHz or 1–16 MHz external crystal or ceramic resonator. When used to supply a source to the internal PLL, the crystal/resonator must be in the 4 MHz to 8 MHz range. Tie this pin low or configure as GPIO if XTAL is being driven by an external clock source. If using a 32.768 kHz crystal, place the crystal as close as possible to device pins to speed startup. After reset, the default state is GPIOA3. GPIOA4 16 22 18 33 Input/ Input, Port A GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (PWM4) Output enabled PWM4 — The PWM channel 4. (SDA) Input/Open- SDA — The I2C serial data line. drain Output (FAULT1) Input FAULT1 — PWM fault input 1used for disabling selected PWM outputs in cases where fault conditions originate off-chip. (TIN2) Input TIN2 — Dual timer module channel 2 input After reset, the default state is GPIOA4. GPIOA5 14 20 16 29 Input/ Input, Port A GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (PWM5) Output enabled PWM5 — The PWM channel 5. (FAULT2/ Input/ FAULT2 — PWM fault input 2 used for disabling selected PWM EXT_SYNC) Output outputs in cases where fault conditions originate off-chip. EXT_SYNC — When not being used as a fault input, this pin can be used to receive a pulse to reset the PWM counter or to generate a positive pulse at the start of every PWM cycle. (TIN3) Input TIN3 — Dual timer module channel 3 input After reset, the default state is GPIOA5. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 19

Signal/Connection Descriptions Table5. 56F8006/56F8002 Signal and Package Information (continued) 32 State Signal 28 32 48 PSDI Type During Signal Description Name SOIC LQFP LQFP P Reset GPIOA6 12 18 14 26 Input/ Input, Port A GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (FAULT0) Input enabled FAULT0 — PWM fault input 0 used for disabling selected PWM outputs in cases where fault conditions originate off-chip. (ANA1 & Analog ANA1 and ANB1 — Analog input to channel 1 of ADCA and ADCB. ANB1) Input SCL — The I2C serial clock (SCL) Input/Open- drain Output TXD — The SCI transmit data output or transmit/receive in single (TXD) Output wire operation. CLKO_1 — This is a buffered clock output; the clock source is (CLKO_1) Output selected by clockout select (CLKOSEL) bits in the clock output select register (CLKOUT) in the SIM. When used as an analog input, the signal goes to the ANA1 and ANB1. After reset, the default state is GPIOA6. GPIOB0 15 21 17 32 Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (SCLK) Input/ enabled SCLK — The SPI serial clock. In master mode, this pin serves as Output an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. (SCL) Input/Open- SCL — The I2C serial clock. drain Output (ANB13) Analog ANB13 — Analog input to channel 13 of ADCB Input (PWM3) Output PWM3 — The PWM channel 3. (T1) Input/ T1 — Dual timer module channel 1 input/output. Output After reset, the default state is GPIOB0. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 20 Freescale Semiconductor

Signal/Connection Descriptions Table5. 56F8006/56F8002 Signal and Package Information (continued) 32 State Signal 28 32 48 PSDI Type During Signal Description Name SOIC LQFP LQFP P Reset GPIOB1 27 2 30 2 Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (SS) Input/ enabled SS — SS is used in slave mode to indicate to the SPI module that Output the current transfer is to be received. (SDA) Input/Open- SDA — The I2C serial data line. drain Output (ANA12 and Analog ANA12 and CMP2_P3 — Analog input to channel 12 of ADCA and CMP2_P3) input Positive input 3 of analog comparator 2. When used as an analog input, the signal goes to the ANA12 and CMP2_P3. After reset, the default state is GPIOB1. GPIOB2 17 13 25 Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (MISO) Input/ enabled MISO — Master in/slave out. In master mode, this pin serves as the Output data input. In slave mode, this pin serves as the data output. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. (TIN2) Input/ TIN2 — Dual timer module channel 2 input. Output (ANA2 and Analog ANA2 and ANB2 — Analog input to channel 2 of ADCA and ADCB. ANB2) Input CMP0_OUT— Analog comparator 0 output. (CMP0_ Output OUT) When used as an analog input, the signal goes to the ANA2 and ANB2. After reset, the default state is GPIOB2. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 21

Signal/Connection Descriptions Table5. 56F8006/56F8002 Signal and Package Information (continued) 32 State Signal 28 32 48 PSDI Type During Signal Description Name SOIC LQFP LQFP P Reset GPIOB3 11 16 12 24 Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (MOSI) Input/ enabled MOSI — Master out/slave in. In master mode, this pin serves as the Output data output. In slave mode, this pin serves as the data input. (TIN3) Input/ TIN3 — Dual timer module channel 3 input. Output (ANA3 and Input ANA3 and ANB3 — Analog input to channel 3 of ADCA and ADCB. ANB3) PWM5 — The PWM channel 5. (PWM5) Output CMP1_OUT— Analog comparator 1 output. (CMP1_ Output OUT When used as an analog input, the signal goes to the ANA3 and ANB3. After reset, the default state is GPIOB3. GPIOB4 13 19 15 27 Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (T0) Input/ enabled T0 — Dual timer module channel 0 input/output. Output (CLKO_0) Output CLKO_0 — This is a buffered clock output; the clock source is selected by clockout select (CLKOSEL) bits in the clock output select register (CLKOUT) of the SIM. (MISO) Input/ MISO — Master in/slave out. In master mode, this pin serves as the Output data input. In slave mode, this pin serves as the data output. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. (SDA) Input/Open- SDA — The I2C serial data line. drain Output (RXD) Input RXD — The SCI receive data input. (ANA0 and Analog ANA0 and ANB0 — Analog input to channel 0 of ADCA and ADCB. ANB0) Input When used as an analog input, the signal goes to the ANA0 and ANB0. After reset, the default state is GPIOB4. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 22 Freescale Semiconductor

Signal/Connection Descriptions Table5. 56F8006/56F8002 Signal and Package Information (continued) 32 State Signal 28 32 48 PSDI Type During Signal Description Name SOIC LQFP LQFP P Reset GPIOB5 4 32 4 Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (T1) Input/ enabled T1 — Dual timer module channel 1 input/output. Output (FAULT3) Input FAULT3 — PWM fault input 3 used for disabling selected PWM outputs in cases where fault conditions originate off-chip. (SCLK) Input SCLK — SPI serial clock. In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. After reset, the default state is GPIOB5. GPIOB6 26 1 29 1 Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (SDA) Input/Open- enabled SDA — The I2C serial data line. drain Output (ANA13 and Analog ANA13 and CMP0_P2 — Analog input to channel 13 of ADCA and CMP0_P2) Input positive input 2 of analog comparator 0. (CLKIN) Input External Clock Input — This pin serves as an external clock input. When used as an analog input, the signal goes to the ANA13 and CMP0_P2. After reset, the default state is GPIOB6. GPIOB7 3 31 3 Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (TXD) Input/ enabled TXD — The SCI transmit data output or transmit/receive in single Output wire operation. (SCL) Input/Open- SCL — The I2C serial clock. drain Output (ANA11 and Analog ANA11 and CMP2_M3 — Analog input to channel 11 of ADCA and CMP2_M3) Input negative input 3 of analog comparator 2. When used as an analog input, the signal goes to the ANA11 and CMP2_M3. After reset, the default state is GPIOB7. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 23

Signal/Connection Descriptions Table5. 56F8006/56F8002 Signal and Package Information (continued) 32 State Signal 28 32 48 PSDI Type During Signal Description Name SOIC LQFP LQFP P Reset ANA5 and 7 12 8 19 Analog Analog ANA5 and CMP1_M1— Analog input to channel 5 of ADCA and CMP1_M1 Input Input negative input 1 of analog comparator 1. (GPIOC0) Analog Port C GPIO — This GPIO pin can be individually programmed as Input an input or output pin. (FAULT0) Input FAULT0 — PWM fault input 0 is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. When used as an analog input, the signal goes to the ANA5 and CMP1_M1. After reset, the default state is ANA5 and CMP1_M1. ANA7 and 6 11 7 17 Analog Analog ANA7 and PGA0+ and CMP2_M2 — Analog input to channel 7 of PGA0+ and Input Input ADCA and PGA0 positive input and negative input 2 of analog CMP2_M2 comparator 2. (GPIOC1) Input/ Port C GPIO — This GPIO pin can be individually programmed as Output an input or output pin. When used as an analog input, The signal goes to the ANA7 and PGA0+ and CMP2_M2. After reset, the default state is ANA7 and PGA0+ and CMP2_M2. ANA9 and 5 10 6 15 Analog Analog ANA9 and PGA0– and CMP2_P4 — Analog input to channel 9 of PGA0– and Input Input ADCA and PGA0 negative input and positive input 4 of analog CMP2_P4 comparator 2. (GPIOC2) Input/ Port C GPIO — This GPIO pin can be individually programmed as Output an input or output pin. When used as an analog input, The signal goes to the ANA9 and PGA0– and CMP2_P4. After reset, the default state is ANA9 and PGA0– and CMP2_P4. GPIOC3 46 Input/ Input, Port C GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (EXT_ Input enabled EXT_TRIGGER — PDB external trigger input. TRIGGER) After reset, the default state is GPIOC3. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 24 Freescale Semiconductor

Signal/Connection Descriptions Table5. 56F8006/56F8002 Signal and Package Information (continued) 32 State Signal 28 32 48 PSDI Type During Signal Description Name SOIC LQFP LQFP P Reset ANB8 and 28 5 1 7 Analog Analog ANB8 and PGA1+ and CMP0_M2 — Analog input to channel 8 of PGA1+ and Input Input ADCB and PGA1 positive input and negative input 2 of analog CMP0_M2 comparator 0. (GPIOC4) Input/ Port C GPIO — This GPIO pin can be individually programmed as Output an input or output pin. When used as an analog input, the signal goes to the ANB8 and PGA1+ and CMP0_M2. After reset, the default state is ANB8 and PGA1+ and CMP0_M2. ANB6 and 1 6 2 9 Input/ Analog ANB6 and PGA1– and CMP0_P4 — Analog input to channel 6 of PGA1– and Output Input ADCB and PGA1 negative input and positive input 4 of analog CMP0_P4 comparator 0. (GPIOC5) Analog Port C GPIO — This GPIO pin can be individually programmed as Input an input or output pin. When used as an analog input, the signal goes to the ANB6 and PGA1– and CMP0_P4. After reset, the default state is ANB6 and PGA1– and CMP0_P4. ANB4 and 2 7 3 11 Analog Analog ANB4 and CMP1_P1 — Analog input to channel 4 of ADCB and CMP1_P1 Input Input positive input 1 of analog comparator 1. (GPIOC6) Input/ Port C GPIO — This GPIO pin can be individually programmed as Output an input or output pin. (PWM2) Output PWM2 — The PWM channel 2. When used as an analog input, the signal goes to the ANB4 and CMP1_P1. After reset, the default state is ANB4 and CMP1_P1. GPIOC7 10 Input/ Input, Port C GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup enabled (ANB5 and Analog ANB5 and CMP1_M2 — Analog input to channel 5 of ADCB and CMP1_M2) Input negative input 2 of analog comparator 1. After reset, the default state is GPIOC7. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 25

Signal/Connection Descriptions Table5. 56F8006/56F8002 Signal and Package Information (continued) 32 State Signal 28 32 48 PSDI Type During Signal Description Name SOIC LQFP LQFP P Reset TDI 23 30 26 45 Input Input, Test Data Input — This input pin provides a serial input data stream internal to the JTAG/EOnCE port. It is sampled on the rising edge of TCK pullup and has an on-chip pullup resistor. enabled (GPIOD0) Input/ Port D GPIO — This GPIO pin can be individually programmed as Output an input or output pin. (ANB12) Analog ANB12 — Analog input to channel 12 of ADCB Input (SS) Input SS — SS is used in slave mode to indicate to the SPI module that the current transfer is to be received. (TIN2) Input TIN2 — Dual timer module channel 2 input. (CMP0_ Output CMP1_OUT — Analog comparator 1 output. OUT) After reset, the default state is TDI. TDO 25 32 28 48 Output Output, Test Data Output — This three-stateable output pin provides a serial tri-stated, output data stream from the JTAG/EOnCE port. It is driven in the internal shift-IR and shift-DR controller states, and changes on the falling pullup edge of TCK. enabled (GPIOD1) Input/ Port D GPIO — This GPIO pin can be individually programmed as Output an input or output pin. (ANB10) Analog ANB10 — Analog input to channel 10 of ADCB. Input (T0) Input/ T0 — Dual timer module channel 0 input/output. Output (CMP2_ Output CMP2_OUT — Analog comparator 2 output. OUT) After reset, the default state is TDO. TCK 9 14 10 22 Input Input, Test Clock Input — This input pin provides a gated clock to internal synchronize the test logic and shift serial data to the JTAG/EOnCE pullup port. The pin is connected internally to a pullup resistor. A enabled Schmitt-trigger input is used for noise immunity. (GPIOD2) Input/ Port D GPIO — This GPIO pin can be individually programmed as Output an input or output pin. (ANA4 and Analog ANA4 and CMP1_P2 — Analog input to channel 4 of ADCA and CMP1_P2) Input positive input 2 of analog comparator 1. (CMP2_ Output CMP2_OUT — Analog comparator 2 output. OUT) After reset, the default state is TCK. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 26 Freescale Semiconductor

Signal/Connection Descriptions Table5. 56F8006/56F8002 Signal and Package Information (continued) 32 State Signal 28 32 48 PSDI Type During Signal Description Name SOIC LQFP LQFP P Reset TMS 24 31 27 47 Input Input, Test Mode Select Input — This input pin is used to sequence the internal JTAG TAP controller’s state machine. It is sampled on the rising pullup edge of TCK and has an on-chip pullup resistor. enabled (GPIOD3) Input/ Port D GPIO — This GPIO pin can be individually programmed as Output an input or output pin. (ANB11) Analog ANB11 — Analog input to channel 11 of ADCB. Input (T1) Input/ T1 — Dual timer module channel 1 input/output. Output (CMP1_ Output CMP1_OUT — Analog comparator 2 output. OUT) After reset, the default state is TMS. Always tie the TMS pin to VDD through a 2.2 k resistor. GPIOE0 5 Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup enabled After reset, the default state is GPIOE0. GPIOE1 6 Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (ANB9 and Analog enabled ANB9 and CMP0_P1 — Analog input to channel 9 of ADCB and CMP0_P1) Input positive input 1 of analog comparator 0. After reset, the default state is GPIOE1. GPIOE2 8 Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (ANB7 and Analog enabled ANB7 and CMP0_M1 — Analog input to channel 7 of ADCB and CMP0_M1) Input negative input 1 of analog comparator 0. After reset, the default state is GPIOE2. GPIOE3 14 Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (ANA10 and Analog enabled ANA10 and CMP2_M1— Analog input to channel 10 of ADCA and CMP2_M1) Input negative input 1 of analog comparator 2. After reset, the default state is GPIOE3. GPIOE4 18 Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (ANA6 and Analog enabled ANA6 and CMP2_P2 — Analog input to channel 6 of ADCA and CMP2_P2) Input positive input 2 of analog comparator 2. After reset, the default state is GPIOE4. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 27

Signal/Connection Descriptions Table5. 56F8006/56F8002 Signal and Package Information (continued) 32 State Signal 28 32 48 PSDI Type During Signal Description Name SOIC LQFP LQFP P Reset GPIOE5 16 Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (ANA8 and Analog enabled ANA8 and CMP2_P1— Analog input to channel 8 of ADCA and CMP2_P1) Input positive input 1 of analog comparator 2. After reset, the default state is GPIOE5. GPIOE6 28 Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup enable After reset, the default state is GPIOE6. GPIOE7 34 Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin pullup (CMP1_M3) Analog enabled CMP1_M3 — Analog input to both negative input 3 of analog Input comparator 1. After reset, the default state is GPIOE7. GPIOF0 18 25 21 37 Input/ Input, Port F GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (XTAL) Analog enabled XTAL — External Crystal Oscillator Output. This output connects Input/ the internal crystal oscillator output to an external crystal or ceramic Output resonator. After reset, the default state is GPIOF0. GPIOF1 40 Input/ Input, Port F GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin (CMP1_P3) pullup Analog enabled CMP1_P3 — Analog input to both positive input 3 of analog Input comparator 1. After reset, the default state is GPIOF1 GPIOF2 41 Input/ Input, Port F GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (CMP0_M3) Analog enabled CMP0_M3 — Analog input to both negative input 3 of analog Input comparator 0. After reset, the default state is GPIOF2. GPIOF3 42 Input/ Input, Port F GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup (CMP0_P3) Analog enabled CMP0_P3 — Analog input to both positive input 3 of analog Input comparator 0. After reset, the default state is GPIOF3. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 28 Freescale Semiconductor

Memory Maps 5 Memory Maps 5.1 Introduction The 56F8006/56F8002 device is based on the 56800E core. It uses a dual Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is shared by both data and program spaces and flash memory is used only in program space. This section provides memory maps for: • Program address space, including the interrupt vector table • Data address space, including the EOnCE memory and peripheral memory maps On-chip memory sizes for the device are summarized in Table6. Flash memories’ restrictions are identified in the “Use Restrictions” column of Table6. Table6. Chip Memory Configurations On-Chip Memory 56F8006 56F8002 Use Restrictions Program Flash 8K x 16 6K x 16 Erase/program via flash interface unit and word writes to CDBW (PFLASH) or or 16 KB 12 KB Unified RAM (RAM) 1K x 16 1K x 16 Usable by the program and data memory spaces or or 2 KB 2 KB 5.2 Program Map The 56F8006/56F8002 series provide up to 16 KB on-chip flash memory. It primarily accesses through the program memory buses (PAB; PDB). PAB is used to select program memory addresses; instruction fetches are performed over PDB. Data can be read and written to program memory space through primary data memory buses: CDBW for data write and CDBR for data read. Accessing program memory space over the data memory buses takes longer access time compared to accessing data memory space. The special MOVE instructions are provided to support these accesses. The benefit is that non time critical constants or tables can be stored and accessed in program memory. The program memory map is shown in Table7 and Table8. Table7. Program Memory Map1 for 56F8006 at Reset Begin/End Address Memory Allocation P: 0x1F FFFF RESERVED P: 0x00 8800 P: 0x00 83FF On-Chip RAM2: 2 KB P: 0x00 8000 P: 0x00 7FFF RESERVED P: 0x00 2000 P: 0x00 1FFF (cid:129) Internal program flash: 16 KB P: 0x00 0000 (cid:129) Interrupt vector table locates from 0x00 0000 to 0x00 0065 (cid:129) COP reset address = 0x00 0002 (cid:129) Boot location = 0x00 0000 1 All addresses are 16-bit word addresses. 2 This RAM is shared with data space starting at address X: 0x00 0000; see Figure8. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 29

Memory Maps Table8. Program Memory Map1 for 56F8002 at Reset (continued) Begin/End Address Memory Allocation P: 0x1F FFFF RESERVED P: 0x00 8800 P: 0x00 83FF On-Chip RAM2: 2 KB P: 0x00 8000 P: 0x00 7FFF RESERVED P: 0x00 2000 P: 0x00 1FFF (cid:129) Internal program flash: 12 KB P: 0x00 0800 (cid:129) Interrupt vector table locates from 0x00 0800 to 0x00 0865 (cid:129) COP reset address = 0x00 0802 (cid:129) Boot location = 0x00 0800 P: 0x00 07FF RESERVED P: 0x00 0000 1 All addresses are 16-bit word addresses. 2 This RAM is shared with data space starting at address X: 0x00 0000; see Figure9. 5.3 Data Map The 56F8006/56F8002 series contain a dual access memory. It can be accessed from core primary data buses (XAB1; CDBW; CDBR) and secondary data buses (XAB2; XDB2). Addresses in data memory are selected on the XAB1 and XAB2 buses. Byte, word, and long data transfers occur on the 32-bit CDBR and CDBW buses. A second 16-bit read operation can be performed in parallel on the XDB2 bus. Peripheral registers and on-chip JTAG/EOnCE controller registers are memory-mapped into data memory access. A special direct address mode is supported for accessing a first 64-location in data memory by using a single word instruction. The data memory map is shown in Table9. Table9. Data Memory Map1 Begin/End Address Memory Allocation X:0xFF FFFF EOnCE X:0xFF FF00 256 locations allocated X:0xFF FEFF RESERVED X:0x01 0000 X:0x00 FFFF On-Chip Peripherals X:0x00 F000 4096 locations allocated X:0x00 EFFF RESERVED X:0x00 8800 X:0x00 87FF RESERVED X:0x00 8000 X:0x00 7FFF RESERVED X:0x00 0400 X:0x00 03FF On-Chip Data RAM X:0x00 0000 2 KB2 1 All addresses are 16-bit word addresses. 2 This RAM is shared with Program space starting at P: 0x00 8000. See Figure8 and Figure9. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 30 Freescale Semiconductor

Memory Maps On-chip RAM is also mapped into program space starting at P: 0x00 8000. This makes for easier online reprogramming of on-chip flash. Program Data EOnCE 0xFF FF00 Reserved 0x00 8400 Reserved RAM 0x01 0000 0x00 8000 Peripherals 0x00 F000 Reserved Dual Port RAM Reserved 0x00 2000 0x00 0400 Flash RAM 0x00 0000 0x00 0000 Figure8. 56F8006 Dual Port RAM Map Program Data EOnCE 0xFF FF00 Reserved 0x00 8400 Reserved RAM 0x01 0000 0x00 8000 Peripherals Reserved 0x00 F000 Dual Port RAM 0x00 2000 Reserved Flash 0x00 0400 0x00 0800 RAM Reserved 0x00 0000 0x00 0000 Figure9. 56F8002 Dual Port RAM Map 5.4 Interrupt Vector Table and Reset Vector The location of the vector table is determined by the vector base address register (VBA). The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower seven bits are determined based on the highest priority interrupt and are then appended onto VBA before presenting the full VAB to the core. Please see the MC56F8006 Peripheral Reference Manual for detail. The reset startup addresses of 56F8002 and 56F8006 are different. • 56F8006 startup address is located at 0x00 0000. The reset value of VBA is reset to a value of 0x0000 that corresponds to address 0x00 0000 • 56F8002 startup address is located at 0x00 0800. The reset value of VBA is reset to a value of 0x0010 that corresponds to address 0x00 0800 By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. The highest number vector, a user assignable vector USER6 (vector 50), can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 31

Memory Maps Table43 provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals. 5.5 Peripheral Memory-Mapped Registers The locations of on-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read or written using word accesses only. Table10 summarizes the base addresses for the set of peripherals on the 56F8006/56F8002 devices. Peripherals are listed in order of the base address. Table10. Data Memory Peripheral Base Address Map Summary Peripheral Prefix Base Address Dual Channel Timer TMR X:0x00 F000 PWM Module PWM X:0x00 F020 Interrupt Controller INTC X:0x00 F040 ADCA ADCA X:0x00 F060 ADCB ADCB X:0x00 F080 Programmable Gain Amplifier 0 PGA0 X:0x00 F0A0 Programmable Gain Amplifier 1 PGA1 X:0x00 F0C0 SCI SCI X:0x00 F0E0 SPI SPI X:0x00 F100 I2C I2C X:0x00 F120 Computer Operating Properly COP X:0x00 F140 On-Chip Clock Synthesis OCCS X:0x00 F160 GPIO Port A GPIOA X:0x00 F180 GPIO Port B GPIOB X:0x00 F1A0 GPIO Port C GPIOC X:0x00 F1C0 GPIO Port D GPIOD X:0x00 F1E0 GPIO Port E GPIOE X:0x00 F200 GPIO Port F GPIOF X:0x00 F220 System Integration Module SIM X:0x00 F240 Power Management Controller PMC X:0x00 F260 Analog Comparator 0 CMP0 X:0x00 F280 Analog Comparator 1 CMP1 X:0x00 F2A0 Analog Comparator 2 CMP2 X:0x00 F2C0 Programmable Interval Timer PIT X:0x00 F2E0 Programmable Delay Block PDB X:0x00 F300 Real Timer Clock RTC X:0x00 F320 Flash Memory Interface FM X:0x00 F400 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 32 Freescale Semiconductor

Memory Maps 5.6 EOnCE Memory Map Control registers of the EOnCE are located at the top of data memory space. These locations are fixed by the 56F800E core. These registers can also be accessed through JTAG port if flash security is not set. Table11 lists all EOnCE registers necessary to access or control the EOnCE. Table11. EOnCE Memory Map Address Register Acronym Register Name X:0xFF FFFF OTX1/ORX1 Transmit Register Upper Word Receive Register Upper Word X:0xFF FFFE OTX/ORX Transmit Register (32 bits) Receive Register X:0xFF FFFD OTXRXSR Transmit and Receive Status and Control Register X:0xFF FFFC OCLSR Core Lock/Unlock Status Register X:0xFF FFFB– Reserved X:0xFF FFA1 X:0xFF FFA0 OCR Control Register X:0xFF FF9F– OSCNTR Instruction Step Counter X:0xFF FF9E (24 bits) X:0xFF FF9D OSR Status Register X:0xFF FF9C OBASE Peripheral Base Address Register X:0xFF FF9B OTBCR Trace Buffer Control Register X:0xFF FF9A OTBPR Trace Buffer Pointer Register X:0xFF FF99– OTB Trace Buffer Register Stages X:0xFF FF98 (21–24 bits/stage) X:0xFF FF97– OBCR Breakpoint Unit Control Register X:0xFF FF96 (24 bits) X:0xFF FF95– OBAR1 Breakpoint Unit Address Register 1 X:0xFF FF94 (24 bits) X:0xFF FF93– OBAR2 (32 bits) Breakpoint Unit Address Register 2 X:0xFF FF92 X:0xFF FF91– OBMSK (32 bits) Breakpoint Unit Mask Register 2 X:0xFF FF90 X:0xFF FF8F Reserved X:0xFF FF8E OBCNTR EOnCE Breakpoint Unit Counter X:0xFF FF8D Reserved X:0xFF FF8C Reserved X:0xFF FF8B Reserved X:0xFF FF8A OESCR External Signal Control Register X:0xFF FF89 – Reserved X:0xFF FF00 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 33

General System Control Information 6 General System Control Information 6.1 Overview This section discusses power pins, reset sources, interrupt sources, clock sources, the system integration module (SIM), ADC synchronization, and JTAG/EOnCE interfaces. 6.2 Power Pins V , V and V , V are the primary power supply pins for the devices. This voltage source supplies power to all on-chip DD SS DDA SSA peripherals, I/O buffer circuitry and to internal voltage regulators. Device has multiple internal voltages provide regulated lower-voltage source for the peripherals, core, memory, and on-chip relaxation oscillators. Typically, there are at least two separate capacitors across the power pins to bypass the glitches and provide bulk charge storage. In this case, there should be a bulk electrolytic or tantalum capacitor, such as a 10 F tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1 F ceramic bypass capacitor located as near to the device power pins as practical to suppress high-frequency noise. Each pin must have a bypass capacitor for best noise suppression. V and V are the analog power supply pins for the device. This voltage source supplies power to the ADC, PGA, and DDA SSA CMP modules. A 0.1 F ceramic bypass capacitor should be located as near to the device V and V pins as practical to DDA SSA suppress high-frequency noise. V and V are also the voltage reference high and voltage reference low inputs, DDA SSA respectively, for the ADC module. 6.3 Reset Resetting the device provides a way to start processing from a known set of initial conditions. During reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector. On-chip peripheral modules are disabled and I/O pins are initially configured as the reset status shown in Table5. The 56F8006/56F8002 has the following sources for reset: • Power-on reset (POR) • Partial power down reset (PPD) • Low-voltage detect (LVD) • External pin reset (EXTR) • Computer operating properly loss of reference reset (COP_LOR) • Computer operating properly time-out reset (COP_CPU) • Software Reset (SWR) Each of these sources has an associated bit in the reset status register (RSTAT) in the system integration module (SIM). The external pin reset function is shared with an GPIO port A7 on the RESET/GPIOA7 pin. The reset function is enabled following any reset of the device. Bit 7 of GPIOA_PER register must be cleared to use this pin as an GPIO port pin. When enabled as the RESET pin, an internal pullup device is automatically enabled. 6.4 On-chip Clock Synthesis The on-chip clock synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56F8000 family devices at user-selectable frequencies up to 32 MHz. The features of OCCS module include: • Ability to power down the internal relaxation oscillator or crystal oscillator • Ability to put the internal relaxation oscillator into standby mode • Ability to power down the PLL MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 34 Freescale Semiconductor

General System Control Information • Provides a 3X system clock that operates at three times the system clock to PWM, timer, and SCI modules • Safety shutdown feature is available if the PLL reference clock is lost • Can be driven from an external clock source The clock generation module provides the programming interface for the PLL, internal relaxation oscillator, and crystal oscillator. It also provides a postscaler to divide clock frequency down by 1, 2, 4, 8, 16, 32, 64, 128, 256 before feeding to the SIM. The SIM is responsible for further dividing these frequencies by two, which ensures a 50% duty cycle in the system clock output. For detail, see the OCCS chapter in the MC56F8006 Peripheral Reference Manual. 6.4.1 Internal Clock Source An internal relaxation oscillator can supply the reference frequency when an external frequency source or crystal is not used. It is optimized for accuracy and programmability while providing several power-saving configurations that accommodate different operating conditions. The internal relaxation oscillator has little temperature and voltage variability. To optimize power, the internal relaxation oscillator supports a run state (8 MHz), standby state (400 kHz), and a power-down state. During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the PLLCR word is set to 0). Application code can then also switch to the external clock source and power down the internal oscillator, if desired. If a changeover between internal and external clock sources is required at power-on, ensure that the clock source is not switched until the desired external clock source is enabled and stable. To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.078% of 8 MHz by trimming an internal capacitor. Bits 0–9 of the OSCTL (oscillator control) register allow you to set in an additional offset (trim) to this preset value to increase or decrease capacitance. Each unit added or subtracted changes the output frequency by about 0.078% of 8 MHz, allowing incremental adjustment until the desired frequency accuracy is achieved. The center frequency of the internal oscillator is calibrated at the factory to 8 MHz and the TRIM value is stored in the flash information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM. For further information, see the MC56F8006 Peripheral Reference Manual. 6.4.2 Crystal Oscillator/Ceramic Resonator The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in the frequency range, specified for the external crystal, of 32.768 kHz (Typ) or 1–16 MHz. A ceramic resonator can be substituted for the 1–16 MHz range. When used to supply a source to the internal PLL, the recommended crystal/resonator is in the 4 MHz to 8 MHz (recommend 8 MHz) range to achieve optimized PLL performance. Oscillator circuits are shown in Figure10, Figure11, and Figure12. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. When using low-frequency, low-power mode, the only external component is the crystal itself. In the other oscillator modes, load capacitors (C , C ) and feedback resistor (R ) are required. In addition, a series resistor (R ) may be used in high-gain modes. x y F S Recommended component values are listed in Table28. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 35

General System Control Information 56F8002/56F8006 XTAL EXTAL Crystal Frequency = 32–38.4 kHz Figure10. Typical Crystal Oscillator Circuit: Low-Range, Low-Power Mode 56F8002/56F8006 XTAL EXTAL Crystal Frequency = 1–16 MHz R F C C 1 2 Figure11. Typical Crystal or Ceramic Resonator Circuit: High-Range, Low-Power Mode 56F8002/56F8006 XTAL EXTAL R Low Range: Crystal Frequency = 32–38.4 kHz S or High Range: Crystal Frequency = 1–16 MHz R F C C 1 2 Figure12. Typical Crystal or Ceramic Resonator Circuit: Low Range and High Range, High-Gain Mode 6.4.3 External Clock Input — Crystal Oscillator Option The recommended method of connecting an external clock is illustrated in Figure13. The external clock source is connected to XTAL and the EXTAL pin is grounded or configured as GPIO while CLK_MOD bit in OSCTL register is set. The external clock input must be generated using a relatively low impedance driver with maximum frequency less than 8 MHz. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 36 Freescale Semiconductor

General System Control Information 56F8006/56F8002 CLK_MOD = 1 XTAL EXTAL External Clock GND or GPIO (<50 MHz) Figure13. Connecting an External Clock Signal Using XTAL 6.4.4 Alternate External Clock Input The recommended method of connecting an external clock is illustrated in Figure14. The external clock source is connected to GPIOB6/RXD/SDA/ANA13 and CMP0_P2/CLKIN while EXT_SEL bit in OSCTL register is set and corresponding bits in GPIOB_PER register GPIO module and GPSB1 register in the system integration module (SIM) are set to the correct values. The external clock input must be generated using a relatively low impedance driver with maximum frequency not greater than 64MHz. EXT_SEL = 1; 56F8002/56F8006 GPIO_B_PER[6] = 0; GPIOB6/RXD/SDA/ANA13 and CMP0_P2/CLKIN GPS_B6 = 11 External Clock ( 64 MHz) Figure14. Connecting an External Clock Signal Using GPIO 6.5 Interrupt Controller The 56F8006/56F8002 interrupt controller (INTC) module arbitrates the various interrupt requests (IRQs). The INTC signals to the 56800E core when an interrupt of sufficient priority exists and what address to jump to to service this interrupt. The interrupt controller contains registers that allow up to three interrupt sources to be set to priority level 1 and other up to three interrupt sources to be set to priority level 2. By default, all peripheral interrupt sources are set to priority level 0. Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numeric value of the active interrupt requests for that level. Within a given priority level, the lowest vector number is the highest priority and the highest vector number is the lowest. The highest vector number, a user assignable vector USER6 (vector 50), can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail. 6.6 System Integration Module (SIM) The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features including the pin muxing control; inter-module connection control (for example connecting comparator output to PWM fault input); individual peripheral enable/disable; PWM, timer, and SCI clock rate control; enabling peripheral operation in stop mode; port configuration overwrite protection. For further information, see the MC56F8006 Peripheral Reference Manual. The SIM is responsible for the following functions: • Chip reset sequencing • Core and peripheral clock control and distribution • Stop/wait mode control • System status control MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 37

General System Control Information • Registers containing the JTAG ID of the chip • Controls for programmable peripheral and GPIO connections • Peripheral clocks for TMR and PWM and SCI with a high-speed (3X) option • Power-saving clock gating for peripherals • Controls the enable/disable functions of large regulator standby mode with write protection capability • Permits selected peripherals to run in stop mode to generate stop recovery interrupts • Controls for programmable peripheral and GPIO connections • Software chip reset • I/O short address base location control • Peripheral protection control to provide runaway code protection for safety-critical applications • Controls output of internal clock sources to CLKO pin • Four general-purpose software control registers are reset only at power-on • Peripherals stop mode clocking control 6.7 PWM, PDB, PGA, and ADC Connections The comparators, timers, and PWM_reload_sync output can be connected to the programmable delay block (PDB) trigger input. The PDB pre-trigger A and trigger A outputs are connected to the ADCA and PGA0 hardware trigger inputs. The PDB pre-trigger B and trigger B outputs are connected to the ADCB and PGA1 hardware trigger inputs. When the input trigger of PDB is asserted, PDB trigger and pre-trigger outputs are asserted after a delay of a pre-programmed period. See the MC56F8006 Peripheral Reference Manual for additional information. CMP0 CMP1 CMP2 PWM EXT TMR0 TMR1 SW Trigger0 Trigger1 Trigger2 Trigger3 Trigger4 Trigger5 Trigger6 Trigger7 System Programmable Delay Block (PDB) Clock Pre- Pre- TriggerA TriggerA TriggerB TriggerB SSEL[1] SSEL[1] SSEL[0] SSEL[0] ADCA ADCA ADCB ADCB Trigger Trigger ADHWT ADHWT ANA7 ANA9 ANA15 ANB15 ANB8 ANB6 PGA0 Controller PGA1 Controller – + – + Figure15. Synchronization of ADC, PDB MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 38 Freescale Semiconductor

Security Features Each ADC contains a temperature sensor. Outputs of temperature sensors, PGAs, on-chip regulators and VDDA are internally routed to ADC inputs. • Internal PGA0 output available on ANA15 • Internal PGA0 positive input calibration voltage available on ANA16 • Internal PGA0 negative input calibration voltage available on ANA17 • Internal PGA1 output available on ANB15 • Internal PGA1 positive input calibration voltage available on ANB16 • Internal PGA1 negative input calibration voltage available on ANB17 • ADCA temperature sensor available on ANA26 • ADCB temperature sensor available on ANB26 • Output of on-chip digital voltage regulator is routed to ANA24 • Output of on-chip analog voltage regulator is routed to ANA25 • Output of on-chip small voltage regulator for ROSC is routed to ANB24 • Output of on-chip small voltage regulator for PLL is routed to ANB25 • VDDA is routed to ANA27 and ANB27 6.8 Joint Test Action Group (JTAG)/Enhanced On-Chip Emulator (EOnCE) The DSP56800E Family includes extensive integrated support for application software development and real-time debugging. Two modules, the Enhanced On-Chip Emulation module (EOnCE) and the core test access port (TAP, commonly called the JTAG port), work together to provide these capabilities. Both are accessed through a common 4-pin JTAG/EOnCE interface. These modules allow you to insert the 56F8006/56F8002 into a target system while retaining debug control. This capability is especially important for devices without an external bus, because it eliminates the need for a costly cable to bring out the footprint of the chip, as is required by a traditional emulator system. The DSP56800E EOnCE module is a Freescale-designed module used to develop and debug application software used with the chip. This module allows non-intrusive interaction with the CPU and is accessible through the pins of the JTAG interface or by software program control of the DSP56800E core. Among the many features of the EOnCE module is the support for data communication between the controller and the host software development and debug systems in real-time program execution. Other features allow for hardware breakpoints, the monitoring and tracking of program execution, and the ability to examine and modify the contents of registers, memory, and on-chip peripherals, all in a special debug environment. No user-accessible resources need to be sacrificed to perform debugging operations. The DSP56800E JTAG port is used to provide an interface for the EOnCE module to the DSP JTAG pins. Joint Test Action Group (JTAG) boundary scan is an IEEE 1149.1 standard methodology enabling access to test features using a test access port (TAP). A JTAG boundary scan consists of a TAP controller and boundary scan registers. Please contact your Freescale sales representative or authorized distributor for device-specific BSDL information. NOTE In normal operation, an external pullup on the TMS pin is highly recommend to place the JTAG state machine in reset state if this pin is not configured as GPIO. 7 Security Features The 56F8006/56F8002 offers security features intended to prevent unauthorized users from reading the contents of the flash memory (FM) array. The 56F8006/56F8002’s flash security consists of several hardware interlocks that prevent unauthorized users from gaining access to the flash array. After flash security is set, an authorized user can be enabled to access on-chip memory if a user-defined software subroutine, which reads and transfers the contents of internal memory via peripherals, is included in the application software. This MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 39

Security Features application software could communicate over a serial port, for example, to validate the authenticity of the requested access, then grant it until the next device reset. The inclusion of such a back door technique is at the discretion of the system designer. 7.1 Operation with Security Enabled After you have programmed flash with the application code, or as part of the programming of the flash with the application code, the 56F8006/56F8002 can be secured by programming the security word, 0x0002, into program memory location 0x00 1FF7. This can also be effected by use of the CodeWarrior IDE menu flash lock command. This nonvolatile word keeps the device secured after reset, caused, for example, by a power-down of the device. Refer to the flash memory chapter in the MC56F8006 Peripheral Reference Manual for detail. When flash security mode is enabled, the 56F8006/56F8002 disables the core EOnCE debug capabilities. Normal program execution is otherwise unaffected. 7.2 Flash Access Lock and Unlock Mechanisms There are several methods that effectively lock or unlock the on-chip flash. 7.2.1 Disabling EOnCE Access On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (test access port) is active and provides the chip’s boundary scan capability and access to the ID register, but proper implementation of flash security blocks any attempt to access the internal flash memory via the EOnCE port when security is enabled. This protection is effective when the device comes out of reset, even prior to the execution of any code at startup. 7.2.2 Flash Lockout Recovery Using JTAG If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared). This does not compromise security, as the entire contents of your secured code stored in flash are erased before security is disabled on the device on the next reset or power-up sequence. To start the lockout recovery sequence via JTAG, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller’s instruction register. After the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, you must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence is complete. Refer to the MC56F8006 Peripheral Reference Manual for detail, or contact Freescale. NOTE After the lockout recovery sequence has completed, you must reset the JTAG TAP controller and device to return to normal unsecured operation. Power-on reset resets both too. 7.2.3 Flash Lockout Recovery Using CodeWarrior CodeWarrior can unlock a device by selecting the Debug menu, then selecting DSP56800E, followed by Unlock Flash. Another mechanism is also built into CodeWarrior using the device’s memory configuration file. The command “Unlock_Flash_on_Connect 1” in the .cfg file accomplishes the same task as using the Debug menu. This lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared). MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 40 Freescale Semiconductor

Specifications 7.2.4 Flash Lockout Recovery without Mass Erase 7.2.4.1 Without Presenting Back Door Access Keys to the Flash Unit A user can un-secure a secured device by programming the word 0x0000 into program flash location 0x00 1FF7. After completing the programming, the JTAG TAP controller and the device must be reset to return to normal unsecured operation. You are responsible for directing the device to invoke the flash programming subroutine to reprogram the word 0x0000 into program flash location 0x00 1FF7. This is done by, for example, toggling a specific pin or downloading a user-defined key through serial interfaces. NOTE Flash contents can be programmed only from 1s to 0s. 7.2.4.2 Presenting Back Door Access Key to the Flash Unit It is possible to temporarily bypass the security through a back door access scheme, using a 4-word key, to temporarily unlock of the flash. A back door access requires support from the embedded software. This software would typically permit an external user to enter a four word code through one of the communications interfaces and then use it to attempt the unlock sequence. If your input matches the four word code stored at location 0x00 1FFC–0x00 1FFF in the flash memory, the part immediately becomes unsecured (at runtime) and you can access internal memory via JTAG/EOnCE port. Refer to the MC56F8006 Peripheral Reference Manual for detail. The key must be entered in four consecutive accesses to the flash, so this routine should be designed to run in RAM. 7.3 Product Analysis The recommended method of unsecuring a secured device for product analysis of field failures is via the method described in Section7.2.4.2, “Presenting Back Door Access Key to the Flash Unit.” The customer would need to supply technical support with the details of the protocol to access the subroutines in flash memory. An alternative method for performing analysis on a secured device would be to mass-erase and reprogram the flash with the original code, but modify the security word or not program the security word. 8 Specifications 8.1 General Characteristics The 56F8006/56F8002 is fabricated in high-density low power and low leakage CMOS with a maximum voltage of 3.6 V digital inputs during normal operation without causing damage. Absolute maximum ratings in Table12 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Unless otherwise stated, all specifications within this chapter apply over the temperature range of –40ºC to 105ºC ambient temperature over the following supply ranges: V =V =0V,V =V =3.0–3.6 V,CL<50 pF,f =32 MHz SS SSA DD DDA OP CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 41

Specifications 8.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified Table12 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the SS DD programmable pullup resistor associated with the pin is enabled. Table12. Absolute Maximum Ratings (V = 0 V, V = 0 V) SS SSA Characteristic Symbol Notes Min Max Unit Supply Voltage Range V –0.3 3.8 V DD Analog Supply Voltage Range V –0.3 3.6 V DDA Voltage difference V to V V –0.3 0.3 V DD DDA DD Voltage difference V to V V –0.3 0.3 V SS SSA SS Digital Input Voltage Range V Pin Groups 1, 2 –0.3 V +0.3 V IN DD Oscillator Voltage Range V Pin Group 4 TBD TBD V OSC Analog Input Voltage Range V Pin Group 3 –0.3 3.6 V INA Input clamp current, per pin (V < 0)1 2 3 V — –25.0 mA IN IC Output clamp current, per pin (V < 0)1 2 3 V — –20.0 mA O OC Output Voltage Range V Pin Group 1 –0.3 V V OUT DD (Normal Push-Pull mode) Ambient Temperature Industrial T –40 105 °C A Storage Temperature Range T –55 150 °C STG (Extended Industrial) 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (V ) and negative (V ) clamp voltages, then use the larger of the two resistance values. DD SS 2 All functional non-supply pins are internally clamped to V and V . SS DD 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (V > V ) is greater than I , the injection current may flow out of V and could result In DD DD DD in external power supply going out of regulation. Ensure external V loads shunt current greater than maximum injection DD current. This is the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present or if the clock rate is low (which would reduce overall power consumption). 8.2.1 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, use normal handling precautions to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM), and the charge device model (CDM). MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 42 Freescale Semiconductor

Specifications A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table13. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Series Resistance R1 1500  Human Storage Capacitance C 100 pF Body Number of Pulses per Pin — 3 Series Resistance R1 0  Machine Storage Capacitance C 200 pF Number of Pulses per Pin — 3 Minimum inpUt Voltage Limit –2.5 V Latch-up Maximum Input Voltage Limit 7.5 V Table14. 56F8006/56F8002 ESD Protection Characteristic 1 Min Typ Max Unit ESD for Human Body Model (HBM) 2000 — — V ESD for Machine Model (MM) 200 — — V ESD for Charge Device Model (CDM) 750 — — V Latch-up current at T = 85oC (I )  100 mA A LAT 1 Parameter is achieved by design characterization on a small sample size from typical devices un- der typical conditions unless otherwise noted. 8.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine I/O the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of SS DD unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small. SS DD Table15. 28SOIC Package Thermal Characteristics Value Characteristic Comments Symbol Unit (LQFP) Junction to ambient Single layer board R 70 °C/W Natural convection (1s) JA Junction to ambient Four layer board R 47 °C/W Natural convection (2s2p) JMA Junction to ambient Single layer board R 55 °C/W (@200 ft/min) (1s) JMA MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 43

Specifications Table15. 28SOIC Package Thermal Characteristics (continued) Value Characteristic Comments Symbol Unit (LQFP) Junction to ambient Four layer board R 42 °C/W (@200 ft/min) (2s2p) JMA Junction to board R 23 °C/W JB Junction to case R 26 °C/W JC Junction to package top Natural Convection  9 °C/W JT Table16. 32LQFP Package Thermal Characteristics Value Characteristic Comments Symbol Unit (LQFP) Junction to ambient Single layer board R 84 °C/W Natural convection (1s) JA Junction to ambient Four layer board R 56 °C/W Natural convection (2s2p) JMA Junction to ambient Single layer board R 70 °C/W (@200 ft/min) (1s) JMA Junction to ambient Four layer board R 49 °C/W (@200 ft/min) (2s2p) JMA Junction to board R 33 °C/W JB Junction to case R 20 °C/W JC Junction to package top Natural convection  4 °C/W JT Table17. 32PSDIP Package Thermal Characteristics Value Characteristic Comments Symbol Unit (LQFP) Junction to ambient Single layer board R 56 °C/W Natural convection (1s) JA Junction to ambient Four layer board R 41 °C/W Natural convection (2s2p) JMA Junction to ambient Single layer board R 45 °C/W (@200 ft/min) (1s) JMA Junction to ambient Four layer board R 36 °C/W (@200 ft/min) (2s2p) JMA Junction to board R 18 °C/W JB Junction to case R 24 °C/W JC Junction to package top Natural convection  10 °C/W JT MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 44 Freescale Semiconductor

Specifications Table18. 48LQFP Package Thermal Characteristics Value Characteristic Comments Symbol Unit (LQFP) Junction to ambient Single layer board R 79 °C/W Natural convection (1s) JA Junction to ambient Four layer board R 55 °C/W Natural convection (2s2p) JMA Junction to ambient Single layer board R 66 °C/W (@200 ft/min) (1s) JMA Junction to ambient Four layer board R 48 °C/W (@200 ft/min) (2s2p) JMA Junction to board R 34 °C/W JB Junction to case R 20 °C/W JC Junction to package top Natural Convection  4 °C/W JT NOTE Junction-to-ambient thermal resistance determined per JEDEC JESD51–3 and JESD51–6. Thermal test board meets JEDEC specification for this package. Junction-to-board thermal resistance determined per JEDEC JESD51–8. Thermal test board meets JEDEC specification for the specified package. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51–2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. See Section9.1, “Thermal Design Considerations,” for more detail on thermal design considerations. 8.4 Recommended Operating Conditions This section includes information about recommended operating conditions. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 45

Specifications Table19. Recommended Operating Conditions (V = 0 V, V = 0 V, V = 0 V) REFL x SSA SS Characteristic Symbol Notes Min Typ Max Unit Supply voltage V V 3 3.3 3.6 V DD, DDA Voltage difference V to V V –0.1 0 0.1 V DD DDA DD Voltage difference V to V V –0.1 0 0.1 V SS SSA SS Device Clock Frequency FSYSCLK Using relaxation oscillator 1 32 MHz Using external clock source 0 32 Input Voltage High (digital inputs) V Pin Groups 1, 2 2.0 V V IH DD Input Voltage Low (digital inputs) V Pin Groups 1, 2 –0.3 0.8 V IL Oscillator Input Voltage High V Pin Group 4 2.0 V + 0.3 V IHOSC DDA XTAL driven by an external clock source Oscillator Input Voltage Low V Pin Group 4 –0.3 0.8 V ILOSC Output Source Current High at V min.)1 I OH OH When programmed for low drive strength Pin Group 1 — –4 mA When programmed for high drive strength Pin Group 1 — –8 Output Source Current Low (at V max.)1 I OL OL When programmed for low drive strength Pin Groups 1, 2 — 4 mA When programmed for high drive strength Pin Groups 1, 2 — 8 Ambient Operating Temperature (Extended T –40 105 °C A Industrial) Flash Endurance N T = –40°Cto 125°C 10,000 — cycles F A (Program Erase Cycles) Flash Data Retention t T  85°Cavg 15 — years R J Flash Data Retention with <100 t T  85°Cavg 20 — — years FLRET J Program/Erase Cycles 1 Total chip source or sink current cannot exceed 75 mA. Table20. Default Mode Pin Group 1 GPIO, TDI, TDO, TMS, TCK Pin Group 2 SCL, SDA ADC and Comparator Pin Group 3 Analog Inputs and PGA Inputs Pin Group 4 XTAL, EXTAL 8.5 DC Electrical Characteristics This section includes information about power supply requirements and I/O pin characteristics. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 46 Freescale Semiconductor

Specifications Table21. DC Characteristics Ambient temperature Characteristic Symbol Condition Min Typ1 Max Unit operating range Operating Voltage 1.82 3.6 V Output high All I/O pins, V 1.8 V, I = –2 mA V – 0.5 — — V OH Load DD voltage low-drive strength All I/O pins, 2.7 V, I = –10 mA V – 0.5 — — Load DD high-drive strength 2.3 V, I = –6 mA V – 0.5 — — Load DD 1.8 V, I = –3 mA V – 0.5 — — Load DD Output high Max total I for all I — — 100 mA OH OHT current ports Output low All I/O pins, V 1.8 V, I = 2 mA — — 0.5 V OL Load voltage low-drive strength All I/O pins, 2.7 V, I = 10 mA — — 0.5 Load high-drive strength 2.3 V, I = 6 mA — — 0.5 Load 1.8 V, I = 3 mA — — 0.5 Load Output low Max total I for all I — — 100 mA OL OLT current ports Input high all digital inputs V V  2.7 V 0.70 x V — — V IH DD DD voltage V 1.8 V 0.85 x V — — —40C ~ DD DD +125C Input low voltage all digital inputs V V  2.7 V — — 0.35 x V IL DD DD V 1.8 V — — 0.30 x V DD DD Input hysteresis all digital inputs V 0.06 x V — — mV hys DD Input leakage all input only pins |I V = V or V — — 1 A In| In DD SS current (Per pin) Hi-Z (off-state) all input/output |IOZ| VIn = VDD or VSS — — 1 A leakage current (per pin) Pullup resistors all digital inputs, when R 17.5 — 52.5 k PU enabled DC injection Single pin limit I V < V , V > V –0.2 — 0.2 mA IC In SS In DD current 3, 4, 5 Total MCU limit, includes –5 — 5 mA sum of allstressed pins Input Capacitance, all pins C — — 8 pF In RAM retention voltage V — 0.6 1.0 V RAM POR re-arm voltage6 V 0.9 1.4 1.79 V POR POR re-arm time t 10 — — s POR MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 47

Specifications Table21. DC Characteristics (continued) Ambient temperature Characteristic Symbol Condition Min Typ1 Max Unit operating range Low-voltage detection threshold — V 8 V falling 2.31 2.34 2.36 V –40C ~ LVDH DD high range7 105C 2.16 2.3 2.48 —40C ~ +125C V rising 2.38 2.44 2.47 –40C ~ DD 105C 2.23 2.39 2.49 —40C ~ +125C Low-voltage detection threshold — V V falling 1.8 1.84 1.87 V –40C ~ LVDL DD low range7 105C N/A N/A N/A —40C ~ +125C V rising 1.88 1.93 1.96 –40C ~ DD 105C Low-voltage warning threshold V 9 V falling 2.58 2.62 2.71 V –40C ~ LVW DD 105C 2.5 2.61 2.74 —40C ~ +125C V rising 2.59 2.67 2.74 –40C ~ DD 105C 2.51 2.66 2.79 —40C ~ +125C Low-voltage inhibit reset/recover V — 50 — mV —40C ~ hys hysteresis7 +105C Bandgap Voltage Reference10 V 1.15 1.17 1.18 V –40C ~ BG 105C 1.14 —40C ~ +125C 1 Typical values are measured at 25C. Characterized, not tested 2 As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above V . If the system clock LVDL frequency < 16MHz, V can be 1.7V to 3.6V. DD 3 All functional non-supply pins are internally clamped to V and V . SS DD 4 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 5 Power supply must maintain regulation within operating V range during instantaneous and operating maximum current DD conditions. If positive injection current (V > V ) is greater than I , the injection current may flow out of V and could result In DD DD DD in external power supply going out of regulation. Ensure external V load shunts current greater than maximum injection current. DD This is the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present or if clock rate is low (which would reduce overall power consumption). 6 Maximum is highest voltage that POR is guaranteed. 7 Low voltage detection and warning limits measured at 32 MHz bus frequency. This characteristic is not applicable to devices with a temperature range from –40C to 125C. Please see the PMC chapter in the reference manual for details. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 48 Freescale Semiconductor

Specifications 8 Runs at 32 MHz bus frequency. 9 Both Low Voltage Warning (LVW) and Out Of Regulation (OOR) sample the same input source. The OOR flag is a stick bit which is in the PMC_SCR register. 10Factory trimmed at V = 3.3V, Temp = 25C. DD W) (kW) 40 PULLUP RESISTOR TYPICA 8L255SCC CE (k 40 PULLDOWN RESISTOR TYP8IC5ACLS R –40C N 25C O35 A –40C T T 35 S S SI SI E30 E R R 30 P N U W L25 O L 25 U D P L L 20 U 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 P 20 V (V) 1.8 2.3 2.8 3.3 3.6 DD V (V) DD Figure16. Pullup and Pulldown Typical Resistor Values TYPICAL V VS I AT V = 3.0 V TYPICAL V VS V OL OL DD OL DD 1.2 0.2 85C 25C 1 –40C 0.15 0.8 V) V) (L0.6 (L 0.1 O O V0.4 V 0.05 85C, IOL = 2 mA 0.2 25C, I = 2 mA OL –40C, I = 2 mA 0 0 OL 0 5 10 15 20 1 2 3 4 V (V) I (mA) DD OL Figure17. Typical Low-Side Driver (Sink) Characteristics — Low Drive (GPIO_x_DRIVEn = 0) TYPICAL VOL VS IOL AT VDD = 3.0 V TYPICAL VOL VS VDD 1 85C 0.4 85C 25C 25C 0.8 –40C –40C 0.3 V) 0.6 V) (OL 0.4 (OL 0.2 IOL = 10 mA V V IOL = 6 mA 0.1 0.2 I = 3 mA OL 0 0 0 10 20 30 1 2 3 4 V (V) I (mA) DD OL Figure18. Typical Low-Side Driver (Sink) Characteristics — High Drive (GPIO_x_DRIVEn = 1) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 49

Specifications TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V TYPICAL VDD – VOH VS VDD AT SPEC IOH 1.2 0.25 85C 85C, I = 2 mA V) 1 25C V) 25C, IOH = 2 mA (H –40C (H 0.2 –40C, IOOHH = 2 mA O0.8 O V V0.15 – 0.6 – V DD0.4 V DD 0.1 0.2 0.05 0 0 0 –5 –10 –15 –20 1 2 3 4 IOH (mA)) VDD (V) Figure19. Typical High-Side (Source) Characteristics — Low Drive (GPIO_x_DRIVEn = 0) TYPICAL V – V VS V AT SPEC I DD OH DD OH 0.4 85C 25C V) 0.8 85TCYPICAL VDD – VOH VS IOH AT VDD = 3.0 V (V) 0.3 –40C (OH0.6 – 2450CC V OH 0.2 IOH = –10 mA – VD0.4 – DD 0.1 IOH = –6 mA D0.2 V I = –3 mA V OH 0 0 0 –5 –10 –15 –20 –25 –30 1 2 3 4 I (mA) OH V (V) DD Figure20. Typical High-Side (Source) Characteristics — High Drive (GPIO_x_DRIVEn = 1) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 50 Freescale Semiconductor

Specifications 8.6 Supply Current Characteristics Table22. Supply Current Consumption Typical @ 3.3 V, Maximum @ 3.6 V, Maximum @ 3.6V, 25°C 105°C 125°C Mode Conditions I 1 I I 1 I I 1 I DD DDA DD DDA DD DDA Run 32 MHz device clock; 41.52mA 1.71mA 53 mA 2.7 mA 53 mA 2.9 mA relaxation oscillator (ROSC) in high speed mode; PLL engaged; All peripheral modules enabled. TMR and PWM using 1X clock; continuous MAC instructions with fetches from program flash; ADC/DAC powered on and clocked; comparator powered on. LSrun 2 200 kHz device clock; 340.75 A 1.70 mA 480 A 2.5 mA 495 A 2.6 mA relaxation oscillator (ROSC) in standby mode; PLL disabled All peripheral modules disabled and clock gated off; simple loop with fetches from program flash; LPrun 3 32.768 kHz device clock; 166.30 A 1.74 mA 390 A 3.4 mA 399 A 3.8 mA Clocked by a 32.768 kHz external crystal relaxation oscillator (ROSC) in power down; PLL disabled All peripheral modules disabled and clock gated off; simple loop with fetches from program flash; Wait 32 MHz device clock 19.3mA 1.78mA 28 mA 2.7 mA 28 mA 2.8 mA relaxation oscillator (ROSC) in high speed mode PLL engaged; All non-communication peripherals enabled and running; all communication peripherals disabled but clocked; processor core in wait state LSwait 2 200 kHz device clock; 265.42 A 1.70 mA 380 A 2.5 mA 398 A 2.6 mA relaxation oscillator (ROSC) in standby mode; PLL disabled; All peripheral modules disabled and clock gated off; processor core in wait state MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 51

Specifications Table22. Supply Current Consumption (continued) Typical @ 3.3 V, Maximum @ 3.6 V, Maximum @ 3.6V, 25°C 105°C 125°C Mode Conditions I 1 I I 1 I I 1 I DD DDA DD DDA DD DDA LPwait 3 32.768 kHz device clock; 157.55 A 1.57 mA 380 A 3.4 mA 398 A 3.6 mA Clocked by a 32.768 kHz external crystal oscillator in power down; PLL disabled; All peripheral modules disabled and clock gated off; processor core in wait state Stop 32 MHz device clock 8.21mA 65.51 A 9.8 mA 130 A 10.3 mA 132A relaxation oscillator (ROSC) in high speed mode; PLL engaged; all peripheral module and core clocks are off; ADC/DAC/comparator powered off; processor core in stop state LSstop 2 200 kHz device clock; 194.69 A 65.51 A 340 A 120 A 357 A 123 A relaxation oscillator (ROSC) in standby mode; PLL disabled; all peripheral modules disabled and clock gated off; processor core in stop state. LPstop 2 32.768 kHz device clock; 2.77 A 13.99 nA 45 A 3.0 A 58 A 3.6 A Clocked by a 32.768 kHz external crystal relaxation oscillator (ROSC) in power down; PLL disabled; all peripheral modules disabled and clock gated off; processor core in stop state. PPD 4 with 32.768 kHz clock fed on XTAL 879.72 nA 11.56 nA 18 A 2.4 A 22 A 3.0 A XOSC RTC or COP monitoring XOSC (but no wakeup) processor core in stop state PPD with LP RTC or COP monitoring LP oscillator (but no 499.15 nA 13.9 nA 14 A 2.4 A 17 A 2.8 mA oscillator wakeup); (1kHz) processor core in stop state. enabled PPD with no RTC and LP oscillator are disabled; 494.04 nA 12.88 nA 14 A 2.4 A 17 A 2.8 A clock processor core in stop state. monitoring 1 No output switching; all ports configured as inputs; all inputs low; no DC loads. 2 Low speed mode: LPR (lower voltage regulator control bit) = 0 and voltage regulator is in full regulation. Characterization only. 3 Low power mode: LPR (lower voltage regulator control bit) = 1; the voltage regulator is put into standby. 4 Partial power down mode: PPDE (partial power down enable bit) = 1; power management controller (PMC) enters partial power down mode the next time that the STOP command is executed. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 52 Freescale Semiconductor

Specifications 8.7 Flash Memory Characteristics Table23. Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time1 tprog 20 — 40 s Erase time 2 terase 20 — — ms Mass erase time tme 100 — — ms 1 There is additional overhead that is part of the programming sequence. See the MC56F8006 Peripheral Reference Manual for detail. 2 Specifies page erase time. There are 512 bytes per page in the program flash memory. 8.8 External Clock Operation Timing Table24. External Clock Operation Timing Requirements1 Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)2 f — — 64 MHz osc Clock pulse width3 t 6.25 — — ns PW External clock input rise time4 t — — 3 ns rise External clock input fall time5 t — — 3 ns fall Input high voltage overdrive by an external clock V 0.85V — — V ih DD Input high voltage overdrive by an external clock V — — 0.3V V il DD 1 Parameters listed are guaranteed by design. 2 See Figure21 for detail on using the recommended connection of an external clock driver. 3 The chip may not function if the high or low pulse width is smaller than 6.25ns. 4 External clock input rise time is measured from 10% to 90%. 5 External clock input fall time is measured from 90% to 10%. V IH External 90% 90% 50% 50% Clock 10% 10% tfall trise VIL tPW tPW Note: The midpoint is V + (V – V )/2. IL IH IL Figure21. External Clock Timing MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 53

Specifications 8.9 Phase Locked Loop Timing Table25. Phase Locked Loop Timing Characteristic Symbol Min Typ Max Unit PLL input reference frequency1 f 4 8 — MHz ref PLL output frequency2 f 120 192 — MHz op PLL lock time3 4 t — 40 100 µs plls Accumulated jitter using an 8 MHz external crystal as the PLL source5 J — — 0.37 % A Cycle-to-cycle jitter t — 350 — ps jitterpll 1 An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8 MHz input. 2 The core system clock operates at 1/6 of the PLL output frequency. 3 This is the time required after the PLL is enabled to ensure reliable operation. 4 From powerdown to powerup state at 32 MHz system clock state. 5 This is measured on the CLKO signal (programmed as system clock) over 264 system clocks at 32 MHz system clock frequency and using an 8 MHz oscillator frequency. 8.10 Relaxation Oscillator Timing Table26. Relaxation Oscillator Timing Characteristic Symbol Minimum Typical Maximum Unit Relaxation oscillator output frequency1 f — — op Normal Mode 8.05 MHz Standby Mode 400 kHz Relaxation oscillator stabilization time2 t — 1 3 ms roscs Cycle-to-cycle jitter. This is measured on the CLKO signal t — 400 — ps jitterrosc (programmed prescaler_clock) over 264 clocks3 Variation over temperature –40C to 105C4 — — –3.0 to +2.0 % Variation over temperature 0C to 105C5 — — –2.0 to +2.0 % Variation over temperature –40C to 125C4 — — –3.5 to +3.0 % 1 Output frequency after factory trim. 2 This is the time required from standby to normal mode transition. 3 J is required to meet QSCI requirements. A 4 See Figure22. The power supply VDD must be greater than or equal to 2.6V. Below 2.6V, the maximum variation over the whole temperature and whole voltage range from 1.8V to 2.6V will be +/-16%. 5 This data is only applied to devices with temperature range from –40C to 105C. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 54 Freescale Semiconductor

Specifications z H M Degrees C (Junction) Figure22. Relaxation Oscillator Temperature Variation (Typical) After Trim for devices with temperature operating range from –40C to 105C Figure23. Relaxation Oscillator Temperature Variation (Typical) After Trim for devices with temperature operating range from –40C to 125C MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 55

Specifications 8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing NOTE All address and data buses described here are internal. Table27. Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 Characteristic Symbol Typical Min Typical Max Unit See Figure Minimum RESET Assertion Duration t 4T — ns — RA Minimum GPIO pin Assertion for Interrupt t 2T — ns Figure24 IW RESET deassertion to First Address Fetch t 96T + 64T 97T + 65T ns — RDA OSC OSC Delay from Interrupt Assertion to Fetch of first t — 6T ns — IF instruction (exiting Stop) 1 In the formulas, T = system clock cycle and T = oscillator clock cycle. For an operating frequency of 32 MHz, T=31.25 ns. osc At 4 MHz (used coming out of reset and stop modes), T = 250 ns. 2 Parameters listed are guaranteed by design. GPIO pin (Input) t IW Figure24. GPIO Interrupt Timing (Negative Edge-Sensitive) 8.12 External Oscillator (XOSC) Characteristics Reference Figure10, and Figure11, and Figure12 for crystal or resonator circuits. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 56 Freescale Semiconductor

Specifications Table28. Crystal Oscillator Characteristics Characteristic Symbol Min Typ1 Max Unit Oscillator crystal or resonator (PRECS = 1, CLK_MOD = 0) Low range (RANGE = 0) f 32 — 38.4 kHz lo High range (RANGE = 1), high gain (COHL =0) f 1 — 16 MHz hi High range (RANGE = 1), low power (COHL =1) f 1 — 8 MHz hi Load capacitors C C See Note2 1, 2 Low range (RANGE=0), low power (COHL =1) See Note3 Other oscillator settings Feedback resistor R M F Low range, low power (RANGE=0, COHL =1)2 — — — Low range, high gain (RANGE=0, COHL =0) — 10 — High range (RANGE=1, COHL=X) — 1 — Series resistor R S Low range, low power (RANGE = 0, COHL =1)2 — 0 — k Low range, high gain (RANGE = 0, COHL =0) — 100 — High range, low power (RANGE = 1, COHL =1) — 0 — High range, high gain (RANGE = 1,COHL =0)  8 MHz — 0 0 4 MHz — 0 10 1 MHz — 0 20 Crystal start-up time 4 Low range, low power t — TBD — ms CSTL Low range, high gain — TBD — High range, low power t — TBD — CSTH High range, high gain — TBD — Square wave input clock frequency (PRECS = 1, CLK_MOD = 1) f — — 50.0 MHz xtal 1 Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. 2 Load capacitors (C ,C ), feedback resistor (R ) and series resistor (R ) are incorporated internally when 1 2 F S RANGE=HGO=0. 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. 8.13 AC Electrical Characteristics Tests are conducted using the input levels specified in Table22. Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure25. Low High V IH 90% 50% Input Signal Midpoint1 10% V Fall Time IL Rise Time The midpoint is V + (V – V )/2. IL IH IL Figure25. Input Signal Measurement References Figure26 shows the definitions of the following signal states: • Active state, when a bus or signal is driven, and enters a low impedance state MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 57

Specifications • Tri-stated, when a bus or signal is placed in a high impedance state • Data Valid state, when a signal level has reached V or V OL OH • Data Invalid state, when a signal level is in transition between V and V OL OH Data1 Valid Data2 Valid Data3 Valid Data1 Data2 Data3 Data Data Invalid State Three-stated Data Active Data Active Figure26. Signal States 8.13.1 Serial Peripheral Interface (SPI) Timing Table29. SPI Timing1 Characteristic Symbol Min Max Unit See Figure Cycle time t Figure27, C Master 125 — ns Figure28, Slave 62.5 — ns Figure29, Figure30 Enable lead time t Figure30 ELD Master — — ns Slave 31 — ns Enable lag time t Figure30 ELG Master — — ns Slave 125 — ns Clock (SCK) high time t Figure27, CH Master 50 — ns Figure28, Slave 31 — ns Figure29, Figure30 Clock (SCK) low time t Figure30 CL Master 50 — ns Slave 31 — ns Data set-up time required for inputs t Figure27, DS Master 20 — ns Figure28, Slave 0 — ns Figure29, Figure30 Data hold time required for inputs t Figure27, DH Master 0 — ns Figure28, Slave 2 — ns Figure29, Figure30 Access time (time to data active from high-impedance t Figure30 A state) 4.8 15 ns Slave Disable time (hold time to high-impedance state) t Figure30 D Slave 3.7 15.2 ns MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 58 Freescale Semiconductor

Specifications Table29. SPI Timing1 (continued) Characteristic Symbol Min Max Unit See Figure Data valid for outputs t Figure27, DV Master — 4.5 ns Figure28, Slave (after enable edge) — 20.4 ns Figure29, Figure30 Data invalid t Figure27, DI Master 0 — ns Figure28, Slave 0 — ns Figure29, Figure30 Rise time t Figure27, R Master — 11.5 ns Figure28, Slave — 10.0 ns Figure29, Figure30 Fall time t Figure27, F Master — 9.7 ns Figure28, Slave — 9.0 ns Figure29, Figure30 1 Parameters listed are guaranteed by design. SS SS is held high on master (Input) t C t R t F t SCLK (CPOL = 0) CL (Output) t CH t F t R t CL SCLK (CPOL = 1) (Output) tDH tCH t DS MISO MSB in Bits 14–1 LSB in (Input) tDI tDV tDI(ref) MOSI Master MSB out Bits 14–1 Master LSB out (Output) t t F R Figure27. SPI Master Timing (CPHA = 0) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 59

Specifications SS SS is held High on master (Input) t C t F t R t CL SCLK (CPOL = 0) (Output) t CH t F t CL SCLK (CPOL = 1) (Output) t CH t DS tR tDH MISO MSB in Bits 14–1 LSB in (Input) tDV(ref) tDI tDV tDI(ref) MOSI Master MSB out Bits 14– 1 Master LSB out (Output) t t F R Figure28. SPI Master Timing (CPHA = 1) SS (Input) t C t F t ELG t CL t R SCLK (CPOL = 0) (Input) t CH t ELD t CL SCLK (CPOL = 1) (Input) tA tCH tR tF t D MISO Slave MSB out Bits 14–1 Slave LSB out (Output) tDS tDV t t DI DI t DH MOSI MSB in Bits 14–1 LSB in (Input) Figure29. SPI Slave Timing (CPHA = 0) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 60 Freescale Semiconductor

Specifications SS (Input) t t F C t R t SCLK (CPOL = 0) CL (Input) t CH t ELG t ELD t CL SCLK (CPOL = 1) (Input) tDV tCH t R tA tF tD MISO Slave MSB out Bits 14–1 Slave LSB out (Output) t t DS DV t DI t DH MOSI MSB in Bits 14–1 LSB in (Input) Figure30. SPI Slave Timing (CPHA = 1) 8.13.2 Serial Communication Interface (SCI) Timing Table30. SCI Timing1 Characteristic Symbol Min Max Unit See Figure Baud rate2 BR — (f /16) Mbps — MAX RXD pulse width RXD 0.965/BR 1.04/BR ns Figure31 PW TXD pulse width TXD 0.965/BR 1.04/BR ns Figure32 PW LIN Slave Mode Deviation of slave node clock from F –14 14 % — TOL_UNSYNCH nominal clock rate before synchronization Deviation of slave node clock relative to F –2 2 % — TOL_SYNCH the master node clock after synchronization Minimum break character length T 13 — Master node — BREAK bit periods 11 — Slave node — bit periods 1 Parameters listed are guaranteed by design. 2 f is the frequency of operation of the SCI in MHz, which can be selected system clock (max. 32 MHz) or 3x system clock MAX (max. 96 MHz) for the 56F8006/56F8002 device. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 61

Specifications RXD SCI receive data pin (Input) RXDPW Figure31. RXD Pulse Width TXD SCI receive data pin TXD (Input) PW Figure32. TXD Pulse Width 2 8.13.3 Inter-Integrated Circuit Interface (I C) Timing Table31. I2C Timing Standard Mode Characteristic Symbol Unit Minimum Maximum SCL Clock Frequency f 0 100 MHz SCL Hold time (repeated) START condition. t 4.0 — s HD; STA After this period, the first clock pulse is generated. LOW period of the SCL clock t 4.7 — s LOW HIGH period of the SCL clock t 4.0 — s HIGH Set-up time for a repeated START condition t 4.7 — s SU; STA Data hold time for I2C bus devices t 01 3.452 s HD; DAT Data set-up time t 250 — ns SU; DAT Rise time of SDA and SCL signals t — 1000 ns r Fall time of SDA and SCL signals t — 300 ns f Set-up time for STOP condition t 4.0 — s SU; STO Bus free time between STOP and START condition t 4.7 — s BUF Pulse width of spikes that must be suppressed by the input filter t N/A N/A ns SP 1 The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2 The maximum t must be met only if the device does not stretch the LOW period (t ) of the SCL signal. HD; DAT LOW MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 62 Freescale Semiconductor

Specifications SDA tSU; DAT tf tf tLOW tr tHD; STA tSP tr tBUF SCL tHD; STA tSU; STA tSU; STO S t t SR P S HD; DAT HIGH Figure33. Timing Definition for Standard Mode Devices on the I2C Bus 8.13.4 JTAG Timing Table32. JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK frequency of operation1 fOP DC SYS_CLK/8 MHz Figure34 TCK clock pulse width t 50 — ns Figure34 PW TMS, TDI data set-up time t 5 — ns Figure35 DS TMS, TDI data hold time t 5 — ns Figure35 DH TCK low to TDO data valid t — 30 ns Figure35 DV TCK low to TDO tri-state t — 30 ns Figure35 TS 1 TCK frequency of operation must be less than 1/8 the processor rate. 1/f OP tPW tPW V IH V V TCK M M (Input) V IL V = V + (V – V )/2 M IL IH IL Figure34. Test Clock Input Timing Diagram MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 63

Specifications TCK (Input) t t DS DH TDI TMS Input Data Valid (Input) t DV TDO Output Data Valid (Output) t TS TDO (Output) Figure35. Test Access Port Timing Diagram 8.13.5 Dual Timer Timing Table33. Timer Timing1, 2 Characteristic Symbol Min Max Unit See Figure Timer input period P 2T + 6 — ns Figure36 IN Timer input high/low period P 1T + 3 — ns Figure36 INHL Timer output period P 125 — ns Figure36 OUT Timer output high/low period P 50 — ns Figure36 OUTHL 1 In the formulas listed, T = the clock cycle. For 32 MHz operation, T = 31.25ns. 2.Parameters listed are guaranteed by design. Timer Inputs P P P INHL INHL IN Timer Outputs POUT POUTHL POUTHL Figure36. Timer Timing MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 64 Freescale Semiconductor

Specifications 8.14 COP Specifications Table34. COP Specifications Parameter Symbol Min Typ Max Unit Oscillator output frequency LPFosc 500 1000 1500 Hz Oscillator current consumption in partial power down mode IDD TBD nA 8.15 PGA Specifications Table35. PGA Specifications Parameter Symbol Min Max Unit Digital logic inputs amplitude (_2p5 signal) V 2.75 V 2p5 DC analog input level (@ V = avdd3p3) V 0 V DD IL PGA S/H stage enabled (BP=0) V DD PGA S/H stage disabled (BP=1) V – 0.5 DD Max differential input voltage (@ Gain and V = avdd3p3) V (V – 1) x 0.5/gain V DD DIFFMAX DD Linearity (@ voltage gain) 1x 1 – 1/2 LSB 1 + 1/2 LSB 2x 2 – 1/2 LSB 2 + 1/2 LSB 4x L 4 – 1 LSB 4 + 1 LSB V/V V 8x 8 – 1 LSB 8 + 1 LSB 16x 16 – 4 LSB 16 + 4 LSB 32x 32 – 4 LSB 32 + 4 LSB Gain error (@ voltage gain) 1x 2x 4x A 1% V/V V 8x 16x 32x Sampling frequency (pga_clk_2p5) normal mode (pga_lp_2p5 asserted) SF 8 max low power mode (pga_lp_2p5 negated) 4 MHz Input signal bandwidth Motor Control mode (BP=0) BW PGA sampling rate/2 Hz max General Purpose mode (BP=1) PGA sampling rate/8 Internal voltage doubler clock frequency(pga_clk_doubler_2p5) VD 100 2000 kHz clk Operating temperature T –40 125 oC MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 65

Specifications 8.16 ADC Specifications Table36. ADC Operating Conditions Characteristic Conditions Symb Min Typ1 Max Unit Comment Input voltage V V 2 — V 3 V ADIN REFL REFH Input C — 4.5 5.5 pF ADIN capacitance Input resistance R — 5 7 k ADIN Analog source 12-bit mode R k External to MCU AS resistance f > 4 MHz — — 2 ADCK f < 4 MHz — — 5 ADCK 10-bit mode f > 4 MHz — — 5 ADCK f < 4 MHz — — 10 ADCK 8-bit mode (all valid f ) — — 10 ADCK ADC conversion High speed (ADLPC=0) f 0.4 — 8.0 MHz ADCK clock freq. Low power (ADLPC=1) 0.4 — 4.0 1 Typical values assume V = 3.0 V, Temp = 25C, f = 1.0 MHz unless otherwise stated. Typical values are for DDAD ADCK reference only and are not tested in production. 2 V = V REFL SSA 3 V = V REFH DDA Simplified Input Pin Equivalent Circuit ZADIN Simplified Z Pad Channel Select AS leakage Circuit due to ADC SAR R input R Engine AS protection ADIN + V ADIN – C VAS + AS – R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure37. ADC Input Impedance Equivalency Diagram MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 66 Freescale Semiconductor

Specifications Table37. ADC Characteristics (V = V , V = V ) REFH DDA REFL SSA Characteristic Conditions Symb Min Typ1 Max Unit Comment Supply current I — 120 — A DDAD ADLPC=1 ADLSMP=1 ADCO=1 Supply current I — 202 — A DDAD ADLPC=1 ADLSMP=0 ADCO=1 Supply current I — 288 — A DDAD ADLPC=0 ADLSMP=1 ADCO=1 Supply current I — 0.532 1 mA DDAD ADLPC=0 ADLSMP=0 ADCO=1 ADC High speed (ADLPC=0) f 2 3.3 5 MHz t = ADACK ADACK asynchronous 1/f Low power (ADLPC=1) 1.25 2 3.3 ADACK clock source Conversion time Short sample (ADLSMP=0) t — 20 — ADCK ADC (including cycles Long sample (ADLSMP=1) — 40 — sample time) Sample time Short sample (ADLSMP=0) t — 3.5 — ADCK ADS cycles Long sample (ADLSMP=1) — 23.5 — Differential 12-bit mode DNL — 1.75 — LSB2 Non-linearity 10-bit mode3 — 0.5 1.0 8-bit mode3 — 0.3 0.5 Integral 12-bit mode INL — 1.5 — LSB2 non-linearity 10-bit mode — 0.5 1.0 8-bit mode — 0.3 0.5 Quantization 12-bit mode E — –1 to 0 — LSB2 Q error 10-bit mode — — 0.5 8-bit mode — — 0.5 Input leakage 12-bit mode E — 2 — LSB2 Pad leakage4 * IL error R 10-bit mode — 0.2 4 AS 8-bit mode — 0.1 1.2 Temp sensor –40C–25C m — 1.646 — mV/C slope 25C–125C — 1.769 — Temp sensor 25C V — 701.2 — mV TEMP25 voltage MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 67

Specifications 1 Typical values assume V = 3.0 V, Temp = 25C, f =1.0 MHz unless otherwise stated. Typical values are for DDA ADCK reference only and are not tested in production. 2 1 LSB = (V – V )/2N REFH REFL 3 Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 4 Based on input pad leakage current. Refer to pad electricals. 8.17 HSCMP Specifications Table38. HSCMP Specifications Parameter Symbol Min Typ Max Unit Supply voltage V 1.8 3.6 V PWR Supply current, high speed mode (EN=1, I 150 A DDAHS PMODE=1, V  V ) DDA LVI_trip Supply current, low speed mode (EN=1, I 10 A DDALS PMODE=0) Supply current, off mode (EN=0,) I 100 nA DDAOFF Analog input voltage V V – 0.01 V + 0.01 V AIN SSA DDA Analog input offset voltage V 40 mV AIO Analog comparator hysteresis V 3.0 20.0 mV H Propagation Delay, high speed mode (EN=1, t 1 70 140 ns DHSN PMODE=1), 2.4V < V < 3.6V DDA Propagation Delay, High Speed Mode (EN=1, t 2 70 249 ns DHSB PMODE=1), 1.8V < V < 2.4V DDA Propagation Delay, Low Speed Mode (EN=1, t 3 400 600 ns AINIT PMODE=0), 2.4V < V < 3.6V DDA Propagation Delay, Low Speed Mode (EN=1, t 4 400 600 ns AINIT PMODE=0), 1.8V < V < 2.4V DDA 1 Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. V > DDA V => LVI_WARNING NOT ASSERTED. LVI_WARNING 2 Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. V < DDA V => LVI_WARNING ASSERTED. LVI_WARNING 3 Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. V > DDA V => LVI_WARNING NOT ASSERTED. LVI_WARNING 4 Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. V < DDA V => LVI_WARNING ASSERTED. LVI_WARNING 8.18 Optimize Power Consumption See Section8.6, “Supply Current Characteristics,” for a list of I requirements for the 56F8006/56F8002. This section DD provides additional detail that can be used to optimize power consumption for a given application. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 68 Freescale Semiconductor

Specifications Power consumption is given by the following equation: Eqn.1 Total power = A: internal [static component] +B: internal [state-dependent component] +C: internal [dynamic component] +D: external [dynamic component] +E: external [static component] A, the internal [static] component, is comprised of the DC bias currents for the oscillator, leakage currents, PLL, and voltage references. These sources operate independently of processor state or operating frequency. B, the internal [state-dependent] component, reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, flash memory, and the ADCs. C, the internal [dynamic] component, is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic. D, the external [dynamic] component, reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two of the I/O cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero Y-intercept. Table39. I/O Loading Coefficients at 10 MHz Intercept Slope 8 mA drive 1.3 0.11 mW/pF 4 mA drive 1.15 mW 0.11 mW/pF Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. Table39 provides coefficients for calculating power dissipated in the I/O cells as a function of capacitive load. In these cases: TotalPower = ((Intercept + Slope*Cload)*frequency/10 MHz) Eqn.2 where: • Summation is performed over all output pins with capacitive loads • Total power is expressed in mW • C is expressed in pF load Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V=0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving 10 mA into LEDs, then P = 8*0.5*0.01 = 40 mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 69

Design Considerations 9 Design Considerations 9.1 Thermal Design Considerations An estimation of the chip junction temperature, T , can be obtained from the equation: J T = T + (R x P ) Eqn.3 J A J D where: T = Ambient temperature for the package (oC) A R = Junction-to-ambient thermal resistance (oC/W) J P = Power dissipation in the package (W) D The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: R = R + R Eqn.4 JA JC CA where: R = Package junction-to-ambient thermal resistance (°C/W) JA R = Package junction-to-case thermal resistance (°C/W) JC R = Package case-to-ambient thermal resistance (°C/W) CA RJC is device related and cannot be adjusted. You control the thermal environment to change the case to ambient thermal resistance, R . For instance, you can change the size of the heat sink, the air flow around the device, the interface material, CA the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at the top center of JT the package case using the following equation: T = T + ( x P ) Eqn.5 J T JT D where: T = Thermocouple temperature on top of package (oC) T  = Thermal characterization parameter (oC/W) JT P = Power dissipation in package (W) D The thermal characterization parameter is measured per JESD51–2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 70 Freescale Semiconductor

Design Considerations junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. 9.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct operation of the 56F8006/56F8002: • Provide a low-impedance path from the board power supply to each V pin on the 56F8006/56F8002 and from the DD board ground to each V (GND) pin. SS • The minimum bypass requirement is to place 0.01–0.1µF capacitors positioned as near as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the V /V pairs, DD SS including V /V Ceramic and tantalum capacitors tend to provide better tolerances. DDA SSA. • Ensure that capacitor leads and associated printed circuit traces that connect to the chip V and V (GND)pins are DD SS as short as possible. • Bypass the V and V with approximately 100 µF, plus the number of 0.1 µF ceramic capacitors. DD SS • PCB trace lengths should be minimal for high-frequency signals. • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V and DD V circuits. SS • Take special care to minimize noise levels on the V , V , and V pins. REF DDA SSA • Using separate power planes for V and V and separate ground planes for V and V are recommended. DD DDA SS SSA Connect the separate analog and digital power and ground planes as near as possible to power supply outputs. If an analog circuit and digital circuit are powered by the same power supply, you should connect a small inductor or ferrite bead in serial with V and V traces. DDA SSA • Physically separate analog components from noisy digital components by ground planes. Do not place an analog trace in parallel with digital traces. Place an analog ground trace around an analog signal trace to isolate it from digital traces. • Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI, or I2C, the designer should provide an interface to this port if in-circuit flash programming is desired. • If desired, connect an external RC circuit to the RESET pin. The resistor value should be in the range of 4.7 k–10k; the capacitor value should be in the range of 0.22 µF–4.7 µF. • Configuring the RESET pin to GPIO output in normal operation in a high-noise environment may help to improve the performance of noise transient immunity. • Add a 2.2 k external pullup on the TMS pin of the JTAG port to keep EOnCE in a restate during normal operation if JTAG converter is not present. • During reset and after reset but before I/O initialization, all I/O pins are at input state with internal pullup enabled. The typical value of internal pullup is around 33 k. These internal pullups can be disabled by software. • To eliminate PCB trace impedance effect, each ADC input should have a no less than 33 pF 10  RC filter. • External clamp diodes on analog input pins are recommended. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 71

Design Considerations 9.3 Ordering Information Table40 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order devices. Table40. 56F8006/56F8002 Ordering Information Ambient Supply Pin Frequency Device Package Type Temperature Order Number Voltage Count (MHz) Range MC56F8002 1.8–3.6 V Small Outline IC (SOIC) 28 32 –40° to + 105° C MC56F8002VWL –40° to + 125° C MC56F8002MWL1 MC56F8006 1.8–3.6 V Small Outline IC (SOIC) 28 32 –40° to + 105° C MC56F8006VWL –40° to + 125° C MC56F8006MWL1 MC56F8006 1.8–3.6 V Low-Profile Quad Flat Pack 32 32 –40° to + 105° C MC56F8006VLC (LQFP) –40° to + 125° C MC56F8006MLC1 MC56F8006 1.8–3.6 V Low-Profile Quad Flat Pack 48 32 –40° to + 105° C MC56F8006VLF (LQFP) –40° to + 125° C MC56F8006MLF1 MC56F8006 1.8–3.6 V Plastic Shrink Dual In-line 32 32 –40° to + 105° C MC56F8006VBM Package (PSDIP) 1 This package is RoHS compliant. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 72 Freescale Semiconductor

Package Mechanical Outline Drawings 10 Package Mechanical Outline Drawings 10.1 28-pin SOIC Package MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 73

Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 74 Freescale Semiconductor

Package Mechanical Outline Drawings Figure38. 56F8006/56F8002 28-Pin SOIC Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 75

Package Mechanical Outline Drawings 10.2 32-pin LQFP MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 76 Freescale Semiconductor

Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 77

Package Mechanical Outline Drawings Figure39. 56F8006/56F8002 32-Pin LQFP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 78 Freescale Semiconductor

Package Mechanical Outline Drawings 10.3 48-pin LQFP MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 79

Package Mechanical Outline Drawings Figure40. 56F8006/56F8002 48-Pin LQFP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 80 Freescale Semiconductor

Package Mechanical Outline Drawings 10.4 32-Pin PSDIP MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 81

Package Mechanical Outline Drawings Figure41. 56F8006/56F8002 32-Pin PSDIP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 82 Freescale Semiconductor

Revision History 11 Revision History Table41 lists major changes between versions of the MC56F8006 document. Table41. Changes Between Revisions 2 and 3 Location Description Introduction onpage1 Added part marking for devices covered by this document Section6.7, “PWM, PDB, PGA, and ADC Updated routing details for ANB24 and ANB25 Connections,” onpage38 Table12 onpage42 Removed row about open drain mode (GPIO supports only push-pull mode) Table21 onpage47 Updated specifications for low-voltage detection threshold (high and low range) and low-voltage warning threshold Table22 onpage51 Updated all Supply Current Consumption specifications Table26 and Figure22 onpage55 Updated ROSC variation over temperature specifications (both ranges) Table31 onpage62 Removed I2C fast mode specifications and footnote about setup time if the TX FIFO is empty (fast mode and FIFO not supported) Appendix B onpage86 Added note explaining ADC and GPIO naming conventions Table44 onpage86 For I2C_SMB_CSR, clarified that bits 7 and 6 are reserved Table42. Changes Between Revisions 3 and 4 Location Description Throughout document. Added information for 32-pin PSDIP device and devices with temperature range from –40C to + 125C. Appendix A Interrupt Vector Table Table43 provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts are serviced before level 2 and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the vector base address (VBA). Please see the MC56F8006 Peripheral Reference Manual for detail. By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 83

Interrupt Vector Table Table43. Interrupt Vector Table Contents1 Vector User Priority Vector Base Peripheral Interrupt Function Number Encoding Level Address + Core P:0x00 Reserved for Reset Overlay2 Core P:0x02 Reserved for COP Reset Overlay Core 2 N/A 3 P:0x04 Illegal Instruction Core 3 N/A 3 P:0x06 HW Stack Overflow Core 4 N/A 3 P:0x08 Misaligned Long Word Access Core 5 N/A 3 P:0x0A EOnCE Step Counter Core 6 N/A 3 P:0x0C EOnCE Breakpoint Unit Core 7 N/A 3 P:0x0E EOnCE Trace Buffer Core 9 N/A 3 P:0x10 EOnCE Transmit Register Empty Core 9 N/A 3 P:0x12 EOnCE Receive Register Full PMC 10 0x0A 0 P:0x14 Low-Voltage Detector PLL 11 0x0B 0 P:0x16 Phase-Locked Loop Loss of Locks and Loss of Clock ADCA 12 0x0C 0 P:0x18 ADCA Conversion Complete ADCB 13 0x0D 0 P:0x1A ADCB Conversion Complete PWM 14 0x0E 0 P:0x1C Reload PWM and/or PWM Faults CMP0 15 0x0F 0 P:0x1E Comparator 0 Rising/Falling Flag CMP1 16 0x10 0 P:0x20 Comparator 1 Rising/Falling Flag CMP2 17 0x11 0 P:0x22 Comparator 2 Rising/Falling Flag FM 18 0x12 0 P:0x24 Flash Memory Access Status SPI 19 0x13 0 P:0x26 SPI Receiver Full SPI 20 0x14 0 P:0x28 SPI Transmitter Empty SCI 21 0x15 0 P:0x2A SCI Transmitter Empty/Idle SCI 22 0x16 0 P:0x2C SCI Receiver Full/Overrun/Errors I2C 23 0x17 0 P:0x2E I2C Interrupt PIT 24 0x18 0 P:0x30 Interval Timer Interrupt TMR0 25 0x19 0 P:0x32 Dual Timer, Channel 0 Interrupt TMR1 26 0x1A 0 P:0x34 Dual Timer, Channel 1 Interrupt GPIOA 27 0x1B 0 P:0x36 GPIOA Interrupt GPIOB 28 0x1C 0 P:0x38 GPIOB Interrupt GPIOC 29 0x1D 0 P:0x3A GPIOC Interrupt GPIOD 30 0x1E 0 P:0x3C GPIOD Interrupt GPIOE 29 0x1F 0 P:0x3E GPIOE Interrupt GPIOF 30 0x20 0 P:0x40 GPIOF Interrupt RTC 33 0x21 0 P:0x42 Real Time Clock MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 84 Freescale Semiconductor

Interrupt Vector Table Table43. Interrupt Vector Table Contents1 (continued) Vector User Priority Vector Base Peripheral Interrupt Function Number Encoding Level Address + Reserved 34- 39 0x22-0x27 0 P:0x44 - Reserved P:0x4E core 40 N/A 0 P:0x50 SW Interrupt 0 core 41 N/A 1 P:0x52 SW Interrupt 1 core 42 N/A 2 P:0x54 SW Interrupt 2 core 43 N/A 3 P:0x56 SW Interrupt 3 SWILP 44 N/A -1 P:0x58 SW Interrupt Low Priority USER1 45 N/A 1 P:0x5A User Programmable Priority Level 1 Interrupt USER2 46 N/A 1 P:0x5C User Programmable Priority Level 1 Interrupt USER3 47 N/A 1 P:0x5E User Programmable Priority Level 1 Interrupt USER4 48 N/A 2 P:0x60 User Programmable Priority Level 2 Interrupt USER5 49 N/A 2 P:0x62 User Programmable Priority Level 2 Interrupt USER6 3 50 N/A 2 P:0x64 User Programmable Priority Level 2 Interrupt 1 Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2 If the VBA is set to the reset value, the first two locations of the vector table overlay the chip reset addresses because the reset address would match the base of this vector table. 3 USER6 vector can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 85

F Appendix B re e s Peripheral Register Memory Map and Reset Value c a le S e NOTE m ic In Table44, ADC0 stands for ADCA, ADC1 stands for ADCB, and GPIOn is the same as GPIO_n (for example, o nd GPIOA_PUR is the same as GPIO_A_PUR). u c to Table44. Detailed Peripheral Memory Map r Offset Reset Bit Bit Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 M 15 0 C (Hex) (Hex) 5 6 F TMR0_ 8 00 0000 TMR0 COMPARISON_1 0 COMP1 0 6 /M TMR0_ C 01 0000 TMR0 COMPARISON_2 5 COMP2 6 F 8 TMR0_ 002 02 0000 TMR0 CAPT CAPTURE D ig TMR0_ ita 03 0000 TMR0 LOAD LOAD l S ig TMR0_ n 04 0000 TMR0 HOLD a HOLD l C Pe on 05 0000 TMR0 TMR0_ COUNTER rip tro CNTR he ller, Re 06 0000 TMR0 TCMTRR0L_ CM PCS SCS NCE NGTH DIR _INIT OM ral Reg v. 4 O LE Co iste r 07 0000 TMR0 TSMCTRR0_L TCF TCFIE TOF TOFIE IEF IEFIE IPS INPUT CAMPOTUDREE_ MSTR EEOF VAL FORCE OPS OEN Memor y TMR0_ M 08 0000 TMR0 COMPARATOR_LOAD_1 a CMPLD1 p a n TMR0_ d 09 0000 TMR0 CMPLD2 COMPARATOR_LOAD_2 R e s e t V a 8 lu 6 e

F Table44. Detailed Peripheral Memory Map (continued) re e s c Offset Reset a Bit Bit le Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S (Hex) (Hex) 15 0 e m ic D ond TMR0_ LT OA EN EN u 0A 0000 TMR0 DBG_EN U L 0 0 0 0 2 1 TCF2 TCF1 CL2 CL1 c CSCTRL A _ F F tor F ALT TC TC TMR0_ 0B 0000 TMR0 0 0 0 0 0 FILT_CNT FILT_PER FILT M C 0C–0E — TMR0 Reserved RESERVED 5 6 F 8 TMR_ 0 0F 000F TMR0 0 0 0 0 0 0 0 0 0 0 0 0 ENBL 0 ENBL 6 /M C TMR1_ 10 0000 TMR1 COMPARISON_1 56 COMP1 F 8 0 TMR1_ 0 11 0000 TMR1 COMPARISON_2 2 COMP2 D ig TMR1_ ital S 12 0000 TMR1 CAPT CAPTURE ig TMR1_ n 13 0000 TMR1 LOAD a LOAD l C Pe o r n TMR1_ ip tro 14 0000 TMR1 HOLD HOLD he ller, R 15 0000 TMR1 TCMNRT1R_ COUNTER ral Re e g v. 4 16 0000 TMR1 TMR1_ CM PCS SCS CE GTH DIR NIT OM ister M CTRL N N OI e O E C m L o r 17 0000 TMR1 TSMCTRR1_L TCF TCFIE TOF TOFIE IEF IEFIE IPS INPUT CAMPOTUDREE_ MSTR EEOF VAL FORCE OPS OEN y Map a n TMR1_ d 18 0000 TMR1 COMPARATOR_LOAD_1 R CMPLD1 e s e 19 0000 TMR1 TMR1_ COMPARATOR_LOAD_2 t V CMPLD2 a 8 lu 7 e

8 Table44. Detailed Peripheral Memory Map (continued) P 8 e r ip Offset Reset h Bit Bit e Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r 15 0 a (Hex) (Hex) l R e g 1A 0000 TMR1 CTSMCRT1R_L DBG_EN AULT _LOAD 0 0 0 0 F2EN F1EN TCF2 TCF1 CL2 CL1 ister M F T C C e L T T m A o r TMR1_ y 1B 0000 TMR1 0 0 0 0 0 FILT_CNT FILT_PER M FILT a M p C 1C–1F — TMR1 Reserved RESERVED a 5 n 6 d F8006/MC 20 0000 PWM PCWTRML_ LDFQ HALF IPOL2 IPOL1 IPOL0 PRSC PWMRIE PWMF ISENS LDOK PWMEN Reset Va 56F800 21 0000 PWM FPCWTMR_L 0 0 0 0 POL3 POL2 POL1 POL0 FIE3 ODE3 FIE2 ODE2 FIE1 ODE1 FIE0 ODE0 lue 2 F F F F M M M M D F F F F ig 3 2 1 0 3 2 1 0 ital S 22 0000 PWM FPLWTAMC_K PIN3 LAG PIN2 LAG PIN1 LAG PIN0 LAG ACK ACK ACK ACK ig F FF F FF F FF F FF FT FT FT FT n a 5 4 3 2 1 0 l C PWM_ EN TL TL TL TL TL TL 5 4 3 2 1 0 o 23 0000 PWM _ 0 C C C C C C 0 0 T T T T T T n OUT D T T T T T T U U U U U U tro PA OU OU OU OU OU OU O O O O O O lle r PWM_ , R 24 0000 PWM CNTR 0 CR e v . 4 PWM_ 25 0000 PWM 0 PWMCM CMOD PWM_ Fre 26 0000 PWM VAL0 PMVAL e sc PWM_ a 27 0000 PWM PMVAL le VAL1 S e PWM_ m 28 0000 PWM PMVAL ic VAL2 o n d u c to r

F Table44. Detailed Peripheral Memory Map (continued) re e s c Offset Reset a Bit Bit le Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S (Hex) (Hex) 15 0 e m ic PWM_ ond 29 0000 PWM VAL3 PMVAL u c to PWM_ r 2A 0000 PWM PMVAL VAL4 PWM_ 2B 0000 PWM PMVAL M VAL5 C 5 6 PWM_ F 2C 0FFF PWM 0 0 0 0 PWMDT0 8 DTIM0 0 0 6 PWM_ /M 2D 0FFF PWM 0 0 0 0 PWMDT1 C DTIM1 5 6 F PWM_ 8 2E FFFF PWM DISMAP_15_0 0 DMAP1 0 2 D PWM_ ig 2F 00FF PWM DMAP2 0 0 0 0 0 0 0 0 DISMAP_23_16 ita l Signal Con 30 0000 PWM PCWNFMG_ 0 DBG_EN WAIT_EN EDG 0 TOPNEG45 TOPNEG23 TOPNEG01 0 BOTNEG45 BOTNEG23 BOTNEG01 INDEP45 INDEP23 INDEP01 WP Perip troller, R 31 0000 PWM CPCWTMR_L ENHA nBX MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 0 0 VLMODE 0 SWP45 SWP23 SWP01 heral Re e g v. 4 32 00-U1 PWM PPWORMT_ 0 0 0 0 0 0 0 0 0 PORT ister M 33 0000 PWM PWM_ 0 0 0 0 0 0 0 0 0 0 PEC2 PEC1 PEC0 ICC2 ICC1 ICC0 em ICCTRL o r y 34 0000 PWM SPCWTMR_L 0 0 CINV5 CINV4 CINV3 CINV2 CINV1 CINV0 0 SRC2 0 SRC1 0 SRC0 Map a n d R e s e t V a 8 lu 9 e

9 Table44. Detailed Peripheral Memory Map (continued) P 0 e r ip Offset Reset h Bit Bit e Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r 15 0 a (Hex) (Hex) l R e g N is _E te PWM_ UT r M 35 0000 PWM O SYNC_WINDOW e SYNC _ m C o N r y SY M a M 0 p C PWM_ R a 5 36 0000 PWM T 0 0 0 0 FILT0_CNT FILT0_PER n 6 FFILT0 S d F8 G R 0 e 0 1 s 6 PWM_ R e /M 37 0000 PWM FFILT1 ST 0 0 0 0 FILT1_CNT FILT1_PER t V C G a 5 lu 6F80 38 0000 PWM PWM_ TR2 0 0 0 0 FILT2_CNT FILT2_PER e 0 FFILT2 S 2 G D ig PWM_ R3 ital S 39 0000 PWM FFILT3 GST 0 0 0 0 FILT3_CNT FILT3_PER ig n 3B–3F — PWM Reserved RESERVED a l Controlle 40 0000 INTC IINCTSCR_ INT IPIC VAB INT_DIS ERRF ETRE TRBUF BKPT STPCNT r , R 41 0000 INTC INTC_ 0 0 VECTOR_BASE_ADDRESS e VBA v . 4 INTC_ 42 0000 INTC 0 0 USER2 0 0 USER1 IAR0 INTC_ F 43 0000 INTC 0 0 USER4 0 0 USER3 re IAR1 e s ca INTC_ le S 44 0000 INTC IAR2 0 0 USER6 0 0 USER5 e m 45–5F — INTC Reserved RESERVED ic o ndu 60 001F ADC0 ADC0_ 0 0 0 0 0 0 0 0 CO AIEN CO ADCH c ADCSC1A O D to C A r

F Table44. Detailed Peripheral Memory Map (continued) re e s c Offset Reset a Bit Bit le Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S (Hex) (Hex) 15 0 e m ic T G ondu 61 0000 ADC0 AADDCCS0C_2 0 0 0 0 0 0 0 0 DAC DTR 0 0 0 ECC REFSEL cto A A r 62–65 — ADC0 Reserved RESERVED P ADC0_ PC M MC56 66 0000 ADC0 ADCCFG 0 0 0 0 0 0 0 0 ADL ADIV ADLS MODE ADICLK F 8 67–69 — ADC0 Reserved RESERVED 0 0 6/M 6A 001F ADC0 ADC0_ 0 0 0 0 0 0 0 0 CO AIEN CO ADCH C ADCSC1B O D 5 C A 6 F 8002 6B 0000 ADC0 AADDCCR0_A 0 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 0 0 0 D A A A A A A A A A A A A igita 6C 0000 ADC0 ADC0_ 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0 0 0 l Sig ADCRB AD AD AD AD AD AD AD AD AD AD AD AD n 6D–6F — ADC0 Reserved RESERVED a l C Pe on 80 001F ADC1 ADC1_ 0 0 0 0 0 0 0 0 CO AIEN CO ADCH rip tro ADCSC1A CO AD he ller, Rev. 4 81 0000 ADC1 AADDCCS1C_2 0 0 0 0 0 0 0 0 ADACT ADTRG 0 0 0 ECC REFSEL ral Registe 82–85 — ADC1 Reserved RESERVED r M e P m 86 0000 ADC1 AADDCCC1F_G 0 0 0 0 0 0 0 0 ADLPC ADIV DLSM MODE ADICLK ory M A a p 87–89 — ADC1 Reserved RESERVED a n d ADC1_ O O R 8A 001F ADC1 0 0 0 0 0 0 0 0 C AIEN C ADCH e ADCSC1B O D s C A et V a 9 lu 1 e

9 Table44. Detailed Peripheral Memory Map (continued) P 2 e r ip Offset Reset h Bit Bit e Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r 15 0 a (Hex) (Hex) l R e g 8B 0000 ADC1 AADDCCR1_A 0 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 0 0 0 ister A A A A A A A A A A A A M e 8C 0000 ADC1 AADDCCR1_B 0 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 0 0 0 mory A A A A A A A A A A A A M a M 8D–8F — ADC1 Reserved RESERVED p C a 5 n 6 PGA0_ d F8 A0 0000 PGA0 CNTL0 0 0 0 0 0 0 0 0 TM GAINSEL LP EN R 0 e 0 s 6/MC56F A1 0002 PGA0 PCGNATL01_ 0 0 0 0 0 0 0 0 PPDIS RMODE 0 CALMODE CPD et Value 8 A 0 P 0 2 G D PGA0_ RI igita A2 000E PGA0 CNTL2 0 0 0 0 0 0 0 0 0 0 WT NUM_CLK_GS ADIV l S S ig G P n N M al C A3 0000 PGA0 PGA0_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NNI CO o U T n R S tr o A4–BF — PGA0 Reserved RESERVED lle r , R C0 0000 PGA1 PGA1_ 0 0 0 0 0 0 0 0 TM GAINSEL LP EN e CNTL0 v . 4 E C1 0002 PGA1 PGA1_ 0 0 0 0 0 0 0 0 DIS MOD 0 CALMODE CPD CNTL1 P P R F A re P e s G cale C2 000E PGA1 PCGNATL12_ 0 0 0 0 0 0 0 0 0 0 TRI NUM_CLK_GS ADIV S W e S m ic o n d u c to r

F Table44. Detailed Peripheral Memory Map (continued) re e s c Offset Reset a Bit Bit le Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S (Hex) (Hex) 15 0 e m ico G P n N M du C3 0000 PGA1 PGA1_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NI O c N C to U T r R S C4–DF — PGA1 Reserved RESERVED E0 0200 SCI SCI_RATE SBR FRAC_SBR M C 56F80 E1 0000 SCI CSTCRIL_1 LOOP SWAI RSRC M WAKE POL PE PT TEIE TIIE RFIE REIE TE RE RWU SBK 0 6/M DE C SCI_ O 5 E2 0000 SCI 0 0 0 0 0 0 0 0 0 0 0 0 M 0 0 0 6F8 CTRL2 N _ 00 LI 2 D E E F E ig E3 C000 SCI SCI_STAT DR DL DR DL OR NF FE PF 0 0 0 0 LSE 0 0 RAF ita T TI R RI l S E4 0000 SCI SCI_DATA 0 0 0 0 0 0 0 RECEIVE_TRANSMIT_DATA ig n a E5–FF — SCI Reserved RESERVED l C Pe ontroller, R 00 6141 SPI SSCPTIR_L SPR DSO ERRIE MODFEN SPRIE SPMSTR CPOL CPHA SPE SPTIE SPRF OVRF MODF SPTE ripheral Re e A M O R B R g v. 4 01 000F SPI DSSCPTI_RL WOM 0 0 BD2X SB_IN B_DAT B_OD B_AUT B_DD B_STR B_OVE SPR3 DS ister M S S S S S S S e S S S S S S m o 02 0000 SPI SPI_DRCV R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 ry M 03 0000 SPI SPI_DXMIT T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 a p a 04–1F — SPI Reserved RESERVED n d R 20 0000 I2C I2C_ADDR 0 0 0 0 0 0 0 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 e s e 21 0000 I2C I2C_ 0 0 0 0 0 0 0 0 MULT ICR t V 9 FREQDIV alu 3 e

9 Table44. Detailed Peripheral Memory Map (continued) P 4 e r ip Offset Reset h Bit Bit e Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r 15 0 a (Hex) (Hex) l R e g N is 22 0000 I2C I2C_CR1 0 0 0 0 0 0 0 0 CE IICIE MST TX TXAK RSTA 0 0 te II r M Y K e 23 0080 I2C I2C_SR 0 0 0 0 0 0 0 0 TCF IAAS S ARBL 0 SRW IICIF A m U X o B R ry 24 0000 I2C I2C_DATA 0 0 0 0 0 0 0 0 DATA M a M p C N T a 5 E X n 6 25 0000 I2C I2C_CR2 0 0 0 0 0 0 0 0 A E 0 0 0 AD10 AD9 AD8 d F8 C D R 0 G A e 0 s 6/M ED ED N L et V C I2C_SMB_ V V E E a 56F8 26 0000 I2C CSR 0 0 0 0 0 0 0 0 ESER ESER SIICA TCKS SLTF SHTF 0 0 lue 00 R R 2 D I2C_ ig 27 0000 I2C ADDR2 0 0 0 0 0 0 0 0 SAD7 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 0 ita l Sign 28 0000 I2C I2C_SLT1 0 0 0 0 0 0 0 0 SLT15 SLT14 SLT13 SLT12 SLT11 SLT10 SLT9 SLT8 al C S S S S S S S S o 7 6 5 4 3 2 1 0 ntr 29 0000 I2C I2C_SLT2 0 0 0 0 0 0 0 0 SLT SLT SLT SLT SLT SLT SLT SLT o S S S S S S S S lle r 30–3F — I2C Reserved RESERVED , R ev. 4 40 0302 COP COP_ 0 0 0 0 0 0 PSS 0 CLKSEL REN EN EN CEN CWP CTRL O S W L C C C COP_ F 41 FFFF COP TIMEOUT re TOUT e s cale 42 FFFF COP CCNOTPR_ COUNT_SERVICE S e m 43–5F — COP Reserved RESERVED ic o n d u c to r

F Table44. Detailed Peripheral Memory Map (continued) re e s c Offset Reset a Bit Bit le Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S (Hex) (Hex) 15 0 e m icondu 60 0011 OCCS OCCTCRSL_ PLLIE1 PLLIE0 OCIE 0 0 0 CKON 0 0 LLPD 0 RECS ZSRC cto L L P P r OCCS_ 61 2000 OCCS LORTP COD 0 0 0 0 0 0 0 0 DIVBY Y M N D C OCCS_ 1 0 D R 5 62 0015 OCCS LI LI LOCI 0 0 0 0 0 0 LCK1 LCK0 P 0 _ ZSRC 6F80 STAT LO LO PLL OSC 0 C 6 /M E C56F80 64 1611 OCCS OOCCCTRSL_ ROPD ROSB COHL K_MOD RANGE XT_SEL TRIM 0 L E 2 C D ig NA ital S 65 0000 OCCS COLKCCCHSK_R K_E REFERENCE_CNT ig CH n a l C 66 0000 OCCS OCCS_ 0 0 0 0 0 0 0 0 0 TARGET_CNT Pe o CLKCHKT r n ip tro OCCS_ he ller, R 67 0000 OCCS PROT 0 0 0 0 0 0 0 0 0 0 FRQEP OSCEP PLLEP ral Re e 68–7F — OCCS Reserved RESERVED g v. 4 GPIOA_ iste 80 00FF GPIOA PUR 0 0 0 0 0 0 0 0 PU r M e m 81 0000 GPIOA GPIOA_DR 0 0 0 0 0 0 0 0 D o r y GPIOA_ M 82 0000 GPIOA 0 0 0 0 0 0 0 0 DD a DDR p a n GPIOA_ d 83 0080 GPIOA PER 0 0 0 0 0 0 0 0 PE R e s 84 — GPIOA Reserved RESERVED et V a 9 lu 5 e

9 Table44. Detailed Peripheral Memory Map (continued) P 6 e r ip Offset Reset h Bit Bit e Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r 15 0 a (Hex) (Hex) l R e g GPIOA_ is 85 0000 GPIOA IENR 0 0 0 0 0 0 0 0 IEN te r M GPIOA_ e 86 0000 GPIOA 0 0 0 0 0 0 0 0 IPOL m IPOLR o r y GPIOA_ M 87 0000 GPIOA 0 0 0 0 0 0 0 0 IP a M IPR p C a 5 n 6 GPIOA_ d F8 88 0000 GPIOA IESR 0 0 0 0 0 0 0 0 IES R 0 e 0 s 6/M 89 — GPIOA Reserved RESERVED et V C a 56F 8A 0000 GPIOA RGAPWIODAAT_A 0 0 0 0 0 0 0 0 RAWDATA lue 8 0 0 GPIOA_ 2 D 8B 0000 GPIOA DRIVE 0 0 0 0 0 0 0 0 DRIVE ig ita 8C 00FF GPIOA GPIOA_IFE 0 0 0 0 0 0 0 0 IFE l S ig GPIOA_ n 8D 0000 GPIOA 0 0 0 0 0 0 0 0 SLEW a SLEW l C o 8E–9F — GPIOA Reserved RESERVED n tr o GPIOB_ lle A0 00FF GPIOB PUR 0 0 0 0 0 0 0 0 PUR r , R e A1 0000 GPIOB GPIOB_DR 0 0 0 0 0 0 0 0 DR v . 4 GPIOB_ A2 0000 GPIOB 0 0 0 0 0 0 0 0 DDR DDR GPIOB_ F A3 0080 GPIOB 0 0 0 0 0 0 0 0 PER re PER e s c A4 — GPIOB Reserved RESERVED a le S GPIOB_ e A5 0000 GPIOB 0 0 0 0 0 0 0 0 IENR m IENR ic o n GPIOB_ d A6 0000 GPIOB 0 0 0 0 0 0 0 0 IPOLR u IPOLR c to r

F Table44. Detailed Peripheral Memory Map (continued) re e s c Offset Reset a Bit Bit le Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S (Hex) (Hex) 15 0 e m ic GPIOB_ ond A7 0000 GPIOB IPR 0 0 0 0 0 0 0 0 IPR u c to GPIOB_ r A8 0000 GPIOB 0 0 0 0 0 0 0 0 IESR IESR A9 — GPIOB Reserved RESERVED M C GPIOB_ 5 AA 0000 GPIOB 0 0 0 0 0 0 0 0 RAWDATA 6 RAWDATA F 8 0 GPIOB_ 0 AB 0000 GPIOB 0 0 0 0 0 0 0 0 DRIVE 6 DRIVE /M C 5 AC 00FF GPIOB GPIOB_IFE 0 0 0 0 0 0 0 0 IFE 6 F 8 GPIOB_ 0 AD 0000 GPIOB 0 0 0 0 0 0 0 0 SLEW 0 SLEW 2 D ig AE–BF — GPIOB Reserved RESERVED ita l S C0 00FF GPIOC GPIOC_ 0 0 0 0 0 0 0 0 PUR ig PUR n a l C C1 0000 GPIOC GPIOC_DR 0 0 0 0 0 0 0 0 DR Pe o r n GPIOC_ ip tro C2 0000 GPIOC DDR 0 0 0 0 0 0 0 0 DDR he ller, R C3 0080 GPIOC GPIOC_ 0 0 0 0 0 0 0 0 PER ral Re e PER g v. 4 C4 — GPIOC Reserved RESERVED iste r M GPIOC_ e C5 0000 GPIOC 0 0 0 0 0 0 0 0 IENR m IENR o r y GPIOC_ M C6 0000 GPIOC 0 0 0 0 0 0 0 0 IPOLR a IPOLR p a n GPIOC_ d C7 0000 GPIOC IPR 0 0 0 0 0 0 0 0 IPR R e s e C8 0000 GPIOC GPIOC_ 0 0 0 0 0 0 0 0 IESR t V IESR a 9 lu 7 e

9 Table44. Detailed Peripheral Memory Map (continued) P 8 e r ip Offset Reset h Bit Bit e Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r 15 0 a (Hex) (Hex) l R e g C9 — GPIOC Reserved RESERVED is te CA 0000 GPIOC GPIOC_ 0 0 0 0 0 0 0 0 RAWDATA r M RAWDATA e m o GPIOC_ r CB 0000 GPIOC 0 0 0 0 0 0 0 0 DRIVE y DRIVE M a M p C5 CC 00FF GPIOC GPIOC_ 0 0 0 0 0 0 0 0 IFE an 6 IFE d F8 R 0 GPIOC_ e 0 CD 0000 GPIOC 0 0 0 0 0 0 0 0 SLEW s 6/M SLEW et V C a 5 CE–DF — GPIOC Reserved RESERVED lu 6F e 8 GPIOD_ 0 E0 00FF GPIOD 0 0 0 0 0 0 0 0 0 0 0 0 PUR 0 PUR 2 D ig E1 0000 GPIOD GPIOD_DR 0 0 0 0 0 0 0 0 0 0 0 0 DR ita l S E2 0000 GPIOD GPIOD_ 0 0 0 0 0 0 0 0 0 0 0 0 DDR ig DDR n a l C E3 0080 GPIOD GPIOD_ 0 0 0 0 0 0 0 0 0 0 0 0 PER o PER n tr o E4 — GPIOD Reserved RESERVED lle r, R E5 0000 GPIOD GPIOD_ 0 0 0 0 0 0 0 0 0 0 0 0 IENR e IENR v . 4 GPIOD_ E6 0000 GPIOD 0 0 0 0 0 0 0 0 0 0 0 0 IPOLR IPOLR GPIOD_ F E7 0000 GPIOD 0 0 0 0 0 0 0 0 0 0 0 0 IPR re IPR e s c GPIOD_ a E8 0000 GPIOD 0 0 0 0 0 0 0 0 0 0 0 0 IESR le IESR S e m E9 — GPIOD Reserved RESERVED ic o n GPIOD_ d EA 0000 GPIOD 0 0 0 0 0 0 0 0 0 0 0 0 RAWDATA u RAWDATA c to r

F Table44. Detailed Peripheral Memory Map (continued) re e s c Offset Reset a Bit Bit le Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S (Hex) (Hex) 15 0 e m ic GPIOD_ ond EB 0000 GPIOD DRIVE 0 0 0 0 0 0 0 0 0 0 0 0 DRIVE u c to GPIOD_ r EC 00FF GPIOD 0 0 0 0 0 0 0 0 0 0 0 0 IFE IFE GPIOD_ ED 0000 GPIOD 0 0 0 0 0 0 0 0 0 0 0 0 SLEW M SLEW C 5 6 EE–9F — GPIOD Reserved RESERVED F 8 0 GPIOE_ 0 00 00FF GPIOE 0 0 0 0 0 0 0 0 PUR 6 PUR /M C 5 01 0000 GPIOE GPIOE_DR 0 0 0 0 0 0 0 0 DR 6 F 8 GPIOE_ 0 02 0000 GPIOE 0 0 0 0 0 0 0 0 DDR 0 DDR 2 D ig GPIOE_ ita 03 0080 GPIOE PER 0 0 0 0 0 0 0 0 PER l S ig 04 — GPIOE Reserved RESERVED n a l C 05 0000 GPIOE GPIOE_ 0 0 0 0 0 0 0 0 IENR Pe o IENR r n ip tro GPIOE_ he ller, R 06 0000 GPIOE IPOLR 0 0 0 0 0 0 0 0 IPOLR ral Re e GPIOE_ g v. 4 07 0000 GPIOE IPR 0 0 0 0 0 0 0 0 IPR iste r GPIOE_ M 08 0000 GPIOE 0 0 0 0 0 0 0 0 IESR e IESR m o r 09 — GPIOE Reserved RESERVED y M a GPIOE_ p 0A 0000 GPIOE RAWDATA 0 0 0 0 0 0 0 0 RAWDATA an d GPIOE_ R 0B 0000 GPIOE 0 0 0 0 0 0 0 0 DRIVE e DRIVE s e t V 0C 00FF GPIOE GPIOE_IFE 0 0 0 0 0 0 0 0 IFE a 9 lu 9 e

1 Table44. Detailed Peripheral Memory Map (continued) P 0 e 0 r ip Offset Reset h Bit Bit e Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r 15 0 a (Hex) (Hex) l R e g GPIOE_ is 0D 0000 GPIOE SLEW 0 0 0 0 0 0 0 0 SLEW te r M 0E–1F — GPIOE Reserved RESERVED e m o GPIOF_ r 20 00FF GPIOF 0 0 0 0 0 0 0 0 0 0 0 0 PUR y PUR M a M p C 21 0000 GPIOF GPIOF_DR 0 0 0 0 0 0 0 0 0 0 0 0 DR a 5 n 6 d F8 22 0000 GPIOF GPIOF_ 0 0 0 0 0 0 0 0 0 0 0 0 DDR R 0 DDR e 0 s 6 e /M GPIOF_ t V C 23 0080 GPIOF 0 0 0 0 0 0 0 0 0 0 0 0 PER a 5 PER lu 6F e 8 24 — GPIOF Reserved RESERVED 0 0 2 D 25 0000 GPIOF GPIOF_ 0 0 0 0 0 0 0 0 0 0 0 0 IENR ig IENR ita l S 26 0000 GPIOF GPIOF_ 0 0 0 0 0 0 0 0 0 0 0 0 IPOLR ig IPOLR n a l C 27 0000 GPIOF GPIOF_ 0 0 0 0 0 0 0 0 0 0 0 0 IPR o IPR n tr o GPIOF_ lle 28 0000 GPIOF IESR 0 0 0 0 0 0 0 0 0 0 0 0 IESR r , R e 29 — GPIOF Reserved RESERVED v . 4 GPIOF_ 2A 0000 GPIOF 0 0 0 0 0 0 0 0 0 0 0 0 RAWDATA RAWDATA GPIOF_ F 2B 0000 GPIOF 0 0 0 0 0 0 0 0 0 0 0 0 DRIVE re DRIVE e s c 2C 00FF GPIOF GPIOF_IFE 0 0 0 0 0 0 0 0 0 0 0 0 IFE a le S GPIOF_ e 2D 0000 GPIOF 0 0 0 0 0 0 0 0 0 0 0 0 SLEW m SLEW ic o n 2E–3F — GPIOF Reserved RESERVED d u c to r

F Table44. Detailed Peripheral Memory Map (continued) re e s c Offset Reset a Bit Bit le Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S (Hex) (Hex) 15 0 e m ic L o B T n E S STOP_ WAIT_ duc 40 0000 SIM SIM_CTRL 0 0 0 0 0 0 0 0 0 0 CE W R DISABLE DISABLE to N S r O U R P O M 41 0001 SIM RSSIMTA_T 0 0 0 0 0 0 0 0 0 SWR P_C P_L XTR LVDR PPD POR C O O E 5 C C 6 F 8 SIM_ 0 42 01F2 SIM SIM_MSH_ID 0 MSHID 6 /M C SIM_ 5 43 601D SIM SIM_LSH_ID 6 LSHID F 8 0 1 0 0 S S 2 D 45 2020 SIM CLSKIMO_UT 0 0 KDI 0 0 CLKOSEL1 0 0 KDI CLKOSEL0 ig L L ita C C l Signal C 46 0000 SIM SIM_PCR TMR_CR 0 PWM_CR SCI_CR 0 0 0 0 0 0 0 0 0 0 0 0 Pe o r n 2 1 0 1 0 1 0 ip tro 47 0000 SIM SIM_PCE MP MP MP DC DC GA GA I2C SCI SPI PWM COP PDB PIT TA1 TA0 he ller, Rev. 4 48 0000 SIM SIM_SDR CCMP2 CCMP1 CCMP0 AADC1 AADC0 PPGA1 PPGA0 I2C SCI SPI PWM COP PDB PIT TA1 TA0 ral Registe 49 F000 SIM SIM_ISAL ADDR_15_6 0 0 0 0 0 0 r M e 4A 0000 SIM SIM_PROT 0 0 0 0 0 0 0 0 0 0 0 0 PCEP GIPSP m o r 4B 0000 SIM SIM_GPSA 0 0 0 0 0 0 0 GPS_A6 GPS_A5 GPS_A4 GPS_A3 y M a SIM_ p 4C 0000 SIM GPS_B5 GPS_B4 GPS_B3 GPS_B2 0 GPS_B1 GPS_B0 a GPSB0 n d R SIM_ 4D 0000 SIM GPSB1 0 0 0 0 0 0 0 0 0 0 0 0 GPS_B7 GPS_B6 ese t V a 10 lu 1 e

1 Table44. Detailed Peripheral Memory Map (continued) P 0 e 2 r ip Offset Reset h Bit Bit e Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r 15 0 a (Hex) (Hex) l R e g 4E 0000 SIM SIM_GPSC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _C6 _C0 iste PS PS r M G G e m 4F 0000 SIM SIM_GPSD 0 0 0 0 0 0 0 GPS_D3 GPS_D2 GPS_D1 GPS_D0 o r y 3 2 1 M T T T a M L L L p C 50 0000 SIM SIM_IPS0 0 0 0 0 AU AU AU IPS_PSRC2 IPS_PSRC1 IPS_PSRC0 a 5 F F F n 6 _ _ _ d F80 PS PS PS Re 0 I I I s 6/M 51 0000 SIM SIM_IPS1 0 IPS_C2_WS IPS_C1_WS IPS_C0_WS IPS_T1 IPS_T0 et V C a 5 52–5F — SIM Reserved RESERVED lu 6F e 8002 D 60 0208 PMC PMC_SCR OORF LVDF PPDF PORF OORIE LVDIE LVDRE PPDE LPR LPRS LPWUI BGBE LVDE LVLS PROT ig ita EN l S 61 00--2 PMC PMC_CR2 0 0 0 0 0 0 0 O_ LPO_TRIM TRIM ig P n L a l C 7F — PMC Reserved RESERVED o ntr 80 0000 CMP0 CMP0_ 0 0 0 0 0 0 0 0 0 FILTER_CNT PMC MMC o CR0 lle r , R CMP0_ DE e 81 0000 CMP0 0 0 0 0 0 0 0 0 SE WE 0 O INV COS OPE EN v. 4 CR1 PM CMP0_ 82 0000 CMP0 0 0 0 0 0 0 0 0 FILT_PER FPR F ree 83 0000 CMP0 CMP0_ 0 0 0 0 0 0 0 0 0 0 0 IER IEF CFR CFF UT s SCR O ca C le S 84–9F — CMP0 Reserved RESERVED e m CMP1_ ic A0 0000 CMP1 0 0 0 0 0 0 0 0 0 FILTER_CNT PMC MMC o CR0 n d u c to r

F Table44. Detailed Peripheral Memory Map (continued) re e s c Offset Reset a Bit Bit le Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S (Hex) (Hex) 15 0 e m ic E o CMP1_ D ndu A1 0000 CMP1 CR1 0 0 0 0 0 0 0 0 SE WE 0 MO INV COS OPE EN cto P r CMP1_ A2 0000 CMP1 0 0 0 0 0 0 0 0 FILT_PER FPR M CMP1_ T C A3 0000 CMP1 SCR 0 0 0 0 0 0 0 0 0 0 0 IER IEF CFR CFF OU 56 C F 8 A4–BF — CMP1 Reserved RESERVED 0 0 6 /M C0 0000 CMP2 CMP2_ 0 0 0 0 0 0 0 0 0 FILTER_CNT PMC MMC C CR0 5 6 F E 8 CMP2_ D 002 C1 0000 CMP2 CR1 0 0 0 0 0 0 0 0 SE WE 0 MO INV COS OPE EN D P ig ita C2 0000 CMP2 CMP2_ 0 0 0 0 0 0 0 0 FILT_PER l S FPR igna C3 0000 CMP2 CMP2_ 0 0 0 0 0 0 0 0 0 0 0 IER IEF CFR CFF UT l C SCR CO Pe o r n C4–DF — CMP2 Reserved RESERVED ip tro he ller, R E0 0000 PIT PIT_CTRL 0 0 0 0 0 0 0 0 0 PRESCALER PRF PRIE T_EN ral Re e N g v. 4 C iste E1 0000 PIT PIT_MOD MODULO_VALUE r M e E2 0000 PIT PIT_CNTR COUNTER_VALUE m o r E3–FF — PIT Reserved RESERVED y M 00 0000 PDB PDB_SCR PRESCALER 0 AOS 0 BOS ONT TRIG TRIGSEL ENA ENB ap an C SW d R e PDB_ se 01 0000 PDB DELAYA DELAYA t V a 10 lu 3 e

1 Table44. Detailed Peripheral Memory Map (continued) P 0 e 4 r ip Offset Reset h Bit Bit e Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r 15 0 a (Hex) (Hex) l R e g PDB_ is 02 0000 PDB DELAYB DELAYB te r M 03 FFFF PDB PDB_MOD MOD e m o PDB_ r 04 FFFF PDB COUNT y COUNT M a M p C 05–1F — PDB Reserved RESERVED a 5 n 6 d F8 20 0000 RTC RTC_SC 0 0 0 0 0 0 0 0 RTIF RTCLKS RTIE RTCPS R 0 e 06 21 0000 RTC RTC_CNT 0 0 0 0 0 0 0 0 RTCCNT se /M t V C 22 0000 RTC RTC_MOD 0 0 0 0 0 0 0 0 RTCMOD a 5 lu 6F 23–FF — RTC Reserved RESERVED e 8 0 0 2 Digita 00 0000 HFM CLFKMD_IV 0 0 0 0 0 0 0 0 DIVLD PRDIV8 DIV l S C ign 01 0000 HFM FM_CNFG 0 0 0 0 0 CK 0 AEIE EIE CCIE AC 0 0 0 LBTS BTS a O B Y l C L C KE o n T troller, R 03 -0003 HFM FM_SECHI KEYEN SECSTA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e v FM_ . 4 04 0000 HFM SECLO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC 06–0F — HFM Reserved RESERVED F 10 FFFF6 HFM FM_PROT PROTECT re e s 11 — HFM Reserved RESERVED c a le S F L RR K emico 13 00C0 HFM FM_USTAT 0 0 0 0 0 0 0 0 CBEI CCIF PVIO ACCE 0 BLAN 0 0 n d u 14 0000 HFM FM_CMD 0 0 0 0 0 0 0 0 0 CMD c to r

F Table44. Detailed Peripheral Memory Map (continued) re e s c Offset Reset a Bit Bit le Addr. Value Periph. Register 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S (Hex) (Hex) 15 0 e m ic 17 — HFM Reserved RESERVED o n d u 18 0000 HFM FM_DATA FMDATA c to r 19 — HFM Reserved RESERVED 1A FFFF4 HFM FM_OPT0 IFR_OPT0 M 1B FFFF5 HFM FM_OPT1 IFR_OPT1 C 5 6 FM_ F 1D FFFF6 HFM TST_AREA_SIG 8 TSTSIG 0 0 6 /M 1E–3F — HFM Reserved RESERVED C 5 1 The binary reset value of this register is 0000 0000 0UUU UUUU, where U represents an undefined value. Spaces have been added to the value for clarity. 6 F8 2 The binary reset value of this register is 0000 0000 111NC NC NC NC NC. Spaces have been added to the value for clarity. 0 0 3 The binary reset value of this register is FS00 0000 0000 0000, where F indicates that the reset state is loaded from the flash array during reset, and where S 2 D indicates that the reset state is determined by the security state of the module. Spaces have been added to the value for clarity. igita 4 The reset state is loaded from the flash array during reset. l S 5 The reset state is loaded from the flash array during reset. ig 6 The reset state is loaded from the flash array during reset. n a l C Pe o r n ip tro he ller, R ral Re e g v. 4 iste r M e m o r y M a p a n d R e s e t V a 10 lu 5 e

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