Freescale Semiconductor Document Number: MC34903_4_5 Technical Data Rev. 4.0, 10/2013 System Basis Chip with CAN 34903/4/5 High Speed and LIN Interface 34903/ Industrial The 34903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power SYSTEM BASIS CHIP management unit for the MCU with additional integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and fail-safe operation modes. The SBC may include zero or one LIN 2.1 interface with LIN output pin switches. It includes up to four wake-up input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Low-power (LP) modes, with very EK Suffix (Pb-free) low-current consumption. In addition, the device is part of a family 98ASA10556D concept where pin compatibility adds versatility to module design. 32-PIN SOIC The 34903/4/5 also implements an innovative and advanced fail-safe state machine and concept solution. Applications Features • Industrial process control • Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with • Automation possibility of usage external PNP to extend current capability and • Motor control share power dissipation • Robotics • Voltage, current, and temperature protection • Extremely low quiescent current in LP modes • Fully-protected embedded 5.0 V regulator for the CAN driver • Multiple undervoltage detections to address various MCU specifications and system operation modes (i.e. cranking) • Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection • MUX output pin for device internal analog signal monitoring and power supply monitoring • Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. • Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and V overcurrent DD detection. • ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s • Scalable product family of devices ranging from 0 to 1 LIN, compatible to J2602-2 and LIN 2.1 Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2013. All rights reserved.

TABLE OF CONTENTS TABLE OF CONTENTS Simplified Application Diagrams .................................................................................................................3 Device Variations .......................................................................................................................................5 Internal Block Diagrams .............................................................................................................................6 Pin Connections .........................................................................................................................................8 Electrical Characteristics ..........................................................................................................................12 Maximum Ratings ..................................................................................................................................12 Static Electrical Characteristics .............................................................................................................15 Dynamic Electrical Characteristics ........................................................................................................23 Timing Diagrams ...................................................................................................................................26 Functional Description ..............................................................................................................................31 Introduction ............................................................................................................................................31 Functional Pin Description .....................................................................................................................31 Functional Device Operation ....................................................................................................................35 Mode and State Description ..................................................................................................................35 LP Modes ..............................................................................................................................................36 State Diagram ........................................................................................................................................37 Mode Change ........................................................................................................................................38 Watchdog Operation ..............................................................................................................................38 Functional Block Operation Versus Mode .............................................................................................40 Illustration of Device Mode Transitions. .................................................................................................41 Cyclic Sense Operation During LP Modes ............................................................................................43 Behavior at Power Up and Power Down ...............................................................................................45 Fail-safe Operation ...................................................................................................................................47 CAN Interface ........................................................................................................................................51 CAN Interface Description .....................................................................................................................51 CAN Bus Fault Diagnostic .....................................................................................................................54 LIN Block ..................................................................................................................................................57 LIN Interface Description .......................................................................................................................57 LIN Operational Modes ..........................................................................................................................57 Serial Peripheral Interface ........................................................................................................................59 High Level Overview ..............................................................................................................................59 Detail Operation .....................................................................................................................................60 Detail of Control Bits And Register Mapping .........................................................................................63 Flags and Device Status ........................................................................................................................78 Typical Applications .................................................................................................................................85 Packaging ................................................................................................................................................90 34903/4/5 Analog Integrated Circuit Device Data 2 Freescale Semiconductor

SIMPLIFIED APPLICATION DIAGRAMS SIMPLIFIED APPLICATION DIAGRAMS 34905S * = Optional VBAT D1 (5.0V/3.3V) Q2 Q1* VBAUXVCAUXVSUP1 VAUX VE VBVDD VDD VSUP2 SAFE RST DBG INT GND MOSI VSENSE SCLK MISO SPI MCU I/O-0 CS MUX-OUT A/D I/O-1 5V-CAN CANH SPLIT TXD RXD CAN Bus CANL VBAT LIN-T TXD-L RXD-L LIN Bus LIN I/O-3 Figure 1. 34905S Simplified Application Diagram 34904 VBAT D1 (5.0V/3.3V) * = Optional Q2 Q1* VBAUXVCAUXVSUP1 VAUX VE VBVDD VDD VSUP2 SAFE RST DBG INT GND MOSI VSENSE SCLK MISO SPI MCU I/O-0 CS MUX-OUT A/D I/O-1 5V-CAN CANH SPLIT TXD VBAT CAN Bus CANL RXD I/O-2 I/O-3 Figure 2. 34904 Simplified Application Diagram 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 3

SIMPLIFIED APPLICATION DIAGRAMS VBAT D1 * = Optional 34903S Q1* VSUP VE VB VDD VDD SAFE RST DBG INT GND MOSI VSENSE SCLK MISO SPI MCU IO-0 CS MUX-OUT A/D CANH 5V-CAN SPLIT CANL TXD VBAT CAN Bus LIN-T1/I/O-2 RXD TXD-L1 LIN Bus LIN-1 RXD-L1 I/O-3 Figure 3. 34903S Simplified Application Diagram 34903P VBAT D1 * = Optional Q1* VSUP VE VB VDD VDD SAFE RST DBG INT GND MOSI VSENSE SCLK MISO SPI MCU IO-0 CS MUX-OUT A/D CANH SPLIT 5V-CAN CAN Bus CANL VBAT TXD RXD VBAT I/O-2 I/O-3 Figure 4. 34903P Simplified Application Diagram 34903/4/5 Analog Integrated Circuit Device Data 4 Freescale Semiconductor

DEVICE VARIATIONS DEVICE VARIATIONS Table 1. MC34905 Device Variations - (All devices rated at T = -40 TO 125 °C) A Freescale Part Number Version VDVDo Oltaugtpeut InterLfIaNc e(s) Wake-upT eInrmpuint a/ tLioINn Master Package VAUX VSENSE MUX MC34905S (Single LIN) MC34905CS3EK/R2 C 3.3 V 3 Wake-up + 1 LIN terms SOIC 32 pin 1 or Yes Yes Yes MC34905CS5EK/R2 C 5.0 V exposed pad 4 Wake-up + no LIN terms Table 2. MC34904 Device Variations - (All devices rated at T = -40 TO 125 °C) A Freescale Part Number Version VDVDo Oltaugtpeut InterLfIaNc e(s) Wake-upT eInrmpuint a/ tLioINn Master Package VAUX VSENSE MUX MC34904 MC34904C3EK/R2 C 3.3 V SOIC 32 pin 0 4 Wake-up Yes Yes Yes MC34904C5EK/R2 C 5.0 V exposed pad Table 3. MC34903 Device Variations - (All devices rated at T = -40 TO 125 °C) A Freescale Part Number Version VDVDo Oltaugtpeut InterLfIaNc e(s) Wake-upT eInrmpuint a/ tLioINn Master Package VAUX VSENSE MUX MC34903S (Single LIN) MC34903CS3EK/R2 C 3.3 V 2 Wake-up + 1 LIN terms SOIC 32 pin 1 or No Yes Yes MC34903CS5EK/R2 C 5.0 V 3 Wake-up + no LIN terms exposed pad MC34903P MC34903CP5EK/R2 5.0 V SOIC 32 pin C 0 3 Wake-up No Yes Yes MC34903CP3EK/R2 3.3 V exposed pad 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 5

INTERNAL BLOCK DIAGRAMS INTERNAL BLOCK DIAGRAMS VBAUX VCAUX VAUX VSUP1 VE VB 5V Auxiliary VSUP2 Regulator VDD Regulator VDD VS2-INT SAFE RST Fail-safe INT DBG Power Management MOSI State Machine GND Oscillator SPI SCLK MISO VSENSE Analog Monitoring CS Signals Condition & Analog MUX MUX-OUT VS2-INT I/O-0 I/O-1 Configurable 5V-CAN 5V-CAN Input-Output Regulator I/O-3 CANH Enhanced High Speed CAN TXD SPLIT Physical Interface CANL RXD VS2-INT TXD-L LIN-T LIN Term #1 LIN 2.1 Interface - #1 RXD-L LIN 34905S Figure 5. 34905 Internal Block Diagram VBAUX VCAUX VAUX VSUP1 VE VB 5V Auxiliary VSUP2 Regulator VDD Regulator VDD VS2-INT SAFE RST Fail-safe INT DBG Power Management MOSI State Machine GND Oscillator SPI SCLK MISO VSENSE Analog Monitoring CS Signals Condition & Analog MUX MUX-OUT II//OO--10 Configurable VS2-INT 5V-CAN I/O-2 Input-Output Regulator 5V-CAN I/O-3 CANH Enhanced High Speed CAN TXD SPLIT Physical Interface C ANL RXD Figure 6. 34904 Internal Block Diagram 34903/4/5 Analog Integrated Circuit Device Data 6 Freescale Semiconductor

INTERNAL BLOCK DIAGRAMS VSUP VE VB VSUP VE VB VS-INT VDD Regulator VDD VS-INT VDD Regulator VDD SAFE RST SAFE RST Fail-safe INT Fail-safe INT DBG Power Management MOSI DBG Power Management MOSI GND Oscillator State Machine SPI SCLK GND Oscillator State Machine SPI SCLK MISO MISO VSENSE Analog Monitoring CS VSENSE Analog Monitoring CS Signals Condition & Analog MUX MUX-OUT Signals Condition & Analog MUX MUX-OUT I/O-0 VS-INT VS-INT II//OO--32 CInopnufti-gOuuratpbulet R5eVg-uClaAtNor 5V-CAN II//OO--03 CInopnufti-gOuuratpbulet R5eVg-uClaAtNor 5V-CAN CANH CANH SCPALNITL EnhaPncheydsi cHaigl Ihn tSeprfeaecde CAN RTXXDD SCPALNITL EnhaPncheydsi cHaigl Ihn tSeprfeaecde CAN RTXXDD VS-INT 34903P TXD-L LIN-T LIN Term #1 LIN 2.1 Interface - #1 RXD-L LIN 34903S Figure 7. 34903 Internal Block Diagram 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 7

PIN CONNECTIONS PIN CONNECTIONS MC34905S MC34904 VSUP1 1 32 VB VSUP1 1 32 VB VSUP2 2 31 VE VSUP2 2 31 VE I/O-3 3 30 RXD I/O-3 3 30 RXD LIN-T/I/O-2 4 29 TXD I/O-2 4 29 TXD SAFE 5 28 VDD SAFE 5 28 VDD 5V-CAN 6 27 MISO 5V-CAN 6 27 MISO CANH 7 26 MOSI CANH 7 26 MOSI CANL 8 GROUND 25 SCLK CANL 8 GROUND 25 SCLK GND CAN 9 24 CS GND CAN 9 24 CS SPLIT 10 23 INT SPLIT 10 23 INT V-BAUX 11 22 RST V-BAUX 11 22 RST V-CAUX 12 21 I/O-1 V-CAUX 12 21 I/O-1 V-AUX 13 20 VSENSE V-AUX 13 20 VSENSE MUX-OUT 14 19 RXD-L MUX-OUT 14 19 NC I/O-0 15 18 TXD-L I/O-0 15 18 NC DBG 16 17 LIN DBG 16 17 NC GND - LEAD FRAME GND - LEAD FRAME 32 pin exposed package 32 pin exposed package MC34903S MC34903P VB 1 32 VE VB 1 32 VE VSUP 2 31 RXD VSUP 2 31 RXD I/O-3 3 30 TXD I/O-3 3 30 TXD LIN-T / I/O-2 4 29 VDD I/O-2 4 29 VDD SAFE 5 28 MISO SAFE 5 28 MISO 5V-CAN 6 27 MOSI 5V-CAN 6 27 MOSI CANH 7 26 SCLK CANH 7 26 SCLK CANL 8 GROUND 25 CS CANL 8 GROUND 25 CS GND CAN 9 24 INT GND CAN 9 24 INT SPLIT 10 23 RST SPLIT 10 23 RST MUX-OUT 11 22 VSENSE MUX-OUT 11 22 VSENSE I/O-0 12 21 RXD-L I/O-0 12 21 N/C DBG 13 20 TXD-L DBG 13 20 N/C NC 14 19 LIN NC 14 19 N/C GND 15 18 GND GND 15 18 GND NC 16 17 NC NC 16 17 NC GND - LEAD FRAME GND - LEAD FRAME 32 pin exposed package 32 pin exposed package Note: MC34905D, MC34905S, MC34904 and MC34903 are footprint compatible, Figure 8. MC34905S, MC34904 and MC34903 Pin Connections 34903/4/5 Analog Integrated Circuit Device Data 8 Freescale Semiconductor

PIN DEFINITIONS PIN DEFINITIONS A functional description of each pin can be found in the Functional Pin Description section beginning on page 31. Table 4. 34903/4/5 Pin Definitions 32 Pin 32 Pin 32 Pin 32 Pin Pin Formal Pin Name Definition 34905S 34904 34903S 34903P Function Name N/A 17, 18, N/A N/A N/C No - Connect to GND. 19 Connect N/A N/A 14, 16, 14, 16, N/C No Do NOT connect the N/C pins to GND. Leave these pins 17 17, 19- Connect Open. 21 1 1 2 2 VSUP/1 Power Battery Supply input for the device internal supplies, power on reset Voltage circuitry and the VDD regulator. VSUP and VSUP1 supplies are Supply 1 internally connected on part number MC34903BDEK and MC34903BSEK 2 2 N/A N/A VSUP2 Power Battery Supply input for 5 V-CAN regulator, VAUX regulator, I/O and LIN Voltage pins. VSUP1 and VSUP2 supplies are internally connected on Supply 2 part number MC34903BDEK and MC34903BSEK 3 3 3 3 I/O-3 Output LIN Configurable pin as an input or HS output, for connection to Termination 2 external circuitry (switched or small load). The input can be used or as a programmable Wake-up input in (LP) mode. When used as Input/ or a HS, no overtemperature protection is implemented. A basic Output Input/Output short to GND protection function, based on switch drain-source 3 overvoltage detection, is available. 4 4 4 4 LIN-T1 Output LIN Configurable pin as an input or HS output, for connection to or or Termination external circuitry (switched or small load). The input can be used as a programmable Wake-up input in (LP) mode. When used as LIN-T Input/ 1 or a HS, no overtemperature protection is implemented. A basic or Output Input/Output short to GND protection function, based on switch drain-source 2 I/O-2 overvoltage detection, is available. 5 5 5 5 SAFE Output Safe Output Output of the safe circuitry. The pin is asserted LOW if a fault (Active LOW) event occurs (e.g.: software watchdog is not triggered, VDD low, issue on the RST pin, etc.). Open drain structure. 6 6 6 6 5 V-CAN Output 5V-CAN Output voltage for the embedded CAN interface. A capacitor must be connected to this pin. 7 7 7 7 CANH Output CAN High CAN high output. 8 8 8 8 CANL Output CAN Low CAN low output. 9 9 9 9 GND-CAN Ground GND-CAN Power GND of the embedded CAN interface 10 10 10 10 SPLIT Output SPLIT Output Output pin for connection to the middle point of the split CAN termination 11 11 N/A N/A VBAUX Output VB Auxiliary Output pin for external path PNP transistor base 12 12 N/A N/A VCAUX Output VCOLLECT Output pin for external path PNP transistor collector OR Auxiliary 13 13 N/A N/A VAUX Output VOUT Output pin for the auxiliary voltage. Auxiliary 14 14 11 11 MUX-OUT Output Multiplex Multiplexed output to be connected to an MCU A/D input. Output Selection of the analog parameter available at MUX-OUT is done via the SPI. A switchable internal pull-down resistor is integrated for V current sense measurements. DD 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 9

PIN DEFINITIONS Table 4. 34903/4/5 Pin Definitions (continued) 32 Pin 32 Pin 32 Pin 32 Pin Pin Formal Pin Name Definition 34905S 34904 34903S 34903P Function Name 15 15 12 12 I/O-0 Input/ Input/Output Configurable pin as an input or output, for connection to external Output 0 circuitry (switched or small load). The voltage level can be read by the SPI and via the MUX output pin. The input can be used as a programmable Wake-up input in LP mode. In LP, when used as an output, the High Side (HS) or Low Side (LS) can be activated for a cyclic sense function. 16 16 13 13 DBG Input Debug Input to activate the Debug mode. In Debug mode, no watchdog refresh is necessary. Outside of Debug mode, connection of a resistor between DBG and GND allows the selection of Safe mode functionality. N/A N/A 15, 18 15, 18 GND Ground Ground Ground of the IC. 17 N/A 19 N/A LIN Input/ LIN bus LIN bus input output connected to the LIN bus. Output 18 N/A 20 N/A TXD-L Input LIN Transmit LIN bus transmit data input. Includes an internal pull-up resistor Data to VDD. 19 N/A 21 N/A RXD-L Output LIN Receive LIN bus receive data output. Data 20 20 22 22 VSENSE Input Sense input Direct battery voltage input sense. A serial resistor is required to limit the input current during high voltage transients. 21 21 N/A N/A I/O-1 Input/ Input Output Configurable pin as an input or output, for connection to external Output 1 circuitry (switched or small load). The voltage level can be read by the SPI and the MUX output pin. The input can be used as a programmable Wake-up input in (LP) mode. It can be used in association with I/O-0 for a cyclic sense function in (LP) mode. 22 22 23 23 RST Output Reset Output This is the device reset output whose main function is to reset the (Active LOW) MCU. This pin has an internal pull-up to VDD. The reset input voltage is also monitored in order to detect external reset and safe conditions. 23 23 24 24 INT Output Interrupt This output is asserted low when an enabled interrupt condition Output occurs. This pin is an open drain structure with an internal pull up (Active LOW) resistor to VDD. 24 24 25 25 CS Input Chip Select Chip select pin for the SPI. When the CS is low, the device is (Active LOW) selected. In (LP) mode with VDD ON, a transition on CS is a Wake-up condition 25 25 26 26 SCLK Input Serial Data Clock input for the Serial Peripheral Interface (SPI) of the device Clock 26 26 27 27 MOSI Input Master Out / SPI data received by the device Slave In 27 27 28 28 MISO Output Master In / SPI data sent to the MCU. When the CS is high, MISO is high- Slave Out impedance 28 28 29 29 VDD Output Voltage 5.0 or 3.3 V output pin of the main regulator for the Microcontroller Digital Drain supply. 29 29 30 30 TXD Input Transmit CAN bus transmit data input. Internal pull-up to VDD Data 30 30 31 31 RXD Output Receive Data CAN bus receive data output 31 31 32 32 VE Voltage Connection to the external PNP path transistor. This is an Emitter intermediate current supply source for the VDD regulator 34903/4/5 Analog Integrated Circuit Device Data 10 Freescale Semiconductor

PIN DEFINITIONS Table 4. 34903/4/5 Pin Definitions (continued) 32 Pin 32 Pin 32 Pin 32 Pin Pin Formal Pin Name Definition 34905S 34904 34903S 34903P Function Name 32 32 1 1 VB Output Voltage Base Base output pin for connection to the external PNP pass transistor EX PAD EX PAD EX PAD EX PAD GND Ground Ground Ground 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 11

ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 5. Maximum Ratings All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ELECTRICAL RATINGS(1) Supply Voltage at VSUP/1 and VSUP2 V Normal Operation (DC) V -0.3 to 28 SUP1/2 Transient Conditions (Load Dump) V -0.3 to 40 SUP1/2TR DC voltage on LIN/1 V Normal Operation (DC) V -28 to 28 BUSLIN Transient Conditions (Load Dump) V -28 to 40 BUSLINTR DC voltage on CANL, CANH, SPLIT V Normal Operation (DC) V -28 to 28 BUS Transient Conditions (Load Dump) V -32 to 40 BUSTR DC Voltage at SAFE V Normal Operation (DC) V -0.3 to 28 SAFE Transient Conditions (Load Dump) V -0.3 to 40 SAFETR DC Voltage at I/O-0, I/O-1, I/O-2, I/O-3 (LIN-T Pins) V Normal Operation (DC) V -0.3 to 28 I/O Transient Conditions (Load Dump) V -0.3 to 40 I/OTR DC voltage on TXD-L, TXD-L1, RXD-L, RXD-L1 VDIGLIN -0.3 to VDD +0.3 V DC voltage on TXD, RXD(3) VDIG -0.3 to VDD +0.3 V DC Voltage at INT V -0.3 to 10 V INT DC Voltage at RST VRST -0.3 to VDD +0.3 V DC Voltage at MOSI, MSIO, SCLK and CS VRST -0.3 to VDD +0.3 V DC Voltage at MUX-OUT VMUX -0.3 to VDD +0.3 V DC Voltage at DBG V -0.3 to 10 V DBG Continuous current on CANH and CANL ILH 200 mA DC voltage at VDD, 5V-CAN, VAUX, VCAUX V -0.3 to 5.5 V REG DC voltage at VBASE(2) and VBAUX V -0.3 to 40 V REG DC voltage at VE(3) VE -0.3 to 40 V DC voltage at VSENSE V -28 to 40 V SENSE Notes 1. The voltage on non-VSUP pins should never exceed the V voltage at any time or permanent damage to the device may occur. SUP 2. If the voltage delta between VSUP/1/2 and VBASE is greater than 6.0 V, the external V ballast current sharing functionality may be DD damaged. 3. Potential Electrical Over Stress (EOS) damage may occur if RXD is in contact with VE while the device is ON. 34903/4/5 Analog Integrated Circuit Device Data 12 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 5. Maximum Ratings (continued) All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ESD Capability V AECQ100(4) Human Body Model - JESD22/A114 (C = 100 pF, R = 1500 Ω) ZAP ZAP V ±8000 CANH and CANL. LIN1 Pins versus all GND pins ESD1-1 V ±2000 all other Pins including CANH and CANL ESD1-2 Charge Device Model - JESD22/C101 (C = 4.0 pF) ZAP V ±750 Corner Pins (Pins 1, 16, 17, and 32) ESD2-1 V ±500 All other Pins (Pins 2-15, 18-31) ESD2-2 Tested per IEC 61000-4-2 (C = 150 pF, R = 330 Ω) ZAP ZAP V ±15000 Device unpowered, CANH and CANL pin without capacitor, versus GND ESD3-1 V ±15000 Device unpowered, LIN, LIN1 pin, versus GND ESD3-2 V ±15000 Device unpowered, VS1/VS2 (100 nF to GND), versus GND ESD3-3 Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor on VSUP/1/2 pins (See Typical Applications on page 85) CANH, CANL without bus filter V ±9000 ESD4-1 LIN, LIN1 with and without bus filter V ±12000 ESD4-2 I/O with external components (22 k - 10 nF) V ±7000 ESD4-3 THERMAL RATINGS Junction temperature(5) T 150 °C J Ambient temperature T -40 to 125 °C A Storage temperature T -50 to 150 °C ST THERMAL RESISTANCE Thermal resistance junction to ambient(8) RθJA 50(8) °C/W Peak package reflow temperature during reflow(6), (7) T Note 7 °C PPRT Notes 4. ESD testing is performed in accordance with the Human Body Model (HBM) (C = 100 pF, R = 1500 Ω), the Charge Device Model ZAP ZAP (CDM), and Robotic (C = 4.0 pF). ZAP 5. To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not exceed 125 °C. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC34xxxD enter 34xxx), and review parametrics. 8. This parameter was measured according to Figure 9: 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 13

ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS PCB 100mm x 100mm Top side, 300 sq. mm (20mmx15mm) Bottom side Bottom view 20mm x 40mm Figure 9. PCB with Top and Bottom Layer Dissipation Area (Dual Layer) 34903/4/5 Analog Integrated Circuit Device Data 14 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 6. Static Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit POWER INPUT Nominal DC Voltage Range(9) V /V 5.5 - 28 V SUP1 SUP2 Extended DC Low Voltage Range(10) V /V 4.0 - 5.5 V SUP1 SUP2 Undervoltage Detector Thresholds, at the VSUP/1 pin, V V S1_LOW Low threshold (VSUP/1 ramp down) 5.5 6.0 6.5 High threshold (VSUP/1 ramp up) - - 6.6 Hysteresis 0.2 0.35 0.5 Note: function not active in LP mode Undervoltage Detector Thresholds, at the VSUP2 pin: V V S2_LOW Low threshold (VSUP2 ramp down) 5.5 6.0 6.5 High threshold (VSUP2 ramp up) - - 6.6 Hysteresis 0.2 0.35 0.5 Note: function not active in LP modes VSUP Overvoltage Detector Thresholds, at the VSUP/1 pin: VS_HIGH 16.5 17 18.5 V Not active in LP modes Battery loss detection threshold, at the VSUP/1 pin. BATFAIL 2.0 2.8 4.0 V VSUP/1 to turn VDD ON, VSUP/1 rising VSUP-TH1 - 4.1 4.5 V VSUP/1 to turn VDD ON, hysteresis (Guaranteed by design) VSUP-TH1HYST 150 180 mV Supply current(11), (12) I mA SUP1 - from VSUP/1 - 2.0 4.0 - from VSUP2, (5V-CAN VAUX, I/O OFF) - 0.05 0.85 Supply current, ISUP1 + ISUP2, Normal mode, VDD ON ISUP1+2 mA - 5 V-CAN OFF, VAUX OFF - 2.8 4.5 - 5 V-CAN ON, CAN interface in Sleep mode, VAUX OFF - - 5.0 - 5 V-CAN OFF, Vaux ON - - 5.5 - 5 V-CAN ON, CAN interface in TXD/RXD mode, V OFF, I/O-x disabled - - 8.0 AUX LP mode VDD OFF. Wake-up from CAN, I/O-x inputs ILPM_OFF μA VSUP ≤ 18 V, -40 to 25 °C - 15 35 VSUP ≤ 18 V, 125 °C - - 50 LP mode VDD ON (5.0 V) with VDD undervoltage and VDD ILPM_ON μA overcurrent monitoring, Wake-up from CAN, I/O-x inputs - VSUP ≤ 18 V, -40 to 25 °C, IDD = 1.0 μA - 20 - VSUP ≤ 18 V, -40 to 25 °C, IDD = 100 μA 40 65 V ≤ 18 V, 125 °C, I = 100 μA - 85 SUP DD LP mode, additional current for oscillator (used for: cyclic sense, forced Wake- I μA OSC up, and in LP V ON mode cyclic interruption and watchdog) DD V ≤ 18 V, -40 to 125 °C SUP - 5.0 9.0 Debug mode DBG voltage range V 8.0 - 10 V DBG Notes 9. All parameters in spec (ex: V regulator tolerance). DD 10. Device functional, some parameters could be out of spec. V is active, device is not in Reset mode if the lowest V undervoltage reset DD DD threshold is selected (approx. 3.4 V). CAN and I/Os are not operational. 11. In Run mode, CAN interface in Sleep mode, 5 V-CAN and V turned OFF. I at V < 50 mA. Ballast: turned OFF or not connected. AUX OUT DD 12. VSUP1 and VSUP2 supplies are internally connected on part number MC34903BDEK and MC34903BSEK. Therefore, I and I SUP1 SUP2 cannot be measured individually. 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 15

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 6. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit V VOLTAGE REGULATOR, VDD PIN DD Output Voltage V VDD = 5.0 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA VOUT-5.0 4.9 5.0 5.1 VDD = 3.3 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA VOUT-3.3 3.234 3.3 3.4 Drop voltage without external PNP pass transistor(13) V mV DROP VDD = 5.0 V, IOUT = 100 mA - 330 450 VDD = 5.0 V, IOUT = 150 mA - - 500 Drop voltage with external transistor(13) V mV DROP-B IOUT = 200 mA (I_BALLAST + I_INTERNAL) - 350 500 VSUP/1 to maintain VDD within VOUT-3.3 specified voltage range VSUP1-3.3 V VDD = 3.3 V, IOUT = 150 mA 4.0 - - VDD = 3.3 V, IOUT = 200 mA, external transistor implemented 4.0 - - External ballast versus internal current ratio (I_BALLAST = K x Internal current) K 1.5 2.0 2.5 Output Current limitation, without external transistor I 150 350 550 mA LIM Temperature pre-warning (Guaranteed by design) T - 140 - °C PW Thermal shutdown (Guaranteed by design) T 160 - - °C SD Range of decoupling capacitor (Guaranteed by design)(14) C 4.7 - 100 μF EXT LP mode VDD ON, IOUT ≤ 50 mA (time limited) VDDLP V VDD = 5.0 V, 5.6 V ≤ VSUP ≤ 28 V 4.75 5.0 5.25 VDD = 3.3 V, 5.6 V ≤ VSUP ≤ 28 V 3.135 3.3 3.465 LP mode VDD ON, dynamic output current capability (Limited duration. Ref. to LP-IOUTDC - - 50 mA device description). LP VDD ON mode: LP-ITH mA Overcurrent Wake-up threshold. 1.0 3.0 - Hysteresis 0.1 1.0 - LP mode VDD ON, drop voltage, at IOUT = 30 mA (Limited duration. Ref. to LP-VDROP - 200 400 mV device description) (13) LP mode VDD ON, min VSUP operation (Below this value, a VDD, undervoltage LP-MINVS 5.5 - - V reset may occur) VDD when VSUP < VSUP-TH1, at I_VDD ≤ 10 μA (Guaranteed by design) VDD_OFF - - 0.3 V VDD when VSUP ≥ VSUP-TH1, at I_VDD ≤ 40 mA (Guaranteed with parameter VDD_START UP 3.0 - - V V SUP-TH1 Notes 13. For 3.3 V V devices, the drop-out voltage test condition leads to a V below the min V threshold (4.0 V). As a result, the dropout DD SUP SUP voltage parameter cannot be specified. 14. The regulator is stable without an external capacitor. Usage of an external capacitor is recommended for AC performance. 34903/4/5 Analog Integrated Circuit Device Data 16 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 6. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit VOLTAGE REGULATOR FOR CAN INTERFACE SUPPLY, 5.0 V-CAN PIN Output voltage, VSUP/2 = 5.5 to 40 V V 5V IOUT 0 to 160 mA -C OUT 4.75 5.0 5.25 Output Current limitation (15) 5V 160 280 - mA -C ILIM Undervoltage threshold 5V 4.1 4.5 4.7 V -C UV Thermal shutdown (Guaranteed by design) 5V 160 - - °C -CTS External capacitance (Guaranteed by design) C 1.0 - 100 μF EXT-CAN V AUXILIARY OUTPUT, 5.0 AND 3.3 V SELECTABLE PIN VB-AUX, VC-AUX, VAUX VAUX output voltage V V AUX VAUX = 5.0 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA 4.75 5.0 5.25 VAUX = 3.3 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA 3.135 3.3 3.465 VAUX undervoltage detector (VAUX configured to 5.0 V) V V AUX-UVTH Low Threshold 4.2 4.5 4.70 Hysteresis 0.06 - 0.12 VAUX undervoltage detector (VAUX configured to 3.3 V, default value) 2.75 3.0 3.135 VAUX overcurrent threshold detector V mA AUX-ILIM VAUX set to 3.3 V 250 360 450 VAUX set to 5.0 V 230 330 430 External capacitance (Guaranteed by design) V 2.2 - 100 μF AUX CAP UNDERVOLTAGE RESET AND RESET FUNCTION, RST PIN VDD undervoltage threshold down - 90% VDD (VDD 5.0 V)(16), (18) VRST-TH1 4.5 4.65 4.85 V VDD undervoltage threshold up - 90% VDD (VDD 5.0 V) - - 4.90 VDD undervoltage threshold down - 90% VDD (VDD 3.3 V)(16), (18) 2.75 3.0 3.135 VDD undervoltage threshold up - 90% VDD (VDD 3.3 V) - - 3.135 VDD undervoltage reset threshold down - 70% VDD (VDD 5.0 V)(17), (18) VRST-TH2-5 2.95 3.2 3.45 V Hysteresis V mV RST-HYST for threshold 90% VDD, 5.0 V device 20 - 150 for threshold 70% VDD, 5.0 V device 10 - 150 Hysteresis 3.3 V V DD for threshold 90% V , 3.3 V device 10 - 150 DD VDD undervoltage reset threshold down - LP VDD ON mode VRST-LP V (Note: device change to Normal Request mode). VDD 5.0 V 4.0 4.5 4.85 (Note: device change to Normal Request mode). VDD 3.3 V 2.75 3.0 3.135 Notes 15. Current limitation will be reported by setting a flag. 16. Generate a Reset or an INT. SPI programmable 17. Generate a Reset 18. In Non-LP modes 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 17

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 6. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit UNDERVOLTAGE RESET AND RESET FUNCTION, RST PIN (CONTINUED) Reset VOL @ 1.5 mA, VSUP 5.5 to 28 V VOL - 300 500 mV Current limitation, Reset activated, VRESET = 0.9 x VDD IRESET LOW 2.5 7.0 10 mA Pull-up resistor (to VDD pin) R 8.0 11 15 kΩ PULL-UP VSUP to guaranteed reset low level(19) VSUP-RSTL 2.5 - - V Reset input threshold V V RST-VTH Low threshold, VDD = 5.0 V 1.5 1.9 2.2 High threshold, VDD = 5.0 V 2.5 3.0 3.5 Low threshold, V = 3.3 V 0.99 1.17 1.32 DD High threshold, V = 3.3 V 1.65 2.0 2.31 DD Reset input hysteresis V 0.5 1.0 1.5 V HYST I/O PINS WHEN FUNCTION SELECTED IS OUTPUT I/O-0 HS switch drop @ I = -12 mA, V = 10.5 V V - 0.5 1.4 V SUP I/O-0 HSDRP I/O-2 and I/O-3 HS switch drop @ I = -20 mA, V = 10.5 V V - 0.5 1.4 V SUP I/O-2-3 HSDRP I/O-1, HS switch drop @ I = -400 μA, V = 10.5 V V - 0.4 1.4 V SUP I/O-1 HSDRP I/O-0, I/O-1 LS switch drop @ I = 400 μA, V = 10.5 V V - 0.4 1.4 V SUP I/O-01 LSDRP Leakage current, I/O-x ≤ V I - 0.1 3.0 μA SUP I/O_LEAK I/O PINS WHEN FUNCTION SELECTED IS INPUT Negative threshold V 1.4 2.0 2.9 V I/O_NTH Positive threshold V 2.1 3.0 3.8 V I/O_PTH Hysteresis V 0.2 1.0 1.4 V I/O_HYST Input current, I/O ≤ VSUP/2 I -5.0 1.0 5.0 μA I/O_IN I/O-0 and I/O-1 input resistor. I/O-0 (or I/O-1) selected in R - 100 - kΩ I/O-X register, 2.0 V < V <16 V (Guaranteed by design). I/O-X VSENSE INPUT VSENSE undervoltage threshold (Not active in LP modes) V V SENSE_TH Low Threshold 8.1 8.6 9.0 High threshold - - 9.1 Hysteresis 0.1 0.25 0.5 Input resistor to GND. In all modes except in LP modes. (Guaranteed by R - 125 - kΩ VSENSE design). Notes 19. Reset must be kept low 34903/4/5 Analog Integrated Circuit Device Data 18 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 6. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit ANALOG MUX OUTPUT Output Voltage Range, with external resistor to GND >2.0 kΩ V 0.0 - V - 0.5 V OUT_MAX DD Internal pull-down resistor for regulator output current sense R 0.8 1.9 2.8 kΩ MI External capacitor at MUX OUTPUT(20) (Guaranteed by design) C - - 1.0 nF MUX Chip temperature sensor coefficient (Guaranteed by design and device TEMP mv/°C -COEFF characterization) VDD = 5.0 V 20 21 22 VDD = 3.3 V 13.2 13.9 14.6 Chip temperature: MUX-OUT voltage V V TEMP VDD = 5.0 V, TA = 125 °C 3.6 3.75 3.9 VDD = 3.3 V, TA = 125 °C 2.45 2.58 2.65 Chip temperature: MUX-OUT voltage (guaranteed by design and V V TEMP(GD) characterization) TA = -40 °C, VDD = 5.0 V 0.12 0.30 0.48 TA = 25 °C, VDD = 5.0 V 1.5 1.65 1.8 T = -40 °C, V = 3.3 V 0.07 0.19 0.3 A DD T = 25 °C, V = 3.3 V 1.08 1.14 1.2 A DD Gain for VSENSE, with external 1.0 k 1% resistor VSENSE GAIN VDD = 5.0 V 5.42 5.48 5.54 VDD = 3.3 V 8.1 8.2 8.3 Offset for VSENSE, with external 1.0 k 1% resistor VSENSE -20 - 20 mV OFFSET Divider ratio for VSUP/1 VSUP/1 RATIO VDD = 5.0 V 5.335 5.5 5.665 VDD = 3.3 V 7.95 8.18 8.45 Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: VI/O RATIO VDD = 5.0 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to 1) 3.8 4.0 4.2 VDD = 5.0 V, (Gain, MUX-OUT register bit 3 set to 0) - 2.0 - V = 3.3 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to 1) 5.6 5.8 6.2 DD V = 3.3 V, (Gain, MUX-OUT register bit 3 set to 0) - 1.3 - DD Internal reference voltage V V REF VDD = 5.0 V 2.45 2.5 2.55 VDD = 3.3 V 1.64 1.67 1.7 Current ratio between VDD output & IOUT at MUX-OUT IDD_RATIO (I at MUX-OUT = I out / I ) OUT DD DD_RATIO At IOUT = 50 mA 80 97 115 I_OUT from 25 to 150 mA 62.5 97 117 SAFE OUTPUT SAFE low level, at I = 500 μA V 0.0 0.2 1.0 V OL Safe leakage current (VDD low, or device unpowered). VSAFE 0 to 28 V. ISAFE-IN - 0.0 1.0 μA Notes 20. When C is higher than CMUX, a serial resistor must be inserted 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 19

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 6. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit INTERRUPT Output low voltage, IOUT = 1.5 mA VOL - 0.2 1.0 V Pull-up resistor RPU 6.5 10 14 kΩ Output high level in LP VDD ON mode (Guaranteed by design) VOH-LPVDDON 3.9 4.3 V Leakage current INT voltage = 10 V (to allow high-voltage on MCU INT pin) V - 35 100 μA MAX Sink current, VINT > 5.0 V, INT low state I SINK 2.5 6.0 10 mA MISO, MOSI, SCLK, CS PINS Output low voltage, IOUT = 1.5 mA (MISO) VOL - - 1.0 V Output high voltage, IOUT = -0.25 mA (MISO) VOH VDD -0.9 - V Input low voltage (MOSI, SCLK,CS) V - - 0.3 x V V IL DD Input high voltage (MOSI, SCLK,CS) V 0.7 x V - - V IH DD Tri-state leakage current (MISO) I -2.0 - 2.0 μA HZ Pull-up current (CS) I 200 370 500 μA PU CAN LOGIC INPUT PINS (TXD) High Level Input Voltage V 0.7 x V - V + 0.3 V IH DD DD Low Level Input Voltage V -0.3 - 0.3 x V V IL DD Pull-up Current, TXD, VIN = 0 V IPDWN µA VDD =5.0 V -850 -650 -200 VDD =3.3 V -500 -250 -175 CAN DATA OUTPUT PINS (RXD) Low Level Output Voltage VOUT V LOW IRXD = 5.0 mA 0.0 - 0.3 x VDD High Level Output Voltage VOUT V HIGH IRX = -3.0 mA 0.7 x VDD - VDD High Level Output Current IOUT mA HIGH VRXD = VDD - 0.4 V 2.5 5.0 9.0 Low Level Input Current IOUT mA LOW VRXD = 0.4 V 2.5 5.0 9.0 34903/4/5 Analog Integrated Circuit Device Data 20 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 6. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit CAN OUTPUT PINS (CANH, CANL) Bus pins common mode voltage for full functionality VCOM -12 - 12 V Differential input voltage threshold VCANH-VCANL 500 - 900 mV Differential input hysteresis VDIFF-HYST 50 - - mV Input resistance RIN 5.0 - 50 kΩ Differential input resistance RIN-DIFF 10 - 100 kΩ Input resistance matching RIN-MATCH -3.0 0.0 3.0 % CANH output voltage (45 Ω < RBUS < 65 Ω) VCANH V TXD dominant state 2.75 3.5 4.5 TXD recessive state 2.0 2.5 3.0 CANL output voltage (45 Ω < RBUS < 65 Ω) VCANL V TXD dominant state 0.5 1.5 2.25 TXD recessive state 2.0 2.5 3.0 Differential output voltage (45 Ω < RBUS < 65 Ω) VOH-VOL V TXD dominant state 1.5 2.0 3.0 TXD recessive state -0.5 0.0 0.05 CAN H output current capability - Dominant state I - - -30 mA CANH CAN L output current capability - Dominant state I 30 - - mA CANL CANL overcurrent detection - Error reported in register I 75 120 195 mA CANL-OC CANH overcurrent detection - Error reported in register I -195 -120 -75 mA CANH-OC CANH, CANL input resistance to GND, device supplied, CAN in Sleep mode, R 5.0 - 50 kΩ INSLEEP V_CANH, V_CANL from 0 to 5.0 V CANL, CANH output voltage in LP VDD OFF and LP VDD ON modes VCANLP -0.1 0.0 0.1 V CANH, CANL input current, VCANH, VCANL = 0 to 5.0 V, device unpowered I - 3.0 10 µA CAN-UN_SUP1 (VSUP, VDD, 5V-CAN: open).(21) CANH, CANL input current, VCANH, VCANL = -2.0 to 7.0 V, device I - - 250 µA CAN-UN_SUP2 unpowered (VSUP, VDD, 5V-CAN: open).(21) Differential voltage for recessive bit detection in LP mode(22) V - - 0.4 V DIFF-R-LP Differential voltage for dominant bit detection in LP mode(22) V 1.15 - - V DIFF-D-LP CANH AND CANL DIAGNOSTIC INFORMATION CANL to GND detection threshold V 1.6 1.75 2.0 V LG CANH to GND detection threshold V 1.6 1.75 2.0 V HG CANL to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V VLVB - VSUP -2.0 - V CANH to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V VHVB - VSUP -2.0 - V CANL to VDD detection threshold V 4.0 V -0.43 - V L5 DD CANH to VDD detection threshold V 4.0 V -0.43 - V H5 DD Notes 21. VSUP, VDD, 5V-CAN: shorted to GND, or connected to GND via a 47 k resistor instances are guaranteed by design and device characterization. 22. Guaranteed by design and device characterization. 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 21

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 6. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit SPLIT Output voltage V V SPLIT Loaded condition ISPLIT = ±500 µA 0.3 x VDD 0.5 x VDD 0.7 x VDD Unloaded condition Rmeasure > 1.0 MΩ 0.45 x 0.5 x V 0.55 x V DD DD V DD Leakage current I µA LSPLIT -12 V < VSPLIT < +12 V - 0.0 5.0 -22 to -12 V < VSPLIT < +12 to +35 V - - 200 LIN TERMINALS (LIN-T/1) LIN-T1 HS switch drop @ I = -20 mA, V > 10.5 V V - 1.0 1.4 V SUP LT_HSDRP LIN1 34903D/5D PIN - LIN 34903S/5S PIN (Parameters guaranteed for V V 7.0 V ≤ V ≤ 18 V) SUP/1, SUP2 SUP Operating Voltage Range V 8.0 - 18 V BAT Supply Voltage Range V 7.0 - 18 V SUP Current Limitation for Driver Dominant State I mA BUS_LIM Driver ON, VBUS = 18 V 40 90 200 Input Leakage Current at the receiver I mA BUS_PAS_DOM Driver off; VBUS = 0 V; VBAT = 12 V -1.0 - - Leakage Output Current to GND I µA BUS_PAS_REC Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT - - 20 Control unit disconnected from ground (Loss of local ground must not affect I mA BUS_NO_GND communication in the residual network) -1.0 - 1.0 GND = V ; V = 12 V; 0 < V < 18 V (Guaranteed by design) DEVICE SUP BAT BUS VBAT Disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V (Node has to IBUSNO_BAT µA sustain the current that can flow under this condition. Bus must remain - - 100 operational under this condition). (Guaranteed by design) Receiver Dominant State V V BUSDOM SUP - - 0.4 Receiver Recessive State V V BUSREC SUP 0.6 - - Receiver Threshold Center V V BUS_CNT SUP (VTH_DOM + VTH_REC)/2 0.475 0.5 0.525 Receiver Threshold Hysteresis V V HYS SUP (VTH_REC - VTH_DOM) - - 0.175 LIN Wake-up threshold from LP VDD ON or LP VDD OFF mode VBUSWU - 5.3 5.8 V LIN Pull-up Resistor to VSUP RSLAVE 20 30 60 kΩ Overtemperature Shutdown (Guaranteed by design) T 140 160 180 °C LINSD Overtemperature Shutdown Hysteresis (Guaranteed by design) T - 10 - °C LINSD_HYS 34903/4/5 Analog Integrated Circuit Device Data 22 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 7. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ V ≤ 28 V, - 40 °C ≤ T ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical SUP A values noted reflect the approximate parameter means at T 25 °C under nominal conditions, unless otherwise noted. A = Characteristic Symbol Min Typ Max Unit SPI TIMING SPI Operation Frequency (MISO cap = 50 pF) FREQ 0.25 - 4.0 MHz SCLK Clock Period t 250 - N/A ns PCLK SCLK Clock High Time t 125 - N/A ns WSCLKH SCLK Clock Low Time t 125 - N/A ns WSCLKL Falling Edge of CS to Rising Edge of SCLK t ns LEAD “C” version 30 - N/A All others 550 - N/A Falling Edge of SCLK to Rising Edge of CS t 30 - N/A ns LAG MOSI to Falling Edge of SCLK t 30 - N/A ns SISU Falling Edge of SCLK to MOSI t 30 - N/A ns SIH MISO Rise Time (CL = 50 pF) t - - 30 ns RSO MISO Fall Time (CL = 50 pF) t - - 30 ns FSO Time from Falling to MISO Low-impedance t - - 30 ns SOEN Time from Rising to MISO High-impedance t - - 30 SODIS Time from Rising Edge of SCLK to MISO Data Valid t - - 30 ns VALID Delay between falling and rising edge on CS t μs CSLOW “C” version 1.0 - N/A All others 5.5 - N/A CS Chip Select Low Timeout Detection t 2.5 - - ms CS-TO SUPPLY, VOLTAGE REGULATOR, RESET VSUP undervoltage detector threshold deglitcher tVS_LOW1/ 30 50 100 μs 2_DGLT Rise time at turn ON. V from 1.0 to 4.5 μV. 2.2 μF at the VDD pin. t 50 250 800 μs DD RISE-ON Deglitcher time to set RST pin low t 20 30 40 μs RST-DGLT RESET PULSE DURATION VDD undervoltage (SPI selectable) tRST-PULSE ms short, default at power on when BATFAIL bit set 0.9 1.0 1.4 medium 4.0 5.0 6.5 medium long 8.5 10 12 long 17 20 24 Watchdog reset tRST-WD 0.9 1.0 1.4 ms I/O INPUT Deglitcher time (Guaranteed by design) t 19 30 41 μs IODT VSENSE INPUT Undervoltage deglitcher time t 30 - 100 μs BFT 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 23

ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 7. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ V ≤ 28 V, - 40 °C ≤ T ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical SUP A values noted reflect the approximate parameter means at T 25 °C under nominal conditions, unless otherwise noted. A = Characteristic Symbol Min Typ Max Unit INTERRUPT INT pulse duration (refer to SPI for selection. Guaranteed by design) t μs INT-PULSE short (25 to 125 °C) 20 25 35 short (-40 °C) 20 25 40 long (25 to 125 °C) 90 100 130 long (-40 °C) 90 100 140 STATE DIGRAM TIMINGS Delay for SPI Timer A, Timer B or Timer C write command after entering Normal t 60 - - μs D_NM mode (No command should occur within t . D_NM t delay definition: from CS rising edge of “Go to Normal mode (i.e. 0x5A00)” D_NM command to CS falling edge of “Timer write” command) Tolerance for: watchdog period in all modes, FWU delay, Cyclic sense period t -10 - 10 % TIMING-ACC and active time, Cyclic Interrupt period, LP mode overcurrent (unless otherwise noted)(26) CAN DYNAMIC CHARACTERISTICS TXD Dominant State Timeout t 300 600 1000 µs DOUT Bus dominant clamping detection t 300 600 1000 µs DOM Propagation loop delay TXD to RXD, recessive to dominant (Fast slew rate) t 60 120 210 ns LRD Propagation delay TXD to CAN, recessive to dominant t - 70 110 ns TRD Propagation delay CAN to RXD, recessive to dominant t - 45 140 ns RRD Propagation loop delay TXD to RXD, dominant to recessive (Fast slew rate) t 100 120 200 ns LDR Propagation delay TXD to CAN, dominant to recessive t - 75 150 ns TDR Propagation delay CAN to RXD, dominant to recessive t - 50 140 ns RDR Loop time TXD to RXD, Medium Slew Rate (Selected by SPI) t ns LOOP-MSL Recessive to Dominant - 200 - Dominant to Recessive - 200 - Loop time TXD to RXD, Slow Slew Rate (Selected by SPI) t ns LOOP-SSL Recessive to Dominant - 300 - Dominant to Recessive - 300 - CAN Wake-up filter time, single dominant pulse detection(23) (See Figure 31) t 0.5 2.0 5.0 μs CAN-WU1-F CAN Wake-up filter time, 3 dominant pulses detection(24) t 300 - - ns CAN-WU3-F CAN Wake-up filter time, 3 dominant pulses detection timeout(25) (See t - - 120 μs CAN-WU3-TO Figure 32) Notes 23. No Wake-up for single pulse shorter than t min. Wake-up for single pulse longer than t max. CAN-WU1 CAN-WU1 24. Each pulse should be greater than t min. Guaranteed by design, and device characterization. CAN-WU3-F 25. The 3 pulses should occur within t . Guaranteed by design, and device characterization. CAN-WU3-TO 26. Guaranteed by design. 34903/4/5 Analog Integrated Circuit Device Data 24 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 7. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ V ≤ 28 V, - 40 °C ≤ T ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical SUP A values noted reflect the approximate parameter means at T 25 °C under nominal conditions, unless otherwise noted. A = Characteristic Symbol Min Typ Max Unit LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION BUS LOAD R AND C 1.0 NF / 1.0 KΩ, 6.8 NF / 660 Ω, 10 NF / 500 Ω. SEE Figure 14, PAGE 28. BUS BUS Duty Cycle 1: D1 TH = 0.744 * V REC(MAX) SUP TH = 0.581 * V DOM(MAX) SUP D1 = t /(2 x t ), t = 50 µs, 7.0 V ≤ V ≤ 18 V 0.396 - - BUS_REC(MIN) BIT BIT SUP Duty Cycle 2: D2 TH = 0.422 * V REC(MIN) SUP TH = 0.284 * V DOM(MIN) SUP D2 = t /(2 x t ), t = 50 µs, 7.6 V ≤ V ≤ 18 V - - 0.581 BUS_REC(MAX) BIT BIT SUP LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION BUS LOAD R AND C 1.0 NF / 1.0 KΩ, 6.8 NF / 660 Ω, 10 NF / 500 Ω. MEASUREMENT THRESHOLDS. SEE Figure 15, PAGE 29. BUS BUS Duty Cycle 3: D3 TH = 0.778 * V REC(MAX) SUP TH = 0.616 * V DOM(MAX) SUP D3 = t /(2 x t ), t = 96 µs, 7.0 V ≤ V ≤ 18 V 0.417 - - BUS_REC(MIN) BIT BIT SUP Duty Cycle 4: D4 TH = 0.389 * V REC(MIN) SUP TH = 0.251 * V DOM(MIN) SUP D4 = t /(2 x t ), t = 96 µs, 7.6 V ≤ V ≤ 18 V - - 0.590 BUS_REC(MAX) BIT BIT SUP LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming Mode) SR - 20 - V / μs FAST LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS V FROM 7.0 TO 18 V, BUS LOAD R AND C 1.0 NF / 1.0 KΩ, 6.8 NF / 660 Ω, 10 NF / 500 Ω. SEE Figure 14, PAGE 28. SUP BUS BUS Propagation Delay and Symmetry (See Figure 14, page 27 and Figure 15, μs page 29) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) t REC_PD - 4.2 6.0 Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR t REC_SYM - 2.0 - 2.0 Bus Wake-up Deglitcher (LP VDD OFF and LP VDD ON modes) (See Figure 16, t PROPWL 42 70 95 μs page 28 for LP V OFF mode and Figure 17, page 29 for LP mode) DD Bus Wake-up Event Reported μs From LP VDD OFF mode t WAKE_LPVDD - - 1500 OFF From LP VDD ON mode t WAKE_LPVDD 1.0 - 12 ON TXD Permanent Dominant State Delay (Guaranteed by design) t 0.65 1.0 1.35 s TXDDOM 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 25

ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS tPCLK CS tLEAD tWCLKH tLAG SCLK tWCLKL tSISU tSIH MOSI Undefined Di 0 Don’t Care Di n Don’t Care tVALID tSODIS tSOEN MISO Do 0 Do n tCSLOW Figure 10. SPI Timings t LRD TXD 0.7 x V DD 0.3 x V DD t LDR RXD 0.7 x VDD 0.3 x V DD Figure 11. CAN Signal Propagation Loop Delay TXD to RXD 34903/4/5 Analog Integrated Circuit Device Data 26 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS t TRD TXD 0.7 x V DD 0.3 x VDD t TDR 0.9V V DIFF t 0.5V RRD t RDR RXD 0.7 x V DD 0.3 x V DD Figure 12. CAN Signal Propagation Delays TXD to CAN and CAN to RXD . 12V 10μF VSUP 5V_CAN 100nF 22μF CANH Signal generator TXD RBUS CBus 60Ω 100pF CANL RXD GND SPLIT All pins are not shown 15pF Figure 13. Test Circuit for CAN Timing Characteristics 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 27

ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TXD t t BIT BIT t t V BUS_DOM(MAX) BUS_REC(MIN) LIN_REC THREC(MAX) 74.4% VSUP Thresholds of receiving node 1 THDOM(MAX) 58.1% VSUP LIN THREC(MIN) 42.2% VSUP Trehcreeisvhinogld nso odfe 2 THDOM(MIN) 28.4% VSUP tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDR(2) tREC_PDF(2) Figure 14. LIN Timing Measurements for Normal Slew Rate 34903/4/5 Analog Integrated Circuit Device Data 28 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TXD t t BIT BIT t t V BUS_DOM(MAX) BUS_REC(MIN) LIN_REC THREC(MAX) 77.8% VSUP Thresholds of receiving node 1 THDOM(MAX) 61.6% VSUP LIN THREC(MIN) 38.9% VSUP Trehcreeisvhinogld nso odfe 2 THDOM(MIN) 25.1% VSUP tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDR(2) tREC_PDF(2) Figure 15. LIN Timing Measurements for Slow Slew Rate VREC LIN VBUSWU 0.4VSUP Dominant level VDD 3V TPROPWL TWAKE Figure 16. LIN Wake-up LP V OFF Mode Timing DD 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 29

ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS V LIN_REC LIN 0.4VSUP VBUSWU Dominant level IRQ TPROPWL TWAKE IRQ stays low until SPI reading command Figure 17. LIN Wake-up LP V ON Mode Timing DD 34903/4/5 Analog Integrated Circuit Device Data 30 Freescale Semiconductor

FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The MC34903_4_5 is the second generation of System - Built in LIN interface, compliant to LIN 2.1 and J2602-2 Basis Chip, combining: specification, with local and bus failure diagnostic and - Advanced power management unit for the MCU, the protection. integrated CAN interface and for the additional ICs such as - Innovative hardware configurable fail-safe state machine sensors, CAN transceiver. solution. - Built in enhanced high speed CAN interface (ISO11898- - Multiple LP modes, with low current consumption. 2 and -5), with local and bus failure diagnostic, protection, - Family concept with pin compatibility; with and without and fail-safe operation mode. LIN interface devices. FUNCTIONAL PIN DESCRIPTION POWER SUPPLY (VSUP/1 AND VSUP2) (Wake-up detection, timer start for overcurrent duration monitoring or watchdog refresh). Note: VSUP1 and VSUP2 supplies are externally available on all devices except the 34903D, 34903S, and 34903P, where these are connected internally. EXTERNAL TRANSISTOR Q1 (VE AND VB) VSUP1 is the input pin for the internal supply and the VDD The device has a dedicated circuit to allow usage of an regulator. VSUP2 is the input pin for the 5 V-CAN regulator, external “P” type transistor, with the objective to share the LIN’s interfaces and I/O functions. The VSUP block includes power dissipation between the internal transistor of the VDD over and undervoltage detections which can generate regulator and the external transistor. The recommended interrupt. The device includes a loss of battery detector bipolar PNP transistor is MJD42C or BCP52-16. connected to VSUP/1. When the external PNP is connected, the current is shared Loss of battery is reported through a bit (called BATFAIL). between the internal path transistor and the external PNP, This generates a POR (Power On Reset). with the following typical ratio: 1/3 in the internal transistor and 2/3 in the external PNP. The PNP activation and control VDD VOLTAGE REGULATOR (VDD) is done by SPI. The device is able to operate without an external The regulator has two main modes of operation (Normal transistor. In this case, the VE and VB pins must remain mode and LP mode). It can operate with or without an open. external PNP transistor. In Normal mode, without external PNP, the max DC 5 V-CAN VOLTAGE REGULATOR FOR CAN AND capability is 150 mA. Current limitation, temperature pre- ANALOG MUX warning flag and overtemperature shutdown features are included. When V is turned ON, rise time from 0 to 5.0 V is This regulator is supplied from the VSUP/2 pin. A capacitor DD controlled. Output voltage is 5.0 V. A 3.3 V option is available is required at 5 V-CAN pin. Analog MUX and part of the LIN via dedicated part number. interfaces are supplied from 5 V-CAN. Consequently, the If current higher than 150 mA is required, an external PNP 5 V-CAN must be ON in order to have Analog MUX operating transistor must be connected to VE (PNP emitter) and VB and to have the LIN interface operating in TXD/RXD mode. (PNP base) pins, in order to increase total current capability The 5 V-CAN regulator is OFF by default and must be and share the power dissipation between internal VDD turned ON by SPI. In Debug mode, the 5 V-CAN is ON by transistor and the external transistor. See External Transistor default. Q1 (VE and VB). The PNP can be used even if current is less than 150 mA, depending upon ambient temperature, V AUXILIARY OUTPUT, 5.0 AND 3.3 V maximum supply and thermal resistance. Typically, above SELECTABLE (VB-AUX, VC-AUX, AND VCAUX) - 100-200 mA, an external ballast transistor is recommended. Q2 The VAUX block is used to provide an auxiliary voltage VDD REGULATOR IN LP MODE output, 5.0 or 3.3 V, selectable by the SPI. It uses an external When the device is set in LP VDD ON mode, the VDD PNP pass transistor for flexibility and power dissipation regulator is able to supply the MCU with a DC current below constraints. The external recommended bipolar transistors typically 1.5 mA (LP-ITH). Transient current can also be are MJD42C or BCP52-16. supplied up to a tenth of a mA. Current in excess of 1.5 mA An overcurrent and undervoltage detectors are provided. is detected, and this event is managed by the device logic 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 31

FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION V is controlled via the SPI, and can be turned ON or When cyclic sense is used, I/O-0 is the HS/LS switch, I/O- AUX OFF. V low threshold detection and overcurrent 1, -2 and -3 are the wake inputs. AUX information will disable VAUX, and are reported in the SPI and I/O-2 and I/O-3 pins share the LIN Master pin function. can generate INT. VAUX is OFF by default and must be turned ON by the SPI. VSENSE INPUT (VSENSE) This pin can be connected to the battery line (before the UNDERVOLTAGE RESET AND RESET FUNCTION reverse battery protection diode), via a serial resistor and a (RST) capacitor to GND. It incorporates a threshold detector to The RST pin is an open drain structure with an internal sense the battery voltage and provide a battery early pull-up resistor. The LS driver has limited current capability warning. It also includes a resistor divider to measure the when asserted low, in order to tolerate a short to 5.0 V. The VSENSE voltage via the MUX-OUT pin. RST pin voltage is monitored in order to detect failure (e.g. RST pin shorted to 5.0 V or GND). MUX-OUTPUT (MUXOUT) The RST pin reports an undervoltage condition to the MCU The MUX-OUT pin (Figure 18) delivers an analog voltage at the VDD pin, as a RST failure in the watchdog refresh to the MCU A/D input. The voltage to be delivered to MUX- operation. VDD undervoltage reset also operates in LP VDD OUT is selected via the SPI, from one of the following ON mode. functions: V , V , I/O-0, I/O-1, Internal 2.5 V SUP/1 SENSE Two VDD undervoltage thresholds are included. The upper reference, die temperature sensor, VDD current copy. (typically 4.65 V, RST-TH1-5) can lead to a Reset or an Voltage divider or amplifier is inserted in the chain, as Interrupt. This is selected by the SPI. When “RST-TH2-5“is shown in Figure 18. selected, in Normal mode, an INT is asserted when VDD falls For the V current copy, a resistor must be added to the DD below “R “, then, when V falls below “R ” a ST-TH1-5 DD ST-TH2-5 MUX-OUT pin, to convert current into voltage. Device Reset will occur. This will allow the MCU to operate in a includes an internal 2.0 k resistor selectable by the SPI. degraded mode (i.e., with 4.0 V V ). DD Voltage range at MUX-OUT is from GND to VDD. It is automatically limited to V (max 3.3 V for 3.3 V part I/O PINS (I/O-0: I/O-3) DD numbers). I/Os are configurable input/output pins. They can be used The MUX-OUT buffer is supplied from 5 V-CAN regulator, for small loads or to drive external transistors. When used as so the 5 V-CAN regulator must be ON in order to have: output drivers, the I/Os are either a HS or LS type. They can 1) MUX-OUT functionality and also be set to high-impedance. I/Os are controlled by the SPI and at power on, the I/Os are set as inputs. They include 2) SPI selection of the analog function. overload protection by temperature or excess of a voltage If the 5 V-CAN is OFF, the MUX-OUT voltage is near GND drop. and the SPI command that selects one of the analog inputs When I/O-0/-1/-2/-3 voltage is greater than VSUP/2 is ignored. voltage, the leakage current (I ) parameter is not Delay must be respected between SPI commands for 5 V- I/O_LEAK applicable CAN turned ON and SPI to select MUX-OUT function. The • I/O-0 and I/O-1 will have current flowing into the device delay depends mainly upon the 5 V-CAN capacitor and load through three diodes limited by an 80 kOhm resistor (in on 5 V-CAN. series). The delay can be estimated using the following formula: • I/O-2 and I/O-3 will have unlimited current flowing into the delay = C(5 V-CAN) x U (5.0 V) / I_lim 5 V-CAN. device through one diode. C = cap at 5 V-CAN regulator, U = 5.0 V, In LP mode, the state of the I/O can be turned ON or OFF, I 5 V-CAN = min current limit of 5 V-CAN regulator _LIM with extremely low power consumption (except when there is (parameter 5 V ). -C ILIM a load). Protection is disabled in LP mode. 34903/4/5 Analog Integrated Circuit Device Data 32 Freescale Semiconductor

FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION V BAT D1 S_in V DD-I_COPY Multiplexer VSUP/1 VSENSE S_in S_iddc 5V-CAN RSENSE 1.0k 5V-CAN MCU MUX-OUT buffer A/D in S_in I/O-0 S_g3.3 RMI RM(*) S_ir S_I/O_att S_g5 (*)Optional S_in I/O-1 Temp All swicthes and resistor are configured and controlled via the SPI RM: internal resistor connected when VREG current monitor is used S_g3.3 and S_g5 for 5.0 V or 3.3 V VDD versions VREF: 2.5V S_iddc to select VDD regulator current copy S_in1 for LP mode resistor bridge disconnection S_I/O_att S_ir to switch on/off of the internal RMI resistor S_I/O_att for I/O-0 and I/O-1 attenuation selection Figure 18. Analog Multiplexer Block Diagram DGB (DGB) AND DEBUG MODE Flexibility is provided to select SAFE output operation via a resistor at the DBG pin or via a SPI command. The SPI Primary Function command has higher priority than the hardware selection via Debug resistor. It is an input used to set the device in Debug mode. This is achieved by applying a voltage between 8.0 and 10 V at the When the Debug mode is selected, the SAFE modes DEBUG pin and then, powering up the device (See State cannot be configured via the resistor connected at DBG pin. Diagram). When the device leaves the INIT Reset mode and enters into INIT mode, it detects the voltage at the DEBUG SAFE pin to be between a range of 8.0 to 10 V, and activates the Debug mode. Safe Output Pin When Debug mode is detected, no Watchdog SPI refresh This pin is an output and is asserted low when a fault event commands are necessary. This allows an easy debug of the occurs. The objective is to drive electrical safe circuitry and hardware and software routines (i.e. SPI commands). set the ECU in a known state, independent of the MCU and When the device is in Debug mode it is reported by the SPI SBC, once a failure has been detected. flag. While in Debug mode, and the voltage at DBG pin falls The SAFE output structure is an open drain, without a pull- below the 8.0 to 10 V range, the Debug mode is left, and the up. device starts the watchdog operation, and expects the proper watchdog refresh. The Debug mode can be left by SPI. This INTERRUPT (INT) is recommended to avoid staying in Debug mode when an The INT output pin is asserted low or generates a low unwanted Debug mode selection (FMEA pin) is present. The pulse when an interrupt condition occurs. The INT condition SPI command has a higher priority than providing 8.0 to 10 V is enabled in the INT register. The selection of low level or at the DEBUG pin. pulse and pulse duration are selected by SPI. Secondary Function No current will flow inside the INT structure when VDD is low, and the device is in LP V OFF mode. This allows the DD The resistor connected between the DBG pin and the GND connection of an external pull-up resistor and connection of selects the Fail-Safe mode operation. DBG pin can also be an INT pin from other ICs without extra consumption in connected directly to GND (this prevents the usage of Debug unpowered mode. mode). 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 33

FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION INT has an internal pull-up structure to V . In LP V ON The MC34903P, and MC34904 do not have a LIN DD DD mode, a diode is inserted in series with the pull-up, so the interface. However, the MC34903S/5S (S = Single) contains high level is slightly lower than in other modes. 1 interface. LIN and LIN1 pins are the connection to the LIN sub buses. CANH, CANL, SPLIT, RXD, TXD LIN interfaces are connected to the MCU via the TXD, These are the pins of the high speed CAN physical TXD-L1, RXD, RXD-L1 pins. interface, between the CAN bus and the micro controller. A The device also includes one or two HS switches to VSUP/ detail description is provided in the document. 2 pin which can be used as a LIN master termination switch. Pins LINT and LINT-1 pins are the same as LIN, LIN-T, TXDL AND RXDL I/O-2 and I/O-3. These are the pins of the LIN physical interface. Device contains zero or 1 LIN interfaces. 34903/4/5 Analog Integrated Circuit Device Data 34 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION The device has several operation modes. The transitions A watchdog refresh SPI command is necessary to and conditions to enter or leave each mode are illustrated in transition to NORMAL mode. The duration of the Normal the state diagram. request mode is 256 ms when Normal Request mode is entered after RESET mode. Different durations can be INIT RESET selected by SPI when normal request is entered from LP VDD ON mode. This mode is automatically entered after the device is “powered on”. In this mode, the RST pin is asserted low, for If the watchdog refresh SPI command does not occur a duration of typically 1.0 ms. Control bits and flags are “set” within the 256 ms (or the shorter user defined time out), then to their default reset condition. The BATFAIL is set to indicate the device will enter into RESET mode for a duration of the device is coming from an unpowered condition, and all typically 1.0 ms. previous device configurations are lost and “reset” the default Note: in init reset, init, reset and normal request modes as value. The duration of the INIT reset is typically 1.0 ms. well as in LP modes, the V external PNP is disabled. INIT reset mode is also entered from INIT mode if the DD expected SPI command does not occur in due time (Ref. INIT NORMAL mode), and if the device is not in the debug mode. In this mode, all device functions are available. This mode INIT is entered by a SPI watchdog refresh command from Normal This mode is automatically entered from the INIT Reset Request mode, or from INIT mode. mode. In this mode, the device must be configured via SPI During Normal mode, the device watchdog function is within a time of 256 ms max. operating, and a periodic watchdog refresh must occur. Four registers called INIT Wdog, INIT REG, INIT LIN I/O When an incorrect or missing watchdog refresh command is and INIT MISC must be, and can only be configured during initiated, the device will enter into Reset mode. INIT mode. While in Normal mode, the device can be set to LP modes Other registers can be written in this and other modes. (LP V ON or LP V OFF) using the SPI command. Once the INIT register configuration is done, a SPI DD DD Watchdog Refresh command must be sent in order to set the Dedicated, secured SPI commands must be used to enter device into Normal mode. If the SPI watchdog refresh does from Normal mode to Reset mode, INIT mode or Flash mode. not occur within the 256 ms period, the device will return into INIT Reset mode for typically 1.0 ms, and then re enter into FLASH INIT mode. In this mode, the software watchdog period is extended up Register read operation is allowed in INIT mode to collect device status or to read back the INIT register configuration. to typically 32 seconds. This allow programming of the MCU flash memory while minimizing the software over head to When INIT mode is left by a SPI watchdog refresh refresh the watchdog. The flash mode is entered by Secured command, it is only possible to re-enter the INIT mode using SPI command and is left by SPI command. Device will enter a secured SPI command. In INIT mode, the CAN, LIN1, VAUX, I/O_x and Analog MUX functions are not operating. into Reset mode. When an incorrect or missing watchdog The 5 V-CAN is also not operating, except if the Debug mode refresh command device will enter into Reset mode. An is detected. interrupt can be generated at 50% of the watchdog period. CAN interface operates in Flash mode to allow flash via RESET CAN bus, inside the vehicle. In this mode, the RST pin is asserted low. Reset mode is DEBUG entered from Normal mode, Normal Request mode, LP V DD on mode and from the Flash mode when the watchdog is not Debug is a special operation mode of the device which triggered, or if a V low condition is detected. allows for easy software and hardware debugging. The DD debug operation is detected after power up if the DBG pin is The duration of reset is typically 1.0 ms by default. You set to 8.0 to 10 V range. can define a longer Reset pulse activation only when the When debug is detected, all the software watchdog Reset mode is entered following a V low condition. Reset DD operations are disabled: 256 ms of INIT mode, watchdog pulse is always 1.0 ms, when reset mode is entered due to refresh of Normal mode and Flash mode, Normal Request wrong watchdog refresh command. time out (256 ms or user defined value) are not operating and Reset mode can be entered via the secured SPI will not lead to transition into INIT reset or Reset mode. command. When the device is in Debug mode, the SPI command can be sent without any time constraints with respect to the NORMAL REQUEST watchdog operation and the MCU program can be “halted” or “paused” to verify proper operation. This mode is automatically entered after RESET mode, or after a Wake-up from LP V ON mode. DD 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 35

FUNCTIONAL DEVICE OPERATION LP MODES Debug can be left by removing 8 to 10 V from the DEBUG The 5 V-CAN regulator is ON by default in Debug mode. pin, or by the SPI command (Ref. to MODE register). LP MODES The device has two main LP modes: LP mode with V During this mode, the 5 V-CAN and V regulators are DD AUX OFF, and LP mode with V ON. OFF. The optional external PNP at VDD will also be DD Prior to entering into LP mode, I/O and CAN Wake-up automatically disabled when entering this mode. flags must be cleared (Ref. to mode register). If the Wake-up The same Wake-up events as in LP V OFF mode (CAN, DD flags are not cleared, the device will not enter into LP mode. LIN, I/O, timer, cyclic sense) are available in LP V on DD In addition, the CAN failure flags (i.e. CAN_F and CAN_UF) mode. must be cleared, in order to meet the LP current consumption In addition, two additional Wake-up conditions are specification. available. • Dedicated SPI command. When device is in LP V ON DD LP - V OFF DD mode, the Wake-up by SPI command uses a write to In this mode, V is turned OFF and the MCU connected “Normal Request mode”, 0x5C10. DD to VDD is unsupplied. This mode is entered using SPI. It can • Output current from VDD exceeding L threshold. P-ITH also be entered by an automatic transition due to fail-safe In LP V ON mode, the device is able to source several DD management. 5 V-CAN and V regulators are also turned AUX tenths of mA DC. The current source capability can be time OFF. limited, by a selectable internal timer. Timer duration is up to When the device is in LP VDD OFF mode, it monitors 32 ms, and is triggered when the output current exceed the external events to Wake-up and leave the LP mode. The output current threshold typically 1.5 mA. Wake-up events can occur from: This allows for instance, a periodic activation of the MCU, • CAN while the device remains in LP V on mode. If the duration DD • LIN interface, depending upon device part number exceed the selected time (ex 32 ms), the device will detect a • Expiration of an internal timer Wake-up. • I/O-0, and I/O-1 inputs, and depending upon device part Wake-up events are reported to the MCU via a low level number and configuration, I/O-2 and/or -3 input pulse at INT pulse. The MCU will detect the INT pulse and • Cyclic sense of I/O-1 input, associated by I/O-0 resume operation. activation, and depending upon device part number and configuration, cyclic sense of I/O-2 and -3 input, Watchdog Function in LP V ON Mode DD associated by I/O-0 activation It is possible to enable the watchdog function in LP V DD When a Wake-up event is detected, the device enters into ON mode. In this case, the principle is timeout. Reset mode and then into Normal Request mode. The Wake- Refresh of the watchdog is done either by: up sources are reported to the device SPI registers. In • a dedicated SPI command (different from any other SPI summary, a Wake-up event from LP V OFF leads to the DD command or simple CS activation which would Wake- V regulator turned ON, and the MCU operation restart. DD up - Ref. to the previous paragraph) • or by a temporary (less than 32 ms max) V over LP - V ON DD DD current Wake-up (I > 1.5 mA typically). DD In this mode, the voltage at the VDD pin remains at 5.0 V As long as the watchdog refresh occurs, the device (or 3.3 V, depending upon device part number). The remains in LP V on mode. objective is to maintain the MCU powered, with reduced DD consumption. In such mode, the DC output current is Mode Transitions expected to be limited to 100 μA or a few mA, as the ECU is in reduced power operation mode. Mode transitions are either done automatically (i.e. after a timeout expired or voltage conditions), or via a SPI command, or by an external event such as a Wake-up. Some mode changes are performed using the Secured SPI commands. 34903/4/5 Analog Integrated Circuit Device Data 36 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION STATE DIAGRAM STATE DIAGRAM VSUP/1 rise > VSUP-TH1 VSUP fall & VDD > VDD_UVTH INIT Reset POWER DOWN start T_IR Debug (T_IR=1.0ms) mode detection VSUP fall or VTD_DIN<IVTD eDx_pUirVeTdH watchdog refresh by SPI T_IR expired INIT FLASH start T_WDF (T_sItNaITrt =T_2I5N6ITms) (config) SPI secured (3) Ext reset SPI secured SPI write (0x5A00) or T_WDF expired SPI secured (3) (watchdog refresh) or VDD<VDD_UVTH RESET NORMAL (4) watchdog refresh (1.0smtasr to Tr _cRonfig) VDD<VDD_UVTH or T_WD expired (Ts_tWarDt NT=_WcDoNnfig) by SPI Wake-up or watchdog failure (1) or SPI secured or VDD TSD T_NR expired SPI write (0x5A00) (watchdog refresh) T_R expired & VDD>VDD_UVTH NORMAL SPI REQUEST start T_NR if enable (256ms or config) Wake-up (5) LP watchdog refresh V ON by SPI DD T_OC expired start T_WDL (2) or Wake-up I-DD<IOC (1.5mA) LP V ON I-DD>IOC DD (1.5mA) I > 1.5mA DD VDD<VDD_UVTHLP start T_OC time T_WDL expired or VDD<VDD_UVTHLP SPI LP V OFF DD FAIL-SAFE DETECTED (1) watchdog refresh in closed window or enhanced watchdog refresh failure (2) If enable by SPI, prior to enter LP VDD ON mode (3) Ref. to “SPI secure” description (4) VDD external PNP is disable in all mode except Normal and Flash modes. (5) Wake-up from LP VDD ON mode by SPI command is done by a SPI mode change: 0X5C10 Figure 19. State Diagram 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 37

FUNCTIONAL DEVICE OPERATION MODE CHANGE MODE CHANGE “SECURED SPI” DESCRIPTION: - from Normal mode to Flash mode A request is done by a SPI command, the device provide - from Normal mode to Reset mode (reset request). on MISO an unpredictable “random code”. Software must “Random code” is also used when the “advance perform a logical change on the code and return it to the watchdog” is selected. device with the new SPI command to perform the desired action. CHANGING OF DEVICE CRITICAL PARAMETERS The “random code” is different at every exercise of the Some critical parameters are configured one time at secured procedure and can be read back at any time. device power on only, while the batfail flag is set in the INIT The secured SPI uses the Special MODE register for the mode. If a change is required while device is no longer in INIT following transitions: mode, device must be set back in INIT mode using the “SPI - from Normal mode to INT mode secure” procedure. WATCHDOG OPERATION IN NORMAL REQUEST MODE If the watchdog is triggered before 50%, or not triggered before end of period, a reset has occurred. The device enters In Normal Request mode, the device expects to receive a into Reset mode. watchdog configuration before the end of the normal request time out period. This period is reset to a long (256 ms) after Watchdog in Debug Mode power on and when BATFAIL is set. The device can be configured to a different (shorter) time When the device is in Debug mode (entered via the DBG out period which can be used after Wake-up from LP V on pin), the watchdog continues to operate but does not affect DD mode. the device operation by asserting a reset. For the user, operation appears without the watchdog. After a software watchdog reset, the value is restored to 256 ms, in order to allow for a complete software initialization, When Debug mode is set by software (SPI mode reg), the similar to a device power up. watchdog period starts at the end of the SPI command. In Normal Request mode the watchdog operation is When Debug mode is set by hardware (DBG pin below 8- “timeout” only and can be triggered/observed any time within 10 V), the device enters into Reset mode. the period. Watchdog in Flash Mode WATCHDOG TYPE SELECTION During Flash mode, watchdog can be set to a long timeout Three types of watchdog operation can be used: period. Watchdog is timeout only and an INT pulse can be generated at 50% of the time window. - Window watchdog (default) - Timeout operation Advance Watchdog Operation - Advanced When the Advance watchdog is selected (at INIT mode), The selection of watchdog is performed in INIT mode. This the refresh of the watchdog must be done using a random is done after device power up and when the BATFAIL flag is number and with 1, 2, or 4 SPI commands. The number for set. The Watchdog configuration is done via the SPI, then the the SPI command is selected in INIT mode. Watchdog mode selection content is locked and can be The software must read a random byte from the device, changed only via a secured SPI procedure. and then must return the random byte inverted to clear the watchdog. The random byte write can be performed in 1, 2, Window Watchdog Operation or 4 different SPI commands. The window watchdog is available in Normal mode only. If one command is selected, all eight bits are written at The watchdog period selection can be kept (SPI is selectable once. in INIT mode), while the device enters into LP V ON mode. DD If two commands are selected, the first write command The watchdog period is reset to the default long period after must include four of the eight bits of the inverted random byte. BATFAIL. The second command must include the next four bits. This The period and the refresh of watchdog are done by the completes the watchdog refresh. SPI. A refresh must be done in the open window of the If four commands are selected, the first write command period, which starts at 50% of the selected period and ends must include two of the eight bits of the inverted random byte. at the end of the period. The second command must include the next two bits, the 3rd command must include the next two, and the last command, 34903/4/5 Analog Integrated Circuit Device Data 38 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION WATCHDOG OPERATION must include the last two. This completes the watchdog along with the next refresh command. It must be done in an refresh. open window, if the Window operation was selected. When multiple writes are used, the most significant bits are sent first. The latest SPI command needs to be done inside Advance Watchdog, Refresh by two SPI Commands: the open window time frame, if window watchdog is selected. The refresh command is split in two SPI commands. The first partial refresh command is 0x5Aw1, and the DETAIL SPI OPERATION AND SPI COMMANDS second is 0x5Aw2. Byte w1 contains the first four inverted FOR ALL WATCHDOG TYPES. bits of the RD byte plus the last four bits equal to zero. Byte All SPI commands and examples do not use parity w2 contains four bits equal to zero plus the last four inverted functions. bits of the RD byte. In INIT mode, the watchdog type (window, timeout, During this second refresh command the device returns on advance and number of SPI commands) is selected using the MISO a new Random Code. This new random code must be register Init watchdog, bits 1, 2 and 3. The watchdog period inverted and send along with the next two refresh commands is selected using the TIM_A register. The watchdog period and so on. selection can also be done in Normal mode or in Normal The second command must be done in an open window if Request mode. the Window operation was selected. Transition from INIT mode to Normal mode or from Normal Request mode to Normal mode is done using a single Advance Watchdog, Refresh by four SPI Commands watchdog refresh command (SPI 0x 5A00). The refresh command is split into four SPI commands. While in Normal mode, the Watchdog Refresh Command The first partial refresh command is 0x5Aw1, the second is depends upon the watchdog type selected in INIT mode. 0x5Aw2, the third is 0x5Aw3, and the last is 0x5Aw4. They are detailed in the paragraph below: Byte w1 contains the first two inverted bits of the RD byte, plus the last six bits equal to zero. Simple Watchdog Byte w2 contains two bits equal to zero, plus the next two The Refresh command is 0x5A00. It can be send any time inverted bits of the RD byte, plus four bits equal to zero. within the watchdog period, if the timeout watchdog operation Byte w3 contains four bits equal to zero, plus the next two is selected (INIT-watchdog register, bit 1 WD N/Win = 0). It inverted bits of the RD byte, plus two bits equal to zero. must be send in the open window (second half of the period) if the Window Watchdog operation was selected (INIT- Byte w4 contains six bits equal to zero, plus the next two watchdog register, bit 1 WD N/Win = 1). inverted bits of the RD byte. During this fourth refresh command, the device will return, Advance Watchdog on MISO, a new Random Code. This new Random Code must be inverted and send along with the next four refresh The first time the device enters into Normal mode (entry on commands. Normal mode using the 0x5A00 command), Random (RNDM) code must be read using the SPI command, The fourth command must be done in an open window if 0x1B00. The device returns on MISO second byte the RNDM the Window operation was selected. code. The full 16 bits MISO is called 0x XXRD. RD is the complement of the RD byte. PROPER RESPONSE TO INT During a device detect upon an INT, the software handles Advance Watchdog, Refresh by 1 SPI Command the INT in a timely manner: Access of the INT register is done The refresh command is 0x5ARD. During each refresh within two watchdog periods. This feature must be enabled command, the device will return on MISO, a new Random by SPI using the INIT watchdog register bit 7. Code. This new Random Code must be inverted and send 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 39

FUNCTIONAL DEVICE OPERATION FUNCTIONAL BLOCK OPERATION VERSUS MODE FUNCTIONAL BLOCK OPERATION VERSUS MODE Table 8. Device Block Operation for Each State State VDD 5 V-CAN I/O-X VAUX CAN LIN1 Power down OFF OFF OFF OFF High-impedance High-impedance Init Reset ON OFF HS/LS off OFF OFF: OFF: Wake-up disable CAN termination 25 k to GND internal 30 k pull-up active. Transmitter / receiver /Wake-up Transmitter: receiver / OFF Wake-up OFF. LIN term OFF INIT ON OFF (28) OFF OFF OFF WU disable (29)(30)(31) Reset ON Keep SPI config OFF OFF OFF WU disable (29)(30)(31) Normal Request ON Keep SPI config OFF OFF OFF WU disable (29)(30)(31) Normal ON SPI config SPI config SPI config SPI config SPI config WU SPI config LP VDD OFF OFF OFF user defined OFF OFF + Wake-up en/dis OFF + Wake-up en/dis WU SPI config LP VDD ON ON(27) OFF user defined OFF OFF + Wake-up en/dis OFF + Wake-up en/dis WU SPI config SAFE output low: safe case A: Keep SPI HS/LS off OFF OFF + Wake-up enable OFF + Wake-up enable Safe case A A:ON config, B: OFF Wake-up by change safe case B: state OFF FLASH ON SPI config SPI config OFF SPI config OFF Notes 27. With limited current capability 28. 5 V-CAN is ON in Debug mode. 29. I/O-0 and I/O-1, configured as an output high-side switch and ON in Normal mode will remain ON in RESET, INIT or Normal Request. 30. I/O-0, configured as an output low-side switch and ON in Normal mode will turn OFF when entering Reset mode, resume operation in Normal mode. 31. I/O-1, configured as an output low-side switch and ON in Normal mode will remain ON in RESET, INIT or Normal Request. The 5 V-CAN default is ON when the device is powered-up and set in Debug mode. It is fully controllable via the SPI command. 34903/4/5 Analog Integrated Circuit Device Data 40 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION ILLUSTRATION OF DEVICE MODE TRANSITIONS. ILLUSTRATION OF DEVICE MODE TRANSITIONS. Power up to Normal Mode Normal to LP Normal to LP A B B VDD OFF Mode C B VDD ON Mode D VSUP >4.0V VSUP VSUP VDD VDD-UV (4.5V typically) VDD VDD-UV VDD 5V-CAN 5V-CAN 5V-CAN VAUX VAUX VAUX RST RST RST INT INT INT 11 1 12 2 13 3 _ _ _ _ _ _ SPI s s SPI s s SPI s s MODE RESET INIT NORMAL NORMALLP VDD OFF NORMAL LP VDD On BATFAIL s_1: go to Normal mode s_2: go to LP VDD OFF mode s_3: go to LP mode s_11: write INT registers s_12: LP Mode configuration s_13: LP Mode configuration legend: Series of SPI Single SPI Figure 20. Power Up Normal and LP Modes 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 41

FUNCTIONAL DEVICE OPERATION ILLUSTRATION OF DEVICE MODE TRANSITIONS. C Wake-up from LP VDD OFF Mode D Wake-up from LP VDD ON Mode VSUP VSUP VDD VDD-UV (4.5V typically) VDD 5V-CAN Based on reg configuration 5V-CAN Based on reg configuration VAUX Based on reg configuration VAUX Based on reg configuration RST RST INT INT 4 4 1 4 1 4 _ _ _ _ SPI s s SPI s s NORMAL NORMAL MODE LP VDD_OFF RESET REQUEST NORMAL MODE LP VDD ON REQUEST NORMAL CAN bus e) CAN bus v CAN Wake-up si CAN Wake-up pattern u pattern cl x LIN Bus e LIN Bus s ( nt LIN Wake-up filter ve LIN Wake-up filter e p u e- k I/O-x toggle a I/O-x toggle W e bl a FWU timer ail FWU timer v A Start . Start Stop FWU timer FWU timer duration (50-8192ms) duration (50-8192ms) SPI selectable SPI selectable Wake-up detected IDD current IDD-OC (3.0mA typically) IDD OC deglitcher or timer (100us typically, 3 -32ms) SPI Wake-up detected Figure 21. Wake-up from LP Modes 34903/4/5 Analog Integrated Circuit Device Data 42 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION CYCLIC SENSE OPERATION DURING LP MODES CYCLIC SENSE OPERATION DURING LP MODES This function can be used in both LP modes: V OFF and transistor can be activated. The selection is done by the state DD V ON. of I/O-0 prior to entering in LP mode. DD Cyclic sense is the periodic activation of I/O-0 to allow During the T duration, the I/O-x’s are monitored. If -CSON biasing of external contact switches. The contact switch state one of them is high, the device will detect a Wake-up. can be detected via I/O-1, -2, and -3, and the device can (Figure 22). Wake-up from either LP mode. Cyclic sense period is selected by the SPI configuration Cyclic sense is optimized and designed primarily for prior to entering LP mode. Upon entering LP mode, the I/O-0 closed contact switch in order to minimize consumption via should be activated. the contact pull-up resistor. The level of I/O-1 is sense during the I/O-0 active time, and is deglitched for a duration of typically 30 μs. This means that Principle I/O-1 should be in the expected state for a duration longer A dedicated timer provides an opportunity to select a cyclic than the deglitch time. sense period from 3.0 to 512 ms (selection in timer B). The diagram below (Figure 22) illustrates the cyclic sense At the end of the period, the I/O-0 will be activated for a operation, with I/O-0 HS active and I/O-1 Wake-up at high duration of T (SPI selectable in INIT register, to 200 μs, level. _CSON 400 μs, 800 μs, or 1.6 ms). The I/O-0 HS transistor or LS I/O-0 HS active in Normal mode I/O-0 HS active during cyclic sense active time I/O-0 Zoom S1 S1 closed S1 open Cyclic sense active time (ex 200us) I/O-1 I/O-0 I/O-1 high => Wake-up I/O-1 Cyclic sense period state of I/O-1 low => no Wake-up I/O-1 deglitcher time Cyclic sense active time (typically 30us) NORMAL MODE LP MODE RESET or NORMAL REQUEST MODE Wake-up event detected Wake-up detected. R R R R R R I/O-0 I/O-0 I/O-1 I/O-1 S1 S1 I/O-2 I/O-2 S2 S2 I/O-3 I/O-3 S3 S3 Upon entering in LP mode, all 3 In LP mode, 1 contact switch is open. contact switches are closed. High level is detected on I/O-x, and device wakes up. Figure 22. Cyclic Sense Operation - Switch to GND, Wake-up by Open Switch 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 43

FUNCTIONAL DEVICE OPERATION CYCLIC INT OPERATION DURING LP VDD ON MODE CYCLIC INT OPERATION DURING LP VDD ON MODE Principle SPI commands to acknowledge INT: (2 commands) This function can be used only in LP V ON mode (LP - read the Random code via the watchdog register address DD V ON). using the following command: MOSI 0x1B00 device report on DD MISO second byte the RNDM code (MISO bit 0-7). When Cyclic INT is selected and device is in LP V ON DD mode, the device will generate a periodic INT pulse. - write watchdog refresh command using the random code inverted: 0x5A RNDb. Upon reception of the INT pulse, the MCU must acknowledge the INT by sending SPI commands before the These commands can occur at any time within the period. end of the next INT period in order to keep the process going. Initial entry in LP mode with Cyclic INT: after the device is When Cyclic INT is selected and operating, the device set in LP VDD ON mode, with cyclic INT enable, no SPI remains in LP V ON mode, assuming the SPI commands command is necessary until the first INT pulse occurs. The DD are issued properly. When no/improper SPI commands are acknowledge process must start only after the 1st INT pulse. sent, the device will cease Cyclic INT operation and leave LP Leave LP mode with Cyclic INT: V ON mode by issuing a reset. The device will then enter DD This is done by a SPI Wake-up command, similar to SPI into Normal Request mode. Wake-up from LP V ON mode: 0x5C10. The device will DD VDD current capability and VDD regulator behavior is enter into Normal Request mode. similar as in LP V ON mode. DD Improper SPI command while Cyclic INT operates: When no/improper SPI commands are sent, while the Operation device is in LP V ON mode with Cyclic INT enable, the DD Cyclic INT period selection: register timer B device will cease Cyclic INT operation and leave LP V ON DD SPI command in hex 0x56xx [example; 0x560E for 512ms mode by issuing a reset. The device will then enter into cyclic Interrupt period (SPI command without parity bit)]. Normal Request mode. This command must be send while the device is in Normal The figure below (Figure 23) describes the complete mode. Cyclic Interrupt operation. Prepare LP VDD ON Leave LP with Cyclic INT In LP VDD ON with Cyclic INT VDD ON Mode INT LP VDD ON mode SPI Timer B Cyclic INT period 1st period 2nd period 3rd period Cyclic INT period Cyclic INT period Cyclic INT period NORMAL MODE LP VDD ON MODE NORMAL REQUEST MODE Legend for SPI commands Leave LP VDD ON and Cyclic INT due to improper operation Write Timer B, select Cyclic INT period (ex: 512 ms, 0x560E) INT Write Device mode: LP VDD ON with Cyclic INT enable (example: 0x5C90) Improper or no Read RNDM code SPI acknowledge SPI command Write RNDM code inv. SPI Wake-up: 0x5C10 RST Cyclic INT period RESET and NORMAL REQUEST LP VDD ON MODE MODE Figure 23. Cyclic Interrupt Operation 34903/4/5 Analog Integrated Circuit Device Data 44 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN BEHAVIOR AT POWER UP AND POWER DOWN DEVICE POWER UP The figures below illustrate the device behavior during V ramp up. As the Crank bit is by default set to 0, V is This section describe the device behavior during ramp up, SUP/1 DD enabled when V is above V parameters. and ramp down of V , and the flexibility offered mainly by SUP/1 SUP TH 1 SUP/1 the Crank bit and the two V undervoltage reset thresholds. DD VSUP_NOMINAL (ex 12V) VDD NOMINAL (ex 5.0V) VSUP slew rate V BAT VDD_UV TH (typically 4.65V) D1 VSUP/1 VDD VSUP_TH1 3490X VDD_START UP I_VDD 90% VDD_START UP VSUP/1 Gnd 10% VDD_START UP VDD VDD_OFF RST 1.0ms Figure 24. V Start-up Versus V Tramp DD SUP/1 DEVICE POWER DOWN (V < 4.6 V or V < 3.2 V typically, threshold selected by DD DD the SPI). When device is in Reset, if V is below The figures below illustrate the device behavior during SUP/1 “V ”, V is turned OFF. V ramp down, based on Crank bit configuration, and SUP_TH1 DD SUP/1 V undervoltage reset selection. DD Crank Bit Set (INIT Watchdog Register, Bit 0 =1) Crank Bit Reset (INIT Watchdog Register, Bit 0 =0) The bit 0 is set by SPI write. During V ramp down, SUP/1 V remains ON until device detects a POR and set Bit 0 = 0 is the default state for this bit. DD BATFAIL. This occurs for a V approx 3.0 V. During V ramp down, V remain ON until device SUP/1 SUP/1 DD enters in Reset mode due to a V undervoltage condition DD 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 45

FUNCTIONAL DEVICE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN VBAT VBAT VSUP_NOMINAL VSUP_NOMINAL (ex 12V) (ex 12V) VSUP/1 VSUP/1 VDD (5.0V) VSUP_TH1 (4.1V) VDD (5.0V) VDD_UV TH (typically 4.65V) VDD_UV TH (typically 4.65V) BATFAIL (3.0V) VDD VDD RST RST Case 1: “V 4.6V”, with bit Crank = 0 (default value) Case 2: “V 4.6V”, with bit Crank = 1 DD UV TH DD UV VBAT VBAT VSUP_NOMINAL VSUP_NOMINAL (ex 12V) (ex 12V) VSUP/1 VSUP/1 VSUP_TH1 (4.1V) VDD (5.0V) VDD (5.0V) VDD_UV TH (typically 4.65V) VDD_UV TH (typically 4.65V) BATFAIL (3.0V) VDD VDD VDD_UV TH2 (typically 3.2V) VDD_UV TH2 (typically 3.2V) (2) INT INT RST (1) RST (1) reset then (2) VDD turn OFF Case 1: “VDD UV TH 3.2V”, with bit Crank = 0 (default value) Case 2: “VDD UV 3.2V”, with bit Crank = 1 Figure 25. V Behavior During V Ramp Down DD SUP/1 34903/4/5 Analog Integrated Circuit Device Data 46 Freescale Semiconductor

FAIL-SAFE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN FAIL-SAFE OPERATION OVERVIEW to properly control the device and properly refresh the watchdog). Fail-safe mode is entered when specific fail conditions occur. The “Safe state” condition is defined by the resistor Modes B1, B2 and B3 connected at the DGB pin. Safe mode is entered after additional event or conditions are met: time out for CAN Upon SAFE activation, the system continues to monitor communication and state at I/O-1 pin. external event, and disable the MCU supply (turn V OFF). DD Exiting the safe state is always possible by a Wake-up The external events monitored are: CAN traffic, I/O-1 low event: in the safe state, the device can automatically be level or both of them. 3 sub cases exist, B1, B2 and B3. awakened by CAN and I/O (if configured as inputs). Upon Note: no CAN traffic indicates that the ECU of the vehicle Wake-up, the device operation is resumed: enter in Reset are no longer active, thus that the car is being parked and mode. stopped. The I/O low level detection can also indicate that the vehicle is being shutdown, if the I/O-1 pin is connected for FAIL-SAFE FUNCTIONALITY instance to a switched battery signal (ignition key on/off signal). Upon dedicated event or issue detected at a device pin The selection of the monitored events is done by (i.e. RST short to VDD), the Safe mode can be entered. In hardware, via the resistor connected at DBG pin, but can be this mode, the SAFE pin is active low. over written by software, via a specific SPI command. By default, after power up the device detect the resistor Description value at DBG pin (upon transition from INIT to Normal mode), Upon activation of the SAFE pin, and if the failure and, if no specific SPI command related to Debug resistor condition that make the SAFE pin activated have not change is send, operates according to the detected resistor. recovered, the device can help to reduce ECU consumption, The INIT MISC register allow you to verify and change the assuming that the MCU is not able to set the whole ECU in LP device behavior, to either confirm or change the hardware mode. Two main cases are available: selected behavior. Device will then operate according to the SAFE mode configured by the SPI. Mode A Table 9 illustrates the complete options available: Upon SAFE activation, the MCU remains powered (V DD stays ON), until the failure condition recovers (i.e. S/W is able Table 9. Fail-safe Options Resistor at SPI coding - register INIT MISC bits [2,1,0] Safe mode DBG pin (higher priority that Resistor coding) code VDD status <6.0 k bits [2,1,0) = [111]: verification enable: resistor at DBG pin is typically A remains ON 0 kohm (RA) - Selection of SAFE mode A typically 15 k bits [2,1,0) = [110]: verification enable: resistor at DBG pin is typically B1 Turn OFF 8.0 s after CAN traffic bus idle detection. 15 kohm (RB1) - Selection of SAFE mode B1 typically 33 k bits [2,1,0) = [101]: verification enable: resistor at DBG pin is typically B2 Turn OFF when I/O-1 low level detected. 33 kohm (RB2 - Selection of SAFE mode B2 typically 68 k bits [2,1,0) = [100]: verification enable: resistor at DBG pin is typically B3 Turn OFF 8.0 s after CAN traffic bus idle detection 68 kohm (RB3) - Selection of SAFE mode B3 AND when I/O-1 low level detected. Exit of Safe Mode Wake-up, the device operation is resumed, and device enters in Reset mode. The SAFE pin remains active, until there is a Exit of the safe state with V OFF is always possible by DD proper read and clear of the SPI flags reporting the SAFE a Wake-up event: in this safe state the device can conditions. automatically awakened by CAN and I/O (if I/O Wake-up was enable by the SPI prior to enter into SAFE mode). Upon 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 47

FAIL-SAFE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN . SAFE Operation Flow Chart Legend: Failure events Device state: RESET RESET NR detection of 2nd bit 4, INIT watchdog=1 (1) consecutive watchdog failure SAFE high Reset: 1.0ms pulse (6) bit 4, INIT watchdog=0 (1) SAFE low Reset: 1.0ms pulse SAFE low 8 consecutive watchdog failure (5) - SAFE low - VDD ON State A: RDBG <6.0k AND - Reset: 1.0ms A watchdog failure periodic pulse SAFE pin release a) Evaluation of e (SAFE high) watchdog failure aRte DsBisGto rp dine tdeucrtiendg e stat S(VtaDtDe lAow: R oDr BRGS <T6 s./0c kG ANNDD) failure - SAFE low SPI (3) power up, or SPI saf -- VRDeDse Ot Nlow VDD low: register content State B1: RDBG=15k AND VDD <VDD_UVTH Bus idle timeout expired NNoorrmmaIaNl lR,I TFe,LqAueSsH tRst s/c GND: --- RSVAeDsFDeE Ot llNooww -b-m )Ibo/ OEunsC-it 1oiUd rm lieeno xgtnit me(it7roen)r: aionlu gstignal safe state B SRSRtDtDaaBBtteGeG BB==2334::37kk AANNDD II//OO--11 llooww --- RVSDAeDsFe EOt FllooFww AND Bus idle time out expired Rst <2.5V, t >100ms RESET Wake-up (2), VDD ON, SAFE pin remains low failure recovery, SAFE pin remains low 1) bit 4 of INIT Watchdog register 2) Wake-up event: CAN, LIN or I/O-1 high level (if I/O-1 Wake-up previously enabled) 3) SPI commands: 0xDD00 or 0xDD80 to release SAFE pin 4) Recovery: reset low condition released, VDD low condition released, correct SPI watchdog refresh 5) detection of 8 consecutive watchdog failures: no correct SPI watchdog refresh command occurred for duration of 8 x 256ms. 6) Dynamic behavior: 1.0ms reset pulse every 256ms, due to no watchdog refresh SPI command, and device state transition between RESET and NORMAL REQUEST mode, or INIT RESET and INIT modes. 7) 8 second timer for bus idle timeout. I/O-1 high to low transition. Figure 26. Safe Operation Flow Chart Conditions to Set SAFE Pin Active Low VDD low: VDD < RST-TH. SAFE pin is set low at the same time as the RST pin is set low. Watchdog refresh issue: SAFE activated at 1st reset pulse or at the second consecutive reset pulse (selected by bit 4, The RST pin is monitored to verify that reset is not INIT watchdog register). clamped to a low level preventing the MCU to operate. If this is the case, the Safe mode is entered. 34903/4/5 Analog Integrated Circuit Device Data 48 Freescale Semiconductor

FAIL-SAFE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN SAFE Mode A Illustration Figure 27 illustrates the event and consequences when SAFE mode A is selected via the appropriate debug resistor or SPI configuration. Behavior Illustration for Safe State A (R <6.0kohm), or Selection by the SPI DG step 2: Consequence on step 1: Failure illustration V , RST and SAFE DD VDD VDD failure event, i.e. watchdog 1st 2nd 8th RST RST SAFE OFF state ON state SAFE 8 x 256ms delay time to enter in SAFE mode to evaluate resistor at DBG pin and monitor ECU external events failure event, VDD low VDD VDD_UV TH VDD VDD < VDD_UV TH GND GND RST RST SAFE OFF state ON state SAFE 100ms 100ms delay time to enter in SAFE mode to evaluate resistor at DBG pin and monitor ECU external events failure event, Reset s/c GND VDD VDD RST 2.5V RST SAFE OFF state ON state SAFE 100ms 100ms deglitcher time to activate SAFE and enter in SAFE mode to evaluate resistor at the DBG pin and monitor ECU external events Figure 27. SAFE Mode A Behavior Illustration 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 49

FAIL-SAFE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN SAFE Mode B1, B2 and B3 Illustration Figure 28 illustrates the event, and consequences when SAFE mode B1, B2, or B3 is selected via the appropriate debug resistor or SPI configuration. Behavior illustration for the safe state B (R > 10kohm) DG CAN bus DBG resistor => safe state B1 step 2: CAN bus idle time Exclusive detection of ECU external event to I/O-1 disable V based on I/O-1 high to low transition DD DBG resistor => safe state B2 R resistor or DBG SPI configuration CAN bus DBG resistor => safe state B3 CAN bus idle time I/O-1 I/O-1 high to low transition step 1: Failure illustration step 3: Consequences for VDD VDD VDD failure event, i.e. watchdog 1st 2nd 8th RST RST SAFE SAFE OFF state ON state 8 x 256ms delay time to enter in SAFE mode to evaluate resistor at the DBG pin and monitor ECU external events failure event, VDD low If VDD failure recovered GNDVDD VDD_UV TH GNDVDD VDD < VDD_UV TH VDD OFF RST RST SAFE OFF state ON state SAFE n 100ms ditio 1a0n0dm mso dneittlooa rye E vtiCamlUuea ettoex tereenrsnteiasrlt oienrv SaetnA DtFsBEG m poidne ernal cdoinsable W ake-up ext V DD failure event, Reset s/c GND C U => If Reset s/c GND recovered E et m VDD VDD VDD OFF 2.5V RST RST SAFE OFF state ON state SAFE 100ms 100ms deglitcher time to activate SAFE and enter in SAFE mode to evaluate resistor at DBG pin and monitor ECU external events Figure 28. SAFE Modes B1, B2, or B3 Behavior Illustration 34903/4/5 Analog Integrated Circuit Device Data 50 Freescale Semiconductor

CAN INTERFACE CAN INTERFACE DESCRIPTION CAN INTERFACE CAN INTERFACE DESCRIPTION The figure below is a high level schematic of the CAN internal 2.5 V reference provides the 2.5 V recessive levels interface. It exist in a LS driver between CANL and GND, and via the matched R resistors. The resistors can be switched IN a HS driver from CANH to 5 V-CAN. Two differential to GND in CAN Sleep mode. A dedicated split buffer provides receivers are connected between CANH and CANL to detect a low-impedance 2.5 V to the SPLIT pin, for recessive level a bus state and to Wake-up from CAN Sleep mode. An stabilization. VSUP/2 Pattern Wake-up SPI & State machine Detection Receiver 5V-CAN Driver QH 2.5V RIN CANH Differential RXD Receiver RIN CANL 5V-CAN TXD Driver QL SPI & State machine Thermal 5V-CAN Failure Detection Buffer SPLIT SPI & State machine & Management Figure 29. CAN Interface Block Diagram Can Interface Supply The 5 V-CAN regulator must be ON. It supplies the CAN driver and receiver.The SPLIT pin is active and a 2.5 V The supply voltage for the CAN driver is the 5 V-CAN pin. biasing is provided on the SPLIT output pin. The CAN interface also has a supply pass from the battery line through the VSUP/2 pin. This pass is used in CAN Sleep Receive Only Mode mode to allow Wake-up detection. During CAN communication (transmission and reception), This mode is used to disable the CAN driver, but leave the the CAN interface current is sourced from the 5 V-CAN pin. CAN receiver active. In this mode, the device is only able to During CAN LP mode, the current is sourced from the VSUP/ report the CAN state on the RXD pin. The TXD pin has no 2 pin. effect on CAN bus lines. The 5 V-CAN regulator must be ON. The SPLIT pin is active and a 2.5 V biasing is provided on the TXD/RXD Mode SPLIT output pin. In TXD/RXD mode, both the CAN driver and the receiver Operation in TXD/RXD Mode are ON. In this mode, the CAN lines are controlled by the TXD pin level and the CAN bus state is reported on the RXD pin. The CAN driver will be enabled as soon as the device is in Normal mode and the TXD pin is recessive. 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 51

CAN INTERFACE CAN INTERFACE DESCRIPTION When the CAN interface is in Normal mode, the driver has to the bus and from the bus to the RXD. The loop time is thus two states: recessive or dominant. The driver state is affected by the slew rate selection. controlled by the TXD pin. The bus state is reported through the RXD pin. Minimum Baud Rate When TXD is high, the driver is set in the recessive state, The minimum baud rate is determined by the shortest TXD and CANH and CANL lines are biased to the voltage set with permanent dominant timing detection. The maximum number 5 V-CAN divided by 2, or approx. 2.5 V. of consecutive dominant bits in a frame is 12 (6 bits of active When TXD is low, the bus is set into the dominant state, error flag and its echo error flag). and CANL and CANH drivers are active. CANL is pulled low The shortest TXD dominant detection time of 300 μs lead and CANH is pulled high. to a single bit time of: 300 μs / 12 = 25 μs. The RXD pin reports the bus state: CANH minus the CANL So the minimum Baud rate is 1 / 25 μs = 40 kBaud. voltage is compared versus an internal threshold (a few hundred mV). Sleep Mode If “CANH minus CANL” is below the threshold, the bus is Sleep mode is a reduced current consumption mode. recessive and RXD is set high. CANH and CANL drivers are disabled and CANH and CANL If “CANH minus CANL” is above the threshold, the bus is lines are terminated to GND via the R resistor, the SPLIT IN dominant and RXD is set low. pin is high-impedance. In order to monitor bus activities, the The SPLIT pin is active and provides a 2.5 V biasing to the CAN Wake-up receiver can be enabled. It is supplied SPLIT output. internally from VSUP/2. Wake-up events occurring on the CAN bus pin are TXD/RXD Mode and Slew Rate Selection reporting by dedicated flags in SPI and by INT pulse, and results in a device Wake-up if the device was in LP mode. The CAN signal slew rate selection is done via the SPI. By default and if no SPI is used, the device is in the fastest slew When the device is set back into Normal mode, CANH and rate. Three slew rates are available. The slew rate controls CANL are set back into the recessive level. This is illustrated the recessive to dominant, and dominant to recessive in Figure 30. transitions. This also affects the delay time from the TXD pin . TXD Dominant state Recessive state CANH-DOM CANH CANL/CANH-REC 2.5V CANH-CANL CANL CANL-DOM High ohmic termination (50kohm) to GND RXD 2.5V SPLIT High-impedance Bus Driver Receiver (bus dominant set by other IC) Go to sleep, Normal or Listen Only mode Normal or Listen Only mode Sleep or Stand-by mode Figure 30. Bus Signal in TXD/RXD and LP Mode Wake-up up is a pattern Wake-up. The Wake-up by the CAN is enabled or disabled via the SPI. When the CAN interface is in Sleep mode with Wake-up enabled, the CAN bus traffic is detected. The CAN bus Wake- 34903/4/5 Analog Integrated Circuit Device Data 52 Freescale Semiconductor

CAN INTERFACE CAN INTERFACE DESCRIPTION CAN CANH bus Dominant Dominant Pulse # 1 Pulse # 2 CANL Internal differential Wake-up receiver signal Internal Wake-up signal Can Wake-up detected tCAN WU1-F Figure 31. Single Dominant Pulse Wake-up Pattern Wake-up A valid dominant pulse should be longer than 500 ns. The three pulses should occur in a time frame of 120 μs, to be In order to Wake-up the CAN interface, the Wake-up considered valid. When three pulses meet these conditions, receiver must receive a series of three consecutive valid the wake signal is detected. This is illustrated by the following dominant pulses, by default when the CANWU bit is low. figure. CANWU bit can be set high by SPI and the Wake-up will occur after a single pulse duration of 2.0 μs (typically). . CAN CANH bus Dominant Dominant Dominant Dominant Pulse # 1 Pulse # 2 Pulse # 3 Pulse # 4 CANL Internal differential Wake-up receiver signal Internal Wake-up signal Can Wake-up detected tCAN WU3-F tCAN WU3-F tCAN WU3-F tCAN WU3-TO Dominant Pulse # n: duration 1 or multiple dominant bits Figure 32. Pattern Wake-up - Multiple Dominant Detection BUS TERMINATION • SPLIT termination concept, with the mid point of the differential termination connected to GND through a The device supports the two main types of bus capacitor and to the SPLIT pin. terminations: • In application, the device can also be used without • Differential termination resistors between CANH and termination. CANL lines. • Figure 33 illustrates some of the most common terminations. 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 53

CAN INTERFACE CAN BUS FAULT DIAGNOSTIC CANH CANH SPLIT No 120 CAN bus SPLIT No CAN bus connect connect CANL ECU connector CANL ECU connector Standard termination No termination CANH 60 SPLIT CAN bus 60 CANL ECU connector Figure 33. Bus Termination Options CAN BUS FAULT DIAGNOSTIC The device includes diagnostic of bus short-circuit to GND, monitor the bus level in the recessive and dominant states. VBAT, and internal ECU 5.0 V. Several comparators are The information is then managed by a logic circuitry to implemented on CANH and CANL lines. These comparators properly determine the failure and report it. Vr5 H5 VBAT (12-14V) Vrvb Hb VDD VRVB (VSUP-2.0V) Vrg TXD Logic Hg CANH VDD (5.0V) Diag VR5 (VDD-.43V) Lg CANL CANH dominant level (3.6V) Vrg Lb Recessive level (2.5V) Vrvb VRG (1.75V) L5 CANL dominant level (1.4V) Vr5 GND (0.0V) Figure 34. CAN Bus Simplified Structure Truth Table for Failure Detection The following table indicates the state of the comparators when there is a bus failure, and depending upon the driver state. Table 10. Failure Detection Truth Table Driver Recessive State Driver Dominant State Failure Description Lg (threshold 1.75 V) Hg (threshold 1.75 V) Lg (threshold 1.75 V) Hg (threshold 1.75 V) No failure 1 1 0 1 CANL to GND 0 0 0 1 CANH to GND 0 0 0 0 Lb (threshold VSUP -2.0 V) Hb (threshold VSUP -2.0 V) Lb (threshold VSUP -2.0 V) Hb (threshold VSUP -2.0 V) No failure 0 0 0 0 CANL to VBAT 1 1 1 1 CANH to VBAT 1 1 0 1 34903/4/5 Analog Integrated Circuit Device Data 54 Freescale Semiconductor

CAN INTERFACE CAN BUS FAULT DIAGNOSTIC Table 10. Failure Detection Truth Table Driver Recessive State Driver Dominant State Failure Description Lg (threshold 1.75 V) Hg (threshold 1.75 V) Lg (threshold 1.75 V) Hg (threshold 1.75 V) L5 (threshold VDD -0.43 V) H5 (threshold VDD -0.43 V) L5 (threshold VDD -0.43 V) H5 (threshold VDD -0.43 V) No failure 0 0 0 0 CANL to 5.0 V 1 1 1 1 CANH to 5.0 V 1 1 0 1 DETECTION PRINCIPLE This condition could occur when the CANH line is shorted to a high-voltage. In this case, current will flow from the high- In the recessive state, if one of the two bus lines are voltage short-circuit, through the bus termination resistors shorted to GND, VDD (5.0 V), or VBAT, the voltage at the (60 Ω), into the SPLIT pin (if used), and into the device CANH other line follows the shorted line, due to the bus termination and CANL input resistors, which are terminated to internal resistance. For example: if CANL is shorted to GND, the 2.5 V biasing or to GND (Sleep mode). CANL voltage is zero, the CANH voltage measured by the Hg comparator is also close to zero. Depending upon the high-voltage short-circuit, the number of nodes, usage of the SPLIT pin, R actual resistor and In the recessive state, the failure detection to GND or IN mode state (Sleep or Active) the voltage across the bus VBAT is possible. However, it is not possible with the above termination can be sufficient to create a positive dominant implementation to distinguish which of the CANL or CANH voltage between CANH and CANL, and the RXD pin will be lines are shorted to GND or VBAT. A complete diagnostic is low. This would prevent start of any CAN communication and possible once the driver is turned on, and in the dominant thus, proper failure identification requires five pulses on TXD. state. The bus dominant clamp circuit will help to determine such failure situation. Number of Samples for Proper Failure Detection The failure detector requires at least one cycle of the RXD Permanent Recessive Failure (does not apply recessive and dominant states to properly recognize the bus to “C version”) failure. The error will be fully detected after five cycles of the recessive-dominant states. As long as the failure detection The aim of this detection is to diagnose an external circuitry has not detected the same error for five recessive- hardware failure at the RXD output pin and ensure that a dominant cycles, the error is not reported. permanent failure at RXD does not disturb the network communication. If RXD is shorted to a logic high signal, the BUS CLAMPING DETECTION CAN protocol module within the MCU will not recognize any incoming message. In addition, it will not be able to easily If the bus is detected to be in dominant for a time longer distinguish the bus idle state and can start communication at than (T ), the bus failure flag is set and the error is DOM any time. In order to prevent this, RXD failure detection is reported in the SPI. necessary. When a failure is detected, the RXD high flag is set and CAN switches to receive only mode. TXD CANL&H Diag Logic TXD driver Diff output VDD/2 Sampling Sampling Rxsense VDD VDD RXD CANH RXD output RXD short to VDD RXD flag latched RXD driver Diff 60 RXD flag CANL Prop delay The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 35. RXD Path Simplified Schematic, RXD Short to V Detection DD Implementation for Detection external short to VDD at the RXD output, RXD will be tied to a high level and can be detected at the next low to high The implementation senses the RXD output voltage at transition of the differential receiver. each low to high transition of the differential receiver. Excluding the internal propagation delay, the RXD output As soon as the RXD permanent recessive is detected, the should be low when the differential receiver is low. When an RXD driver is deactivated. 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 55

CAN INTERFACE CAN BUS FAULT DIAGNOSTIC Once the error is detected the driver is disabled and the Recovery Condition error is reported via SPI in CAN register. The internal recovery is done by sampling a correct low level at TXD as shown in the following illustration. CANL&H Diff output Sampling Sampling RXD output RXD short to VDD RXD no longer shorted to VDD RXD flag latched RXD flag The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 36. RXD Path Simplified Schematic, RXD Short to V Detection DD TXD PERMANENT DOMINANT low and drives CANH and CANL into a dominant state. Thus the bus is stuck in dominant. No further communication is Principle possible. If the TXD is set to a permanent low level, the CAN bus is Detection and Recovery set into dominant level, and no communication is possible. The device has a TXD permanent timeout detector. After the The TXD permanent dominant timeout will be activated and timeout (T ), the bus driver is disabled and the bus is DOUT release the CANL and CANH drivers. However, at the next released into a recessive state. The TXD permanent flag is incoming dominant bit, the bus will then be stuck in dominant set. again. The recovery condition is same as the TXD dominant failure Recovery The TXD permanent dominant is used and activated when IMPORTANT INFORMATION FOR BUS DRIVER there is a TXD short to RXD. The recovery condition for a REACTIVATION TXD permanent dominant (recovery means the re-activation The driver stays disabled until the failure is/are removed of the CAN drivers) is done by entering into a Normal mode (TXD and/or RXD is no longer permanent dominant or controlled by the MCU or when TXD is recessive while RXD recessive state or shorted) and the failure flags cleared change from recessive to dominant. (read). The CAN driver must be set by SPI in TXD/RXD mode in order to re enable the CAN bus driver. TXD TO RXD SHORT-CIRCUIT Principle When TXD is shorted to RXD during incoming dominant information, RXD is set to low. Consequently, the TXD pin is 34903/4/5 Analog Integrated Circuit Device Data 56 Freescale Semiconductor

LIN BLOCK LIN INTERFACE DESCRIPTION LIN BLOCK LIN INTERFACE DESCRIPTION The physical interface is dedicated to automotive LIN sub- The LIN pin exhibits no reverse current from the LIN bus bus applications. line to VSUP/2, even in the event of a GND shift or VSUP/2 The interface has 20 kbps and 10 kbps baud rates, and disconnection. includes as well as a fast baud rate for test and programming The transmitter has a 20 kbps, 10 kbps and fast baud rate, modes. It has excellent ESD robustness and immunity which are selected by SPI. against disturbance, and radiated emission performance. It has safe behavior when a LIN bus short-to-ground, or a LIN Receiver Characteristics bus leakage during LP mode. The receiver thresholds are ratiometric with the device Digital inputs are related to the device VDD pin. V voltage. SUP/2 If the V voltage goes below typically 6.1 V, the LIN SUP/2 POWER SUPPLY PIN (VSUP/2) bus enters into a recessive state even if communication is The VSUP/2 pin is the supply pin for the LIN interface. To sent on TXD. avoid a false bus message, an undervoltage on VSUP/2 If LIN driver temperature reaches the overtemperature disables the transmission path (from TXD to LIN) when threshold, the transceiver and receiver are disabled. When V falls below 6.1 V. SUP/2 the temperature falls below the overtemperature threshold, LIN driver and receiver will be automatically enabled. GROUND PIN (GND) When there is a ground disconnection at the module level, DATA INPUT PIN (TXD-L, TXD-L1) the LIN interface do not have significant current consumption The TXD-L and TXD-L1 input pin are the MCU interface to on the LIN bus pin when in the recessive state. control the state of the LIN output. When TXD-L is LOW (dominant), LIN output is LOW. When TXD-L is HIGH LIN BUS PIN (LIN AND LIN1) (recessive), the LIN output transistor is turned OFF. The LIN pin represents the single-wire bus transmitter and This pin has an internal pull-up current source to V to DD receiver. It is suited for automotive bus systems, and is force the recessive state if the input pin is left floating. compliant to the LIN bus specification 2.1 and SAEJ2602-2. If the pin stays low (dominant sate) more than t , TXDDOM The LIN interface is only active during Normal mode. the LIN transmitter goes automatically in recessive state. This is reported by flag in LIN register. Driver Characteristics The LIN driver is a LS MOSFET with internal overcurrent DATA OUTPUT PIN (RXD-L AND RXD-L1) thermal shutdown. An internal pull-up resistor with a serial This output pin is the MCU interface, which reports the diode structure is integrated so no external pull-up state of the LIN bus voltage. components are required for the application in a slave node. LIN HIGH (recessive) is reported by a high voltage on An additional pull-up resistor of 1.0 kΩ must be added when RXD, LIN LOW (dominant) is reported by a low voltage on the device is used in the master node. The 1.0 kΩ pull-up RXD. resistor can be connected to the LIN pin or to the ECU battery supply. LIN OPERATIONAL MODES The LIN interface have two operational modes, Transmit When the fast baud rate is selected, the slew rate and receiver and LIN disable modes. timing are much faster than the above specification and allow fast data transition. The LIN interface can be set by the SPI TRANSMIT RECEIVE command in TXD/RXD mode, only when TXD-L is at a high level. When the SPI command is send while TXD-L is low, the In the TXD/RXD mode, the LIN bus can transmit and command is ignored. receive information. When the 20 kbps baud rate is selected, the slew rate and SLEEP MODE timing are compatible with LIN protocol specification 2.1. This mode is selected by SPI, and the transmission path is When the 10 kbps baud rate is selected, the slew rate and disabled. Supply current for LIN block from V is very low timing are compatible with J2602-2. SUP/2 (typically 3.0 μA). LIN bus is monitor to detect Wake-up 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 57

LIN BLOCK LIN OPERATIONAL MODES event. In the Sleep mode, the internal 725 kOhm pull-up recessive transition. This is illustrated in Figures 16 and 17. resistor is connected and the 30 kOhm disconnected. Once the Wake-up is detected, the event is reported to the The LIN block can be awakened from Sleep mode by device state machine. An INT is generated if the device is in detection of LIN bus activity. LP VDD ON mode, or VDD will restart if the device was in LP V OFF mode. DD LIN Bus Activity Detection The Wake-up can be enable or disable by the SPI. The LIN bus Wake-up is recognized by a recessive to Fail-safe Features dominant transition, followed by a dominant level with a Table 11 describes the LIN block behavior when there is a duration greater than 70 μs, followed by a dominant to failure. Table 11. LIN Block Failure FAULT FUNCTIONNAL CONDITION CONSEQUENCE RECOVERY MODE LIN supply undervoltage LIN supply voltage < 6.0 V (typically) LIN transmitter in recessive State Condition gone TXD RXD TXD PDionm Pinearmnta nent TXD pin low for more than t TXDDOM LIN transmitter in recessive State Condition gone TXD RXD LIN driver temperature > 160 °C LIN transmitter and receiver disabled LIN Thermal Shutdown Condition gone (typically) HS turned off 34903/4/5 Analog Integrated Circuit Device Data 58 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE HIGH LEVEL OVERVIEW SERIAL PERIPHERAL INTERFACE HIGH LEVEL OVERVIEW The device uses a 16 bits SPI, with the following • bit 7 to 0 (D7 to D0): control bits arrangements: MISO, Master In Slave Out bits: MOSI, Master Out Slave In bits: • bits 15 to 8 (S15 to S8) are device status bits • bits 15 and 14 (called C1 and C0) are control bits to • bits 7 to 0 (Do7 to Do0) are either extended device select the SPI operation mode (write control bit to status bits, device internal control register content or device register, read back of the control bits, read of device flags. device flag). The SPI implementation does not support daisy chain • bit 13 to 9 (A4 to A0) to select the register address. capability. • bit 8 (P/N) has two functions: parity bit in write mode Figure 37 is an overview of the SPI implementation. (optional, = 0 if not used), Next bit ( = 1) in read mode. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MOSI C1 C0 A4 A3 A2 A1 A0 P/N D7 D6 D5 D4 D3 D2 D1 D0 control bits register address Parity (optional) or data Next bit=1 MISO S15 S14 S13 S12 S11 S10 S9 S8 Do7 Do6 Do5 Do4 Do3 Do2 Do1 Do0 Device Status Extended Device Status, Register Control bits or Device Flags CS active low. Must rise at end of 16 clocks, CS for write commands, MOSI bits [15, 14]=[0, 1] SCLK SCLK signal is low outside of CS active MOSI and MISO data changed at SCLK rising edge MOSI Don’t Care C1 C0 D0 Don’t Care and sampled at falling edge. Msb first. MISO Tri-state S15 S14 Do0 Tri-state MISO tri-state outside of CS active SPI Wave Form, and Signals Polarity Figure 37. SPI Overview 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 59

SERIAL PERIPHERAL INTERFACE DETAIL OPERATION DETAIL OPERATION SPI Operation Deviation (does not apply to “C” version) When the previous steps are implemented, the device will operate as follows: In some cases, the SPI write command is not properly interpreted by the device. This results in either a “non For a given SPI write command (named SPI write ‘n’): received SPI command” or a “corrupted SPI command”. • In case the SPI write command ‘n’ is not accepted, the Important: Due to this, the tLEAD and tCSLOW parameters following SPI command (named SPI ‘n+1’) will finish the must be carefully acknowledged. write process of the SPI write ‘n’, thanks to step 2 Only SPI write commands (starting with bits 15,14 = 01) (tLAG > 550 ns) and step 3 (which is the additional SPI are affected. The SPI read commands (starting with bits command ‘n+1’). 15,14 = 00 or 11) are not affected. • By applying steps 1, 2, and 3, no SPI command is ignored. The occurrence of this issue is extremely low and is Worst case, the SPI write ‘n’ is executed at the time the caused by the synchronization between internal and external SPI ‘n+1’ is sent. This will lead to a delay in device signals. In order to guarantee proper operation, the following operation (delay between SPI command ‘n’ and ‘n+1’). steps must be taken. Note: Occurrence of an incorrect command is reduced, thanks to step 1 (extension of t duration to >5.5 μs). 1. Ensure the duration of the Chip Select Low (t ) CSLOW CSLOW state is >5.5 μs. Sequence examples: Note: In data sheet revisions prior to 7.0, this parameter is Example 1: not specified and is indirectly defined by the sum of 3 • 0x60C0 (CAN interface control) – in case this command is parameters, t + 16 x t + t (sum = 4.06 μs). missed, next write command will complete it LEAD PCLK LAG 2. Ensure SPI timing parameter t is a min. of • 0x66C0 (LIN interface control) – in case this command is LEAD missed, next read command will complete it 550 ns. • 0x2580 (read device ID) – Additional command to Note: In data sheet revisions prior to 7.0, the t LEAD complete previous LIN command, in case it was missed parameter is a min of 30 ns. Example 2: 3. Make sure to include a SPI read command after a • 0x60C0 (CAN interface control) - in case this command is SPI write command. missed, next write command will complete it In case a series of SPI write commands is used, only one • 0x66C0 (LIN interface control) - in case this command is additional SPI read is necessary. The recommended SPI missed, next read command will complete it read command is “device ID read: 0x2580” so device • 0x2100 (read CAN register content) – this command will operation is not affected (ex: clear flag). Other SPI read complete previous one, in case it was missed commands may also be used. • 0x2700 (read LIN register content) BITS 15, 14, AND 8 FUNCTIONS Table 12 summarizes the various SPI operation, depending upon bit 15, 14, and 8. Table 12. SPI Operations (bits 8, 14, & 15) Parity/Next Control Bits MOSI[15-14], C1-C0 Type of Command Note for Bit 8 P/N MOSI[8] P/N 00 Read back of register 1 Bit 8 must be set to 1, independently of the parity function content and block (CAN, selected or not selected. I/O, INT, LINs) real time state. See Table 38. 01 Write to register 0 If bit 8 is set to “0”: means parity not selected OR address, to control the parity is selected AND parity = 0 device operation 1 if bit 8 is set to “1”: means parity is selected AND parity = 1 10 Reserved 11 Read of device flags 1 Bit 8 must be set to 1, independently of the parity function form a register address selected or not selected. 34903/4/5 Analog Integrated Circuit Device Data 60 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE DETAIL OPERATION BITS 13-9 FUNCTIONS Device Status on MISO The device contains several registers coded on five bits When a write operation is performed to store data or (bits 13 to 9). control bits into the device, the MISO pin reports a 16 bit fixed Each register controls or reports part of the device’s device status composed of 2 bytes: Device Fixed Status (bits function. Data can be written to the register to control the 15 to 8) + extended Device Status (bits 7 to 0). In a read device operation or to set the default value or behavior. operation, MISO will report the Fixed device status (bits 15 to 8) and the next eight bits will be the content of the selected Every register can also be read back in order to ensure register. that it’s content (default setting or value previously written) is correct. REGISTER ADRESS TABLE In addition, some of the registers are used to report device flags. Table 13 is a list of device registers and addresses, coded with bits 13 to 9. Table 13. Device Registers with Corresponding Address Address Quick Ref. MOSI[13-9] Description Functionality Name A4...A0 0_0000 Analog Multiplexer MUX 1) Write “device control bits” to register address. 2) Read back register “control bits” 0_0001 Memory byte A RAM_A 1) Write “data byte” to register address. 2) Read back “data byte” from register address 0_0010 Memory byte B RAM_B 0_0011 Memory byte C RAM_C 0_0100 Memory byte D RAM_D 0_0101 Initialization Regulators Init REG 1) Write “device initialization control bits” to register address. 2) Read back “initialization control bits” from register address 0_0110 Initialization Watchdog Init watchdog 0_0111 Initialization LIN and I/O Init LIN I/O 0_1000 Initialization Miscellaneous functions Init MISC 0_1001 Specific modes SPE_MODE 1) Write to register to select device Specific mode, using “Inverted Random Code”. 2) Read “Random Code” 0_1010 Timer_A: watchdog & LP MCU consumption TIM_A 1) Write “timing values” to register address. 2) Read back register “timing values” 0_1011 Timer_B: Cyclic Sense & Cyclic Interrupt TIM_B 0_1100 Timer_C: watchdog LP & Forced Wake-up TIM_C 0_1101 Watchdog Refresh watchdog Watchdog Refresh Commands 0_1110 Mode register MODE 1) Write to register to select LP mode, with optional “Inverted Random code” and select Wake-up functionality 2) Read operations: Read back device “Current mode” Read “Random Code”, Leave “Debug mode” 0_1111 Regulator Control REG 1_0000 CAN interface control CAN 1) Write “device control bits” to register address, to select device operation. 1_0001 Input Output control I/O 2) Read back register “control bits”. 1_0010 Interrupt Control Interrupt 3) Read device flags from each of the register addresses. 1_0011 LIN1 interface control LIN1 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 61

SERIAL PERIPHERAL INTERFACE DETAIL OPERATION COMPLETE SPI OPERATION Table 14 is a compiled view of all the SPI capabilities and options. Both MOSI and MISO information are described. Table 14. SPI Capabilities with Options MOSI/ Control bits Address Parity/Next Type of Command Bit 7 Bits [6-0] MISO [15-14] [13-9] bits [8] Read back of “device control bits” (MOSI bit 7 = 0) MOSI 00 address 1 0 000 0000 OR MISO Device Fixed Status (8 bits) Register control bits content Read specific device information (MOSI bit 7 = 1) MOSI 00 address 1 1 000 0000 MISO Device Fixed Status (8 bits) Device ID and I/Os state Write device control bit to address selected by bits MOSI 01 address (note) Control bits (13-9). MISO return 16 bits device status MISO Device Fixed Status (8 bits) Device Extended Status (8 bits) Reserved MOSI 10 Reserved MISO Reserved Read device flags and Wake-up flags, from MISO 11 address Reserved 0 Read of device flags form a register address, register address (bit 13-9), and sub address (bit 7). and sub address LOW (bit 7) MISO return fixed device status (bit 15-8) + flags from the selected address and sub-address. MOSI Device Fixed Status (8 bits) Flags MISO 11 address 1 1 Read of device flags form a register address, and sub address HIGH (bit 7) MOSI Device Fixed Status (8 bits) Flags Note: P = 0 if parity bit is not selected or parity = 0. P = 1 if parity Thus the Exact command will then be: is selected and parity = 1. MOSI [bit 15-0] = 01 00 011 0 01101001 PARITY BIT 8 Examples 2: MOSI [bit 15-0] = 01 00 011 P 0100 0000, P should be 1, Calculation because the command contains 4 bits with logic 1. The parity is used for the write-to-register command (bit Thus the Exact command will then be: 15,14 = 01). It is calculated based on the number of logic one MOSI [bit 15-0] = 01 00 011 1 0100 0000 contained in bits 15-9,7-0 sequence (this is the entire 16 bits of the write command except bit 8). Parity Function Selection Bit 8 must be set to 0 if the number of 1 is odd. All SPI commands and examples do not use parity Bit 8 must be set to 1if the number of 1 is even. functions. The parity function is optional. It is selected by bit 6 in INIT Examples 1: MISC register. MOSI [bit 15-0] = 01 00 011 P 01101001, P should be 0, If parity function is not selected (bit 6 of INIT MISC = 0), because the command contains 7 bits with logic 1. then Parity bits in all SPI commands (bit 8) must be “0”. 34903/4/5 Analog Integrated Circuit Device Data 62 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING DETAIL OF CONTROL BITS AND REGISTER MAPPING The following tables contain register bit meaning arranged by register address, from address 0_000 to address 1_0100 MUX AND RAM REGISTERS Table 15. MUX Register(32) MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 0_0000 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 000 P MUX_2 MUX_1 MUX_0 Int 2K I/O-att 0 0 0 Default state 0 0 0 0 0 0 0 0 Condition for default POR, 5 V-CAN off, any mode different from Normal Bits Description b7 b6 b5 MUX_2, MUX_1, MUX_0 - Selection of external input signal or internal signal to be measured at MUX-OUT pin 000 All functions disable. No output voltage at MUX-OUT pin 001 VDD regulator current recopy. Ratio is approx 1/97. Requires an external resistor or selection of Internal 2.0 K (bit 3) 010 Device internal voltage reference (approx 2.5 V) 011 Device internal temperature sensor voltage 100 Voltage at I/O-0. Attenuation or gain is selected by bit 3. 101 Voltage at I/O-1. Attenuation or gain is selected by bit 3. 110 Voltage at VSUP/1 pin. Refer to electrical table for attenuation ratio (approx 5) 111 Voltage at VSENSE pin. Refer to electrical table for attenuation ratio (approx 5) b4 INT 2k - Select device internal 2.0 kohm resistor between AMUX and GND. This resistor allows the measurement of a voltage proportional to the VDD output current. 0 Internal 2.0 kohm resistor disable. An external resistor must be connected between AMUX and GND. 1 Internal 2.0 kohm resistor enable. b3 I/O-att - When I/O-0 (or I/O-1) is selected with b7,b6,b5 = 100 (or 101), b3 selects attenuation or gain between I/O-0 (or I/O-1) and MUX-OUT pin 0 Gain is approx 2 for device with VDD = 5.0 V (Ref. to electrical table for exact gain value) Gain is approx 1.3 for device with VDD = 3.3 V (Ref. to electrical table for exact gain value) 1 Attenuation is approx 4 for device with VDD = 5.0 V (Ref. to electrical table for exact attenuation value) Attenuation is approx 6 for device with VDD = 3.3 V (Ref. to electrical table for exact attenuation value) Notes 32. The MUX register can be written and read only when the 5V-CAN regulator is ON. If the MUX register is written or read while 5V-CAN is OFF, the command is ignored, and the MXU register content is reset to default state (all control bits = 0). 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 63

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 16. Internal Memory Registers A, B, C, and D, RAM_A, RAM_B, RAM_C, and RAM_D MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 0_0xxx [P/N] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 01 00 _ 001 P Ram a7 Ram a6 Ram a5 Ram a4 Ram a3 Ram a2 Ram a1 Ram a0 Default state 0 0 0 0 0 0 0 0 Condition for default POR 01 00 _ 010 P Ram b7 Ram b6 Ram b5 Ram b4 Ram b3 Ram b2 Ram b1 Ram b0 Default state 0 0 0 0 0 0 0 0 Condition for default POR 01 00 _ 011 P Ram c7 Ram c6 Ram c5 Ram c4 Ram c3 Ram c2 Ram c1 Ram c0 Default state 0 0 0 0 0 0 0 0 Condition for default POR 01 00 _ 100 P Ram d7 Ram d6 Ram d5 Ram d4 Ram d3 Ram d2 Ram d1 Ram d0 Default state 0 0 0 0 0 0 0 0 Condition for default POR INIT REGISTERS Note: these registers can be written only in INIT mode Table 17. Initialization Regulator Registers, INIT REG (note: register can be written only in INIT mode) MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 0_0101 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 101 P I/O-x sync VDDL rst[1] VDDL rst[0] VDD rstD[1] VDD rstD[0] VAUX5/3 Cyclic on[1] Cyclic on[0] Default state 1 0 0 0 0 0 0 0 Condition for default POR Bit Description b7 I/O-x sync - Determine if I/O-1 is sensed during I/O-0 activation, when cyclic sense function is selected 0 I/O-1 sense anytime 1 I/O-1 sense during I/O-0 activation b6, b5 VDDL RST[1] VDDL RST[0] - Select the VDD undervoltage threshold, to activate RST pin and/or INT 00 Reset at approx 0.9 VDD. 01 INT at approx 0.9 VDD, Reset at approx 0.7 VDD 10 Reset at approx 0.7 VDD 11 Reset at approx 0.9 VDD. b4, b3 VDD RSTD[1] VDD RSTD[0] - Select the RST pin low lev duration, after VDD rises above the VDD undervoltage threshold 00 1.0 ms 01 5.0 ms 10 10 ms 11 20 ms b2 [VAUX 5/3] - Select Vauxilary output voltage 0 VAUX = 3.3 V 34903/4/5 Analog Integrated Circuit Device Data 64 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Bit Description 1 VAUX = 5.0 V b1, b0 Cyclic on[1] Cyclic on[0] - Determine I/O-0 activation time, when cyclic sense function is selected 00 200 μs (typical value. Ref. to dynamic parameters for exact value) 01 400 μs (typical value. Ref. to dynamic parameters for exact value) 10 800 μs (typical value. Ref. to dynamic parameters for exact value) 11 1600 μs (typical value. Ref. to dynamic parameters for exact value) Table 18. Initialization Watchdog Registers, INIT watchdog (note: register can be written only in INIT mode) MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 0_0110 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 110 P WD2INT MCU_OC OC-TIM WD Safe WD_spi[1] WD_spi[0] WD N/Win Crank Default state 0 1 0 0 0 1 0 Condition for default POR Bit Description b7 WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command 0 Function disable. No constraint between INT occurrence and INT source read. 1 INT source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods. b6, b5 MCU_OC, OC-TIM - In LP VDD ON, select watchdog refresh and VDD current monitoring functionality. VDD_OC_LP threshold is defined in device electrical parameters (approx 1.5 mA) In LP mode, when watchdog is not selected no watchdog In LP VDD ON mode, VDD overcurrent has no effect + 00 no watchdog In LP VDD ON mode, VDD overcurrent has no effect + 01 no watchdog In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time > 100 μs (typically) is a wake-up event + 10 no watchdog In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer register + 11 (selection range from 3.0 to 32 ms) In LP mode when watchdog is selected watchdog + In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command. 00 watchdog + In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command. 01 watchdog + In LP VDD ON mode, VDD overcurrent for a time > 100 μs (typically) is a wake-up event. 10 watchdog + In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time < I_mcu_OC is a watchdog refresh condition. VDD current > VDD_OC_LP 11 threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer register (selection range from 3.0 to 32 ms) b4 WD Safe - Select the activation of the SAFE pin low, at first or second consecutive RESET pulse 0 SAFE pin is set low at the time of the RST pin low activation 1 SAFE pin is set low at the second consecutive time RST pulse b3, b2 WD_spi[1] WD_spi[0] - Select the Watchdog (watchdog) Operation 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 65

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Bit Description 00 Simple Watchdog selection: watchdog refresh done by a 8 bits or 16 bits SPI 01 Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits. 10 Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command. 11 Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command. b1 WD N/Win - Select the Watchdog (watchdog) Window or Timeout operation 0 Watchdog operation is TIMEOUT, watchdog refresh can occur anytime in the period 1 Watchdog operation is WINDOW, watchdog refresh must occur in the open window (second half of period) b0 Crank - Select the VSUP/1 threshold to disable VDD, while VSUP1 is falling toward GND 0 VDD disable when VSUP/1 is below typically 4.0 V (parameter VSUP-TH1), and device in Reset mode 1 VDD kept ON when VSUP/1 is below typically 4.0 V (parameter VSUP_TH1) Table 19. Initialization LIN and I/O Registers, INIT LIN I/O (note: register can be written only in INIT mode) MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 0_0111 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 111 P I/O-1 ovoff LIN_T2[1] LIN_T2[0] LIN_T/1[1] LIN_T/1[0] I/O-1 out-en I/O-0 out-en Cyc_Inv Default state 0 0 0 0 0 0 0 Condition for default POR Bit Description b7 I/O-1 ovoff - Select the deactivation of I/O-1 when VDD or VAUX overvoltage condition is detected 0 Disable I/O-1 turn off. 1 Enable I/O-1 turn off, when VDD or VAUX overvoltage condition is detected. b6, b5 LIN_T2[1], LIN_T2[0] - Select pin operation for I/O 00 pin is OFF 01 Reserved configuration. Do not use 10 pin operation as I/O: HS switch and Wake-up input 11 N/A b4, b3 LIN_T/1[1], LIN_T/1[0] - Select pin operation as LIN Master pin switch or I/O 00 pin is OFF 01 pin operation as LIN Master pin switch 10 pin operation as I/O: HS switch and Wake-up input 11 N/A b2 I/O-1 out-en- Select the operation of the I/O-1 as output driver (HS, LS) 0 Disable HS and LS drivers of pin I/O-1. I/O-1 can only be used as input. 1 Enable HS and LS drivers of pin I/O-1. Pin can be used as input and output driver. b1 I/O-0 out-en - Select the operation of the I/O-0 as output driver (HS, LS) 34903/4/5 Analog Integrated Circuit Device Data 66 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Bit Description 0 Disable HS and LS drivers of I/O-0 can only be used as input. 1 Enable HS and LS drivers of the I/O-0 pin. Pin can be used as input and output drivers. b0 Cyc_Inv - Select I/O-0 operation in device LP mode, when cyclic sense is selected 0 During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, I/O-0 is disable (HS and LS drivers OFF). 1 During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, the opposite driver of I/ O_0 is actively set. Example: If I/0_0 HS is ON during active time, then I/O_O LS is turned ON at expiration of the active time, for the duration of the cyclic sense period. Table 20. Initialization Miscellaneous Functions, INIT MISC (Note: Register can be written only in INIT mode) MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 0_1000 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 000 P LPM w RNDM SPI parity INT pulse INT width INT flash Dbg Res[2] Dbg Res[1] Dbg Res[0] Default state 0 0 0 0 0 0 0 Condition for default POR Bit Description b7 LPM w RNDM - This enables the usage of random bits 2, 1 and 0 of the MODE register to enter into LP VDD OFF or LP VDD ON. 0 Function disable: the LP mode can be entered without usage of Random Code 1 Function enabled: the LP mode is entered using the Random Code b6 SPI parity - Select usage of the parity bit in SPI write operation 0 Function disable: the parity is not used. The parity bit must always set to logic 0. 1 Function enable: the parity is used, and parity must be calculated. b5 INT pulse -Select INT pin operation: low level pulse or low level 0 INT pin will assert a low level pulse, duration selected by bit [b4] 1 INT pin assert a permanent low level (no pulse) b4 INT width - Select the INT pulse duration 0 INT pulse duration is typically 100 μs. Ref. to dynamic parameter table for exact value. 1 INT pulse duration is typically 25 μs. Ref. to dynamic parameter table for exact value. b3 INT flash - Select INT pulse generation at 50% of the Watchdog Period in Flash mode Function disable Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in Flash mode. b2, b1, b0 Dbg Res[2], Dbg Res[1], Dbg Res[0] - Allow verification of the external resistor connected at DBG pin. Ref. to parametric table for resistor range value.(33) 0xx Function disable 100 100 verification enable: resistor at DBG pin is typically 68 kohm (RB3) - Selection of SAFE mode B3 101 101 verification enable: resistor at DBG pin is typically 33 kohm (RB2 - Selection of SAFE mode B2 110 110 verification enable: resistor at DBG pin is typically 15 kohm (RB1) - Selection of SAFE mode B1 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 67

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Bit Description 111 111 verification enable: resistor at DBG pin is typically 0 kohm (RA) - Selection of SAFE mode A Notes 33. Bits b2,1 and 0 allow the following operation: First, check the resistor device has detected at the DEBUG pin. If the resistor is different, bit 5 (Debug resistor) is set in INTerrupt register (Ref. to device flag table). Second, over write the resistor decoded by device, to set the SAFE mode operation by SPI. Once this function is selected by bit 2 = 1, this selection has higher priority than “hardware”, and device will behave according to b2,b1 and b0 setting SPECIFIC MODE REGISTER Table 21. Specific Mode Register, SPE_MODE MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 01_001 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 001 P Sel_Mod[1] Sel_Mod[0] Rnd_C5b Rnd_C4b Rnd_C3b Rnd_C2b Rnd_C1b Rnd_C0b Default state 0 0 0 0 0 0 0 Condition for default POR Bit Description b7, b6 Sel_Mod[1], Sel_Mod[0] - Mode selection: these 2 bits are used to select which mode the device will enter upon a SPI command. 00 RESET mode 01 INIT mode 10 FLASH mode 11 N/A b5....b0 [Rnd_C4b... Rnd_C0b] - Random Code inverted, these six bits are the inverted bits obtained from the SPE MODE Register read command. The SPE MODE Register is used for the Following 2) Write INIT mode + random code inverted Operation MOSI : 0101 0010 01 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 - Set the device in RESET mode, to exercise or test the HH] (RIX = random code inverted) RESET functions. MISO : xxxx xxxx xxxx xxxx (don’t care) - Go to INIT mode, using the Secure SPi command. SAFE pin activation: SAFE pin can be set low, only in INIT - Go to FLASH mode (in this mode the watchdog timer can mode, with following commands: be extended up to 32 s). 1) Read random code: - Activate the SAFE pin by S/W. MOSI : 0001 0011 0000 0000 [Hex:0x 13 00] This mode (called Special mode) is accessible from the MISO report 16 bits, random code are bits (5-0) secured SPI command, which consist of 2 commands: miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits 1) reading a random code and random code) 2) then write the inverted random code plus mode 2) Write INIT mode + random code bits 5:4 not inverted selection or SAFE pin activation: and random code bits 3:0 inverted Return to INIT mode is done as follow (this is done from MOSI : 0101 0010 01 R5 R4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 Normal mode only): HH] (R = random code inverted) IX 1) Read random code: MISO : xxxx xxxx xxxx xxxx (don’t care) MOSI : 0001 0011 0000 0000 [Hex:0x 13 00] Return to Reset or Flash mode is done similarly to the go MISO report 16 bits, random code are bits (5-0) to INIT mode, except that the b7 and b6 are set according to the table above (b7, b6 = 00 - go to reset, b7, b6 = 10 - go to miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits Flash). random code) 34903/4/5 Analog Integrated Circuit Device Data 68 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING TIMER REGISTERS Table 22. Timer Register A, LP V Overcurrent & Watchdog Period Normal mode, TIM_A DD MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 01_010 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 010 P I_mcu[2] I_mcu[1] I_mcu[1] watchdog W/D_N[4] W/D_Nor[3] W/D_N[2] W/D_Nor[0] Nor[4] Default state 0 0 0 1 1 1 1 0 Condition for default POR LP VDD Overcurrent (ms) b6, b5 b7 00 01 10 11 0 3 (def) 6 12 24 1 4 8 16 32 Watchdog Period in Device Normal Mode (ms) b2, b1, b0 b4, b3 000 001 010 011 100 101 110 111 00 2.5 5 10 20 40 80 160 320 01 3 6 12 24 48 96 192 384 10 3.5 7 14 28 56 112 224 448 11 4 8 16 32 64 128 256 (def) 512 Table 23. Timer Register B, Cyclic Sense and Cyclic INT, in Device LP Mode, TIM_B MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 01_011 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 011 P Cyc-sen[3] Cyc-sen[2] Cyc-sen[1] Cyc-sen[0] Cyc-int[3] Cyc-int[2] Cyc-int[1] Cyc-int[0] Default state 0 0 0 0 0 0 0 0 Condition for default POR Cyclic Sense (ms) b6, b5, b4 b7 000 001 010 011 100 101 110 111 0 3 6 12 24 48 96 192 384 1 4 8 16 32 64 128 256 512 Cyclic Interrupt (ms) b2, b1, b0 b3 000 001 010 011 100 101 110 111 0 6 (def) 12 24 48 96 192 384 768 1 8 16 32 64 128 258 512 1024 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 69

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 24. Timer Register C, Watchdog LP Mode or Flash Mode and Forced Wake-up Timer, TIM_C MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 01_100 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 100 P WD-LP-F[3] WD-LP-F[2] WD-LP-F[1] WD-LP-F[0] FWU[3] FWU[2] FWU[1] FWU[0] Default state 0 0 0 0 0 0 0 0 Condition for default POR Table 25. Typical Timing Values Watchdog in LP VDD ON Mode (ms) b6, b5, b4 b7 000 001 010 011 100 101 110 111 0 12 24 48 96 192 384 768 1536 1 16 32 64 128 256 512 1024 2048 Watchdog in Flash Mode (ms) b6, b5, b4 b7 000 001 010 011 100 101 110 111 0 48 (def) 96 192 384 768 1536 3072 6144 1 256 512 1024 2048 4096 8192 16384 32768 Forced Wake-up (ms) b2, b1, b0 b3 000 001 010 011 100 101 110 111 0 48 (def) 96 192 384 768 1536 3072 6144 1 64 128 258 512 1024 2048 4096 8192 WATCHDOG AND MODE REGISTERS Table 26. Watchdog Refresh Register, watchdog(34) MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 01_101 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 101 P 0 0 0 0 0 0 0 0 Default state 0 0 0 0 0 0 0 0 Condition for default POR Notes 34. The Simple Watchdog Refresh command is in hexadecimal: 5A00. This command is used to refresh the watchdog and also to transition from INIT mode to Normal mode, and from Normal Request mode to Normal mode (after a wake-up of a reset) . Table 27. MODE Register, MODE MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 01_110 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 110 P mode[4] mode[3] mode[2] mode[1] mode[0] Rnd_b[2] Rnd_b[1] Rnd_b[0] Default state N/A N/A N/A N/A N/A N/A N/A N/A 34903/4/5 Analog Integrated Circuit Device Data 70 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 28. LP V OFF Selection and FWU / Cyclic Sense Selection DD b7, b6, b5, b4, b3 FWU Cyclic Sense 0 1100 OFF OFF 0 1101 OFF ON 0 1110 ON OFF 0 1111 ON ON Table 29. LP V ON Selection and Operation Mode DD b7, b6, b5, b4, b3 FWU Cyclic Sense Cyclic INT Watchdog 1 0000 OFF OFF OFF OFF 1 0001 OFF OFF OFF ON 1 0010 OFF OFF ON OFF 1 0011 OFF OFF ON ON 1 0100 OFF ON OFF OFF 1 0101 OFF ON OFF ON 1 0110 OFF ON ON OFF 1 0111 OFF ON ON ON 1 1000 ON OFF OFF OFF 1 1001 ON OFF OFF ON 1 1010 ON OFF ON OFF 1 1011 ON OFF ON ON 1 1100 ON ON OFF OFF 1 1101 ON ON OFF ON 1 1110 ON ON ON OFF 1 1111 ON ON ON ON b2, b1, b0 Random Code inverted, these 3bits are the inverted bits obtained from the previous SPI command. The usage of these bits are optional and must be previously selected in the INIT MISC register [See bit 7 (LPM w RNDM) in Table 20] Prior to enter in LP V ON or LP V OFF, the Wake-up Mode Register Features DD DD flags must be cleared or read. The mode register includes specific functions and a “global This is done by the following SPI commands (See Table SPI command” that allow the following: 38, Device Flag, I/O Real Time and Device Identification): - read device current mode 0xE100 for CAN Wake-up clear - read device Debug status 0xE380 for I/O Wake-up clear - read state of SAFE pin 0xE700 for LIN1 Wake-up clear - leave Debug state If Wake-up flags are not cleared, the device will enter into - release or turn off SAFE pin the selected LP mode and immediately Wake-up. In addition, - read a 3 bit Random Code to enter in LP mode the CAN failure flags (i.e. CAN_F and CAN_UF) must be cleared in order to meet the low power current consumption These global commands are built using the MODE register specification. This is done by the following SPI command: address bit [13-9], along with several combinations of bit [15- 14] and bit [7]. Note, bit [8] is always set to 1. 0xE180 (read CAN failure flags) When the device is in LP V ON mode, the Wake-up by DD a SPI command uses a write to “Normal Request mode”, 0x5C10. 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 71

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Entering into LP Mode Using Random Code 1. in hex: 0x5C60 to enter in LP VDD OFF mode without using the 3 random code bits. - LP mode using Random Code must be selected in INIT mode via bit 7 of the INIT MISC register. 2. if Random Code is selected, the commands are: - In Normal mode, read the Random Code using 0x1D00 or - Read Random Code: 0x1D00 or 0x1D80, 0x1D80 command. The 3 Random Code bits are available on MISO report in binary: bits 15-8, bits 7-3, Rnd_[2], Rnd_[1], MISO bits 2,1 and 0. Rnd_[0]. - Write LP mode by inverting the 3 random bits. - Write LP VDD OFF mode, using Random Code inverted: Example - Select LP VDD OFF without cyclic sense and in binary: 0101 1100 0110 0 Rnd_b[2], Rnd_b[1], Rnd_b[0]. FWU: Table 30 summarizes these commands Table 30. Device Modes Global commands and effects Read device current mode, Leave debug mode. MOSI bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0 Keep SAFE pin as is. 00 01 110 1 0 000 0000 MOSI in hexadecimal: 1D 00 MISO bit 15-8 bit 7-3 bit 2-0 Fix Status device current mode Random code Read device current mode MOSI bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0 Release SAFE pin (turn OFF). 00 01 110 1 1 000 0000 MOSI in hexadecimal: 1D 80 MISO bit 15-8 bit 7-3 bit 2-0 Fix Status device current mode Random code Read device current mode, Leave debug mode. MOSI bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0 Keep SAFE pin as is. 11 01 110 1 0 000 0000 MOSI in hexadecimal: DD 00 MISO reports Debug and SAFE state (bits 1,0) MISO bit 15-8 bit 7-3 bit 2 bit 1 bit 0 Fix Status device current mode X SAFE DEBUG Read device current mode, Keep DEBUG mode MOSI bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0 Release SAFE pin (turn OFF). 11 01 110 1 1 000 0000 MOSI in hexadecimal: DD 80 MISO reports Debug and SAFE state (bits 1,0) MISO bit 15-8 bit 7-3 bit 2 bit 1 bit 0 Fix Status device current mode X SAFE DEBUG Table 31 describes MISO bits 7-0, used to decode the Table 32. SAFE and DEBUG status device’s current mode. SAFE and DEBUG bits Table 31. MISO bits 7-3 b1 description Device current mode, any of the above commands 0 SAFE pin OFF, not activated b7, b6, b5, b4, b3 MODE 1 SAFE pin ON, driver activated. 0 0000 INIT b0 description 0 0001 FLASH 0 Debug mode OFF 0 0010 Normal Request 1 Debug mode Active 0 0011 Normal mode 1 XXXX Low Power mode (Table 29) Table 32 describes the SAFE and DEBUG bit decoding. 34903/4/5 Analog Integrated Circuit Device Data 72 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING REGULATOR, CAN, I/O, INT AND LIN REGISTERS Table 33. Regulator Register MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 01_111 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 111 P VAUX[1] VAUX[0] - 5V-can[1] 5V-can[0] VDD bal en VDD bal auto VDD OFF en Default state 0 0 N/A 0 0 N/A N/A N/A Condition for default POR POR Bits Description b7 b6 VAUX[1], VAUX[0] - Vauxilary regulator control 00 Regulator OFF 01 Regulator ON. Undervoltage (UV) and Overcurrent (OC) monitoring flags not reported. VAUX is disabled when UV or OC detected after 1.0 ms blanking time. 10 Regulator ON. Undervoltage (UV) and overcurrent (OC) monitoring flags active. VAUX is disabled when UV or OC detected after 1.0 ms blanking time. 11 Regulator ON. Undervoltage (UV) and overcurrent (OC) monitoring flags active. VAUX is disabled when UV or OC detected after 25 μs blanking time. b4 b3 5 V-can[1], 5 V-can[0] - 5V-CAN regulator control 00 Regulator OFF 01 Regulator ON. Thermal protection active. Undervoltage (UV) and overcurrent (OC) monitoring flags not reported. 1.0 ms blanking time for UV and OC detection. Note: by default when in Debug mode 10 Regulator ON. Thermal protection active. Undervoltage (UV) and overcurrent (OC) monitoring flags active. 1.0 ms blanking time for UV and OC detection. 11 Regulator ON. Thermal protection active. Undervoltage (UV) and overcurrent (OC) monitoring flags active after 25 μs blanking time. b2 VDD bal en - Control bit to Enable the VDD external ballast transistor 0 External VDD ballast disable 1 External VDD ballast Enable b1 VDD bal auto - Control bit to automatically Enable the VDD external ballast transistor, if VDD is > typically 60 mA 0 Disable the automatic activation of the external ballast 1 Enable the automatic activation of the external ballast, if VDD > typically 60 mA b0 VDD OFF en - Control bit to allow transition into LP VDD OFF mode (to prevent VDD turn OFF) 0 Disable Usage of LP VDD OFF mode 1 Enable Usage of LP VDD OFF mode 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 73

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 34. CAN Register(35) MOSI Second Byte, bits 7-0 MOSI First byte [15-8] [b_15 b_14] 10_000 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 000P CAN mod[1] CAN mod[0] Slew[1] Slew[0] Wake-up 1/3 - - CAN int Default state 1 0 0 0 0 - - 0 Condition for default note POR POR POR Bits Description b7 b6 CAN mod[1], CAN mod[0] - CAN interface mode control, Wake-up enable / disable 00 CAN interface in Sleep mode, CAN Wake-up disable. 01 CAN interface in receive only mode, CAN driver disable. 10 CAN interface is in Sleep mode, CAN Wake-up enable. In device LP mode, CAN Wake-up is reported by device Wake-up. In device Normal mode, CAN Wake-up reported by INT. 11 CAN interface in transmit and receive mode. b5 b4 Slew[1] Slew[0] - CAN driver slew rate selection 00/11 FAST 01 MEDIUM 10 SLOW b3 Wake-up 1/3 - Selection of CAN Wake-up mechanism 0 3 dominant pulses Wake-up mechanism 1 Single dominant pulse Wake-up mechanism b0 CAN INT - Select the CAN failure detection reporting 0 Select INT generation when a bus failure is fully identified and decoded (i.e. after 5 dominant pulses on TxCAN) 1 Select INT generation as soon as a bus failure is detected, event if not fully identified Notes 35. The first time the device is set to Normal mode, the CAN is in Sleep Wake-up enabled (bit7 = 1, bit 6 =0). The next time the device is set in Normal mode, the CAN state is controlled by bits 7 and 6. 34903/4/5 Analog Integrated Circuit Device Data 74 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 35. I/O Register MOSI Second Byte, bits 7-0 MOSI First byte [15-8] [b_15 b_14] 10_001 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 001P I/O-3 [1] I/O-3 [0] I/O-2 [1] I/O-2 [0] I/O-1 [1] I/O-1 [0] I/O-0 [1] I/O-0 [0] Default state 0 0 0 0 0 0 0 0 Condition for default POR Bits Description b7 b6 I/O-3 [1], I/O-3 [0] - I/O-3 pin operation 00 I/O-3 driver disable, Wake-up capability disable 01 I/O-3 driver disable, Wake-up capability enable. 10 I/O-3 HS driver enable. 11 I/O-3 HS driver enable. b5 b4 I/O-2 [1], I/O-2 [0] - I/O-2 pin operation 00 I/O-2 driver disable, Wake-up capability disable 01 I/O-2 driver disable, Wake-up capability enable. 10 I/O-2 HS driver enable. 11 I/O-2 HS driver enable. b3 b2 I/O-1 [1], I/O-1 [0] - I/O-1 pin operation 00 I/O-1 driver disable, Wake-up capability disable 01 I/O-1 driver disable, Wake-up capability enable. 10 I/O-1 LS driver enable. 11 I/O-1 HS driver enable. b1 b0 I/O-0 [1], I/O-0 [0] - I/O-0 pin operation 00 I/O-0 driver disable, Wake-up capability disable 01 I/O-0 driver disable, Wake-up capability enable. 10 I/O-0 LS driver enable. 11 I/O-0 HS driver enable. 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 75

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 36. INT Register MOSI Second Byte, bits 7-0 MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 010P CAN failure MCU req 0 LIN1fail I/O SAFE - Vmon Default state 0 0 0 0 0 0 0 0 Condition for default POR Bits Description CAN failure - control bit for CAN failure INT (CANH/L to GND, VDD or VSUP, CAN overcurrent, Driver Overtemp, TXD-PD, b7 RXD-PR, RX2HIGH, and CANBUS Dominate clamp) 0 INT disable 1 INT enable. b6 MCU req - Control bit to request an INT. INT will occur once when the bit is enable 0 INT disable 1 INT enable. b4 LIN/1 fail - Control bit to enable INT when of failure on LIN1 interface 0 INT disable 1 INT enable. b3 I/O - Bit to control I/O interruption: I/O failure 0 INT disable 1 INT enable. b2 SAFE - Bit to enable INT when of: Vaux overvoltage, VDD overvoltage, VDD Temp pre-warning, VDD undervoltage(36), SAFE resistor mismatch, RST terminal short to VDD, MCU request INT.(37) 0 INT disable 1 INT enable. b0 VMON - enable interruption by voltage monitoring of one of the voltage regulator: VAUX, 5 V-CAN, VDD (IDD Overcurrent, VSUV, V , V , 5V-CAN low or thermal shutdown, V low or V overcurrent SOV SENSELOW AUX AUX 0 INT disable 1 INT enable. Notes 36. If VDD undervoltage is set to 70% of VDD, see bits b6 and b5 in Table 15 on page 64. 37. Bit 2 is used in conjunction with bit 6. Both bit 6 and bit 2 must be set to 1 to activate the MCU INT request. 34903/4/5 Analog Integrated Circuit Device Data 76 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 37. LIN/1 Register(39) MOSI Second Byte, bits 7-0 MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 011P LIN mode[1] LIN mode[0] Slew rate[1] Slew rate[0] - LIN T/1 on - VSUP ext Default state 0 0 0 0 0 0 0 0 Condition for default POR Bits Description b7 b6 LIN mode [1], LIN mode [0] - LIN/1 interface mode control, Wake-up enable / disable 00 LIN/1 disable, Wake-up capability disable 01 not used 10 LIN/1 disable, Wake-up capability enable 11 LIN/1 Transmit Receive mode(38) b5 b4 Slew rate[1], Slew rate[0] LIN/1 slew rate selection 00 Slew rate for 20 kbit/s baud rate 01 Slew rate for 10 kbit/s baud rate 10 Slew rate for fast baud rate 11 Slew rate for fast baud rate b2 LIN T/1 on 0 LIN/1 termination OFF 1 LIN/1 termination ON b0 VSUP ext 0 LIN goes recessive when device VSUP/2 is below typically 6.0 V. This is to meet J2602 specification 1 LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled. Notes 38. The LIN interface can be set in TXD/RXD mode only when the TXD-L input signal is in recessive state. An attempt to set TXD/RXD mode, while TXD-L is low, will be ignored and the LIN interface remains disabled. 39. In order to use the LIN interface, the 5V-CAN regulator must be set to ON. 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 77

SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS FLAGS AND DEVICE STATUS DESCRIPTION • - [0 0] for I/O real time status, device identification and CAN LIN driver receiver real time state. The table below is a summary of the device flags, I/O real time level, device Identification, and includes examples of • bit 13 to 9 are the register address from which the flags is SPI commands (SPI commands do not use parity functions). to be read. They are obtained using the following commands. • bit 8 = 1 (this is not parity bit function, as this is a read command). This command is composed of the following: When a failure event occurs, the respective flag is set and bits 15 and 14: remains latched until it is cleared by a read command • [1 1] for failure flags (provided the failure event has recovered). Table 38. Device Flag, I/O Real Time and Device Identification Bits 15-14 13-9 8 7 6 5 4 3 2 1 0 MOSI bits 15-7 MOSI Next 7 MOSI bits (bits 6.0) should be “000_0000” bits [15, Address bit bit 8 14] [13-9] 7 MISO bits [7-0], device response on MISO pin 8 Bits Device Fixed Status MISO (bits 15...8) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 REG 11 0_1111 1 0 VAUX_LOW VAUX_overCUR 5V-CAN_ 5V-CAN_ 5V-CAN_ VSENSE_ VSUP_ IDD-OC- REG RENT THERMAL UV overCURRENT LOW underVOLTAGE NORMAL SHUTDOWN MODE 11 1 - - - VDD_ RST_LOW VSUP_ IDD-OC-LP THERMAL (<100 ms) BATFAIL VDDON SHUTDOWN MODE Hexa SPI commands to get Vreg Flags: MOSI 0x DF 00, and MOSI Ox DF 80 CAN 11 1_0000 1 0 CAN - CAN RXD low(40) Rxd high TXD dom Bus Dom CAN CAN Wake-up Overtemp clamp Overcurrent 1 CAN_UF CAN_F CANL CANL to VDD CANL to CANH to CANH to VDD CANH to to VBAT GND VBAT GND Hexa SPI commands to get CAN Flags: MOSI 0x E1 00, and MOSI 0x E1 80 00 1_0000 1 1 CAN Driver CAN Receiver CAN WU - - - - - CAN State State en/dis Hexa SPI commands to get CAN real time status: MOSI 0x 21 80 I/O 11 1_0001 1 0 HS3 short to HS2 short to SPI parity CSB low VSUP/2-UV VSUP/1-OV I/O_O thermal watchdog I/O GND GND error >2.0 ms flash mode 50% 1 I/O_1-3 I/O_0-2 SPI Wake-up FWU INT service LP VDD OFF Reset request Hardware Wake-up Wake-up Timeout Leave Debug Hexa SPI commands to get I/O Flags and I/O Wake-up: MOSI 0x E3 00, and MOSI 0x E3 80 00 1_0001 1 1 I/O_3 I/O_2 I/O_1 state I/O_0 state I/O state state Hexa SPI commands to get I/O real time level: MOSI 0x 23 80 SAFE 11 1_0010 1 0 INT request RST high DBG resistor VDD temp VDD UV VDD VAUX_overVOL - SAFE Pre-warning Overvoltage TAGE 1 - - - VDD low VDD low RST RST low multiple watchdog >100 ms >100 ms Resets refresh failure Hexa SPI commands to get INT and RST Flags: MOSI 0x E5 00, and MOSI 0x E5 80 00 1_0010 1 1 VDD (5.0 V or device device id4 id3 id2 id1 id0 SAFE 3.3 V) p/n 1 p/n 0 Hexa SPI commands to get device Identification: MOSI 0x 2580 example: MISO bit [7-0] = 1011 0100: MC34904, 5.0 V version, silicon Rev. C (Pass 3.3) 34903/4/5 Analog Integrated Circuit Device Data 78 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS Table 38. Device Flag, I/O Real Time and Device Identification (continued) LIN/1 11 1_0011 1 0 - LIN1 LIN1 Term LIN 1 RXD1 low RXD1 high TXD1 dom LIN1 bus LIN 1 Wake-up short to GND Overtemp dom clamp Hexa SPI commands to get LIN 2 Flags: MOSI 0x E7 00 00 1_0011 1 1 LIN1 State LIN1 WU - - - - - - LIN 1 en/dis Hexa SPI commands to get LIN1 real time status: MOSI 0x 27 80 Notes 40. Not available on “C” versions Table 39. Flag Descriptions Flag Description REG V Description Reports that V regulator output voltage is lower than the V _ threshold. AUX_LOW AUX AUX UV Set / Reset condition Set: V below threshold for t >100 μs typically. Reset: V above threshold and flag read (SPI) AUX AUX V Description Report that current out of V regulator is above V threshold. AUX_overCUR AUX AUX_OC RENT Set / Reset condition Set: Current above threshold for t >100 μs. Reset: Current below threshold and flag read by SPI. 5 V Description Report that the 5 V-CAN regulator has reached overtemperature threshold. -CAN_ THERMAL Set / Reset condition Set: 5 V-CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read SHUTDOWN (SPI) 5V Description Reports that 5 VCAN regulator output voltage is lower than the 5 V threshold. -CAN_UV - -CAN UV Set / Reset condition Set: 5V-CAN below 5V for t >100 μs typically. Reset: 5V-CAN > threshold and flag read (SPI) -CAN UV 5V-can_ Description Report that the CAN driver output current is above threshold. overcurrent Set / Reset condition Set: 5V-CAN current above threshold for t>100 μs. Reset: 5V-CAN current below threshold and flag read (SPI) V Description Reports that VSENSE pin is lower than the V threshold. SENSE_ SENSE LOW LOW Set / Reset condition Set: VSENSE below threshold for t >100 μs typically. Reset: VSENSE above threshold and flag read (SPI) V Description Reports that VSUP/1 pin is lower than the V threshold. SUP_ S1_LOW underVOLTAGE Set / Reset condition Set: VSUP/1 below threshold for t >100 μs typically. Reset: VSUP/1 above threshold and flag read (SPI) I Description Report that current out of VDD pin is higher that I threshold, while device is in Normal mode. DD-OC- DD-OC NORMAL MODE Set / Reset condition Set: current above threshold for t>100 μs typically. Reset; current below threshold and flag read (SPI) V Description Report that the V has reached overtemperature threshold, and was turned off. DD_ DD THERMAL Set / Reset condition Set: VDD OFF due to thermal condition. Reset: VDD recover and flag read (SPI) SHUTDOWN R Description Report that the RST pin has detected a low level, shorter than 100 ms ST_LOW (<100 ms) Set / Reset condition Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI) V Description Report that the device voltage at VSUP/1 pin was below BATFAIL threshold. SUP_ BATFAIL Set / Reset condition Set: VSUP/1 below BATFAIL. Reset: VSUP/1 above threshold, and flag read (SPI) I Description Report that current out of VDD pin is higher that I threshold LP, while device is in LP V ON DD-OC-LP DD-OC DD V ON mode mode. DD Set / Reset condition Set: current above threshold for t>100 μs typically. Reset; current below threshold and flag read (SPI) 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 79

SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS Table 39. Flag Descriptions Flag Description CAN CAN driver Description Report real time CAN bus driver state: 1 if Driver is enable, 0 if driver disable state Set / Reset condition Set: CAN driver is enable. Reset: CAN driver is disable. Driver can be disable by SPI command (ex CAN set in RXD only mode) or following a failure event (ex: TXD Dominant). Flag read SPI command (0x2180) do not clear the flag, as it is “real time” information. CAN receiver Description Report real time CAN bus receiver state: 1 if Enable, 0 if disable state Set / Reset condition Set: CAN bus receiver is enable. Reset: CAN bus receiver is disable. Receiver disable by SPI command (ex: CAN set in sleep mode). Flag read SPI command (0x2180) do not clear the flag, as it is “real time” information. CAN WU Description Report real time CAN bus Wake-up receiver state: 1 if WU receiver is enable, 0 if disable enable Set / Reset condition Set: CAN Wake-up receiver is enable. Reset: CAN Wake-up receiver is disable. Wake-up receiver is controlled by SPI, and is active by default after device Power ON. SPI command (0x2180) do not change flag state. CAN Description Report that Wake-up source is CAN Wake-up Set / Reset condition Set: after CAN wake detected. Reset: Flag read (SPI) CAN Description Report that the CAN interface has reach overtemperature threshold. Overtemp Set / Reset condition Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI) RXD low(41) Description Report that RXD pin is shorted to GND. Set / Reset condition Set: RXD low failure detected. Reset: failure recovered and flag read (SPI) Rxd high Description Report that RXD pin is shorted to recessive voltage. Set / Reset condition Set: RXD high failure detected. Reset: failure recovered and flag read (SPI) TXD dom Description Report that TXD pin is shorted to GND. Set / Reset condition Set: TXD low failure detected. Reset: failure recovered and flag read (SPI) Bus Dom Description Report that the CAN bus is dominant for a time longer than t DOM clamp Set / Reset condition Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI) CAN Description Report that the CAN current is above CAN overcurrent threshold. Overcurrent Set / Reset condition Set: CAN current above threshold. Reset: current below threshold and flag read (SPI) CAN_UF Description Report that the CAN failure detection has not yet identified the bus failure Set / Reset condition Set: bus failure pre detection. Reset: CAN bus failure recovered and flag read CAN_F Description Report that the CAN failure detection has identified the bus failure Set / Reset condition Set: bus failure complete detetction.Reset: CAN bus failure recovered and flag read CANL Description Report CAN L short to V failure BAT to VBAT Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) CANL to VDD Description Report CANL short to VDD Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) CANL to GND Description Report CAN L short to GND failure Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) CANH Description Report CAN H short to V failure BAT to VBAT Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) CANH to VDD Description Report CANH short to VDD Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) CANH to Description Report CAN H short to GND failure GND Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) Notes 41. Not available on “C” versions 34903/4/5 Analog Integrated Circuit Device Data 80 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS Table 39. Flag Descriptions Flag Description I/O HS3 short to Description Report I/O-3 HS switch short to GND failure GND Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) HS2 short to Description Report I/O-2 HS switch short to GND failure GND Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) SPI parity Description Report SPI parity error was detected. error Set / Reset condition Set: failure detected. Reset: flag read (SPI) CSB low Description Report SPI CSB was low for a time longer than typically 2.0 ms >2.0 ms Set / Reset condition Set: failure detected. Reset: flag read (SPI) VSUP/2-UV Description Report that VSUP/2 is below VS2_LOW threshold. Set / Reset condition Set VSUP/2 below VS2_LOW thresh. Reset VSUP/2 > VS2_LOW thresh and flag read (SPI) VSUP/1-OV Description Report that VSUP/1 is above VS_HIGH threshold. Set / Reset condition Set VSUP/1 above VS_HIGH threshold. Reset VSUP/1 < VS_HIGH thresh and flag read (SPI) I/O-0 thermal Description Report that the I/O-0 HS switch has reach overtemperature threshold. Set / Reset condition Set: I/O-0 HS switch thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI) watchdog Description Report that the watchdog period has reach 50% of its value, while device is in Flash mode. flash mode Set / Reset condition Set: watchdog period > 50%. Reset: flag read 50% I/O-1-3 Wake- Description Report that Wake-up source is I/O-1 or I/O-3 up Set / Reset condition Set: after I/O-1 or I/O-3 wake detected. Reset: Flag read (SPI) I/O-0-2 Wake- Description Report that Wake-up source is I/O-0 or I/O-2 up Set / Reset condition Set: after I/O-0 or I/O-2 wake detected. Reset: Flag read (SPI) SPI Wake-up Description Report that Wake-up source is SPI command, in LP V ON mode. DD Set / Reset condition Set: after SPI Wake-up detected. Reset: Flag read (SPI) FWU Description Report that Wake-up source is forced Wake-up Set / Reset condition Set: after Forced Wake-up detected. Reset: Flag read (SPI) INT service Description Report that INT timeout error detected. Timeout Set / Reset condition Set: INT service timeout expired. Reset: flag read. LP V OFF Description Report that LP V OFF mode was selected, prior Wake-up occurred. DD DD Set / Reset condition Set: LP V OFF selected. Reset: Flag read (SPI) DD Reset request Description Report that RST source is an request from a SPI command (go to RST mode). Set / Reset condition Set: After reset occurred due to SPI request. Reset: flag read (SPI) Hardware Description Report that the device left the Debug mode due to hardware cause (voltage at DBG pin lower than Leave Debug typically 8.0 V). Set / Reset condition Set: device leave debug mode due to hardware cause. Reset: flag read. 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 81

SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS Table 39. Flag Descriptions Flag Description INT INT request Description Report that INT source is an INT request from a SPI command. Set / Reset condition Set: INT occurred. Reset: flag read (SPI) RST high Description Report that RST pin is shorted to high voltage. Set / Reset condition Set: RST failure detection. Reset: flag read. DBG resistor Description Report that the resistor at DBG pin is different from expected (different from SPI register content). Set / Reset condition Set: failure detected. Reset: correct resistor and flag read (SPI). V Description Report that the V has reached overtemperature pre-warning threshold. DD TEMP PRE- DD WARNING Set / Reset condition Set: V thermal sensor above threshold. Reset: V thermal sensor below threshold and flag read DD DD (SPI) V Description Reports that VDD pin is lower than the V threshold. DD UV DDUV Set / Reset condition Set: VDD below threshold for t >100 μs typically. Reset: V above threshold and flag read (SPI) DD V Description Reports that VDD pin is higher than the typically V + 0.6 Vthreshold. I/O-1 can be turned OFF if DD DD this function is selected in INIT register. overVOLTAGE Set / Reset condition Set: VDD above threshold for t >100 μs typically. Reset: V below threshold and flag read (SPI) DD V Description Reports that VAUX pin is higher than the typically V + 0.6 Vthreshold. I/O-1 can be turned OFF if AUX_overVOL AUX this function is selected in INIT register. TAGE Set / Reset condition Set: V above threshold for t >100 μs typically. Reset: V below threshold and flag read (SPI) AUX AUX V Description Reports that VDD pin is lower than the VDD threshold for a time longer than 100 ms DD LOW UV >100 ms Set / Reset condition Set: VDD below threshold for t >100 ms typically. Reset: V above threshold and flag read (SPI) DD V Description Report that V is below V undervoltage threshold. DD LOW DD DD Set / Reset condition Set: V below threshold. Reset: fag read (SPI) DD V (5.0 V or Description 0: mean 3.3 V V version DD DD 3.3 V) 1: mean 5.0 V V D version D Set / Reset condition N/A Device P/N1 Description Describe the device part number: and 0 00: MC34903 01: MC34904 10: MC34905S 11: MC343905D Set / Reset condition N/A Device id 4 to Description Describe the silicon revision number 0 10010: silicon revision A (Pass 3.1) 10011: silicon revision B (Pass 3.2) 10100: silicon revision C (Pass 3.3) Set / Reset condition N/A RST low Description Report that the RST pin has detected a low level, longer than 100 ms (Reset permanent low) >100 ms Set / Reset condition Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI) Multiple Description Report that the more than 8 consecutive reset pulses occurred, due to missing or wrong watchdog Resets refresh. Set / Reset condition Set: after detection of multiple reset pulses. Reset: flag read (SPI) watchdog Description Report that a wrong or missing watchdog failure occurred. refresh failure Set / Reset condition Set: failure detected. reset: flag read (SPI) 34903/4/5 Analog Integrated Circuit Device Data 82 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS Table 39. Flag Descriptions Flag Description LIN/1/2 LIN/1 bus Description Report that the LIN/1 bus is dominant for a time longer than t DOM dom clamp Set / Reset condition Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI) LIN/1 State Description Report real time LIN interface TXD/RXD mode. 1 if LIN is in TXD/RXD mode. 0 is LIN is not in TXD/ RXD mode. Set / Reset condition Set: LIN in TXD RXD mode. Reset: LIN not in TXD/RXD mode. LIN not in TXD/RXD mode by SPI command (ex LIN set in Sleep mode) or following a failure event (ex: TxL Dominant). Flag read SPI command (0x2780) do not clear it, as it is “real time” flag. LIN/1 WU Description Report real time LIN Wake-up receiver state. 1 if LIN Wake-up is enable, 0 if LIN Wake-up is disable (means LIN signal will not be detected and will not Wake-up the device). Set / Reset condition Set: LIN WU enable (LIN interface set in Sleep mode Wake-up enable). Reset: LIN Wake-up disable (LIN interface set in Sleep mode Wake-up disable). Flag read SPI command (0x2780) do not clear the flag, as it is “real time” information. LIN/1 Description Report that Wake-up source is LIN/1 Wake-up Set / Reset condition Set: after LIN/1 wake detected. Reset: Flag read (SPI) LIN/1 Term Description Report LIN/1 short to GND failure short to GND Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) LIN/1 Description Report that the LIN/1 interface has reach overtemperature threshold. Overtemp Set / Reset condition Set: LIN/1 thermal sensor above threshold. Reset: sensor below threshold and flag read (SPI) RXD-L/1 low Description Report that RXD/1 pin is shorted to GND. Set / Reset condition Set: RXD low failure detected. Reset: failure recovered and flag read (SPI) RXD-L/1 high Description Report that RXD/1 pin is shorted to recessive voltage. Set / Reset condition Set: RXD high failure detected. Reset: failure recovered and flag read (SPI) TXD-L/1 dom Description Report that TXD/1 pin is shorted to GND. Set / Reset condition Set: TXD low failure detected. Reset: failure recovered and flag read (SPI) 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 83

SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS FIX AND EXTENDED DEVICE STATUS One Byte For every SPI command, the device response on MISO is Fix Status: when a device read operation is performed fixed status information. This information is either: (MOSI bits 15-14, bits C1 C0 = 00 or 11). Two Bytes Fix Status + Extended Status: when a device write command is used (MOSI bits 15-14, bits C1 C0 = 01) Table 40. Status Bits Description Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MISO INT WU RST CAN-G LIN-G I/O-G SAFE-G VREG-G CAN-BUS CAN-LOC 0 LIN1 I/O-1 I/O-0 VREG-1 VREG-0 Bits Description INT Indicates that an INT has occurred and that INT flags are pending to be read. WU Indicates that a Wake-up has occurred and that Wake-up flags are pending to be read. RST Indicates that a reset has occurred and that the flags that report the reset source are pending to be read. CAN-G The INT, WU, or RST source is CAN interface. CAN local or CAN bus source. LIN-G The INT, WU, or RST source is LIN1 interface I/O-G The INT, WU, or RST source is I/O interfaces. SAFE-G The INT, WU, or RST source is from a SAFE condition VREG-G The INT, WU, or RST source is from a Regulator event, or voltage monitoring event CAN-LOC The INT, WU, or RST source is CAN interface. CAN local source. CAN-BUS The INT, WU, or RST source is CAN interface. CAN bus source. LIN/LIN1 The INT, WU, or RST source is LIN1 interface I/O-0 The INT, WU, or RST source is I/O interface, flag from I/O sub adress Low (bit 7 = 0) I/O-1 The INT, WU, or RST source is I/O interface, flag from I/O sub adress High (bit 7 = 1) VREG-1 The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress high (bit 7 = 1) VREG-0 The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress low (bit 7 = 0) 34903/4/5 Analog Integrated Circuit Device Data 84 Freescale Semiconductor

TYPICAL APPLICATIONS FLAGS AND DEVICE STATUS TYPICAL APPLICATIONS Q2 5.0V (3.3V) RF module <10k >2.2μF Switch Detection Interface eSwitch V BAT Safing Micro Controller D1 VBAUXVCAUX VAUX Q1* CAN xcvr VE VSUP VSUP2 VB 22μF 100nF VSUP1 (42) VDD VDD DBG >4.7μF >1.0μF 1.0k 5V-CAN RST RST V BAT INT INT VSENSE 22k 100nF MUX A/D V SUP I/O-0 4.7k * 100nF MOSI MCU SCLK I/O-1 SPI MISO VSUP CS TXD I/O-3 CAN RXD C ANH TXD-L1 60 LIN1 RXD-L1 SPLIT 60 4.7nF CAN BUS CANL VSUP1/2 LIN TERM1 1.0k 1.0k LIN BUS 1 LIN1 option 1 option 2 GND SAFE VSUP VSUP Safe Circuitry Notes 42. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP1/VSUP2 pins Figure 38. 34905S Typical Application Schematic 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 85

TYPICAL APPLICATIONS FLAGS AND DEVICE STATUS * Optional Q2 5V (3.3V) RF module <10k >2.2μF Switch Detection Interface VBAT eSwitch Q1* Safing Micro Controller D1 VBAUXVCAUX VAUX VE CAN xcvr V SUP VSUP2 VB 22μF 100nF VSUP1 (43) VDD VDD DBG >4.7μF >1.0μF 1.0 k 5V-CAN RST RST V BAT INT INT VSENSE MUX A/D 100nF V 22k I/O-0 MOSI 4.7k * MCU SUP 100nF SCLK SPI MISO I/O-1 V CS BAT 22k TXD CAN VSUP I/O-2 RXD 100nF I/O-3 C ANH N/C 60 SPLIT 4.7nF 60 CANL CAN BUS GND SAFE V V SUP SUP OR function Safe Circuitry Notes 43. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP1/VSUP2 pins Figure 39. 34904 Typical Application Schematic 34903/4/5 Analog Integrated Circuit Device Data 86 Freescale Semiconductor

TYPICAL APPLICATIONS FLAGS AND DEVICE STATUS V BAT Q1* * = Optional D1 V SUP VSUP VE VB 22μF 100nF DBG VDD VDD >1.0μF >4.7μF 1.0k 5V-CAN VBAT RST RST VSENSE INT INT 22k 100nF MUX A/D VSUP 100nF IO-0 MOSI 4.7k (optional) SCLK IO-3 SPI MCU MISO CS C ANH TXD CAN 60 RXD SPLIT TXD-L 60 4.7nF LIN CAN BUS RXD-L CANL VSUP LIN-T 1.0k 1.0k N/C LIN BUS LIN option1 option2 GND SAFE VSUP VSUP Safe Circuitry Notes 44. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP pin 45. Leave N/C pins open. Figure 40. 34903S Typical Application Schematic 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 87

TYPICAL APPLICATIONS FLAGS AND DEVICE STATUS V BAT Q1* * = Optional D1 V SUP VSUP VE VB 22μF 100nF DBG VDD VDD >1.0μF >4.7μF 1.0k 5V-CAN VBAT RST RST VSENSE INT INT 22k 100nF MUX A/D IO-0 4.7k (optional) 100nF MOSI V SCLK BAT SPI MCU MISO 22k CS I/O-2 VSUP 100nF TXD CAN RXD IO-3 C ANH 60 SPLIT 60 4.7nF N/C CAN BUS CANL GND SAFE VSUP VSUP Safe Circuitry Notes 46. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP pin 47. Leave N/C pins open. Figure 41. 34903P Typical Application Schematic 34903/4/5 Analog Integrated Circuit Device Data 88 Freescale Semiconductor

TYPICAL APPLICATIONS FLAGS AND DEVICE STATUS The following figure illustrates the application case during the cranking pulse and temporary (50 ms) loss of the where two reverse battery diodes can be used for V supply. BAT optimization of the filtering and buffering capacitor at the Applications without an external ballast on V and DD VDD pin. This allows using a minimum value capacitor at without using the VAUX regulator are illustrated as well. the VDD pin to guarantee reset-free operation of the MCU Q2 Q2 V 5.0V/3.3V BAT 5.0V/3.3V V D2 BAT D1 VBAUXVCAUX VAUX C2 VBAUXVCAUX VAUX Q1 Q1 VSUP2 VE D1 VSUP2 VE VSUP1 VB VSUP1 VB C1 VDD VDD Partial View Partial View ex2: Split V Supply SUP ex1: Single V Supply SUP Optimized solution for cranking pulses. C1 is sized for MCU power supply buffer only. Q2 5.0V/3.3V VBAT VBAT D1 VBAUXVCAUX VAUX D1 VBAUX VCAUXVAUX VSUP2 VE VSUP2 VE VSUP1 VSUP1 VB VB VDD VDD Partial View Partial View ex 3: No External Transistor, V ~100mA Capability ex 4: No External Transistor - No VAUX DD delivered by internal path transistor. Figure 42. Application Options 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 89

PACKAGING SOIC 32 PACKAGE DIMENSIONS PACKAGING SOIC 32 PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D 34903/4/5 Analog Integrated Circuit Device Data 90 Freescale Semiconductor

PACKAGING SOIC 32 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 91

PACKAGING SOIC 32 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D 34903/4/5 Analog Integrated Circuit Device Data 92 Freescale Semiconductor

REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 1.0 7/2013 • Initial Release based on the the MC33903_4_5 data sheet 2.0 8/2013 • Update TA for industrial market applications. • Corrected document title 3.0 9/2013 • Added Applications to page one • Corrected blank fields. 4.0 10/2013 • Upgraded temperature to 125 °C to support additional industrial applications. 34903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 93

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