Freescale Semiconductor Document Number: MC34704 Technical Data Rev. 8.0, 12/2014 Multiple Channel DC-DC Power Management IC 34704 The 34704 is a multi-channel Power Management IC (PMIC) used to address power management needs for various multimedia application microprocessors. Its ability to provide either 5 or 8 MULTI-CHANNEL IC independent output voltages with a single input power supply (2.7 and 5.5 V) together with its high efficiency, make it ideal for portable devices powered up by Li-Ion/polymer batteries or for USB powered devices as well. This device is powered by SMARTMOS technology. The 34704 is housed in a 7x7 mm, Pb-free, QFN56 and is capable of operating at a switching frequency of up to 2.0 MHz. This makes it possible to reduce external component size and to implement full space efficient power management solutions. EP SUFFIX (PB-FREE) Features 98ASA00712D • 8 DC/DC (34704A) or 5 DC/DC (34704B) switching regulators with 56-PIN QFN up to 2% output voltage accuracy • Dynamic voltage scaling on all regulators. ORDERING INFORMATION • Selectable output voltage or current regulation on REG8 • I2C programmability Device Temperature Package Range (T ) A • Output undervoltage and overvoltage detection for each regulator • Overcurrent limit detection and short-circuit protection for each MC34704AEP/R2 -20 °C to 85 °C 56 QFN EP regulator MC34704BEP/R2 • Thermal limit detection for each regulator, except REG7 • Integrated compensation for REG1, REG3, REG6, and REG8 • 5.0 µA maximum shutdown current (All regulators are off, 5.5 V VIN) • True cutoff on all of the boost and buck-boost regulators 34704A/B V BKL REG 8 V DDR REG 4 DDR I2C COMM MEMORY GND V CORE REG 3 V IO1 REG 2 MPU LCD V IO2 GND REG 5 PGND *REG 1 +5V *REG 6 VREF+ (5 to 16V) *REG 7 VREF- (-5 to -9V) * Available only in 34704A device Figure 1. 34704 Simplified Application Diagram © Freescale Semiconductor, Inc., 2008 - 2014. All rights reserved.

DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Variations Orderable Part Number No. of Regulators Regulator Number MC34704AEP/R2 8 Reg 1 - 8 MC34704BEP/R2 5 Reg 2, 3, 4, 5, 8 34704 Analog Integrated Circuit Device Data 2 Freescale Semiconductor

INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM REG8 voltage data voltage data REG1/VG Control Control OUT8 VOUT1 (34704A) L Error Amp VG Error Amp SBWT88 VG BoPreDrv PWM SIpteaartk--Udpet PPW-skMip ootPreDrv VG BSTW11 ot Error Amp aSnWd cbolanntrkoinlg B FB8 VG OUT7 REG7 (34704A) voltage data REvGolt2age data Boot BPTV2IND2 Control Control Drv SW2D e P Error Amp Pr DRV7 reD PWM VOUT2 rv Error Amp FB7 Amp PPW-skMip PreDrv SW2U VG VREF7 oot BT2U COMP7 B COMP2 FB2 REG6 (34704A) voltage data REG3 Control VG VOUT6 voltage data oot BT3 Control B PVIN3 L Error Amp SW3 Drv SW6 P e reD PWM Pr VG rv B Error Amp BT6 oo VOUT3 t Error Amp PWM FB3 P-skip FB6 REG4 VG ot BT4D VG REG5 voltage data Bo PVIN4 PBVTI5ND5 PBoot voltage data Control PreDrv SW4D SW5D reD Control rv VOUT4 Error Amp VSOWU5TU5 VG PreDrv PP-WskMip Error Amp PPW-skMip BootPreDrv VG SBWT44UU B FB4 BT5U oo COMP4 t COMP5 VIN FB5 VG UVLO Startup Control ONOFF VDDI VDDI (2.5V) VDDIMON (VDDIdet) Detection LION SSDCAL I2C Registers Thermal ADC mux FSRSEQ To Reg 1-8 Detection RST Reset Driver Sequencer OSC/Divider PGND (EXPAD) VIN AGND Soft Start Figure 2. 34704 Internal Block Diagram 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 3

PIN CONNECTIONS PIN CONNECTIONS OMP5 B5 T5D VIN5 W5D OUT5 W5U W2U OUT2 W2D VIN2 T2D B2 OMP2 OMP5 B5 T5D VIN5 W5D OUT5 W5U W2U OUT2 W2D VIN2 T2D B2 OMP2 C F B P S V S S V S P B F C C F B P S V S S V S P B F C 56 55 54 53 52 51 50 4948 47 46 45 44 43 565554 53 52 51 50 49 48 47 464544 43 BT5U 1 42 BT2U BT5U 1 42 BT2U BT4D 2 41 ONOFF BT4D 2 41 ONOFF PVIN4 3 57 40 LION PVIN4 3 57 40 LION SW4D 4 39 VDDI SW4D 4 39 VDDI VOUT4 5 38 VIN VOUT4 5 38 VIN SW4U 6 37 AGND SW4U 6 37 AGND Exposed Pad Exposed Pad BT4U 7 PGND 36 VOUT6 BT4U 7 PGND 36 PGND5 FB4 8 35 SW6 FB4 8 35 PGND4 COMP4 9 34 BT6 COMP4 9 34 NC4 BT3 10 33 FB6 BT3 10 33 AGND3 PVIN3 11 32 VOUT7 PVIN3 11 32 PGND2 SW3 12 31 DRV7 SW3 12 31 NC3 VOUT3 13 30 FB7 VOUT3 13 30 AGND1 FB3 14 29 VREF7 FB3 14 29 NC2 15 16 17 18 19 2021 22 23 24 25 26 27 28 15 16 17 18 19 20 21 22 232425 26 27 28 S Q 8 8 8 8 1 G 1 1 L A T 7 S Q 8 8 8 8 1 G 0 1 L A T 1 S FRE FB BT VOUT SW SW V VOUT BT SC SD RS COMP S FRE FB BT VOUT SW SW V NC BT SC SD RS NC 34704A 34704B Figure 3. 34704 Pin Connections Table 2. 34704 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number Device Pin Name Pin Function Formal Name Definition 1 A/B BT5U Passive REG5 Boost Stage Connect a 1.0 F capacitor between this pin and SW5U pin to bootstrap capacitor input enhance the gate of the Switch Power MOSFET. pin 2 A/B BT4D Passive REG4 Buck Stage Connect a 0.01 F capacitor between this pin and SW4D pin to bootstrap capacitor input enhance the gate of the Switch Power MOSFET. pin 3 A/B PVIN4 Power REG4 power supply input This is the connection to the drain of the high-side switch FET. voltage Input decoupling /filtering is required for proper REG4 operation. Use a 10uf decoupling capacitor for better performance. 4 A/B SW4D Input/Output REG4 Buck Stage The inductor is connected between this pin and the SW4U pin. switching node 5 A/B VOUT4 Output REG4 regulated output Connect this pin to the load and to the output filter as close to voltage pin the pin as possible. 6 A/B SW4U Input/Output REG4 Boost Stage The inductor is connected between this pin and the SW4D pin. switching node 7 A/B BT4U Passive REG4 Boost Stage Connect a 0.01 F capacitor between this pin and SW4U pin to bootstrap capacitor input enhance the gate of the Switch Power MOSFET. pin 8 A/B FB4 Input REG4 voltage feedback Connect the feedback resistor divider to this pin. input for voltage regulation/programming 9 A/B COMP4 Passive REG4 compensation REG4 compensation network connection. network connection 10 A/B BT3 Passive REG3 bootstrap capacitor Connect a 0.01 F capacitor between this pin and SW3 pin to input pin enhance the gate of the Switch Power MOSFET. 34704 Analog Integrated Circuit Device Data 4 Freescale Semiconductor

PIN CONNECTIONS Table 2. 34704 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number Device Pin Name Pin Function Formal Name Definition 11 A/B PVIN3 Power REG3 power supply input This is the connection to the drain of the high-side switch FET. voltage Input decoupling /filtering is required for proper REG3 operation. Use a 10uf decoupling capacitor for better performance. 12 A/B SW3 Output REG3 switching node The inductor is connected between this pin and the regulated REG3 output. 13 A/B VOUT3 Output REG3 output voltage This is the discharge path of REG3 output voltage. return pin 14 A/B FB3 Input REG3 voltage feedback Connect the feedback resistor divider to this pin. input for voltage regulation/programming 15 A/B SS Input Soft start time The soft start time for all regulators can be adjusted by connecting this pin to an external resistor divider between VDDI and AGND pins. 16 A/B FREQ Input Oscillator frequency The oscillator frequency can be adjusted by connecting this pin to an external resistor divider between VDDI and AGND pins. This pin sets F value. SW1 17 A/B FB8 Input REG8 voltage feedback Connect the feedback resistor divider to this pin. input for voltage regulation/programming 18 A/B BT8 Passive REG8 bootstrap capacitor Connect a 0.01 F capacitor between this pin and SW8 pin to input pin enhance the gate of the Synchronous Power MOSFET. 19 A/B VOUT8 Output REG8 regulated output Connect this pin directly to the load directly and to the output voltage pin filter as close to the pin as possible. 20 A/B SW8 Output REG8 switching node The inductor is connected between this pin and the VIN pin. 21 A/B SW1 Output REG1 switching node The inductor is connected between this pin and the VIN Pin. 22 A/B VG Passive REG1 regulated output REG1 regulated output voltage before the cut-off switch. This voltage before the cutoff supplies the internal circuits and the gate drive switch 23(1) A VOUT1 Output REG1 regulated output Connect this pin directly to the load directly and to the output voltage pin. filter as close to the pin as possible. B NC0 No Connect - Pin 23 is not connected. 24 A/B BT1 Passive REG1 bootstrap capacitor Connect a 1.0 F capacitor between this pin and SW1 pin to input pin enhance the gate of the Switch Power MOSFET. 25 A/B SCL Input/Output I2C serial interface clock I2C serial interface clock input. input 26 A/B SDA Input/Output I2C serial interface data I2C serial interface data input. input 27 A/B RST Open Drain Power reset output signal This is an open drain output and must be pulled up by an (Microprocessor Reset) external resistor to a supply voltage like V . IN 28 A COMP7 Passive REG7 compensation REG7 compensation network connection. network connection B NC1 No Connect - Pin 28 is not connected 29 A VREF7 Output REG7 resistor feedback Connect this pin to the bottom of the feedback resistor divider. network reference voltage B NC2 No Connect - Pin 29 is not connected 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 5

PIN CONNECTIONS Table 2. 34704 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number Device Pin Name Pin Function Formal Name Definition 30 A FB7 Input REG7 voltage feedback Connect the feedback resistor divider to this pin. input for voltage regulation/programming B AGND1 - - Pin 30 is connected to AGND 31 A DRV7 Output REG7 external Power REG7 external Power MOSFET gate drive. MOSFET gate drive B NC3 No Connect - Pin 31 is not connected 32 A VOUT7 Output REG7 output voltage This is the discharge path of REG7 output voltage. return pin. B PGND1 - - Pin 32 is connected to PGND 33 A FB6 Input REG6 voltage feedback Connect the feedback resistor divider to this pin. input for voltage regulation/programming B AGND2 - - Pin 33 is connected to AGND 34 A BT6 Passive REG6 bootstrap capacitor Connect a 0.01 F capacitor between this pin and SW6 pin to input pin. enhance the gate of the Synchronous Power MOSFET. B NC4 No Connect - Pin 34 is not connected 35 A SW6 Output REG6 switching node The inductor is connected between this pin and the VIN pin. B PGND2 - - Pin 35 is connected to PGND 36 A VOUT6 Output REG6 regulated output Connect this pin directly to the load directly and to the output voltage pin filter as close to the pin as possible. B PGND3 - - Pin 36 is connected to PGND 37 A/B AGND Ground Analog ground of the IC Analog ground of the IC. 38 A/B VIN Power Battery voltage Input decoupling /filtering is required for the device to operate connection properly. 39 A/B VDDI Output Internal supply voltage Connect a 1.0 F low ESR decoupling filter capacitor between this pin and GND. 40 A/B LION Input Battery Detection Always pull this pin High with a 470kohm Resistor to indicate Input power is present. 41 A/B ONOFF Input Dual function IC turn On/ This is a hardware enable/disable for the 34704A/B. It can be Off connected to a mechanical switch to turn the power On or Off. 42 A/B BT2U Passive REG2 Boost Stage Connect a 1.0 F capacitor between this pin and SW2U pin to bootstrap capacitor input enhance the gate of the Switch Power MOSFET. pin 43 A/B COMP2 Passive REG2 compensation REG2 compensation network connection. network connection 44 A/B FB2 Input REG2 voltage feedback Connect the feedback resistor divider to this pin. input for voltage regulation/programming 45 A/B BT2D Passive REG2 Buck Stage Connect a 1.0 F capacitor between this pin and SW2D pin to bootstrap capacitor input enhance the gate of the Switch Power MOSFET. pin 46 A/B PVIN2 Power REG2 power supply input This is the connection to the drain of the high-side switch FET. voltage Input decoupling /filtering is required for proper REG2 operation. Use a 10uf decoupling capacitor for better performance 34704 Analog Integrated Circuit Device Data 6 Freescale Semiconductor

PIN CONNECTIONS Table 2. 34704 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number Device Pin Name Pin Function Formal Name Definition 47 A/B SW2D Input/Output REG2 Buck Stage The inductor is connected between this pin and the SW2U pin. switching node 48 A/B VOUT2 Output REG2 regulated output Connect this pin to the load and to the output filter as close to voltage pin the pin as possible. 49 A/B SW2U Input/Output REG2 Boost Stage The inductor is connected between this pin and the SW2D pin. switching node 50 A/B SW5U Input/Output REG5 Boost Stage The inductor is connected between this pin and the SW5D pin. switching node 51 A/B VOUT5 Output REG5 regulated output Connect this pin to the load and to the output filter as close to voltage pin the pin as possible. 52 A/B SW5D Input/Output REG5 Buck Stage The inductor is connected between this pin and the SW5U pin. switching node 53 A/B PVIN5 Power REG5 power supply input This is the connection to the drain of the high-side switch FET. voltage Input decoupling /filtering is required for proper REG5 operation. Use a 10uf decoupling capacitor for better performance 54 A/B BT5D Passive REG5 Buck Stage Connect a 1.0 F capacitor between this pin and SW5D pin to bootstrap capacitor input enhance the gate of the Switch Power MOSFET. pin 55 A/B FB5 Input REG5 voltage feedback Connect the feedback resistor divider to this pin. input for voltage regulation/programming 56 A/B COMP5 Passive REG5 compensation REG5 compensation network connection. network connection Exposed A/B PGND Ground Power Ground Power Ground Connection for all of the regulators except Pad Connection for all of the REG7. This pad is provided to enhance thermal performance. regulators except REG7 Notes 1. If regulator 1 is not used, leave pin 23 Unconnected, All other components should be used to provide VG to the system 2. If regulators 5, 6, 7 and 8 are not used, connect the corresponding pins as follows: FB, SW and VOUT nodes: tied to GND; BT, COMP and PVIN pins: Not connected; DRV and VREF nodes (REG7 only): Not connected 3. REG 2,3 and 4 should always be populated. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 7

ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ELECTRICAL RATINGS Battery Input Supply Voltage (VIN) Pin V -0.3 to 6.0 V IN PVINx, RST, ONOFF, LION, DRV7(8), VG, SCL, SDA and VOUT1-5 Pins -0.3 to 6.0 VDDI, COMPx, FBx, VREF7(8), FREQ, and SS Pins -0.3 to 3.0 SW1-5 Pins V -1.0 to 6.0 V SW-LOW SW8, SW6(8) Pins V -1.0 to 27 V SW-HIGH BTx Pins (Referenced to switch node) V -V -0.3 to 6.0 V BT SW BTx Pins to GND V -0.3 to 27 V BT VOUT8, VOUT6(8) Pins V -0.3 to 27 V OUT-HIGH VOUT7 Pin(8) V -10.0 to 0.3 V OUT-NEG Continuous Output Current mA REG1(8) 500 REG2,5 500 REG3 550 REG4 300 REG6,7(8) 60 REG8 30 ESD Voltage V Human Body Model V ±1000 ESD1 Charge Device Model V ±500 ESD2 THERMAL RATINGS Maximum Junction Temperature T +150 °C J(MAX) Storage Temperature T -65 to +150 °C STG Maximum Power Dissipation (TA = 85°C) PD 2.5 W THERMAL RESISTANCE(7) Thermal Resistance °C/W Junction to Ambient R 26 ΘJA Junction to Board R 10 ΘJB Peak Package Reflow Temperature During Reflow(5),(6) T Note 6 °C PPRT Notes 4. ESD testing is performed in accordance with the Human Body Model (HBM) (C = 100 pF, R = 1500 ), and the Charge Device ZAP ZAP Model (CDM), Robotic (C = 4.0 pF). ZAP 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 7. Thermal Resistance is based on a four-layer board (2s2p) 8. Available only on the 34704A 34704 Analog Integrated Circuit Device Data 8 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 2.7 V  VIN  5.5 V, - 20C  TA  85 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit POWER INPUT Input Supply Voltage Typical Range V 2.7 - 5.5 V IN Input DC Supply Current(9) I mA IN VIN Pin Only - - - All regulators are ON, no load; VIN = 3.6 V, FSW =1.0 MHz - 86 - - - Regulators 1 - 5 On, Reg 6, 7 and 8 Off; V = 3.6 V, FSW = 1.0 MHz 32 IN Input DC Shutdown Supply Current(9) I A OFF (Shutdown, All regulators are OFF and VIN = 5.5V) - - 5.0 This includes any pin connected to the battery Rising UVLO Threshold UVLO - - 3.0 V R Falling UVLO Threshold UVLO - - 2.7 V F RST RST Low Level Output Voltage V V RST-OL IOL = 1.0 mA - - 0.4 RST Leakage Current, Off-state @ 25°C I - - 1.0 A RST-LKG Current Limit Monitoring Over and Short-circuit Current Limit Accuracy - -20 - 20 % REGULATOR 1 & VG VG Output Voltage V - 5.0 - V VG REG1 Output Voltage(10) V - 5.0 - V OUT Output Accuracy - -4.0 - 4.0 % Line/Load Regulation(9) REG -1.0 - 1.0 % LN/LD Dynamic Voltage Scaling Range V -10 - 10 % DYN Dynamic Voltage Scaling Step Size V - 2.5 - % DYN_STEP Continuous Output Current(9) I - 100 500 mA OUT Overcurrent Limit (Detected in Low-side FET) I - 2.7 - A LIM_ION Short-circuit Current Limit (Detected in the Blocking FET) I - 4.0 - A SHORT_ION Overcurrent Limit Accuracy - -20 - 20 % N-CH Switch Power MOSFET RDS(on) RDS(on)-SW - 100 - m N-CH Synch. Power MOSFET RDS(on) RDS(on)-SY - 150 - m N-CH Shutdown Power MOSFET RDS(on) RDS(on)-SH - 100 - m Discharge MOSFET RDS(ON) RDS(on)-DIS - 70 -  Thermal Shutdown Threshold(9) T - 170 - °C SD Thermal Shutdown Hysteresis(9) T - 25 - °C SD-HYS SW1 Leakage Current (Off State) @ 25°C I - - 1.0 A SW1_LKG Peak Current Detection Threshold at Power Up(9) I - 300 - mA PEAK Notes: 9. Guaranteed by Design 10. Available only on the 34704A 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 9

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 2.7 V  VIN  5.5 V, - 20C  TA  85 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit REGULATOR 2 Output Voltage Range V 0.6 3.3 3.6 V OUT Output Accuracy - -2.0 - 2.0 % Line/Load Regulation(11) REG -1.0 - 1.0 % LN/LD Feedback Reference Voltage V - 0.600(12) - V FB Dynamic Voltage Scaling Range V -17.5 - 17.5 % DYN Dynamic Voltage Scaling Step Size V - 2.5 - % DYN_STEP Continuous Output Current(11) I - 200 500 mA OUT Overcurrent Limit (Detected in buck high-side FET) I - 1.4 - A LIM_ION Short-circuit Current Limit (Detected in buck high-side FET) I - 2.1 - A SHORT_ION Battery Overcurrent Limit Accuracy - -20 - 20 % N-CH Buck Switch Power MOSFET RDS(on) RDS(on)-SW - 120 - m N-CH Buck Synch. Power MOSFET RDS(on) RDS(on)-SY - 1000 - m N-CH Boost Switch Power MOSFET RDS(on) RDS(on)-SW - 120 - m N-CH Boost Synch. Power MOSFET RDS(on) RDS(on)-SY - 120 - m Discharge MOSFET RDS(ON) RDS(on)-DIS - 70 -  Thermal Shutdown Threshold(11) T - 170 - °C SD Thermal Shutdown Hysteresis(11) T - 25 - °C SD-HYS PVIN2 Leakage Current (Off State) @25°C I - - 1.0 A PVIN2G_LKG SW2D Leakage Current (Off State) @25°C I - - 1.0 A SW2D_LKG SW2U Leakage Current (Off State) @25°C I - - 1.0 A SW2U_LKG REGULATOR 3 Output Voltage Range V 0.6 1.2 1.8 V OUT Output Accuracy - -4.0 - 4.0 % Line/Load Regulation(11) REG -1.0 - 1.0 % LN/LD Feedback Reference Voltage V - 0.600(12) - V FB Dynamic Voltage Scaling Range V -17.5 - 17.5 % DYN Dynamic Voltage Scaling Step Size V - 2.5 - % DYN_STEP Continuous Output Current(11) I - 150 550 mA OUT Overcurrent Limit (Detected in buck high-side FET) I - 1.0 - A LIM_ION Short-circuit Current Limit (Detected in buck high-side FET) I - 1.5 - A SHORT_ION Overcurrent Limit Accuracy - -20 - 20 % N-CH Switch Power MOSFET RDS(on) RDS(on)-SW - 500 - m N-CH Synch. Power MOSFET RDS(on) RDS(on)-SY - 500 - m Discharge MOSFET RDS(ON) RDS(on)-DIS - 70 -  Thermal Shutdown Threshold (11) T - 170 - °C SD Thermal Shutdown Hysteresis(11) T - 25 - °C SD-HYS PVIN3 Leakage Current (Off State) @25°C I - - 1.0 A PVIN3_LKG SW3 Leakage Current (Off State) @25°C I - - 1.0 A SW3_LKG Notes: 11. Guaranteed by Design 12. V is 0.6V when the part is powered up and no DVS is changed. DVS is achieved by modifying V reference. FB FB 34704 Analog Integrated Circuit Device Data 10 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 2.7 V  VIN  5.5 V, - 20C  TA  85 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit REGULATOR 4 Output Voltage Range V 0.6 1.8 3.6 V OUT Output Accuracy - -2.0 - 2.0 % Line/Load Regulation(13) REG -1.0 - 1.0 % LN/LD Feedback Reference Voltage V - 0.600(14) - V FB Dynamic Voltage Scaling Range V -10 - 10 % DYN Dynamic Voltage Scaling Step Size V - 1.0 - % DYN_STEP Continuous Output Current(13) I - 100 300 mA OUT Overcurrent Limit (Detected in buck high-side FET) I - 1.5 - A LIM_ION Short-circuit Current Limit (Detected in buck high-side FET) I - 2.25 - A SHORT_ION Overcurrent Limit Accuracy - -20 - 20 % N-CH Buck Switch Power MOSFET RDS(on) RDS(on)-SW - 200 - m N-CH Buck Synch. Power MOSFET RDS(on) RDS(on)-SY - 600 - m N-CH Boost Switch Power MOSFET RDS(on) RDS(on)-SW - 200 - m N-CH Boost Synch. Power MOSFET RDS(on) RDS(on)-SY - 600 - m Discharge MOSFET RDS(ON) RDS(on)-DIS - 70 -  Thermal Shutdown Threshold(13) T - 170 - °C SD Thermal Shutdown Hysteresis(13) T - 25 - °C SD-HYS PVIN4 Leakage Current (Off State) @25°C I - - 1.0 A PVIN4_LKG SW4D Leakage Current (Off State) @25°C I - - 1.0 A SW4D_LKG SW4U Leakage Current (Off State) @25°C I - - 1.0 A SW4U_LKG REGULATOR 5 Output Voltage Range V 0.6 3.3 3.6 V OUT Output Accuracy - -2.0 - 2.0 % Line/Load Regulation(13) REG -1.0 - 1.0 % LN/LD Feedback Reference Voltage V - 0.600(14) - V FB Dynamic Voltage Scaling Range V -17.5 - 17.5 % DYN Dynamic Voltage Scaling Step Size V - 2.5 - % DYN_STEP Continuous Output Current(13) I - 150 500 mA OUT Overcurrent Limit (Detected in buck high-side FET) I - 1.4 - A LIM_ION Short-circuit Current Limit (Detected in buck high-side FET) I - 2.1 - A SHORT_ION Overcurrent Limit Accuracy - -20 - 20 % N-CH Buck Switch Power MOSFET RDS(on) RDS(on)-SW - 120 - m N-CH Buck Synch. Power MOSFET RDS(on) RDS(on)-SY - 1000 - m N-CH Boost Switch Power MOSFET RDS(on) RDS(on)-SW - 120 - m N-CH Boost Synch. Power MOSFET RDS(on) RDS(on)-SY - 120 - m Discharge MOSFET RDS(on) RDS(on)-DIS - 70 -  Thermal Shutdown Threshold(13) T - 170 - °C SD Thermal Shutdown Hysteresis(13) T - 25 - °C SD-HYS Notes: 13. Guaranteed by Design 14. V is 0.6V when the part is powered up and no DVS is changed. DVS is achieved by modifying V reference. FB FB 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 11

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 2.7 V  VIN  5.5 V, - 20C  TA  85 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit PVIN5 Leakage Current (Off State) @25°C I - - 1.0 A PVIN5_LKG SW5D Leakage Current (Off State) @25°C I - - 1.0 A SW5D_LKG SW5U Leakage Current (Off State) @25°C I - - 1.0 A SW5U_LKG REGULATOR 6(16) Output Voltage Range V 5.0 15 15 V OUT Output Accuracy - -4.0 - 4.0 % Line/Load Regulation(15) REG -1.0 - 1.0 % LN/LD Feedback Reference Voltage V - 0.600(17) - V FB Dynamic Voltage Scaling Range V -10 - 10 % DYN Dynamic Voltage Scaling Step Size V - 2.5 - % DYN_STEP Continuous Output Current(15) I - 50 60 mA OUT Overcurrent Limit (Detected in low-side FET) I - 3.0 - A LIM_ION Short-circuit Current Limit (Detected in the Blocking FET) I - 4.5 - A SHORT_ION Overcurrent Limit Accuracy - -20 - 20 % N-CH Switch Power MOSFET RDS(on) RDS(on)-SW - 200 - m N-CH Synch. Power MOSFET RDS(on) RDS(on)-SY - 600 - m N-CH Shutdown Power MOSFET RDS(on) RDS(on)-SH - 200 - m Discharge MOSFET RDS(ON) RDS(on)-DIS - 70 -  Thermal Shutdown Threshold(15) T - 170 - °C SD Thermal Shutdown Hysteresis(15) T - 25 - °C SD-HYS SW6 Leakage Current (Off State) @25°C I - - 1.0 A SW6_LKG REGULATOR 7(16) Output Voltage Range V -5.0 -7.0 -9.0 V OUT Output Accuracy - -2.0 - 2.0 % Line/Load Regulation(15) REG -1.0 - 1.0 % LN/LD Feedback Reference Voltage V - 0.600(17) - V FB Continuous Output Current(15) I - 50 60 mA OUT Discharge MOSFET RDS(on) RDS(on)-DIS - 55 -  Gate Drive Voltage High Level (@ -50 mA, VIN=3.6V) VIN-VOH - 0.8 1.4 V Gate Drive Voltage Low Level (@ 50 mA, VIN=3.6V) VOL - 1.1 1.8 V VREF7 Output Voltage V - 1.5 - V REF7 VREF7 Voltage Accuracy - 1.43 - 1.57 V VREF7 Output Load Regulation (10 A to 1.0 mA) REG 1.43 - 1.57 V LD Notes 15. Guaranteed by Design 16. Available only on the 34704A 17. V is 0.6V when the part is powered up and no DVS is changed. DVS is achieved by modifying V reference. FB FB 34704 Analog Integrated Circuit Device Data 12 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 2.7 V  VIN  5.5 V, - 20C  TA  85 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit REGULATOR 8 Output Voltage Range V 5.0(19) 15 15 V OUT Output Accuracy - -4.0 - 4.0 % Feedback Reference Voltage V - 0.600(20) - V FB Feedback Reference Voltage on current regulation mode V - 0.230(21) - V FB Dynamic Voltage Scaling Range V -10 - 10 % DYN Dynamic Voltage Scaling Step Size V - 2.5 - % DYN_STEP Line/Load Regulation(18) REG -1.0 - 1.0 % LN/LD Continuous Output Current(18) I - 15 30 mA OUT Overcurrent Limit (Detected in low-side FET) I - 1.0 - A LIM_ION Short-circuit Current Limit (Detected in the Blocking FET) I - 1.5 - A SHORT_ION Overcurrent Limit Accuracy - -20 - 20 % N-CH Switch Power MOSFET RDS(on) RDS(on)-SW - 450 - m N-CH Synch. Power MOSFET RDS(on) RDS(on)-SY - 1000 - m N-CH Shutdown Power MOSFET RDS(on) RDS(on)-SH - 450 - m Discharge MOSFET RDS(ON) RDS(on)-DIS - 70 -  Thermal Shutdown Threshold(18) T - 170 - °C SD Thermal Shutdown Hysteresis(18) T - 25 - °C SD-HYS SW8 Leakage Current (Off State) @25°C I - - 1.0 A SW8_LKG Notes 18. Guaranteed by Design 19. When Battery voltage is higher than 5.0V and VOUT8 is 5.0V, a polarization diode is necessary to achieve accurate output voltage. See Component Calculation on page 39 for further details. 20. V is 0.6V when the part is powered up and no DVS is changed. DVS is achieved by modifying V reference. FB FB 21. When in Current regulation mode, the Voltage reference is set to 0.230mV to set the maximum current, and it is internally decreased to achieve a factor of the maximum current passing through the LED string 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 13

ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 2.7 V  V  5.5 V, -20C  T  85 C, GND = 0 V, unless otherwise noted. Typical IN A values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit I2C COMMUNICATION Device Physical Address (7 bit Address) - $54 - Maximum I2C Speed - - 400 kHz FREQ Selectable Switching Frequency 1 f 750 - 2000 kHz SW1 Selectable Switching Frequency 2 f 250 - 1000 kHz SW2 Selectable Switching Frequency Step Size f - 250 - kHz STEP Switching Frequency Accuracy -10 - 10 % Retry Timeout Period(23) t - 10 - ms TIMEOUT CURRENT LIMIT MONITORING Overcurrent Limit Timer(23) t - 10 - ms LIMIT Retry Timeout Period(23) t - 10 - ms RETRY OUTPUT OVERVOLTAGE/UNDERVOLTAGE MONITORING Undervoltage Threshold (Response A) V - -20 - % UV-R Overvoltage Threshold (Response A) V - 20 - % OV-R Undervoltage Threshold (Response B) V - -20 - % UV-R Overvoltage Threshold (Response B) V - 20 - % OV-R Filter Delay Timer(23) t - 20 - s FILTER RST RST Reset Delay(23) t - 10 ms RST-DELAY REGULATOR 1 & VG Operating Frequency(22), (23) f 750 - 1500 kHz SW1 Operating Frequency Selection Step Size f - 250 - kHz STEP Constant Time Off Value(23) t - 1.0 - s OFF Low-side Timeout(23) t - 15 - s TIMEOUT REGULATOR 2 Operating Frequency(23) f 750 - 2000 kHz SW1 Operating Frequency Selection Step Size f - 250 - kHz STEP Notes 22. When REG1 is used, the maximum f Frequency programed with external components should be 1500 kHz SW1 23. Guaranteed by design. 34704 Analog Integrated Circuit Device Data 14 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 2.7 V  V  5.5 V, -20C  T  85 C, GND = 0 V, unless otherwise noted. Typical IN A values noted reflect the approximate parameter means at T = 25 °C under nominal conditions, unless otherwise noted. A Characteristic Symbol Min Typ Max Unit REGULATOR 3 Operating Frequency f 750 - 2000 kHz SW1 Operating Frequency Selection Step Size f - 250 - kHz STEP REGULATOR 4 Operating Frequency f 750 - 2000 kHz SW1 Operating Frequency Selection Step Size f - 250 - kHz STEP REGULATOR 5 Operating Frequency f 750 - 2000 kHz SW1 Operating Frequency Selection Step Size f - 250 - kHz STEP REGULATOR 6 Operating Frequency f 250 - 1000 kHz SW2 Operating Frequency Selection Step Size f - 250 - kHz STEP REGULATOR 7 Operating Frequency Selections f 250 - 1000 kHz SW2 Operating Frequency Selection Step Size f - 250 - kHz STEP REGULATOR 8 Operating Frequency f 250 - 1000 kHz SW2 Operating Frequency Selection Step Size f - 250 - kHz STEP 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 15

FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 34704 is an multi-channel power management IC The 34704 accepts an input voltage from various sources: (PMIC) meant to address power management needs for 1 cell Li-Ion/Polymer (2.7 to 4.2 V) various multimedia applications microprocessors in various 5.0 V USB supply or AC wall adapter configurations with a target overall efficiency of > 80% at The different channels are: typical loads. REGULATOR REGULATOR TYPE V TYP (V) I TYP (MA) I MAX (MA) TARGET APPLICATION OUT OUT OUT REG1(25) Synchronous Boost 5.0 100 500 +5.0 V REF REG2 Synchronous Buck-Boost 2.8 / 3.3 200 500 µP I/O REG3 Synchronous Buck 1.2 / 1.5 / 1.8 150 550 µP Core REG4 Synchronous Buck-Boost 1.8 / 2.5 100 300 DDR REG5 Synchronous Buck-Boost 3.3 150 500 µP I/O REG6(25) Synchronous Boost 15.0 20 60 REF+ REG7(25) Inverter Boost -7.0 20 60 REF - REG8 Synchronous Boost 15.0 15 30 Backlight Display Notes 24. Synchronous Buck-Boost: These regulators can work as pure BUCK regulator when the output voltage is lower than the input voltage; and work as pure BOOST regulator when the input voltage is lower than the output voltage. Compensation should be done for the worst case scenario, which is in most of the cases when the device is working as a boost converter, after compensating for this scenario it is recommended to verify the buck operation to assure stability in the whole operating range. 25. Available only on the 34704A REG1, REG3, REG6, and REG8 use internal regulators except REG6, 7, and 8, to spread out the current compensation, while REG2, REG4, REG5, and REG7 use draw by the individual converters from the input supply over external compensation. time, to reduce the peak input current demand. This allows The switching frequency of all regulators except REG6, 7, for better EMI performance and reduction in the input filter & 8 can be selected through the FREQ pin between 750 kHz requirements. and 2.0 MHz in 250 kHz steps. The high frequency operation Each regulator except REG1 uses an external feedback is meant to minimize the size of external components while resistor divider to set the output voltage. All output voltages lower operating frequencies will allow for higher efficiency. can be adjusted dynamically (Dynamic Voltage Scaling) on REG7 is limited to operate at a lower frequency to minimize the fly through an I²C serial interface. All converters, except switching noise induced by driving the external switching REG1, utilize automatic soft-start by ramping the reference MOSFET, but also can operate at the 1.0 MHz value with voltage to the error amplifier to prevent sudden change in proper board layout. REG 6, 7, and 8 switching frequency can duty cycle and output current/voltage at power up. REG1 be selected between 250 kHz and 1.0 MHz in 250 kHz steps (VG) will limit the inrush current by implementing a peak through I2C. current detect and a constant off time. For all regulators and at lower loads, a pulse skipping The 34704 is equipped with a dual function Power On/Off mode is implemented to maintain high efficiency. pin (ONOFF). This pin can be controlled by a mechanical Note that pulse skipping occurs when the regulator enters switch to turn the device on or off. Pressing and releasing the into discontinuous conduction mode (DCM) at very light mechanical switch turns the 34704 on while pressing and loads, however transitions between DCM and CCM may holding the switch for a time period (programmable through result in noisy switching nodes, therefore it is recommended I2C) turns the 34704 off. Enable/disable control is also to design the regulators to work in CCM all the time. Pulse granted through I2C for groups of regulators and the whole skipping function is not guaranteed by circuit implementation. IC. The 34704 uses 4 different phases of switching for all 34704 Analog Integrated Circuit Device Data 16 Freescale Semiconductor

FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION FUNCTIONAL PIN DESCRIPTION REG5 BOOST STAGE BOOTSTRAP CAPACITOR REG3 SWITCHING NODE (SW3) INPUT PIN (BT5U) The inductor is connected between this pin and the Connect a 1.0 F capacitor between this pin and SW5U regulated REG3 output. pin to enhance the gate of the Switch Power MOSFET. REG3 OUTPUT VOLTAGE RETURN PIN (VOUT3) REG4 BUCK STAGE BOOTSTRAP CAPACITOR This is the discharge path of REG3 output voltage. INPUT PIN (BT4D) Connect a 0.01 F capacitor between this pin and SW4D REG3 VOLTAGE FEEDBACK INPUT FOR pin to enhance the gate of the Switch Power MOSFET. VOLTAGE REGULATION/PROGRAMMING (FB3) Connect the feedback resistor divider to this pin. REG4 POWER SUPPLY INPUT VOLTAGE (PVIN4) This is the connection to the drain of the high-side switch SOFT START TIME (SS) FET. Input decoupling /filtering is required for proper REG4 The soft start time for all regulators can be adjusted by operation. connecting this pin to an external resistor divider between VDDI and AGND pins. REG4 BUCK STAGE SWITCHING NODE (SW4D) The inductor is connected between this pin and the SW4U OSCILLATOR FREQUENCY (FREQ) pin. The oscillator frequency can be adjusted by connecting this pin to an external resistor divider between VDDI and REG4 REGULATED OUTPUT VOLTAGE PIN AGND pins. This pin sets F value. SW1 (VOUT4) Connect this pin to the load and to the output filter as close REG8 VOLTAGE FEEDBACK INPUT FOR to the pin as possible. VOLTAGE REGULATION/PROGRAMMING (FB8) Connect the feedback resistor divider to this pin, when REG4 BOOST STAGE SWITCHING NODE (SW4U) voltage mode control is used. When current mode control is The inductor is connected between this pin and the SW4D used, connect this pin between the LED string and an ISET pin. resistor to GND to force the operating current. Refer to Figure 10 and Figure 11. Exclude the components not used. REG4 BOOST STAGE BOOTSTRAP CAPACITOR INPUT PIN (BT4U) REG8 BOOTSTRAP CAPACITOR INPUT PIN (BT8) Connect a 0.01 F capacitor between this pin and SW4U Connect a 0.01 F capacitor between this pin and SW8 pin pin to enhance the gate of the Switch Power MOSFET. to enhance the gate of the Synchronous Power MOSFET. REG4 VOLTAGE FEEDBACK INPUT FOR REG8 REGULATED OUTPUT VOLTAGE PIN VOLTAGE REGULATION/PROGRAMMING (FB4) (VOUT8) Connect the feedback resistor divider to this pin. Connect this pin directly to the load directly and to the output filter as close to the pin as possible. REG4 COMPENSATION NETWORK CONNECTION (COMP4) REG8 SWITCHING NODE (SW8) REG4 compensation network connection. The inductor is connected between this pin and VIN pin. REG3 BOOTSTRAP CAPACITOR INPUT PIN (BT3) REG1 SWITCHING NODE (SW1) Connect a 0.01 F capacitor between this pin and SW3 pin The inductor is connected between this pin and VIN pin. to enhance the gate of the Switch Power MOSFET. REG1 REGULATED OUTPUT VOLTAGE BEFORE REG3 POWER SUPPLY INPUT VOLTAGE (PVIN3) THE CUT-OFF SWITCH (VG) This is the connection to the drain of the high-side switch REG1 regulated output voltage before the cutoff switch. FET. Input decoupling /filtering is required for proper REG3 This supplies the internal circuits and the gate drive. operation. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 17

FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION REG1 REGULATED OUTPUT VOLTAGE PIN REG6 SWITCHING NODE (SW6) (34704A ONLY) (VOUT1) (34704A ONLY) The inductor is connected between this pin and the VIN Connect this pin directly to the load directly and to the pin. output filter as close to the pin as possible. REG6 REGULATED OUTPUT VOLTAGE PIN REG1 BOOTSTRAP CAPACITOR INPUT PIN (BT1) (VOUT6) (34704A ONLY) Connect a 1.0 F capacitor between this pin and SW1 pin Connect this pin directly to the load directly and to the to enhance the gate of the Switch Power MOSFET. output filter as close to the pin as possible. I2C SERIAL INTERFACE CLOCK INPUT (SCL) ANALOG GROUND (AGND) I2C serial interface clock input. Analog ground of the IC. I2C SERIAL INTERFACE DATA INPUT (SDA) BATTERY VOLTAGE CONNECTION (VIN) I2C serial interface data input Input decoupling /filtering is required for the device to operate properly. POWER RESET OUTPUT SIGNAL (MICROPROCESSOR RESET) (RST) INTERNAL SUPPLY VOLTAGE (VDDI) This is an open drain output and must be pulled up by an Connect a 1.0 F low ESR decoupling filter capacitor external resistor to a supply voltage like V . between this pin and GND. IN REG7 COMPENSATION NETWORK CONNECTION BATTERY DETECTION (LION) (COMP7) Pull this pin high to VIN to indicate a connection to a Li-Ion REG7 compensation network connection. battery. REG7 RESISTOR FEEDBACK NETWORK DUAL FUNCTION IC TURN ON/OFF (ONOFF) REFERENCE VOLTAGE (VREF7) (34704A ONLY) This is a hardware enable/disable for the 34704. It can be Connect this pin to the bottom of the feedback resistor connected to a mechanical switch to turn the power On or Off. divider. REG2 BOOST STAGE BOOTSTRAP CAPACITOR REG7 VOLTAGE FEEDBACK INPUT FOR INPUT PIN (BT2U) VOLTAGE REGULATION/PROGRAMMING (FB7) Connect a 1.0 F capacitor between this pin and SW2U (34704A ONLY) pin to enhance the gate of the Switch Power MOSFET. Connect the feedback resistor divider to this pin. REG2 COMPENSATION NETWORK CONNECTION (COMP2) REG7 EXTERNAL POWER MOSFET GATE DRIVE (DRV7) (34704A ONLY) REG2 compensation network connection. REG7 external Power MOSFET gate drive. REG2 VOLTAGE FEEDBACK INPUT FOR VOLTAGE REGULATION/PROGRAMMING (FB2) REG7 OUTPUT VOLTAGE RETURN PIN (VOUT7) (34704A ONLY) Connect the feedback resistor divider to this pin. This is the discharge path of REG7 output voltage. REG2 BUCK STAGE BOOTSTRAP CAPACITOR INPUT PIN (BT2D) REG6 VOLTAGE FEEDBACK INPUT FOR VOLTAGE REGULATION/PROGRAMMING (FB6) Connect a 1.0 F capacitor between this pin and SW2D (34704A ONLY) pin to enhance the gate of the Switch Power MOSFET. Connect the feedback resistor divider to this pin. REG2 POWER SUPPLY INPUT VOLTAGE (PVIN2) REG6 BOOTSTRAP CAPACITOR INPUT PIN (BT6) This is the connection to the drain of the high-side switch (34704A ONLY) FET. Input decoupling /filtering is required for proper REG2 operation. Connect a 0.01 F capacitor between this pin and SW6 pin to enhance the gate of the Synchronous Power MOSFET. 34704 Analog Integrated Circuit Device Data 18 Freescale Semiconductor

FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION REG2 BUCK STAGE SWITCHING NODE (SW2D) REG5 POWER SUPPLY INPUT VOLTAGE (PVIN5) The inductor is connected between this pin and the SW2U This is the connection to the drain of the high-side switch pin. FET. Input decoupling /filtering is required for proper REG5 operation. REG2 REGULATED OUTPUT VOLTAGE PIN (VOUT2) REG5 BUCK STAGE BOOTSTRAP CAPACITOR INPUT PIN (BT5D) Connect this pin to the load and to the output filter as close to the pin as possible. Connect a 1.0 F capacitor between this pin and SW5D pin to enhance the gate of the Switch Power MOSFET. REG2 BOOST STAGE SWITCHING NODE (SW2U) REG5 VOLTAGE FEEDBACK INPUT FOR The inductor is connected between this pin and the SW2D pin. VOLTAGE REGULATION/PROGRAMMING (FB5) Connect the feedback resistor divider to this pin. REG5 BOOST STAGE SWITCHING NODE (SW5U) The inductor is connected between this pin and the SW5D REG5 COMPENSATION NETWORK CONNECTION pin. (COMP5) REG5 compensation network connection. REG5 REGULATED OUTPUT VOLTAGE PIN (VOUT5) POWER GROUND CONNECTION FOR ALL OF THE Connect this pin to the load and to the output filter as close REGULATORS EXCEPT REG7 (PGND) to the pin as possible. Power Ground Connection for all of the regulators except REG7. REG5 BUCK STAGE SWITCHING NODE (SW5D) The inductor is connected between this pin and the SW5U pin. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 19

FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION * Figure 4. MC34704 Functional Internal Block Diagram INTERNAL BIAS CIRCUIT VDDI Reference Voltage The 34704 uses the internal VG voltage to provide a Gate Driver Voltage (VG) precise low current 2.5 V voltage that is meant to serve as REG1/VG is the main regulator of the 34704 IC and will be reference voltage to derive the FREQ and SS voltage needed used to supply internal circuitry and voltage biases through to set the switching frequency 1 (FSW1) and the soft start, the VG output. It also provides the gate drive voltage for the respectively. rest of the regulators and itself. See Power-Up Sequence on page 28 for more details on FAULT DETECTION AND PROTECTION how REG1 is a critical part of powering up the 34704. Based on this, REG1 will need extra circuitry to help it boot up until Thermal Limit Detection its output voltage is high enough that it can supply internal There is a thermal sensor for each regulator except REG7. circuitry for the main control loop to take over. All regulators of the corresponding group will shutdown if at REG1 VG starts up in peak current detect PFM mode and least one of them reaches the thermal limit. If either REG2, REG1 VG output starts rising. When the appropriate internal REG3 or REG4 reaches its thermal limit, the whole part will circuitry is alive and the switching frequency F is shutdown immediately. SW1 selected, the PWM control of REG1 can take over. Overcurrent & Short-circuit Monitoring VREF Generator - Internal Reference The current limit circuitry has two levels of current limiting: Each one of the regulators in the 34704 uses a DAC which • A soft overcurrent limit (overcurrent limit): If the peak is controlled by the I2C interface to generate a dynamic VREF current reaches the typical overcurrent limit, the switcher voltage for setting the output voltage on each regulator. will start a cycle-by-cycle operation to limit the current and a 10 ms current limit timer starts. The switcher will stay in this mode of operation until the part regains normal 34704 Analog Integrated Circuit Device Data 20 Freescale Semiconductor

FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION operation, or shuts down after a failure to regain normal changed via I2C at any time after power up has successfully operation. completed. • A hard overcurrent limit (short-circuit limit) that is higher than the cycle by cycle limit at which the device reacts by Phase Control shutting down the output immediately. This is necessary to REG1 to REG5 use the main Switching frequency FSW1, prevent damage in case of a short-circuit. After that, only which is configured through the FREQ terminal at power up. GrpB will attempt a one time retry after a time-out period of FSW1 uses 4 different phases of switching (clock is 80 10 ms and will go through a new soft start cycle degrees out of phase) to spread out the current draw by the individual converters from the input supply over time to Output Overvoltage/Undervoltage Monitoring reduce the peak input current demand. The remaining In the case of an output overvoltage/undervoltage, the regulators use FSW2 which can be programmed at any time user has two options that can be programmed through the via I2C after a successful power up sequence. I2C interface: Fault Register Response A: The output will switch off automatically and the 34704 would alert the processor through I2C that such an The 34704 has a dedicate fault register accessible via I2C event happened. which indicate which regulator is detecting a fault situation. In Response B: The output will not switch off. Rather the addition to this, each channel has its own fault register which 34704 communicates to the processor that an overvoltage/ indicates the type of fault detected in that regulator. undervoltage condition has occurred and waits for the processor decision to either shutoff or not; in the mean time I2C communication and Registers the control loop will try to fix itself. The 34704 can communicate using a standard I2C, NOTE: If Response A is set on any of the regulators from communication protocol or an accurate I2C protocol. During GrpB, and a OV/UV event occurs in the corresponding the first one, the device processes the given command as regulator, the complete device will shutdown and try to restart soon as it has received it. During the accurate data as long as the OV/UV is no longer present. This will also set communication, the device requires that each read/write the RST signal low until REG2, 3 and 4 are on regulation. command be sent twice to validate the data. The 34704 provides a user accessible register map that allows various LOGIC AND CONTROL general IC configurations as well as independent control of each regulator, including fault flag registers and all configurable features for each regulator. Startup Sequencing At power up, the VG regulator starts ramping up in peak OUTPUT GROUPS - REGULATORS detect mode. Meanwhile, VDDI is tracking VG until it reaches regulation and releases a POR signal that enables the The 34704 is divided in 5 different groups which are internal circuitry and reads the FREQ and SS configuration to arranged as follows: ramp up REG2, REG3 and REG4, that serve as the MPU • GrpA: Includes REG1(26) (VOUT1) main power supplies. Once the MPU is up, I2C • GrpB: Includes REG2, REG3, and REG4 communication is available to enable or disable GrpA, GrpC, • GrpC: Includes REG5, REG6(26), and REG7(26) GrpD and GrpE. An extra sequence can be configured for • GrpD: Includes REG8 REG5, REG6 and REG7, changing the order in which they • GrpE: This is a special group. It includes REG5 when ramp up when enabled. See Power-Up Sequence on page GrpC/E power sequencing option#1 is chosen 28. Turning on/off each group would cause all contained Soft Start Control regulators to turn on/off. During power up the 34704 reads the SS terminal to Notes configure a default soft start timing for all regulators when 26. Only on 34704A these are enabled. Soft start for REG5 to REG8 can be 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 21

FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION REGUALATOR OVERVIEW WITH EFFICIENCY ANALYSIS REG1 (34704A Only) • There is no ALLOFF shutdown command through the I2C interface AND REG1 is a synchronous boost PWM voltage-mode control DC/DC regulator available only in the 34704A. Even though • No faults exist that would cause the 34704 to shutdown REG1 is a synchronous regulator, it is recommended to have The VOUT1 output will be active when: a diode connected externally across its synchronous • VG output is available AND MOSFET. When the battery voltage is above REG1’s output • There is no GrpA shutdown command through the I2C (>5.0 V) as the case might be when connected to the USB interface AND supply or wall adaptor, the REG1 power MOSFETs will be tri- • No faults exist that would cause the VOUT1 to shut down stated and the voltage on the output will be Battery minus the diode drop. This will help maintain REG1’s output to a REG2 maximum of 5.2 V and not allow it to drift all the way to 5.5 V. The switcher will operate in DCM at very light loads to This is a 4-switch synchronous buck-boost PWM voltage- allow pulse skipping. mode control DC/DC regulator. On the 34704A, when the appropriate command is See Power-Up Sequence on page 28 for more details on received from the processor to turn on VOUT1, then the when REG2 is powered up in the sequence. isolation FET of REG1 would turn on gradually to avoid any The switcher will operate in DCM at very light loads to inrush current out of VG and to ramp the VOUT1 voltage in a allow pulse skipping. controlled manner. VOUT2 will be discharged every time the regulator is REG1 VOUT1 will be discharged every time GrpA is shutting down and it will be held low by the discharge FET as shutting down and it will be held low by the discharge FET as long as possible. long as possible. Characteristics Characteristics • It powers up directly from the battery • It powers up directly from the battery • Operates at a switching frequency equals to F SW1 • Operates at a switching frequency equals to FSW1 • Drives integrated low RDS(on) N-channel power MOSFETs • Drives integrated low R N-channel power MOSFETs (NHV_HC) as its output stage DS(on) (NHV_HC) as its output stage • The output is ±2% accuracy • It offers load disconnect from the input battery when the • Output voltage is adjustable by means of an external output is off (True Cutoff) resistor divider • The output is ±4% accuracy • The output can be adjusted up or down at 2.5% steps for • Output voltage is set to 5.0 V by means of an internal a total of +17.5% to -20.0% on each direction allowing resistor divider Dynamic Voltage Scaling • The output can be adjusted up or down at 2.5% for a total • Uses bootstrap networks with an internal diode to power of 10% on each direction allowing Dynamic Voltage its high-side MOSFETs Scaling • All gate drive circuits are supplied from VG • Uses a bootstrap network with an internal diode to power • Uses external compensation its synchronous MOSFET • The output is monitored for undervoltage and overvoltage • All gate drive circuits are supplied from REG1’s own VG conditions output. • The output is monitored for overcurrent and short-circuit • Uses integrated compensation conditions • The output is monitored for undervoltage and overvoltage • The regulator is monitored for overtemperature conditions conditions • The output is monitored for overcurrent and short-circuit Operation Modes conditions The switcher will be active when: • The regulator is monitored for overtemperature conditions • VG is in regulation AND • There is no GrpB shutdown command through the I2C Operation Modes interface AND The VG output is always active as long as: • No faults exist that would cause GrpB to shut down • The IC is not in an undervoltage lockout AND • No shutdown signal through the ONOFF pin is present REG3 AND This is a synchronous buck PWM voltage-mode control DC/DC regulator. 34704 Analog Integrated Circuit Device Data 22 Freescale Semiconductor

FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION See Power-Up Sequence on page 28 for more details on • Drives integrated low R N-channel power MOSFETs DS(on) when REG3 is powered up in the sequence. (NHV_HC) as its output stage The switcher will operate in DCM at very light loads to • The output is ±2% accuracy allow pulse skipping. • Output voltage is adjustable by means of an external VOUT3 will be discharged every time the regulator is resistor divider shutting down and it will be held low by the discharge FET as • The output can be adjusted up or down at 2.5% steps for long as possible. a total of +17.5% to -20.0% on each direction allowing Dynamic Voltage Scaling. Characteristics • Uses bootstrap networks with an internal diode to power • It powers up directly from the battery its high-side MOSFETs • Operates at a switching frequency equals to F • All gate drive circuits are supplied from VG. SW1 • Drives integrated low R N-channel power MOSFETs • Uses external compensation DS(on) (NHV_HC) as its output stage • The output is monitored for undervoltage and overvoltage • The output is ±4% accuracy conditions • Output voltage is adjustable by means of an external • The output is monitored for overcurrent and short-circuit resistor divider conditions • The output can be adjusted up or down at 2.5% steps to • The regulator is monitored for overtemperature conditions achieve from +17.5% to -20.0% on each direction allowing Dynamic Voltage Scaling using the I2C DVS register. Operation Modes • An extra fine voltage scaling in 0.5% steps helps to adjust The switcher will be active when: down the output voltage as low as 40%. • VG is in regulation AND • Uses a bootstrap network with an internal diode to power • There is no GrpB shutdown command through the I2C its switch MOSFET interface AND • All gate drive circuits are supplied from VG. • No faults exist that would cause GrpB to shut down • Uses integrated compensation. • The output is monitored for undervoltage and overvoltage REG5 conditions This is a 4-switch synchronous buck-boost PWM voltage- • The output is monitored for overcurrent and short-circuit mode control DC/DC regulator. conditions See Power-Up Sequence on page 28 on for more details • The regulator is monitored for overtemperature conditions on when REG5 is powered up in the sequence. The switcher will operate in DCM at very light loads to Operation Modes allow pulse skipping. The switcher will be active when: VOUT5 will be discharged every time the regulator is • VG is in regulation AND shutting down and it will be held low by the discharge FET as • There is no GrpB shutdown command through the I2C long as possible. interface AND Characteristics • No faults exist that would cause GrpB to shut down • It powers up directly from the battery REG4 • Operates at a switching frequency equals to F SW1 This is a 4-switch synchronous buck-boost PWM voltage- • Drives integrated low R N-channel power MOSFETs DS(on) mode control DC/DC regulator. (NHV_HC) as its output stage See Power-Up Sequence on page 28 for more details on • The output is ±2% accuracy when REG4 is powered up in the sequence. • Output voltage is adjustable by means of an external The switcher will operate in DCM at very light loads to resistor divider allow pulse skipping. • The output can be adjusted up or down at 2.5% steps for VOUT4 will be discharged every time the regulator is a total of +17.5% to -20.0% on each direction allowing shutting down and it will be held low by the discharge FET as Dynamic Voltage Scaling. long as possible. • Uses bootstrap networks with an internal diodes to power its high-side MOSFETs Characteristics • All gate drive circuits are supplied from VG. • It powers up directly from the battery • Uses external compensation • Operates at a switching frequency equals to FSW1 • The output is monitored for undervoltage and overvoltage conditions 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 23

FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION • The output is monitored for overcurrent and short-circuit REG7 (Only 34704A) conditions This is a none-synchronous buck-boost inverting PWM • The regulator is monitored for overtemperature conditions voltage-mode control DC/DC regulator. See Power-Up Sequence on page 28 for more details on Operation Modes when REG7 is powered up in the sequence. The switcher will be active when: The switcher will operate in DCM at very light loads to • VG is in regulation AND allow pulse skipping. • There is no GrpC (OR GrpE) shutdown command through VOUT7 will be discharged every time the regulator is the I2C interface AND shutting down and it will be held high to ground by the • No faults exist that would cause GrpC (OR GrpE) to shut discharge FET as long as possible. down Characteristics REG6 (Only 34704A) • It powers up directly from the battery This is a synchronous boost PWM voltage-mode control • Operates at a switching frequency equals to F SW2 DC/DC regulator. • Drives an external P-channel power MOSFET See Power-Up Sequence on page 28 for more details on • The output is ±2% accuracy when REG6 is powered up in the sequence. • Output voltage is adjustable by means of an external The switcher will operate in DCM at very light loads to resistor divider allow pulse skipping. • The output can be adjusted up or down at 2.5% steps for VOUT6 will be discharged every time the regulator is a total of 10% on each direction allowing Dynamic Voltage shutting down and it will be held low by the discharge FET as Scaling. long as possible. • All gate drive circuits are supplied from V G • Uses external compensation, the type is up to the designer Characteristics • The output is monitored for undervoltage and overvoltage • It powers up directly from the battery conditions • Operates at a switching frequency equals to F SW2 • Drives integrated low R N-channel power MOSFETs Operation Modes DS(on) (NVHV_LC) as its output stage The switcher will be active when: • It offers load disconnect from the input battery when the • VG is in regulation AND output is off (True Cut-Off) • There is no GrpC shutdown command through the I2C • The output is ±4% accuracy interface AND • Output voltage is adjustable by means of an internal • No faults exist that would cause GrpC to shut down resistor divider • The output can be adjusted up or down at 2.5% steps for REG8 a total of 10% on each direction allowing Dynamic Voltage This is a synchronous boost PWM voltage-mode control Scaling DC/DC regulator. • Uses a bootstrap network with an internal diode to power See Power-Up Sequence on page 28 for more details on its synchronous MOSFET when REG8 is powered up in the sequence. • All gate drive circuits are supplied from VG. VOUT8 will be discharged every time the regulator is • Uses integrated compensation. shutting down and it will be held to ground by the discharge • The output is monitored for undervoltage and overvoltage FET as long as possible. conditions This regulator offers either voltage regulation for organic • The output is monitored for overcurrent and short-circuit LEDs or current regulation for LCD backlighting LEDs. It conditions provides either voltage or current feedback for these • The regulator is monitored for overtemperature conditions purposes through the same feedback pin. The regulator cannot drive only 1LED with a forward Operation Modes voltage drop of less than the battery input voltage. The switcher will be active when: The processor would set the REG8 register through I2C • VG is in regulation AND before enabling REG8 to indicate if voltage regulation or • There is no GrpC shutdown command through the I2C current regulation will be used. interface AND Characteristics • No faults exist that would cause GrpC to shut down • It powers up directly from the battery 34704 Analog Integrated Circuit Device Data 24 Freescale Semiconductor

FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION • Operates at a switching frequency equals to F OVERALL EFFICIENCY ANALYSIS SW2 • Drives integrated low RDS(on) N-channel power MOSFETs In battery applications, it is highly recommended to power (NVHV_LC) as its output stage every single regulator directly from the battery to obtain full • It offers load disconnect from the input battery when the output capability: output is off (True Cut-Off) • The output is ±4% accuracy VBAT REG1 V1 (5.0V) • Output voltage is adjustable by means of an external VBAT REG2 V2 (2.8 / 3.3V) resistor divider when in voltage regulation mode • A 240 mV current limit comparator will be used to program/ VBAT REG3 V3 (1.2V / 1.5V / 1.8V) sense the voltage drop across the current setting resistor VBAT REG4 V4 (1.8V / 2.5V) at the bottom of the LED string connected to the REG8 output when the current regulation mode is selected. VBAT REG5 V5 (3.3V) This will be used to program the maximum current flowing VBAT REG6 V6 (15V) and will regulate it • The output can be adjusted up or down at 2.5% steps for VBAT REG7 V7 (-7.0V) a total of 10% on each direction allowing Dynamic Voltage VBAT REG8 V8 (15V) Scaling • Maximum output current is adjustable by means of an Figure 5. Overall Efficiency Analysis external resistor connected to the FB8 pin and then the Efficiency analysis includes the following losses: output current can be scaled down from the set maximum • MOSFET Conduction Losses in 16 steps through I2C interface • MOSFET Switching Losses (Except for REG7 due to • Uses a bootstrap network with an internal diode to power external MOSFET and board layout dependence) its synchronous MOSFET • MOSFET Gate Charging Losses • All gate drive circuits are supplied from VG. • MOSFET Deadtime Losses • Uses integrated compensation • External Diode Losses (Only for REG7) • The output is monitored for overcurrent and short-circuit • Inductor Winding DC Losses conditions • Inductor Core Losses (Assumed to be 20% of DC Losses • The regulator is monitored for overtemperature conditions as a rule of thumb) • The output is monitored for undervoltage and overvoltage • Output AC Losses conditions Efficiency Analysis Operation Modes In this configuration, all of the regulators are supplied or The switchers will be active when: powered directly with 3.6 V nominal, battery voltage. • VG is in regulation AND Efficiency was calculated using the maximum allowed • There is no GrpD shutdown command through the I2C frequency of 1.5 MHz and 1.0 MHz for F and F , SW1 SW2 interface AND respectively, in this configuration. As a result, the following • No faults exist that would cause GrpD to shut down numbers are valid for worst case operation conditions. The following table shows the detailed analysis for each regulator with V2 at 3.3 V, V3 at 1.2 V, and V4 at 1.8 V. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 25

FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Table 6. Regulator Analysis Table REG1 REG2 REG3 REG4 REG5 REG6 REG7 REG8 Vin (V) 3.60 3.60 3.60 3.60 3.60 3.60 3.60 3.60 Vout (V) 5.00 3.30 1.20 1.80 3.30 15 -7 15 Iout_typ (A) 0.100 0.200 0.150 0.100 0.150 0.050 0.050 0.015 Iout_max (A) 0.500 0.500 0.550 0.300 0.500 0.060 0.060 0.030 DCR(m) 230 230 230 310 230 230 230 230 Cout (F) 22 22 22 22 22 22 22 22 ESR (m 9.00 9.00 9.00 9.00 9.00 9.00 9.00 9.00 Fsw (kHz) 1500 1500 1500 1500 1500 1000 1000 1000 Lout (H) 1.50 1.50 1.50 1.50 1.50 4.70 4.70 4.70 Iin_typ (A) 0.154 0.201 0.063 0.059 0.150 0.254 0.107 0.077 Iin_max (A) 0.540 0.502 0.209 0.178 0.501 0.304 0.128 0.154 ILout_peak (A) 0.724 0.510 0.649 0.444 0.512 0.444 0.443 0.297 ICout_RMS (A) 0.212 0.005 0.074 0.076 0.0006 0.071 0.129 0.043 Pout (W) 0.500 0.660 0.180 0.180 0.495 0.750 0.350 0.225 Ploss On Chip (W) 0.042 0.047 0.038 0.028 0.034 0.135 0.000 0.045 Ploss Total (W) 0.044 0.049 0.041 0.030 0.035 0.145 0.027 0.047 Pin (W) 0.544 0.709 0.221 0.210 0.530 0.895 0.377 0.272 n (%) 91.90% 93.12% 81.48% 85.91% 93.33% 60.00% 69.00% 64.00% Table 7. 34704A overall system efficiency 84% Table 8. 34704B overall system efficiency 89% Overall System Overall System Pout (W) 3.340 Pout (W) 1.74 Ploss On Chip (W) 0.369 Ploss On Chip (W) 0.192 Ploss Total (W) 0.41 Ploss Total (W) 0.202 Pin (W) 3.75 Pin (W) 1.942 n (%) 84.00% n (%) 89.6% 34704 Analog Integrated Circuit Device Data 26 Freescale Semiconductor

FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MC34704 EFFICIENCY WAVEFORMS REG5 Efficiency 100% REG1 Efficiency 90% 100% 80% 90% 70% 80% 60% 70% 50% 60% 40% 50% 30% 40% 20% 30% 10% 20% 0% 10% 0 100 200 300 400 500 600 IOUT 0% 0 100 200 300 400 500 600 IOUT REG6 Efficiency 100% REG2 Efficiency 90% 100% 80% 90% 70% 80% 60% 70% 50% 60% 40% 50% 30% 40% 20% 30% 10% 20% 0% 10% 0 10 20 30 40 50 60 70 IOUT 0% 0 100 200 300 400 500 600 IOUT REG7 Efficiency 100% REG3 Efficiency 90% 100% 80% 90% 70% 80% 60% 70% 50% 60% 40% 50% 30% 40% 20% 30% 10% 20% 0% 10% 0 10 20 30 40 50 60 70 IOUT 0% 0 100 200 300 400 500 600 IOUT REG8 Efficiency 100% REG4 Efficiency 90% 100% 80% 90% 70% 80% 60% 70% 50% 60% 40% 50% 30% 40% 20% 30% 10% 20% 0% 10% 0 5 10 15 20 25 30 35 IOUT 0% 0 50 100 150 200 250 300 350 IOUT 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 27

FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES POWER-UP SEQUENCE other and the entire system. This makes power sequencing control a much easier task for the user where most of the Following is the power up sequence from a battery group internal sequencing in now handled by the PMIC. All connection or a Power On signal through the ONOFF pin. the processor has to do is to command the group and not 1. Battery initially connected to VIN. each regulator. 2. LION pin is used to determine if a battery is being used The regulators groups are as follows: (High for Li-Ion battery). • GrpA: Includes REG1 (VOUT1) 3. At initial power up from a cold start like the above with • GrpB: Includes REG2, REG3, and REG4 the battery first connected, the status of the ONOFF • GrpC: Includes REG5, REG6, and REG7 pin is ignored and 34704 moves forward to step (5). • GrpD: Includes REG8 4. After the cold start or battery insertion power up, activity on the ONOFF pin is used to determine if the • GrpE: This is a special group. It includes REG5 when device is enabled or disabled. If the device is disabled, GrpC/E power sequencing option#1 is chosen then nothing happens. If the device is enabled then, 34704 moves forward to step (5). SHUTDOWN SEQUENCES 5. The input battery UVLO signal de-asserts if the input • Processor can disable VOUT1 (GrpA) at any point it voltage is above the UVLO rising threshold. desires 6. REG1 VG starts up in peak detect PFM and REG1 VG • Processor can disable REG8 (GrpD) at any point it desires output starts rising. • Processor can disable REG5 (GrpE) at any point it desires if sequencing option#1 is picked 7. V output voltage will start tracking REG1 VG output. DDI • Processor can shutdown GrpC according to the power 8. When REG1 VG output rises high enough such that sequencing options 1, 2, 3, or 4 (see section “I2C User V voltage is in regulation a POR signal is released DDI Interface”) and all internal circuitry can be enabled. I2C • If any regulator in GrpC is shutting down due to a fault, the communication will remain disabled for normal power other regulators in GrpC will also shutdown by following up sequence. The values of the FREQ and SS pins are the GrpC power sequencing options 1, 2, 3, or 4 (see read at this point. section “I2C User Interface”) 9. REG1 PWM control loop can take over control of • If any regulator in GrpB is shutting down due to a fault, the REG1 output once the VG voltage reaches a certain other regulators in GrpB will also shutdown by following threshold set internally. the processor supplies shutdown sequence. Then, GrpA, 10. When REG1 is in regulation, it will be used to supply GrpC, GrpD, and GrpE (if applicable) will simultaneously the Power MOSFET gate voltage for all of the other shutdown keeping any sequencing within each group as regulators except REG7. necessary. VG will stay alive to perform a power up retry for GrpB but only for one time. If the power up cycle is 11. REG3 is enabled, then when REG3 is in regulation. successful, then normal operation is back. If the fault 12. REG2 is enabled, then when REG2 is in regulation. returns, then the shutdown sequence is repeated and then 13. REG4 is enabled, then when REG4 is in regulation. VG shuts down 14. I2C communication is enabled now since the processor • Processor can shutdown the 34704 by sending an supplies are up. “ALLOFF” command, then GrpA, GrpC, GrpD, and GrpE (if applicable) will simultaneously shutdown keeping any 15. 34704 will de-assert the RST signal to indicate a sequencing within each group as necessary. Then, GrpB “Power Good” after 10 ms of wait time. This output will will shutdown according to the processor supply shutdown be connected to the reset pin of the microprocessor. sequence. Then, VG will shut down. 16. The microprocessor then takes over and can enable • The previous shutdown event can also happen through the REG1 VOUT1 and REG5 through REG8. The ONOFF pin by pressing and holding the pin for a time processor needs to send a command for REG8 mode period (programmable through I2C with a default of 1sec) of operation. The processor can also change REG5-8 • During battery depletion and when the input voltage soft start time before enabling them. The processor can passes the UVLO falling threshold, all of the outputs will be also power down the system with an ALLOFF disabled without honouring the power down sequence command. This is to guarantee that the outputs are off and battery is For power sequencing needs, the different regulators are not depleted further. grouped based on their function and how they relate to each 34704 Analog Integrated Circuit Device Data 28 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES • In any of the previous shutdown sequences, VG output will The switching frequency will be selectable for all of the stay alive to maintain internal circuitry and logic until all regulators. REG6, 7 & 8 switching frequency (F ) will be SW2 other regulators are off, then it will shut off. selectable through I2C to be between 250 kHz and 1.0 MHz in 250 kHz steps. The rest of the regulators switching POWER SUPPLY frequency (FSW1) will be selectable through the FREQ pin and can be selected between 750 kHz and 2.0 MHz, in The battery voltage range is the following depending on 250 kHz steps. the application: F default value is 2.0 MHz. This value is obtained by • 1-cell Li-Ion/Polymer: 2.7 to 4.2 V. Typ value is 3.6 V SW1 tying the FREQ pin to VDDI. F default value is 500 kHz. • USB supply or AC wall adapter: 4.5 to 5.5 V. Typ value is SW2 F will be selectable through programming the FREQ 5.0 V. This gives a total input voltage supply range of 2.7 SW1 pin with an external resistor divider connected between VDDI to 5.5 V and AGND pins. F will only be selectable through I2C. For the regulators, each one will be supplied separately Please refer to theS “WI22C Programmability” section. through its own power input. The 34704 uses 4 different phases of switching (clock is 80 degrees out of phase) for F to spread out the current LION PIN SW1 draw by the individual converters from the input supply over LION pin is always tied to VIN level. time to reduce the peak input current demand. This allows for better EMI performance and reduction in the input filter FREQUENCY SETTING PIN (FREQ PIN) requirements. F has no phase relation with F . The SW1 SW2 There are two switching frequencies on board the 34704, following distribution is shown for FSW1 of 2.0 MHz. The one for REG6, 7 & 8, and the other for the rest of the regulators grouping is based on their maximum current draw regulators. To avoid any jitter or interference problems by and attempts to reduce the effect on the input current draw. having two oscillators on board, the switching frequency will be derived from the main oscillator using a frequency divider. 500ns 500ns 500ns 500ns REG1/VG REG1/VG REG1/VG REG1/VG REG2 REG2 REG2 REG2 REG5, REG3 REG5, REG3 REG5, REG3 REG4 REG4 REG4 SOFT START PIN (SS PIN) • If and only if the device is on and the ONOFF pin is pulled down for a time period (1s as a default and selectable to Initially at power up, the soft start time will be set for all of 2.0 sec, 1.5 sec, 1.0 sec or 0.5 sec via the I2C interface), the regulators through programming the SS pin with an then the device powers off after a second time period external resistor divider connected between VDDI and AGND elapses unless it is masked by a command via the I2C pins (see the 34704A Typical Application Diagram). interface: After power up, the soft start value for REG5 through REG8 can be changed and programmed through I2C. REG2 • The second period is the same amount of time as the through REG4 soft start value is only set by the SS pin and first period so that the counter can be shared cannot be programmed through I2C. See section “I2C Programmability” for more details. • When the first period elapses a shutdown flag is set to alert the processor that a shutdown signal has been ONOFF PIN activated. The ONOFF pin can be released after this This is a hardware enable/disable feature OR pin for flag is set without affecting what will happen next the 34704: • A CPU can read out the shutdown flag to determine • It can be connected to a mechanical switch to turn the what to do power On or Off • The device is power off by a command via the I2C interface • Power off the device immediately by a command via I2C as well interface (ALLOFF command) • The power off by hardware can be masked by a command via the I2C interface • Ignore the power off by sending a command via I2C • If the device is off and a falling edge is detected at the interface to clear the shutdown flag ONOFF pin, the device starts up 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 29

FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES • Do nothing until the second time period expires and let The ONOFF pin is edge sensitive and activates on a falling the device power off by itself edge. It is normally pulled high. Shutdown Flag Asserted Shutdown if No Processor Communication 1st Period 2nd Period 1 0 Programmable Programmable Shutdown Delay Shutdown Delay 1st Period 2st Period Turn On During this time, the processor can abort the shutdown ON/OFF Pin can be released during this process or shutdown immediately before the 2nd period period without affecting the device response process elapses with an I2C command Figure 6. Hardware Power Up/Down Timing RST OUTPUT SIGNAL PIN a 10 ms current limit timer starts. The switcher will stay in this mode of operation until one of the following occurs: This is a power reset output signal. It is an open drain output that should be connected to the reset input of the • The current is reduced back to the normal level inside microprocessor. An external pull up resistor should be the 10 ms timer and in this case normal operation is connected to this output and is recommended to be pulled up gained back to V2 for best performance (If this pin is pulled up to the VIN pin, then the 1.0 µA shutdown current budget is not • The output reaches the thermal shutdown limit and guaranteed) turns off At power up, the RST pin is asserted (low) to keep the processor in “reset”. When VG, REG2, REG3, and REG4 are • The current limit timer expires without gaining normal all in regulation (both OV and UV flags for each regulator are operation at which point the output turns off. Then only de-asserted) and no faults exist, the RST output is de- for GrpB, at the end of a timeout period of 10 ms, the asserted after a 10 ms delay to take the processor out of output will attempt to restart again but for one time only. reset. Then the processor can go through its own internal power up sequence and can start communicating to the rest • The output current keeps increasing until it reaches the of the system. second overcurrent limit, see below for more details If ANY of the above four regulators has any of the following • A hard overcurrent limit (short circuit limit) that is higher faults: overtemperature, short-circuit, overcurrent for more than the cycle by cycle limit at which the device reacts by than 10 ms, overvoltage in response A, undervoltage in shutting down the output immediately. This is necessary to response A, or is shutting down normally, the RST output is prevent damage in case of a short-circuit. After that, only asserted to put the processor back in reset. If ANY of the GrpB will attempt a one time retry after a timeout period of above four regulators has an overvoltage response B fault or 10ms and will go through a new soft start cycle an undervoltage response B fault, the RST output will not be asserted (only the OV and UV flags will be available for the OUTPUT OVERVOLTAGE/UNDERVOLTAGE microprocessor to read). MONITORING THERMAL LIMIT DETECTION In the case of an output overvoltage/undervoltage, the user has two options that can be programmed through the There is a thermal sensor for each regulator except REG7. I2C interface: It uses an external MOSFET. Response A: The output will switch off automatically and the 34704 would alert the processor through I2C that such an CURRENT LIMIT MONITORING event happened. The current limit circuitry has two levels of current limiting: Response B: The output will not switch off. Rather the • A soft overcurrent limit (overcurrent limit): If the peak 34704 communicates to the processor that an overvoltage/ current reaches the typical overcurrent limit, the switcher undervoltage condition has occurred and wait for the will start a cycle-by-cycle operation to limit the current and 34704 Analog Integrated Circuit Device Data 30 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS processor decision to either shutoff or not, in the mean time The OV/UV fault flag is masked during DVS until the control loop will try to fix itself. DVSSTAT flag is asserted “Done”. To avoid erroneous conditions, a 20 μs filter will be To keep the RST output low during ramp up and until the implemented. soft start is done, the OV/UV protection is masked from reporting that the output is in regulation. LOGIC COMMANDS AND REGISTERS I2C USER INTERFACE The 34704 communicates via I2C using a default device reading or writing mode as shown in Figure 7 and Figure 8. address $54 to access all user registers and program all After each byte read or sent, the MC34704 answers with an regulators features independently. Physical address is in a 7- Acknowledge bit, indicating the bite was transferred bit format. The extra bit to complete the 8-bit indicates the successfully. 77 bbiitt PPhhyyssiiccaall AAddddrreessss ++ SSuubb--AAddddrreessss AACCKK AACCKK DDaattaa AACCKK ((ww)) bbiitt ((MMSSBB==00)) 11001100110000 ++ 00 00 00XXXXXXXXXXXXXX 00 XXXXXXXXXXXXXXXX 00 StartBit ACK ACK ACK EndBit 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 Figure 7. Writing sequence I2C bit stream   7 bit Physical ADD + Sub-address Physical ACK ACK RS ACK Data Read ACK (w) bit (MSB=1) ADD + (r) bit 1010100 + 0 0 1XXXXXXX 0 1 1010100 + 1 0 XXXXXXX 1 Start Bit ACK ACK ACK ACKEnd Bit 1 0 1 0 1 0 0 1 0 0 0 0 0 0 RS 1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 Figure 8. Reading sequence I2C bit stream USER PROGRAMMABLE REGISTERS and tied with REG6 and REG7 in a preset power sequence. By default, only REG6 and REG7 are involved in the power GrpC/E power sequencing setting (34704A Only) sequence and REG5 is independently controlled with GrpE. The microprocessor can choose one of several voltage 34704A assigns 2 bits to program the GrpC/E power sequence options for the GrpC/E supply (REG5), high sequencing options (CCDSEQ[1:0]). These bits value is voltage supply (REG6), and negative voltage supply (REG7). latched in at GrpC power up and will not be allowed to change For 3 of the sequencing options, REG5 supply is controlled unless a power recycle happens. OPTION MSB LSB GRPC/E ENABLED GRPC/E DISABLED 1 0 0 REG5 is independently controlled REG5 is independently controlled (Default) REG6 and REG7 ramp up together. REG6 and REG7 ramp down together 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 31

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS OPTION MSB LSB GRPC/E ENABLED GRPC/E DISABLED 2 0 1 REG5 ramps up first REG5, REG6 and REG7 ramp down together Then REG6 and REG7 ramp up together 3 1 0 REG5, REG6, and REG7 ramp up together REG5, REG6, and REG7 ramp down together 4 1 1 REG5 and REG6 ramp up together first. REG7 ramps down first. Then ramp up REG7 Then REG5 and REG6 ramp down together Switching frequency for REG6, 7 & 8 can decide whether to shutdown the output or not. In the mean time, the concerned output control loop will be F can be selected to be between 250 kHz and 1.0 MHz SW2 attempting to correct the error. in 250 kHz steps. On the 34704B, FSW2 is just for REG8 since REG6 and 7 do not exist in this device. See Output Overvoltage/Undervoltage Monitoring on page 30 for more details. 34704 assigns 2 bits to program F (F [1:0]) SW2 SW2 Response A and Response B share the same flag bit 34704 assigns 1 bit for this function (OVUVSETx) where x FSW2 MSB LSB corresponds to each regulator. 500kHz (Default) 0 0 250kHz 0 1 750kHz 1 0 OV/UV Response bit 1000kHz 1 1 A (Default) 0 B 1 Shutdown Hold (Delay) Time The 34704 assigns 2 bits (SDDELAY[1:0]) for the Dynamic Voltage Scaling for each regulator processor to program the shutdown delay time period The customer can adjust each regulator’s output dynamically with 2.5% step size. The total range of Shutdown Delay MSB LSB adjustability will vary depending on each regulator to accommodate different operating environments. Some 1.0sec (Default) 0 0 regulators will utilize the full range of -20.00% to +17.50% 0.5sec 0 1 and some regulators will only use the range of 10.00%. For details, see each regulator’s section. Each 2.5% step takes 1.5sec 1 0 50 s before moving to the next step. REG8 only performs 2.0sec 1 1 DVS when in voltage regulation mode. Please refer to the /ONOFF pin description for more During DVS, the Overvoltage and Undervoltage details monitoring will not be active. In addition to that, these faults will be masked and not active for a DVS settling time period Programming 34704 response to undervoltage/ equal to 1ms. This DVS settling time will start after the overvoltage conditions on each regulator DVSSTAT register is flagged indicating that the DVS cycle is There are two responses that can be programmed for an done. This is to ensure that during DVS and soft start alike overvoltage/undervoltage condition: the output will not be tripped due to a momentary overvoltage Response A: When an overvoltage (undervoltage) event is or undervoltage fault. This is the same for Response A and detected, the concerned output shuts down and a register is Response B of the overvoltage/undervoltage fault flagged to alert the processor. monitoring. Response B: When an overvoltage/undervoltage event is 34704 assigns 4 bits register to program the Dynamic detected, the concerned output will not shutdown, but the Voltage Scaling for each regulator (DVSSETx[3:0]) where x register is flagged to alert the processor. Then, the processor corresponds to each regulator. 34704 Analog Integrated Circuit Device Data 32 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Here is how the SSTIME bits interacts with the SSSETx register bits: Percentage Change MSB LSB 1. SSTIME is set by a value read through the SS pin. 0.00% (Default) 0 0 0 0 2. SSTIME is copied into the bits SSSET5, SSSET6, +2.50% 0 0 0 1 SSSET7, and SSSET8. +5.00% 0 0 1 0 3. The soft start time of REG2, REG3, and REG4 are only affected by the value of SSTIME bits. +7.50% 0 0 1 1 4. The soft start time of REG5, REG6, REG7, and REG8 +10.00% 0 1 0 0 are affected by the value of bits SSSET5, SSSET6, +12.50% 0 1 0 1 SSSET7, and SSSET8 respectively. +15.00% 0 1 1 0 34704 assigns 2 bits to store the value programmed by the SS pin. Bits SSTIME[1:0] can only be read by the user. +17.50% 0 1 1 1 -20.00% 1 0 0 0 Soft Start MSB LSB -17.50% 1 0 0 1 0.5ms 0 0 -15.00% 1 0 1 0 2ms 0 1 -12.50% 1 0 1 1 8ms 1 0 -10.00% 1 1 0 0 32ms 1 1 -7.50% 1 1 0 1 34704 assigns 2 bits for REG5 through REG8 to program -5.00% 1 1 1 0 the soft start times for these regulators (SSSETx[1:0]) where -2.50% 1 1 1 1 x corresponds to each regulator from REG5 through REG8. On/Off Control for each group of regulators as defined Soft Start MSB LSB previously and for the whole IC 0.5ms 0 0 34704 assigns 1 bit per group to turn each group on/off (ONOFFA, C, D, or E bits). Please note that GrpB does not 2ms 0 1 have a dedicated enable register which is enabled by default. 8ms 1 0 32ms 1 1 GrpA, C, D, or E ONOFF bit REG8 Regulation Mode OFF (Default) 0 The 34704 assigns 1 bit to indicate REG8’s regulation ON 1 mode (REG8MODE). The processor assigns this bit to either Also, 34704 assigns 1 bit (ALLOFF) for disabling the whole regulation mode before enabling the REG8 output. IC through the I2C. (ALLOFF bit) REG8 Regulation bit ALL OFF bit Current (Default) 0 False (Default) 0 Voltage 1 True 1 When REG8 is current regulated, LED backlight current Soft Start Time can be reduced from the maximum in 16 steps through There are two set of bits for setting the soft start value for the I2C interface all of the regulators except REG1. The SSTIME[1:0] bits The maximum LED current can be set using the external reads the soft start value set by the SS pin and is used to resistor at the bottom of the LED string, then through I2C initially set the soft start value for all of the regulators except programming, this current value can be reduced in 16 steps. REG1. Then, the SSSET bits for REG5 through REG8 can be 34704 assigns 4 bits for this function (ILED[3:0]) used to change the soft start value for these regulators from the value set by the SSTIME. The ILED setting is not a guaranteed characteristic from I * (1/16) to I * (9/16), due to an error amp common MAX MAX mode limitation. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 33

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Dynamic Voltage Scaling Status Flag LED Current MSB LSB In addition and for each regulator, 34704 assigns 1 bit (DVSSTATx) to flag to the processor that the desired output I * (1/16) 0 0 0 0 MAX voltage level set with the DVSSETx bits has been reached. I * (2/16) 0 0 0 1 MAX IMAX * (3/16) 0 0 1 0 DVS STATUS bit IMAX * (4/16) 0 0 1 1 DVS Not Done 0 IMAX * (5/16) 0 1 0 0 DVS Done 1 I * (6/16) 0 1 0 1 MAX USER ACCESSIBLE FAULT REGISTERS I * (7/16) 0 1 1 0 MAX IMAX * (8/16) 0 1 1 1 Overcurrent Fault Register IMAX * (9/16) 1 0 0 0 The 34704 assigns 1 bit for each regulator (ILIMFx) to indicate a fault due to overcurrent limit, where x corresponds I * (10/16) 1 0 0 1 MAX to each regulator from REG1 to REG8, except REG7 I * (11/16) 1 0 1 0 MAX I * (12/16) 1 0 1 1 MAX ILIMF bit I * (13/16) 1 1 0 0 MAX False 0 I * (14/16) 1 1 0 1 MAX True 1 I * (15/16) 1 1 1 0 MAX Short-circuit Fault Register I (Default) 1 1 1 1 MAX The 34704 assigns 1 bit for each regulator (SCFx) to ACCURATE I2C COMMUNICATION MODE indicate a fault due to short-circuit current limit, where x The 34704 assigns 1 bit to enable the Accurate I2C corresponds to each regulator from REG1 to REG8, except REG7 communication mode (ACCURATE). Setting this bit enables the Accurate mode in which each command and data should be sent 2 times to avoid false commands. SCF bit False 0 USER ACCESSIBLE FLAG REGISTERS True 1 Cold Start Flag Overvoltage Fault Register The 34704 assigns 1 bit (COLDF) to flag the processor that the power up was a result of battery insertion and not The 34704 assigns 1 bit for each regulator (OVFx) to through ONOFF pin. This flag should be cleared after power indicate a fault due to overvoltage limit, where x corresponds up by the processor. to each regulator from REG1 to REG8 Cold Start Flag bit OVF bit /ONOFF (Default) 0 False 0 Battery Insertion 1 True 1 Shutdown Flag Undervoltage Fault Register The 34704 assigns 1 bit (SHUTDOWN) to flag the The 34704 assigns 1 bit for each regulator (UVFx) to processor if a shutdown signal is received through the indicate a fault due to undervoltage limit, where x ONOFF pin and a programmable time period with a default of corresponds to each regulator from REG1 to REG8. 1sec has elapsed. UVF bit /ONOFF Status bit False 0 Normal (Default) 0 True 1 Shutdown 1 Thermal Shutdown Fault Register 34704 Analog Integrated Circuit Device Data 34 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS The 34704 assigns 1 bit for each regulator (TSDFx) to REG7 Independent ON/OFF Control (Only on 34704A) indicate a fault due to thermal limit, where x corresponds to The 34704B provide two register to independently turn on each regulator from REG1 to REG8, except REG7 REG7 when REG6 is not needed. Care must be taken when turning on REG7 to avoid inrush currents during regulator ramp-up. Following Process must be followed to assure TSDF bit successful turn on of REG7. False 0 1. Set EN0 and clear DISCHR_B on REG7CR0 register True 1 2. After 1ms or more, set EN1 on REG7CR0 register Regulator Fault Register 3. Set REG7DAC register to $00 4. Gradually shift up REG7DAC register from $00 to $D9 The 34704 assigns 1 bit for each regulator (FAULTx) to to ramp-up the output voltage in a soft-start like wave. indicate that a fault had occurred on each regulator. The Soft start timing is dependant of I2C communication processor can just access this register periodically to speed and number of bit you change per writing, for determine system status. This reduces the access cycles. If instance use 4,8 or 16 bits increase to ramp up the a regulator fault register asserted, then the processor can output voltage. access that regulator’s registers to see what kind of fault had occurred. Register Address Code 1 $58 $50 2 $58 $D0 FAULT bit 3 $59 $00 False 0 4 $59 $04 True 1 5 $59 $08 SPECIAL REGISTERS 6 $59 $0C ... ... ... REG3 Fine Voltage Scaling Register Regulator 3 has an additional fine output voltage scaling 55 $59 $D9 that enables to lower the output voltage in 0.5% steps. The 34704 assigns an 8-bit register (REG3DAC) to the REG3 REG7 independent start up example Digital to analog converter for the FB3 voltage generation. Output votlage must be reduced gradually to avoid a OV/UV fault to occur. REGISTER DESCRIPTION SUMMARY TABLE Register ADDR R/W Bit Name Bits Description R/W CCDSEQ 1:0 GrpC/E power sequence selection GENERAL1 $01 SDDELAY 3:2 Hard shutdown delay timer selection R/W ONOFFx 3:0 GrpA,C,D,E On/off bits GENERAL2 $02 ALLOFF 4 Soft shutdown bit (turn off all regulators) R SSTIME 1:0 Soft start configuration latch GENERAL3 $03 R/W COLDF 3 Cold power up detection flag R/W SHTD 4 Hard Shutdown detection flag R/W OVUVSET1 0 Set REG1/VG response type to OV/UV VGSET1 $04 R/W DVSSET1 4:1 REG1 DVS value setting R DVSSTAT1 0 DVS voltage level status flag VGSET2 $05 R - 5:1 REG1 fault flags: Thermal SD, SC, ILim, UV and OV R/W OVUVSET2 0 Set REG2 response type to OV/UV REG2SET1 $06 R/W DVSSET2 4:1 REG2 DVS value setting 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 35

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Register ADDR R/W Bit Name Bits Description R DVSSTAT2 0 DVS voltage level status flag REG2SET2 $07 R - 5:1 REG2 fault flags: Thermal SD, SC, ILim, UV and OV R/W OVUVSET3 0 Set REG3 response type to OV/UV REG3SET1 $08 R/W DVSSET3 4:1 REG3 DVS value setting R DVSSTAT3 0 DVS voltage level status flag REG3SET2 $09 R - 5:1 REG3 fault flags: Thermal SD, SC, ILim, UV and OV R/W OVUVSET4 0 Set REG4 response type to OV/UV REG4SET1 $0A R/W DVSSET4 4:1 REG4 DVS value setting R DVSSTAT4 0 DVS voltage level status flag REG4SET2 $0B R - 5:1 REG4 fault flags: Thermal SD, SC, ILim, UV and OV R/W OVUVSET5 0 Set REG5 response type to OV/UV REG5SET1 $0C R/W DVSSET5 4:1 REG5 DVS value setting REG5SET2 $0D R/W SSSET5 1:0 REG5 Soft Start setting. R DVSSTAT5 0 DVS voltage level status flag REG5SET3 $0E R - 5:1 REG5 fault flags: Thermal SD, SC, ILim, UV and OV R/W OVUVSET6 0 Set REG6 response type to OV/UV REG6SET1 $0F R/W DVSSET6 4:1 REG6 DVS value setting REG6SET2 $10 R/W SSSET6 1:0 REG6 Soft Start setting. R DVSSTAT6 0 DVS voltage level status flag REG6SET3 $11 R - 5:1 REG6 fault flags: Thermal SD, SC, ILim, UV and OV R/W OVUVSET7 0 Set REG7 response type to OV/UV REG7SET1 $12 R/W DVSSET7 4:1 REG7 DVS value setting R/W SSSET7 1:0 REG7 Soft Start setting. REG7SET2 $13 R/W FSW2 3:2 REG6, 7 8, Frequency setting R DVSSTAT7 0 DVS voltage level status flag REG7SET3 $14 R - 2:1 REG7 fault flags: UV and OV R/W OVUVSET8 0 Set REG8 response type to OV/UV REG8SET1 $15 R/W DVSSET8 4:1 REG8 DVS value setting R/W SSSET8 1:0 REG8 Soft Start setting. REG8SET2 $16 R/W REG8MODE 3:2 Voltage or Current Regulation mode on REG8 R/W ILED 6:4 LED string current configuration during current regulation mode R DVSSTAT8 0 DVS voltage level status flag REG8SET3 $17 R - 5:1 REG8 fault flags: Thermal SD, SC, ILim, UV and OV FAULTS $18 R FLTx 7:0 First Level fault register for REG1 through REG8 I2CSET1 $19 R/W ACCURATE 0 Accurate I2C communication mode enable REG3DAC $49 R/W 3DACx 7:0 REG3 DAC reference voltage configuration for Fine voltage Scaling R/W DISCHG_B 4 Discharge enable for independent REG7 Control REG7CR0 $58 R/W EN 7:6 Output Enable bits for Independent REG7 Control REG7DAC $59 R/W 7DACx 7:0 REG7 DAC refence voltage configuration for REG7 Control 34704 Analog Integrated Circuit Device Data 36 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS I2C REGISTER DISTRIBUTION There are also the IC general use registers. Those registers are also split between status reporting registers and Each regulator has a fault register that records any fault processor programmable registers. that occurs in that regulator. Then there is a regulator fault reporting register that the processor can access at all times This distribution keeps each regulator’s registers bundled to see if any fault had occurred. together which makes it easier for the user to access one regulator at a time. Addr Name D7 D6 D5 D4 D3 D2 D1 D0 $00 Reserved - $01 GENERAL1 - SDDELAY[1:0] CCDSEQ[1:0] $02 GENERAL2 - ALLOFF ONOFFA ONOFFC ONOFFD ONOFFE $03 GENERAL3 - SHTD COLDF - SSTIME[1:0] $04 VGSET1 - DVSSET1[3:0] OVUVSET1 $05 VGSET2 - TSDF1 SCF1 ILIMF1 UVF1 OVF1 DVSSTAT1 $06 REG2SET1 - DVSSET2[3:0] OVUVSET2 $07 REG2SET2 - TSDF2 SCF2 ILIMF2 UVF2 OVF2 DVSSTAT2 $08 REG3SET1 - DVSSET3[3:0] OVUVSET3 $09 REG3SET2 - TSDF3 SCF3 ILIMF3 UVF3 OVF3 DVSSTAT3 $0A REG4SET1 - DVSSET4[3:0] OVUVSET4 $0B REG4SET2 - TSDF4 SCF4 ILIMF4 UVF4 OVF4 DVSSTAT4 $0C REG5SET1 - DVSSET5[3:0] OVUVSET5 $0D REG5SET2 - SSSET5[1:0] $0E REG5SET3 - TSDF5 SCF5 ILIMF5 UVF5 OVF5 DVSSTAT5 $0F REG6SET1 - DVSSET6[3:0] OVUVSET6 $10 REG6SET2 - SSSET6[1:0] $11 REG6SET3 - TSDF6 SCF6 ILIMF6 UVF6 OVF6 DVSSTAT6 $12 REG7SET1 - DVSSET7[3:0] OVUVSET7 $13 REG7SET2 - FSW2[1:0] SSSET7[1:0] $14 REG7SET3 - UVF7 OVF7 DVSSTAT7 $15 REG8SET1 - DVSSET8[3:0] OVUVSET8 $16 REG8SET2 - ILED[3:0] REG8MODE SSSET8[1:0] $17 REG8SET3 - TSDF8 SCF8 ILIMF8 UVF8 OVF8 DVSSTAT8 $18 FAULTS FLT8 FLT7 FLT6 FLT5 FLT4 FLT3 FLT2 FLT1 $19 I2CSET1 - ACCURATE $49 REG3DAC 3DAC7 3DAC6 3DAC5 3DAC4 3DAC3 3DAC2 3DAC1 3DAC0 $58 REG7CR0 EN[1:0] - DISCHG_B - $59 REG7DAC 7DAC7 7DAC6 7DAC5 7DAC4 7DAC3 7DAC2 7DAC1 7DAC0 34704A Register Distribution Map 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 37

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Addr Name D7 D6 D5 D4 D3 D2 D1 D0 $00 Reserved - $01 GENERAL1 - SDDELAY[1:0] - $02 GENERAL2 - ALLOFF - - ONOFFD ONOFFE $03 GENERAL3 - SHTD COLDF - SSTIME[1:0] $04 Reserved - $05 VGSET2 - - - - UVF1 OVF1 - $06 REG2SET1 - DVSSET2[3:0] OVUVSET2 $07 REG2SET2 - TSDF2 SCF2 ILIMF2 UVF2 OVF2 DVSSTAT2 $08 REG3SET1 - DVSSET3[3:0] OVUVSET3 $09 REG3SET2 - TSDF3 SCF3 ILIMF3 UVF3 OVF3 DVSSTAT3 $0A REG4SET1 - DVSSET4[3:0] OVUVSET4 $0B REG4SET2 - TSDF4 SCF4 ILIMF4 UVF4 OVF4 DVSSTAT4 $0C REG5SET1 - DVSSET5[3:0] OVUVSET5 $0D REG5SET2 - SSSET5[1:0] $0E REG5SET3 - TSDF5 SCF5 ILIMF5 UVF5 OVF5 DVSSTAT5 $0F- Reserved - $12 $13 FSW2SET - FSW2[1:2] - $14 Reserved - $15 REG8SET1 - DVSSET8[3:0] OVUVSET8 $16 REG8SET2 - ILED[3:0] REG8MODE SSSET8[1:0] $17 REG8SET3 - TSDF8 SCF8 ILIMF8 UVF8 OVF8 DVSSTAT8 $18 FAULTS FLT8 - - FLT5 FLT4 FLT3 FLT2 FLT1 $19 I2CSET1 - ACCURATE $49 REG3DAC DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 $58 REG7CR0 EN[1:0] - DISCHG_B - $59 REG7DAC 7DAC7 7DAC6 7DAC5 7DAC4 7DAC3 7DAC2 7DAC1 7DAC0 34704B Register Distribution Map 34704 Analog Integrated Circuit Device Data 38 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION COMPONENT CALCULATION F AND GENERAL SOFT START SW1 CONFIGURATION Soft Start timing Ratio The 34704 uses F as the switching frequency for [ms] SW1 REG1(VG) thru REG5, and this can be changed by applying a voltage between 0 to 2.5 V to the FREQ pin. If the FREQ 0 0.5 pin is left unconnected, the 34704 starts up with a default frequency of 750 KHz. To configure the FSW1, use a 2 11/32 2.0 resistors voltage divider from VDDI to ground to set the voltage on the FREQ pin as indicated bellow: 19/32 8.0 VDDI 32.0 F Ratio SW1 I max = 100 [KHz] DD 0 750 V = V -----------R----S----S----2------------ 9/32 1000 VDDI SS DDIRSS1+RSS2 RSS1 RSS1, RSS2 tolerance  13/32 1250 VSS SS 17/32 1500 RSS2 GND 21/32 1750 VDDI 2000 REGULATORS POWER STAGE AND COMPENSATION CALCULATION Notes 27. If an external voltage is used, FSW1 can only be set during Regulator 1 and 6 (Synchronous Boost - internally device startup. compensated - REG1 is VG supply). REG1 is a Synchronous Boost converter set to 5.0 V and Maximum current of 500 mA while REG6 is set to 15 V at V = V ---------R-----F---2----------- 60 mA (on the 34704B, REG1 does not exist but similar VDDI FREQ DDIRF1+RF2 circuitry is used to provide the internal VG voltage). They do RF1 RF1, RF2 tolerance  not need an external compensation network, thus, the only components that need to be calculated are: VFREQ FREQ • R1 and RB (Only REG6): These two resistors help to set RF2 the output voltage to the desire value using a Vref=0.6 V, GND select R1 between 10 k and 100 K and then calculate RB as follows: Initially at power up, the soft start time will be set for all of the regulators through programming the SS pin with an R1 RB = --------------------- external resistor divider connected between VDDI and AGND Vo [] ------------–1 as follows: Vref • L: A boost power stage can be designed to operate in CCM for load currents above a certain level usually 5 to 15% of full load. The minimum value of inductor to maintain CCM can be determined by using the following procedure: 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 39

FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION 1. Define I as the minimum current to maintain CCM as regulators may work as a buck or a boost depending on the OB 15% of full load. operating voltages, they need to be compensated in different ways for each situation. Since the 34704 is meant to work using a LiIon battery, the 2 operating input voltage range is set from 2.7 - 4.2 V, then the LminV-----o------D----2----I-1-----–-----D---------T--- (H) following scenarios are possible: OB where: D = Dutycycle Vo = Output Voltage Regulator Vo Input voltage Operation T = Switching Period range IOB = Boundary Current to achieve CCM 2. However the worst case condition for the boost power 2 2.8 V 3.0 - 4.2 Buck stage is when the input voltage is equal to one half of the output voltage, which results in the Maximum I , 3.3 V 2.7 - 3.0 Boost L then: 3.3 V 3.5 - 4.2 Buck 4 1.8 V 2.7 - 4.2 Buck L V-----o------T----- (H) min 16I OB 2.5 V 2.7 - 4.2 Buck Note: On the 34704B Use the recommended 3.0uH 5 3.3 V 2.7 - 3.0 Boost inductor rated between 50 to 100 mA in order to have this regulator working in DCM. Rising the inductor value will make 3.3 V 3.5 - 4.2 Buck the regulator to begin working in CCM. • C : The three elements of output capacitor that OUT contribute to its impedance and output voltage ripple are • NOTE: Since these 3 regulators can work as a buck or a the ESR, the ESL and the capacitance C. The minimum boost in a single application, a good practice to configure capacitor value is approximately: these regulators is to compensate for a boost scenario and then verify that the regulator is working in buck mode using that same compensation. Io D C ------m----a--x--------m----a--x-- (F) OUT FswVo Compensating for Buck operation: r • L: A buck power stage can be designed to operate in CCM where: Dmax = Maximum Dutycycle for load currents above a certain level usually 5 to 15% of FSW = Switching Frequency full load. The minimum value of inductor to maintain CCM • Where VOis the desired output voltage ripple. can be determined by using the following procedure: r 1. Define I as the minimum current to maintain CCM OB • Now calculate the maximum allowed ESR to reach the between 10 to 15% of full load. desired VO. r Vo+Io R +R D T max DSONLSFET L min Vo L -----------------------------------------------------------------------------------------------------------------------D T-------------- min 2I MAX 2I Vo OB OB ESR---------------------------r---------------- [] [H] Io ----------m----a---x-----+I  1–D OB max where: RDSONLSFET = Body Resistance of the Lowside Fet RL = Inductor Winding Resistance • 1CVG (Only Reg1): Use a 47uF capacitor from Ground to D'Min = Minimum Off Percentage given by 1- (Vin_min/Vout_max) VG. D'max = Maximum Off Percentage given by 1- (Vin_max/Vout_min) • D1 (Only Reg1): Use a fast recovery schottky diode rated to 10V at 1A. • COUT: The three elements of output capacitor that contribute to its impedance and output voltage ripple are Regulator 2, 4 and 5 (Synchronous Buck-Boost regulator the ESR, the ESL and the capacitance C. A good with external compensation) approach to calculate the minimum real capacitance needed is to include the transient response analysis to These three regulators are 4-Switch synchronous buck- control the maximum overshoot as desired. boost voltage mode control DC-DC regulator that can operate at various output voltage levels. Since each of the 34704 Analog Integrated Circuit Device Data 40 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION 1. First calculate the dt_I (inductor current rising time) • R1 and RB: These two resistors help to set the output given by: voltage to the desire value using a Vref=0.6 V, select R1 between 10 k and 100 K and then calculate RB as follows: dtI = --I--o---m----a---x--T---- [s] R1 Iostep RB = --------------------- Vo [] Where the parameter Io_step is the maximum current V-----r---e---f-–1 step during the current rising time and is define as: • Compensation network. (C1,C2,C3, R2, R3): For compensating a buck converter, 3 important frequencies D Vin –Vo [A] referring to the plant are: Iostep = -----m----a--x------------m----i--n--------------- Fsw L  1. Output LC filter cutoff frequency (FLC): 2. Then the output capacitor can be chosen as follow: 1 F = -------------------------- [Hz] LC C I---o---m----a--x---d----t---I [A] 2 LCOUT OUT Vo 2. Cutoff frequency due to capacitor ESR: max • Where VO is the maximum allowed transient 1 max F = -------------------------------------- [Hz] overshoot expressed as a percentage of the output ESR 2C ESR OUT voltage, typically from 3 to 5% of Vo. 3. Crossover frequency (or bandwidth): 3. Finally find the maximum allowed ESR to allow the desired transient response: F = F----S---W--- [Hz] BW 10 Vo FswL ESRmax = --V-----o-----r-1----–-----D---------------- [] The Type 3 external compensation network will be in min charge of canceling some of these poles and zeros to NOTE: Do not use the parameters VO and VO achieve stability in the system. The following poles and r max indistinctly, the first one indicates the output voltage ripple, zeroes frequencies are provided by the type 3 compensation. while the second one is the maximum output voltage overshoot (transient response). 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 41

FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION F = F F = 0.9F F = 1.1F PO BW Z1 LC Z2 LC F F = F F = ----S---W--- P1 ESR P2 2 The passive components associated to these frequencies are calculated with the following formulas. C1 = -V-----i--n---m----i--n---------------1--------------- V 2F R1 RAMP PO C2 = -------------1--------------- 2F R1 Z2 R2 = -------------1--------------- 2F C1 Z1 R3 = -------------1--------------- 2F C2 P1 C3 = -------------1--------------- 2F R2 P2 On the 34704 V is half of 1.2 V since each operation mode spends only half the ramp. RAMP 34704 Analog Integrated Circuit Device Data 42 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION Compensating for boost operation: R1 • L: A boost power stage can be designed to operate in RB = ----------------------- [] Vo CCM for load currents above a certain level usually 5 to -------------–1 V 15% of full load. The minimum value of inductor to REF maintain CCM can be determined by using the following procedure: • Compensation network. (C1,C2,C3, R2, R3) 1. Define I as the minimum current to maintain CCM OB For compensating a boost converter, 4 important between 10 to 15% of full load: frequencies referring to the plant are: 1. Output LC filter cutoff frequency (F ): LC VoD1–D2T [H] L ------------------------------------------ min 2I OB D However the worst case condition for the boost power FLC = -------------m----i-n-------- [Hz] 2 LC stage is when the input voltage is equal to one half of the OUT output voltage, which results in the Maximum I , then: L • Where D’ is the minimum off time percentage given min by: VoT L ---------------- [H] min 16I OB Vin • COUT: The three elements of output capacitor that D = ------------m----i--n---- contribute to its impedance and output voltage ripple are min Vout max the ESR, the ESL and the capacitance C. The minimum capacitor value is approximately: 2. Cutoff frequency due to capacitor ESR: COUTI--F-o---sm---w-a--x---D--V---m--o--a--x-- [F] FESR = 2----------C----O----U1----T-----E----S----R--- [Hz] r 3. The right plane zero frequency: • Where VO is the desired output voltage ripple. r • Now calculate the maximum allowed ESR to reach the 2 D  R [Hz] desired VOr: RHPZ = ---------m----i--n2-------L-----L---O----A----D-- 4. Crossover frequency (or bandwidth): select this Vo frequency as far away form the RHP as much as ESR---------------------------r---------------- Z ----I---o---m----a--x------+I  [] possible: 1–D OB max • R1 and RB: F «R-----H-----P---Z-- [Hz] These two resistors help to set the output voltage to the BW 6 desire value using a Vref=0.6V, select R1 between 10k and The Type 3 external compensation network will be in 100K and then calculate RB as follows: charge of canceling some of these poles and zeros to achieve stability in the system. The following poles and zeroes frequencies are provided by the type 3 compensation: F = F F = 0.9F F = 1.1F PO BW Z1 LC 22 LC F F = F F = ----S---W--- P1 ESR 2P 2 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 43

FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION The passive components associated to these frequencies are calculated with the following formulas C1 = -V-----i--n---m----i--n--------1-----------------------1--------------- VRAMPD 22FPOR1 min C2 = -------------1--------------- 2F R1 Z2 R2 = -------------1--------------- 2F C1 Z1 R3 = -------------1--------------- 2F C2 P1 C3 = -------------1--------------- 2F R2 P2 On the 34704 V is half of 1.2 V since each operation mode spends only half the ramp. RAMP Regulator 3 (Synchronous Buck - internally • Then the output capacitor can be chosen as follow: compensated) • L: A buck power stage can be designed to operate in CCM for load currents above a certain level usually 5 to 15% of C I---o---m----a--x---d----t--I- [F] full load. The minimum value of inductor to maintain CCM OUT Vo max can be determined by using the following procedure: Where VO is the maximum allowed transient max 1. Define I as the minimum current to maintain CCM OB overshoot expressed as a percentage of the output voltage, between 10 to 15% of full load. typically from 3 to 5% of Vo. • Finally find the maximum allowed ESR to allow the L ---V-----o----+-----I--o----m----a--x------R----D---S---O----N----L---S---F---E---T-----+-----R----L--------D------m----i--n-----T--- desired transient response: min 2I OB Vo [H] L DT------------ Vo FswL [] min 2I ESR = ------------r------------------------- OB max Vo1–D  min • C : The three elements of output capacitor that coOnUtrTibute to its impedance and output voltage ripple are NOTE: do not use the parameters VOR and VOmax the ESR, the ESL and the capacitance C. A good indistinctly, the first one indicates the output voltage rip- approach to calculate the minimum real capacitance ple, while the second one is the maximum output volt- needed is to include the transient response analysis to age overshoot (transient response). control the maximum overshoot as desired. • R1 and RB: These two resistors help to set the output • First calculate the dt_I (inductor current rising time) voltage to the desire value using a VREF=0.6 V, select R1 given by: between 10 k and 100 K and then calculate RB as follows: dtI = -I---o---m----a--x---T---- [s] RB = ---V----R-o----1--------- [] Iostep ------------–1 Vref Where the parameter IO step is the maximum current _ step during the current rising time and is define as: Regulator 8 (Synchronous Boost - internally compensated -Voltage or current feedback) D Vin –Vo [A] Iostep = -----m----a--x------------m----i--n--------------- REG8 is a Synchronous Boost converter set to 15V with a Fsw L  maximum current of 30 mA and can be used with voltage 34704 Analog Integrated Circuit Device Data 44 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION feedback using the standard voltage divider configuration, or controls the amount of current flowing through it. To can be programmed to work with a current feedback calculate this resistor, set the maximum current you want configuration to control the current flowing through a LED to flow though the string and use the following formula: string. It does not need external compensation network, thus the only components that need to be calculated are: • L: A boost power stage can be designed to operate in RS = V-----r--e---f [] CCM for load currents above a certain level usually 5 to Io 15% of full load. The minimum value of inductor to Where V =230 mV is the maximum internal reference maintain CCM can be determined by using the following REF voltage in current mode control that is reflected on the FB8 procedure: pin. When Input voltage is equal to or higher than VOUT8, a • Define I between 60 to 80% of the maximum current OB reverse bias diode is needed from the switching node to the rating to maintain CCM as 15% of full load: output in order to cause a drop from the Input to the output, see Figure 9 below: 2 L V-----o------D---------1-----–-----D---------T--- [H] min 2IOB VIN BT8 However the worst case condition for the boost power CBOOT stage is when the input voltage is equal to one half of the L8 output voltage, which results in the Maximum ÄIL, then: SW8 D8 VOUT8 VOUT8 L V-----o------T----- [H] min 16I R1 OB FB8 • C : The three elements of output capacitor that OUT RB contribute to its impedance and output voltage ripple are the ESR, the ESL and the capacitance C. The minimum capacitor value is approximately: Figure 9. Reverse Bias Diode C I---o---m----a--x---D-----m----a--x-- [F] Regulator 7 (Inverter controller - external compensation OUT FswVo needed) r REG7 is a non-synchronous buck/boost inverting PWM • Where VO is the desired output voltage ripple. voltage-mode control DC-DC regulator that drive an external r P-MOSFET to supply a typical voltage of -7.0 V at a • Now calculate VO the maximum allowed ESR to maximum current of 60 mA. r reach the desired. • P-MOSFET: The peak current of the MOSFET is assumed to be I , which is obtained by the following formula, define D I between 60 to 80% of the maximum current rating. OB Vo [] ESR---------------------------r---------------- Io 1-----–----D-m----ma--x--a--x--+IOB I I = –------I---o----+-----I--O----B---- Q Lpeak 1–D • R1 and RB (for Voltage feedback control): These two And the voltage rating is given by: resistors help to set the output voltage to the desire value using a V =0.6 V, select R1 between 10k and 100K and REF then calculate RB as follows: V = Vin–Vo Q • Diode D7: The peak value of the diode current is I FSM which should also be higher than I . The average R1 [] Lpeak RB = --------------------- current rating should be higher than the output current low Vo ------------–1 and the repetition reverse voltage V is given by: Vref RRM • RS (For current feedback control with LED string): This resistor is attached at the end of the LED string and it 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 45

FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION • Output LC filter cutoff frequency (F ): LC V Vin–Vo RRM • L: The minimum value of inductor to maintain CCM can be D determined by using the following procedure: F = -------------m----i-n-------- [Hz] LC 2 LC OUT Lmin2--–--I-V-o----o---T----V-----o--V---–--i--nV---m--i--ni--n--------2 [H] Where D’min is the minimum off time percentage given by: max min • C : The three elements of output capacitor that OUT Vin contribute to its impedance and output voltage ripple are D = --------------m----i--n----- min Vout the ESR, the ESL and the capacitance C. The minimum max capacitor value is approximately: C I---o---m----a---x--D-----m----a--x-- [F] • Cutoff frequency due to capacitor ESR: OUT F Vo SW r F = ------------------1-------------------- [Hz] • Where VO is the desired output voltage ripple. ESR 2C ESR r OUT • Now calculate the maximum allowed ESR to reach the desired. • The right plane zero frequency: 2 D  R RHP = ---------m----i--n------------L---O----A----D-- [Hz] Z D2L Vo ESR------------------------------r------------------ [] Io I • Crossover frequency (or bandwidth): select this ----------m----a--x------+-----O----B---- 1–D 1–D frequency as far away form the RHPZ as much as max possible: RHP • R1 and RB: These two resistors help to set the output F «-------------Z-- [Hz] BW 6 voltage to the desire value using a V 7=0.6V, select R1 FB between 10 k and 150 K and then calculate RB as follows: The Type 3 external compensation network will be in charge of canceling some of these poles and zeros to achieve stability in the system. The following poles and 0.9 RB = ----------------------------------R1 [] zeroes frequencies are provided by the type 3 compensation: 1.5–Vo–0.9 NOTE: RB is not grounded, instead is connected to VREF7 pin (VREF7=1.5 V) which provide a positive voltage F = F F = 0.9F F = 1.1F PO BW Z1 LC 22 LC to assure a positive voltage at the FB7 pin. F F = F F = ----S---W--- P1 ESR 2P 2 • Compensation network. (C1,C2,C3, R2, R3) For compensating a buck converter, 4 important frequencies referring to the plant are: 34704 Analog Integrated Circuit Device Data 46 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION The passive components associated to these frequencies are calculated with the following formulas. C1 = -V-----i--n---m----i--n--------1-----------------------1--------------- VRAMPD 22FPOR1 min C2 = -------------1--------------- 2F R1 Z2 R2 = -------------1--------------- 2F C1 Z1 R3 = -------------1--------------- 2F C2 P1 C3 = -------------1--------------- 2F R2 P2 On the 34704 V is half of 1.2 V since each operation mode spends only half the ramp. RAMP 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 47

TYPICAL APPLICATIONS TYPICAL APPLICATIONS VIN VIN 34704A (19) VOUT1 REG8 V1 V8 VG VG SW8 SW1 REG8 BT8 BT1 BT2D VIN FB8 PVIN2 VIN SW2D VOUT7 VOUT2 V2 DRV7 V7 REG2 SW2U REG7 BT2U FB7 FB2 COMP2 VREF7 COMP7 BT3 VIN PVIN3 VIN VOUT6 SW3 V6 REG3 SW6 REG6 VOUT3 V3 BT6 FB3 FB6 VIN VIN BT4D BT5D PVIN4 PVIN5 SW4D SW5D VOUT4 VOUT5 V4 V5 REG4 SW4U SW5U REG5 BT4U BT5U FB4 FB5 COMP4 COMP5 VDDI VIN VBUS ONOFF SCL VIN VIN VDDI SDA V2 FREQ RST SS VIN VIN AGND PGND (EXPAD) Notes (18) 18. AGND(S) & PGND(S) SHOULD BE CONNECTED TOGETHER AS CLOSE TO THE IC AS POSSIBLE 19. REFER TO THE FB8 FUNCTIONAL PIN DESCRIPTION ON PAGE 17. 34704 Analog Integrated Circuit Device Data 48 Freescale Semiconductor

TYPICAL APPLICATIONS Figure 10. 34704A Typical Application Diagram VIN VIN 34704B (21) REG8 VG SW8 VG SW1 BT8 REG8 BT1 FB8 VIN PVIN2 VIN BT2D PVIN5 SW2D BT5D SW5D VOUT2 V2 VOUT5 V5 REG2 SW2U REG5 SW5U BT2U FB2 BT5U COMP2 FB5 COMP5 VIN PVIN3 VIN BT3 PVIN4 SW3 BT4D SW4D REG3 V4 VOUT4 VOUT3 V3 REG4 FB3 SW4U BT4U VIN FB4 COMP4 ONOFF VDDI VIN VBUS VIN SCL VIN SDA FREQ V2 SS RST VIN VIN AGND PGND (EXPAD) (20) Notes 20. AGND(S) & PGND(S) SHOULD BE CONNECTED TOGETHER AS CLOSE TO THE IC AS POSSIBLE 21. REFER TO THE FB8 FUNCTIONAL PIN DESCRIPTION ON PAGE 17. Figure 11. 34704B Typical Application Diagram 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 49

PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. 34704 Analog Integrated Circuit Device Data 50 Freescale Semiconductor

PACKAGING PACKAGE DIMENSIONS (CONTINUED) PACKAGE DIMENSIONS (CONTINUED) 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 51

PACKAGING PACKAGE DIMENSIONS (CONTINUED) PACKAGE DIMENSIONS (CONTINUED) 34704 Analog Integrated Circuit Device Data 52 Freescale Semiconductor

REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 2.0 4/2008 • Initial Release 3.0 6/2008 • Revised 34704 Simplified Application Diagram on page 1 • Revised 34704 Internal Block Diagram on page 3 • Revised 34704 Pin Definitions on page 4 • Revised 34704A Typical Application Diagram on page 49 and 34704B Typical Application Diagram on page 49 4.0 6/2009 • Updated category from Advance Information to Technical Data. 5.0 1/2010 • Added Max I2C Speed as 400kHz to dynamic electrical characteristics table • Added Device Physical address to dynamic electrical characteristics table. • Added register Definition summary table • Changed REG7 name definition on Functional Description table to "Inverter boost" • Added efficiency Plots • Clarified GrpC and E Shutdown Sequence • Clarified REG8 Voltage/Current Regulation Mode on feature list. • Clarified Pulse Skipping operation. • Added minimum Fine Scaling value at 40% • Corrected Register Vs Bit notation on I2C user interface section. • Added I2C reading and writing Bit stream sequence example. • Added ACCURATE Bit definition • Revised Pin Definitions Table for Pins 3, 11, 35, 40, 46 and 53 • Removed Li-ion battery references throughout document. • Added Feedback Reference Voltage and Feedback Reference Voltage on Current Regulation Mode to Table 4. 6.0 9/2011 • Revised Note 2 on page 7. • Changed F to F and F to F on page 42. 22 Z2 2P P2 • Revised step 1 under “Compensating for Buck operation" section on page 40. • Updated the formula for C1 on page 42. • Revised step 1 under “Compensating for boost operation" section on page 43. • Revised step 1 under “Regulator 3 (Synchronous Buck - internally compensated)" section on page 44. • Revised I definition under “Regulator 8 (Synchronous Boost - internally compensated -Voltage OB or current feedback)" section on page 45. • Revised P-MOSFET description under “Regulator 7 (Inverter controller - external compensation needed)" section on page 46. 7.0 12/2011 • Changed RST Leakage Current from 1 mA to 1 A in the Static Electrical Characteristics table on page 9. 4/2013 • No technical changes. Revised back page. Updated document properties. Added SMARTMOS sentence to first paragraph. 8.0 12/2014 • Updated case outline (changed 98ASA10751D to 98ASA00712D) as per PCN 16331 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 53

How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based freescale.com on the information in this document. Web Support: Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no freescale.com/support warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2014 Freescale Semiconductor, Inc. Document Number: MC34704 Rev. 8.0 12/2014

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