MC34163, MC33163 3.4 A, Step-Up/Down/ Inverting Switching Regulators The MC34163 series are monolithic power switching regulators that contain the primary functions required for dc−to−dc converters. This series is specifically designed to be incorporated in step−up, http://onsemi.com step−down, and voltage−inverting applications with a minimum number of external components. These devices consist of two high gain voltage feedback MARKING comparators, temperature compensated reference, controlled duty DIAGRAMS cycle oscillator, driver with bootstrap capability for increased efficiency, and a high current output switch. Protective features consist 16 of cycle−by−cycle current limiting, and internal thermal shutdown. MC3x163P Also included is a low voltage indicator output designed to interface 16 AWLYYWWG with microprocessor based systems. 1 PDIP−16 These devices are contained in a 16 pin dual−in−line heat tab plastic 1 P SUFFIX package for improved thermal conduction. CASE 648C Features • Output Switch Current in Excess of 3.0 A • 16 Operation from 2.5 V to 40 V Input • Low Standby Current • 16 MC3x163DW Precision 2% Reference AWLYYWWG • Controlled Duty Cycle Oscillator SOIC−16W • 1 Driver with Bootstrap Capability for Increased Efficiency DW SUFFIX • Cycle−by−Cycle Current Limiting CASE 751G 1 • Internal Thermal Shutdown Protection • Low Voltage Indicator Output for Direct Microprocessor Interface x = 3 or 4 • A = Assembly Location Heat Tab Power Package • WL = Wafer Lot Moisture Sensitivity Level (MSL) Equals 1 YY = Year • Pb−Free Packages are Available* WW= Work Week G = Pb−Free Package Driver Ipk Sense 8 - ILimit 9 Collector PIN CONNECTIONS + VCC 7 10 LVI Output 1 16 Bootstrap Input + Switch Voltage Feedback 2 2 15 Collector Switch Timing Emitter 6 OSC 11 Voltage Feedback 1 3 14 Capacitor 4 13 GND GND 5 12 Control Logic 5 12 GND and Thermal GND Shutdown Timing Capacitor 6 11 4 13 Switch Collector + VCC 7 10 Voltage 3 14 Ipk Sense 8 9 Driver Collector Feedback 1 Switch VFB Emitter (Top View) Voltage 2 + 15 Feedback 2 + - ORDERING INFORMATION LVI + Bootstrap See detailed ordering and shipping information in the package LVI Output 1 + 16 Input dimensions section on page 2 of this data sheet. - + *For additional information on our Pb−Free strategy (Bottom View) and soldering details, please download the This device contains 114 active transistors. ON Semiconductor Soldering and Mounting Figure 1. Representative Block Diagram Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 1 Publication Order Number: August, 2008 − Rev. 6 MC34163/D

MC34163, MC33163 MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit Power Supply Voltage VCC 40 V Switch Collector Voltage Range VC(switch) −1.0 to +40 V Switch Emitter Voltage Range VE(switch) −2.0 to VC(switch) V Switch Collector to Emitter Voltage VCE(switch) 40 V Switch Current (Note 2) ISW 3.4 A Driver Collector Voltage VC(driver) −1.0 to +40 V Driver Collector Current IC(driver) 150 mA Bootstrap Input Current Range (Note 2) IBS −100 to +100 mA Current Sense Input Voltage Range VIpk (Sense) (VCC−7.0) to (VCC+1.0) V Feedback and Timing Capacitor Input Voltage Range Vin −1.0 to +7.0 V Low Voltage Indicator Output Voltage Range VC(LVI) −1.0 to +40 V Low Voltage Indicator Output Sink Current IC(LVI) 10 mA Thermal Characteristics °C/W P Suffix, Dual−In−Line Case 648C Thermal Resistance, Junction−to−Air R(cid:2)JA 80 Thermal Resistance, Junction−to−Case (Pins 4, 5, 12, 13) R(cid:2)JC 15 DW Suffix, Surface Mount Case 751G Thermal Resistance, Junction−to−Air R(cid:2)JA 94 Thermal Resistance, Junction−to−Case (Pins 4, 5, 12, 13) R(cid:2)JC 18 Operating Junction Temperature TJ +150 °C Operating Ambient Temperature (Note 3) TA °C MC34163 0 to +70 MC33163 −40 to +85 Storage Temperature Range Tstg −65 to +150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 1500 V per MIL−STD−883, Method 3015. Machine Model Method 150 V. 2. Maximum package power dissipation limits must be observed. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. ORDERING INFORMATION Device Package Shipping† MC33163DW SOIC−16W 47 Units / Rail MC33163DWG SOIC−16W 47 Units / Rail (Pb−Free) MC33163DWR2 SOIC−16W 1000 Units / Reel MC33163DWR2G SOIC−16W 1000 Units / Reel (Pb−Free) MC33163P PDIP−16 25 Units / Rail MC33163PG PDIP−16 25 Units / Rail (Pb−Free) MC34163DW SOIC−16W 47 Units / Rail MC34163DWG SOIC−16W 47 Units / Rail (Pb−Free) MC34163DWR2 SOIC−16W 1000 Units / Reel MC34163DWR2G SOIC−16W 1000 Units / Reel (Pb−Free) MC34163P PDIP−16 25 Units / Rail MC34163PG PDIP−16 25 Units / Rail (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2

MC34163, MC33163 ELECTRICAL CHARACTERISTICS (VCC = 15 V, Pin 16 = VCC, CT = 620 pF, for typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies (Note 5), unless otherwise noted.) Characteristic Symbol Min Typ Max Unit OSCILLATOR Frequency fOSC kHz TA = 25°C 46 50 54 Total Variation over VCC = 2.5 V to 40 V, and Temperature 45 − 55 Charge Current Ichg − 225 − (cid:3)A Discharge Current Idischg − 25 − (cid:3)A Charge to Discharge Current Ratio Ichg/Idischg 8.0 9.0 10 − Sawtooth Peak Voltage VOSC(P) − 1.25 − V Sawtooth Valley Voltage VOSC(V) − 0.55 − V FEEDBACK COMPARATOR 1 Threshold Voltage Vth(FB1) TA = 25°C 4.9 5.05 5.2 V Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C) − 0.008 0.03 %/V Total Variation over Line, and Temperature 4.85 − 5.25 V Input Bias Current (VFB1 = 5.05 V) IIB(FB1) − 100 200 (cid:3)A FEEDBACK COMPARATOR 2 Threshold Voltage Vth(FB2) TA = 25°C 1.225 1.25 1.275 V Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C) − 0.008 0.03 %/V Total Variation over Line, and Temperature 1.213 − 1.287 V Input Bias Current (VFB2 = 1.25 V) IIB(FB2) −0.4 0 0.4 (cid:3)A CURRENT LIMIT COMPARATOR Threshold Voltage Vth(Ipk Sense) mV TA = 25°C − 250 − Total Variation over VCC = 2.5 V to 40 V, and Temperature 230 − 270 Input Bias Current (VIpk (Sense) = 15 V) IIB(sense) − 1.0 20 (cid:3)A DRIVER AND OUTPUT SWITCH (Note 4) Sink Saturation Voltage (ISW = 2.5 A, Pins 14, 15 grounded) VCE(sat) V Non−Darlington Connection (RPin 9 = 110 (cid:4) to VCC, ISW/IDRV ≈ 20) − 0.6 1.0 Darlington Connection (Pins 9, 10, 11 connected) − 1.0 1.4 Collector Off−State Leakage Current (VCE = 40 V) IC(off) − 0.02 100 (cid:3)A Bootstrap Input Current Source (VBS = VCC + 5.0 V) Isource(DRV) 0.5 2.0 4.0 mA Bootstrap Input Zener Clamp Voltage (IZ = 25 mA) VZ VCC + 6.0 VCC + 7.0 VCC + 9.0 V LOW VOLTAGE INDICATOR Input Threshold (VFB2 Increasing) Vth 1.07 1.125 1.18 V Input Hysteresis (VFB2 Decreasing) VH − 15 − mV Output Sink Saturation Voltage (Isink = 2.0 mA) VOL(LVI) − 0.15 0.4 V Output Off−State Leakage Current (VOH = 15 V) IOH − 0.01 5.0 (cid:3)A TOTAL DEVICE Standby Supply Current (VCC = 2.5 V to 40 V, Pin 8 = VCC, ICC − 6.0 10 mA Pins 6, 14, 15 = GND, remaining pins open) 4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 5. Tlow = 0°C for MC34163 Thigh = +70°C for MC34163 = −40°C for MC33163 = +85°C for MC33163 http://onsemi.com 3

MC34163, MC33163 μON-OFF TIME ( s) 100 4VT123A))))C(cid:3)(cid:3)(cid:3)(cid:3) C=ttttoooo =nnnf2f,,,, 5 1RtRR°o5CDDDf f,VTTT R ===D 22∞T00 = kk 10 k 1 NCY CHANGE (%) 2.00 VCCT C= =6 2105 pVF H 5)(cid:3)toff, RDT = ∞ UE C 10 2 Q -(cid:2)2.0 T E WI R , OUTPUT Soff 345 OSCILLATOR F -(cid:2)4.0 -ton 1.00.1 1.0 10 , OSC-(cid:2)6.-0(cid:2)55 -(cid:2)25 0 25 50 75 100 125 t CT, OSCILLATOR TIMING CAPACITOR (nF) Δf TA, AMBIENT TEMPERATURE (°C) Figure 2. Output Switch On−Off Time Figure 3. Oscillator Frequency Change versus Oscillator Timing Capacitor versus Temperature 140 V) 1300 m VCC = 15 V E ( μT ((cid:3)(cid:2)A) 120 VFB1 = 5.05 V OLTAG 1280 VCC = 15 V Vth Max = 1275 mV N V URRE HOLD 1260 Vth Typ = 1250 mV S C 100 ES A R NPUT BI 80 OR 2 TH 1240 Vth Min = 1225 mV , IB RAT 1220 II A P M 60 O 1200 -(cid:2)55 -(cid:2)25 TA, 0AMBIEN2T5 TEMPE5R0ATURE 7(°5C) 100 125 , CFB2) -(cid:2)55 -(cid:2)25 TA,0 AMBIEN2T5 TEMPE5R0ATURE7 (5°C) 100 125 h( Figure 4. Feedback Comparator 1 Input Bias Vt Figure 5. Feedback Comparator 2 Threshold Current versus Temperature Voltage versus Temperature A) m CE ( V) ENT SOUR 2.8 VPCinC 1 =6 1=5 V VCC + 5.0 V VOLTAGE ( 7.6 IZ = 25 mA R 2.4 P 7.4 R M U A C L UT R C NP 2.0 NE 7.2 OOTSTRAP I 1.6 AP INPUT ZE 7.0 B R , V) ST R T D 1.2 O 6.8 e ( -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 BO -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 ourc TA, AMBIENT TEMPERATURE (°C) V, Z TA, AMBIENT TEMPERATURE (°C) s I Figure 6. Bootstrap Input Current Figure 7. Bootstrap Input Zener Clamp Source versus Temperature Voltage versus Temperature http://onsemi.com 4

MC34163, MC33163 0 1.2 V) VCC Darlington Configuration , SOURCE SATURATION (CE (sat)----(cid:2)(cid:2)0011....4826 BNooont-sBtroaoptpsetrda,p Ppiend 1, 6P i=n V1C6 C= +V 5C.EPPTC0Aiim nnV =ssit t742e,,5r 85°SC,,o 11,u 02(rNc,, i11on13tge == C2 VGu)rCNrCeDnt to GND V, SINK SATURATION (V)CE (sat) 10000.....08642 DarPTGCPliAiionrnn olg=ssluet on472cndt,,5o ,e58° rPCd, =S 1i,nE i2Vn(smN,kC 91oiiCnt,3tt gee1=, r0 1C2 1C,4)u 51o,r 1rVn1e f5SCing at=ou tFn ruGanrroNtaeimotcDent edVd CSCwitch, RPin9 = 110 (cid:4) to VCC V GND -(cid:2)2.0 0 0 0.8 1.6 2.4 3.2 0 0.8 1.6 2.4 3.2 IE, EMITTER CURRENT (A) IC, COLLECTOR CURRENT (A) Figure 8. Output Switch Source Saturation Figure 9. Output Switch Sink Saturation versus Emitter Current versus Collector Current 0 V) 0.5 AGE (V) -(cid:2)0.4 GND IC = 10 (cid:3)A N VOLTAGE ( 0.4 VTAC(cid:3)C=(cid:3)(cid:3)=2(cid:3)55° VC ER VOLT -(cid:2)0.8 IC = 10 mA TURATIO 0.3 T -(cid:2)1.2 A 0.2 T S MI T E U , E VCC = 15 V TP V -(cid:2)1.6 Pins 7, 8, 9, 10, 16 = VCC OU 0.1 PPiinn s1 44, D6r i=v eGnN NDegative , VI) L -(cid:2)2.0 L ( 0 -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 O 0 2.0 4.0 6.0 8.0 V TA, AMBIENT TEMPERATURE (°C) Isink, OUTPUT SINK CURRENT (mA) Figure 10. Output Switch Negative Emitter Figure 11. Low Voltage Indicator Output Sink Voltage versus Temperature Saturation Voltage versus Sink Current V) 254 1.6 TAGE (m VCC = 15 V μNT ( A) 1.4 VVCIpCk (=S e1n5se V) = 15 V OL 252 RE V R D U ESHOL 250 BIAS C 1.2 R T H U 1.0 T P , nse) 248 IN,e) k Se Sens0.8 Vth (Ip 246 IIB (0.6 -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 12. Current Limit Comparator Threshold Figure 13. Current Limit Comparator Input Bias Voltage versus Temperature Current versus Temperature http://onsemi.com 5

MC34163, MC33163 8.0 7.2 VCC = 15 V A) A) Pins 7, 8, 16 = VCC T (m 6.0 T (m 6.4 PRienms a4i,n 6in, g1 4P i=n sG ONpDen N N E E R R R R U U C 4.0 C 5.6 Y Y L L P P P P SU Pins 7, 8, 16 = VCC SU , C 2.0 Pins 4, 6, 14 = GND , C4.8 C C I Remaining Pins Open I TA = 25°C 0 4.0 0 10 20 30 40 -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 VCC, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C) Figure 14. Standby Supply Current Figure 15. Standby Supply Current versus Supply Voltage versus Temperature NIMUM OPERATING SUPPLY VOLTAGE (V) 32211.....06284 PPini n1 61 6= OVpCeCn CPPPPiiiiTnnnn ss=19 740 6=,, 28 = 110 =41. 0p 0=V F0k C(cid:4)G (cid:4)CN t Doto 1 155 V V R, THERMAL RESISTANCEθJA°JUNCTION-TO-AIR ( C/W)18624000000 PRD(cid:2)(mJAax) for TA = 70°C PGLÎÎÎrirnatpehdCs 2c o.ÎÎÎri0erpc Lppourezietr sbeoÎÎÎnatr sdy hmeÎÎÎmatestirnicka eÎÎÎl x3laa.y0mo mpultem 54321.....00000, MAXIMUM POWER DISSIPATION (W)D , MIn)1.-0(cid:2)55 -(cid:2)25 0 25 50 75 100 125 00 10 20 30 40 500 P mi C( TA, AMBIENT TEMPERATURE (°C) L, LENGTH OF COPPER (mm) C V Figure 16. Minimum Operating Supply Figure 17. P Suffix (DIP−16) Thermal Resistance Voltage versus Temperature and Maximum Power Dissipation versus P.C.B. Copper Length 100 2.8 90 PD(max) for TA = 50°C 2.4 N (W) E O R, THERMAL RESISTANCθJA°JUNCTION-TO-AIR ( C/W) 4567800000 R(cid:2)JA GLraÎÎÎphC2 r.o0epL pÎÎÎoprzee.rseÎÎÎÎnts syÎmmeÎÎÎÎtrica3l ÎÎÎl.a0y moumt 00112.....48260 MAXIMUM POWER DISSIPATI , D P 30 0 0 10 20 30 40 50 L, LENGTH OF COPPER (mm) Figure 18. DW Suffix (SOP−16L) Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length http://onsemi.com 6

MC34163, MC33163 Current 0.25 V Ipk Sense 8 + - Limit 9 Driver Collector RSC + VCC 7 10 + Switch Collector Timing Capacitor CT 6 Oscillator Q1 11 Shutdown RDT 5 RQ Q2 12 Thermal S 60 GND GND Latch 4 13 + Voltage Feedback 1 3 14 45 k Switch Emitter Voltage Feedback 2 2 + Feedback 15 + +- Comparator LVI Output 1 ++- +1.25 V 15 k 7.20. 0V mA 16 Bootstrap Input +- = SPoinskit iOven lTyrue Logic LVI 1.125 V + (Bottom View) Figure 19. Representative Block Diagram 1 Comparator Output 0 1.25 V Timing Capacitor CT 0.55 V t 9t 1 Oscillator Output 0 On Output Switch Off Nominal Output Voltage Level Output Voltage Startup Quiescent Operation Figure 20. Typical Operating Waveforms http://onsemi.com 7

MC34163, MC33163 INTRODUCTION resistor increases the discharge current which reduces the on−time of the output switch. A graph of the Output Switch The MC34163 series are monolithic power switching On−Off Time versus Oscillator Timing Capacitance for regulators optimized for dc−to−dc converter applications. various values of R is shown in Figure 2. Note that the The combination of features in this series enables the system DT maximum output duty cycle, t /t + t , remains constant designer to directly implement step−up, step−down, and on on off for values of C greater than 0.2 nF. The converter output voltage−inverting converters with a minimum number of T can be inhibited by clamping C to ground with an external external components. Potential applications include cost T NPN small−signal transistor. sensitive consumer products as well as equipment for the automotive, computer, and industrial markets. A Feedback and Low Voltage Indicator Comparators Representative Block Diagram is shown in Figure 19. Output voltage control is established by the Feedback comparator. The inverting input is internally biased at 1.25 V OPERATING DESCRIPTION and is not pinned out. The converter output voltage is typically divided down with two external resistors and The MC34163 operates as a fixed on−time, variable monitored by the high impedance noninverting input at Pin 2. off−time voltage mode ripple regulator. In general, this The maximum input bias current is ±0.4 (cid:3)A, which can cause mode of operation is somewhat analogous to a capacitor an output voltage error that is equal to the product of the input charge pump and does not require dominant pole loop bias current and the upper divider resistance value. For compensation for converter stability. The Typical Operating applications that require 5.0 V, the converter output can be Waveforms are shown in Figure 20. The output voltage directly connected to the noninverting input at Pin 3. The high waveform shown is for a step−down converter with the impedance input, Pin 2, must be grounded to prevent noise ripple and phasing exaggerated for clarity. During initial pickup. The internal resistor divider is set for a nominal converter startup, the feedback comparator senses that the voltage of 5.05 V. The additional 50 mV compensates for a output voltage level is below nominal. This causes the 1.0% voltage drop in the cable and connector from the output switch to turn on and off at a frequency and duty cycle converter output to the load. The Feedback comparator’s controlled by the oscillator, thus pumping up the output filter output state is controlled by the highest voltage applied to capacitor. When the output voltage level reaches nominal, either of the two noninverting inputs. the feedback comparator sets the latch, immediately The Low Voltage Indicator (LVI) comparator is designed terminating switch conduction. The feedback comparator for use as a reset controller in microprocessor−based will inhibit the switch until the load current causes the output systems. The inverting input is internally biased at 1.125 V, voltage to fall below nominal. Under these conditions, which sets the noninverting input thresholds to 90% of output switch conduction can be inhibited for a partial nominal. The LVI comparator has 15 mV of hysteresis to oscillator cycle, a partial cycle plus a complete cycle, prevent erratic reset operation. The Open Collector output is multiple cycles, or a partial cycle plus multiple cycles. capable of sinking in excess of 6.0 mA (see Figure 11). An Oscillator external resistor (RLVI) and capacitor (CDLY) can be used to The oscillator frequency and on−time of the output switch program a reset delay time (tDLY) by the formula shown are programmed by the value selected for timing capacitor below, where V is the microprocessor reset input th(MPU) C . Capacitor C is charged and discharged by a 9 to 1 ratio threshold. Refer to Figure 21. T T (cid:3) (cid:2) internal current source and sink, generating a negative going 1 sawtooth waveform at Pin 6. As C charges, an internal T V pulse is generated at the oscillator output. This pulse is tDLY = RLVI CDLY In 1 − th(MPU) V connected to the NOR gate center input, preventing output out switch conduction, and to the AND gate upper input, Current Limit Comparator, Latch and Thermal allowing the latch to be reset if the comparator output is low. Shutdown Thus, the output switch is always disabled during ramp−up With a voltage mode ripple converter operating under and can be enabled by the comparator output only at the start normal conditions, output switch conduction is initiated by of ramp−down. The oscillator peak and valley thresholds are the oscillator and terminated by the Voltage Feedback 1.25 V and 0.55 V, respectively, with a charge current of 225 (cid:3)A and a discharge current of 25 (cid:3)A, yielding a comparator. Abnormal operating conditions occur when the converter output is overloaded or when feedback voltage maximum on−time duty cycle of 90%. A reduction of the sensing is lost. Under these conditions, the Current Limit maximum duty cycle may be required for specific converter comparator will protect the Output Switch. configurations. This can be accomplished with the addition of an external deadtime resistor (R ) placed across C . The DT T http://onsemi.com 8

MC34163, MC33163 The switch current is converted to a voltage by inserting additional device heating and reduced conversion a fractional ohm resistor, R , in series with V and output efficiency. SC CC switch transistor Q . The voltage drop across R is Figure 10 shows that by clamping the emitter to 0.5 V, the 2 SC monitored by the Current Sense comparator. If the voltage collector current will be in the range 10 (cid:3)A over drop exceeds 250 mV with respect to V , the comparator temperature. A 1N5822 or equivalent Schottky barrier CC will set the latch and terminate output switch conduction on rectifier is recommended to fulfill these requirements. a cycle−by−cycle basis. This Comparator/Latch A bootstrap input is provided to reduce the output switch configuration ensures that the Output Switch has only a saturation voltage in step−down and voltage−inverting single on−time during a given oscillator cycle. The converter applications. This input is connected through a calculation for a value of R is: series resistor and capacitor to the switch emitter and is used SC to raise the internal 2.0 mA bias current source above V . 0.25V CC RSC(cid:4)Ipk(Switch) An internal zener limits the bootstrap input voltage to VCC +7.0 V. The capacitor’s equivalent series resistance must Figures 12 and 13 show that the Current Sense comparator limit the zener current to less than 100 mA. An additional threshold is tightly controlled over temperature and has a series resistor may be required when using tantalum or other typical input bias current of 1.0 (cid:3)A. The propagation delay low ESR capacitors. The equation below is used to calculate from the comparator input to the Output Switch is typically a minimum value bootstrap capacitor based on a minimum 200 ns. The parasitic inductance associated with R and the SC zener voltage and an upper limit current source. circuit layout should be minimized. This will prevent unwanted voltage spikes that may falsely trip the Current CB(min)(cid:4)I (cid:5)(cid:5)Vt (cid:4)4.0mA4t.o0nV(cid:4)0.001ton Limit comparator. Parametric operation of the MC34163 is guaranteed over Internal thermal shutdown circuitry is provided to protect a supply voltage range of 2.5 V to 40 V. When operating the IC in the event that the maximum junction temperature is exceeded. When activated, typically at 170°C, the Latch below 3.0 V, the Bootstrap Input should be connected to V . Figure 16 shows that functional operation down to is forced into the “Set” state, disabling the Output Switch. CC 1.7V at room temperature is possible. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used Package as a replacement for proper heatsinking. The MC34163 is contained in a heatsinkable 16−lead plastic dual−in−line package in which the die is mounted on Driver and Output Switch a special heat tab copper alloy lead frame. This tab consists To aid in system design flexibility and conversion of the four center ground pins that are specifically designed efficiency, the driver current source and collector, and to improve thermal conduction from the die to the circuit output switch collector and emitter are pinned out board. Figures 17 and 18 show a simple and effective separately. This allows the designer the option of driving the method of utilizing the printed circuit board medium as a output switch into saturation with a selected force gain or heat dissipater by soldering these pins to an adequate area of driving it near saturation when connected as a Darlington. copper foil. This permits the use of standard layout and The output switch has a typical current gain of 70 at 2.5 A mounting practices while having the ability to halve the and is designed to switch a maximum of 40 V collector to junction−to−air thermal resistance. These examples are for emitter, with up to 3.4 A peak collector current. The a symmetrical layout on a single−sided board with two minimum value for R is: SC ounce per square foot of copper. 0.25V RSC(min)(cid:4) (cid:4)0.0735(cid:4) 3.4A APPLICATIONS When configured for step−down or voltage−inverting The following converter applications show the simplicity applications, as in Figures 21 and 25, the inductor will and flexibility of this circuit architecture. Three main forward bias the output rectifier when the switch turns off. converter topologies are demonstrated with actual test data Rectifiers with a high forward voltage drop or long turn−on shown below each of the circuit diagrams. delay time should not be used. If the emitter is allowed to go sufficiently negative, collector current will flow, causing http://onsemi.com 9

MC34163, MC33163 Current 0.25 V 8 + - Limit 9 RSC + Vin 0.075 7 10 12 V Cin + + 330 CT 6 Oscillator Q1 11 680 pF R Q2 5 Q 12 Thermal S 60 Latch 4 13 + 3 14 45 k + Feedback 1N5822 2 + +- Comparator 15 Low Voltage R10LV kI + 1.25 V 15 k 2.0 mA 0.02 Indicator Output CDLY 1 LVI +- +1.125 V + 7.0 V 16 CB RB L C18o0il c(cid:3)raHft LO451-A Vout (Bottom View) 2200 +CO 5.05 V/3.0 A Test Condition Results Line Regulation Vin = 8.0 V to 24 V, IO = 3.0 A 6.0 mV = ±0.06% Load Regulation Vin = 12 V, IO = 0.6 A to 3.0 A 2.0 mV = ±0.02% Output Ripple Vin = 12 V, IO = 3.0 A 36 mVpp Short Circuit Current Vin = 12 V, RL = 0.1 (cid:4) 3.3 A Efficiency, Without Bootstrap Vin = 12 V, IO = 3.0 A 76.7% Efficiency, With Bootstrap Vin = 12 V, IO = 3.0 A 81.2% Figure 21. Step−Down Converter 8 9 8 9 Q3 7 10 7 10 + + 6 Q1 11 6 Q1 11 Q2 Q2 5 12 5 12 4 13 4 13 + + 3 14 Q3 3 14 2 15 2 15 1 16 1 16 + + (Bottom View) (Bottom View) Figure 22A. External NPN Switch Figure 22B. External PNP Saturated Switch Figure 22. External Current Boost Connections for Ipk (Switch) Greater Than 3.4 A http://onsemi.com 10

MC34163, MC33163 180 (cid:3)H 0.25 V Current L Coilcraft 8 + - Limit 9 LO451-A RSC + Vin 0.075 7 10 12 V Cin + + 330 6 Oscillator Q1 11 CT 680 pF R Q2 5 Q 12 Thermal S 60 Latch 4 13 + 1N5822 3 14 45 k 2 ++ Feedback 15 + - Comparator Low Voltage + 1.25 V 15 k 2.0 mA Indicator 1 + + 16 Output RLVI LVI - 1.125 V + 7.0 V 1.0 k Vout R1 R2 (Bottom View) +CO 28 V/600 mA 2.2 k 47 k 330 Test Condition Results Line Regulation Vin = 9.0 V to 16 V, IO = 0.6 A 30 mV = ±0.05% Load Regulation Vin = 12 V, IO = 0.1 A to 0.6 A 50 mV = ±0.09% Output Ripple Vin = 12 V, IO = 0.6 A 140 mVpp Efficiency Vin = 12 V, IO = 0.6 A 88.1% Figure 23. Step−Up Converter 8 9 8 9 7 10 7 10 + + 6 Q1 11 6 Q1 11 Q2 Q2 5 12 5 12 4 13 4 13 + + 3 14 Q3 3 14 Q3 2 15 2 15 1 16 1 16 + + (Bottom View) (Bottom View) Figure 24A. External NPN Switch Figure 24B. External NPN Saturated Switch Figure 24. External Current Boost Connections for Ipk (Switch) Greater Than 3.4 A http://onsemi.com 11

MC34163, MC33163 Current 0.25 V 8 + - Limit 9 RSC + Vin 0.075 7 10 12 V Cin + + 330 CT 6 Oscillator Q1 11 470 pF R Q2 5 Q 12 Thermal S 60 Latch 4 13 + Coilcraft LO451-A 3 14 L 45 k 180 (cid:3)H 2 ++ Feedback 15 + - Comparator RB 0.02 + 1.25 V 15 k 2.0 mA CB 1 + 16 - + 7.0 V LVI 1.125 V + 1N5822 Vout 8R.22 k R1 (Bottom View) 2200 +CO -(cid:2)12 V/1.0 A 953 Test Condition Results Line Regulation Vin = 9.0 V to 16 V, IO = 1.0 A 5.0 mV = ±0.02% Load Regulation Vin = 12 V, IO = 0.6 A to 1.0 A 2.0 mV = ±0.01% Output Ripple Vin = 12 V, IO = 1.0 A 130 mVpp Short Circuit Current Vin = 12 V, RL = 0.1 (cid:4) 3.2 A Efficiency, Without Bootstrap Vin = 12 V, IO = 1.0 A 73.1% Efficiency, With Bootstrap Vin = 12 V, IO = 1.0 A 77.5% Figure 25. Voltage−Inverting Converter 8 9 8 9 Q3 7 10 7 10 + + 6 Q1 11 6 Q1 11 Q2 Q2 5 12 5 12 4 13 4 13 + + 3 14 3 14 2 15 Q3 2 15 1 16 1 16 + + (Bottom View) (Bottom View) Figure 26A. External NPN Switch Figure 26B. External PNP Saturated Switch Figure 26. External Current Boost Connections for Ipk (Switch) Greater Than 3.4 A http://onsemi.com 12

MC34163, MC33163 + + + + + VO- n O w C −Do + Vin - R2 RLVI CB + p B e R St 3 1 6 R 1 n 4 Ci 3 L C M + T C + + + RSC + Bottom View Top View + + + + + VO - −Up + Vin - R2 RLVI CO p + e St 3 6 1 1 R 4 3 n C Ci L M + T C + + + RSC + Bottom View Top View + + + + + VO - g n erti CO e−Inv + Vin - R2R1 CB B + g R a olt V 63 Cin 1 L 4 3 MC + CT + + + RSC + Bottom View Top View All printed circuit boards are 2.58” in width by 1.9” in height. Figure 27. Printed Circuit Board and Component Layout (Circuits of Figures 21, 23, 25) http://onsemi.com 13

MC34163, MC33163 Calculation Step−Down Step−Up Voltage−Inverting ton Vout (cid:5) VF Vout (cid:5) VF Vin |Vout| (cid:5) VF (Notesto 1ff, 2, 3) Vin (cid:6) Vsat (cid:6) Vout Vin Vsat Vin (cid:6) Vsat ton ton ton t t t (cid:3) off (cid:2) (cid:3) off (cid:2) (cid:3) off (cid:2) ton ƒ ton (cid:5) 1 ƒ ton (cid:5) 1 ƒ ton (cid:5) 1 t t t off off off 32.143·106 32.143·106 32.143·106 CT ƒ ƒ ƒ (cid:3) (cid:2) (cid:3) (cid:2) IL(avg) Iout Iout tton (cid:5) 1 Iout tton (cid:5) 1 off off (cid:5)I (cid:5)I (cid:5)I Ipk(Switch) IL(avg) (cid:5) L IL(avg) (cid:5) L IL(avg) (cid:5) L 2 2 2 0.25 0.25 0.25 RSC Ipk(Switch) Ipk(Switch) Ipk(Switch) (cid:3) (cid:2) (cid:3) (cid:2) (cid:3) (cid:2) V (cid:6) V (cid:6) V V (cid:6) V V (cid:6) V in sat out in sat in sat L (cid:5)I ton (cid:5)I ton (cid:5)I ton L L L (cid:3) (cid:2) Vripple(pp) (cid:5)IL 8ƒ1CO 2 (cid:5) (ESR)2 (cid:7) tonCOIout (cid:7) tonCOIout (cid:3) (cid:2) (cid:3) (cid:2) (cid:3) (cid:2) R R R Vout Vref R2 (cid:5) 1 Vref R2 (cid:5) 1 Vref R2 (cid:5) 1 1 1 1 The following Converter Characteristics must be chosen: Vin −Nominal operating input voltage. Vout −Desired output voltage. Iout −Desired output current. (cid:5)IL −Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that (cid:5)IL be chosen to be less than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit threshold set by RSC. If the design goal is to use a minimum inductance value, let (cid:5)IL = 2(IL(avg)). This will proportionally reduce converter output current capability. (cid:2) −Maximum output switch frequency. Vripple(pp) −Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications. NOTES: 1. Vsat − Saturation voltage of the output switch, refer to Figures 8 and 9. NOTES: 2. VF − Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V. NOTES: 3. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum NOTES: 3. operating input voltage. Figure 28. Design Equations http://onsemi.com 14

MC34163, MC33163 PACKAGE DIMENSIONS PDIP−16 P SUFFIX CASE 648C−04 ISSUE D A NOTES: A B B 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. M T 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN M 16 9 J FORMED PARALLEL. 1 8 B L 16X 005 (0.13) 4. DDIMIMENSIOMNIN IBN CDHOEEMSSA NXOT INMMCILILNLUIDMEE TMMEOARXLSD FLASH. 0. A 0.744 0.783 18.90 19.90 B 0.240 0.260 6.10 6.60 F C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 E 0.050 BSC 1.27 BSC F 0.040 0.70 1.02 1.78 N G 0.100 BSC 2.54 BSC J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L 0.300 BSC 7.62 BSC C M 0 (cid:3) 10(cid:3) 0 (cid:3) 10(cid:3) N 0.015 0.040 0.39 1.01 K T SEATING E PLANE G 16XD 0.005 (0.13) M T A http://onsemi.com 15

MC34163, MC33163 PACKAGE DIMENSIONS SOIC−16W DW SUFFIX CASE 751G−03 ISSUE C NOTES: D A (cid:2) 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 16 9 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. M 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR B PROTRUSION. ALLOWABLE DAMBAR H8X 25M E (cid:3)X 45 PEMRXACOTEETRSRSIUA SOLI FOC NOTH NSEDH IBAT LIDOLIN MB.EE N0S.1I3O NTO ATTA ML AINXIMUM 0. h MILLIMETERS DIM MIN MAX 1 8 A 2.35 2.65 A1 0.10 0.25 16XB B BC 00..3253 00..4392 D 10.15 10.45 0.25 M T A S B S E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 A q 0 (cid:3) 7 (cid:3) SEATING L 14X e PLANE 1 A T C ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5773−3850 Sales Representative http://onsemi.com MC34163/D 16

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