MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A Single Supply 3.0 V to 44 V Operational Amplifiers Quality bipolar fabrication with innovative design concepts are hhttttpp::////oonnsseemmii..ccoomm employed for the MC33071/72/74, MC34071/72/74, NCV33072/74A series of monolithic operational amplifiers. This series of operational amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/(cid:2)s slew rate PDIP−8 P SUFFIX and fast settling time without the use of JFET device technology. 8 CASE 626 Although this series can be operated from split supplies, it is 1 particularly suited for single supply operation, since the common mode input voltage range includes ground potential (V ). With a EE Darlington input stage, this series exhibits high input resistance, low SOIC−8 8 D SUFFIX input offset voltage and high gain. The all NPN output stage, CASE 751 characterized by no deadband crossover distortion and large output 1 voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response. WQFN10 MT SUFFIX The MC33071/72/74, MC34071/72/74, NCV33072/74,A series of CASE 510AJ devices are available in standard or prime performance (A Suffix) grades and are specified over the commercial, industrial/vehicular or military temperature ranges. The complete series of single, dual and quad operational amplifiers are available in plastic DIP, SOIC, QFN and TSSOP surface mount packages. PDIP−14 Features P SUFFIX • CASE 646 Wide Bandwidth: 4.5 MHz 14 • High Slew Rate: 13 V/(cid:2)s 1 • Fast Settling Time: 1.1 (cid:2)s to 0.1% SOIC−14 • Wide Single Supply Operation: 3.0 V to 44 V 14 D SUFFIX • CASE 751A Wide Input Common Mode Voltage Range: Includes Ground (VEE) 1 • Low Input Offset Voltage: 3.0 mV Maximum (A Suffix) • Large Output Voltage Swing: −14.7 V to +14 V (with ±15 V TSSOP−14 Supplies) DTB SUFFIX • 14 Large Capacitance Drive Capability: 0 pF to 10,000 pF CASE 948G 1 • Low Total Harmonic Distortion: 0.02% • Excellent Phase Margin: 60° ORDERING INFORMATION • Excellent Gain Margin: 12 dB See detailed ordering and shipping information on page 18 of • Output Short Circuit Protection this data sheet. • ESD Diodes/Clamps Provide Input Protection for Dual and Quad DEVICE MARKING INFORMATION • NCV Prefix for Automotive and Other Applications Requiring See general marking information in the device marking Unique Site and Control Change Requirements; AEC−Q100 section on page 21 of this data sheet. Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: July, 2014 − Rev. 22 MC34071/D

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A PIN CONNECTIONS CASE 626/CASE 751 CASE 646/CASE 751A/CASE 948G CASE 510AJ VCC Offset Null 1 8 NC Output 1 1 14 Output 4 10 Inputs 23 -+ 76 VOCuCtput Inputs 1 2 -+ 1 4 -+ 13 Inputs 4 Output 1 1 9 Output 2 3 12 VEE 4 5 Offset Null NC 2 8 NC VCC 4 11 VEE (Single, Top View) In ­ 1 3 7 In ­ 2 Inputs 2 5 +- 2 3 +- 10 Inputs 3 In + 1 4 ­ 6 In + 2 Output 1 1 8 VCC 6 9 5 2 - 7 Output 2 Output 2 7 8 Output 3 Inputs 1 3 + 6 VEE/GND - Inputs 2 VEE 4 + 5 (Quad, Top View) (Top View) (Dual, Top View) VCC Q3 Q4 Q5 Q6 Q7 Q1 Q17 Q2 R1 C1 R2 D2 Q18 Bias - Q8 Q9 Q10 Q11 R6 R7 Output Inputs R8 + C2 D3 Q19 Base Q13 Q14 Q15 Q16 Current Cancellation Q12 Current D1 Limit R5 R3 R4 VEE/GND Offset Null (MC33071, MC34071 only) Figure 1. Representative Schematic Diagram (Each Amplifier) http://onsemi.com 2

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage (from VEE to VCC) VS +44 V Input Differential Voltage Range VIDR (Note 1) V Input Voltage Range VIR (Note 1) V Output Short Circuit Duration (Note 2) tSC Indefinite Sec Operating Junction Temperature TJ +150 °C Storage Temperature Range Tstg −60 to +150 °C ESD Capability, Dual and Quad (Note 3) V Human Body Model ESDHBM 2000 Machine Model ESDMM 200 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Either or both input voltages should not exceed the magnitude of VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2). 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JEDEC standard: JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (JEDEC standard: JESD22−A115) http://onsemi.com 3

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL = connected to ground, unless otherwise noted. See Note 4 for TA = Tlow to Thigh) A Suffix Non−Suffix Characteristics Symbol Min Typ Max Min Typ Max Unit InpVuCt CO =ff s+e1t5 V Vo,lt aVgEeE (=R −S1 =5 1V0, 0T A(cid:3) =, V +C2M5 °=C 0 V, VO = 0 V) VIO −− 0.5 3.0 −− 1.0 5.0 mV VCC = +5.0 V, VEE = 0 V, TA = +25°C − 0.5 3.0 − 1.5 5.0 VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh − 5.0 − 7.0 Average Temperature Coefficient of Input Offset (cid:4)VIO/(cid:4)T − 10 − − 10 − (cid:2)V/°C Voltage RS = 10 (cid:3), VCM = 0 V, VO = 0 V, TA = Tlow to Thigh Input Bias Current (VCM = 0 V, VO = 0 V) IIB nA TA = +25°C − 100 500 − 100 500 TA = Tlow to Thigh − − 700 − − 700 Input Offset Current (VCM = 0 V, VO = 0V) IIO nA TA = +25°C − 6.0 50 − 6.0 75 TA = Tlow to Thigh − − 300 − − 300 Input Common Mode Voltage Range VICR V TA = +25°C VEE to (VCC −1.8) VEE to (VCC −1.8) TA = Tlow to Thigh VEE to (VCC −2.2) VEE to (VCC −2.2) Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 k(cid:3)) AVOL V/mV TA = +25°C 50 100 − 25 100 − TA = Tlow to Thigh 25 − − 20 − − Output Voltage Swing (VID = ±1.0 V) VOH V VCC = +5.0 V, VEE = 0 V, RL = 2.0 k(cid:3), TA = +25°C 3.7 4.0 − 3.7 4.0 − VCC = +15 V, VEE = −15 V, RL = 10 k(cid:3), TA = +25°C 13.6 14 − 13.6 14 − VCC = +15 V, VEE = −15 V, RL = 2.0 k(cid:3), 13.4 − − 13.4 − − TA = Tlow to Thigh VCC = +5.0 V, VEE = 0 V, RL = 2.0 k(cid:3), TA = +25°C VOL − 0.1 0.3 − 0.1 0.3 V VCC = +15 V, VEE = −15 V, RL = 10 k(cid:3), TA = +25°C − −14.7 −14.3 − −14.7 −14.3 VCC = +15 V, VEE = −15 V, RL = 2.0 k(cid:3), − − −13.5 − − −13.5 TA = Tlow to Thigh Output Short Circuit Current (VID = 1.0 V, VO = 0 V, ISC mA TA = 25°C) Source 10 30 − 10 30 − Sink 20 30 − 20 30 − Common Mode Rejection CMR 80 97 − 70 97 − dB RS ≤ 10 k(cid:3), VCM = VICR, TA = 25°C Power Supply Rejection (RS = 100 (cid:3)) PSR 80 97 − 70 97 − dB VCC/VEE = +16.5 V/−16.5 V to +13.5 V/−13.5 V, TA = 25°C Power Supply Current (Per Amplifier, No Load) ID mA VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25°C − 1.6 2.0 − 1.6 2.0 VCC = +15 V, VEE = −15 V, VO = 0 V, TA = +25°C − 1.9 2.5 − 1.9 2.5 VCC = +15 V, VEE = −15 V, VO = 0 V, − − 2.8 − − 2.8 TA = Tlow to Thigh Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Tlow = −40°C for MC33071,2,4,/A, NCV33074/AThigh = +85°C for MC33071,2,4,/A, NCV33074/A = 0°C for MC34071,2,4,/A = +70°C for MC34071,2,4,/A = −40°C for MC34072,4/V, NCV33072,4A = +125°C for MC34072,4/V, NCV33072,4A, NCV34074V Case 510AJ Tlow/Thigh guaranteed by product characterization. http://onsemi.com 4

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL = connected to ground. TA = +25°C, unless otherwise noted.) A Suffix Non−Suffix Characteristics Symbol Min Typ Max Min Typ Max Unit Slew Rate (Vin = −10 V to +10 V, RL = 2.0 k(cid:3), CL = 500 pF) SR V/(cid:2)s AV = +1.0 8.0 10 − 8.0 10 − AV = −1.0 − 13 − − 13 − Setting Time (10 V Step, AV = −1.0) ts (cid:2)s To 0.1% (+1/2 LSB of 9−Bits) − 1.1 − − 1.1 − To 0.01% (+1/2 LSB of 12−Bits) − 2.2 − − 2.2 − Gain Bandwidth Product (f = 100 kHz) GBW 3.5 4.5 − 3.5 4.5 − MHz Power Bandwidth BW − 160 − − 160 − kHz AV = +1.0, RL = 2.0 k(cid:3), VO = 20 Vpp, THD = 5.0% Phase margin fm Deg RL = 2.0 k(cid:3) − 60 − − 60 − RL = 2.0 k(cid:3), CL = 300 pF − 40 − − 40 − Gain Margin Am dB RL = 2.0 k(cid:3) − 12 − − 12 − RL = 2.0 k(cid:3), CL = 300 pF − 4.0 − − 4.0 − Equivalent Input Noise Voltage en − 32 − − 32 − nV/√Hz RS = 100 (cid:3), f = 1.0 kHz Equivalent Input Noise Current in − 0.22 − − 0.22 − pA/√Hz f = 1.0 kHz Differential Input Resistance Rin − 150 − − 150 − M(cid:3) VCM = 0 V Differential Input Capacitance Cin − 2.5 − − 2.5 − pF VCM = 0 V Total Harmonic Distortion THD − 0.02 − − 0.02 − % AV = +10, RL = 2.0 k(cid:3), 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz Channel Separation (f = 10 kHz) − − 120 − − 120 − dB Open Loop Output Impedance (f = 1.0 MHz) |ZO| − 30 − − 30 − W Single Supply Split Supplies 3.0 V to 44 V VCC+|VEE|≤44 V VCC VCC VCC 7 2 - 1 VCC 1 6 3 + 5 2 2 1 4 3 3 10 k 4 VEE 4 VEE VEE VEE Offset nulling range is approximately ±80 mV with a 10 k potentiometer (MC33071, MC34071 only). Figure 2. Power Supply Configurations Figure 3. Offset Null Circuit http://onsemi.com 5

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A 2400 W) TION (m 2000 GE (mV) 4.0 VVVCECECM === -+01155 VV SSIPA 1600 OLTA 2.0 ER DI 1200 SOIC-14 Pkg 8 & 14 Pin Plastic Pkg SET V 0 W F M PO 800 UT OF-2.0 U P M SOIC-8 Pkg N AXI 400 (cid:4)(cid:3), IO P(cid:3)(cid:3)(cid:3), MD 0 VVI-4.0 -55 -40 -20 0 20 40 60 80 100 120 140 160 -55 -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 4. Maximum Power Dissipation versus Figure 5. Input Offset Voltage versus Temperature for Package Types Temperature for Representative Units V) VCC NGE (D) 1.3 VCC -0.8 VCC VCC/VEE = +1.5 V/ -1.5 V to +22 V/ -22 V TAGE RARMALIZE 1.2 VVVCECECM === - 0+1155 V V LO ON 1.1 VCC -1.6 MODE VRRENT ( 1.0 N U VCC -2.4 MOS C 0.9 MA OBI VEE +0.01 UT CPUT 0.8 VEE-55 -25 0 VEE 25 50 75 100 125(cid:4)(cid:3)(cid:3)(cid:3), INPCRI(cid:4), INIB0.7-55 -25 0 25 50 75 100 125 VI TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 6. Input Common Mode Voltage Figure 7. Normalized Input Bias Current Range versus Temperature versus Temperature D) 1.4 50 E ORMALIZ 1.2 TVVACE EC= ==2 5- +°1C155 V V G (V)pp 40 RtoL G Croonunnedc TteAd = 25°C N N T ( WI N S 30 URRE 1.0 TAGE RL = 10 k RL = 2.0 k C L T BIAS 0.8 PUT VO 20 PU UT 10 N O (cid:4), IB , O I V I 0.6 0 -12 -8.0 -4.0 0 4.0 8.0 12 0 5.0 10 15 20 25 VIC, INPUT COMMON MODE VOLTAGE (V) VCC, |VEE|, SUPPLY VOLTAGE (V) Figure 8. Normalized Input Bias Current versus Figure 9. Split Supply Output Voltage Input Common Mode Voltage Swing versus Supply Voltage http://onsemi.com 6

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A E (V) VCC Source VCC/VEE = +4.5 V/ -4.5 V to +22 V/ -22 V E (V) VCC VCC G G OLTA VCC -1.0 −40 OLTAVCC-2.0 VCC = +15 V N V 25 N V RL = GND TIO VCC -2.0 125 TIOVCC-4.0 TA = 25°C A A R R U U SAT VEE +2.0 Sink SAT 0.2 T T U U P 25 P UT VEE +1.0 UT 0.1 O 85 O V , sat VEE 125 V , sat 0 GND 0 5.0 10 15 20 100 1.0 k 10 k 100 k IL, LOAD CURRENT (±mA) RL, LOAD RESISTANCE TO GROUND ((cid:3)) Figure 10. Split Supply Output Saturation Figure 11. Single Supply Output Saturation versus Load Current versus Load Resistance to Ground V) 0 60 E ( LTAG-0.4 VCC mA) 50 Sink N VO NT ( 40 TURATIO-0.8 T CURRE 30 Source V , OUTPUT SAsat 21..00 GND VRTACL C=to =2 V 5+C°1CC5 V I(cid:5)(cid:5)(cid:3)(cid:3), OUTPUSC21000 VRV(cid:4)CELV EC≤in = = 0= -.+ 1111 .5(cid:3)05 VVV 100 1.0 k 10 k 100 k -55 -25 0 25 50 75 100 125 RL, LOAD RESISTANCE TO VCC ((cid:3)) TA, AMBIENT TEMPERATURE (°C) Figure 12. Single Supply Output Saturation Figure 13. Output Short Circuit Current versus Load Resistance to V versus Temperature CC 50 28 VCC = +15 V ΩPEDANCE ((cid:4)) 4300 VV(cid:4)TVAECOI OEM == == =20 5 -±0°10C5.5 V mA GE SWING (V)pp 221406 VARTTVAVHCEL ECD=== = =2+2≤ 5.1-+ 01°.11 0.Ck505 % VV T IM 20 OLTA 12 OUTPU AV = 1000 AV = 100 AV = 10 AV = 1.0 PUT V 8.0 Z(cid:5)(cid:3), O 10 OUT 4.0 , O V 0 0 1.0 k 10 k 100 1.0 M 10 M 3.0 k 10 k 30 k 100 k 300 k 1.0 M 3.0 M f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 14. Output Impedance Figure 15. Output Voltage Swing versus Frequency versus Frequency http://onsemi.com 7

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A 0.4 4.0 %) %) TORTION ( 0.3 AV = 1000 TORTION ( 3.0 AV = 1000 VVRTACEL EC== ==22 5.- 0+°1 C1k55 V V C DIS VVCEEC == - +1155 V V C DIS NI 0.2 VO = 2.0 Vpp NI 2.0 MO RL = 2.0 k MO HAR AV = 100 TA = 25°C HAR AV = 100 TAL 0.1 TAL 1.0 AV = 10 D, TO AV = 10 D, TO AV = 1.0 TH 0 AV = 1.0 TH 0 10 100 1.0 k 10 k 100 k 0 4.0 8.0 12 16 20 f, FREQUENCY (Hz) VO, OUTPUT VOLTAGE SWING (Vpp) Figure 16. Total Harmonic Distortion Figure 17. Total Harmonic Distortion versus Frequency versus Output Voltage Swing 116 100 B) B) d d 0 AIN (112 VCC = +15 V AIN ( 80 S) GE G VVEOE= =- 1-01 5V Vto +10 V GE G Phase Gain 45 GREE P VOLTA108 Rf ≤L =1 01H0z k P VOLTA 60 MPhaargsien 90 ASE (DE OO104 OO 40 = 60° PH N L N L VCC = +15 V 135SS PE PE VEE = -15 V CE A(cid:4)(cid:3)(cid:3)(cid:3), OVOL100 A(cid:4)(cid:3)(cid:3)(cid:3), OVOL20 VRTAOL === 2205. 0V° Ck 180φ, EX 96 0 -55 -25 0 25 50 75 100 125 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (Hz) Figure 18. Open Loop Voltage Gain Figure 19. Open Loop Voltage Gain and versus Temperature Phase versus Frequency D) E B) 20 1 ALI 1.15 AIN (d 10 PMhaargsien = 60° 100 NORM 1.1 VVCEEC == - +1155 V V LTAGE G 0 GMaairngin = 12 dB 112400EGREES) ODUCT ( 1.05 RL = 2.0 k O D R P V-10 E ( H P 1.0 A(cid:4)(cid:3)(cid:3)(cid:3), OPEN LOOVOL---234000 1234VVV....CEO PPGGEC = hh aa== aa0ii nn ss1+ Vee5RR1 (cid:4) 5LLRRV LL==V(cid:4) ==22 ..(cid:4)2200.. 00kk(cid:4) ,kk C,(cid:4) LC L=T A=3 0=30 02 0p5 F°pCF 2 43 116800φ, EXCESS PHAS W, GAIN BANDWIDT 00..098.559 B 1.0 2.0 3.0 5.0 7.0 10 20 30 G -55 -25 0 25 50 75 100 125 f, FREQUENCY (MHz) TA, AMBIENT TEMPERATURE (°C) Figure 20. Open Loop Voltage Gain and Figure 21. Normalized Gain Bandwidth Phase versus Frequency Product versus Temperature http://onsemi.com 8

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A 100 70 VCC = +15 V S) 60 VCC = +15 V 80 VEE = -15 V EE VEE = -15 V T OVERSHOOT 60 RVTAOL === 22-5.10°0 Ck V to +10 V MARGIN (DEGR 543000 ARVTAVOL ==== 2+2-5.110°.0 0Ck V to t o(cid:2) +10 V PERCEN 4200 , PHASE m20 φ 10 0 0 10 100 1.0 k 10 k 10 100 1.0 k 10 k CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF) Figure 22. Percent Overshoot versus Figure 23. Phase Margin versus Load Capacitance Load Capacitance 14 80 12 VVCEEC == - +1155 V V EES) CL = 10 pF N (dB) 10 ARVL == +2.10. 0k to ∞ DEGR 60 CL = 100 pF ARGI 8.0 VTAO == 2-51°0C V to +10 V GIN ( VCC = +15 V A(cid:4), GAIN Mm64..00 PHASE MAR 2400 CL = 1,000 pF VARVVEOL E === = +2- .1-10.10 0k5 V tVo t o∞ +10 V , m 2.0 φ CL = 10,000 pF 0 0 10 100 1.0 k 10 k -55 -25 0 25 50 75 100 125 CL, LOAD CAPACITANCE (pF) TA, AMBIENT TEMPERATURE (°C) Figure 24. Gain Margin versus Load Capacitance Figure 25. Phase Margin versus Temperature 16 12 70 VCC = +15 V 10 60 S) A(cid:4), GAIN MARGIN (dB)m841..200 VARVVEOL E === = +2C- .1 10L-.0 01=k 5V 1t o V,t0 o∞0 +01 p0F V CLC =L =1C 01L0 0= ,p 01F000 p pFF A(cid:4), GAIN MARGIN (dB)m8642....0000 VVRAVCET EC== RR = =+R2 1 1- 1+01 +105- 5+ RV V2 VO GainPhase 54320000 , PHASE MARGIN (DEGREEm 0 VO = 0 V 10φ TA = 25°C 0 0 -55 -25 0 25 50 75 100 125 1.0 10 100 1.0 k 10 k 100 k TA, AMBIENT TEMPERATURE (°C) RT, DIFFERENTIAL SOURCE RESISTANCE ((cid:3)) Figure 26. Gain Margin versus Temperature Figure 27. Phase Margin and Gain Margin versus Differential Source Resistance http://onsemi.com 9

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A 1.15 V) 10 LIZED) 1.1 VVAVCE EC= ==+ 1- +.10155 V V ROM 0 V ( 5.0 10 mV 1.0 mV 1.0 mV VVAVCE EC= ==- 1- +.10155 V V MA1.05 RL = 2.0 k G F TA = 25°C W RATE (NOR0.19.50 CL = 500 pF OLTAGE SWIN 0 UCnocmopmepnesnasteadted SLE T V-5.0 1.0 mV R, 0.9 PU 10 mV S UT 1.0 mV O 0.85 (cid:4), O-10 -55 -25 0 25 50 75 100 125 V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Δ TA, AMBIENT TEMPERATURE (°C) ts, SETTLING TIME ((cid:2)s) Figure 28. Normalized Slew Rate Figure 29. Output Settling Time versus Temperature VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k 50 mV/DIV 0 VVCEEC == -+1155 VV 5.0 V/DIV 0 CTAL == 2350°0C pF AV = +1.0 RL = 2.0 k CL = 300 pF TA = 25°C 2.0 (cid:2)s/DIV 1.0 (cid:2)s/DIV Figure 30. Small Signal Transient Response Figure 31. Large Signal Transient Response 100 100 dB) TA = 125°C VCC = +15 V B) VCC = +15 V TION ( 80 TA = 25°C VVECEM == -01 V5 V ON (d 80 VTAE E= =2 5-°1C5 V EC TA = -55°C (cid:4)VCM = ±1.5 V CTI (cid:4)VCC E REJ 60 REJE 60 -ADM (cid:4)VO ((cid:4)VCC = +1.5 V) D Y + O L OMMON M 40 (cid:4)VCM -A+DM (cid:4)VO WER SUPP 40 +PSR = 20 L(cid:4)ogVEE (cid:4)V(cid:4)OV/CACDM +PSR CMR, C 200 CMR = 20 Log (cid:4)(cid:4)VVCOM x ADM PSR, PO 200 -PSR = 20 Log (cid:4)V(cid:4)OV/EAEDM ((cid:4)VEE = -+P1S.5R V) 0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 32. Common Mode Rejection Figure 33. Power Supply Rejection versus Frequency versus Frequency http://onsemi.com 10

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A 9.0 105 mA) 8.0 TA = -55°C ON (dB) -PSR ((cid:4)VEE = +1.5 V) VVCEEC == - +1155 V V T ( CTI95 N E URRE 7.0 TA = 25°C Y REJ +PSR ((cid:4)VCC = +1.5 V) I(cid:4)(cid:3) , SUPPLY CCC65..00 TA = 125°C Quad device PSR, POWER SUPPL8755 +-PPSSRR == 2200 LLoogg (cid:4)(cid:4)(cid:4)(cid:4)VVOOVV//CEAAECDDMM -A+DM (cid:4)(cid:4)VVCEEC (cid:4)VO 4.0 65 0 5.0 10 15 20 25 -55 -25 0 25 50 75 100 125 VCC, |VEE|, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C) Figure 34. Supply Current versus Figure 35. Power Supply Rejection Supply Voltage versus Temperature 120 70 2.8 CHANNEL SEPARATION (dB)18642000000 VVTACE EC= ==2 5- +°1C155 V V √NPUT NOICE VOLTAGE (nVHz(cid:3)) 6543200000 CuVrroeltnatge VVVTACEC ECM= ===2 5 - 0+°1C155 V V 22110.....40628 √PUT NOISE CURRENT (pA )Hz e(cid:5)(cid:3)(cid:3), In 10 0.4 (cid:4), INn 0 0 0 i 10 20 30 50 70 100 200 300 10 100 1.0 k 10 k 100 k f, FREQUENCY (kHz) f, FREQUENCY (kHz) Figure 36. Channel Separation versus Frequency Figure 37. Input Noise versus Frequency APPLICATIONS INFORMATION CIRCUIT DESCRIPTION/PERFORMANCE FEATURES Although the bandwidth, slew rate, and settling time of the up to approximately 5.0 mA of current from V through EE MC34071 amplifier series are similar to op amp products either inputs clamping diode without damage or latching, utilizing JFET input devices, these amplifiers offer other although phase reversal may again occur. additional distinct advantages as a result of the PNP If one or both inputs exceed the upper common mode transistor differential input stage and an all NPN transistor voltage limit, the amplifier output is readily predictable and output stage. may be in a low or high state depending on the existing input Since the input common mode voltage range of this input bias conditions. stage includes the V potential, single supply operation is Since the input capacitance associated with the small EE feasible to as low as 3.0 V with the common mode input geometry input device is substantially lower (2.5 pF) than voltage at ground potential. the typical JFET input gate capacitance (5.0 pF), better The input stage also allows differential input voltages up frequency response for a given input source resistance can to ±44 V, provided the maximum input voltage range is not be achieved using the MC34071 series of amplifiers. This exceeded. Specifically, the input voltages must range performance feature becomes evident, for example, in fast between V and V supply voltages as shown by the settling D−to−A current to voltage conversion applications EE CC maximum rating table. In practice, although not where the feedback resistance can form an input pole with recommended, the input voltages can exceed the V the input capacitance of the op amp. This input pole creates CC voltage by approximately 3.0 V and decrease below the V a 2nd order system with the single pole op amp and is EE voltage by 0.3 V without causing product damage, although therefore detrimental to its settling time. In this context, output phase reversal may occur. It is also possible to source lower input capacitance is desirable especially for higher http://onsemi.com 11

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A values of feedback resistances (lower current DACs). This Because the PNP output emitter−follower transistor has input pole can be compensated for by creating a feedback been eliminated, the MC34071 series offers a 20 mA zero with a capacitance across the feedback resistance, if minimum current sink capability, typically to an output necessary, to reduce overshoot. For 2.0 k(cid:3) of feedback voltage of (V +1.8 V). In single supply applications the EE resistance, the MC34071 series can settle to within 1/2 LSB output can directly source or sink base current from a of 8−bits in 1.0 (cid:2)s, and within 1/2 LSB of 12−bits in 2.2 (cid:2)s common emitter NPN transistor for fast high current for a 10 V step. In a inverting unity gain fast settling switching applications. configuration, the symmetrical slew rate is ±13 V/(cid:2)s. In the In addition, the all NPN transistor output stage is classic noninverting unity gain configuration, the output inherently fast, contributing to the bipolar amplifier’s high positive slew rate is +10 V/(cid:2)s, and the corresponding gain bandwidth product and fast settling capability. The negative slew rate will exceed the positive slew rate as a associated high frequency low output impedance (30 (cid:3) typ function of the fall time of the input waveform. @ 1.0 MHz) allows capacitive drive capability from 0 pF to Since the bipolar input device matching characteristics 10,000 pF without oscillation in the unity closed loop gain are superior to that of JFETs, a low untrimmed maximum configuration. The 60° phase margin and 12 dB gain margin offset voltage of 3.0 mV prime and 5.0 mV downgrade can as well as the general gain and phase characteristics are be economically offered with high frequency performance virtually independent of the source/sink output swing characteristics. This combination is ideal for low cost conditions. This allows easier system phase compensation, precision, high speed quad op amp applications. since output swing will not be a phase consideration. The The all NPN output stage, shown in its basic form on the high frequency characteristics of the MC34071 series also equivalent circuit schematic, offers unique advantages over allow excellent high frequency active filter capability, the more conventional NPN/PNP transistor Class AB output especially for low voltage single supply applications. stage. A 10 k(cid:3) load resistance can swing within 1.0 V of the Although the single supply specifications is defined at positive rail (V ), and within 0.3 V of the negative rail 5.0V, these amplifiers are functional to 3.0 V @ 25°C CC (V ), providing a 28.7 V swing from ±15 V supplies. although slight changes in parametrics such as bandwidth, EE pp This large output swing becomes most noticeable at lower slew rate, and DC gain may occur. supply voltages. If power to this integrated circuit is applied in reverse The positive swing is limited by the saturation voltage of polarity or if the IC is installed backwards in a socket, large the current source transistor Q , and V of the NPN pull up unlimited current surges will occur through the device that 7 BE transistor Q , and the voltage drop associated with the short may result in device destruction. 17 circuit resistance, R . The negative swing is limited by the Special static precautions are not necessary for these 7 saturation voltage of the pull−down transistor Q , the bipolar amplifiers since there are no MOS transistors on the 16 voltage drop I R , and the voltage drop associated with die. L 6 resistance R , where I is the sink load current. For small As with most high frequency amplifiers, proper lead 7 L valued sink currents, the above voltage drops are negligible, dress, component placement, and PC board layout should be allowing the negative swing voltage to approach within exercised for optimum frequency performance. For millivolts of V . For large valued sink currents (>5.0 mA), example, long unshielded input or output leads may result in EE diode D3 clamps the voltage across R , thus limiting the unwanted input−output coupling. In order to preserve the 6 negative swing to the saturation voltage of Q , plus the relatively low input capacitance associated with these 16 forward diode drop of D3 (≈V +1.0 V). Thus for a given amplifiers, resistors connected to the inputs should be EE supply voltage, unprecedented peak−to−peak output voltage immediately adjacent to the input pin to minimize additional swing is possible as indicated by the output swing stray input capacitance. This not only minimizes the input specifications. pole for optimum frequency response, but also minimizes If the load resistance is referenced to V instead of extraneous “pick up” at this node. Supply decoupling with CC ground for single supply applications, the maximum adequate capacitance immediately adjacent to the supply pin possible output swing can be achieved for a given supply is also important, particularly over temperature, since many voltage. For light load currents, the load resistance will pull types of decoupling capacitors exhibit great impedance the output to V during the positive swing and the output changes over temperature. CC will pull the load resistance near ground during the negative The output of any one amplifier is current limited and thus swing. The load resistance value should be much less than protected from a direct short to ground. However, under that of the feedback resistance to maximize pull up such conditions, it is important not to allow the device to capability. exceed the maximum junction temperature rating. Typically for ±15 V supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating. http://onsemi.com 12

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A (Typical Single Supply Applications V = 5.0 V) CC VCC 5.1 M VO 0 3.7 Vpp VCC 0 3.7 Vpp 20 k Cin 1.0 M 100 k + CO VO 68 k MC34071 + 36.6 mVpp - Cin 10 k MC34071 VO Vin 100 k 10 k - CO 10 k 1.0 k AV = 101 RL Vin 370 mVpp 100 k RL BW (-3.0 dB) = 45 kHz AV = 10 BW (-3.0 dB) = 450 kHz Figure 38. AC Coupled Noninverting Amplifier Figure 39. AC Coupled Inverting Amplifier VO 4.75 Vpp VCC 2.63 V 91 k 5.1 k RL 5.1 k + 2.5 V 100 k MC34071 VO - 0 0 to 10,000 pF Vin + MC54/74XX 1.0 M MC34071 - Cable TTL Gate Vin AV = 10 BW (-3.0 dB) = 450 kHz Figure 40. DC Coupled Inverting Amplifier Figure 41. Unity Gain Buffer TTL Driver Maximum Output Swing C R3 0.047 2.2 k R1 Vin - 1.1 k C MC34071 VO R2 0.047 + VCC Vin ≥ 0.2 Vdc 5.6 k fo = 30 kHz - VO Ho = 10 R R MC34071 0.4 VCC Ho = 1.0 Vin 16 k 16 k + GAOiv e=n G foa i=n Cate Cnteenr tFerr eFqrueeqnuceyncy C Choose Value fo, Q, Ao, C 0.01 Then: Q R3 R1 R3 R3 = (cid:4) R1 = (cid:4) R2 = fo = 1.0 kHz (cid:5)foC 2Ho 4Q2R1-R3 2.0 R 32 k 1 Qofo fo = 4(cid:5)RC For less than 10% error from operational amplifier GBW < 0.1 2.0 C 2.0 C where fo and GBW are expressed in Hz. 0.02 0.02 GBW = 4.5 MHz Typ. Figure 42. Active High−Q Notch Filter Figure 43. Active Bandpass Filter http://onsemi.com 13

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A CF Vin 2.0 V RF Vin + VO 5.0 k 5.0 k 5.0 k MC34071 t - VO - MC34071 2.0 k VO 10 k 10 k 10 k + VCC 1.0 V RL 0.2 (cid:2)s 4.0 V Delay Bit 13 V/(cid:2)s Switches 25 V/(cid:2)s (R-2R) Ladder Network 0.1 t Settling Time Delay 1.0 (cid:2)s (8-Bits, 1/2 LSB) 1.0 (cid:2)s Figure 44. Low Voltage Fast D/A Converter Figure 45. High Speed Low Voltage Comparator VCC “ON" Vin < Vref VCC VCC Vin + RL MC34071 - + + Vref MC34071 MC34071 - - “ON" Vin > Vref RL (A) PNP (B) NPN Figure 46. LED Driver Figure 47. Transistor Driver ILoad RF + MC34071 VO - GSeronusned R Ceusrisretonrt RS R1 ICell M-C34071 VO + R2 R1 VO = ILoad RS 1+ R2 For VO > 0.1V VCell = 0 V BW ( -3.0 dB) = GBW R2 VO = ICell RF R1+R2 VO > 0.1 V Figure 48. AC/DC Ground Current Monitor Figure 49. Photovoltaic Cell Amplifier http://onsemi.com 14

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A VO Hysteresis R2 Vref R1 + VOH Iout Vin M-C34071 VOL VinL VinH Vin Vin M+C34071 VinL = R1R+1R2 (VOL-Vref)+Vref Vref - R1 VinH = R1+R2 (VOH-Vref)+Vref R1 Vin±VIO R VH = R1+R (VOH -VOL) Iout = R Figure 50. Low Input Voltage Comparator Figure 51. High Compliance Voltage to with Hysteresis Sink Current Converter R1 R2 R4 +Vref RF M-C13/42072 R3 - 1/2 VO R R +V1 + M+C34072 - VO MC34071 +V2 R = (cid:4)R R + R2 R4 = (Critical to CMRR) R1 R3 VO = 1 + RR43 V2-V1 RR43 (cid:4)R < < R RF VO = Vref (cid:4)2RR 2RF For (V2 ≥ V1), V > 0 RF > > R (VO ≥ 0.1 V) Figure 52. High Input Impedance Figure 53. Bridge Current Amplifier Differential Amplifier fOSC (cid:3) 0R.8C5 V + IB + ISC VP 0 t Vin + VO = Vin (pk) t - Base Charge Removal MC34071 - Iout R -1/2 + 1/2 + MC34072 MC34072 RL VP 10,000 pF C + - ±IB V+ 100 k Pulse Width Vin 100 k 47 k VP Control Group VP OSC Comparator High Current t Output Figure 54. Low Voltage Peak Detector Figure 55. High Frequency Pulse Width Modulation http://onsemi.com 15

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A GENERAL ADDITIONAL APPLICATIONS INFORMATION V = ±15.0 V S C2 C2 R1 0.02 0.05 C1 46.1 k 1.0 R2 - R1 R3 5.6 k C1 MC34071 560 510 - 1.0 R2 + fo = 100 Hz 1.1 k Ho = 20 MC34071 0.C414 + fo = 1.0 kHz Choose: fo, Ho, C2 Ho = 10 Choose: fo, Ho, C1 Then: R1 = (cid:5)(cid:4)HfooC+10.(cid:4)52 2 Then: C1 = 2C2 (Ho+1) R2 = 2(cid:5)foC1 (1/Ho+2) (cid:4) 2 R2 R2 C R2 = R3 = R1 = C2 = 4(cid:5)foC2 Ho+1 Ho Ho Figure 56. Second Order Low−Pass Active Filter Figure 57. Second Order High−Pass Active Filter CF* VO = 10 V RF Step 2.0 k + - +MC34071 VO R1 -MC34071 RL VO I Uncompensated ts = 1.0 (cid:2)s Vin R2 to 1/2 LSB (8-Bits) HighD ASCpeed Compensated ttso =1 /22. 2L S(cid:2)Bs (12-Bits) VO = R2 BW (-3.0 dB) = GBW R1 Vin R1 R1 +R2 *Optional Compensation SR = 13 V/(cid:2)s SR = 13 V/(cid:2)s Figure 58. Fast Settling Inverter Figure 59. Basic Inverting Amplifier + MC34071 VO - Vin R2 Vin + RL MC34071 VO - R1 VO R2 = 1 + Vin R1 BWp = 200 kHz BW (-3.0 dB) = GBW R1 VO = 20 Vpp R1 +R2 SR = 10 V/(cid:2)s Figure 60. Basic Noninverting Amplifier Figure 61. Unity Gain Buffer (A = +1.0) V http://onsemi.com 16

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A + R R MC34074 - R - RE MC34074 VO R + - R Example: MC34074 Let: R = RE = 12 k R + R TBhWe n=: 1A.V5 =M 3H.0z AV = 1 +(cid:3)2 RE Figure 62. High Impedance Differential Amplifier +VO + + MC34074 + 100 k - 10 RL 10 +10 - MC34074 220 pF + 100 k -10 + + + RL RL +VO -VO 100 k -MC34074 10 10 ∞ 18.93 -18.78 10 k 18 -18 -VO 5.0 k 15.4 -15.4 Figure 63. Dual Voltage Doubler http://onsemi.com 17

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A ORDERING INFORMATION Op Amp Operating Shipping† Function Device Temperature Range Package MC34071PG PDIP−8 50 Units / Rail (Pb−Free) MC34071APG PDIP−8 50 Units / Rail (Pb−Free) MC34071DG SOIC−8 98 Units / Rail (Pb−Free) MC34071DR2G TA = 0° to +70°C SOIC−8 2500 / Tape & Reel (Pb−Free) MC34071ADG SOIC−8 98 Units / Rail (Pb−Free) MC34071ADR2G SOIC−8 2500 / Tape & Reel (Pb−Free) Single MC33071PG PDIP−8 50 Units / Rail (Pb−Free) MC33071APG PDIP−8 50 Units / Rail (Pb−Free) MC33071DG SOIC−8 98 Units / Rail (Pb−Free) MC33071DR2G TA = −40° to +85°C SOIC−8 2500 / Tape & Reel (Pb−Free) MC33071ADG SOIC−8 98 Units / Rail (Pb−Free) MC33071ADR2G SOIC−8 2500 / Tape & Reel (Pb−Free) http://onsemi.com 18

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A ORDERING INFORMATION (continued) Op Amp Operating Shipping† Function Device Temperature Range Package MC34072PG PDIP−8 (Pb−Free) 50 Units / Rail MC34072APG PDIP−8 (Pb−Free) MC34072DG SOIC−8 (Pb−Free) 98 Units / Rail MC34072ADG SOIC−8 TA = 0° to +70°C (Pb−Free) MC34072DR2G SOIC−8 (Pb−Free) 2500 Units / Tape & Reel MC34072ADR2G SOIC−8 (Pb−Free) MC34072AMTTBG WQFN10 3000 Units / Tape & Reel (Pb−Free) MC33072PG PDIP−8 (Pb−Free) 50 Units / Rail MC33072APG PDIP−8 Dual (Pb−Free) MC33072DG SOIC−8 (Pb−Free) MC33072ADG TA = −40° to +85°C SOIC−8 98 Units / Rail (Pb−Free) MC33072DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC33072ADR2G SOIC−8 (Pb−Free) MC34072VDG SOIC−8 98 Units / Rail (Pb−Free) MC34072VDR2G SOIC−8 2500 / Tape & Reel (Pb−Free) MC34072VPG TA = −40° to +125°C PDIP−8 50 Units / Rail (Pb−Free) NCV33072DR2G* SOIC−8 2500 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV prefix for automotive and other applications requiring unique site and control change requirements; AEC−Q100 qualified and PPAP capable. http://onsemi.com 19

MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A ORDERING INFORMATION (continued) Op Amp Operating Shipping† Function Device Temperature Range Package MC34074PG PDIP−14 (Pb−Free) 25 Units / Rail MC34074APG PDIP−14 (Pb−Free) MC34074DG SOIC−14 (Pb−Free) MC34074ADG TA = 0° to +70°C SOIC−14 55 Units / Rail (Pb−Free) MC34074ADR2G SOIC−14 (Pb−Free) 2500 Units / Tape & Reel MC34074DR2G SOIC−14 (Pb−Free) MC33074PG PDIP−14 (Pb−Free) 25 Units / Rail MC33074APG PDIP−14 (Pb−Free) MC33074DG SOIC−14 (Pb−Free) 55 Units / Rail MC33074ADG SOIC−14 (Pb−Free) MC33074DR2G SOIC−14 (Pb−Free) 2500 / Tape & Reel NCV33074DR2G* SOIC−14 Quad (Pb−Free) MC33074ADR2G SOIC−14 TA = −40° to +85°C (Pb−Free) 2500 / Tape & Reel NCV33074ADR2G* SOIC−14 (Pb−Free) MC33074DTBG TSSOP−14 96 Units / Rail (Pb−Free) MC33074DTBR2G TSSOP−14 2500 / Tape & Reel (Pb−Free) MC33074ADTBG TSSOP−14 96 Units / Rail (Pb−Free) MC33074ADTBR2G TSSOP−14 (Pb−Free) 2500 / Tape & Reel NCV33074ADTBR2G* TSSOP−14 (Pb−Free) MC34074VDG SOIC−14 55 Units / Rail (Pb−Free) MC34074VDR2G SOIC−14 (Pb−Free) NCV34074VDR2G* TA = −40° to +125°C SOIC−14 2500 / Tape & Reel (Pb−Free) MC34074VPG PDIP−14 25 Units / Rail (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV prefix for automotive and other applications requiring unique site and control change requirements; AEC−Q100 qualified and PPAP capable. http://onsemi.com 20

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WQFN10 2.6x2.6, 0.5P CASE 510AJ−01 ISSUE A SCALE 2:1 DATE 27 MAR 2009 D A B L L NOTES: 1. DIMENSIONING AND TOLERANCING PER ÍÍÍ ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. PIN ONE ÍÍÍ L1 3. DIMENSION b APPLIES TO PLATED REFERENCE TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. ÍÍÍ E DETAIL A 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ALTERNATE TERMINAL CONSTRUCTIONS MILLIMETERS 0.15 C DIM MIN MAX A 0.70 0.80 A1 0.00 0.05 0.15 C EXPOSED CuÉÉMOLD CMPD A3 0.20 REF TOP VIEW b 0.20 0.30 ÉÉÉÉ D 2.60 BSC E 2.60 BSC 0.10 C DETAIL B A3 DETAIL B e 0.50 BSC L 0.45 0.55 A COANLSTTERRUNCATTIOENS L1 0.00 0.15 L2 0.55 0.65 0.08 C A1 NOTE 4 SIDE VIEW C SPELAATNIENG MARKGINEGN EDRIAICGRAM* DETAIL A 9XL 5 XXXX AAYW (cid:2) 4 6 XXXX= Specific Device Code AA = Assembly Location 1 9 e Y = Year W = Work Week L2 10 (cid:2) = Pb−Free Package 10Xb 0.10 C A B *This information is generic. Please refer to device data sheet for actual part marking. BOTTOM VIEW 0.05 C NOTE 3 Pb−Free indicator, “G” or microdot “ (cid:2)”, may or may not be present. SOLDERING FOOTPRINT* 2.90 1 0.50 PITCH 2.90 10X 0.30 10X 0.73 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98AON38696E Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: WQFN10 2.6X2.6, 0.5P PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−8 CASE 626−05 ISSUE P DATE 22 APR 2015 SCALE 1:1 D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. E 2. CONTROLLING DIMENSION: INCHES. H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 8 5 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE E1 NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM 1 4 PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE NOTE 8 c LEADS UNCONSTRAINED. b2 B 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE END VIEW LEADS, WHERE THE LEADS EXIT THE BODY. TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). NOTE 5 INCHES MILLIMETERS A2 DIM MIN MAX MIN MAX e/2 A A −−−− 0.210 −−− 5.33 NOTE 3 A1 0.015 −−−− 0.38 −−− A2 0.115 0.195 2.92 4.95 L b 0.014 0.022 0.35 0.56 b2 0.060 TYP 1.52 TYP C 0.008 0.014 0.20 0.36 D 0.355 0.400 9.02 10.16 SEATING A1 PLANE D1 0.005 −−−− 0.13 −−− E 0.300 0.325 7.62 8.26 C M E1 0.240 0.280 6.10 7.11 D1 e 0.100 BSC 2.54 BSC e eB eB −−−− 0.430 −−− 10.92 L 0.115 0.150 2.92 3.81 8Xb END VIEW M −−−− 10° −−− 10° 0.010 M C A M B M NOTE 6 SIDE VIEW GENERIC MARKING DIAGRAM* STYLE 1: PIN 1.AC IN 2.DC + IN XXXXXXXXX 3.DC − IN AWL 4.AC IN 5.GROUND YYWWG 6.OUTPUT 7.AUXILIARY 8.VCC XXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ (cid:2)”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42420B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: PDIP−8 PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE S DATE 22 APR 2015 1 SCALE 1:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. D A 2. CONTROLLING DIMENSION: INCHES. 14 8 E 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- H AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. E1 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE 1 7 c LEADS UNCONSTRAINED. NOTE 8 TOP VIEW b2 B WITH LEEANDSD C VOINESWTRAINED 78.. DLPEAAACTDUKSAM,G PWEL HACENORENE TH TO IHSUE RC LOISEI NAODCPSITD IEEOXNNITTA WLT H(IRTEHO B UTONHDDEY EB.DO OTTRO SMQ OUFA RTEHE NOTE 5 CORNERS). A2 INCHES MILLIMETERS A DIM MIN MAX MIN MAX NOTE 3 A −−−− 0.210 −−− 5.33 L A1 0.015 −−−− 0.38 −−− A2 0.115 0.195 2.92 4.95 b 0.014 0.022 0.35 0.56 SEATING A1 PLANE b2 0.060 TYP 1.52 TYP C 0.008 0.014 0.20 0.36 C M D 0.735 0.775 18.67 19.69 D1 D1 0.005 −−−− 0.13 −−− e eB E 0.300 0.325 7.62 8.26 14Xb END VIEW E1 0.240 0.280 6.10 7.11 e 0.100 BSC 2.54 BSC 0.010 M C A M B M NOTE 6 eB −−−− 0.430 −−− 10.92 SIDE VIEW L 0.115 0.150 2.92 3.81 M −−−− 10° −−− 10° GENERIC MARKING DIAGRAM* 14 XXXXXXXXXXXX XXXXXXXXXXXX AWLYYWWG STYLES ON PAGE 2 1 XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ (cid:2)”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42428B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: PDIP−14 PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

PDIP−14 CASE 646−06 ISSUE S DATE 22 APR 2015 STYLE 1: STYLE 2: STYLE 3: STYLE 4: PIN 1.COLLECTOR CANCELLED CANCELLED PIN 1.DRAIN 2.BASE 2.SOURCE 3.EMITTER 3.GATE 4.NO 4.NO CONNECTION CONNECTION 5.EMITTER 5.GATE 6.BASE 6.SOURCE 7.COLLECTOR 7.DRAIN 8.COLLECTOR 8.DRAIN 9.BASE 9.SOURCE 10.EMITTER 10.GATE 11.NO 11.NO CONNECTION CONNECTION 12.EMITTER 12.GATE 13.BASE 13.SOURCE 14.COLLECTOR 14.DRAIN STYLE 5: STYLE 6: STYLE 7: STYLE 8: PIN 1.GATE PIN 1.COMMON CATHODE PIN 1.NO CONNECTION PIN 1.NO CONNECTION 2.DRAIN 2.ANODE/CATHODE 2.ANODE 2.CATHODE 3.SOURCE 3.ANODE/CATHODE 3.ANODE 3.CATHODE 4.NO CONNECTION 4.NO CONNECTION 4.NO CONNECTION 4.NO CONNECTION 5.SOURCE 5.ANODE/CATHODE 5.ANODE 5.CATHODE 6.DRAIN 6.NO CONNECTION 6.NO CONNECTION 6.NO CONNECTION 7.GATE 7.ANODE/CATHODE 7.ANODE 7.CATHODE 8.GATE 8.ANODE/CATHODE 8.ANODE 8.CATHODE 9.DRAIN 9.ANODE/CATHODE 9.ANODE 9.CATHODE 10.SOURCE 10.NO CONNECTION 10.NO CONNECTION 10.NO CONNECTION 11.NO CONNECTION 11.ANODE/CATHODE 11.ANODE 11.CATHODE 12.SOURCE 12.ANODE/CATHODE 12.ANODE 12.CATHODE 13.DRAIN 13.NO CONNECTION 13.NO CONNECTION 13.NO CONNECTION 14.GATE 14.COMMON ANODE 14.COMMON 14.COMMON ANODE CATHODE STYLE 9: STYLE 10: STYLE 11: STYLE 12: PIN 1.COMMON CATHODE PIN 1.COMMON PIN 1.CATHODE PIN 1.COMMON CATHODE 2.ANODE/CATHODE CATHODE 2.CATHODE 2.COMMON ANODE 3.ANODE/CATHODE 2.ANODE/CATHODE 3.CATHODE 3.ANODE/CATHODE 4.NO CONNECTION 3.ANODE/CATHODE 4.CATHODE 4.ANODE/CATHODE 5.ANODE/CATHODE 4.ANODE/CATHODE 5.CATHODE 5.ANODE/CATHODE 6.ANODE/CATHODE 5.ANODE/CATHODE 6.CATHODE 6.COMMON ANODE 7.COMMON ANODE 6.NO CONNECTION 7.CATHODE 7.COMMON CATHODE 8.COMMON ANODE 7.COMMON ANODE 8.ANODE 8.ANODE/CATHODE 9.ANODE/CATHODE 8.COMMON 9.ANODE 9.ANODE/CATHODE 10.ANODE/CATHODE CATHODE 10.ANODE 10.ANODE/CATHODE 11.NO CONNECTION 9.ANODE/CATHODE 11.ANODE 11.ANODE/CATHODE 12.ANODE/CATHODE 10.ANODE/CATHODE 12.ANODE 12.ANODE/CATHODE 13.ANODE/CATHODE 11.ANODE/CATHODE 13.ANODE 13.ANODE/CATHODE 14.COMMON CATHODE 12.ANODE/CATHODE 14.ANODE 14.ANODE/CATHODE 13.NO CONNECTION 14.COMMON ANODE Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42428B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: PDIP−14 PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB 8 CASE 751−07 1 ISSUE AK DATE 16 FEB 2011 SCALE 1:1 NOTES: −X− 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. 7M5A1X−I0M1U TMH RMUA T7E51R−IA0L6 CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 C NX 45(cid:2) B 3.80 4.00 0.150 0.157 SEATING C 1.35 1.75 0.053 0.069 PLANE D 0.33 0.51 0.013 0.020 −Z− G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 0.10 (0.004) J 0.19 0.25 0.007 0.010 H D M J K 0.40 1.27 0.016 0.050 M 0 (cid:2) 8 (cid:2) 0 (cid:2) 8 (cid:2) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S S 5.80 6.20 0.228 0.244 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 8 8 8 8 XXXXX XXXXX XXXXXX XXXXXX 1.52 ALYWX ALY (cid:3)WX AYWW AY W(cid:3)W 0.060 1 1 1 1 IC IC Discrete Discrete (Pb−Free) (Pb−Free) 7.0 4.0 XXXXX = Specific Device Code XXXXXX= Specific Device Code 0.275 0.155 A = Assembly Location A = Assembly Location L = Wafer Lot Y = Year Y = Year WW = Work Week W = Work Week (cid:3) = Pb−Free Package (cid:3) = Pb−Free Package 0.6 1.270 *This information is generic. Please refer to device data sheet for actual part marking. 0.024 0.050 Pb−Free indicator, “G” or microdot “(cid:3)”, may (cid:2) mm (cid:3) or may not be present. Some products may SCALE 6:1 inches not follow the Generic Marking. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42564B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SOIC−8 NB PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: STYLE 2: STYLE 3: STYLE 4: PIN 1. EMITTER PIN 1. COLLECTOR, DIE, #1 PIN 1. DRAIN, DIE #1 PIN 1. ANODE 2. COLLECTOR 2. COLLECTOR, #1 2. DRAIN, #1 2. ANODE 3. COLLECTOR 3. COLLECTOR, #2 3. DRAIN, #2 3. ANODE 4. EMITTER 4. COLLECTOR, #2 4. DRAIN, #2 4. ANODE 5. EMITTER 5. BASE, #2 5. GATE, #2 5. ANODE 6. BASE 6. EMITTER, #2 6. SOURCE, #2 6. ANODE 7. BASE 7. BASE, #1 7. GATE, #1 7. ANODE 8. EMITTER 8. EMITTER, #1 8. SOURCE, #1 8. COMMON CATHODE STYLE 5: STYLE 6: STYLE 7: STYLE 8: PIN 1. DRAIN PIN 1. SOURCE PIN 1. INPUT PIN 1. COLLECTOR, DIE #1 2. DRAIN 2. DRAIN 2. EXTERNAL BYPASS 2. BASE, #1 3. DRAIN 3. DRAIN 3. THIRD STAGE SOURCE 3. BASE, #2 4. DRAIN 4. SOURCE 4. GROUND 4. COLLECTOR, #2 5. GATE 5. SOURCE 5. DRAIN 5. COLLECTOR, #2 6. GATE 6. GATE 6. GATE 3 6. EMITTER, #2 7. SOURCE 7. GATE 7. SECOND STAGE Vd 7. EMITTER, #1 8. SOURCE 8. SOURCE 8. FIRST STAGE Vd 8. COLLECTOR, #1 STYLE 9: STYLE 10: STYLE 11: STYLE 12: PIN 1. EMITTER, COMMON PIN 1. GROUND PIN 1. SOURCE 1 PIN 1. SOURCE 2. COLLECTOR, DIE #1 2. BIAS 1 2. GATE 1 2. SOURCE 3. COLLECTOR, DIE #2 3. OUTPUT 3. SOURCE 2 3. SOURCE 4. EMITTER, COMMON 4. GROUND 4. GATE 2 4. GATE 5. EMITTER, COMMON 5. GROUND 5. DRAIN 2 5. DRAIN 6. BASE, DIE #2 6. BIAS 2 6. DRAIN 2 6. DRAIN 7. BASE, DIE #1 7. INPUT 7. DRAIN 1 7. DRAIN 8. EMITTER, COMMON 8. GROUND 8. DRAIN 1 8. DRAIN STYLE 13: STYLE 14: STYLE 15: STYLE 16: PIN 1. N.C. PIN 1. N−SOURCE PIN 1. ANODE 1 PIN 1. EMITTER, DIE #1 2. SOURCE 2. N−GATE 2. ANODE 1 2. BASE, DIE #1 3. SOURCE 3. P−SOURCE 3. ANODE 1 3. EMITTER, DIE #2 4. GATE 4. P−GATE 4. ANODE 1 4. BASE, DIE #2 5. DRAIN 5. P−DRAIN 5. CATHODE, COMMON 5. COLLECTOR, DIE #2 6. DRAIN 6. P−DRAIN 6. CATHODE, COMMON 6. COLLECTOR, DIE #2 7. DRAIN 7. N−DRAIN 7. CATHODE, COMMON 7. COLLECTOR, DIE #1 8. DRAIN 8. N−DRAIN 8. CATHODE, COMMON 8. COLLECTOR, DIE #1 STYLE 17: STYLE 18: STYLE 19: STYLE 20: PIN 1. VCC PIN 1. ANODE PIN 1. SOURCE 1 PIN 1. SOURCE (N) 2. V2OUT 2. ANODE 2. GATE 1 2. GATE (N) 3. V1OUT 3. SOURCE 3. SOURCE 2 3. SOURCE (P) 4. TXE 4. GATE 4. GATE 2 4. GATE (P) 5. RXE 5. DRAIN 5. DRAIN 2 5. DRAIN 6. VEE 6. DRAIN 6. MIRROR 2 6. DRAIN 7. GND 7. CATHODE 7. DRAIN 1 7. DRAIN 8. ACC 8. CATHODE 8. MIRROR 1 8. DRAIN STYLE 21: STYLE 22: STYLE 23: STYLE 24: PIN 1. CATHODE 1 PIN 1. I/O LINE 1 PIN 1. LINE 1 IN PIN 1. BASE 2. CATHODE 2 2. COMMON CATHODE/VCC 2. COMMON ANODE/GND 2. EMITTER 3. CATHODE 3 3. COMMON CATHODE/VCC 3. COMMON ANODE/GND 3. COLLECTOR/ANODE 4. CATHODE 4 4. I/O LINE 3 4. LINE 2 IN 4. COLLECTOR/ANODE 5. CATHODE 5 5. COMMON ANODE/GND 5. LINE 2 OUT 5. CATHODE 6. COMMON ANODE 6. I/O LINE 4 6. COMMON ANODE/GND 6. CATHODE 7. COMMON ANODE 7. I/O LINE 5 7. COMMON ANODE/GND 7. COLLECTOR/ANODE 8. CATHODE 6 8. COMMON ANODE/GND 8. LINE 1 OUT 8. COLLECTOR/ANODE STYLE 25: STYLE 26: STYLE 27: STYLE 28: PIN 1. VIN PIN 1. GND PIN 1. ILIMIT PIN 1. SW_TO_GND 2. N/C 2. dv/dt 2. OVLO 2. DASIC_OFF 3. REXT 3. ENABLE 3. UVLO 3. DASIC_SW_DET 4. GND 4. ILIMIT 4. INPUT+ 4. GND 5. IOUT 5. SOURCE 5. SOURCE 5. V_MON 6. IOUT 6. SOURCE 6. SOURCE 6. VBULK 7. IOUT 7. SOURCE 7. SOURCE 7. VBULK 8. IOUT 8. VCC 8. DRAIN 8. VIN STYLE 29: STYLE 30: PIN 1. BASE, DIE #1 PIN 1. DRAIN 1 2. EMITTER, #1 2. DRAIN 1 3. BASE, #2 3. GATE 2 4. EMITTER, #2 4. SOURCE 2 5. COLLECTOR, #2 5. SOURCE 1/DRAIN 2 6. COLLECTOR, #2 6. SOURCE 1/DRAIN 2 7. COLLECTOR, #1 7. SOURCE 1/DRAIN 2 8. COLLECTOR, #1 8. GATE 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42564B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SOIC−8 NB PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 14 ISSUE L 1 DATE 03 FEB 2016 SCALE 1:1 D A NOTES: B 1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.CONTROLLING DIMENSION: MILLIMETERS. 14 8 3.DIMENSION b DOES NOT INCLUDE DAMBAR A3 PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. H E 4.DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. L 5.MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 1 7 DETAIL A MILLIMETERS INCHES 0.25 M B M 13Xb DIM MIN MAX MIN MAX A 1.35 1.75 0.054 0.068 0.25 M C A S B S A1 0.10 0.25 0.004 0.010 A3 0.19 0.25 0.008 0.010 DETAIL A b 0.35 0.49 0.014 0.019 h A X 45(cid:3) DE 38..8550 84..0750 00..135307 00..135474 e 1.27 BSC 0.050 BSC H 5.80 6.20 0.228 0.244 0.10 h 0.25 0.50 0.010 0.019 e A1 C SEATING M ML 0.04 0(cid:3) 1.72 5(cid:3) 0.010 6(cid:3) 0.047 9(cid:3) PLANE GENERIC SOLDERING FOOTPRINT* MARKING DIAGRAM* 6.50 14 14X 1.18 XXXXXXXXXG 1 AWLYWW 1 XXXXX = Specific Device Code A = Assembly Location 1.27 WL = Wafer Lot PITCH Y = Year WW = Work Week G = Pb−Free Package 14X *This information is generic. Please refer to 0.58 device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ (cid:2)”, may or may not be present. DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SOIC−14 NB PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: STYLE 2: STYLE 3: STYLE 4: PIN 1.COMMON CATHODE CANCELLED PIN 1.NO CONNECTION PIN 1.NO CONNECTION 2.ANODE/CATHODE 2.ANODE 2.CATHODE 3.ANODE/CATHODE 3.ANODE 3.CATHODE 4.NO CONNECTION 4.NO CONNECTION 4.NO CONNECTION 5.ANODE/CATHODE 5.ANODE 5.CATHODE 6.NO CONNECTION 6.NO CONNECTION 6.NO CONNECTION 7.ANODE/CATHODE 7.ANODE 7.CATHODE 8.ANODE/CATHODE 8.ANODE 8.CATHODE 9.ANODE/CATHODE 9.ANODE 9.CATHODE 10.NO CONNECTION 10.NO CONNECTION 10.NO CONNECTION 11.ANODE/CATHODE 11.ANODE 11.CATHODE 12.ANODE/CATHODE 12.ANODE 12.CATHODE 13.NO CONNECTION 13.NO CONNECTION 13.NO CONNECTION 14.COMMON ANODE 14.COMMON CATHODE 14.COMMON ANODE STYLE 5: STYLE 6: STYLE 7: STYLE 8: PIN 1.COMMON CATHODE PIN 1.CATHODE PIN 1.ANODE/CATHODE PIN 1.COMMON CATHODE 2.ANODE/CATHODE 2.CATHODE 2.COMMON ANODE 2.ANODE/CATHODE 3.ANODE/CATHODE 3.CATHODE 3.COMMON CATHODE 3.ANODE/CATHODE 4.ANODE/CATHODE 4.CATHODE 4.ANODE/CATHODE 4.NO CONNECTION 5.ANODE/CATHODE 5.CATHODE 5.ANODE/CATHODE 5.ANODE/CATHODE 6.NO CONNECTION 6.CATHODE 6.ANODE/CATHODE 6.ANODE/CATHODE 7.COMMON ANODE 7.CATHODE 7.ANODE/CATHODE 7.COMMON ANODE 8.COMMON CATHODE 8.ANODE 8.ANODE/CATHODE 8.COMMON ANODE 9.ANODE/CATHODE 9.ANODE 9.ANODE/CATHODE 9.ANODE/CATHODE 10.ANODE/CATHODE 10.ANODE 10.ANODE/CATHODE 10.ANODE/CATHODE 11.ANODE/CATHODE 11.ANODE 11.COMMON CATHODE 11.NO CONNECTION 12.ANODE/CATHODE 12.ANODE 12.COMMON ANODE 12.ANODE/CATHODE 13.NO CONNECTION 13.ANODE 13.ANODE/CATHODE 13.ANODE/CATHODE 14.COMMON ANODE 14.ANODE 14.ANODE/CATHODE 14.COMMON CATHODE Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SOIC−14 NB PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−14 WB CASE 948G 14 ISSUE C DATE 17 FEB 2016 1 SCALE 2:1 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER 0.10 (0.004) M T U S V S ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. N MOLD FLASH OR GATE BURRS SHALL NOT 0.25 (0.010) EXCEED 0.15 (0.006) PER SIDE. 14 8 4. DIMENSION B DOES NOT INCLUDE 2XL/2 INTERLEAD FLASH OR PROTRUSION. M INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR −U− N PROTRUSION. ALLOWABLE DAMBAR PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL IDENT. F IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 1 7 DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. 0.15 (0.006) T U S A K MILLIMETERS INCHES −V− K1 DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 ÇÉÇÉÇÉ B 4.30 4.50 0.169 0.177 J J1 C −−− 1.20 −−− 0.047 ÇÉÇÉÇÉ D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 SECTION N−N G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 −W− J1 0.09 0.16 0.004 0.006 C K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 0.10 (0.004) L 6.40 BSC 0.252 BSC M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) −T− SEATING D G H DETAIL E PLANE GENERIC MARKING DIAGRAM* 14 SOLDERING FOOTPRINT XXXX XXXX 7.06 ALYW(cid:2) (cid:2) 1 1 A = Assembly Location L = Wafer Lot Y = Year W = Work Week 0.65 (cid:2) = Pb−Free Package PITCH (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. 01.34X6 14X Pb−Free indicator, “G” or microdot “ (cid:2)”, 1.26 DIMENSIONS: MILLIMETERS may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASH70246A Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: TSSOP−14 WB PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

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