Freescale Semiconductor Document Number: MC33897 Technical Data Rev. 18.0, 4/2012 Single Wire CAN Transceiver 33897 The 33897 series provides a physical layer for digital communication using a Carrier Sense Multiple Access/Collision Resolution (CSMA/CR) data link operating over a single wire medium. This is more commonly referred to as single-wire Controller Area Network (SWCAN). SINGLE-WIRE CAN TRANSCEIVER The 33897 series operates directly from a vehicle's 12 V battery system or a broad range of DC-power sources. It can operate at low or high (33.33 kbps or 83.33 kbps) data rates. A high-voltage wake-up feature allows the device to control the regulator used in support of the MCU and other logic. The device includes a control pin that can be used to put the module regulator into Sleep mode. The presence of a defined wake-up voltage level on the bus will reactivate the control line to turn the regulator and the system back ON. The device complies with the GMW3089v2.4 General Motors EF (PB-FREE) SUFFIX Corporation specification. 98ASB42565B 14-PIN SOICN Features • Waveshaping for low Electromagnetic Interference (EMI) ORDERING INFORMATION • Detects and automatically handles loss of ground Temperature • Worst-case Sleep mode current of only 60 μA Device Range (T ) Package A • Current limit prevents damage due to bus shorts MCZ33897TEF/R2 • Built-in thermal shutdown on bus output -40 to 125 °C 14 SOICN • Protected against vehicular electrical transients *MC33897CTEF/R2 • Under-voltage lockout prevents false data with low battery *Recommended device for all new designs Power source Voltage Battery Regulator EN 33897 CNTL VBATT V CC TXD MCU RXD BUS SWC Bus MODE 0 LOAD MODE 1 GND 4 Figure 1. 33897 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2006 - 2012. All rights reserved.

DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Variations Part No. Load Voltage Sleep Mode See Page 33897T 1.0 V Max 7 *33897CT 0.1 V Max 7 *Recommended device for all new designs 33897 Analog Integrated Circuit Device Data 2 Freescale Semiconductor

INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM TTXXDB BuUsSD DRRVVRR MODE0 HHVVWWUUEnEnable BUS MODE1 Mode WWaavveeSshhaappininggEnEnable Mode Control Control TTXXDDat Daata DDiissaabblele BBuUsSR RCCVVRR HHVVWWUUDDeettect RRXXDDaDtaata DDiissaabblele TXD RXD Undervoltage VBBAATTT Detect Timer Timers OSC LoadSwitch LOAD GND CCNNTTLL Figure 2. 33897 Simplified Internal Block Diagram 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 3

PIN CONNECTIONS PIN CONNECTIONS 33897 GND 1 14 GND TXD 2 13 NC MODE0 3 12 BUS MODE1 4 11 LOAD RXD 5 10 VBATT NC 6 9 CNTL GND 7 8 GND Figure 3. 33897 Pin Connections Table 2. Pin Definitions A functional description of each pin can be found in the Functional Pin Description section, beginning on page 12. 33897 Pin Pin Name Formal Name Definition 1, 7, 8, 14 GND Ground Electrical Common Ground and Heat removal. A good thermal path will also reduce the die temperature. 2 TXD Transmit Data Data input here will appear on the BUS pin. A logic [0] will assert the bus, a logic [1] will make the bus go to the recessive state. 3, 4 MODE0, Mode Control These Pins control Sleep mode, Transmit Level, and Speed. They have weak pull- MODE1 downs. 5 RXD Receive Data Open drain output of the data on BUS. A recessive bus = a logic [1], a dominant bus = logic [0]. An external pull-up is required. 6, 13 NC No Connect No internal connection to these Pins. Pin 13 can be connected to GND. 9 CNTL Control Provides a battery level logic signal. 10 VBATT Battery Power input. An external diode is needed for reverse battery protection. 11 LOAD Load The external bus load resistor connects here to prevent bus pull-up in the event of loss of module ground. 12 BUS Bus This pin connects to the bus through external components. 33897 Analog Integrated Circuit Device Data 4 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit Electrical Ratings Supply Voltage V - 0.3 to 40 V BATT Input Logic Voltage V - 0.3 to 7.0 V IN RXD Pin Voltage V - 0.3 to 7.0 V RXD CNTL Pin Voltage V - 0.3 to 40 V CNTL ESD Voltage(1) V V ESD Human Body Model All Pins Except BUS ± 2000 BUS Pin ± 4000 Machine Model ± 100 Thermal Ratings Ambient Operating Temperature(1) TA - 40 to 125 °C Junction Operating Temperature TJ - 40 to 150 °C Storage Temperature T - 55 to 150 °C STG Junction-to-Ambient Thermal Resistance R 150 °C/W θJA Peak Package Reflow Temperature During Reflow (2), (3) T Note 3. °C PPRT Notes 1. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), Machine Model (C = 200 pF, R = 0 Ω). ZAP ZAP 2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 5

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions of -40 °C ≤ T ≤ 125 °C, unless otherwise stated. Voltages are relative to GND, unless A otherwise noted. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max Unit GENERAL Quiescent Current Sleep 5.0 V ≤ VBATT ≤ 13 V (4) IQSLP – 45 60 μA Awake with Transmitter Disabled 5.0 V ≤ V ≤ 26.5 V I – – 4.0 mA BATT QATDIS Awake with Transmitter Enabled mA 5.0 V ≤ V ≤ 26.5 V I – – 9.0 BATT QATEN Under-voltage Shutdown V 4.0 – 5.0 V BATTUV Under-voltage Hysteresis V 0.1 – 0.5 V UVHYS Thermal Shutdown (5) T °C SD 5.0 V ≤ VBATT ≤ 26.5 V 150 – 190 Thermal Shutdown Hysteresis (5) T °C SDHYS 5.0 V ≤ VBATT ≤ 26.5 V 10 – 20 LOGIC I /O, MODE0, MODE1, TXD, RXD Logic Input Low Level (MODE0, MODE1, and TXD) V V IL 5.0 V ≤ VBATT ≤ 26.5 V – – 0.8 Logic Input High Level (MODE0, MODE1, and TXD) V V IH 5.0 V ≤ VBATT ≤ 26.5 V 2.0 – – Mode Pin Pull-down Current (MODE0 and MODE1) I μA PD Pin Voltage = 0.8 V, 5.0 V ≤ VBATT ≤ 26.5 V 10 – 50 Receiver Output Low (RXD) V V OL IIN = 2.0 mA, 5.0 V ≤ VBATT ≤ 26.5 V – – 0.45 CNTL CNTL Output Low V V OLCNTL IIN = 5.0 μA, 5.0 V ≤ VBATT ≤ 26.5 V – – 0.8 CNTL Output High V V OHCNTL IOUT = 180 μA, 5.0 V ≤ VBATT ≤ 26.5 V VBATT - 0.8 – VBATT Notes 4. After t CNTLFDLY 5. Thermal shutdown causes the BUS output driver to be disabled. Guaranteed by characterization. 33897 Analog Integrated Circuit Device Data 6 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions of -40 °C ≤ T ≤ 125 °C, unless otherwise stated. Voltages are relative to GND, unless A otherwise noted. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max Unit LOAD LOAD Voltage Rise (6) V V LDRISE Normal Speed and Voltage Mode, Transmit High- Voltage Mode, Transmit High Speed Mode IIN = 1.0 mA, 5.0 V ≤ VBATT ≤ 26.5 V – – 0.1 Sleep Mode IIN = 7.0 mA 33897T – – 1.0 I = 7.0 mA (7) 33897CT – – 0.1 IN Loss of Battery I = 7.0 mA – – 1.0 IN LOAD Leakage During Loss of Module Ground (8) I μA LDLEAK 0.0 V ≤ VBATT ≤ 18 V 33897T 0.0 – - 90 0.0 V ≤ VBATT ≤ 18 V 33897CT -10 – 10 BUS Passive Out BUS Leakage μA Passive In I LEAK 0.0 V ≤ VBATT ≤ 26.5 V, -1.5 V ≤ VBUS < 0 V -5.0 – 5.0 Active In I LKAI 0.0 V ≤ VBATT ≤ 26.5 V, 0 V < VBUS ≤ 12.5 V -5.0 – 5.0 BUS Leakage During Loss of Module Ground (9) 0.0 V ≤ V ≤ 18 V 33897T I -10 – 10 BATT BLKLOG 0.0 V ≤ V ≤ 18 V 33897CT 0.0 – -90 BATT High Voltage Wake-up Mode Output High Voltage V 12 V ≤ V ≤ 26.5 V, 200 Ω ≤ R ≤ 3332 Ω BATT L 33897T V 9.7 – 12.5 HVWUOHF 33897CT V 9.9 – 12.5 HVWUOHO 5.0 V ≤ VBATT < 12 V, 200 Ω ≤ RL ≤ 3332 Ω Lesser of VBAT - – VBATT 1.5 or 9.7 High Speed Mode Output High Voltage V V OHHS 8.0 V ≤ VBATT ≤ 16 V, 75 Ω ≤ RL ≤ 135 Ω 4.2 – 5.1 Normal Mode Output High Voltage V 6.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω VNOHF 4.4 – 5.1 5.0 V ≤ VBATT < 6.0 V, 200 Ω ≤ RL ≤ 3332 Ω VNOHO Lesser of VBATT - – Lesser of VBATT 1.6 or 4.4 or 5.1 Notes 6. GMW3089V2.4 specifies the maximum load voltage rise to be 0.1 V whenever module battery is intact, including when in Sleep mode. The maximum load voltage rise of 1.0 V in Sleep mode is a GM-approved exception to GMW3089V2.4. 7. 33897CT removes the diode drop during Sleep mode. 8. LOAD pin is at system ground voltage. 9. BUS pin is at system ground voltage 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 7

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions of -40 °C ≤ T ≤ 125 °C, unless otherwise stated. Voltages are relative to GND, unless A otherwise noted. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max Unit BUS (CONTINUED) BUS Low Voltage V V OL 5.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω - 0.2 – 0.2 Short-circuit BUS Output Current I mA BSC Dominant State, 5.0 V ≤ VBATT ≤ 26.5 V -350 – - 100 Input Threshold V Awake 5.0 V ≤ VBATT ≤ 26.5 V VBIA 2.0 – 2.2 Sleep 12 V ≤ VBATT ≤ 26.5 V VBISF 6.6 – 7.9 Sleep Lesser of 6.6 V or – Lesser of 7.9 V or V 5.0 V ≤ VBATT < 12 V BISO VBATT - 4.3 VBATT - 3.25 33897 Analog Integrated Circuit Device Data 8 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions of -40 °C ≤ T ≤ 125 °C, unless otherwise stated. Voltages are relative to GND unless A otherwise noted. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max Unit BUS Normal Speed Rising Output Delay t μs DLYNORMRO 200 Ω ≤ RL ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs 2.0 – 6.3 Measured from TXD = V to V as follows: IL BUS Max Time to V = 3.7 V, 6.0 V ≤ V ≤ 26.5 V (10) BUSMOD BATT Min Time to V = 1.0 V, 6.0 V ≤ V ≤ 26.5 V (10) BUSMOD BATT Max Time to V = 2.7 V, V = 5.0 V (10) BUSMOD BATT Min Time to V = 1.0 V, V = 5.0 V (10) BUSMOD BATT Normal Speed Falling Output Delay t μs DLYNORMFO 200 Ω ≤ RL ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs 1.8 – 8.5 Measured from TXD = V to V as follows: IH BUS Max Time to V = 1.0 V, 6.0 V ≤ V ≤ 26.5 V (10) BUSMOD BATT Min Time to V = 3.7 V, 6.0 V ≤ V ≤ 26.5 V (10) BUSMOD BATT Max Time to V = 1.0 V, V = 5.0 V (10) BUSMOD BATT Min Time to V = 2.7 V, V = 5.0 V (10) BUSMOD BATT High Speed Rising Output Delay t μs DLYHSRO 75 Ω ≤ RL ≤ 135 Ω, 0.0 μs ≤ Load Time Constants ≤ 1.5 μs, 0.1 – 1.7 8.0 V ≤ VBATT ≤ 16 V Measured from TXD = V to V as follows: IL BUS Max Time to V = 3.7 V (11) BUS Min Time to V = 1.0 V (11) BUS High Speed Falling Output Delay t μs DLYHSFO 75 Ω ≤ RL ≤ 135 Ω, 0.0 μs ≤ Load Time Constants ≤ 1.5 μs, 0.04 – 3.0 8.0 V ≤ V ≤ 16 V BATT Measured from TXD = V to V as follows: IH BUS Max Time to V = 1.0 V (11) BUS Min Time to V = 3.7 V (11) BUS Notes 10. V is the voltage at the BUSMOD node in Figure 6, page 13. BUSMOD 11. V is the voltage at the BUS pin in Figure 7, page 14. BUS 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 9

ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions of -40 °C ≤ T ≤ 125 °C, unless otherwise stated. Voltages are relative to GND unless A otherwise noted. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max Unit BUS (CONTINUED) High Voltage Rising Output Delay t μs DLYHVRO 200 Ω ≤ R ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs L Measured from TXD=V to V as follows: IL BUS Max Time to V = 3.7 V, 6.0 V ≤ V ≤ 26.5 V (12) 2.0 – 6.3 BUSMOD BATT 2.0 – 6.3 Min Time to V = 1.0 V, 6.0 V ≤ V ≤ 26.5 V (12) BUSMOD BATT 2.0 – 18 Max Time to V = 9.4 V, 12.0 V ≤ V ≤ 26.5 V (12) BUSMOD BATT High Voltage Falling Output Delay t μs DLYHVFO 200 Ω ≤ R ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs, L 12.0 V ≤ V ≤ 26.5 V BATT Measured from TXD=V to V as follows: IH BUS Max Time to V = 1.0 V (12) 1.8 – 14 BUSMOD Min Time to V = 3.7 V (12) 1.8 – 14 BUSMOD RECEIVER RXD Receive Delay Time (5.0 V ≤ VBATT ≤ 26.5 V) t RDLY μs Awake 0.2 – 1.0 Receive Delay Time (BUS Rising to RXD Falling, 5.0 V ≤ VBATT ≤ 26.5 V) t RDLYSL μs Sleep 10 – 70 CNTL CNTL Falling Delay Time (5.0 V ≤ VBATT ≤ 26.5 V) t CNTLFDLY 300 – 1000 ms Notes 12. V is the voltage at the BUSMOD node in Figure 6, page 13. BUSMOD 33897 Analog Integrated Circuit Device Data 10 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS t t DLYNORMFO DLYNORMRO V IH TXD V IL V NOHF V BUSMOD* Bus V V BIA BIA V BUSMOD* V IH RXD V IL t t RDLY RDLY * V is the voltage at the BUSMOD node in Figure7. BUSMOD Figure 4. TXD, Bus and RXD Waveforms in Normal Mode tDLYHSFO TDLYHSRO V IH TXD V IL V NOHF V BUS * Bus V V BIA BIA V BUS * V IH RXD V IL t t RDLY RDLY * V is the voltage at the BUS pin in Figure8. BUS Figure 5. TXD, Bus and RXD Waveforms in High Speed Mode 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 11

FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33897 Series is intended for use as a physical layer system communications where the radiated EMI of the higher device in a Single Wire CAN communications bus. rate could be an issue. Communications takes place from a single pin over a single Two pins control the mode of operation (sleep, low speed, wire using a common ground for a current return path. Two high speed, and high voltage wake-up). data rates are available, with the high rate used for factory or assembly line communications and the lower for actual FUNCTIONAL PIN DESCRIPTION The 33897 Series is intended to be used with an MCU to MCU comes out of reset, before the driving signals have control its operation and to process and generate the data for been configured as outputs. the bus. RXD DATA GROUND PINS The data received on the bus is translated to logic levels The four ground pins are not only for electrical conduction, on this pin. This pin is a logic high when the bus is in the their number and locations at each of the four corners serve recessive state (near zero volts) and is logic low when the also to remove heat from the IC. The biggest benefit of this is bus is in either the normal or high voltage dominant state. obtained by putting a lot of copper on the PCB in this area This is an open-drain type of output that requires an and, if ground is an internal layer, by adding numerous external resistor to pull it up. When the device is in sleep plated-through connections to it with the largest diameter mode, the output will be off unless a high voltage wake-up holes the layout can use. level is detected on the bus. If the wake-up level is detected, the output will be driven by the data on the bus. If the level of TXD DATA the data returns to normal level, the output will return to off The data driven onto the SWCAN bus is inverted from the after a short delay unless a non-sleep mode condition is set TXD pin. A “1” driven on TXD will result in an undriven by the MCU. (recessive) state (bus at near zero volts). When the TXD pin is low, the output goes to a driven state. The voltage and LOAD SWITCH waveshaping in the driven state is determined by the levels This switch is ON in all operating modes unless a loss of on the MODE0 and MODE1 Pins (refer to Table 6). ground is detected. If this happens, the switch is opened and the resistor normally attached to its pin will no longer pass Table 6. Mode Control Logic Levels current to or from the bus. Logic Level Operation MODE0 MODE1 CNTL OUTPUT 0 0 Sleep mode This logic level signal is used to control a V regulator. CC When the output is low, the V regulator is expected to 0 1 High voltage wake-up mode CC shutdown. This is normally used to shut down the MCU and 1 0 High speed mode all the devices powered by V when the IC is in Sleep mode. CC This is done to save power. When the part is taken out of the 1 1 Normal mode Sleep mode by the higher than normal bus voltage, this pin is asserted high and the V regulator brings its output up to the MODE CONTROL CC regulated level. This starts the MCU, which controls the mode The MODE pins control the transmitter filtering and BUS of the IC. The MCU must change the mode signals to non- voltage and the IC Sleep mode operation. Table 6 shows the Sleep mode levels in order to keep this pin from going low. mode versus the logic levels on MODE0 and MODE1. There is a delay to allow the MCU to fully wake-up and take The MODE0 and MODE1 pins have a weak pull-down in control after the high voltage signaling is removed before the the IC so that in case the pins are not driven, the device will level on this output returns low. After a delay time, even if the enter the Sleep mode. This is usually the situation as the bus is at high voltage, the IC will return to Sleep mode if both MODE pins are low. 33897 Analog Integrated Circuit Device Data 12 Freescale Semiconductor

FUNCTIONAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM COMPONENTS VBATT INPUT BUS I /O This power input is not reverse battery protected and This input / output may require electrostatic discharge should use an external diode to protect it from damage due (ESD) and /or EMI external circuitry. A set of components is to reverse battery if this protection is desired. The voltage shown in the simplified application diagrams on page 15. The drop of the diode must be taken into consideration when the value of the capacitor should be adjusted downward in direct operating range of the system is being determined. This proportion to the added capacitance of the ESD or EMI diode is generally used to protect the entire module from circuits. The series resistance of the inductor should be kept reverse battery and should be selected accordingly. below 3.5 Ω to prevent its voltage drop from significantly degrading system noise margins. FUNCTIONAL BLOCK DIAGRAM COMPONENTS TIMER OSC TXD BUS DRVR This circuit generates a 500 kHz signal to be used for This circuit drives the BUS. It can drive it with the higher internal logic. It is the reference for some of the required voltage wake-up signals when enabled by the Mode Control delays. circuit. It can also provide waveshaping for reduced EMI or not provide it for the higher data rate mode. The actual data TIMERS is received on TXD at CMOS logic levels, then translated by this circuit to the necessary operating voltages. This circuit contains the timing logic used to hold the CNTL active for the required time after the conditions for sleep UNDER-VOLTAGE DETECT mode have been met. It is also used to keep the TXD driver active for a period of time after it has generated a passive This circuit monitors internal operating voltage to assure level on the bus. proper operation of the part. If a low-voltage condition is detected, it sends a signal to disable the BUS RCVR and MODE CONTROL TXD BUS DRVR circuits. This prevents incorrect data from being put on the bus or sent to the MCU. This circuit contains the control logic for the various operating modes and conditions required for the IC. LOAD SWITCH BUS RCVR The LOAD switch provides a path for an external resistor connected to the BUS to be connected to ground. When a This circuit translates the levels on the BUS pin to a CMOS loss of ground is detected, this switch is opened to prevent level indicating the presence of a logic [0] or a logic [1]. It also the current that would normally be flowing to the ground from determines the presence of a high voltage wake-up (HVWU) the module from going back through the load resistor and signal that is passed to Mode Control and Timers circuits. An raising the bus level. The circuit is opened when the voltage analog filter is used to “de-glitch” the high voltage wake-up between GND and VBATT becomes too low as would be the signal and prevent false exits from the Sleep mode. case if module ground were lost. BUS LOADING PARAMETERS V BATT 100 pF 1.0 kΩ 33897 47 μH BUSMOD BUS 6.49kΩ 6.49 kΩ C = 100pF + (n-1) 220pF R= NOM (n-1) LOAD GND Note: The letter ’n’ represents the number of nodes in the system. Figure 6. Transmitter Delays in Normal and Transmit High Voltage Wake-up Modes 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 13

FUNCTIONAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM COMPONENTS 33897 BUS 6.49kΩ 6.49 kΩ 130 Ω CNOM = (n) 220pF R= (n-1) LOAD GND Note: The letter ’n’ represents the number of nodes in the system. Figure 7. Transmitter Delays in Transmit High Speed Mode 33897 Analog Integrated Circuit Device Data 14 Freescale Semiconductor

TYPICAL APPLICATIONS TYPICAL APPLICATIONS The 33897 can be used in applications where the module bus. This wake-up voltage will activate the CNTL line, which includes a regulator that has the capability of going into Sleep enables the regulator and turns the module back ON. This mode by having an Enable pin. See Figure 8. When the feature allows the module to be more energy efficient since module’s regulator is in Sleep mode, the module is turned off. the current consumption is significantly lowered when it goes The module waits for a defined wake-up voltage level on the into sleep mode. V Power Battery CC Source Voltage 100nF 4.7μF 100pF Regulator EN VBATT 1.0kΩ CNTL V 10kΩ 2.7kΩ CC 47μH TXD BUS SWC BUS 47pF RXD MCU MODE0 LOAD 6.49kΩ MODE1 4 GND 33897 Figure 8. 33897 Typical Application Schematic 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 15

PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important: For the most current Package revision, visit www.freescale.com and perform a Keyword Search on the 98ASB42565B drawing number below. Dimensions shown are provided for reference ONLY. EF (Pb-FREE) SUFFIX 14-pin SOICN 98ASB42565B ISSUE J 33897 Analog Integrated Circuit Device Data 16 Freescale Semiconductor

PACKAGING PACKAGE DIMENSIONS EF (Pb-FREE) SUFFIX 14-pin SOICN 98ASB42565B ISSUE J 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 17

REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 9.0 5/2005 • Converted to Freescale format • Added A & B Versions • Updated Device Variation Table, and Note “* Recommended device for all new designs” • Added EF (Pb-Free) Devices, and higher soldering temperature 10.0 8/2005 • Implemented Revision History page • Updated Simplified Application Diagrams • Updated Typical Application Schematic 11.0 12/2005 • Added 33897C and D versions and Timing Diagrams 12.0 1/2006 • Updated Table 4, Static Electrical Characteristics - LOAD and BUS parameters • Updated Ordering Information. 13.0 6/2006 • Removed “Unless otherwise noted” from Static Electrical Characteristics & Dynamic Electrical Characteristics table introductions 14.0 8/2006 • Added Part Numbers MC33897TD and MC33897TEF to Ordering Information on Page 1. • Added 33897T to Table 1, Device Variations on Page 3, Referencing Electrical Changes per Errata MC33897TER, Revision 3 and specifying ESD variations 15.0 10/2006 • Removed Part Numbers MC33897TD/R2, MC33897TEF/R2, MC33897CLEF/R2, PC33897CLEF/ R2, MC33897DLEF/R2, and PC33897DLEF/R2 • Added Part Numbers MCZ33897EF/R2, MCZ33897TEF/R2, MCZ33897AEF/R2, MCZ33897CEF/ R2, MCZ33897BEF/R2, and MCZ33897DEF/R2 to the Ordering Information block on Page 1. • Updated Device Variations on page 2 for “T” suffix products • Split out Human Body Model on page 5 to differentiate between T and non-T versions • Added Under-voltage Hysteresis on page 6 • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 5. Added note with instructions to obtain this information from www.freescale.com. 16.0 6/2007 • Removed watermark, “Advance Information” from page 1. 17.0 1/2011 • Improved HBM ESD All Pins Except BUS to ±2.0 kV on MC33897CT • Added MC33897CTEKF/R2 to the ordering information • Removed all 8-Pin SOICN device information • Changed Short-circuit BUS Output Current to -100 mA (Approved by GM) 18.0 4/2012 • Updated Quiescent Current IQSLP to 60 μA max. 33897 Analog Integrated Circuit Device Data 18 Freescale Semiconductor

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