MC33077 Low Noise Dual Operational Amplifier The MC33077 is a precision high quality, high frequency, low noise monolithic dual operational amplifier employing innovative bipolar design techniques. Precision matching coupled with a unique analog http://onsemi.com resistor trim technique is used to obtain low input offset voltages. Dual−doublet frequency compensation techniques are used to enhance the gain bandwidth product of the amplifier. In addition, the MC33077 MARKING DIAGRAMS offers low input noise voltage, low temperature coefficient of input offset voltage, high slew rate, high AC and DC open loop voltage gain 8 and low supply current drain. The all NPN transistor output stage SOIC−8 exhibits no deadband cross−over distortion, large output voltage 8 D SUFFIX 33077 ALYW swing, excellent phase and gain margins, low open loop output 1 CASE 751 impedance and symmetrical source and sink AC frequency 1 performance. 8 The MC33077 is available in plastic DIP and SOIC−8 packages (P and D suffixes). PDIP−8 MC33077P P SUFFIX AWL Features 8 CASE 626 YYWW • (cid:4) 1 Low Voltage Noise: 4.4 nV/ Hz @ 1.0 kHz 1 • Low Input Offset Voltage: 0.2 mV A = Assembly Location • Low TC of Input Offset Voltage: 2.0 (cid:5)V/°C WL, L = Wafer Lot • YY, Y = Year High Gain Bandwidth Product: 37 MHz @ 100 kHz WW, W = Work Week • High AC Voltage Gain: 370 @ 100 kHz 1850 @ 20 kHz PIN CONNECTIONS • Unity Gain Stable: with Capacitance Loads to 500 pF • High Slew Rate: 11 V/(cid:5)s • Output 1 1 8 VCC Low Total Harmonic Distortion: 0.007% • Large Output Voltage Swing: +14 V to −14.7 V - • 2 1 7 Output 2 High DC Open Loop Voltage Gain: 400 k (112 dB) + • High Common Mode Rejection: 107 dB Inputs 1 • 3 6 Low Power Supply Drain Current: 3.5 mA - • Dual Supply Operation: ±2.5 V to ±18 V 2 Inputs 2 • Pb−Free Package is Available VEE 4 + 5 (Dual, Top View) ORDERING INFORMATION Device Package Shipping† MC33077D SOIC−8 98 Units/Rail MC33077DR2 SOIC−8 2500 Tape & Reel MC33077DR2G SOIC−8 2500 Tape & Reel (Pb−Free) MC33077P PDIP−8 50 Units/Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.  Semiconductor Components Industries, LLC, 2004 1 Publication Order Number: March, 2004 − Rev. 5 MC33077/D

MC33077 R1 R6 R8 R11 R16 VCC Q1 Q8 Q17 Q13 D3 Q19 k or C3 Q11 w C1 Net R3 R9 Q14 J1 Bias Q6 Z1 D4 D6 Q21 R13 Neg Q7 Q9 Pos Q16 R17 R18 Vout C6 Q2 Q12 R14 D7 R19 Q10 Q4 R5 C2 C7 D1 C8 Q22 Q1 Q5 R4 R7 R10 R12 Q20 R20 D5 R2 R15 D2 VEE Figure 1. Representative Schematic Diagram (Each Amplifier) MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage (VCC to VEE) VS +36 V Input Differential Voltage Range VIDR (Note 1) V Input Voltage Range VIR (Note 1) V Output Short Circuit Duration (Note 2) tSC Indefinite sec Maximum Junction Temperature TJ +150 °C Storage Temperature Tstg −60 to +150 °C ESD Protection at any Pin Vesd V − Human Body Model 550 − Machine Model 150 Maximum Power Dissipation PD (Note 2) mW Operating Temperature Range TA −40 to + 85 °C Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. Functional operation should be restricted to the Recommended Operating Conditions. 1. Either or both input voltages should not exceed VCC or VEE (See Applications Information). 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (See power dissipation performance characteristic, Figure 2). http://onsemi.com 2

MC33077 DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Input Offset Voltage (RS = 10 (cid:4), VCM = 0 V, VO = 0 V) |VIO| mV TA = +25°C − 0.13 1.0 TA = −40° to +85°C − − 1.5 Average Temperature Coefficient of Input Offset Voltage (cid:3)VIO/(cid:3)T (cid:5)V/°C RS = 10 (cid:4), VCM = 0 V, VO = 0 V, TA = −40° to +85°C − 2.0 − Input Bias Current (VCM = 0 V, VO = 0 V) IIB nA TA = +25°C − 280 1000 TA = −40° to +85°C − − 1200 Input Offset Current (VCM = 0 V, VO = 0 V) IIO nA TA = +25°C − 15 180 TA = −40° to +85°C − − 240 Common Mode Input Voltage Range ((cid:3)VIO ,= 5.0 mV, VO = 0 V) VICR ±13.5 ±14 − V Large Signal Voltage Gain (VO = ±1.0 V, RL = 2.0 k(cid:4)) AVOL kV/V TA = +25°C 150 400 − TA = −40° to +85°C 125 − − Output Voltage Swing (VID = ±1.0 V) V RL = 2.0 k(cid:4) VO+ +13.0 +13.6 − RL = 2.0 k(cid:4) VO− − −14.1 −13.5 RL = 10 k(cid:4) VO+ +13.4 +14.0 − RL = 10 k(cid:4) VO− − −14.7 −14.3 Common Mode Rejection (Vin = ±13 V) CMR 85 107 − dB Power Supply Rejection (Note 3) PSR dB VCC/VEE = +15 V/ −15 V to +5.0 V/ −5.0 V 80 90 − Output Short Circuit Current (VID = ±1.0 V, Output to Ground) ISC mA Source +10 +26 +60 Sink −20 −33 +60 Power Supply Current (VO = 0 V, All Amplifiers) ID mA TA = +25°C − 3.5 4.5 TA = −40° to +85°C − − 4.8 3. Measured with VCC and VEE simultaneously varied. http://onsemi.com 3

MC33077 AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Slew Rate (Vin = −10 V to +10 V, RL = 2.0 k(cid:4), CL = 100 pF, AV = +1.0) SR 8.0 11 − V/(cid:5)s Gain Bandwidth Product (f = 100 kHz) GBW 25 37 − MHz AC Voltage Gain (RL = 2.0 k(cid:4), VO = 0 V) AVO V/V f = 100 kHz − 370 − f = 20 kHz − 1850 − Unity Gain Bandwidth (Open Loop) BW − 7.5 − MHz Gain Margin (RL = 2.0 k(cid:4), CL = 10 pF) Am − 10 − dB Phase Margin (RL = 2.0 k(cid:4), CL = 10 pF) ∅m − 55 − Deg Channel Separation (f = 20 Hz to 20 kHz, RL = 2.0 k(cid:4), VO = 10 Vpp) CS − −120 − dB Power Bandwidth (VO = 27p−p, RL = 2.0 k(cid:4), THD ≤ 1%) BWp − 200 − kHz Distortion (RL = 2.0 k(cid:4)(cid:2) THD % AV = +1.0, f = 20 Hz to 20 kHz VO = 3.0 VRMS − 0.007 − AV = 2000, f = 20 kHz VO = 2.0 Vpp − 0.215 − VO = 10 Vpp − 0.242 − AV = 4000, f = 100 kHz VO = 2.0 Vpp − 0.3.19 − VO = 10 Vpp − 0.316 − Open Loop Output Impedance (VO = 0 V, f = fU) |ZO| − 36 − (cid:4) Differential Input Resistance (VCM = 0 V) Rin − 270 − k(cid:4) Differential Input Capacitance (VCM = 0 V) Cin − 15 − pF Equivalent Input Noise Voltage (RS = 100 (cid:4)) en nV/√Hz f = 10 Hz − 6.7 − f = 1.0 kHz − 4.4 − Equivalent Input Noise Current (f = 1.0 kHz) in pA/√Hz f = 10 Hz − 1.3 − f = 1.0 kHz − 0.6 − W) 2400 800 m SSIPATION ( 21060000 RRENT (nA) 600 VTAC M= =25 0° CV DI U WER 1200 MC33077P AS C 400 O BI P T XIMUM 800 MC33077D , INPUB 200 MA 400 II , X) A 0 0 D(M -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0 2.5 5.0 7.5 10 12.5 15 17.5 20 P TA, AMBIENT TEMPERATURE (°C) VCC, |VEE|, SUPPLY VOLTAGE (V) Figure 2. Maximum Power Dissipation Figure 3. Input Bias Current versus Temperature versus Supply Voltage http://onsemi.com 4

MC33077 1000 1.0 VCC = +15 V mV) A) 800 VEE = -15 V E ( NT (n VCM = 0 V LTAG 0.5 E O CURR 600 SET V 0 S F , INPUT BIAB 420000 (cid:4)(cid:2), INPUT OFO -0.5 VRVVCECSECM = == =1 -0+01 1 (cid:4)V55 VV II VI AV = +1.0 0 -1.0 -55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 4. Input Bias Current Figure 5. Input Offset Voltage versus Temperature versus Temperature V) 600 GE ( VCC 0.0 N RRENT (nA)540000 VVTACE EC= ==2 5-+°11C55 VV E VOTAGE RA VVVCCCCCC ---011...505 +VCM VCC = +3.0 V to +15 V S CU300 MOD VIonltpaugte (cid:3)VE VE IO= -=3 5.0.0 V m tVo -15 V UT BIA200 MMON VEE +1.5 Range VO = 0 V , INPIIB100 NPUT CO VVEEEE ++10..05 -VCM 0 , IR VEE +0.0 -15 -10 -5.0 0 5.0 10 15 C -55 -25 0 25 50 75 100 125 VI VCM, COMMON MODE VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C) Figure 6. Input Bias Current versus Figure 7. Input Common Mode Voltage Range Common Mode Voltage versus Temperature ATION VOLTAGE (V) VVVCCCCC C-- 240 -55°C 125°C 25°C VCC = +15 V RCUIT CURRENT (mA) 5400 Sink VVVRCEILD EC< = ==1 ± 0-+1011. 505(cid:4) VVV ATUR 125°C VEE = -15 V RT CI 30 Source S O TPUT VEE +4 25°C UT SH 20 V(cid:4)(cid:2) , OUsat VVEEEE + 200-55°C 0.5 1.0 1.5 2.0 2.5 3.0 (cid:4)(cid:3)|, OUTPSC10-55 -25 0 25 50 75 100 125 |I RL, LOAD RESISTANCE TO GROUND (k(cid:4)) TA, AMBIENT TEMPERATURE (°C) Figure 8. Output Saturation Voltage versus Figure 9. Output Short Circuit Current Load Resistance to Ground versus Temperature http://onsemi.com 5

MC33077 5.0 120 B) I(cid:4)(cid:3), SUPPLY CURRENT (mA)CC 4321....0000 ±15 V ±5.0 V VRVCOL M == =∞0 0V V MR, COMMON MODE REJECTION (d 16482000000 VV(cid:3)TVACEC VECM= C ===2M 5 - 0+°=1 C1V 5±5 V1 V.5 V CM(cid:3)R V C=M 20Log -+A(cid:3)(cid:3)D M VVCOM × A(cid:3)DM VO C 0 0 -55 -25 0 25 50 75 100 125 100 1.0 k 10 k 100 k 1.0 M 10 M TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (Hz) Figure 10. Supply Current Figure 11. Common Mode Rejection versus Temperature versus Frequency ON (dB) 112000 +PSR = 20Log (cid:3)(cid:3)V OV/CACDM -PSR = 20Log (cid:3)(cid:3)V OV/EAEDM CT (MHz) 4484 CfR =LL 1==0 1000 pk kFH(cid:4)z EJECTI 80 +PSR PRODU 40 TA = 25°C Y R -PSR TH PPL 60 WID 36 U D S N PSR, POWER 4200 VVTACE EC= ==2 5- +°1C155 V V -+ADM VVECEC (cid:3) VO GBW, GAIN BA 3228 0 24 100 1.0 k 10 k 100 k 1.0 M 0 5 10 15 20 f, FREQUENCY (Hz) VCC, |VEE|, SUPPLY VOLTAGE (V) Figure 12. Power Supply Rejection Figure 13. Gain Bandwidth Product versus Frequency versus Supply Voltage PRODUCT (MHz) 544062 fRCVV =CELL EC1== 0 ==100 0 - +kp 1k1HF5(cid:4)5 zV V GE (V)p 5211.0500 TA = 25°C Vp + RL = 10 kR(cid:4)L = 2.0 k(cid:4) H TA T L D 38 O 0 BANDWI 34 UTPUT V -5.0 Vp - N O -10 GAI 30 V,O RL = 2.0 k(cid:4) W, -15 GB 26 -20 RL = 10 k(cid:4) -55 -25 0 25 50 75 100 125 0 5.0 10 15 20 TA, AMBIENT TEMPERATURE (°C) VCC, |VEE|, SUPPLY VOLTAGE (V) Figure 14. Gain Bandwidth Product Figure 15. Maximum Output Voltage versus Temperature versus Supply Voltage http://onsemi.com 6

MC33077 30 1200 V/V) RL = 2.0 k(cid:4) GE (V)pp 2250 AIN (X1000 1080000 f(cid:3)T A= V =1O 02 =5H °z2C/3 (VCC -VEE) A G LT E O 15 G 600 V A UT VCC = +15 V OLT OUTP 10 RVEL E= =2 .-01 k5(cid:4) V OP V 400 V,O 5.0 ATVH D=+ ≤1 .10.0% N LO 200 E TA = 25°C OP 0 ,L 0 100 1.0 k 10 k 100 k 1.0 M O 0 5.0 10 15 20 V f, FREQUENCY (Hz) A VCC, |VEE|, SUPPLY VOLTAGE (V) Figure 16. Output Voltage Figure 17. Open Loop Voltage Gain versus Frequency versus Supply Voltage V) 600 80 V/ E GAIN (X1000 555000 VRf(cid:3)V =CEL V EC1= O 0 ==2 =H.-+0 1z1- k515(cid:4) 0 VV V to +10 V WDANCE ((cid:4)(cid:2)) 756000 VVVTACEO EC == == 20 5- +V°1C155 V V G E TA 450 MP 40 OL T I OP V 400 TPU 30 AV = 10 O U EN L 350 (cid:4)|, OO 20 AV = 1000 AV = 100 OP | Z 10 ,OL 300 0 AV = 1.0 AV -55 -25 0 25 50 75 100 125 100 1.0 k 10 k 100 k 1.0 M 10 M TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (Hz) Figure 18. Open Loop Voltage Gain Figure 19. Output Impedance versus Temperature versus Frequency 160 1.0 EL SEPARATION (dB) 111543000 (cid:3)ViMneasureme+-nt Channel (cid:3)VO R(cid:3)DVVTACELrVi ECv==O e ==D22 C 5.-+=0h°11 Ca2k55n0(cid:4) VVn Veplp MONIC DISTORTION (%) 0.1 VVCEEC == - +1155 V 1V 0T 0VA(cid:2)O k=(cid:4) =2 52°.20C. 0V(cid:2)kp(cid:4)p AVAA =VV +==1 ++01100000 N R AN 120 HA 0.01 RA - CS, CH 110 CS = 20 Log (cid:3)VOD TOTAL Vin + VO AV = +1.0 (cid:3)Vin HD, 100 T 0.001 10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 20. Channel Separation Figure 21. Total Harmonic Distortion versus Frequency versus Frequency http://onsemi.com 7

MC33077 1.0 1.0 C DISTORTION (%) 0.1 VTVVACE0 EC== ==2- 51-+°011C 55V VpVp AV = +1VR0inA00 1+-00(cid:2)k(cid:4) 2.V0O(cid:2)k(cid:4) C DISTORTION (%) 00..51 VVfT A=CE EC=2 0==2 5k-+AH°11VC5z5 = VV +1000 VRinA 1+-00(cid:2)k(cid:4) 2.V0O(cid:2)k(cid:4) RMONI AV = +100 RMONI 0.05 AV = +100 HD, TOTAL HA 0.01 AAVV == ++110.0 HD, TOTAL HA0.00.0051 AAVV = = + +110.0 T0.001 T0.001 10 100 1.0 k 10 k 100 k 0 2.0 4.0 6.0 8.0 10 12 f, FREQUENCY (Hz) VO, OUTPUT VOLTAGE (Vpp) Figure 22. Total Harmonic Distortion Figure 23. Total Harmonic Distortion versus Frequency versus Output Voltage 16 40 mW RATE (V/(cid:4)s) 81.20 VTAin == 225/3° C(VCC -VEE) mW RATE (V/(cid:3) s) 3200 (cid:3)VVCEVECin == = -+ 211055 V VV (cid:3)Vin -+2.0(cid:2)k(cid:4) 10V0O(cid:2)pF SR, SLE 4.0 (cid:3)Vin -+2.0(cid:2)k(cid:4) 10V0O(cid:2)pF SR, SLE 10 0 0 0 2.5 5.0 7.5 10 12.5 15 17.5 20 -55 -25 0 25 50 75 100 125 VCC, |VEE|, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C) Figure 24. Slew Rate versus Supply Voltage Figure 25. Slew Rate versus Temperature OPEN-LOOP VOLTAGE GAIN (dB),VOL111-462280000000 GPahinase RTVVACEL EC== ==22 5.-+0°11 Ck55(cid:4) VV 04811200260000f, EXCESS PHASE (DEGREES) A(cid:4), OPEN LOOP GAIN MARGIN (dB)m8642111....4200000 2-55°15C2°5C°C-15255°°CC 25V°inC VV-+2(cid:4)CE.EC0 (cid:2) =k= -+1155 VV CVLO PGhaainse 0123456000000f, PHASE MARGIN (DEGREES)m A -60 240 0 VO = 0 V 70 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M 1.0 10 100 1000 f, FREQUENCY (Hz) CL, OUTPUT LOAD CAPACITANCE (pF) Figure 26. Voltage Gain and Phase Figure 27. Open Loop Gain Margin and Phase versus Frequency Margin versus Output Load Capacitance http://onsemi.com 8

MC33077 70 100 VCC = +15 V GIN (DEGREES) 654000 CL =C L1 0=0 0 p pFF HOOT (%) 8600 (cid:3)Vin -+2(cid:4).0(cid:2)k 10V0O(cid:2)pF (cid:3)VEVEin = = - 11050 V mV MAR 30 VVCEEC == -+1155 VV CL = 300 pF ERS HASE 20 TA = 25°C CL = 500 pF os, OV 40 P - , m 10 Vin + VO 20 f 2.0k(cid:4) CL 125°C and 25°C -55°C 0 0 -10 -5.0 0 5.0 10 1 10 100 1000 VO, OUTPUT VOLTAGE (V) CL, OUTPUT LOAD CAPACITANCE (pF) Figure 28. Phase Margin versus Figure 29. Overshoot versus Output Voltage Output Load Capacitance √D NOISE VOLTAGE ((cid:4)(cid:4)(cid:4) )nV/Hz13215000000 CurrentTVVACE EC= ==2 5-+°11C55 VV 21153..0..0000 RED NOISE CURRENT (pA) √nV/HzD NOISE VOLTAGE ((cid:4)(cid:4) )1010000 VVVCEn EC(t o==t a-+l11) 55= V(cid:4)V(cid:4)(in(cid:4)Rs(cid:4))fT2 (cid:4)=A(cid:1)(cid:1) =1(cid:4) .20(cid:1)e5 kn°H2Cz(cid:1)(cid:1)(cid:1)4KTRS RE 5.0 0.5 ER RE 10 R F R UT REFE 23..00 Voltage 00..32 NPUT RE AL REFE (cid:4), INPn1.01.0 10 100 1.0 k 10 k 100 0k.1 i(cid:4),In (cid:4), TOTn1.010 100 1.0 k 10 k 100 k 1.0 M e f, FREQUENCY (Hz) VV RS, SOURCE RESISTANCE ((cid:4)) Figure 30. Input Referred Noise Voltage Figure 31. Total Input Referred Noise Voltage and Current versus Frequency versus Source Resistant 14 0 Gain V) VCC = +15 V B) 12 R1 10 EES) 0 V/DI AVVE E= =- 1-.105 V (cid:4), GAIN MARGIN (dm 8641...0000 Vin R2 -+ VO Phase VVCEEC == -+1155 VV 23450000 ASE MARGIN (DEGR UTPUT VOLTAGE (5. CTRALL === 2215.00°0 Ck p(cid:4)F A 2.0 RVTAOT === 2R05 1V° +C R2 60 f,PHm V(cid:4), OO 0 70 1.0 10 100 1.0 k 10 k t, TIME (2.0 (cid:5)s/DIV) RT, DIFFERENTIAL SOURCE RESISTANCE ((cid:4)) Figure 32. Phase Margin and Gain Margin Figure 33. Inverting Amplifier Slew Rate versus Differential Source Resistance http://onsemi.com 9

MC33077 V) VCC = +15 V V) V/DI VEE = -15 V V/DI GE (5.0 ARCVLL === +21.0100. 0k p(cid:4)F GE (5.0 CL = 100 pF OLTA TA = 25°C OLTA VCC = +15 V UT V UT V AVVE E= =+ 1-.105 V TP TP RL = 2.0 k(cid:4) OU OU TA = 25°C V , O V , O CL = 0 pF t, TIME (2.0 (cid:5)s/DIV) t, TIME (200 ns/DIV) Figure 34. Non−inverting Amplifier Slew Rate Figure 35. Non−inverting Amplifier Overshoot V) DI V/ n 0 0 1 E ( G A T L O V NOISE VVCEEC == -+1155 VV T BW = 0.1 Hz to 10 Hz NPU TA = 25°C e , In S(Feigeu Nreo i3s6e) Circuit t, TIME (1.0 sec/DIV) Figure 36. Low Frequency Noise Voltage versus Time http://onsemi.com 10

MC33077 APPLICATIONS INFORMATION The MC33077 is designed primarily for its low noise, low relation independent of its output voltage swing). Output offset voltage, high gain bandwidth product and large output phase symmetry degradation in the more conventional PNP swing characteristics. Its outstanding high frequency and NPN transistor output stage was primarily due to the gain/phase performance make it a very attractive amplifier for inherent cut−off frequency mismatch of the PNP and NPN high quality preamps, instrumentation amps, active filters and transistors used (typically 10 MHz and 300 MHz, other applications requiring precision quality characteristics. respectively), causing considerable phase change to occur as The MC33077 utilizes high frequency lateral PNP input the output voltage changes. By eliminating the PNP in the transistors in a low noise bipolar differential stage driving a output, such phase change has been avoided and a very compensated Miller integration amplifier. Dual−doublet significant improvement in output phase symmetry as well frequency compensation techniques are used to enhance the as output swing has been accomplished. gain bandwidth product. The output stage uses an all NPN The output swing improvement is most noticeable when transistor design which provides greater output voltage operation is with lower supply voltages (typically 30% with swing and improved frequency performance over more ±5.0 V supplies). With a 10 k load, the output of the conventional stages by using both PNP and NPN transistors amplifier can typically swing to within 1.0 V of the positive (Class AB). This combination produces an amplifier with rail (V ), and to within 0.3 V of the negative rail (V ), CC EE superior characteristics. producing a 28.7 V signal from ±15 V supplies. Output pp Through precision component matching and innovative voltage swing can be further improved by using an output current mirror design, a lower than normal temperature pull−up resistor referenced to the V . Where output signals CC coefficient of input offset voltage (2.0 (cid:5)V/°C as opposed to are referenced to the positive supply rail, the pull−up resistor 10 (cid:5)V/°C), as well as low input offset voltage, is accomplished. will pull the output to V during the positive swing, and CC The minimum common mode input range is from 1.5 V during the negative swing, the NPN output transistor below the positive rail (V ) to 1.5 V above the negative rail collector will pull the output very near V . This CC EE (V ). The inputs will typically common mode to within configuration will produce the maximum attainable output EE 1.0 V of both negative and positive rails though degradation signal from given supply voltages. The value of load in offset voltage and gain will be experienced as the common resistance used should be much less than any feedback mode voltage nears either supply rail. In practice, though not resistance to avoid excess loading and allow easy pull−up of recommended, the input voltage may exceed V by the output. CC approximately 3.0V and decrease below the V by Output impedance of the amplifier is typically less than EE approximately 0.6V without causing permanent damage to 50(cid:4) at frequencies less than the unity gain crossover the device. If the input voltage on either or both inputs is less frequency (see Figure 19). The amplifier is unity gain stable than approximately 0.6V, excessive current may flow, if not with output capacitance loads up to 500 pF at full output limited, causing permanent damage to the device. swing over the −55° to +125°C temperature range. Output The amplifier will not latch with input source currents up phase symmetry is excellent with typically 4°C total phase to 20 mA, though in practice, source currents should be change over a 20 V output excursion at 25°C with a 2.0 k(cid:4) limited to 5.0 mA to avoid any parametric damage to the and 100 pF load. With a 2.0 k(cid:4) resistive load and no device. If both inputs exceed V , the output will be in the capacitance loading, the total phase change is approximately CC high state and phase reversal may occur. No phase reversal one degree for the same 20V output excursion. With a will occur if the voltage on one input is within the common 2.0 k(cid:4) and 500 pF load at 125°C, the total phase change is mode range and the voltage on the other input exceeds V . typically only 10°C for a 20V output excursion (see CC Phase reversal may occur if the input voltage on either or Figure 28). both inputs is less than 1.0V above the negative rail. Phase As with all amplifiers, care should be exercised to insure reversal will be experienced if the voltage on either or both that one does not create a pole at the input of the amplifier inputs is less than V . which is near the closed loop corner frequency. This becomes EE Through the use of dual−doublet frequency compensation a greater concern when using high frequency amplifiers since techniques, the gain bandwidth product has been greatly it is very easy to create such a pole with relatively small values enhanced over other amplifiers using the conventional of resistance on the inputs. If this does occur, the amplifier’s single pole compensation. The phase and gain error of the phase will degrade severely causing the amplifier to become amplifier remains low to higher frequencies for fixed unstable. Effective source resistances, acting in conjunction amplifier gain configurations. with the input capacitance of the amplifier, should be kept to With the all NPN output stage, there is minimal swing loss a minimum to avoid creating such a pole at the input (see to the supply rails, producing superior output swing, no Figure 32). There is minimal effect on stability where the crossover distortion and improved output phase symmetry created input pole is much greater than the closed loop corner with output voltage excursions (output phase symmetry frequency. Where amplifier stability is affected as a result of being the amplifiers ability to maintain a constant phase a negative feedback resistor in conjunction with the http://onsemi.com 11

MC33077 amplifier’s input capacitance, creating a pole near the closed of the low noise characteristics of the amplifier. Thermal loop corner frequency, lead capacitor compensation noise (Johnson Noise) of a resistor is generated by techniques (lead capacitor in parallel with the feedback thermally−charged carriers randomly moving within the resistor) can be employed to improve stability. The feedback resistor creating a voltage. The RMS thermal noise voltage resistor and lead capacitor RC time constant should be larger in a resistor can be calculated from: than that of the uncompensated input pole frequency. Having Enr = / 4k TR × BW a high resistance connected to the noninverting input of the where: amplifier can create a like instability problem. Compensation k = Boltzmann’s Constant (1.38 × 10−23 joules/k) for this condition can be accomplished by adding a lead T = Kelvin temperature capacitor in parallel with the noninverting input resistor of R = Resistance in ohms such a value as to make the RC time constant larger than the BW = Upper and lower frequency limit in Hertz. RC time constant of the uncompensated input resistor acting in conjunction with the amplifiers input capacitance. By way of reference, a 1.0 k(cid:4) resistor at 25°C will For optimum frequency performance and stability, careful produce a 4.0nV/√Hz of RMS noise voltage. If this resistor component placement and printed circuit board layout is connected to the input of the amplifier, the noise voltage should be exercised. For example, long unshielded input or will be gained−up in accordance to the amplifier’s gain output leads may result in unwanted input output coupling. configuration. For this reason, the selection of input source In order to reduce the input capacitance, the body of resistors resistance for low noise circuit applications warrants serious connected to the input pins should be physically close to the consideration. The total noise of the amplifier, as referred to input pins. This not only minimizes the input pole creation its inputs, is typically only 4.4 nV/√Hz at 1.0 kHz. for optimum frequency response, but also minimizes The output of any one amplifier is current limited and thus extraneous signal “pickup” at this node. Power supplies protected from a direct short to ground, However, under such should be decoupled with adequate capacitance as close as conditions, it is important not to allow the amplifier to exceed possible to the device supply pin. the maximum junction temperature rating. Typically for In addition to amplifier stability considerations, input ±15V supplies, any one output can be shorted continuously source resistance values should be low to take full advantage to ground without exceeding the temperature rating. 0.1 (cid:5)F 10 (cid:4) 100 k(cid:4) - 2.0 k(cid:4) D.U.T. + 22 (cid:5)F 1/2 4.3 k(cid:4) Scope ×1 + 4.7 (cid:5)F MC33077 Rin = 1.0 M(cid:4) - 100 k(cid:4) Voltage Gain = 50,000 2.2 (cid:5)F 24.3 k(cid:4) 110 k(cid:4) 0.1 (cid:5)F Note: All capacitors are non−polarized. Figure 37. Voltage Noise Test Circuit (0.1 Hz to 10 Hz ) p−p http://onsemi.com 12

MC33077 PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AB −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER A ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE 8 5 MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. B S 0.25 (0.010) M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR 1 PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 4 −Y− K IMNA EXXIMCUEMSS M OAFT ETRHIEA LD CDOIMNEDNITSIOIONN. AT 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES C NX 45(cid:1) DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 SEATING PLANE B 3.80 4.00 0.150 0.157 −Z− C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 0.10 (0.004) G 1.27 BSC 0.050 BSC H D M J H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 (cid:1) 8 (cid:1) 0 (cid:1) 8 (cid:1) 0.25 (0.010)M Z Y S X S N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:2) (cid:3) mm SCALE 6:1 inches SOIC−8 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13

MC33077 PDIP−8 P SUFFIX CASE 626−05 ISSUE L NOTES: 1.DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 8 5 2.PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3.DIMENSIONING AND TOLERANCING PER ANSI −B− Y14.5M, 1982. 1 4 MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.40 10.16 0.370 0.400 F B 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175 NOTE 2 −A− DF 01..3082 01..5718 00..001450 00..002700 L G 2.54 BSC 0.100 BSC H 0.76 1.27 0.030 0.050 J 0.20 0.30 0.008 0.012 K 2.92 3.43 0.115 0.135 C L 7.62 BSC 0.300 BSC M --- 10 (cid:1) --- 10(cid:1) J N 0.76 1.01 0.030 0.040 −T− SEATING N PLANE M D K H G 0.13 (0.005) M T A M B M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: http://onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Order Literature: http://www.onsemi.com/litorder Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 For additional information, please contact your Email: orderlit@onsemi.com Phone: 81−3−5773−3850 local Sales Representative. http://onsemi.com MC33077/D 14

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