MC1496, MC1496B Balanced Modulators/ Demodulators These devices were designed for use where the output voltage is a product of an input voltage (signal) and a switching function (carrier). Typical applications include suppressed carrier and amplitude modulation, synchronous detection, FM detection, phase detection, http://onsemi.com and chopper applications. See ON Semiconductor Application Note AN531 for additional design information. SOIC−14 14 D SUFFIX Features CASE 751A 1 • Excellent Carrier Suppression −65 dB typ @ 0.5 MHz −50 dB typ @ 10 MHz • Adjustable Gain and Signal Handling PDIP−14 • Balanced Inputs and Outputs P SUFFIX • High Common Mode Rejection −85 dB Typical 14 CASE 646 • This Device Contains 8 Active Transistors 1 • Pb−Free Package is Available* PIN CONNECTIONS Signal Input 1 14 VEE Gain Adjust 2 13 N/C Gain Adjust 3 12 Output Signal Input 4 11 N/C Bias 5 10 Carrier Input Output 6 9 N/C N/C 7 8 Input Carrier ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 12 of this data sheet. © Semiconductor Components Industries, LLC, 2006 1 Publication Order Number: October, 2006 − Rev. 10 MC1496/D

MC1496, MC1496B 0 IC = 500 kHz IS = 1.0 kHz d e I Scal20 g o L 40 IC = 500 kHz, IS = 1.0 kHz 60 499 kHz 500 kHz 501 kHz Figure 1. Suppressed Carrier Output Figure 2. Suppressed Carrier Spectrum Waveform 10 IC = 500 kHz 8.0 IS = 1.0 kHz ale6.0 Sc ar ne4.0 Li 2.0 IC = 500 kHz 0 IS = 1.0 kHz 499 kHz 500 kHz 501 kHz Figure 3. Amplitude Modulation Figure 4. Amplitude−Modulation Spectrum Output Waveform MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.) Rating Symbol Value Unit Applied Voltage (cid:2)V 30 Vdc (V6−V8, V10−V1, V12−V8, V12−V10, V8−V4, V8−V1, V10−V4, V6−V10, V2−V5, V3−V5) Differential Input Signal V8 − V10 +5.0 Vdc V4 − V1 ±(5+I5Re) Maximum Bias Current I5 10 mA Thermal Resistance, Junction−to−Air R(cid:3)JA 100 °C/W Plastic Dual In−Line Package Operating Ambient Temperature Range MC1496 TA 0 to +70 °C MC1496B −40 to +125 Storage Temperature Range Tstg −65 to +150 °C Electrostatic Discharge Sensitivity (ESD) ESD V Human Body Model (HBM) 2000 Machine Model (MM) 400 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2

MC1496, MC1496B ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = −8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 k(cid:4), Re = 1.0 k(cid:4), TA = Tlow to Thigh, all input and output characteristics are single−ended, unless otherwise noted.) (Note 1) Characteristic Fig. Note Symbol Min Typ Max Unit Carrier Feedthrough 5 1 VCFT (cid:5)Vrms VC = 60 mVrms sine wave and fC = 1.0 kHz − 40 − offset adjusted to zero fC = 10 MHz − 140 − VC = 300 mVpp square wave: mVrms offset adjusted to zero fC = 1.0 kHz − 0.04 0.4 offset not adjusted fC = 1.0 kHz − 20 200 Carrier Suppression 5 2 VCS dB fS = 10 kHz, 300 mVrms fC = 500 kHz, 60 mVrms sine wave 40 65 − fC = 10 MHz, 60 mVrms sine wave − 50 − k Transadmittance Bandwidth (Magnitude) (RL = 50 (cid:4)) 8 8 BW3dB MHz Carrier Input Port, VC = 60 mVrms sine wave − 300 − fS = 1.0 kHz, 300 mVrms sine wave Signal Input Port, VS = 300 mVrms sine wave − 80 − |VC| = 0.5 Vdc Signal Gain (VS = 100 mVrms, f = 1.0 kHz; |VC|= 0.5 Vdc) 10 3 AVS 2.5 3.5 − V/V Single−Ended Input Impedance, Signal Port, f = 5.0 MHz 6 − Parallel Input Resistance rip − 200 − k(cid:4) Parallel Input Capacitance cip − 2.0 − pF Single−Ended Output Impedance, f = 10 MHz 6 − Parallel Output Resistance rop − 40 − k(cid:4) Parallel Output Capacitance coo − 5.0 − pF Input Bias Current 7 − (cid:5)A IbS(cid:2)I1 (cid:3)2 I4; IbC(cid:2)I8 (cid:3)2 I10 IIbbCS −− 1122 3300 Input Offset Current 7 − ⎥IioS⎥ − 0.7 7.0 (cid:5)A IioS = I1−I4; IioC = I8−I10 IioC⎥ − 0.7 7.0 Average Temperature Coefficient of Input Offset Current 7 − ⎥TCIio⎥ − 2.0 − nA/°C (TA = −55°C to +125°C) Output Offset Current (I6−I9) 7 − ⎥Ioo⎥ − 14 80 (cid:5)A Average Temperature Coefficient of Output Offset Current 7 − ⎥TCIoo⎥ − 90 − nA/°C (TA = −55°C to +125°C) Common−Mode Input Swing, Signal Port, fS = 1.0 kHz 9 4 CMV − 5.0 − Vpp Common−Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc 9 − ACM − −85 − dB Common−Mode Quiescent Output Voltage (Pin 6 or Pin 9) 10 − Vout − 8.0 − Vpp Differential Output Voltage Swing Capability 10 − Vout − 8.0 − Vpp Power Supply Current I6 +I12 7 6 ICC − 2.0 4.0 mAdc Power Supply Current I14 IEE − 3.0 5.0 DC Power Dissipation 7 5 PD − 33 − mW 1. Tlow = 0°C for MC1496 Thigh = +70°C for MC1496 = −40°C for MC1496B = +125°C for MC1496B http://onsemi.com 3

MC1496, MC1496B GENERAL OPERATING INFORMATION Carrier Feedthrough Note that in the test circuit of Figure 10, V corresponds to S Carrier feedthrough is defined as the output voltage at a maximum value of 1.0 V peak. carrier frequency with only the carrier applied (signal voltage = 0). Common Mode Swing Carrier null is achieved by balancing the currents in the The common−mode swing is the voltage which may be differential amplifier by means of a bias trim potentiometer applied to both bases of the signal differential amplifier, (R1 of Figure 5). without saturating the current sources or without saturating the differential amplifier itself by swinging it into the upper Carrier Suppression switching devices. This swing is variable depending on the Carrier suppression is defined as the ratio of each particular circuit and biasing conditions chosen. sideband output to carrier output for the carrier and signal voltage levels specified. Power Dissipation Carrier suppression is very dependent on carrier input Power dissipation, PD, within the integrated circuit level, as shown in Figure 22. A low value of the carrier does package should be calculated as the summation of the not fully switch the upper switching devices, and results in voltage−current products at each port, i.e. assuming lower signal gain, hence lower carrier suppression. A higher V12 = V6, I5 = I6 = I12 and ignoring base current, than optimum carrier level results in unnecessary device and PD = 2 I5 (V6 − V14) + I5)V5 − V14 where subscripts refer circuit carrier feedthrough, which again degenerates the to pin numbers. suppression figure. The MC1496 has been characterized Design Equations with a 60 mVrms sinewave carrier input signal. This level The following is a partial list of design equations needed provides optimum carrier suppression at carrier frequencies to operate the circuit with other supply voltages and input in the vicinity of 500 kHz, and is generally recommended for conditions. balanced modulator applications. A. Operating Current Carrier feedthrough is independent of signal level, V . S The internal bias currents are set by the conditions at Pin 5. Thus carrier suppression can be maximized by operating Assume: with large signal levels. However, a linear operating mode I5 = I6 = I12, must be maintained in the signal−input transistor pair −(cid:0)or I (cid:5)(cid:5)I for all transistors harmonics of the modulating signal will be generated and B C then : appear in the device output as spurious sidebands of the suppressed carrier. This requirement places an upper limit on input−signal amplitude (see Figure 20). Note also that an V(cid:6)(cid:6)(cid:6) where: R5 is the resistor between optimum carrier level is recommended in Figure 22 for good R5(cid:2) I5 (cid:6)500(cid:4) where: Pin 5 and ground carrier suppression and minimum spurious sideband where: (cid:6) = 0.75 at TA = +25°C The MC1496 has been characterized for the condition generation. I = 1.0 mA and is the generally recommended value. At higher frequencies circuit layout is very important in 5 order to minimize carrier feedthrough. Shielding may be B. Common−Mode Quiescent Output Voltage necessary in order to prevent capacitive coupling between V6 = V12 = V+ − I5 R L the carrier input leads and the output leads. Biasing Signal Gain and Maximum Input Level The MC1496 requires three dc bias voltage levels which Signal gain (single−ended) at low frequencies is defined must be set externally. Guidelines for setting up these three as the voltage gain, levels include maintaining at least 2.0 V collector−base bias AVS(cid:2)VVSo (cid:2)ReR(cid:3)L2re wherere(cid:2)I256(mmAV) othne aalbl stroalnu3ste0is mtVoadrsxc i w(cid:7)mhu i[mle(V nr6aot,ti Vnegx1 c2tea)eb −dle i(n;Vg8 t,h Ve 1v0o)lt]a (cid:7)ge(cid:0)s2 g Vivdecn in A constant dc potential is applied to the carrier input 30 Vdc (cid:7) [(V8, V10) − (V1, V4)] (cid:7)(cid:0)2.7 Vdc terminals to fully switch two of the upper transistors “on” 30 Vdc (cid:7) [(V1, V4) − (V5)] (cid:7)(cid:0)2.7 Vdc and two transistors “off” (V = 0.5 Vdc). This in effect C The foregoing conditions are based on the following forms a cascode differential amplifier. approximations: Linear operation requires that the signal input be below a V6 = V12, V8 = V10, V1 = V4 critical value determined by R and the bias current I5. E V (cid:4) I5 R (Volts peak) S E http://onsemi.com 4

MC1496, MC1496B Bias currents flowing into Pins 1, 4, 8 and 10 are transistor Negative Supply base currents and can normally be neglected if external bias VEE should be dc only. The insertion of an RF choke in dividers are designed to carry 1.0 mA or more. series with VEE can enhance the stability of the internal current sources. Transadmittance Bandwidth Carrier transadmittance bandwidth is the 3.0 dB bandwidth Signal Port Stability of the device forward transadmittance as defined by: Under certain values of driving source impedance, oscillation may occur. In this event, an RC suppression (cid:7)21C(cid:2)io(evasch(ssigidneabl)and)⎥Vo(cid:2)0 nsheotwrto lreka dshs.o uTlhdi sb ew ciolln nreedcutecde dthiree cQtl yo tfo theaec sho iunrpcue−t tuusninedg Signal transadmittance bandwidth is the 3.0 dB bandwidth circuits that cause the oscillation. of the device forward transadmittance as defined by: Signal Input (cid:7)21S(cid:2)vios((ssiiggnnaall))⎥Vc(cid:2)0.5Vdc, Vo(cid:2)0 (Pins 1 and 4) 510 10 pF Coupling and Bypass Capacitors Capacitors C1 and C2 (Figure 5) should be selected for a reactance of less than 5.0 (cid:4) at the carrier frequency. An alternate method for low−frequency applications is to Output Signal insert a 1.0 k(cid:4) resistor in series with the input (Pins 1, 4). In The output signal is taken from Pins 6 and 12 either this case input current drift may cause serious degradation balanced or single−ended. Figure 11 shows the output levels of carrier suppression. of each of the two output sidebands resulting from variations in both the carrier and modulating signal inputs with a single−ended output connection. TEST CIRCUITS VCC 1.0 k 1.0 k 12 Vdc Re = 1.0 k Re 2 3 Carrier 0.1C 2(cid:5)F 51 0.1 C(cid:5)F1 8 2 1.0 k 33R.9L k 3R.9L k 0.5 V+ − 1810 MC1496 6 Z+ou(cid:2)Vto InputVC 110 MC1496 6 I9 I6 +(cid:2)Vo Zin 4 12 −(cid:2)Vo VS 4 −(cid:2)Vo 14 5 Modulating 12 Signal Input 10 k 10 k 51 51 14 5 6.8 k 50 k I5 6.8 k I10 −8.0 Vdc R1 V− Carrier Null −8.0 Vdc NOTE: Shielding of input and output leads may be needed VEE to properly perform these tests. Figure 5. Carrier Rejection and Suppression Figure 6. Input−Output Impedance VCC VCC 12 Vdc 1.0 k 1.0 k 12 Vdc Re = 1.0 k Re 2.0 k 1.0 k 51 0.1 (cid:5)F 1.0 k 0.01 1.0 k IIII7481 18140 2MC1496 3 6 II69 2.0 k MoCIdnauprlrauiettVVirnCSg0.1 (cid:5)F 18140 2MC14963 162 50 50 +−(cid:2)V(cid:2)Vo(cid:5)oF 12 Signal Input 14 5 10 k 10 k 51 51 14 5 I10 50 k 6.8 k 6.8 k V− Carrier Null −8.0 Vdc −8.0 Vdc VEE VEE Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth http://onsemi.com 5

MC1496, MC1496B VCC VCC 12 Vdc 12 Vdc 1.0 k Re = 1.0 k 1.0 k Re = 1.0 k 0.5 V 8 2 3 3.9 k 3.9 k 1.0 k 0.5 V 8 2 33.9 k 3.9 k 1.0 k + − 110 MC1496 6 +(cid:2)Vo + − 110 MC1496 6 +(cid:2)Vo VS 4 12 −(cid:2)Vo VS 4 12 −(cid:2)Vo 14 5 14 5 50 50 6.8 k I5 = 6.8 k 1.0 mA A (cid:2)20log(cid:3)⎥(cid:2)Vo⎥ −8.0 Vdc CM V VEE S −8.0 Vdc VEE Figure 9. Common Mode Gain Figure 10. Signal Gain and Output Swing TYPICAL CHARACTERISTICS Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave), ms) VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted. Vr D (2.0 1.0 M N BA )Ω 500 SIDE1.6 E (k +rip H NC AC Signal Input = 600 mV TA 100 −rip E S OF 1.2 ESI 50 DE 400 mV T R TU0.8 PU AMPLI 230000 mmVV LEL IN 51.00 V , OUTPUT O0.400 50 100 100 mV 150 200 r , PARALip 1.01.0 5.0 10 50 100 VC, CARRIER LEVEL (mVrms) f, FREQUENCY (MHz) Figure 11. Sideband Output versus Figure 12. Signal−Port Parallel−Equivalent Carrier Levels Input Resistance versus Frequency LEL INPUT CAPACITANCE (pF) 3254....0000 OUTPUT RESISTANCE (k)Ω1118642000000 cop rop 11186420..00EL OUTPUT CAPACITANCE (pF) c , PARALip1.001.0 2.0 5.0 10 20 50 100 r , PARALLEL op 240000 1.0 10 100402..00c , PARALLop f, FREQUENCY (MHz) f, FREQUENCY (MHz) Figure 13. Signal−Port Parallel−Equivalent Figure 14. Single−Ended Output Impedance Input Capacitance versus Frequency versus Frequency http://onsemi.com 6

MC1496, MC1496B TYPICAL CHARACTERISTICS (continued) Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave), VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted. 1.0 0 mho) 0.9 Signal Port dB) 10 CE (m 00..87 SION ( 20 N E TTA 0.6 Side Band PPR 30 MC1496 RANSADMI 000...345 (cid:7)21(cid:2)ISouidt(cid:3)e(VbEiaannc(cid:3)(dhS (cid:3)STigrindaaenlbs)aadnmd)it⎥tan(cid:3)Vcoeut(cid:2)0 ARRIER SU 5400 (70°C) γ21, T 00..21 (cid:7)21(cid:2)SIVoigunta⎥l P(cid:3)Voortu Ttr(cid:2)ans0a(cid:3)d(cid:3)|mVCitt|a(cid:2)nce0.5(cid:3)Vdc V , CCS 60 in 0 70 0.1 1.0 10 100 1000 −75 −50 −25 0 25 50 75 100 125 150 175 fC, CARRIER FREQUENCY (MHz) TA, AMBIENT TEMPERATURE (°C) Figure 15. Sideband and Signal Port Figure 16. Carrier Suppression Transadmittances versus Frequency versus Temperature E GAIN (dB) 2100 RRLe == 35.090 k (cid:4) NDAMENTALB) 100 VOLTAG 0 RRLe == 13..09 kk T(Setsat nCdiarcrduit) RL = 3.9 k ACH FUBAND (d 3200 2fC ED Re = 2.0 k W EDE A (cid:3), SINGLE-ENDVS−−−(cid:2)(cid:2)(cid:2)312000 |VC| = 0.5 VdAcV(cid:2)Re(cid:3)RRRLLe2 r==e 15.000 k (cid:4) PPRESSION BELOCARRIER SI 65470000 fC 3fC 0.01 0.1 1.0 10 100 SU 0.05 0.1 0.5 1.0 5.0 10 50 f, FREQUENCY (MHz) fC, CARRIER FREQUENCY (MHz) Figure 17. Signal−Port Frequency Response Figure 18. Carrier Suppression versus Frequency ms) 10 AL 0 Vr NT T VOLTAGE (m 1.0 CH FUNDAMEAND (dB) 321000 U AB CARRIER OUTP 0.1 SION BELOW ECARRIER SIDE 654000 ffCC ±±(cid:0)(cid:0)32ffSS V , CFT 0.01 PPRES 8700 U 0.05 0.1 0.5 1.0 5.0 10 50 S 0 200 400 600 800 fC, CARRIER FREQUENCY (MHz) VS, INPUT SIGNAL AMPLITUDE (mVrms) Figure 19. Carrier Feedthrough Figure 20. Sideband Harmonic Suppression versus Frequency versus Input Signal Level http://onsemi.com 7

MC1496, MC1496B 0 0 L A MENT 10 N (dB) 10 NDAB) 20 3fC ±(cid:0)fS SIO 20 CH FUAND (d 30 PPRES 30 fC = 10 MHz AB U W EDE 40 2fC ±(cid:0)fS R S 40 ESSION BELOCARRIER SI 6500 2fC ±(cid:0)2fS V , CARRIECS 6500 fC = 500 kHz PR 70 70 P 0.05 0.1 0.5 1.0 5.0 10 50 0 100 200 300 400 500 U S fC, CARRIER FREQUENCY (MHz) VC, CARRIER INPUT LEVEL (mVrms) Figure 21. Suppression of Carrier Harmonic Figure 22. Carrier Suppression versus Sidebands versus Carrier Frequency Carrier Input Level OPERATIONS INFORMATION The MC1496, a monolithic balanced modulator circuit, is components and have an amplitude which is a function of the shown in Figure 23. product of the input signal amplitudes. This circuit consists of an upper quad differential amplifier For high−level operation at the carrier input port and driven by a standard differential amplifier with dual current linear operation at the modulating signal port, the output sources. The output collectors are cross−coupled so that signal will contain sum and difference frequency full−wave balanced multiplication of the two input voltages components of the modulating signal frequency and the occurs. That is, the output signal is a constant times the fundamental and odd harmonics of the carrier frequency. product of the two input signals. The output amplitude will be a constant times the Mathematical analysis of linear ac signal multiplication modulating signal amplitude. Any amplitude variations in indicates that the output spectrum will consist of only the sum the carrier signal will not appear in the output. and difference of the two input frequencies. Thus, the device The linear signal handling capabilities of a differential may be used as a balanced modulator, doubly balanced mixer, amplifier are well defined. With no emitter degeneration, the product detector, frequency doubler, and other applications maximum input voltage for linear operation is requiring these particular output signal characteristics. approximately 25 mV peak. Since the upper differential The lower differential amplifier has its emitters connected amplifier has its emitters internally connected, this voltage to the package pins so that an external emitter resistance may applies to the carrier input port for all conditions. be used. Also, external load resistors are employed at the Since the lower differential amplifier has provisions for an device output. external emitter resistance, its linear signal handling range may be adjusted by the user. The maximum input voltage for Signal Levels linear operation may be approximated from the following The upper quad differential amplifier may be operated expression: either in a linear or a saturated mode. The lower differential V = (I5) (R ) volts peak. amplifier is operated in a linear mode for most applications. E For low−level operation at both input ports, the output This expression may be used to compute the minimum signal will contain sum and difference frequency value of RE for a given input voltage amplitude. (−) 12 Vo, 1.0 k 1.0 k 12 Vdc (+) 6 Output 51 0.1 (cid:5)F 2 Re 1.0 k 33.9R kL 3R.9L k 10 (−) CaInrrpieurt VC8 (+) CarrierVC 0.1 (cid:5)F 180 6 +Vo Input 1 MC1496 4 (−) VS 4 SIingpnuatl VS1 (+) 23GAdajiunst MoSIdniugplnauattilng 10 k 10 k 51 51 14 5 12 −Vo 50 k Bias5 (Pin numbers I5 6.8 k 500 500 500 per G package) Carrier Null −8.0 Vdc VEE14 VEE Figure 23. Circuit Schematic Figure 24. Typical Modulator Circuit http://onsemi.com 8

MC1496, MC1496B Table 1. Voltage Gain and Output Frequencies Carrier Input Signal (VC) Approximate Voltage Gain Output Signal Frequency(s) R V L C (cid:8) (cid:9) Low−level dc 2(RE(cid:3)2re) KqT fM R High−level dc RE(cid:3)L2re fM R V (rms) L C (cid:8) (cid:9) Low−level ac 2(cid:10)2 KqT (RE(cid:3)2re) fC ±(cid:0)fM 0.637R High−level ac RE(cid:3)2rLe fC ±(cid:0)fM, 3fC ±(cid:0)fM, 5fC ±(cid:0)fM, . . . 2. Low−level Modulating Signal, VM, assumed in all cases. VC is Carrier Input Voltage. 3. When the output signal contains multiple frequencies, the gain expression given is for the output amplitude ofeach of the two desired outputs, fC + fM and fC − fM. 4. All gain expressions are for a single−ended output. For a differential output connection, multiply each expression by two. 5. RL = Load resistance. 6. RE = Emitter resistance between Pins 2 and 3. 7. re = Transistor dynamic emitter resistance, at 25°C; re(cid:11) 26mV I5(mA) 8. K = Boltzmann′s Constant, T = temperature in degrees Kelvin, q = the charge on an electron. The gain from the modulating signal input port to the All that is required to shift from suppressed carrier to AM output is the MC1496 gain parameter which is most often of operation is to adjust the carrier null potentiometer for the interest to the designer. This gain has significance only when proper amount of carrier insertion in the output signal. the lower differential amplifier is operated in a linear mode, However, the suppressed carrier null circuitry as shown in but this includes most applications of the device. Figure 26 does not have sufficient adjustment range. As previously mentioned, the upper quad differential Therefore, the modulator may be modified for AM amplifier may be operated either in a linear or a saturated operation by changing two resistor values in the null circuit mode. Approximate gain expressions have been developed as shown in Figure 27. for the MC1496 for a low−level modulating signal input and the following carrier input conditions: Product Detector The MC1496 makes an excellent SSB product detector 1) Low−level dc (see Figure 28). 2) High−level dc This product detector has a sensitivity of 3.0 (cid:5)V and a 3) Low−level ac dynamic range of 90 dB when operating at an intermediate 4) High−level ac frequency of 9.0 MHz. These gains are summarized in Table 1, along with the The detector is broadband for the entire high frequency frequency components contained in the output signal. range. For operation at very low intermediate frequencies down to 50 kHz the 0.1 (cid:5)F capacitors on Pins 8 and 10 should APPLICATIONS INFORMATION be increased to 1.0 (cid:5)F. Also, the output filter at Pin 12 can Double sideband suppressed carrier modulation is the be tailored to a specific intermediate frequency and audio basic application of the MC1496. The suggested circuit for amplifier input impedance. this application is shown on the front page of this data sheet. As in all applications of the MC1496, the emitter In some applications, it may be necessary to operate the resistance between Pins 2 and 3 may be increased or MC1496 with a single dc supply voltage instead of dual decreased to adjust circuit gain, sensitivity, and dynamic supplies. Figure 25 shows a balanced modulator designed range. for operation with a single 12 Vdc supply. Performance of This circuit may also be used as an AM detector by this circuit is similar to that of the dual supply modulator. introducing carrier signal at the carrier input and an AM signal at the SSB input. AM Modulator The carrier signal may be derived from the intermediate The circuit shown in Figure 26 may be used as an frequency signal or generated locally. The carrier signal may amplitude modulator with a minor modification. http://onsemi.com 9

MC1496, MC1496B be introduced with or without modulation, provided its level Figures 30 and 31 show a broadband frequency doubler is sufficiently high to saturate the upper quad differential and a tuned output very high frequency (VHF) doubler, amplifier. If the carrier signal is modulated, a 300 mVrms respectively. input level is recommended. Phase Detection and FM Detection Doubly Balanced Mixer The MC1496 will function as a phase detector. High−level The MC1496 may be used as a doubly balanced mixer input signals are introduced at both inputs. When both inputs with either broadband or tuned narrow band input and output are at the same frequency the MC1496 will deliver an output networks. which is a function of the phase difference between the two The local oscillator signal is introduced at the carrier input input signals. port with a recommended amplitude of 100 mVrms. An FM detector may be constructed by using the phase Figure 29 shows a mixer with a broadband input and a detector principle. A tuned circuit is added at one of the tuned output. inputs to cause the two input signals to vary in phase as a function of frequency. The MC1496 will then provide an Frequency Doubler output which is a function of the input signal frequency. The MC1496 will operate as a frequency doubler by introducing the same frequency at both input ports. TYPICAL APPLICATIONS VCC 1.0 k 820 1.3 k 12 Vdc + 0.1 (cid:5)F 1.0 k 3.0 k 3.0 k 1.0 k 1.0 k V12C CVd C60a rmrieVrr mInspu2t51 5(cid:5) VF 0.1 (cid:5)F 51 1081 M2C14963 6 0.1 (cid:5)F DOSutBput VC 0.1 (cid:5)F 51 0.1 (cid:5)1F082 Re 1.0 k 3 36.9R kL R3.L9+ Carrier Modulating − + 4 Input 1 MC1496 Signal Input 10 (cid:5)F 25 (cid:5)F 14 512 ModulaVtinSg 4 12 − 300 mVrms 15 V +15 V− 10 k Signal 10 k 10 k 51 51 14 5 Carrier Input 50 k Null 50 k 10 k 10 k 100 100 R1 VEE I5 6.8 k Carrier Null −8.0 Vdc Figure 25. Balanced Modulator Figure 26. Balanced Modulator−Demodulator (12 Vdc Single Supply) 1.0 k 1.0 k V12C CVdc 820 1.3 k V12C CVdc RL 0.1 (cid:5)F 51 0.1 (cid:5)F 2 Re 1.0 k 3 3.9 k RL 1.0 k 100 3.0 k 3.0 k 0.1 (cid:5)F 8 3.9 k 51 8 2 3 CarrierVC 10 6 +Vo Carrier Input 0.1 (cid:5)F 10 6 0.005 Input 1 MC1496 300 mVrms 1 MC1496 (cid:5)F AF MoSIdniugplnauVattSilng 750 507 5k0 51 51414 5 12 −Vo SSB Input 0.11. 0(cid:5) kF 1.0 k 40.1 14 5 12 1.0 k 1.0 R(cid:5)LF(cid:12)Ou 1tp0 (cid:5)F 0.005 0.005 15 6.8 k 10 k (cid:5)F (cid:5)F Carrier Adjust VEE −8.0 Vdc Figure 27. AM Modulator Circuit Figure 28. Product Detector (12 Vdc Single Supply) http://onsemi.com 10

MC1496, MC1496B VCC 12 Vdc 1.0 k 1.0 k V+8C.C0 Vdc + 100 (cid:5)F 0.001 (cid:5)F 0.01 1.0 k − 25 Vdc 1.0 k (cid:5)F RFC 2 3 3.9 k OscLilloactoarl 51 8 2 3 100 (cid:5)H 1.0 k C2 100 180 6 3.9 k 100 mIVnrpmuts 0.001 (cid:5)F110 MC1496 6 0.001 (cid:5)F Input 100 (cid:5)F −C2+ MC1496 Outp RF Input 4 9.5 (cid:5)F 9.0 MHz 15 mVrms 15 Vdc Max 100 (cid:5)F 15 Vdc 1 51 10 k 14 512 L1 ORLu t=p u5t0(cid:4) 4 12 10 k 51 5.0−80 50 k pF 90−480 pF 10 k 10 k 100 100 14 5 6.8 k Null Adjust VEE 50 k −8.0 Vdc 6.8 k I5 L1 = 44 Turns AWG No. 28 Enameled Wire, Wound Balance VEE on Micrometals Type 44−6 Toroid Core. −8.0 Vdc Figure 29. Doubly Balanced Mixer Figure 30. Low−Frequency Doubler (Broadband Inputs, 9.0 MHz Tuned Output) VCC 1.0 k 1.0 k V+ +8.0 Vdc 0.001 18 pF (cid:5)F 100 0(cid:5).F001 0.68R (cid:5)FHC L118 nH 8 2 3 6 1.0−10 pF 300 MHz Output 0.001 (cid:5)F 10 RL = 50(cid:4) 150 MHz 1 MC1496 1.0−10 pF Input 4 12 10 k 100 14 5 10 k 100 50 k 6.8 k L1 = 1 Turn AWG Balance VEE No. 18 Wire, 7/32″ ID −8.0 Vdc Figure 31. 150 to 300 MHz Doubler PLITUDE (f − f )C S (f + f )C S AM (f − 2f )C S (f )C (f + 2f )C S (2f − 2f )C S(2f − 2f )C S(2f )C(2f + 2f )C S (2f + 2f )C S (3f − 2f )C S(3f − f )C S (3f )C (3f + f )C S (3f + 2f )C S Frequency Balanced Modulator Spectrum DEFINITIONS fC Carrier Fundamental fC ±(cid:0)nfS Fundamental Carrier Sideband Harmonics fS Modulating Signal nfC Carrier Harmonics fC ±(cid:0)fS Fundamental Carrier Sidebands nfC ±(cid:0)nfS Carrier Harmonic Sidebands http://onsemi.com 11

MC1496, MC1496B ORDERING INFORMATION Device Package Shipping† MC1496D SOIC−14 MC1496DG SOIC−14 55 Units/Rail (Pb−Free) MC1496DR2 SOIC−14 MC1496DR2G SOIC−14 2500 Tape & Reel (Pb−Free) MC1496P PDIP−14 MC1496PG PDIP−14 (Pb−Free) 25 Units/Rail MC1496P1 PDIP−14 MC1496P1G PDIP−14 (Pb−Free) MC1496BD SOIC−14 MC1496BDG SOIC−14 55 Units/Rail (Pb−Free) MC1496BDR2 SOIC−14 MC1496BDR2G SOIC−14 2500 Tape & Reel (Pb−Free) MC1496BP PDIP−14 MC1496BPG PDIP−14 25 Units/Rail (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS SOIC−14 PDIP−14 D SUFFIX P SUFFIX CASE 751A CASE 646 14 14 14 14 MC1496DG MC1496BDG MC1496P MC1496BP AWLYWW AWLYWW AWLYYWWG AWLYYWWG 1 1 1 1 A = Assembly Location WL = Wafer Lot YY, Y = Year WW = Work Week G = Pb−Free Package http://onsemi.com 12

MC1496, MC1496B PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H NOTES: 1.DIMENSIONING AND TOLERANCING PER −A− ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: MILLIMETER. 14 8 3.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4.MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. −B− P7 PL 5.DDIAMMEBNASRIO PNR DO TDROUESSIO NNO. TA LINLCOLWUADBELE 0.25 (0.010)M B M DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL 1 7 CONDITION. G MILLIMETERS INCHES RX 45(cid:2) F DIM MIN MAX MIN MAX C A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 −T− D 0.35 0.49 0.014 0.019 SEATING D14 PL K M J GF 0.14.027 BS1C.25 0.001.0650 B0.S0C49 PLANE J 0.19 0.25 0.008 0.009 0.25 (0.010)M T B S A S K 0.10 0.25 0.004 0.009 M 0 (cid:2) 7 (cid:2) 0 (cid:2) 7 (cid:2) P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019 SOLDERING FOOTPRINT* 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13

MC1496, MC1496B PDIP−14 CASE 646−06 ISSUE P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 14 8 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN B FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 1 7 5. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS A DIM MIN MAX MIN MAX A 0.715 0.770 18.16 19.56 F L B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 N C GF 0.004.1000 B0S.0C70 1.20.254 BS1C.78 H 0.052 0.095 1.32 2.41 −T− J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 SEATING L 0.290 0.310 7.37 7.87 PLANE K J M −−− 10 (cid:2) −−− 10 (cid:2) H G D14 PL M N 0.015 0.039 0.38 1.01 0.13 (0.005) M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: http://onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Order Literature: http://www.onsemi.com/litorder Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 For additional information, please contact your Email: orderlit@onsemi.com Phone: 81−3−5773−3850 local Sales Representative. http://onsemi.com MC1496/D 14

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: MC1496BDG MC1496BDR2G MC1496DG MC1496DR2G