MC1455, MC1455B, NCV1455B Timers The MC1455 monolithic timing circuit is a highly stable controller capable of producing accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode, time is precisely controlled by one external resistor and http://onsemi.com capacitor. For astable operation as an oscillator, the free−running frequency and the duty cycle are both accurately controlled with two MARKING DIAGRAMS external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200 mA or drive TTL circuits. 8 SOIC−8 1455x Features 8 D SUFFIX ALYW (cid:2) • CASE 751 Direct Replacement for NE555 Timers 1 • 1 Timing from Microseconds through Hours • Operates in Both Astable and Monostable Modes 8 • Adjustable Duty Cycle PDIP−8 MC1455yyy • High Current Output Can Source or Sink 200 mA P1 SUFFIX AWL • Output Can Drive TTL 8 CASE 626 YYWWG • Temperature Stability of 0.005% per °C 1 1 • Normally ON or Normally OFF Output • Pb−Free Packages are Available x = B or V yyy = BP1 or P1 A = Assembly Location L = Wafer Lot Y, YY = Year 1.0 k Load W, WW = Work Week MT2 (cid:2) or G = Pb−Free Package 10 k 4 3 8 6 R 20(cid:2)M G MT1 0 Hz 6 2 MC1455 7 Vac/ ORDERING INFORMATION 5 7 0.1 (cid:2)F 0.01 (cid:2)F 1.0 (cid:2)F C 11 See detailed ordering and shipping information in the package 1 dimensions section on page 9 of this data sheet. -10 V 1N4003 3.5 k - tTc h=ima 1ne.g 1di;ne Rgla Rya n (atd)n Cids C=va 2(rs2iae bseel eFc ibgyure 16). 1N4740 250 V +10 (cid:2)F VR ICC VCC Figure 1. 22 Second Solid State Time Delay Relay Circuit Reset 4 8 700 + 5 VCC 7 VCC 0.01 (cid:2)F VCoolntatrgoel Discharge MC1455 8 3 Threshold 6 5 k 7 Output 6 Ith 2.0 k VS ControTlh Vreoslthaogled 5 -+CAomp R FFlloipp Discharge VO IISSionukrce G1ND 2 Trigger 5 k Q 3 Trigger 2 -+CBomp SIRnheisbeitt/ Output Tpae)asrWat mchierecntue Virts Sf)o :(cid:2)r m 2e/3a sVuCrCin,g V DOC is p laorwa.meters (to set output and measure 5 k b)When VS (cid:3)1/3 VCC, VO is high. c)When VO is low, Pin 7 sinks current. To test for Reset, set VO 1 4 c)high, apply Reset voltage, and test for current flowing into Pin 7. GND Reset c)When Reset is not in use, it should be tied to VCC. Figure 2. Representative Block Diagram Figure 3. General Test Circuit © Semiconductor Components Industries, LLC, 2009 1 Publication Order Number: December, 2009 − Rev. 10 MC1455/D

MC1455, MC1455B, NCV1455B MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) Rating Symbol Value Unit Power Supply Voltage VCC +18 Vdc Discharge Current (Pin 7) I7 200 mA Power Dissipation (Package Limitation) P1 Suffix, Plastic Package PD 625 mW Derate above TA = +25°C 5.0 mW/°C D Suffix, Plastic Package PD 625 mW Derate above TA = +25°C 160 °C/W Operating Temperature Range (Ambient) TA °C MC1455B −40 to +85 MC1455 0 to +70 NCV1455B −40 to +125 Maximum Operating Die Junction Temperature TJ +150 °C Storage Temperature Range Tstg −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = +5.0 V to +15 V, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Operating Supply Voltage Range VCC 4.5 − 16 V Supply Current ICC mA VCC = 5.0 V, RL = (cid:4) − 3.0 6.0 VCC = 15 V, RL = (cid:4), Low State (Note 1) − 10 15 Timing Error (R = 1.0 k(cid:3) to 100 k(cid:3)) (Note 2) Initial Accuracy C = 0.1 (cid:2)F − 1.0 − % Drift with Temperature − 50 − PPM/°C Drift with Supply Voltage − 0.1 − %/V Threshold Voltage/Supply Voltage Vth/VCC − 2/3 − Trigger Voltage VT V VCC = 15 V − 5.0 − VCC = 5.0 V − 1.67 − Trigger Current IT − 0.5 − (cid:2)A Reset Voltage VR 0.4 0.7 1.0 V Reset Current IR − 0.1 − mA Threshold Current (Note 3) Ith − 0.1 0.25 (cid:2)A Discharge Leakage Current (Pin 7) Idischg − − 100 nA Control Voltage Level VCL V VCC = 15 V 9.0 10 11 VCC = 5.0 V 2.6 3.33 4.0 Output Voltage Low VOL V ISink = 10 mA (VCC = 15 V) − 0.1 0.25 ISink = 50 mA (VCC = 15 V) − 0.4 0.75 ISink = 100 mA (VCC = 15 V) − 2.0 2.5 ISink = 200 mA (VCC = 15 V) − 2.5 − ISink = 8.0 mA (VCC = 5.0 V) − − − ISink = 5.0 mA (VCC = 5.0 V) − 0.25 0.35 Output Voltage High VOH V VCC = 15 V (ISource = 200 mA) − 12.5 − VCC = 15 V (ISource = 100 mA) 12.75 13.3 − VCC = 5.0 V (ISource = 100 mA) 2.75 3.3 − Rise Time Differential Output tr − 100 − ns Fall Time Differential Output tf − 100 − ns 1. ‘Supply current when output is high is typically 1.0 mA less. 2. Tested at VCC = 5.0 V and VCC = 15 V Monostable mode. 3. This will determine the maximum value of RA + RB for 15 V operation. The maximum total R = 20 M(cid:3). 4. Tlow = 0°C for MC1455, Tlow = −40°C for MC1455B, NCV1455B Thigh = +70°C for MC1455, Thigh = +85°C for MC1455B, Thigh = +125°C for NCV1455B 5. NCV prefix is for Automotive and other applications requiring site and change control. http://onsemi.com 2

MC1455, MC1455B, NCV1455B 150 10 25°C ns min) 112050 NT (mA) 8.0 H ( RE 6.0 T R WID 75 0°C CU E LY S P 4.0 UL 50 25°C UP P S W, 70°C , C P 25 IC 2.0 0 0 0 0.1 0.2 0.3 0.4 5.0 10 15 VT(cid:2)(min), MINIMUM TRIGGER VOLTAGE (x VCC = Vdc) VCC, SUPPLY VOLTAGE (Vdc) Figure 4. Trigger Pulse Width Figure 5. Supply Current 2.0 10 1.8 c) d V 1.6 25°C GE ( (Vdc)H 11..42 T VOLTA 1.0 25°C O 1.0 U V P - T C 0.8 U C O V 0.6 W 0.1 O L 00..42 5.0 V ≤ VCC ≤ 15 V V, OL 0 0.01 1.0 2.0 5.0 10 20 50 100 1.0 2.0 5.0 10 20 50 100 ISource (mA) ISink (mA) Figure 6. High Output Voltage Figure 7. Low Output Voltage @ V = 5.0 Vdc CC 10 10 c) c) d d V V E ( E ( G G LTA 1.0 25°C LTA 1.0 O O V V T T U U P P T T U U O O W 0.1 W 0.1 25°C O O L L , L , L O O V V 0.01 0.01 1.0 2.0 5.0 10 20 50 100 1.0 2.0 5.0 10 20 50 100 ISink (mA) ISink (mA) Figure 8. Low Output Voltage Figure 9. Low Output Voltage @ V = 10 Vdc @ V = 15 Vdc CC CC http://onsemi.com 3

MC1455, MC1455B, NCV1455B 1.015 1.015 D 1.010 D 1.010 E E Z Z LI LI A A M 1.005 M 1.005 R R O O N N E 1.000 E 1.000 M M TI TI Y Y A 0.995 A 0.995 L L E E D D , d 0.990 , d 0.990 t t 0.985 0.985 0 5.0 1100 15 20 -75 -50 -25 0 25 50 75 100 125 VCC, SUPPLY VOLTAGE (Vdc) TA, AMBIENT TEMPERATURE (°C) Figure 10. Delay Time versus Supply Voltage Figure 11. Delay Time versus Temperature 300 s) n E ( 250 M TI Y A 200 L E D N 150 O 0°C TI A G A 100 P RO 70°C 25°C , Pd 50 p t 0 0 0.1 0.2 0.3 0.4 VT(cid:2)(min), MINIMUM TRIGGER VOLTAGE (x VCC = Vdc) Figure 12. Propagation Delay versus Trigger Voltage http://onsemi.com 4

MC1455, MC1455B, NCV1455B Control Voltage Threshold Trigger Flip-Flop Output Comparator Comparator VCC 4.7 k 830 4.7(cid:2)k 1.0 k 6.8 k 5.0 k Threshold 7.0 k 3.9 k 10 k Output c b c b 5.0 k e 4.7 k Trigger 220 Reset Reset 100 k 5.0 k 4.7 k Discharge Discharge GND 100 Figure 13. Representative Circuit Schematic GENERAL OPERATION The MC1455 is a monolithic timing circuit which uses an has been triggered by an input signal, it cannot be retriggered external resistor − capacitor network as its timing element. It until the present timing period has been completed. The time can be used in both the monostable (one−shot) and astable that the output is high is given by the equation t = 1.1 R C. A modes with frequency and duty cycle controlled by the Various combinations of R and C and their associated times capacitor and resistor values. While the timing is dependent are shown in Figure 16. The trigger pulse width must be less upon the external passive components, the monolithic circuit than the timing period. provides the starting circuit, voltage comparison and other A reset pin is provided to discharge the capacitor, thus functions needed for a complete timing circuit. Internal to the interrupting the timing cycle. As long as the reset pin is low, integrated circuit are two comparators, one for the input the capacitor discharge transistor is turned “on” and prevents signal and the other for capacitor voltage; also a flip−flop and the capacitor from charging. While the reset voltage is applied digital output are included. The comparator reference the digital output will remain the same. The reset pin should voltages are always a fixed ratio of the supply voltage thus be tied to the supply voltage when not in use. providing output timing independent of supply voltage. +VCC (5.0 V to 15 V) Monostable Mode In the monostable mode, a capacitor and a single resistor aarned utsheed d fiosrc hthaerg teim trianngs insetotwr oterrkm. Binoatlh a trhee c tohnrensehcoteldd tteorgmetihnearl RL Rese4t V8CC RA Discharge in this mode (refer to circuit in Figure 14). When the input Output 7 voltage to the trigger comparator falls below 1/3 V , the CC comparator output triggers the flip−flop so that its output sets 3 6 MC1455 low. This turns the capacitor discharge transistor “off” and RL 2 Th5reshold C drives the digital output to the high state. This condition Trigger allows the capacitor to charge at an exponential rate which is Control set by the RC time constant. When the capacitor voltage 1 Voltage 0.01 (cid:2)F reaches 2/3 V , the threshold comparator resets the CC flip−flop. This action discharges the timing capacitor and Figure 14. Monostable Circuit returns the digital output to the low state. Once the flip−flop http://onsemi.com 5

MC1455, MC1455B, NCV1455B 100 10 F) μE ( 1.0 C N A T ACI 0.1 P A C C, 0.01 0.001 t = 50 (cid:2)s/cm 10 (cid:2)s 100 (cid:2)s 1.0 ms 10 ms 100 ms 1.0 10 100 (RA = 10 k(cid:3), C = 0.01 (cid:2)F, RL = 1.0 k(cid:3), VCC = 15 V) td, TIME DELAY (s) Figure 15. Monostable Waveforms Figure 16. Time Delay +VCC (5.0 V to 15 V) RL Res4et V8CC RA Output 7(cid:3)Discharge 3 6(cid:3)Threshold MC1455 RB Trigger 5 2 Control RL Voltage 1 C t = 20 (cid:2)s/cm (RA = 5.1 k(cid:3), C = 0.01 (cid:2)F, RL = 1.0 k(cid:3); RB = 3.9 k(cid:3), VCC = 15 V) Figure 17. Astable Circuit Figure 18. Astable Waveforms Astable Mode In the astable mode the timer is connected so that it will To obtain the maximum duty cycle R must be as small as A retrigger itself and cause the capacitor voltage to oscillate possible; but it must also be large enough to limit the between 1/3 V and 2/3 V . See Figure 17. discharge current (Pin 7 current) within the maximum rating CC CC The external capacitor changes to 2/3 V through R and of the discharge transistor (200 mA). CC A R and discharges to 1/3 V through R . By varying the The minimum value of R is given by: B CC B A ratio of these resistors the duty cycle can be varied. The VCC(Vdc) VCC(Vdc) charge and discharge times are independent of the supply RA(cid:2) (cid:2) I7(A) 0.2 voltage. The charge time (output high) is given by: 100 t1(cid:5)0.695(RA(cid:6)RB)C The discharge time (output low) is given by: 10 F) t2(cid:5)0.695(RB)C μE ( C 1.0 Thus the total period is given by: N A T T(cid:5)t1(cid:6)t2(cid:5)0.695(RA(cid:6)2RB)C ACI 0.1 P A The frequency of oscillation is then: C f(cid:5)1(cid:5) 1.44 C, 0.01 1 (RA(cid:6)2RB)C (RA + 2 RB) and may be easily found as shown in Figure 19. 0.001 0.1 1.0 10 100 1.0 k 10 k 100 The duty cycle is given by: DC(cid:5) RB f, FREE RUNNING FREQUENCY (Hz) RA(cid:6)2RB Figure 19. Free Running Frequency http://onsemi.com 6

MC1455, MC1455B, NCV1455B APPLICATIONS INFORMATION Linear Voltage Ramp Missing Pulse Detector In the monostable mode, the resistor can be replaced by a The timer can be used to produce an output when an input constant current source to provide a linear ramp voltage. The pulse fails to occur within the delay of the timer. To capacitor still charges from 0 V to 2/3 V . The linear accomplish this, set the time delay to be slightly longer than CC CC ramp time is given by: the time between successive input pulses. The timing cycle is then continuously reset by the input pulse train until a 2 V V − V − V t = CC , where I = CC B BE change in frequency or a missing pulse allows completion of 3 1 R E the timing cycle, causing a change in the output level. If V is much larger than V , then t can be made B BE independent of V . CC +VCC (5.0 V to 15 V) VCC Reset VCC RL 4 8 RA Reset 4 8 VCC 3 Discharge RE R1 2N4403 Output 7 Digital 3 VE or Equiv MC1455 Threshold Output MC1455 76 I VB Input 2 65 CVoolntatrgoel C Trigger 2 5 Sweep R2 Trigger 1 0.01 (cid:2)F Output C 2N4403 or Equiv 1 0.01 (cid:2)F Control Voltage Figure 20. Linear Voltage Sweep Circuit Figure 21. Missing Pulse Detector t = 100 (cid:2)s/cm t = 500 (cid:2)s/cm (RE = 10 k(cid:3), R2 = 100 k(cid:3), R1 = 39 k(cid:3), C = 0.01 (cid:2)F, VCC = 15 V) (RA = 2.0 k(cid:3), RL = 1.0 k(cid:3), C = 0.01 (cid:2)F, VCC = 15 V) Figure 22. Linear Voltage Ramp Waveforms Figure 23. Missing Pulse Detector Waveforms http://onsemi.com 7

MC1455, MC1455B, NCV1455B Pulse Width Modulation If the timer is triggered with a continuous pulse train in the monostable mode of operation, the charge time of the capacitor can be varied by changing the control voltage at Pin 5. In this manner, the output pulse width can be modulated by applying a modulating signal that controls the threshold voltage. +VCC (5.0 V to 15 V) RL RA 4 8 t = 0.5 ms/cm 3 7 (RA = 10 k(cid:3), C = 0.02 (cid:2)F, VCC = 15 V) Figure 25. Pulse Width Modulation Waveforms Output C 6 MC1455 2 5 Test Sequences Several timers can be connected to drive each other for Clock Modulation Input Input sequential timing. An example is shown in Figure 26 where 1 the sequence is started by triggering the first timer which runs for 10 ms. The output then switches low momentarily Figure 24. Pulse Width Modulator and starts the second timer which runs for 50 ms and so forth. VCC (5.0 V to 15 V) 9.1 k 27 k 9.1 k 27 k 18.2 k 8 4 8 4 8 4 6 5 0.01 (cid:2)F 6 5 0.01 (cid:2)F 6 5 0.01 (cid:2)F 7 7 MC1455 MC1455 MC1455 7 3 2 3 2 3 0.001 (cid:2)F 0.001 (cid:2)F 2 1 1.0 (cid:2)F 5.0 (cid:2)F 1 5.0 (cid:2)F 1 Load Load Load Figure 26. Sequential Timer http://onsemi.com 8

MC1455, MC1455B, NCV1455B ORDERING INFORMATION Device Operating Temperature Range Package Shipping† MC1455P1 PDIP−8 50 Units / Rail MC1455P1G PDIP−8 50 Units / Rail (Pb−Free) MC1455D SOIC−8 98 Units / Rail MC1455DG TA = 0°C to +70°C SOIC−8 98 Units / Rail (Pb−Free) MC1455DR2 SOIC−8 2500 Units / Tape & Reel MC1455DR2G SOIC−8 2500 Units / Tape & Reel (Pb−Free) MC1455BD SOIC−8 98 Units / Rail MC1455BDG SOIC−8 98 Units / Rail (Pb−Free) MC1455BDR2 SOIC−8 2500 Units / Tape & Reel MC1455BDR2G TA = −40°C to +85°C SOIC−8 2500 Units / Tape & Reel (Pb−Free) MC1455BP1 PDIP−8 50 Units / Rail MC1455BP1G PDIP−8 50 Units / Rail (Pb−Free) NCV1455BDR2* SOIC−8 2500 Units / Tape & Reel NCV1455BDR2G* TA = −40°C to +125°C SOIC−8 2500 Units / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV prefix is for automotive and other applications requiring site and control changes. http://onsemi.com 9

MC1455, MC1455B, NCV1455B PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AJ NOTES: −X− 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. M75A1X−I0M1U TMH RMUA T7E51R−IA0L6 CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX C NX 45(cid:3) A 4.80 5.00 0.189 0.197 B 3.80 4.00 0.150 0.157 SEATING PLANE C 1.35 1.75 0.053 0.069 −Z− D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC 0.10 (0.004) H 0.10 0.25 0.004 0.010 H D M J J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 (cid:7) (cid:8) 0.024 0.050 mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10

MC1455, MC1455B, NCV1455B PACKAGE DIMENSIONS PDIP−8 P1 SUFFIX CASE 626−05 ISSUE L NOTES: 1.DIMENSION L TO CENTER OF LEAD WHEN 8 5 FORMED PARALLEL. 2.PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). −B− 3.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 1 4 MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.40 10.16 0.370 0.400 F B 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175 NOTE 2 −A− D 0.38 0.51 0.015 0.020 L F 1.02 1.78 0.040 0.070 G 2.54 BSC 0.100 BSC H 0.76 1.27 0.030 0.050 J 0.20 0.30 0.008 0.012 C K 2.92 3.43 0.115 0.135 L 7.62 BSC 0.300 BSC J M --- 10 (cid:3) --- 10(cid:3) −T− N 0.76 1.01 0.030 0.040 SEATING N PLANE M D K H G 0.13 (0.005) M T A M B M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5773−3850 Sales Representative http://onsemi.com MC1455/D 11