MC14066B Quad Analog Switch/Quad Multiplexer The MC14066B consists of four independent switches capable of controlling either digital or analog signals. This quad bilateral switch is useful in signal gating, chopper, modulator, demodulator and CMOS logic implementation. http://onsemi.com The MC14066B is designed to be pin−for−pin compatible with the MC14016B, but has much lower ON resistance. Input voltage swings as large as the full supply voltage can be controlled via each independent control input. SOIC−14 SOEIAJ−14 TSSOP−14 Features D SUFFIX F SUFFIX DT SUFFIX • CASE 751A CASE 965 CASE 948G Triple Diode Protection on All Control Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc PIN ASSIGNMENT • Linearized Transfer Characteristics • Low Noise − 12 nV/√Cycle, f ≥ 1.0 kHz typical IN 1 1 14 VDD • Pin−for−Pin Replacement for CD4016, CD4016, MC14016B OUT 1 2 13 CONTROL 1 • For Lower RON, Use The HC4066 High−Speed CMOS Device OUT 2 3 12 CONTROL 4 • NLV Prefix for Automotive and Other Applications Requiring IN 2 4 11 IN 4 Unique Site and Control Change Requirements; AEC−Q100 CONTROL 2 5 10 OUT 4 Qualified and PPAP Capable • CONTROL 3 6 9 OUT 3 These Devices are Pb−Free and are RoHS Compliant VSS 7 8 IN 3 MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit MARKING DIAGRAMS VDD DC Supply Voltage Range −0.5 to +18.0 V 14 14 Vin, Vout Input or Output Voltage Range −0.5 to VDD + 0.5 V (DC or Transient) 14066BG MC14066B Iin Input Current (DC or Transient) ±10 mA AWLYWW ALYWG per Control Pin 1 1 ISW Switch Through Current ±25 mA SOIC−14 SOEIAJ−14 PD Power Dissipation, per Package 500 mW (Note 1) 14 TA Ambient Temperature Range −55 to +125 °C 14 Tstg Storage Temperature Range −65 to +150 °C A0L6Y6WB(cid:3) TL Lead Temperature 260 °C (cid:3) (8−Second Soldering) Stresses exceeding those listed in the Maximum Ratings table may damage the 1 device. If any of these limits are exceeded, device functionality should not be TSSOP−14 assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/(cid:2)C From 65(cid:2)C To 125(cid:2)C A = Assembly Location This device contains protection circuitry to guard against damage due to high WL, L = Wafer Lot static voltages or electric fields. However, precautions must be taken to avoid YY, Y = Year applications of any voltage higher than maximum rated voltages to this WW, W = Work Week high−impedance circuit. For proper operation, Vin and Vout should be constrained G or (cid:3) = Pb−Free Package to the range VSS ≤ (Vin or Vout) ≤ VDD. (Note: Microdot may be in either location) Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: August, 2014 − Rev. 10 MC14066B/D

MC14066B BLOCK DIAGRAM 13 CONTROL 1 2 1 OUT 1 IN 1 5 CONTROL 2 3 4 OUT 2 IN 2 6 CONTROL 3 9 OUT 3 8 IN 3 12 CONTROL 4 10 OUT 4 11 IN 4 VDD = PIN 14 VSS = PIN 7 LOGIC DIAGRAM AND TRUTH TABLE (1/4 OF DEVICE SHOWN) IN/OUT OUT/IN CONTROL Control Switch Logic Diagram Restrictions 0=VSS OFF VSS ≤ Vin ≤ VDD 1=VDD ON VSS ≤ Vout ≤ VDD CIRCUIT SCHEMATIC (1/4 OF CIRCUIT SHOWN) VDD VDD VDD VSS VDD VDD VDD VDD CMOS INPUT 300(cid:2) (cid:2) VSS VSS http://onsemi.com 2

MC14066B ELECTRICAL CHARACTERISTICS −55(cid:2)C 25(cid:2)C 125(cid:2)C Typ Characteristic Symbol VDD Test Conditions Min Max Min (Note 2) Max Min Max Unit SUPPLY REQUIREMENTS (Voltages Referenced to VEE) Power Supply Voltage VDD — 3.0 18 3.0 − 18 3.0 18 V Range Quiescent Current Per IDD 5.0 Control Inputs: − 0.25 − 0.005 0.25 − 7.5 (cid:4)A Package 10 Vin = VSS or VDD, − 0.5 − 0.010 0.5 − 15 15 Switch I/O: VSS (cid:2) VI/O − 1.0 − 0.015 1.0 − 30 (cid:2) VDD, and (cid:3)Vswitch (cid:2) 500 mV (3) To(Dtayl nSaumpipcl yP Cluusr Qreunitescent, ID(AV) 51.00 TAch =a n2n5e(cid:2)lC c oomnlyp oTnheent, (0.07 (cid:4)A/kHz) f + IDD (cid:4)A Per Package 15 (nVoitn in–c Vluoduet)d/R.)on, is Typical ((00..2306 (cid:4)(cid:4)AA//kkHHzz)) ff ++ IIDDDD CONTROL INPUTS (Voltages Referenced to VSS) Low−Level Input Voltage VIL 5.0 Ron = per spec, − 1.5 − 2.25 1.5 − 1.5 V 10 Ioff = per spec − 3.0 − 4.50 3.0 − 3.0 15 − 4.0 − 6.75 4.0 − 4.0 High−Level Input Voltage VIH 5.0 Ron = per spec, 3.5 − 3.5 2.75 − 3.5 − V 10 Ioff = per spec 7.0 − 7.0 5.50 − 7.0 − 15 11 − 11 8.25 − 11 − Input Leakage Current Iin 15 Vin = 0 or VDD − ±0.1 − ±0.00001 ±0.1 − ±1.0 (cid:4)A Input Capacitance Cin − − − − 5.0 7.5 − − pF SWITCHES IN AND OUT (Voltages Referenced to VSS) Recommended VI/O − Channel On or Off 0 VDD 0 − VDD 0 VDD Vp–p Peak−to−Peak Voltage Into or Out of the Switch Recommended Static or (cid:3)Vswitch − Channel On 0 600 0 − 600 0 300 mV Dynamic Voltage Across the Switch (Note3) (Figure 1) Output Offset Voltage VOO − Vin = 0 V, No Load − − − 10 − − − (cid:4)V ON Resistance Ron 5.0 (cid:3)Vswitch (cid:2) 500 mV (3), − 800 − 250 1050 − 1200 (cid:2) 10 Vin = VIL or VIH − 400 − 120 500 − 520 15 (Control), and Vin = − 220 − 80 280 − 300 0 to VDD (Switch) (cid:3)ON Resistance Between (cid:3)Ron 5.0 − 70 − 25 70 − 135 (cid:2) Any Two Channels 10 − 50 − 10 50 − 95 in the Same Package 15 − 45 − 10 45 − 65 Off−Channel Leakage Ioff 15 Vin = VIL or VIH − ±100 − ±0.05 ±100 − ±1000 nA Current (Figure 6) (Control) Channel to Channel or Any One Channel Capacitance, Switch I/O CI/O − Switch Off − − − 10 15 − − pF Capacitance, Feedthrough CI/O − − − − 0.47 − − − pF (Switch Off) − Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance. 3. For voltage drops across the switch ((cid:3)Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) http://onsemi.com 3

MC14066B ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25(cid:2)C unless otherwise noted.) VDD Typ Characteristic Symbol Vdc Min (Note 5) Max Unit Propagation Delay Times VSS = 0 Vdc tPLH, tPHL ns Input to Output (RL = 10 k(cid:2)) tPLH, tPHL = (0.17 ns/pF) CL + 15.5 ns 5.0 − 20 40 tPLH, tPHL = (0.08 ns/pF) CL + 6.0 ns 10 − 10 20 tPLH, tPHL = (0.06 ns/pF) CL + 4.0 ns 15 − 7.0 15 Control to Output (RL = 1 k(cid:2)) (Figure 2) tPHZ ns Output “1” to High Impedance 5.0 − 40 80 10 − 35 70 15 − 30 60 Output “0” to High Impedance tPLZ 5.0 − 40 80 ns 10 − 35 70 15 − 30 60 High Impedance to Output “1” tPZH 5.0 − 60 120 ns 10 − 20 40 15 − 15 30 High Impedance to Output “0” tPZL 5.0 − 60 120 ns 10 − 20 40 15 − 15 30 Second Harmonic Distortion VSS = – 5 Vdc − 5.0 − 0.1 − % (Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc, RL = 10 k(cid:2), f = 1.0 kHz) Bandwidth (Switch ON) (Figure 3) VSS = – 5 Vdc − 5.0 − 65 − MHz (RL = 1 k(cid:2), 20 Log (Vout/Vin) = − 3 dB, CL = 50 pF, Vin = 5 Vp−p) Feedthrough Attenuation (Switch OFF) VSS = – 5 Vdc − 5.0 − – 50 − dB (Vin = 5 Vp−p, RL = 1 k(cid:2), fin = 1.0 MHz) (Figure 3) Channel Separation (Figure 4) VSS = – 5 Vdc − 5.0 − – 50 − dB (Vin = 5 Vp−p, RL = 1 k(cid:2), fin = 8.0 MHz) (Switch A ON, Switch B OFF) Crosstalk, Control Input to Signal Output (Figure 5) mVp−p VSS = – 5 Vdc − 5.0 − 300 − (R1 = 1 k(cid:2), RL = 10 k(cid:2), Control tTLH = tTHL = 20 ns) 4. The formulas given are for the typical characteristics only at 25(cid:2)C. 5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 4

MC14066B TEST CIRCUITS Vout VC RL CL ON SWITCH CONTROL 20 ns Vin Vx SECTION 90% VDD OF IC VC 501%0% LOAD tPZH 90%tPHZVSS V Vout 10% Vin = VDD tPZL tPLZ Vx = VSS 90% SOURCE Vout 10% VVixn == VVDSDS Figure 1. (cid:3)V Across Switch Figure 2. Turn−On Delay Time Test Circuit and Waveforms VDD - VSS VC = VDD FOR BANDWIDTH TEST 2 VC = VSS FOR FEEDTHROUGH TEST VDD - VSS Vin 2 VDD RL CL Vin Vout RL CL VC VSS RL CL VDD VSS Figure 3. Bandwidth and Figure 4. Channel Separation Feedthrough Attenuation OFF CHANNEL UNDER TEST Vin A VDD Vout VSS 1 k CONTROL RL CL = 50 pF SECTION 10 k OF IC VSS VC = -(cid:3)5.0 V TO +(cid:3)5.0 V SWING VDD Figure 5. Crosstalk, Figure 6. Off Channel Leakage Control to Output http://onsemi.com 5

MC14066B VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k 1 k(cid:2) VDD RANGE X-Y PLOTTER VSS Figure 7. Channel Resistance (R ) Test Circuit ON TYPICAL RESISTANCE CHARACTERISTICS 350 350 300 300 S) S) M M H H O 250 O 250 E ( E ( C C N 200 N 200 A A T T S S SI SI N” RE 150 TA = 125°C N” RE 150 TA = 125°C , “ORON15000 -2(cid:3)555°C°C , “ORON 15000 -2(cid:3)555°°CC 0 0 -(cid:3)10 -(cid:3)8.0 -(cid:3)6.0 -(cid:3)4.0 -(cid:3)2.0 0 0.2 4.0 6.0 8.0 10 -(cid:3)10 -(cid:3)8.0 -(cid:3)6.0 -(cid:3)4.0 -(cid:3)2.0 0 0.2 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 8. V = 7.5 V, V = − 7.5 V Figure 9. V = 5.0 V, V = − 5.0 V DD SS DD SS 700 350 TA = 25°C 600 300 S) S) M M H H E (O 500 E (O 250 VDD = 2.5 V C C AN 400 AN 200 T T S S SI SI E 300 E 150 R R N” TA = 125°C N” 5.0 V , “ON200 25°C , “ON 100 7.5 V O O R 100 -(cid:3)55°C R 50 0 0 -(cid:3)10 -(cid:3)8.0 -(cid:3)6.0 -(cid:3)4.0 -(cid:3)2.0 0 0.2 4.0 6.0 8.0 10 -(cid:3)10 -(cid:3)8.0 -(cid:3)6.0 -(cid:3)4.0 -(cid:3)2.0 0 0.2 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 10. V = 2.5 V, V = − 2.5 V Figure 11. Comparison at 25°C, V = −(cid:2)V DD SS DD SS http://onsemi.com 6

MC14066B APPLICATIONS INFORMATION Figure A illustrates use of the Analog Switch. The V and/or below V are anticipated on the analog DD SS 0−to−5 V digital control signal is used to directly control a channels, external diodes (D ) are recommended as shown x 5 V peak−to−peak analog signal. in Figure B. These diodes should be small signal types able The digital control logic levels are determined by V to absorb the maximum anticipated current surges during DD and V . The V voltage is the logic high voltage, the V clipping. SS DD SS voltage is logic low. For the example, V = +5 V = logic The absolute maximum potential difference between DD high at the control inputs; V = GND = 0 V = logic low. V and V is 18 V. Most parameters are specified up to SS DD SS The maximum analog signal level is determined by V 15 V which is the recommended maximum difference DD and V . The analog voltage must not swing higher than between V and V . SS DD SS V or lower than V . DD SS The example shows a 5V peak−to−peak signal which allows no margin at either peak. If voltage transients above +5 V VDD VSS +(cid:3)5.0 V 5 Vp-p SWITCH ANALOG SIGNAL IN SWITCH 5 Vp-p +2.5 V +5 V OUT ANALOG SIGNAL GND EXTERNAL 0-TO-5 V DIGITAL MC14066B CMOS CONTROL SIGNALS DIGITAL CIRCUITRY Figure A. Application Example VDD VDD DX DX SWITCH SWITCH IN OUT DX DX VSS VSS Figure B. External Germanium or Schottky Clipping Diodes http://onsemi.com 7

MC14066B ORDERING INFORMATION Device Package Shipping† MC14066BDG SOIC−14 55 Units / Rail (Pb−Free) NLV14066BDG* SOIC−14 55 Units / Rail (Pb−Free) MC14066BDR2G SOIC−14 2500 / Tape & Reel (Pb−Free) NLV14066BDR2G* SOIC−14 2500 / Tape & Reel (Pb−Free) MC14066BDTR2G TSSOP−14 2500 / Tape & Reel (Pb−Free) NLV14066BDTR2G* TSSOP−14 2500 / Tape & Reel (Pb−Free) MC14066BFELG SOEIAJ−14 2000 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 8

MC14066B PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE K D A NOTES: B 1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.CONTROLLING DIMENSION: MILLIMETERS. 14 8 3.DIMENSION b DOES NOT INCLUDE DAMBAR A3 PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. H E 4.DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. L 5.MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 1 7 DETAIL A MILLIMETERS INCHES 0.25 M B M 13Xb DIM MIN MAX MIN MAX A 1.35 1.75 0.054 0.068 0.25 M C A S B S A1 0.10 0.25 0.004 0.010 A3 0.19 0.25 0.008 0.010 DETAIL A b 0.35 0.49 0.014 0.019 h A D 8.55 8.75 0.337 0.344 X 45(cid:2) E 3.80 4.00 0.150 0.157 e 1.27 BSC 0.050 BSC H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 e A1 C SEATING M ML 0.04 0(cid:2) 1.72 5(cid:2) 0.001 6(cid:2) 0.074 9(cid:2) PLANE SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9

MC14066B PACKAGE DIMENSIONS TSSOP−14 CASE 948G ISSUE B 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER 0.10 (0.004) M T U S V S ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. N MOLD FLASH OR GATE BURRS SHALL NOT 0.25 (0.010) EXCEED 0.15 (0.006) PER SIDE. 2XL/2 14 8 4I.NTDEIMRLEENASDIO FNL ABS DHO OERS PNROOT TINRCULSUIODNE. M INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. L B 5. DIMENSION K DOES NOT INCLUDE −U− N DAMBAR PROTRUSION. ALLOWABLE PIN 1 DAMBAR PROTRUSION SHALL BE 0.08 IDENT. F (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL 1 7 DETAIL E CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE 0.15 (0.006) T U S A K DETERMINED AT DATUM PLANE −W−. −V− K1 MILLIMETERS INCHES ÇÉÇÉÇÉ DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 J J1 ÇÉÇÉÇÉ B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 SECTION N−N D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 −W− J 0.09 0.20 0.004 0.008 C J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 0.10 (0.004) K1 0.19 0.25 0.007 0.010 −T− SEATING D G H DETAIL E ML 06 .(cid:2) 4 0 BS8C (cid:2) 00. 2(cid:2) 52 BS8C (cid:2) PLANE SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 14X 0.36 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10

MC14066B PACKAGE DIMENSIONS SOEIAJ−14 CASE 965 ISSUE B NOTES: (cid:4)(cid:5)1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. (cid:4)(cid:5)2. CONTROLLING DIMENSION: MILLIMETER. (cid:4)(cid:5)3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE 14 8 LE MEASURED AT THE PARTING LINE. MOLD FLASH Q1 O(0R.0 0P6R) OPTERRU SSIIDOEN.S SHALL NOT EXCEED 0.15 (cid:4)(cid:5)4. TERMINAL NUMBERS ARE SHOWN FOR E HE M(cid:2) REFERENCE ONLY. (cid:4)(cid:5)5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) 1 7 L TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DETAIL P DAMBAR CANNOT BE LOCATED ON THE LOWER Z RADIUS OR THE FOOT. MINIMUM SPACE D BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). VIEW P MILLIMETERS INCHES e A DIM MIN MAX MIN MAX c A --- 2.05 --- 0.081 A1 0.05 0.20 0.002 0.008 b 0.35 0.50 0.014 0.020 c 0.10 0.20 0.004 0.008 D 9.90 10.50 0.390 0.413 b A1 E 5.10 5.45 0.201 0.215 e 1.27 BSC 0.050 BSC 0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323 L 0.50 0.85 0.020 0.033 LE 1.10 1.50 0.043 0.059 M 0 (cid:2) 10 (cid:2) 0 (cid:2) 10 (cid:2) Q1 0.70 0.90 0.028 0.035 Z --- 1.42 --- 0.056 ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com MC14066B/D 11

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: MC14066BDG MC14066BDR2G MC14066BDTR2G