MC14051B, MC14052B, MC14053B Analog Multiplexers/Demultiplexers The MC14051B, MC14052B, and MC14053B analog multiplexers are digitally−controlled analog switches. The MC14051B effectively implements an SP8T solid state switch, the MC14052B a DP4T, and http://onsemi.com the MC14053B a Triple SPDT. All three devices feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved. Features 1 1 • Triple Diode Protection on Control Inputs SOIC−16 TSSOP−16 • Switch Function is Break Before Make D SUFFIX DT SUFFIX • CASE 751B CASE 948F Supply Voltage Range = 3.0 Vdc to 18 Vdc • Analog Voltage Range (V − V ) = 3.0 to 18 V DD EE MARKING DIAGRAMS Note: V must be ≤ V EE SS • Linearized Transfer Characteristics 16 • Low−noise − 12 nV/√Cycle, f ≥ 1.0 kHz Typical • 1405xBG Pin−for−Pin Replacement for CD4051, CD4052, and CD4053 AWLYWW • For 4PDT Switch, See MC14551B • 1 For Lower R , Use the HC4051, HC4052, or HC4053 ON SOIC−16 High−Speed CMOS Devices • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 16 Qualified and PPAP Capable 14 • 05xB These Devices are Pb−Free and are RoHS Compliant ALYW(cid:3) (cid:3) MAXIMUM RATINGS (Voltages Referenced to VSS) 1 Symbol Parameter Value Unit TSSOP−16 VDD DC Supply Voltage Range −0.5 to +18.0 V (Referenced to VEE, VSS ≥ VEE) x = 1, 2, or 3 Vin, Input or Output Voltage Range −0.5 to VDD + 0.5 V A = Assembly Location Vout (DC or Transient) (Referenced to VSS for WL, L = Wafer Lot Control Inputs and VEE for Switch I/O) Y = Year WW, W = Work Week Iin Input Current (DC or Transient) +10 mA G or (cid:3) = Pb−Free Package per Control Pin ISW Switch Through Current ±25 mA (Note: Microdot may be in either location) PD Power Dissipation per Package (Note 1) 500 mW ORDERING INFORMATION TA Ambient Temperature Range −55 to +125 °C See detailed ordering and shipping information in the package Tstg Storage Temperature Range −65 to +150 °C dimensions section on page 9 of this data sheet. TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/(cid:2)C From 65(cid:2)C To 125(cid:2)C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: August, 2014 − Rev. 14 MC14051B/D

MC14051B, MC14052B, MC14053B MC14051B MC14052B MC14053B 8−Channel Analog Dual 4−Channel Analog Triple 2−Channel Analog Multiplexer/Demultiplexer Multiplexer/Demultiplexer Multiplexer/Demultiplexer 6 INHIBIT 6 INHIBIT 6 INHIBIT 11 A CONTROLS 10 A 11 A X 14 CONTROLS 10 B 9 B X 13 CONTROLS 10 B 9 C 12 X0 9 C 13 X0 14 X1 COMMONS 12 X0 Y 15 COMMONS 1154 XX12 X 3 SWITCHES 1115 XX23 OUT/IN SWITCHES 123 YX01 OUT/IN COMMON SWITCHES 12 X3 IN/OUT 1 Y0 IN/OUT 1 Y1 IN/OUT 1 X4 OUT/IN 5 Y1 Y 3 5 Z0 Z 4 5 X5 2 Y2 3 Z1 2 X6 4 Y3 4 X7 VDD = PIN 16 VDD = PIN 16 VDD = PIN 16 VSS = PIN 8 VSS = PIN 8 VSS = PIN 8 VEE = PIN 7 VEE = PIN 7 VEE = PIN 7 Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS. PIN ASSIGNMENT MC14051B MC14052B MC14053B X4 1 16 VDD Y0 1 16 VDD Y1 1 16 VDD X6 2 15 X2 Y2 2 15 X2 Y0 2 15 Y X 3 14 X1 Y 3 14 X1 Z1 3 14 X X7 4 13 X0 Y3 4 13 X Z 4 13 X1 X5 5 12 X3 Y1 5 12 X0 Z0 5 12 X0 INH 6 11 A INH 6 11 X3 INH 6 11 A VEE 7 10 B VEE 7 10 A VEE 7 10 B VSS 8 9 C VSS 8 9 B VSS 8 9 C http://onsemi.com 2

MC14051B, MC14052B, MC14053B ELECTRICAL CHARACTERISTICS −55(cid:2)C 25(cid:2)C 125(cid:2)C Typ Characteristic Symbol VDD Test Conditions Min Max Min (Note 2) Max Min Max Unit SUPPLY REQUIREMENTS (Voltages Referenced to VEE) Power Supply Voltage VDD − VDD – 3.0 ≥ VSS ≥ VEE 3.0 18 3.0 − 18 3.0 18 V Range Quiescent Current Per IDD 5.0 Control Inputs: − 5.0 − 0.005 5.0 − 150 (cid:3)A Package 10 Vin = VSS or VDD, − 10 − 0.010 10 − 300 15 Switch I/O: VEE (cid:2) VI/O (cid:2) − 20 − 0.015 20 − 600 VDD, and (cid:2)Vswitch (cid:2) 500 mV (Note 3) T(oDtayln Saumpipc lyP lCusurrent ID(AV) 51.00 TcAh =a n2n5e(cid:2)lC c oomnlpyo (nTehnet, (0.07 (cid:3)A/kHz) f + IDD (cid:3)A Quiescent, Per Package 15 (nVoitn in–c Vluoduet)d/R.)on, is Typical ((00..2306 (cid:3)(cid:3)AA//kkHHzz)) ff ++ IIDDDD CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS) Low−Level Input Voltage VIL 5.0 Ron = per spec, − 1.5 − 2.25 1.5 − 1.5 V 10 Ioff = per spec − 3.0 − 4.50 3.0 − 3.0 15 − 4.0 − 6.75 4.0 − 4.0 High−Level Input Voltage VIH 5.0 Ron = per spec, 3.5 − 3.5 2.75 − 3.5 − V 10 Ioff = per spec 7.0 − 7.0 5.50 − 7.0 − 15 11 − 11 8.25 − 11 − Input Leakage Current Iin 15 Vin = 0 or VDD − ±0.1 − ±0.00001 ±0.1 − 1.0 (cid:3)A Input Capacitance Cin − − − − 5.0 7.5 − − pF SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE) Recommended VI/O − Channel On or Off 0 VDD 0 − VDD 0 VDD VPP Peak−to−Peak Voltage Into or Out of the Switch Recommended Static or (cid:2)Vswitch − Channel On 0 600 0 − 600 0 300 mV Dynamic Voltage Across the Switch (Note 3) (Figure 5) Output Offset Voltage VOO − Vin = 0 V, No Load − − − 10 − − − (cid:3)V ON Resistance Ron 5.0 (cid:2)Vswitch (cid:2) 500 mV − 800 − 250 1050 − 1200 (cid:4) 10 (Note 3) Vin = VIL or VIH − 400 − 120 500 − 520 15 (Control), and Vin = − 220 − 80 280 − 300 0 to VDD (Switch) (cid:2)ON Resistance Between (cid:2)Ron 5.0 − 70 − 25 70 − 135 (cid:4) Any Two Channels in the 10 − 50 − 10 50 − 95 Same Package 15 − 45 − 10 45 − 65 Off−Channel Leakage Ioff 15 Vin = VIL or VIH − ±100 − ±0.05 ±100 − ±1000 nA Current (Figure 10) (Control) Channel to Channel or Any One Channel Capacitance, Switch I/O CI/O − Inhibit = VDD − − − 10 − − − pF Capacitance, Common O/I CO/I − Inhibit = VDD pF (MC14051B) − − − 60 − − − (MC14052B) − − − 32 − − − (MC14053B) − − − 17 − − − Capacitance, Feedthrough CI/O − Pins Not Adjacent − − − 0.15 − − − pF (Channel Off) − Pins Adjacent − − − 0.47 − − − Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance. 3. For voltage drops across the switch ((cid:2)Vswitch) > 600 mV (> 300 mV at high temperature), excessive VDD current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) http://onsemi.com 3

MC14051B, MC14052B, MC14053B ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25(cid:2)C) (VEE (cid:2) VSS unless otherwise indicated) VDD – VEE Typ (Note 5) Characteristic Symbol Vdc All Types Max Unit Propagation Delay Times (Figure 6) tPLH, tPHL ns Switch Input to Switch Output (RL = 1 k(cid:4)) MC14051 tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns 5.0 35 90 tPLH, tPHL = (0.08 ns/pF) CL + 11 ns 10 15 40 tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns 15 12 30 MC14052 ns tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns 5.0 30 75 tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns 10 12 30 tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns 15 10 25 MC14053 ns tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns 5.0 25 65 tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns 10 8.0 20 tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns 15 6.0 15 Inhibit to Output (RL = 10 k(cid:4), VEE = VSS) tPHZ, tPLZ, ns Output “1” or “0” to High Impedance, or tPZH, tPZL High Impedance to “1” or “0” Level MC14051B 5.0 350 700 10 170 340 15 140 280 MC14052B 5.0 300 600 ns 10 155 310 15 125 250 MC14053B 5.0 275 550 ns 10 140 280 15 110 220 Control Input to Output (RL = 1 k(cid:4), VEE = VSS) tPLH, tPHL ns MC14051B 5.0 360 720 10 160 320 15 120 240 MC14052B 5.0 325 650 ns 10 130 260 15 90 180 MC14053B 5.0 300 600 ns 10 120 240 15 80 160 Second Harmonic Distortion − 10 0.07 − % (RL = 10K(cid:4), f = 1 kHz) Vin = 5 VPP Bandwidth (Figure 7) BW 10 17 − MHz (RL = 50 (cid:4), Vin = 1/2 (VDD−VEE) p−p, CL = 50pF 20 Log (Vout/Vin) = − 3 dB) Off Channel Feedthrough Attenuation (Figure 7) − 10 –50 − dB RL = 1K(cid:4), Vin = 1/2 (VDD − VEE) p−p fin = 4.5 MHz — MC14051B fin = 30 MHz — MC14052B fin = 55 MHz — MC14053B Channel Separation (Figure 8) − 10 –50 − dB (RL = 1 k(cid:4), Vin = 1/2 (VDD−VEE) p−p, fin = 3.0 MHz Crosstalk, Control Input to Common O/I (Figure 9) − 10 75 − mV (R1 = 1 k(cid:4), RL = 10 k(cid:4) Control tTLH = tTHL = 20 ns, Inhibit = VSS) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. The formulas given are for the typical characteristics only at 25(cid:2)C. 5. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance. http://onsemi.com 4

MC14051B, MC14052B, MC14053B VDD VDD VDD IN/OUT OUT/IN VEE VDD LEVEL CONVERTED IN/OUT OUT/IN CONTROL CONTROL VEE Figure 1. Switch Circuit Schematic TRUTH TABLE 16 VDD Control Inputs INH(cid:2)(cid:2)6 BINARY TO 1-OF-8 Select ON Switches A(cid:2)11 LEVEL DECODER WITH Inhibit C* B A MC14051B MC14052B MC14053B B(cid:2)10 CONVERTER INHIBIT C(cid:2)(cid:2)9 0 0 0 0 X0 Y0 X0 Z0 Y0 X0 0 0 0 1 X1 Y1 X1 Z0 Y0 X1 8 VSS 7 VEE 0 0 1 0 X2 Y2 X2 Z0 Y1 X0 X0(cid:2)13 0 0 1 1 X3 Y3 X3 Z0 Y1 X1 X1(cid:2)14 0 1 0 0 X4 Z1 Y0 X0 X2(cid:2)15 0 1 0 1 X5 Z1 Y0 X1 X3(cid:2)12 3(cid:2)X 0 1 1 0 X6 Z1 Y1 X0 X4(cid:2)(cid:2)1 0 1 1 1 X7 Z1 Y1 X1 X5(cid:2)(cid:2)5 1 x x x None None None X6(cid:2)(cid:2)2 *Not applicable for MC14052 X7(cid:2)(cid:2)4 x = Don’t Care Figure 2. MC14051B Functional Diagram 16 VDD 16 VDD INH(cid:2)(cid:2)6 BINARY TO 1-OF-4 LEVEL AB(cid:2)(cid:2)1(cid:2)09 CONVERTER DECOINDHEIBRI TWITH INHA(cid:2)(cid:2)(cid:2)116 LEVEL BIDNEACROYD TEOR 1 W-OITFH-2 B(cid:2)10 CONVERTER INHIBIT C(cid:2)(cid:2)9 8 VSS 7 VEE X0(cid:2)12 8 VSS 7 VEE X1(cid:2)14 13(cid:2)X X2(cid:2)15 X0(cid:2)12 14(cid:2)X X3(cid:2)11 X1(cid:2)13 Y0(cid:2)(cid:2)1 Y0(cid:2)(cid:2)2 15(cid:2)Y Y1(cid:2)(cid:2)5 Y1(cid:2)(cid:2)1 3(cid:2)(cid:2)Y Y2(cid:2)(cid:2)2 Z0(cid:2)(cid:2)5 4(cid:2)(cid:2)Z Y3(cid:2)(cid:2)4 Z1(cid:2)(cid:2)3 Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram http://onsemi.com 5

MC14051B, MC14052B, MC14053B TEST CIRCUITS ON SWITCH CONTROL PULSE A SECTION B GENERATOR OF IC C LOAD Vout V INH RL CL SOURCE VDD VEE VEE VDD Figure 5. (cid:2)V Across Switch Figure 6. Propagation Delay Times, Control and Inhibit to Output A, B, and C inputs used to turn ON or OFF the switch under test. A RL B A C B ON Vout C VSS INH RL CL = 50 pF INH OFF Vout Vin RL CL = 50 pF VDD - VEE 2 VDD - VEE Vin 2 Figure 7. Bandwidth and Off−Channel Figure 8. Channel Separation Feedthrough Attenuation (Adjacent Channels Used For Setup) OFF CHANNEL UNDER TEST VDD A CONTROL VEE B SECTION OTHER C Vout OF IC CHANNEL(S) VEE INH RL CL = 50 pF VDD R1 COMMON VEE VDD Figure 9. Crosstalk, Control Input to Figure 10. Off Channel Leakage Common O/I NOTE:See also Figures 7 and 8 in the MC14016B data sheet. http://onsemi.com 6

MC14051B, MC14052B, MC14053B VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k 1 k(cid:4) VDD RANGE X-Y PLOTTER VEE = VSS Figure 11. Channel Resistance (R ) Test Circuit ON TYPICAL RESISTANCE CHARACTERISTICS 350 350 300 300 S) S) M M H H O 250 O 250 E ( E ( C C N 200 N 200 A A T T S S SI SI N” RE 150 TA = 125°C N” RE 150 TA = 125°C , “ORON 15000 -2(cid:3)555°C°C , “ORON 15000 -2(cid:3)555°°CC 0 0 -(cid:3)10 -(cid:3)8.0 -(cid:3)6.0 -(cid:3)4.0 -(cid:3)2.0 0 0.2 4.0 6.0 8.0 10 -(cid:3)10 -(cid:3)8.0 -(cid:3)6.0 -(cid:3)4.0 -(cid:3)2.0 0 0.2 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 12. V = 7.5 V, V = − 7.5 V Figure 13. V = 5.0 V, V = − 5.0 V DD EE DD EE 700 350 TA = 25°C 600 300 S) S) M M H H E (O 500 E (O 250 VDD = 2.5 V C C AN 400 AN 200 T T S S SI SI E 300 E 150 R R N” TA = 125°C N” 5.0 V , “ON 200 25°C , “ON 100 7.5 V O O R 100 -(cid:3)55°C R 50 0 0 -(cid:3)10 -(cid:3)8.0 -(cid:3)6.0 -(cid:3)4.0 -(cid:3)2.0 0 0.2 4.0 6.0 8.0 10 -(cid:3)10 -(cid:3)8.0 -(cid:3)6.0 -(cid:3)4.0 -(cid:3)2.0 0 0.2 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 14. V = 2.5 V, V = − 2.5 V Figure 15. Comparison at 25°C, V = −(cid:2)V DD EE DD EE http://onsemi.com 7

MC14051B, MC14052B, MC14053B APPLICATIONS INFORMATION Figure A illustrates use of the on−chip level converter peak. If voltage transients above V and/or below V are DD EE detailed in Figures 2, 3, and 4. The 0−to−5 V Digital Control anticipated on the analog channels, external diodes (Dx) are signal is used to directly control a 9 V analog signal. recommended as shown in Figure B. These diodes should be p−p The digital control logic levels are determined by V small signal types able to absorb the maximum anticipated DD and V . The V voltage is the logic high voltage; the V current surges during clipping. SS DD SS voltage is logic low. For the example, V = +5 V = logic The absolute maximum potential difference between DD high at the control inputs; V = GND = 0 V = logic low. V and V is 18.0 V. Most parameters are specified up to SS DD EE The maximum analog signal level is determined by V 15 V which is the recommended maximum difference DD and V . The V voltage determines the maximum between V and V . EE DD DD EE recommended peak above V . The V voltage Balanced supplies are not required. However, V must SS EE SS determines the maximum swing below V . For the be greater than or equal to V . For example, V = +10 V, SS EE DD example, V − V = 5 V maximum swing above V ; V = +5 V, and V – 3 V is acceptable. See the Table DD SS SS SS EE V − V = 5 V maximum swing below V . The example below. SS EE SS shows a ±4.5 V signal which allows a 1/2 volt margin at each +5 V -5 V VDD VSS VEE +4.5 V +5 V 9 Vp-p SWITCH ANALOG SIGNAL I/O COMMON 9 Vp-p GND MC14051B O/I ANALOG SIGNAL MC14052B EXTERNAL MC14053B CMOS −4.5 V DIGITAL 0-TO-5 V DIGITAL INHIBIT, CIRCUITRY CONTROL SIGNALS A, B, C Figure A. Application Example VDD VDD DX DX ANALOG COMMON I/O O/I DX DX VEE VEE Figure B. External Germanium or Schottky Clipping Diodes POSSIBLE SUPPLY CONNECTIONS Control Inputs VDD VSS VEE Logic High/Logic Low Maximum Analog Signal Range In Volts In Volts In Volts In Volts In Volts +8 0 –8 +8/0 +8 to –8 = 16 Vp–p +5 0 –12 +5/0 +5 to –12 = 17 Vp–p +5 0 0 +5/0 +5 to 0 = 5 Vp–p +5 0 –5 +5/0 +5 to –5 = 10 Vp–p +10 +5 –5 +10/ +5 +10 to –5 = 15 Vp–p http://onsemi.com 8

MC14051B, MC14052B, MC14053B ORDERING INFORMATION Device Package Shipping† MC14051BDG SOIC−16 48 Units / Rail (Pb−Free) NLV14051BDG* SOIC−16 48 Units / Rail (Pb−Free) MC14051BDR2G SOIC−16 2500 / Tape & Reel (Pb−Free) NLV14051BDR2G* SOIC−16 2500 / Tape & Reel (Pb−Free) MC14051BDTR2G TSSOP−16 2500 / Tape & Reel (Pb−Free) NLV14051BDTR2G* TSSOP−16 2500 / Tape & Reel (Pb−Free) MC14052BDG SOIC−16 48 Units / Rail (Pb−Free) NLV14052BDG* SOIC−16 48 Units / Rail (Pb−Free) MC14052BDR2G SOIC−16 2500 / Tape & Reel (Pb−Free) NLV14052BDR2G* SOIC−16 2500 / Tape & Reel (Pb−Free) MC14052BDTR2G TSSOP−16 2500 / Tape & Reel (Pb−Free) NLV14052BDTR2G* TSSOP−16 2500 / Tape & Reel (Pb−Free) MC14053BDG SOIC−16 48 Units / Rail (Pb−Free) NLV14053BDG* SOIC−16 48 Units / Rail (Pb−Free) MC14053BDR2G SOIC−16 2500 / Tape & Reel (Pb−Free) NLV14053BDR2G* SOIC−16 2500 / Tape & Reel (Pb−Free) MC14053BDTR2G TSSOP−16 2500 / Tape & Reel (Pb−Free) NLV14053BDTR2G* TSSOP−16 2500 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 9

MC14051B, MC14052B, MC14053B PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F ISSUE B 16X K REF NOTES: 0.10 (0.004) M T U S V S (cid:4)(cid:2)1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 0.15 (0.006) T U S K (cid:4)(cid:2)2. CONTROLLING DIMENSION: MILLIMETER. (cid:4)(cid:2)3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. ÇÇK1Ç PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER 16 9 ÇÉÇÉÇÉ SIDE. 2XL/2 J1 (cid:4)(cid:2)4. DIMENSION B DOES NOT INCLUDE INTERLEAD ÇÉÇÉÇÉ FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER B SECTION N−N SIDE. L −U− J (cid:4)(cid:2)5.PROTDRIMUSEINOSNIO. ANL KLO DWOAEBSL NEO DTA IMNBCALRU DPER ODATMRUBSAIRON SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K PIN 1 DIMENSION AT MAXIMUM MATERIAL CONDITION. IDENT. N (cid:4)(cid:2)6. TERMINAL NUMBERS ARE SHOWN FOR 1 8 0.25 (0.010) REFERENCE ONLY. (cid:4)(cid:2)7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. M 0.15 (0.006) T U S A MILLIMETERS INCHES N DIM MIN MAX MIN MAX −V− A 4.90 5.10 0.193 0.200 F B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 DETAIL E D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 C −W− J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 0.10 (0.004) K1 0.19 0.25 0.007 0.010 −T− SPELAATNIENG D G H DETAIL E ML 06 .(cid:2) 4 0 BSC8 (cid:2) 00. 2(cid:2) 52 BSC8 (cid:2) SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 16X 0.36 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10

MC14051B, MC14052B, MC14053B PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 −A− NOTES: ISSUE K 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. −B− P8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION 1 8 0.25 (0.010) M B S SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX G A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 F D 0.35 0.49 0.014 0.019 K R X 45(cid:2) F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 C K 0.10 0.25 0.004 0.009 M 0 (cid:2) 7 (cid:2) 0 (cid:2) 7 (cid:2) −T− SEATING P 5.80 6.20 0.229 0.244 PLANE M J R 0.25 0.50 0.010 0.019 D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X1.12 1 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com MC14051B/D 11

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