MC10EP31, MC100EP31 3.3(cid:2)V / 5(cid:2)V ECL D Flip‐Flop with Set and Reset Description The MC10/100EP31 is a D flip-flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. www.onsemi.com With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, 8 8 level triggered signals. Data enters the master portion of the flip-flop when CLK is low and is transferred to the slave, and thus the outputs, 1 1 upon a positive transition of the CLK. The 100 Series contains temperature compensation. SOIC−8 NB TSSOP−8 DFN8 D SUFFIX DT SUFFIX MN SUFFIX CASE 751−07 CASE 948R−02 CASE 506AA Features • 340ps Typical Propagation Delay • Maximum Frequency = > 3 GHz Typical MARKING DIAGRAMS* • PECL Mode Operating Range: V = 3.0 V to 5.5 V with V = 0 V CC EE 8 8 • NECL Mode Operating Range: HEP31 (cid:2)M VCC = 0 V with VEE = −3.0 V to −5.5 V ALYW ALHYPW31(cid:2) 5O (cid:2) • (cid:2) (cid:2) Open Input Default State 1 4 1 1 • Q Output Will Default LOW with Inputs Open or at V EE • These Devices are Pb-Free, Halogen Free and are RoHS Compliant 8 8 KEP31 (cid:2) KP31 M ALYW ALYW(cid:2) J (cid:2) (cid:2) 3 (cid:2) 1 1 1 4 SOIC−8 NB TSSOP−8 DFN8 H = MC10 A = Assembly Location K = MC100 L = Wafer Lot 5O = MC10 Y = Year 3J = MC100 W = Work Week M = Date Code (cid:2) = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2016 − Rev. 11 MC10EP31/D

MC10EP31, MC100EP31 Table 1. PIN DESCRIPTION SET 1 8 VCC Pin Function CLK* ECL Clock Inputs S Reset* ECL Asynchronous Reset D 2 D 7 Q Set* ECL Asynchronous Set D* ECL Data Input Flip Flop Q, Q ECL Data Outputs CLK 3 6 Q VCC Positive Supply R VEE Negative Supply EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal con- RESET 4 5 VEE duit. Electrically connect to the most neg- ative supply (GND) or leave unconnec- ted, floating open. *Pins will default LOW when left open. Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Table 2. TRUTH TABLE D SET RESET CLK Q L L L Z L H L L Z H X H L X H X L H X L X H H X UNDEF Z = LOW to HIGH Transition Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k(cid:2) Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC−8 NB Level 1 TSSOP−8 Level 3 DFN8 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94V−0 @ 0.125 in Transistor Count 75 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2

MC10EP31, MC100EP31 Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0V 6 V VEE NECL Mode Power Supply VCC = 0V −6 V VI PECL Mode Input Voltage VEE = 0V VI ≤ VCC 6 V NECL Mode Input Voltage VCC = 0V VI ≥ VEE −6 Iout Output Current Continuous 50 mA Surge 100 TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C (cid:3)JA Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC−8 NB 190 °C/W 500 lfpm SOIC−8 NB 130 (cid:3)JC Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W (cid:3)JA Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP−8 185 °C/W 500 lfpm TSSOP−8 140 (cid:3)JC Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W (cid:3)JA Thermal Resistance (Junction-to-Ambient) 0 lfpm DFN8 129 °C/W 500 lfpm DFN8 84 Tsol Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C (cid:3)JC Thermal Resistance (Junction-to-Case) (Note 2) DFN8 35 to 40 °C/W Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) www.onsemi.com 3

MC10EP31, MC100EP31 Table 5. 10EP DC CHARACTERISTICS, PECL (VCC = 3.3V, VEE = 0V (Note 1)) −40°C 25°C 85°C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA VOH Output HIGH Voltage (Note 2) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 2) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single-Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single-Ended) 1365 1690 1430 1755 1490 1815 mV IIH Input HIGH Current 150 150 150 (cid:4)A IIL Input LOW Current 0.5 0.5 0.5 (cid:4)A NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3V to −2.2V. 2. All loading with 50(cid:2) to VCC − 2.0V. Table 6. 10EP DC CHARACTERISTICS, PECL (VCC = 5.0V, VEE = 0V (Note 1)) −40°C 25°C 85°C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA VOH Output HIGH Voltage (Note 2) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 2) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single-Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single-Ended) 3065 3390 3130 3455 3190 3515 mV IIH Input HIGH Current 150 150 150 (cid:4)A IIL Input LOW Current 0.5 0.5 0.5 (cid:4)A NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0V to −0.5V. 2. All loading with 50(cid:2) to VCC − 2.0V. Table 7. 10EP DC CHARACTERISTICS, NECL (VCC = 0V; VEE = −5.5V to −3.0V (Note 1)) −40°C 25°C 85°C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA VOH Output HIGH Voltage (Note 2) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 2) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV VIH Input HIGH Voltage (Single-Ended) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single-Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV IIH Input HIGH Current 150 150 150 (cid:4)A IIL Input LOW Current 0.5 0.5 0.5 (cid:4)A NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. 2. All loading with 50(cid:2) to VCC − 2.0V. www.onsemi.com 4

MC10EP31, MC100EP31 Table 8. 100EP DC CHARACTERISTICS, PECL (VCC = 3.3V, VEE = 0V (Note 1)) −40°C 25°C 85°C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA VOH Output HIGH Voltage (Note 2) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 2) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single-Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single-Ended) 1355 1675 1355 1675 1355 1675 mV IIH Input HIGH Current 150 150 150 (cid:4)A IIL Input LOW Current 0.5 0.5 0.5 (cid:4)A NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3V to −2.2V. 2. All loading with 50(cid:2) to VCC − 2.0V. Table 9. 100EP DC CHARACTERISTICS, PECL (VCC = 5.0V, VEE = 0V (Note 1)) −40°C 25°C 85°C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA VOH Output HIGH Voltage (Note 2) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 2) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VIH Input HIGH Voltage (Single-Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single-Ended) 3055 3375 3055 3375 3055 3375 mV IIH Input HIGH Current 150 150 150 (cid:4)A IIL Input LOW Current 0.5 0.5 0.5 (cid:4)A NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0V to −0.5V. 2. All loading with 50(cid:2) to VCC − 2.0V. Table 10. 100EP DC CHARACTERISTICS, NECL (VCC = 0V; VEE = −5.5V to −3.0V (Note 1)) −40°C 25°C 85°C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA VOH Output HIGH Voltage (Note 2) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 2) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV VIH Input HIGH Voltage (Single-Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single-Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV IIH Input HIGH Current 150 150 150 (cid:4)A IIL Input LOW Current 0.5 0.5 0.5 (cid:4)A NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. 2. All loading with 50(cid:2) to VCC − 2.0V. www.onsemi.com 5

MC10EP31, MC100EP31 Table 11. AC CHARACTERISTICS (VCC = 0V; VEE = −3.0V to −5.5V or VCC = 3.0V to 5.5V; VEE = 0V (Note 1)) −40°C 25°C 85°C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit fmax Maximum Frequency > 3 > 3 > 3 GHz (Figure 2) tPLH, Propagation Delay to ps tPHL Output Differential CLK to Q, Q 250 330 400 270 340 410 300 370 440 S, R to Q, Q 300 380 450 330 400 470 360 430 500 tRR Set/Reset Recovery 225 225 225 ps tS Setup Time 100 100 100 ps tH Hold Time 150 150 150 tPW Minimum Pulse width ps SET, RESET 550 450 550 450 550 450 tJITTER Cycle-to-Cycle Jitter 0.2 < 1 0.2 < 1 0.2 < 1 ps (Figure 2) tr Output Rise/Fall Times ps tf Q, Q (20% − 80%) 50 120 180 60 130 200 70 150 220 NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Measured using a 750mV source, 50% duty cycle clock source. All loading with 50(cid:2) to VCC−2.0V. 1100 11 1000 10 900 9 S) (mV) Tpp 780000 78 ps (RMT U U VO 600 6 RO E T 500 5ÉJITÉ 400 4ÉÉ 300 3ÉÉ 200 2 ÉÉÉÉÉÉÉÉÉ 100 1 ÉÉÉÉÉÉÉÉÉ(JITTER) 0 0 1000 2000 3000 4000 5000 6000 FREQUENCY (MHz) Figure 2. F /Jitter max www.onsemi.com 6

MC10EP31, MC100EP31 Q Zo = 50 (cid:2) D Driver Receiver Device Device Q Zo = 50 (cid:2) D 50 (cid:2) 50 (cid:2) VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices) www.onsemi.com 7

MC10EP31, MC100EP31 ORDERING INFORMATION Device Package Shipping† MC10EP31DG SOIC−8 NB 98 Units / Rail (Pb-Free) MC10EP31DR2G SOIC−8 NB 2500 / Tape & Reel (Pb-Free) MC10EP31DTG TSSOP−8 100 Units / Rail (Pb-Free) MC10EP31DTR2G TSSOP−8 2500 / Tape & Reel (Pb-Free) MC10EP31MNR4G DFN8 1000 / Tape & Reel (Pb-Free) MC100EP31DG SOIC−8 NB 98 Units / Rail (Pb-Free) MC100EP31DR2G SOIC−8 NB 2500 / Tape & Reel (Pb-Free) MC100EP31DTG TSSOP−8 100 Units / Rail (Pb-Free) MC100EP31DTR2G TSSOP−8 2500 / Tape & Reel (Pb-Free) MC100EP31MNR4G DFN8 1000 / Tape & Reel (Pb-Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPS(cid:3) I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices www.onsemi.com 8

MC10EP31, MC100EP31 PACKAGE DIMENSIONS SOIC−8 NB D SUFFIX CASE 751−07 ISSUE AK NOTES: −X− 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. 7M5A1X−I0M1U TMH RMUA T7E51R−IA0L6 CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 C NX 45(cid:4) B 3.80 4.00 0.150 0.157 SEATING C 1.35 1.75 0.053 0.069 PLANE D 0.33 0.51 0.013 0.020 −Z− G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 0.10 (0.004) J 0.19 0.25 0.007 0.010 H D M J K 0.40 1.27 0.016 0.050 M 0 (cid:4) 8 (cid:4) 0 (cid:4) 8 (cid:4) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:2) (cid:3) mm SCALE 6:1 inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 9

MC10EP31, MC100EP31 PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX CASE 948R−02 ISSUE A 8x K REF NOTES: 0.10 (0.004) M T U S V S 1. DIMENSIONING AND TOLERANCING PER ANSI 0.15 (0.006) T U S Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. 2XL/2 8 5 0.25 (0.010) PORRO GTARTUES BIOUNRSR SO RS HGAALTLE N BOUTR ERXSC. EMEODL D0. 1F5LASH B L −U− 4. (D0I.M00E6N) SPIEORN SBI DDEO.ES NOT INCLUDE INTERLEAD 1 4 M FLASH OR PROTRUSION. INTERLEAD FLASH OR PIN 1 PROTRUSION SHALL NOT EXCEED 0.25 (0.010) IDENT PER SIDE. 0.15 (0.006) T U S A 5. RTEERFEMRINEANLC NEU OMNBLEYR.S ARE SHOWN FOR F −V− 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DETAIL E MILLIMETERS INCHES DIM MIN MAX MIN MAX A 2.90 3.10 0.114 0.122 C B 2.90 3.10 0.114 0.122 C 0.80 1.10 0.031 0.043 0.10 (0.004) D 0.05 0.15 0.002 0.006 −W− −T− SPELAATNIENG D G GF 0.04.065 BSC0.70 0.001.0626 B0S.C028 K 0.25 0.40 0.010 0.016 DETAIL E L 4.90 BSC 0.193 BSC M 0 (cid:4) 6 (cid:4) 0 (cid:4) 6 (cid:4) www.onsemi.com 10

MC10EP31, MC100EP31 PACKAGE DIMENSIONS DFN8 2x2, 0.5 P MN SUFFIX CASE 506AA ISSUE F D A NOTES: L L 1. DIMENSIONING AND TOLERANCING PER B ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. L1 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. REFEPRINE ONCNEE ÇÇ E DOEPTTIAONILA LA 4. CPAODP LAASN WAREILTLY A ASP TPHLEIE TSE TROM TINHAEL ESX.POSED CONSTRUCTIONS 2X 0.10 C ÇÇ MILLIMETERS DIM MIN MAX A 0.80 1.00 A3 A1 0.00 0.05 2X 0.10 C TOP VIEW EXPOSED CuÉÉMOLD CMPD ÉÇÉÇ A3 0.20 REF b 0.20 0.30 ÉÇÉÇ ÇÇ D 2.00 BSC D2 1.10 1.30 0.10 C DETAIL B A A1 E 2.00 BSC E2 0.70 0.90 DETAIL B e 0.50 BSC K 0.30 REF ALTERNATE L 0.25 0.35 0.08 C (A3) CONSTRUCTIONS L1 −−− 0.10 NOTE 4 A1 C SEATING SIDE VIEW PLANE RECOMMENDED SOLDERING FOOTPRINT* DETAIL A 8X D2 8X L 1.30 0.50 1 4 PACKAGE OUTLINE E2 0.90 2.30 K 8 5 8X b e/2 1 0.10 C A BB e 8X 0.50 0.05 C NOTE 3 0.30 PITCH BOTTOM VIEW DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative www.onsemi.com MC10EP31/D 11