MC100EPT26 3.3(cid:2)V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator Description www.onsemi.com The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead 8 8 package and the 1:2 fanout design of the EPT26 makes it ideal for 1 1 applications which require the low skew duplication of a signal in a tightly packed PC board. SOIC−8 NB TSSOP−8 DFN8 The V output allows the EPT26 to be used in a Single-Ended D SUFFIX DT SUFFIX MN SUFFIX BB input mode. In this mode the V output is tied to the D0 input for a CASE 751−07 CASE 948R−02 CASE 506AA BB non-inverting buffer or the D0 input for an inverting buffer. If used, the V pin should be bypassed to ground with > 0.01(cid:2)(cid:3)F capacitor. BB MARKING DIAGRAMS* For a Single-Ended direct connection, use an external voltage reference source such as a resistor divider. Do not use V for a BB 8 8 Single-Ended direct connection or port to another device. KPT26 KA26 1 3W M(cid:2) ALYW ALYW(cid:2) (cid:2) Features (cid:2) (cid:2) 4 • 1.4ns Typical Propagation Delay 1 1 • Maximum Frequency = > 275MHz Typical SOIC−8 NB TSSOP−8 DFN8 • The 100 Series Contains Temperature Compensation • A = Assembly Location Operating Range: V = 3.0V to 3.6V with GND = 0V CC L = Wafer Lot • 24mA TTL outputs Y = Year • W = Work Week Q Outputs Will Default LOW with Inputs Open or at V EE M = Date Code • V Output (cid:2) = Pb-Free Package BB • These Devices are Pb-Free, Halogen Free and are RoHS Compliant (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping† MC100EPT26DG SOIC−8 NB 98 Units/Tube (Pb-Free) MC100EPT26DR2G SOIC−8 NB 2500 Tape & Reel (Pb-Free) MC100EPT26DTG TSSOP−8 100 Tape & Reel (Pb-Free) MC100RPT26DTR2G TSSOP−8 2500 Tape & Reel (Pb-Free) MC100EPT26MNR4G DFN8 1000 Tape & Reel (Pb-Free) †For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2016 − Rev. 17 MC100EPT26/D

MC100EPT26 Table 1. PIN DESCRIPTION NC 1 8 VCC Pin Function Q0, Q1 LVTTL Outputs D0**, D1** Differential LVPECL Inputs Pair D 2 7 Q0 VCC Positive Supply LVTTL VBB Output Reference Voltage D 3 6 Q1 GND Ground NC No Connect EP (DFN8 only) Thermal exposed pad must be con- VBB 4 LVPECL 5 GND nected to a sufficient thermal conduit. Electric- ally connect to the most negative supply (GND) or leave unconnected, floating open. (Top View) ** Pins will default to VCC/2 when left open. Figure 1. 8-Lead Pinout and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 50k(cid:4) Internal Input Pullup Resistor 50k(cid:4) ESD Protection Human Body Model > 1.5 kV Machine Model > 100V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC−8 NB Level 1 TSSOP−8 Level 3 DFN8 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94V−0 @ 0.125 in Transistor Count 117 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2

MC100EPT26 Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC Positive Power Supply GND = 0V 3.8 V VIN Input Voltage GND = 0V VI ≤ VCC 0 to 3.8 V IBB VBB Sink/Source ±0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C (cid:5)JA Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC−8 NB 190 °C/W 500 lfpm SOIC−8 NB 130 (cid:5)JC Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W (cid:5)JA Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP−8 185 °C/W 500 lfpm TSSOP−8 140 (cid:5)JC Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W (cid:5)JA Thermal Resistance (Junction-to-Ambient) 0 lfpm DFN8 129 °C/W 500 lfpm DFN8 84 Tsol Wave Solder (Pb-Free) 265 °C (cid:5)JC Thermal Resistance (Junction-to-Case) (Note 1) DFN8 35 to 40 °C/W Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) Table 4. PECL INPUT DC CHARACTERISTICS (VCC = 3.3V; GND = 0.0V (Note 1)) −40°C 25°C 85°C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit VIH Input HIGH Voltage (Single-Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single-Ended) 1355 1675 1355 1675 1355 1675 mV VBB Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 V VIHCMR Input HIGH Voltage Common Mode 1.2 3.3 1.2 3.3 1.2 3.3 V Range (Differential) (Note 2) IIH Input HIGH Current 150 150 150 (cid:3)A IIL Input LOW Current (cid:3)A D −150 −150 −150 D −150 −150 −150 NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input parameters vary 1:1 with VCC. 2. VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 3

MC100EPT26 Table 5. TTL OUTPUT DC CHARACTERISTICS (VCC = 3.3V; GND = 0.0V; TA = −40°C to 85°C) Symbol Characteristic Condition Min Typ Max Unit VOH Output HIGH Voltage IOH = −3.0 mA 2.4 V VOL Output LOW Voltage IOL = 24 mA 0.5 V ICCH Power Supply Current 10 25 35 mA ICCL Power Supply Current 15 34 40 mA IOS Output Short Circuit Current −50 −150 mA NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 6. AC CHARACTERISTICS (VCC = 3.0V to 3.6V; GND = 0.0V (Note 1)) −40°C 25°C 85°C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit fmax Maximum Frequency (Figure 2) 275 350 275 350 275 350 MHz tPLH, Propagation Delay to 1.2 1.5 2.0 1.2 1.5 2.0 1.3 1.7 2.2 ns tPHL Output Differential (Note 2) 1.2 1.5 1.8 1.2 1.5 1.8 1.2 1.5 1.8 tSK+ + Within Device Skew + + 15 60 15 60 20 85 ps tSK− − Within Device Skew − − 20 85 20 85 30 85 tSKPP Device-to-Device Skew (Note 3) 100 500 100 500 100 500 tJITTER Random Clock Jitter (RMS) (Figure 2) ps @ ≤ 200 MHz 6 30 6 30 6 30 @ > 200 MHz 20 275 40 275 170 275 VPP InputVoltage Swing (Differential Configuration) 150 800 1200 150 800 1200 150 800 1200 mV tr Output Rise/Fall Times ps tf (0.8 V−2.0 V) Q, Q 330 600 950 330 600 950 330 650 950 NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Measured with a 750 mV 50% duty-cycle clock source. RL = 500 (cid:4) to GND and CL = 20 pF to GND. Refer to Figure 3. 2. Reference (VCC = 3.3 V ± 5%; GND = 0 V) 3. Skews are measured between outputs under identical transitions. 3.0 12 VOL (cid:2) 0.5V VOH S) M R s p 2.0 8 R ( E T T V) K JI ( OH JITTER OC V L C 1.0 4 M O D N A R 0.0 0 0 100 200 300 FREQUENCY (MHz) Figure 2. Typical V / Jitter versus Frequency (25(cid:2)C) OH www.onsemi.com 4

MC100EPT26 APPLICATION TTL RECEIVER CHARACTERISTIC TEST *CL includes CL* RL fixture capacitance AC TEST LOAD GND Figure 3. TTL Output Loading Used for Device Evaluation Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPS(cid:3) I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices www.onsemi.com 5

MC100EPT26 PACKAGE DIMENSIONS SOIC−8 NB D SUFFIX CASE 751−07 ISSUE AK NOTES: −X− 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. 7M5A1X−I0M1U TMH RMUA T7E51R−IA0L6 CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 C NX 45(cid:4) B 3.80 4.00 0.150 0.157 SEATING C 1.35 1.75 0.053 0.069 PLANE D 0.33 0.51 0.013 0.020 −Z− G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 0.10 (0.004) J 0.19 0.25 0.007 0.010 H D M J K 0.40 1.27 0.016 0.050 M 0 (cid:4) 8 (cid:4) 0 (cid:4) 8 (cid:4) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:2) (cid:3) mm SCALE 6:1 inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 6

MC100EPT26 PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX CASE 948R−02 ISSUE A 8x K REF NOTES: 0.10 (0.004) M T U S V S (cid:2)(cid:3)1. DIMENSIONING AND TOLERANCING PER ANSI 0.15 (0.006) T U S Y14.5M, 1982. (cid:2)(cid:3)2. CONTROLLING DIMENSION: MILLIMETER. (cid:2)(cid:3)3. DIMENSION A DOES NOT INCLUDE MOLD 2XL/2 8 5 0.25 (0.010) FFLLAASSHH. OPRR OGTARTEU SBIUORNRSS O SRH GAALTL EN BOUTR ERXSC. EMEODLD B L −U− (cid:2)(cid:3)4.0.15D I(M0.E00N6S)I OPENR B S DIDOEE.S NOT INCLUDE 1 4 M INTERLEAD FLASH OR PROTRUSION. PIN 1 INTERLEAD FLASH OR PROTRUSION SHALL NOT IDENT EXCEED 0.25 (0.010) PER SIDE. 0.15 (0.006) T U S A (cid:2)(cid:3)5.REFTEERREMNINCAEL O NNULMY.BERS ARE SHOWN FOR F −V− (cid:2)(cid:3)6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DETAIL E MILLIMETERS INCHES DIM MIN MAX MIN MAX A 2.90 3.10 0.114 0.122 C B 2.90 3.10 0.114 0.122 C 0.80 1.10 0.031 0.043 0.10 (0.004) D 0.05 0.15 0.002 0.006 −W− −T− SPELAATNIENG D G GF 0.04.065 BSC0.70 0.001.0626 B0S.C028 K 0.25 0.40 0.010 0.016 DETAIL E L 4.90 BSC 0.193 BSC M 0 (cid:4) 6 (cid:4) 0 (cid:4) 6 (cid:4) www.onsemi.com 7

MC100EPT26 PACKAGE DIMENSIONS DFN8 2x2, 0.5 P MN SUFFIX CASE 506AA ISSUE F D A NOTES: L L 1. DIMENSIONING AND TOLERANCING PER B ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. L1 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. REFEPRINE ONCNEE ÇÇ E DOEPTTIAONILA LA 4. CPAODP LAASN WAREILTLY A ASP TPHLEIE TSE TROM TINHAEL ESX.POSED CONSTRUCTIONS 2X 0.10 C ÇÇ MILLIMETERS DIM MIN MAX A 0.80 1.00 A3 A1 0.00 0.05 2X 0.10 C TOP VIEW EXPOSED CuÉÉMOLD CMPD ÉÇÉÇ A3 0.20 REF b 0.20 0.30 ÉÇÉÇ ÇÇ D 2.00 BSC D2 1.10 1.30 0.10 C DETAIL B A A1 E 2.00 BSC E2 0.70 0.90 DETAIL B e 0.50 BSC K 0.30 REF ALTERNATE L 0.25 0.35 0.08 C (A3) CONSTRUCTIONS L1 −−− 0.10 NOTE 4 A1 C SEATING SIDE VIEW PLANE RECOMMENDED SOLDERING FOOTPRINT* DETAIL A 8X D2 8X L 1.30 0.50 1 4 PACKAGE OUTLINE E2 0.90 2.30 K 8 5 8X b e/2 1 0.10 C A BB e 8X 0.50 0.05 C NOTE 3 0.30 PITCH BOTTOM VIEW DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative www.onsemi.com MC100EPT26/D 8

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: MC100EPT26DG MC100EPT26DR2G MC100EPT26DTG MC100EPT26DTR2G MC100EPT26MNR4G