FUJITSU SEMICONDUCTOR DATA SHEET DS501-00012-0v01-E Memory FRAM 64 K (8 K  8) Bit SPI MB85RS64 ■ DESCRIPTION MB85RS64 is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192 words  8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85RS64 adopts the Serial Peripheral Interface (SPI). The MB85RS64 is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85RS64 can be used for 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. MB85RS64 does not take long time to write data unlike Flash memories nor E2PROM, and MB85RS64 takes no wait time. ■ FEATURES • Bit configuration : 8,192 words  8 bits (cid:129) Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) (cid:129) Operating frequency : 20 MHz (Max) (cid:129) High endurance : 10 Billion Read/writes (cid:129) Data retention : 10 years (+85 C) (cid:129) Operating power supply voltage : 2.7 V to 3.6 V (cid:129) Low power consumption : Operating power supply current 1.5(TBD)mA (Typ@20 MHz) Standby current 10 A(TBD) (Typ) (cid:129) Operation ambient temperature range :  40 C to +85 C (cid:129) Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant Copyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.10

MB85RS64 ■ PIN ASSIGNMENT (TOP VIEW) CS 1 8 VDD SO 2 7 HOLD WP 3 6 SCK GND 4 5 SI (FPT-8P-M02) ■ PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name Functional description Chip Select pin This is an input pin to make chips select. When CS is the “H” level, device is in deselect (standby) status as long as device is not write status internally, and SO becomes High- 1 CS Z. Inputs from other pins are ignored at this time. When CS is the “L” level, device is in select (active) status. CS has to be the “L” level before inputting op-code. The Chip Se- lect pin is pulled up internally to the VDD pin. Write Protect pin 3 WP This is a pin to control writing to a status register. When WP is the “L” level, writing to a status register is not operated. Hold pin This pin is used to interrupt serial input/output without making chips deselect. When 7 HOLD HOLD is the “L” level, hold operation is activated, SO becomes High-Z, SCK and SI be- come don’t care. While the hold operation, CS has to be retained the “L” level. Serial Clock pin 6 SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. Serial Data Input pin 5 SI This is an input pin of serial data. This inputs op-code, address, and writing data. Serial Data Output pin 2 SO This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 GND Ground pin 2 DS501-00012-0v01-E

MB85RS64 ■ BLOCK DIAGRAM SI Serial-Parallel Converter r e d o ec FRAM Cell Array D 8,192 ✕ 8 w r o CS nte R u o C FRAM SCK cuit ss Status Register r e Ci dr ol Ad r HOLD ont Column Decoder/Sense Amp/ C Write Amp WP Data Register SO Parallel-Serial Converter DS501-00012-0v01-E 3

MB85RS64 ■ SPI MODE MB85RS64 corresponds to the SPI mode 0 (CPOL  0, CPHA  0) , and SPI mode 3 (CPOL  1, CPHA  1) . CS SCK SI 7 6 5 4 3 2 1 0 MSB LSB SPI Mode 0 CS SCK SI 7 6 5 4 3 2 1 0 MSB LSB SPI Mode 3 4 DS501-00012-0v01-E

MB85RS64 ■ SERIAL PERIPHERAL INTERFACE (SPI) MB85RS64 works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use. SCK MOSI MISO SO SI SCK SO SI SCK SPI MB85RS64 MB85RS64 Microcontroller CS HOLD CS HOLD SS1 SS2 HOLD1 HOLD2 MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select System Configuration with SPI Port SO SI SCK Microcontroller MB85RS64 CS HOLD System Configuration without SPI Port DS501-00012-0v01-E 5

MB85RS64 ■ STATUS REGISTER Bit No. Bit Name Function Status Register Write Protect This is a bit composed of nonvolatile memories (FRAM). WPEN protects 7 WPEN writing to a status register (see “■ WRITING PROTECT”) relating with WP input. Writing with the WRSR command and reading with the RDSR com- mand are possible. Not Used Bits These are bits composed of nonvolatile memories, writing with the WRSR 6 to 4  command is possible, and “000” is written before shipment. These bits are not used but they are read with the RDSR command. Block Protect 3 BP1 This is a bit composed of nonvolatile memory. This defines block size for writing protect with the WRITE command (see “■ BLOCK PROTECT”). 2 BP0 Writing with the WRSR command and reading with the RDSR command are possible. Write Enable Latch This indicates FRAM Array and status register are writable. The WREN command is for setting, and the WRDI command is for resetting. With the RDSR command, reading is possible but writing is not possible with the 1 WEL WRSR command. WEL is reset after the following operations. The time when power is up. The time when the WRDI command is input. The time when the WRSR command is input. The time when the WRITE command is input. 0 0 This is a bit fixed to “0”. ■ OP-CODE MB85RS64 accepts 6 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command are not performed. Name Description Op-code WREN Set Write Enable Latch 0000 0110 B WRDI Reset Write Enable Latch 0000 0100 B RDSR Read Status Register 0000 0101 B WRSR Write Status Register 0000 0001 B READ Read Memory Code 0000 0011 B WRITE Write Memory Code 0000 0010 B 6 DS501-00012-0v01-E

MB85RS64 ■ COMMAND  WREN The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before writing operation (WRSR command and WRITE command) . CS 0 1 2 3 4 5 6 7 SCK SI Invalid 0 0 0 0 0 1 1 0 Invalid High-Z SO  WRDI The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRITE command and WRSR command) are not performed when WEL is reset. CS 0 1 2 3 4 5 6 7 SCK SI Invalid 0 0 0 0 0 1 0 0 Invalid High-Z SO DS501-00012-0v01-E 7

MB85RS64  RDSR The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. Continuously reading status register is enabled by keep on sending SCK before rising CS with the RDSR command. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 1 Invalid Data Out High-Z SO Invalid MSB LSB  WRSR The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot be written. The SI value corresponding to bit 0 is ignored. the WP signal level shall be fixed before performing the WRSR command, and do not change the WP signal level until the end of command sequence. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Instruction Data In SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 MSB LSB High-Z SO 8 DS501-00012-0v01-E

MB85RS64  READ The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ are input to SI. The 3-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by con- tinuously sending clock for 8 cycles each to SCK before CS is risen. When it reaches the most significant address, it rolls over to come back to the starting address, and reading cycle keeps on infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK 16-bit Address OP-CODE SI 0 0 0 0 0 0 1 1 X X X 12 11 10 5 4 3 2 1 0 Invalid MSB LSBMSB Data Out LSB High-Z SO 7 6 5 4 3 2 1 0 Invalid  WRITE The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address and 8 bits of writing data are input to SI. The most significant address bit is invalid. When 8 bits of writing data is input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but if you continue sending the writing data for 8 bits each before CS is risen, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over, comes back to the starting address, and writing cycle can be continued infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK 16-bit Address Data In OP-CODE SI 0 0 0 0 0 0 1 0 X X X 12 11 10 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB LSB MSB LSB High-Z SO DS501-00012-0v01-E 9

MB85RS64 ■ BLOCK PROTECT Writing protect block is configured by the WRITE command with BP1, BP0 value of the status register. BP1 BP0 Protected Block 0 0 None 0 1 1800 to 1FFF (upper 1/4) H H 1 0 1000 to 1FFF (upper 1/2) H H 1 1 0000 to 1FFF (all) H H ■ WRITING PROTECT Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, WPEN, WP as shown in the table. WEL WPEN WP Protected Blocks Unprotected Blocks Status Register 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected ■ HOLD OPERATION Hold status is retained without aborting a command if HOLD is the “L” level while CS is the “L” level. The timing for starting and ending hold status depends on the SCK to be the “H” level or the “L” level when a HOLD pin input is transited to the hold condition as shown in the diagram below. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become don’t care. And, SO becomes High-Z while reading command (RDSR, READ) . If CS is risen with hold status, a command is aborted and device is reset. CS SCK HOLD Hold Condition Hold Condition 10 DS501-00012-0v01-E

MB85RS64 ■ ABSOLUTE MAXIMUM RATINGS Rating Parameter Symbol Unit Min Max Power supply voltage* V  0.5  4.0 V DD Input voltage* V  0.5 V  0.5 V IN DD Output voltage* V  0.5 V  0.5 V OUT DD Operation ambient temperature T  40  85 C A Storage temperature Tstg  40  125 C *:These parameters are based on the condition that V is 0 V. SS WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Value Parameter Symbol Unit Min Typ Max Power supply voltage* V 2.7 3.3 3.6 V DD Input high voltage* V V  0.8  V  0.3 V IH DD DD Input low voltage* V  0.5  V  0.2 V IL DD Operation ambient temperature T  40   85 C A *:These parameters are based on the condition that V is 0 V. SS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS501-00012-0v01-E 11

MB85RS64 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) Value Parameter Symbol Condition Unit Min Typ Max CS  0 V to V   200 DD Input leakage current |ILI| WP, HOLD, SCK, A   10 SI  0 V to V DD Output leakage current |I | V  0 V to V   10 A LO OUT DD Operating power supply current I SCK  20 MHz  1.5 (TBD) 2.0 (TBD) mA DD Standby current I SCK  SI  CS  V  10 (TBD) 15 (TBD) A SB DD Output high voltage V I  2 mA V  0.5  V V OH OH DD DD Output low voltage V I  2 mA V  0.4 V OL OL SS 12 DS501-00012-0v01-E

MB85RS64 2. AC Characteristics Value Parameter Symbol Unit Min Max SCK clock frequency f 0 20 MHz CK Clock high time t 25  ns CH Clock low time t 25  ns CL Chip select set up time t 10  ns CSU Chip select hold time t 10  ns CSH Output disable time t  20 ns OD Output data valid time t  18 ns ODV Output hold time t 0  ns OH Deselect time t 60  ns D Data in rise time t  50 ns R Data fall time t  50 ns F Data set up time t 5  ns SU Data hold time t 5  ns H HOLD set up time t 10  ns HS HOLD hold time t 10  ns HH HOLD output floating time t  20 ns HZ HOLD output active time t  20 ns LZ AC Test Condition Power supply voltage : 2.7 V to 3.6 V Operation ambient temperature :  40 C to  85 C Input voltage magnitude : 0.3 V to 2.7 V Input rising time : 5 ns Input falling time : 5 ns Input judge level : V /2 DD Output judge level : V /2 DD DS501-00012-0v01-E 13

MB85RS64 AC Load Equivalent Circuit 3.3 V 1.2 k Output 30 pF 0.95 k 3. Pin Capacitance Value Parameter Symbol Conditions Unit Min Max Output capacitance CO VDD  VIN  VOUT  0 V  10 pF Input capacitance CI f  1 MHz, TA   25 C  10 pF 14 DS501-00012-0v01-E

MB85RS64 ■ TIMING DIAGRAM  Serial Data Timing tD CS tCSH tCSU tCH tCL SCK tSU tH SI Valid in tODV tOH tOD High-Z High-Z SO : H or L  Hold Timing CS SCK tHS tHS tHS tHS tHH tHH tHH tHH HOLD High-Z High-Z SO tHZ tLZ tHZ tLZ DS501-00012-0v01-E 15

MB85RS64 ■ POWER ON/OFF SEQUENCE tpd tf tr tpu VDD VDD 2.7 V 2.7 V VIH (Min) VIH (Min) 1.0 V 1.0 V VIL (Max) VIL (Max) GND GND CS CS >VDD × 0.8 * CS : don't care CS >VDD × 0.8 * CS * : CS (Max) < V  0.3 V DD Note : Because turning the power-on from an intermediate level may cause malfunctions, when the power is turned on, V is required to be started from 0 V. DD If the device does not operate within the specified conditions of read cycle, write cycle, power on/ off sequence, memory data can not be guaranteed. Value Parameter Symbol Unit Min Max CS level hold time at power OFF tpd 400  ns CS level hold time at power ON tpu 0.1  ms Power supply falling time tf 100  s/V Power supply rising time tr 30  s/V ■ NOTES ON USE Data written before performing IR reflow is not guaranteed after IR reflow. 16 DS501-00012-0v01-E

MB85RS64 ■ ORDERING INFORMATION Minimum shipping Part number Package Shipping form quantity 8-pin plastic SOP MB85RS64PNF-G-JNE1 Tube 1 (FPT-8P-M02) 8-pin plastic SOP MB85RS64PNF-G-JNERE1 Embossed Carrier tape 1500 (FPT-8P-M02) DS501-00012-0v01-E 17

MB85RS64 ■ PACKAGE DIMENSION 8-pin plastic SOP Lead pitch 1.27 mm Package width × 3.9 mm × 5.05 mm package length Lead shape Gullwing Sealing method Plastic mold Mounting height 1.75 mm MAX Weight 0.06 g (FPT-8P-M02) 8-pin plastic SOP Note 1)*1 : These dimensions include resin protrusion. (FPT-8P-M02) Note 2)*2 : These dimensions do not include resin protrusion. Note 3)Pins width and pins thickness include plating thickness. Note 4)Pins width do not include tie bar cutting remainder. *15.05–+00..2205 .199–+..000180 0.22–+00..0073 .009+–..000031 8 5 *23.90±0.30 6.00±0.40 (.154±.012) (.236±.016) Details of "A" part 45° 1.55±0.20 (Mounting height) (.061±.008) 0.25(.010) 0.40(.016) "A" 0~8° 1 4 1.27(.050) 0.44±0.08 (.017±.003) 0.13(.005)M 0.50±0.20 0.15±0.10 (.020±.008) (.006±.004) 0.60±0.15 (Stand off) (.024±.006) 00..1100((..000044)) Dimensions in mm (inches). C 2002-2010 FUJITSUSEMICONDUCTOR LIMITED F08004S-c-4-9 Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 18 DS501-00012-0v01-E

MB85RS64 MEMO DS501-00012-0v01-E 19

MB85RS64 FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America Asia Pacific FUJITSU SEMICONDUCTOR AMERICA, INC. FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 1250 E. Arques Avenue, M/S 333 151 Lorong Chuan, Sunnyvale, CA 94085-5401, U.S.A. #05-08 New Tech Park 556741 Singapore Tel: +1-408-737-5600 Fax: +1-408-737-5999 Tel : +65-6281-0770 Fax : +65-6281-0220 http://us.fujitsu.com/micro/ http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. FUJITSU SEMICONDUCTOR EUROPE GmbH Rm. 3102, Bund Center, No.222 Yan An Road (E), Pittlerstrasse 47, 63225 Langen, Germany Shanghai 200002, China Tel: +49-6103-690-0 Fax: +49-6103-690-122 Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://emea.fujitsu.com/semiconductor/ http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. FUJITSU SEMICONDUCTOR KOREA LTD. 10/F., World Commerce Centre, 11 Canton Road, 902 Kosmo Tower Building, 1002 Daechi-Dong, Tsimshatsui, Kowloon, Hong Kong Gangnam-Gu, Seoul 135-280, Republic of Korea Tel : +852-2377-0226 Fax : +852-2376-3269 Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://cn.fujitsu.com/fsp/ http://kr.fujitsu.com/fsk/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris- ing in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over- current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department