(cid:27) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:4) (cid:4)(cid:6)(cid:7) (cid:8)(cid:9) (cid:10)(cid:11)(cid:10)(cid:6)(cid:7) (cid:1)(cid:12)(cid:13)(cid:8)(cid:14)(cid:15)(cid:16)(cid:2)(cid:17)(cid:17)(cid:18)(cid:13) (cid:19)(cid:20)(cid:6)(cid:5)(cid:4)(cid:5) (cid:13)(cid:14)(cid:17)(cid:18) (cid:21)(cid:19)(cid:14)(cid:7)(cid:18)(cid:19)(cid:22)(cid:19)(cid:18)(cid:15)(cid:18)(cid:14)(cid:7)(cid:18)(cid:19) (cid:23)(cid:14)(cid:8)(cid:16) ±(cid:24)(cid:10)(cid:6)(cid:25)(cid:7) (cid:18)(cid:20)(cid:21) (cid:26)(cid:19)(cid:9)(cid:8)(cid:18)(cid:15)(cid:8)(cid:14)(cid:9)(cid:17) SLLS409K − JANUARY 2000 − REVISED MARCH 2004 (cid:1) RS-232 Bus-Pin ESD Protection Exceeds DB, DW, OR PW PACKAGE ±15 kV Using Human-Body Model (HBM) (TOP VIEW) (cid:1) Meets or Exceeds the Requirements of EN 1 20 FORCEOFF TIA/EIA-232-F and ITU v.28 Standards (cid:1) C1+ 2 19 VCC Operates With 3-V to 5.5-V V Supply CC V+ 3 18 GND (cid:1) Operates Up To 250 kbit/s C1− 4 17 DOUT1 (cid:1) Two Drivers and Two Receivers C2+ 5 16 RIN1 (cid:1) Low Standby Current...1 µA Typical C2− 6 15 ROUT1 (cid:1) External Capacitors...4 × 0.1 µF V− 7 14 FORCEON DOUT2 8 13 DIN1 (cid:1) Accepts 5-V Logic Input With 3.3-V Supply RIN2 9 12 DIN2 (cid:1) Alternative High-Speed Pin-Compatible ROUT2 10 11 INVALID Device (1 Mbit/s) − SNx5C3223 (cid:1) Applications − Battery-Powered Systems, PDAs, Notebooks, Laptops, Palmtop PCs, and Hand-Held Equipment description/ordering information The MAX3223 consists of two line drivers, two line receivers, and a dual charge-pump circuit with ±15-kV ESD protection pin to pin (serial-port connection pins, including GND). The device meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-V supply. The device operates at data signaling rates up to 250 kbit/s and a maximum of 30-V/µs driver output slew rate. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube of 25 MAX3223CDW SSOOIICC ((DDWW)) MMAAXX33222233CC Reel of 2000 MAX3223CDWR Tube of 70 MAX3223CDB −−00°°CC ttoo 7700°°CC SSSSOOPP ((DDBB)) MMAA33222233CC Reel of 2000 MAX3223CDBR Tube of 70 MAX3223CPW TTSSSSOOPP ((PPWW)) MMAA33222233CC Reel of 2000 MAX3223CPWR Tube of 25 MAX3223IDW SSOOIICC ((DDWW)) MMAAXX33222233II Reel of 2000 MAX3223IDWR Tube of 70 MAX3223IDB −−4400°°CC ttoo 8855°°CC SSSSOOPP ((DDBB)) MMBB33222233II Reel of 2000 MAX3223IDBR Tube of 70 MAX3223IPW TTSSSSOOPP ((PPWW)) MMBB33222233II Reel of 2000 MAX3223IPWR †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:26)(cid:19)(cid:9)(cid:21)(cid:12)(cid:15)(cid:8)(cid:14)(cid:9)(cid:17) (cid:21)(cid:2)(cid:8)(cid:2) (cid:28)(cid:29)(cid:30)(cid:31)!"#$(cid:28)(cid:31)(cid:29) (cid:28)% &’!!((cid:29)$ #% (cid:31)(cid:30) )’*+(cid:28)&#$(cid:28)(cid:31)(cid:29) ,#$((cid:11) Copyright  2004, Texas Instruments Incorporated (cid:26)!(cid:31),’&$% &(cid:31)(cid:29)(cid:30)(cid:31)!" $(cid:31) %)(&(cid:28)(cid:30)(cid:28)&#$(cid:28)(cid:31)(cid:29)% )(! $-( $(!"% (cid:31)(cid:30) (cid:8)(.#% (cid:14)(cid:29)%$!’"((cid:29)$% %$#(cid:29),#!, /#!!#(cid:29)$0(cid:11) (cid:26)!(cid:31),’&$(cid:28)(cid:31)(cid:29) )!(cid:31)&(%%(cid:28)(cid:29)1 ,(cid:31)(% (cid:29)(cid:31)$ (cid:29)(&(%%#!(cid:28)+0 (cid:28)(cid:29)&+’,( $(%$(cid:28)(cid:29)1 (cid:31)(cid:30) #++ )#!#"($(!%(cid:11) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:4) (cid:27) (cid:4)(cid:6)(cid:7) (cid:8)(cid:9) (cid:10)(cid:11)(cid:10)(cid:6)(cid:7) (cid:1)(cid:12)(cid:13)(cid:8)(cid:14)(cid:15)(cid:16)(cid:2)(cid:17)(cid:17)(cid:18)(cid:13) (cid:19)(cid:20)(cid:6)(cid:5)(cid:4)(cid:5) (cid:13)(cid:14)(cid:17)(cid:18) (cid:21)(cid:19)(cid:14)(cid:7)(cid:18)(cid:19)(cid:22)(cid:19)(cid:18)(cid:15)(cid:18)(cid:14)(cid:7)(cid:18)(cid:19) (cid:23)(cid:14)(cid:8)(cid:16) ±(cid:24)(cid:10)(cid:6)(cid:25)(cid:7) (cid:18)(cid:20)(cid:21) (cid:26)(cid:19)(cid:9)(cid:8)(cid:18)(cid:15)(cid:8)(cid:14)(cid:9)(cid:17) SLLS409K − JANUARY 2000 − REVISED MARCH 2004 description/ordering information (continued) Flexible control options for power management are available when the serial port is inactive. The auto-powerdown feature functions when FORCEON is low and FORCEOFF is high. During this mode of operation, if the device does not sense a valid RS-232 signal, the driver outputs are disabled. If FORCEOFF is set low and EN is high, both drivers and receivers are shut off, and the supply current is reduced to 1 µA. Disconnecting the serial port or turning off the peripheral drivers causes auto-powerdown to occur. Auto-powerdown can be disabled when FORCEON and FORCEOFF are high. With auto-powerdown enabled, the device is activated automatically when a valid signal is applied to any receiver input. The INVALID output is used to notify the user if an RS-232 signal is present at any receiver input. INVALID is high (valid data) if any receiver input voltage is greater than 2.7 V or less than −2.7 V, or has been between −0.3 V and 0.3 V for less than 30 µs. INVALID is low (invalid data) if the receiver input voltage is between −0.3 V and 0.3 V for more than 30 µs. Refer to Figure 4 for receiver input levels. Function Tables EACH DRIVER INPUTS OOUUTTPPUUTT VALID RIN DRIVER STATUS DIN FORCEON FORCEOFF DOUT RS-232 LEVEL X X L X Z Powered off L H H X H NNoorrmmaall ooppeerraattiioonn wwiitthh H H H X L auto-powerdown disabled L L H Yes H NNoorrmmaall ooppeerraattiioonn wwiitthh H L H Yes L auto-powerdown enabled L L H No Z PPoowweerreedd ooffff bbyy H L H No Z auto-powerdown feature H = high level, L = low level, X = irrelevant, Z = high impedance EACH RECEIVER INPUTS OOUUTTPPUUTT VALID RIN RIN EN ROUT RS-232 LEVEL L L X H H L X L X H X Z Open L No H H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = input disconnected or connected driver off 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:27) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:4) (cid:4)(cid:6)(cid:7) (cid:8)(cid:9) (cid:10)(cid:11)(cid:10)(cid:6)(cid:7) (cid:1)(cid:12)(cid:13)(cid:8)(cid:14)(cid:15)(cid:16)(cid:2)(cid:17)(cid:17)(cid:18)(cid:13) (cid:19)(cid:20)(cid:6)(cid:5)(cid:4)(cid:5) (cid:13)(cid:14)(cid:17)(cid:18) (cid:21)(cid:19)(cid:14)(cid:7)(cid:18)(cid:19)(cid:22)(cid:19)(cid:18)(cid:15)(cid:18)(cid:14)(cid:7)(cid:18)(cid:19) (cid:23)(cid:14)(cid:8)(cid:16) ±(cid:24)(cid:10)(cid:6)(cid:25)(cid:7) (cid:18)(cid:20)(cid:21) (cid:26)(cid:19)(cid:9)(cid:8)(cid:18)(cid:15)(cid:8)(cid:14)(cid:9)(cid:17) SLLS409K − JANUARY 2000 − REVISED MARCH 2004 logic diagram (positive logic) 13 17 DIN1 DOUT1 12 8 DIN2 DOUT2 20 FORCEOFF 11 14 Auto-powerdown INVALID FORCEON 1 EN 15 16 ROUT1 RIN1 10 9 ROUT2 RIN2 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V CC Positive output supply voltage range, V+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Negative output supply voltage range, V− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to −7 V Supply voltage difference, V+ − V− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V Input voltage range, V: Driver, FORCEOFF, FORCEON, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V I Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 V to 25 V Output voltage range, V :Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −13.2 V to 13.2 V O Receiver, INVALID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V CC Package thermal impedance, θ (see Notes 2 and 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W JA DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to network GND. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:4) (cid:27) (cid:4)(cid:6)(cid:7) (cid:8)(cid:9) (cid:10)(cid:11)(cid:10)(cid:6)(cid:7) (cid:1)(cid:12)(cid:13)(cid:8)(cid:14)(cid:15)(cid:16)(cid:2)(cid:17)(cid:17)(cid:18)(cid:13) (cid:19)(cid:20)(cid:6)(cid:5)(cid:4)(cid:5) (cid:13)(cid:14)(cid:17)(cid:18) (cid:21)(cid:19)(cid:14)(cid:7)(cid:18)(cid:19)(cid:22)(cid:19)(cid:18)(cid:15)(cid:18)(cid:14)(cid:7)(cid:18)(cid:19) (cid:23)(cid:14)(cid:8)(cid:16) ±(cid:24)(cid:10)(cid:6)(cid:25)(cid:7) (cid:18)(cid:20)(cid:21) (cid:26)(cid:19)(cid:9)(cid:8)(cid:18)(cid:15)(cid:8)(cid:14)(cid:9)(cid:17) SLLS409K − JANUARY 2000 − REVISED MARCH 2004 recommended operating conditions (see Note 4 and Figure 6) MIN NOM MAX UNIT VCC = 3.3 V 3 3.3 3.6 SSuuppppllyy vvoollttaaggee VV VCC = 5 V 4.5 5 5.5 DDIINN,, EENN,, FFOORRCCEEOOFFFF,, VCC = 3.3 V 2 VVIIHH DDrriivveerr aanndd ccoonnttrrooll hhiigghh--lleevveell iinnppuutt vvoollttaaggee VV FORCEON VCC = 5 V 2.4 VIL Driver and control low-level input voltage DIN, EN, FORCEOFF, FORCEON 0.8 V Driver and control input voltage DIN, EN, FORCEOFF, FORCEON 0 5.5 VVII VV Receiver input voltage −25 25 MAX3223C 0 70 TTAA OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree °°CC MAX3223I −40 85 NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 6) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Input leakage EN, FORCEOFF, II current FORCEON ±0.01 ±1 µA No load, Auto-powerdown FORCEOFF and 0.3 1 mA disabled FORCEON at VCC IICCCC SSuuppppllyy ccuurrrreenntt Powered off VVTTAACC CC== 22==55 33°°..CC33 VV oorr 55 VV,, No load, FORCEOFF at GND 1 10 Auto-powerdown No load, FORCEOFF at VCC, µA FORCEON at GND, 1 10 enabled All RIN are open or grounded †All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:27) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:4) (cid:4)(cid:6)(cid:7) (cid:8)(cid:9) (cid:10)(cid:11)(cid:10)(cid:6)(cid:7) (cid:1)(cid:12)(cid:13)(cid:8)(cid:14)(cid:15)(cid:16)(cid:2)(cid:17)(cid:17)(cid:18)(cid:13) (cid:19)(cid:20)(cid:6)(cid:5)(cid:4)(cid:5) (cid:13)(cid:14)(cid:17)(cid:18) (cid:21)(cid:19)(cid:14)(cid:7)(cid:18)(cid:19)(cid:22)(cid:19)(cid:18)(cid:15)(cid:18)(cid:14)(cid:7)(cid:18)(cid:19) (cid:23)(cid:14)(cid:8)(cid:16) ±(cid:24)(cid:10)(cid:6)(cid:25)(cid:7) (cid:18)(cid:20)(cid:21) (cid:26)(cid:19)(cid:9)(cid:8)(cid:18)(cid:15)(cid:8)(cid:14)(cid:9)(cid:17) SLLS409K − JANUARY 2000 − REVISED MARCH 2004 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 6) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage DOUT at RL = 3 kΩ to GND 5 5.4 V VOL Low-level output voltage DOUT at RL = 3 kΩ to GND −5 −5.4 V IIH High-level input current VI = VCC ±0.01 ±1 µA IIL Low-level input current VI at GND ±0.01 ±1 µA VCC = 3.6 V, VO = 0 V ±35 ±60 IIOOSS SShhoorrtt--cciirrccuuiitt oouuttppuutt ccuurrrreenntt‡‡ VCC = 5.5 V, VO = 0 V ±35 ±60 mmAA ro Output resistance VCC, V+, and V− = 0 V, VO = ±2 V 300 10M Ω VO = ±12 V, VCC = 3 V to 3.6 V ±25 IIooffff OOuuttppuutt lleeaakkaaggee ccuurrrreenntt FFOORRCCEEOOFFFF == GGNNDD VO = ±10 V, VCC = 4.5 V to 5.5 V ±25 µµAA †All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. ‡Short-circuit durations should be controlled to prevent exceeding the device absolute power-dissipation ratings, and not more than one output should be shorted at a time. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 6) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT CL = 1000 pF, RL = 3 kΩ, Maximum data rate 250 kbit/s One DOUT switching, See Figure 1 tsk(p) Pulse skew§ CSeLe = F 1ig5u0r ep F2 to 2500 pF, RL = 3 kΩ to 7 kΩ, 100 ns SSRR((ttrr)) SSlleeww rraattee,, ttrraannssiittiioonn rreeggiioonn VVCCCC == 33..33 VV,, CL = 150 pF to 1000 pF 6 30 VV//µµss (See Figure 1) RL = 3 kΩ to 7 kΩ CL = 150 pF to 2500 pF 4 30 †All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. §Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:4) (cid:27) (cid:4)(cid:6)(cid:7) (cid:8)(cid:9) (cid:10)(cid:11)(cid:10)(cid:6)(cid:7) (cid:1)(cid:12)(cid:13)(cid:8)(cid:14)(cid:15)(cid:16)(cid:2)(cid:17)(cid:17)(cid:18)(cid:13) (cid:19)(cid:20)(cid:6)(cid:5)(cid:4)(cid:5) (cid:13)(cid:14)(cid:17)(cid:18) (cid:21)(cid:19)(cid:14)(cid:7)(cid:18)(cid:19)(cid:22)(cid:19)(cid:18)(cid:15)(cid:18)(cid:14)(cid:7)(cid:18)(cid:19) (cid:23)(cid:14)(cid:8)(cid:16) ±(cid:24)(cid:10)(cid:6)(cid:25)(cid:7) (cid:18)(cid:20)(cid:21) (cid:26)(cid:19)(cid:9)(cid:8)(cid:18)(cid:15)(cid:8)(cid:14)(cid:9)(cid:17) SLLS409K − JANUARY 2000 − REVISED MARCH 2004 RECEIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 6) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage IOH = −1 mA VCC−0.6 VCC−0.1 V VOL Low-level output voltage IOL = 1.6 mA 0.4 V VCC = 3.3 V 1.6 2.4 VVIITT++ PPoossiittiivvee--ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee VV VCC = 5 V 1.9 2.4 VCC = 3.3 V 0.6 1.1 VVIITT−− NNeeggaattiivvee--ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee VV VCC = 5 V 0.8 1.4 Vhys Input hysteresis (VIT+ − VIT−) 0.5 V Ioff Output leakage current EN = VCC ±0.05 ±10 µA ri Input resistance VI = ±3 V to ±25 V 3 5 7 kΩ †All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH Propagation delay time, low- to high-level output CL= 150 pF, See Figure 3 150 ns tPHL Propagation delay time, high- to low-level output CL= 150 pF, See Figure 3 150 ns CL= 150 pF, RL = 3 kΩ, ten Output enable time See Figure 4 200 ns CL= 150 pF, RL = 3 kΩ, tdis Output disable time See Figure 4 200 ns tsk(p) Pulse skew‡ See Figure 3 50 ns †All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. ‡Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ±0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ±0.5 V. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:27) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:4) (cid:4)(cid:6)(cid:7) (cid:8)(cid:9) (cid:10)(cid:11)(cid:10)(cid:6)(cid:7) (cid:1)(cid:12)(cid:13)(cid:8)(cid:14)(cid:15)(cid:16)(cid:2)(cid:17)(cid:17)(cid:18)(cid:13) (cid:19)(cid:20)(cid:6)(cid:5)(cid:4)(cid:5) (cid:13)(cid:14)(cid:17)(cid:18) (cid:21)(cid:19)(cid:14)(cid:7)(cid:18)(cid:19)(cid:22)(cid:19)(cid:18)(cid:15)(cid:18)(cid:14)(cid:7)(cid:18)(cid:19) (cid:23)(cid:14)(cid:8)(cid:16) ±(cid:24)(cid:10)(cid:6)(cid:25)(cid:7) (cid:18)(cid:20)(cid:21) (cid:26)(cid:19)(cid:9)(cid:8)(cid:18)(cid:15)(cid:8)(cid:14)(cid:9)(cid:17) SLLS409K − JANUARY 2000 − REVISED MARCH 2004 AUTO-POWERDOWN SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5) PARAMETER TEST CONDITIONS MIN MAX UNIT Receiver input threshold for VT+(valid) INVALID high-level output voltage FORCEON = GND, FORCEOFF = VCC 2.7 V Receiver input threshold for VT−(valid) INVALID high-level output voltage FORCEON = GND, FORCEOFF = VCC −2.7 V Receiver input threshold for VT(invalid) INVALID low-level output voltage FORCEON = GND, FORCEOFF = VCC −0.3 0.3 V IOH = −1 mA, FORCEON = GND, VOH INVALID high-level output voltage FORCEOFF = VCC VCC−0.6 V IOL = 1.6 mA, FORCEON = GND, VOL INVALID low-level output voltage FORCEOFF = VCC 0.4 V switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5) PARAMETER TYP† UNIT tvalid Propagation delay time, low- to high-level output 1 µs tinvalid Propagation delay time, high- to low-level output 30 µs ten Supply enable time 100 µs †All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. PARAMETER MEASUREMENT INFORMATION 3 V Input 1.5 V 1.5 V RS-232 0 V Output Generator (see Note B) 50 Ω CL tTHL tTLH RL (see Note A) VOH 3 V 3 V 3 V Output FORCEOFF −3 V −3 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS SR(tr)(cid:1) 6V t ort THL TLH NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 1. Driver Slew Rate POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:4) (cid:27) (cid:4)(cid:6)(cid:7) (cid:8)(cid:9) (cid:10)(cid:11)(cid:10)(cid:6)(cid:7) (cid:1)(cid:12)(cid:13)(cid:8)(cid:14)(cid:15)(cid:16)(cid:2)(cid:17)(cid:17)(cid:18)(cid:13) (cid:19)(cid:20)(cid:6)(cid:5)(cid:4)(cid:5) (cid:13)(cid:14)(cid:17)(cid:18) (cid:21)(cid:19)(cid:14)(cid:7)(cid:18)(cid:19)(cid:22)(cid:19)(cid:18)(cid:15)(cid:18)(cid:14)(cid:7)(cid:18)(cid:19) (cid:23)(cid:14)(cid:8)(cid:16) ±(cid:24)(cid:10)(cid:6)(cid:25)(cid:7) (cid:18)(cid:20)(cid:21) (cid:26)(cid:19)(cid:9)(cid:8)(cid:18)(cid:15)(cid:8)(cid:14)(cid:9)(cid:17) SLLS409K − JANUARY 2000 − REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION 3 V Input 1.5 V 1.5 V RS-232 0 V Output Generator 50 Ω (see Note B) CL tPHL tPLH RL (see Note A) VOH 3 V Output 50% 50% FORCEOFF VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤10 ns, tf ≤ 10 ns. Figure 2. Driver Pulse Skew EN 3 V 0 V Input 1.5 V 1.5 V −3 V Output Generator 50 Ω (see Note B) CL tPHL tPLH (see Note A) VOH 0 V Output 50% 50% FORCEOFF VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 3. Receiver Propagation Delay Times 3 V VCC GND Input 1.5V 1.5V FORCEON S1 0 V 3 V or 0 V tPHZ tPHZ RL (S1 at GND) (S1 at GND) 3 V or 0 V Output VOH Output 50% CL EN (see Note A) 0.3 V tPLZ (S1 at VCC) Generator 0.3 V 50 Ω (see Note B) Output 50% VOL tPZL (S1 at VCC) TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 4. Receiver Enable and Disable Times 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:27) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:4) (cid:4)(cid:6)(cid:7) (cid:8)(cid:9) (cid:10)(cid:11)(cid:10)(cid:6)(cid:7) (cid:1)(cid:12)(cid:13)(cid:8)(cid:14)(cid:15)(cid:16)(cid:2)(cid:17)(cid:17)(cid:18)(cid:13) (cid:19)(cid:20)(cid:6)(cid:5)(cid:4)(cid:5) (cid:13)(cid:14)(cid:17)(cid:18) (cid:21)(cid:19)(cid:14)(cid:7)(cid:18)(cid:19)(cid:22)(cid:19)(cid:18)(cid:15)(cid:18)(cid:14)(cid:7)(cid:18)(cid:19) (cid:23)(cid:14)(cid:8)(cid:16) ±(cid:24)(cid:10)(cid:6)(cid:25)(cid:7) (cid:18)(cid:20)(cid:21) (cid:26)(cid:19)(cid:9)(cid:8)(cid:18)(cid:15)(cid:8)(cid:14)(cid:9)(cid:17) SLLS409K − JANUARY 2000 − REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION 3 V 2.7 V 2.7 V Receiver 0 V Input 0 V ROUT −2.7 V −2.7 V −3 V Generator 50 Ω (see Note B) tinvalid tvalid VCC INVALID 50% VCC 50% VCC Output 0 V Auto- ten INVALID powerdown CL = 30 pF V+ ≈V+ (see Note A) 0.3 V Supply VCC FORCEOFF Voltages 0 V 0.3 V DIN DOUT FORCEON V− ≈V− TEST CIRCUIT VOLTAGE WAVEFORMS Valid RS-232 Level, INVALID High 2.7 V ÎÎÎÎÎÎÎÎÎÎÎÎ Indeterminate ÎÎÎÎÎÎÎÎÎÎÎÎ 0.3 V If Signal Remains Within This Region 0 VÎÎfor MÎoreÎ ThÎan 3Î0 µsÎ, INVÎALIÎD Is ÎLowΆ Î −0.3 V ÎÎÎÎÎÎÎÎÎÎÎÎ Indeterminate ÎÎÎÎÎÎÎÎÎÎÎÎ −2.7 V Valid RS-232 Level, INVALID High †Auto-powerdown disables drivers and reduces supply current to 1 µA. NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 5 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 5. INVALID Propagation Delay Times and Supply Enabling Time POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5)(cid:4) (cid:27) (cid:4)(cid:6)(cid:7) (cid:8)(cid:9) (cid:10)(cid:11)(cid:10)(cid:6)(cid:7) (cid:1)(cid:12)(cid:13)(cid:8)(cid:14)(cid:15)(cid:16)(cid:2)(cid:17)(cid:17)(cid:18)(cid:13) (cid:19)(cid:20)(cid:6)(cid:5)(cid:4)(cid:5) (cid:13)(cid:14)(cid:17)(cid:18) (cid:21)(cid:19)(cid:14)(cid:7)(cid:18)(cid:19)(cid:22)(cid:19)(cid:18)(cid:15)(cid:18)(cid:14)(cid:7)(cid:18)(cid:19) (cid:23)(cid:14)(cid:8)(cid:16) ±(cid:24)(cid:10)(cid:6)(cid:25)(cid:7) (cid:18)(cid:20)(cid:21) (cid:26)(cid:19)(cid:9)(cid:8)(cid:18)(cid:15)(cid:8)(cid:14)(cid:9)(cid:17) SLLS409K − JANUARY 2000 − REVISED MARCH 2004 APPLICATION INFORMATION 1 Auto- 20 EN FORCEOFF powerdown 2 19 C1+ VCC + CBYPASS − = 0.1µF + 3 18 C1 + V+ GND − C3† − 4 17 C1− DOUT1 5 16 C2+ RIN1 + C2 − 6 15 C2− ROUT1 5 kΩ 7 14 V− FORCEON − C4 + 8 13 DOUT2 DIN1 9 12 RIN2 DIN2 10 11 ROUT2 INVALID 5 kΩ †C3 can be connected to VCC or GND. NOTES: A. Resistor values shown are nominal. B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be connected as shown. VCC vs CAPACITOR VALUES VCC C1 C2, C3, C4 3.3 V ± 0.3 V 0.1 µF 0.1 µF 5 V ± 0.5 V 0.047 µF 0.33 µF 3 V to 5.5 V 0.1 µF 0.47 µF Figure 6. Typical Operating Circuit and Capacitor Values 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MAX3223CDB ACTIVE SSOP DB 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 MA3223C & no Sb/Br) MAX3223CDBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 MA3223C & no Sb/Br) MAX3223CDW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3223C & no Sb/Br) MAX3223CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3223C & no Sb/Br) MAX3223CDWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3223C & no Sb/Br) MAX3223CPW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 MA3223C & no Sb/Br) MAX3223CPWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 MA3223C & no Sb/Br) MAX3223IDB ACTIVE SSOP DB 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MB3223I & no Sb/Br) MAX3223IDBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MB3223I & no Sb/Br) MAX3223IDW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3223I & no Sb/Br) MAX3223IDWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3223I & no Sb/Br) MAX3223IPW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MB3223I & no Sb/Br) MAX3223IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MB3223I & no Sb/Br) MAX3223IPWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MB3223I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF MAX3223 : •Enhanced Product: MAX3223-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MAX3223CDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 MAX3223CDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 MAX3223CPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 MAX3223IDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 MAX3223IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 MAX3223IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MAX3223CDBR SSOP DB 20 2000 367.0 367.0 38.0 MAX3223CDWR SOIC DW 20 2000 367.0 367.0 45.0 MAX3223CPWR TSSOP PW 20 2000 367.0 367.0 38.0 MAX3223IDBR SSOP DB 20 2000 367.0 367.0 38.0 MAX3223IDWR SOIC DW 20 2000 367.0 367.0 45.0 MAX3223IPWR TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2

PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated