(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 (cid:1) RS-232 Bus-Pin ESD Protection Exceeds DB OR DW PACKAGE ±15 kV Using Human-Body Model (HBM) (TOP VIEW) (cid:1) Meets or Exceeds the Requirements of DOUT3 1 28 DOUT4 TIA/EIA-232-F and ITU v.28 Standards DOUT1 2 27 RIN3 (cid:1) Operates at 5-V VCC Supply DOUT2 3 26 ROUT3 (cid:1) Four Drivers and Five Receivers RIN2 4 25 SHDN (cid:1) Operates Up To 120 kbit/s ROUT2 5 24 EN (cid:1) DIN2 6 23 RIN4 Low Supply Current in Shutdown Mode...1 µA Typical DIN1 7 22 ROUT4 ROUT1 8 21 DIN4 (cid:1) External Capacitors...4 × 0.1 µF RIN1 9 20 DIN3 (cid:1) Latch-Up Performance Exceeds 100 mA Per GND 10 19 ROUT5 JESD 78, Class II V 11 18 RIN5 CC (cid:1) Applications C1+ 12 17 V− − Battery-Powered Systems, PDAs, V+ 13 16 C2− Notebooks, Laptops, Palmtop PCs, and C1− 14 15 C2+ Hand-Held Equipment description/ordering information The MAX211 device consists of four line drivers, five line receivers, and a dual charge-pump circuit with ±15-kV ESD protection pin to pin (serial-port connection pins, including GND). The device meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 5-V supply. The devices operate at data signaling rates up to 120 kbit/s and a maximum of 30-V/µs driver output slew rate. The MAX211 has both shutdown (SHDN) and enable control (EN). In shutdown mode, the charge pumps are turned off, V+ is pulled down to VCC, V− is pulled to GND, and the transmitter outputs are disabled. This reduces supply current typically to 1 µA. EN is used to put the receiver outputs into the high-impedance state to allow wired-OR connection of two RS-232 ports. It has no effect on the RS-232 drivers or the charge pumps. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube of 20 MAX211CDW SSOOIICC ((DDWW)) MMAAXX221111CC Reel of 1000 MAX211CDWR 00°°CC ttoo 7700°°CC Tube of 50 MAX211CDB SSSSOOPP ((DDBB)) MMAAXX221111CC Reel of 2000 MAX211CDBR Tube of 20 MAX211IDW SSOOIICC ((DDWW)) MMAAXX221111II Reel of 1000 MAX211IDWR −−4400°°CC ttoo 8855°°CC Tube of 50 MAX211IDB SSSSOOPP ((DDBB)) MMAAXX221111II Reel of 2000 MAX211IDBR †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:24)(cid:17)(cid:25)(cid:20)(cid:9)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) (cid:20)(cid:2)(cid:11)(cid:2) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ Copyright  2004, Texas Instruments Incorporated (cid:24)(cid:30)(cid:29)*%$"# $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:11)&-!# (cid:12)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:24)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 Function Tables INPUTS DDRRIIVVEERR RREECCEEIIVVEERR DDEEVVIICCEE SSTTAATTUUSS SHDN EN L L All active All active Normal operation L H All active Z Normal operation H X Z Z Shutdown X = don’t care, Z = high impedance EACH DRIVER INPUTS OOUUTTPPUUTT DDRRIIVVEERR SSTTAATTUUSS DIN SHDN DOUT L L H NNoorrmmaall ooppeerraattiioonn H L L X H Z Powered off X = don’t care, Z = high impedance EACH RECEIVER INPUTS OOUUTTPPUUTT RREECCEEIIVVEERR SSTTAATTUUSS RIN EN ROUT L L H NNoorrmmaall ooppeerraattiioonn H L L X H Z Powered off X = don’t care, Z = high impedance 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 logic diagram (positive logic) 7 2 DIN1 DOUT1 6 3 DIN2 DOUT2 TTL/CMOS RS-232 Inputs 20 1 Outputs DIN3 DOUT3 21 28 DIN4 DOUT4 25 SHDN 8 9 ROUT1 RIN1 5 4 ROUT2 RIN2 26 27 RS-232 ROUT3 RIN3 TTL/CMOS Inputs Outputs 22 23 ROUT4 RIN4 19 18 ROUT5 RIN5 24 EN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V CC Positive charge pump voltage range, V+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC − 0.3 V to 14 V Negative charge pump voltage range, V− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to −14 V Input voltage range, V: Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V+ + 0.3 V I Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V Output voltage range, VO: Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V− − 0.3 V to V+ + 0.3 V Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V CC Short-circuit duration: DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Package thermal impedance, θ (see Notes 2 and 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W JA DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to network GND. θ 2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4 and Figure 4) MIN NOM MAX UNIT Supply voltage 4.5 5 5.5 V Driver high-level input voltage DIN 2 VVIIHH VV Control high-level input voltage EN, SHDN 2.4 VIL Driver and control low-level input voltage DIN, EN, SHDN 0.8 V Driver and control input voltage DIN, EN, SHDN 0 5.5 VVII VV Receiver input voltage −30 30 MAX211C 0 70 TTAA OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree °°CC MAX211I −40 85 NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ±0.5 V. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4) PARAMETER TEST CONDITIONS MIN TYP‡ MAX UNIT ICC Supply current No load, See Figure 6 14 20 mA Shutdown supply current TA = 25°C, See Figure 1 1 10 µA ‡All typical values are at VCC = 5 V, and TA = 25°C. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ±0.5 V. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 4) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage DOUT at RL = 3 kΩ to GND 5 9 V VOL Low-level output voltage DOUT at RL = 3 kΩ to GND −5 −9 V Driver high-level input current DIN = VCC 15 200 IIIIHH µAA Control high-level input current EN, SHDN = VCC 3 10 Driver low-level input current DIN = 0 V −15 −200 IIIILL µAA Control low-level input current EN, SHDN = 0 V −3 −10 IOS‡ Short-circuit output current VCC = 5.5 V, VO = 0 V ±10 ±60 mA ro Output resistance VCC, V+, and V− = 0 V, VO = ±2 V 300 (cid:1) †All typical values are at VCC = 5 V, and TA = 25°C. ‡Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one output should be shorted at a time. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ±0.5 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT CL = 50 pF to 1000 pF, RL = 3 kΩ to 7 kΩ, Maximum data rate 120 kbit/s One DOUT switching, See Figure 2 tPLH (D) Plorwo-p taog haitgiohn- ledveelal yo utimtpeu,t CAlLl d=r i2v5e0rs0 lopaF,ded, RSeLe = F 3ig kuΩre, 2 2 µs tPHL (D) Phirgohp-a tgoa ltoiown- ledveelal yo utimtpeu,t CAlLl d=r i2v5e0rs0 lopaF,ded, RSeLe = F 3ig kuΩre, 2 2 µs tsk(p) Pulse skew§ CL = 150 pF to 2500 pF, RSeLe = F 3ig kuΩre t o3 7 kΩ, 300 ns SR(tr) Slew rate, transition region CL = 50 pF to 1000 pF, RL = 3 kΩ to 7 kΩ, 3 6 30 V/µs (see Figure 2) VCC = 5 V †All typical values are at VCC = 5 V, and TA = 25°C. §Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ±0.5 V. ESD protection PIN TEST CONDITIONS TYP UNIT DOUT, RIN Human-Body Model ±15 kV POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 RECEIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 6) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage IOH = −1 mA 3.5 VCC−0.4 V V VOL Low-level output voltage IOL = 1.6 mA 0.4 V VIT+ Positive-going input threshold voltage VCC = 5 V, TA = 25°C 1.7 2.4 V VIT− Negative-going input threshold voltage VCC = 5 V, TA = 25°C 0.8 1.2 V Vhys Input hysteresis (VIT+ − VIT−) 0.2 0.5 1 V ri Input resistance VCC = 5 V, TA = 25°C 3 5 7 k(cid:1) Output leakage current EN = VCC, 0 ≤ROUT ≤VCC ±0.05 ±10 µA †All typical values are at VCC = 5 V, and TA = 25°C. NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ±0.5 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH (R) Propagation delay time, low- to high-level output CL= 150 pF, See Figure 4 0.5 10 µs tPHL (R) Propagation delay time, high- to low-level output CL= 150 pF, See Figure 4 0.5 10 µs CL= 150 pF, RL = 1 kΩ, ten Output enable time See Figure 5 600 ns CL= 150 pF, RL = 1 kΩ, tdis Output disable time See Figure 5 200 ns tsk(p) Pulse skew‡ See Figure 3 300 ns †All typical values are at VCC = 5 V, and TA = 25°C. ‡Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. NOTE 4: Test conditions are C1−C4 = 0.1 µF, at VCC = 5 V ±0.5 V. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION ISHDN 0.1 µF − + 5.5 V + 0.1 µF − VCC C1+ V+ + 0.1 µF 0.1 µF − − + V− C1− C2+ + 0.1 µF − C2− VCC 400 kΩ DIN DOUT 5.5 V 3 kΩ D1 to D4 RIN ROUT +5.5 V 0-V or 5.5-V Drive EN 5 kΩ R1 to R5 5.5 V SHDN GND Figure 1. Shutdown Current Test Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION 0 V SHDN 3 V Input 1.5 V 1.5 V RS-232 0 V Output Generator (see Note B) 50 Ω CL tPHL (D) tPLH (D) RL (see Note A) VOH 3 V 3 V Output −3 V −3 V VOL TEST CIRCUIT SR(tr)(cid:1) 6V VOLTAGE WAVEFORMS t ort PHL(D) PLH(D) NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤10 ns, tf ≤ 10 ns. Figure 2. Driver Slew Rate and Propagation Delay Times 0 V SHDN 3 V RS-232 Input 1.5 V 1.5 V Generator Output 0 V (see Note B) 50 Ω CL tPHL (D) tPLH (D) RL (see Note A) VOH Output 50% 50% VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 3. Driver Pulse Skew 0 V SHDN 3 V Input 1.5 V 1.5 V Output −3 V Generator (see Note B) 50 Ω CL tPHL (R) tPLH (R) (see Note A) 0 V VOH EN Output 50% 50% VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 4. Receiver Propagation Delay Times 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION 3 V VCC GND 1.5 V 1.5 V 0 V Input 0 V S1 SHDN tPHZ tPZH RL (S1 at GND) (S1 at GND) 3 V or 0 V Output Output VOH VOH − 0.1 V 3.5 V CL EN (see Note A) tPLZ tPZL Generator (S1 at VCC) (S1 at VCC) 50 Ω (see Note B) VOL + 0.1 V 0.8 V Output VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. C. tPLZ and tPHZ are the same as tdis. D. tPZL and tPZH are the same as ten. Figure 5. Receiver Enable and Disable Times POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 APPLICATION INFORMATION 1 28 DOUT3 DOUT4 2 27 DOUT1 RIN3 DOUT2 3 5 kΩ 4 RIN2 26 ROUT3 5 kΩ 25 SHDN 24 ROUT2 5 EN 23 RIN4 5 V 5 kΩ 400 kΩ 6 22 DIN2 ROUT4 5 V 5 V 400 kΩ 7 DIN1 400 kΩ 21 ROUT1 8 DIN4 9 5 V RIN1 GND 10 5 kΩ 400 kΩ 20 − CBYPASS DIN3 + = 0.1µF 11 19 VCC VCC ROUT5 − C3†= 18 0.1 µF + 12 RIN5 6.3 V C1+ 5 kΩ C4 = 13 0.1 µF V+ 16 V 17 V− C1 = + − + 0.1 µF − 14 6.3 V C1− 16 C2− − C2 = 0.1 µF + 16 V 15 C2+ †C3 can be connected to VCC or GND. NOTES: A. Resistor values shown are nominal. B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be connected as shown. Figure 6. Typical Operating Circuit and Capacitor Values 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 APPLICATION INFORMATION capacitor selection The capacitor type used for C1−C4 is not critical for proper operation. The MAX211 requires 0.1-µF capacitors, although capacitors up to 10 µF can be used without harm. Ceramic dielectrics are suggested for the 0.1-µF capacitors. When using the minimum recommended capacitor values, make sure the capacitance value does not degrade excessively as the operating temperature varies. If in doubt, use capacitors with a larger (e.g., 2×) nominal value. The capacitors’ effective series resistance (ESR), which usually rises at low temperatures, influences the amount of ripple on V+ and V−. Use larger capacitors (up to 10 µF) to reduce the output impedance at V+ and V−. Bypass V to ground with at least 0.1 µF. In applications sensitive to power-supply noise generated by the CC charge pumps, decouple V to ground with a capacitor the same size as (or larger than) the charge-pump CC capacitors (C1−C4). electrostatic discharge (ESD) protection Texas Instruments MAX211 devices have standard ESD protection structures incorporated on the pins to protect against electrostatic discharges encountered during assembly and handling. In addition, the RS232 bus pins (driver outputs and receiver inputs) of these devices have an extra level of ESD protection. Advanced ESD structures were designed to successfully protect these bus pins against ESD discharge of ±15 kV when powered down. ESD test conditions ESD testing is stringently performed by TI, based on various conditions and procedures. Please contact TI for a reliability report that documents test setup, methodology, and results. Human-Body Model The Human-Body Model (HBM) of ESD testing is shown in Figure 7. Figure 8 shows the current waveform that is generated during a discharge into a low impedance. The model consists of a 100-pF capacitor charged to the ESD voltage of concern and subsequently discharged into the DUT through a 1.5-kΩ resistor. RD 1.5 kΩ + VHBM − CS 100 pF DUT Figure 7. HBM ESD Test Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:5) (cid:6)(cid:7)(cid:8) (cid:1)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:2)(cid:15)(cid:15)(cid:16)(cid:10) (cid:17)(cid:18)(cid:7)(cid:4)(cid:19)(cid:4) (cid:10)(cid:12)(cid:15)(cid:16) (cid:20)(cid:17)(cid:12)(cid:8)(cid:16)(cid:17)(cid:21)(cid:17)(cid:16)(cid:13)(cid:16)(cid:12)(cid:8)(cid:16)(cid:17) (cid:22)(cid:12)(cid:11)(cid:14) ±(cid:5)(cid:6)(cid:7)(cid:23)(cid:8) (cid:16)(cid:18)(cid:20) (cid:24)(cid:17)(cid:25)(cid:11)(cid:16)(cid:13)(cid:11)(cid:12)(cid:25)(cid:15) SLLS567E − MAY 2003 − REVISED JANUARY 2004 APPLICATION INFORMATION 1.5 VHBM = 2 kV DUT = 10 V, 1-Ω Zener Diode 1.0 A − T U D I 0.5 0.0 0 50 100 150 200 Time − ns Figure 8. Typical HBM Current Waveform Machine Model The Machine Model (MM) ESD test applies to all pins, using a 200-pF capacitor with no discharge resistance. The purpose of the MM test is to simulate possible ESD conditions that can occur during the handling and assembly processes of manufacturing. In this case, ESD protection is required for all pins, not just RS-232 pins. However, after PC board assembly, the MM test no longer is as pertinent to the RS-232 pins. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MAX211CDB ACTIVE SSOP DB 28 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 MAX211C & no Sb/Br) MAX211CDBR ACTIVE SSOP DB 28 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 MAX211C & no Sb/Br) MAX211CDW ACTIVE SOIC DW 28 20 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 MAX211C & no Sb/Br) MAX211CDWR ACTIVE SOIC DW 28 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 MAX211C & no Sb/Br) MAX211IDB ACTIVE SSOP DB 28 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MAX211I & no Sb/Br) MAX211IDBG4 ACTIVE SSOP DB 28 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MAX211I & no Sb/Br) MAX211IDBR ACTIVE SSOP DB 28 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MAX211I & no Sb/Br) MAX211IDBRE4 ACTIVE SSOP DB 28 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MAX211I & no Sb/Br) MAX211IDBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MAX211I & no Sb/Br) MAX211IDW ACTIVE SOIC DW 28 20 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MAX211I & no Sb/Br) MAX211IDWR ACTIVE SOIC DW 28 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 MAX211I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MAX211CDBR SSOP DB 28 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 MAX211CDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 MAX211IDBR SSOP DB 28 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 MAX211IDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MAX211CDBR SSOP DB 28 2000 367.0 367.0 38.0 MAX211CDWR SOIC DW 28 1000 350.0 350.0 66.0 MAX211IDBR SSOP DB 28 2000 367.0 367.0 38.0 MAX211IDWR SOIC DW 28 1000 350.0 350.0 66.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0028A SSOP - 2 mm max height SCALE 1.500 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 26X 0.65 28 1 2X 10.5 8.45 9.9 NOTE 3 14 15 0.38 28X 0.22 5.6 0.15 C A B B 5.0 NOTE 4 2 MAX 0.25 (0.15) TYP SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214853/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0028A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 28X (1.85) SYMM (R0.05) TYP 1 28X (0.45) 28 26X (0.65) SYMM 14 15 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214853/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0028A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 28X (1.85) SYMM (R0.05) TYP 1 28X (0.45) 28 26X (0.65) SYMM 14 15 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214853/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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