M48Z02 M48Z12 ® 5 V, 16 Kbit (2 Kb x 8) ZEROPOWER SRAM Features ■ Integrated, ultra low power SRAM and power- fail control circuit ■ Unlimited WRITE cycles ■ READ cycle time equals WRITE cycle time ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltages (V = power-fail deselect voltage): PFD – M48Z02: V = 4.75 to 5.5 V; 24 CC 4.5 V ≤ V ≤ 4.75 V 1 PFD – M48Z12: V = 4.5 to 5.5 V; CC 4.2 V ≤ V ≤ 4.5 V PFD ■ Self-contained battery in the CAPHAT™ DIP package PCDIP24 Battery CAPHAT™ ■ Pin and function compatible with JEDEC standard 2 K x 8 SRAMs ■ RoHS compliant – Lead-free second level interconnect June 2011 Doc ID 2420 Rev 9 1/22 www.st.com 1

Contents M48Z02, M48Z12 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 V noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12 CC 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 9. Power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical data . . . . . . . . . 17 Table 12. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID 2420 Rev 9 3/22

List of figures M48Z02, M48Z12 List of figures Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. READ mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. Checking the BOK flag status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Supply voltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 9. AC testing load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline. . . . . . . . . . . . . . . . . 17 Figure 12. Shipping tube dimensions for PCDIP24 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 Description 1 Description The M48Z02/12 ZEROPOWER® RAM is a 2 K x 8 non-volatile static RAM which is pin and function compatible with the DS1220. A special 24-pin, 600 mil DIP CAPHAT™ package houses the M48Z02/12 silicon with a long-life lithium button cell to form a highly integrated battery-backed memory solution. The M48Z02/12 button cell has sufficient capacity and storage life to maintain data functionality for an accumulated time period of at least 10 years in the absence of power over commercial operating temperature range. The M48Z02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Figure 1. Logic diagram VCC 11 8 A0-A10 DQ0-DQ7 W M48Z02 M48Z12 E G VSS AI01186 Table 1. Signal names A0-A10 Address inputs DQ0-DQ7 Data inputs / outputs E Chip enable G Output enable W WRITE enable V Supply voltage CC V Ground SS Doc ID 2420 Rev 9 5/22

Description M48Z02, M48Z12 Figure 2. DIP connections A7 1 24 VCC A6 2 23 A8 A5 3 22 A9 A4 4 21 W A3 5 20 G A2 6 M48Z02 19 A10 A1 7 M48Z12 18 E A0 8 17 DQ7 DQ0 9 16 DQ6 DQ1 10 15 DQ5 DQ2 11 14 DQ4 VSS 12 13 DQ3 AI01187 Figure 3. Block diagram A0-A10 LITHIUM CELL POWER 2K x 8 DQ0-DQ7 SRAM ARRAY VOLTAGE SENSE AND E SWITCHING VPFD CIRCUITRY W G VCC VSS AI01255 6/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 Operation modes 2 Operation modes The M48Z02/12 also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out of tolerance condition. When V is out of CC tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V . As V falls below CC CC approximately 3 V, the control circuitry connects the battery which maintains data operation until valid power returns. Table 2. Operating modes DQ0- Mode V E G W Power CC DQ7 Deselect V X X High Z Standby IH 4.75 to 5.5 V WRITE V X V D Active IL IL IN or READ V V V D Active 4.5 to 5.5 V IL IL IH OUT READ V V V High Z Active IL IH IH Deselect V to V (min)(1) X X X High Z CMOS standby SO PFD Deselect ≤ V (1) X X X High Z Battery backup mode SO 1. See Table10 on page16 for details. Note: X = V or V ; V = battery backup switchover voltage. IH IL SO 2.1 READ mode The M48Z02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The device architecture allows ripple-through access of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t ) after the last AVQV address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access time (t ) or output enable access time (t ). ELQV GLQV The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before t , the data lines will be driven to an indeterminate state until t . If AVQV AVQV the address inputs are changed while E and G remain active, output data will remain valid for output data hold time (t ) but will go indeterminate until the next address access. AXQX Doc ID 2420 Rev 9 7/22

Operation modes M48Z02, M48Z12 Figure 4. READ mode AC waveforms tAVAV A0-A10 VALID tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI01330 Note: WRITE enable (W) = high. Table 3. READ mode AC characteristics M48Z02/M48Z12 Symbol Parameter(1) –70 –150 –200 Unit Min Max Min Max Min Max t READ cycle time 70 150 200 ns AVAV t Address valid to output valid 70 150 200 ns AVQV t Chip enable low to output valid 70 150 200 ns ELQV t Output enable low to output valid 35 75 80 ns GLQV t Chip enable low to output transition 5 10 10 ns ELQX t Output enable low to output transition 5 5 5 ns GLQX t Chip enable high to output Hi-Z 25 35 40 ns EHQZ t Output enable high to output Hi-Z 25 35 40 ns GHQZ t Address transition to output transition 10 5 5 ns AXQX 1. Valid for ambient operating temperature: T = 0 to 70 °C or –40 to 85 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where A CC noted). 2.2 WRITE mode The M48Z02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of t from chip enable or t from WRITE enable prior EHAX WHAX to the initiation of another READ or WRITE cycle. Data-in must be valid t prior to the DVWH end of WRITE and remain valid for t afterward. G should be kept high during WRITE WHDX cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs t after W falls. WLQZ 8/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 Operation modes Figure 5. WRITE enable controlled, WRITE AC waveform tAVAV A0-A10 VALID tAVWH tAVEL tWHAX E tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA INPUT tDVWH AI01331 Figure 6. Chip enable controlled, WRITE AC waveforms tAVAV A0-A10 VALID tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI01332B Doc ID 2420 Rev 9 9/22

Operation modes M48Z02, M48Z12 Table 4. WRITE mode AC characteristics M48Z02/M48Z12 Symbol Parameter(1) –70 –150 –200 Unit Min Max Min Max Min Max t WRITE cycle time 70 150 200 ns AVAV t Address valid to WRITE enable low 0 0 0 ns AVWL t Address valid to chip enable 1 low 0 0 0 ns AVEL t WRITE enable pulse width 50 90 120 ns WLWH t Chip enable low to chip enable 1 high 55 90 120 ns ELEH t WRITE enable high to address transition 0 10 10 ns WHAX t Chip enable high to address transition 0 10 10 ns EHAX t Input valid to WRITE enable high 30 40 60 ns DVWH t Input valid to chip enable high 30 40 60 ns DVEH t WRITE enable high to input transition 5 5 5 ns WHDX t Chip enable high to input transition 5 5 5 ns EHDX t WRITE enable low to output Hi-Z 25 50 60 ns WLQZ t Address valid to WRITE enable high 60 120 140 ns AVWH t Address valid to chip enable high 60 120 140 ns AVEH t WRITE enable high to output transition 5 10 10 ns WHQX 1. Valid for ambient operating temperature: T = 0 to 70 °C or –40 to 85 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where A CC noted). 2.3 Data retention mode With valid V applied, the M48Z02/12 operates as a conventional BYTEWIDE™ static CC RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V falls within the V (max), V (min) window. All outputs CC PFD PFD become high impedance, and all inputs are treated as “don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V (min), the PFD user can be assured the memory will be in a write protected state, provided the V fall time CC is not less than t . The M48Z02/12 may respond to transient noise spikes on V that reach F CC into the deselect window during the time the device is sampling V . Therefore, decoupling CC of the power supply lines is recommended. The power switching circuit connects external V to the RAM and disconnects the battery CC when V rises above V . As V rises, the battery voltage is checked. If the voltage is CC SO CC too low, an internal Battery Not OK (BOK) flag will be set. The BOK flag can be checked after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is automatically cleared after the first WRITE, and normal RAM operation resumes. Figure7 on page11 illustrates how a BOK check routine could be structured. For more information on a battery storage life refer to the application note AN1012. 10/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 Operation modes Figure 7. Checking the BOK flag status POWER-UP READ DATA AT ANY ADDRESS WRITE DATA COMPLEMENT BACK TO SAME ADDRESS READ DATA AT SAME ADDRESS AGAIN IS DATA COMPLEMENT NO (BATTERY LOW) OF FIRST READ? NOTIFY SYSTEM (BATTERY OK) YES OF LOW BATTERY (DATA MAY BE CORRUPTED) WRITE ORIGINAL DATA BACK TO SAME ADDRESS CONTINUE AI00607 Doc ID 2420 Rev 9 11/22

Operation modes M48Z02, M48Z12 2.4 V noise and negative going transients CC I transients, including those produced by output switching, can produce voltage CC fluctuations, resulting in spikes on the V bus. These transients can be reduced if CC capacitors are used to store energy which stabilizes the V bus. The energy stored in the CC bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in Figure8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V that drive it to values below V by as much as CC SS one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a Schottky diode from V to V (cathode connected to V , anode to V ). CC SS CC SS Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 8. Supply voltage protection VCC VCC 0.1µF DEVICE VSS AI02169 12/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 Maximum ratings 3 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol Parameter Value Unit T Ambient operating temperature Grade 1 0 to 70 °C A T Storage temperature (V off, oscillator off) –40 to 85 °C STG CC T (1) Lead solder temperature for 10 seconds 260 °C SLD V Input or output voltages –0.3 to 7 V IO V Supply voltage –0.3 to 7 V CC I Output current 20 mA O P Power dissipation 1 W D 1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries. Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode. Doc ID 2420 Rev 9 13/22

DC and AC parameters M48Z02, M48Z12 4 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in Table6: Operating and AC measurement conditions. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions Parameter M48Z02 M48Z12 Unit Supply voltage (V ) 4.75 to 5.5 4.5 to 5.5 V CC Ambient operating temperature (T ) Grade 1 0 to 70 0 to 70 °C A Load capacitance (C ) 100 100 pF L Input rise and fall times ≤ 5 ≤ 5 ns Input pulse voltages 0 to 3 0 to 3 V Input and output timing ref. voltages 1.5 1.5 V Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC testing load circuit 5V 1.8kΩ DEVICE UNDER OUT TEST 1kΩ CL = 100pF CL includes JIG capacitance AI01019 Table 7. Capacitance Symbol Parameter(1)(2) Min Max Unit C Input capacitance - 10 pF IN C (3) Input / output capacitance - 10 pF IO 1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested. 2. At 25°C, f = 1 MHz. 3. Outputs deselected. 14/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 DC and AC parameters Table 8. DC characteristics Symbol Parameter Test condition(1) Min Max Unit I Input leakage current 0V ≤ V ≤ V ±1 µA LI IN CC I (2) Output leakage current 0V ≤ V ≤ V ±1 µA LO OUT CC I Supply current Outputs open 80 mA CC I Supply current (standby) TTL E = V 3 mA CC1 IH I Supply current (standby) CMOS E = V – 0.2 V 3 mA CC2 CC V Input low voltage –0.3 0.8 V IL V Input high voltage 2.2 V + 0.3 V IH CC V Output low voltage I = 2.1 mA 0.4 V OL OL V Output high voltage I = –1 mA 2.4 V OH OH 1. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). A CC 2. Outputs deselected. Figure 10. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO tF tDR tR tPD tFB tRB tREC INPUTS RECOGNIZED DON'T CARE NOTE RECOGNIZED HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI00606 Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as V rises past V (min). Some systems may perform inadvertent WRITE cycles after V CC PFD CC rises above V (min) but before normal system operations begin. Even though a power on PFD reset is being applied to the processor, a reset condition may not occur until after the system is running. Doc ID 2420 Rev 9 15/22

DC and AC parameters M48Z02, M48Z12 Table 9. Power down/up AC characteristics Symbol Parameter(1) Min Max Unit t E or W at V before power down 0 - µs PD IH t (2) V (max) to V (min) V fall time 300 - µs F PFD PFD CC t (3) V (min) to V V fall time 10 - µs FB PFD SS CC t V (min) to V (max) V rise time 0 - µs R PFD PFD CC t V to V (min) V rise time 1 - µs RB SS PFD CC t E or W at V after power up 2 - ms REC IH 1. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where A CC noted). 2. V (max) to V (min) fall time of less than t may result in deselection/write protection not occurring PFD PFD F until 200 µs after V passes V (min). CC PFD 3. V (min) to V fall time of less than t may cause corruption of RAM data. PFD SS FB Table 10. Power down/up trip points DC characteristics Symbol Parameter(1)(2) Min Typ Max Unit M48Z02 4.5 4.6 4.75 V V Power-fail deselect voltage PFD M48Z12 4.2 4.3 4.5 V V Battery backup switchover voltage 3.0 V SO t (3) Expected data retention time 10 YEARS DR 1. All voltages referenced to V . SS 2. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where A CC noted). 3. At 25 °C, V = 0 V. CC 16/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 Package mechanical data 5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline A2 A A1 L C B1 B e1 eA e3 D N E 1 PCDIP Note: Drawing is not to scale. Table 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical data mm inches Symb Typ Min Max Typ Min Max A 8.89 9.65 0.350 0.380 A1 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 34.29 34.80 1.350 1.370 E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 27.94 1.1 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 24 24 Doc ID 2420 Rev 9 17/22

Package mechanical data M48Z02, M48Z12 Figure 12. Shipping tube dimensions for PCDIP24 package 1011292_E Note: All dimensions are in inches. 18/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 Part numbering 6 Part numbering Table 12. Ordering information scheme Example: M48Z 02 –70 PC 1 Device type M48Z Supply voltage and write protect voltage 02 = V = 4.75 to 5.5 V; V = 4.5 to 4.75 V CC PFD 12 = V = 4.5 to 5.5 V; V = 4.2 to 4.5 V CC PFD Speed –70 = 70 ns (M48Z02/12) –150 = 150 ns (M48Z02/12) –200 = 200 ns (M48Z02/12)(1) Package PC = PCDIP24 Temperature range 1 = 0 to 70 °C 1. Not recommended for new design. Contact local ST sales office for availability. For a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the ST sales office nearest you. Doc ID 2420 Rev 9 19/22

Environmental information M48Z02, M48Z12 7 Environmental information Figure 13. Recycling symbols This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. 20/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 Revision history 8 Revision history Table 13. Document revision history Date Revision Changes May-1999 1 First issue Reformatted; temperature information added to tables (Table5, 6, 7, 8, 09-Jul-2001 2 3, 4, 9, 10); Figure updated (Figure10) 17-Dec-2001 2.1 Remove references to “clock” in document 20-May-2002 2.2 Updated V noise and negative going transients text CC 01-Apr-2003 3 v2.2 template applied; test condition updated (Table10) 22-Apr-2003 3.1 Fix error in ordering information (Table12) Update template, Lead-free text, and remove references to ‘crystal’ and 12-Dec-2005 4 footnote (Table8, 12) Reformatted document; added lead-free second level interconnect 02-Nov-2007 5 information to cover page and Section5: Package mechanical data; updated Table5, 6, 8, 9, 10, 12. 03-Dec-2008 6 Added Section7: Environmental information; minor formatting changes. 27-May-2010 7 Updated Section3, Table11, text in Section5; reformatted document. Updated Table12: Ordering information scheme for 200 ns version of 21-Jan-2011 8 devices; updated Section7; added Figure12; minor textual updates. 07-Jun-2011 9 Updated footnote of Table5: Absolute maximum ratings. Doc ID 2420 Rev 9 21/22

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: S TMicroelectronics: M48Z02-150PC1 M48Z12-150PC1 M48Z02-70PC1 M48Z12-70PC1 M48Z02-200PC1 M48Z12-200PC1