M48T02 M48T12 ® 5.0 V, 16 Kbit (2 Kb x 8) TIMEKEEPER SRAM Features ■ Integrated, ultra low power SRAM, real-time clock, and power-fail control circuit ■ BYTEWIDE™ RAM-like clock access ■ BCD coded year, month, day, date, hours, minutes, and seconds ■ Typical clock accuracy of ±1 minute a month, at 25 °C ■ Software controlled clock calibration for high accuracy applications ■ Automatic power-fail chip deselect and WRITE protection 24 ■ WRITE protect voltages 1 (V = power-fail deselect voltage): PFD – M48T02: V = 4.75 to 5.5 V; CC 4.5 V ≤ V ≤ 4.75 V PFD – M48T12: V = 4.5 to 5.5 V; CC PCDIP24 4.2 V ≤ V ≤ 4.5 V battery/crystal PFD CAPHAT™ ■ Self-contained battery and crystal in the CAPHAT™ DIP package ■ Pin and function compatible with JEDEC standard 2 K x 8 SRAMs ■ RoHS compliant – Lead-free second level interconnect June 2011 Doc ID 2410 Rev 9 1/25 www.st.com 1

Contents M48T02, M48T12 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 V noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 16 CC 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 Doc ID 2410 Rev 9

M48T02, M48T12 List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 7. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 10. Power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 12. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mech. data . . . . . . . . . . . . . 21 Table 13. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Doc ID 2410 Rev 9 3/25

List of figures M48T02, M48T12 List of figures Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. READ mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. Checking the BOK flag status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Crystal accuracy across temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. Clock calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10. Supply voltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11. AC testing load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline. . . . . . . . . . . . . . . . . 21 Figure 14. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4/25 Doc ID 2410 Rev 9

M48T02, M48T12 Description 1 Description The M48T02/12 TIMEKEEPER® RAM is a 2 Kb x 8 non-volatile static RAM and real-time clock which is pin and functional compatible with the DS1642. A special 24-pin, 600 mil DIP CAPHAT™ package houses the M48T02/12 silicon with a quartz crystal and a long life lithium button cell to form a highly integrated battery-backed memory and real-time clock solution. The M48T02/12 button cell has sufficient capacity and storage life to maintain data and clock functionality for an accumulated time period of at least 10 years in the absence of power over the operating temperature range. The M48T02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2 Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Figure 1. Logic diagram VCC 11 8 A0-A10 DQ0-DQ7 W M48T02 M48T12 E G VSS AI01027 Table 1. Signal names A0-A10 Address inputs DQ0-DQ7 Data inputs / outputs E Chip enable G Output enable W WRITE enable V Supply voltage CC V Ground SS Doc ID 2410 Rev 9 5/25

Description M48T02, M48T12 Figure 2. DIP connections A7 1 24 VCC A6 2 23 A8 A5 3 22 A9 A4 4 21 W A3 5 20 G A2 6 M48T02 19 A10 A1 7 M48T12 18 E A0 8 17 DQ7 DQ0 9 16 DQ6 DQ1 10 15 DQ5 DQ2 11 14 DQ4 VSS 12 13 DQ3 AI01028 Figure 3. Block diagram OSCILLATOR AND 8 x 8 BiPORT CLOCK CHAIN SRAM ARRAY 32,768 Hz CRYSTAL A0-A10 POWER DQ0-DQ7 2040 x 8 SRAM ARRAY LITHIUM CELL E VPFD VOLTAGE SENSE W AND SWITCHING BOK G CIRCUITRY VCC VSS AI01329 6/25 Doc ID 2410 Rev 9

M48T02, M48T12 Operation modes 2 Operation modes As Figure3 on page6 shows, the static memory array and the quartz controlled clock oscillator of the M48T02/12 are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 7F8h-7FFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 7F8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE memory cells. The M48T02/12 includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T02/12 also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out of tolerance condition. When V is out of CC tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V . As V falls below CC CC approximately 3 V, the control circuitry connects the battery which maintains data and clock operation until valid power returns. Table 2. Operating modes Mode V E G W DQ0-DQ7 Power CC Deselect V X X High Z Standby IH 4.75 to 5.5 V WRITE V X V D Active IL IL IN or READ V V V D Active 4.5 to 5.5 V IL IL IH OUT READ V V V High Z Active IL IH IH V to Deselect SO X X X High Z CMOS standby V (min)(1) PFD Deselect ≤ V (1) X X X High Z Battery backup mode SO 1. See Table11 on page20 for details. Note: X = V or V ; V = Battery backup switchover voltage. IH IL SO 2.1 READ mode The M48T02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The device architecture allows ripple-through access of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t ) after the last AVQV address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access time (t ) or output enable access time (t ). ELQV GLQV Doc ID 2410 Rev 9 7/25

Operation modes M48T02, M48T12 The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before t , the data lines will be driven to an indeterminate state until t . If AVQV AVQV the address inputs are changed while E and G remain active, output data will remain valid for output data hold time (t ) but will go indeterminate until the next address access. AXQX Figure 4. READ mode AC waveforms tAVAV A0-A10 VALID tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI01330 Note: WRITE enable (W) = High. Table 3. READ mode AC characteristics M48T02/M48T12 Symbol Parameter(1) –70 –150 –200 Unit Min Max Min Max Min Max t READ cycle time 70 150 200 ns AVAV t Address valid to output valid 70 150 200 ns AVQV t Chip enable low to output valid 70 150 200 ns ELQV t Output enable low to output valid 35 75 80 ns GLQV t Chip enable low to output transition 5 10 10 ns ELQX t Output enable low to output transition 5 5 5 ns GLQX t Chip enable high to output Hi-Z 25 35 40 ns EHQZ t Output enable high to output Hi-Z 25 35 40 ns GHQZ t Address transition to output transition 10 5 5 ns AXQX 1. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). A CC 8/25 Doc ID 2410 Rev 9

M48T02, M48T12 Operation modes 2.2 WRITE mode The M48T02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of t from chip enable or t from WRITE enable prior EHAX WHAX to the initiation of another READ or WRITE cycle. Data-in must be valid t prior to the DVWH end of WRITE and remain valid for t afterward. G should be kept high during WRITE WHDX cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs t after W falls. WLQZ Figure 5. WRITE enable controlled, WRITE AC waveform tAVAV A0-A10 VALID tAVWH tAVEL tWHAX E tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA INPUT tDVWH AI01331 Figure 6. Chip enable controlled, WRITE AC waveforms tAVAV A0-A10 VALID tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI01332B Doc ID 2410 Rev 9 9/25

Operation modes M48T02, M48T12 Table 4. WRITE mode AC characteristics M48T02/M48T12 Symbol Parameter(1) –70 –150 –200 Unit Min Max Min Max Min Max t WRITE cycle time 70 150 200 ns AVAV t Address valid to WRITE enable low 0 0 0 ns AVWL t Address valid to chip enable low 0 0 0 ns AVEL t WRITE enable pulse width 50 90 120 ns WLWH t Chip enable low to chip enable high 55 90 120 ns ELEH t WRITE enable high to address transition 0 10 10 ns WHAX t Chip enable high to address transition 0 10 10 ns EHAX t Input valid to WRITE enable high 30 40 60 ns DVWH t Input valid to chip enable high 30 40 60 ns DVEH t WRITE enable high to input transition 5 5 5 ns WHDX t Chip enable high to input transition 5 5 5 ns EHDX t WRITE enable low to output Hi-Z 25 50 60 ns WLQZ t Address valid to WRITE enable high 60 120 140 ns AVWH t Address valid to chip enable high 60 120 140 ns AVEH t WRITE enable high to output transition 5 10 10 ns WHQX 1. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where A CC noted). 2.3 Data retention mode With valid V applied, the M48T02/12 operates as a conventional BYTEWIDE™ static CC RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V falls within the V (max), V (min) window. All outputs CC PFD PFD become high impedance, and all inputs are treated as “don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V (min), the PFD user can be assured the memory will be in a write protected state, provided the V fall time CC is not less than t . The M48T02/12 may respond to transient noise spikes on V that reach F CC into the deselect window during the time the device is sampling V . Therefore, decoupling CC of the power supply lines is recommended. The power switching circuit connects external V to the RAM and disconnects the battery CC when V rises above V . As V rises, the battery voltage is checked. If the voltage is too CC SO CC low, an internal battery not oK (BOK) flag will be set. The BOK flag can be checked after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is automatically cleared after the first WRITE, and normal RAM operation resumes. Figure7 on page11 illustrates how a BOK check routine could be structured. For more information on a battery storage life refer to the application note AN1012. 10/25 Doc ID 2410 Rev 9

M48T02, M48T12 Operation modes Figure 7. Checking the BOK flag status POWER-UP READ DATA AT ANY ADDRESS WRITE DATA COMPLEMENT BACK TO SAME ADDRESS READ DATA AT SAME ADDRESS AGAIN IS DATA COMPLEMENT NO (BATTERY LOW) OF FIRST READ? NOTIFY SYSTEM (BATTERY OK) YES OF LOW BATTERY (DATA MAY BE CORRUPTED) WRITE ORIGINAL DATA BACK TO SAME ADDRESS CONTINUE AI00607 Doc ID 2410 Rev 9 11/25

Clock operations M48T02, M48T12 3 Clock operations 3.1 Reading the clock Updates to the TIMEKEEPER® registers should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, the seventh bit in the control register. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.' 3.2 Setting the clock The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a '1,' like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (on Table5 on page13). Resetting the WRITE bit to a '0' then transfers the values of all time registers (7F9-7FF) to the actual TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits marked as '0' in Table5 on page13 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. See the application note AN923, “TIMEKEEPER® rolling into the 21st century” for information on century rollover. 12/25 Doc ID 2410 Rev 9

M48T02, M48T12 Clock operations Table 5. Register map Data Function/range Address D7 D6 D5 D4 D3 D2 D1 D0 BCD format 7FF 10 years Year Year 00-99 7FE 0 0 0 10 M Month Month 01-12 7FD 0 0 10 date Date Date 01-31 7FC 0 FT 0 0 0 Day Day 01-07 7FB 0 0 10 hours Hours Hours 00-23 7FA 0 10 minutes Minutes Minutes 00-59 7F9 ST 10 seconds Seconds Seconds 00-59 7F8 W R S Calibration Control Keys: S = SIGN bit FT = FREQUENCY TEST bit (set to '0' for normal clock operation) R = READ bit W = WRITE bit ST = STOP bit 0 = Must be set to '0' 3.3 Stopping and starting the oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T02/12 is shipped from STMicroelectronics with the STOP bit set to a '1.' When reset to a '0,' the M48T02/12 oscillator starts within one second. 3.4 Calibrating the clock The M48T02/12 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. A typical M48T02/12 is accurate within 1 minute per month at 25°C without calibration. The devices are tested not to exceed ± 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. The oscillation rate of any crystal changes with temperature. Figure8 on page15 shows the frequency error that can be expected at various temperatures. Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The M48T02/12 design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure9 on page15. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration byte occupies the five lower order bits in the control register. This byte can be set to represent any value between 0 and 31 in binary form. The sixth bit is the sign bit; Doc ID 2410 Rev 9 13/25

Clock operations M48T02, M48T12 '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T02/12 may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the Frequency Test (FT) bit, the seventh-most significant bit in the day register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB (DQ0) of the seconds register will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring –10 (WR001010) to be loaded into the calibration byte for correction. Note: Setting or changing the calibration byte does not affect the frequency test output frequency. The device must be selected and addresses must be stable at address 7F9 when reading the 512 Hz on DQ0. The FT bit must be set using the same method used to set the clock: using the WRITE bit. The LSB of the seconds register is monitored by holding the M48T02/12 in an extended READ of the seconds register, but without having the READ bit set. The FT bit MUST be reset to '0' for normal clock operations to resume. Note: It is not necessary to set the WRITE bit when setting or resetting the frequency test bit (FT) or the stop bit (ST). For more information on calibration, see the application note AN924, “TIMEKEEPER® calibration.” 14/25 Doc ID 2410 Rev 9

M48T02, M48T12 Clock operations Figure 8. Crystal accuracy across temperature ppm 20 0 -20 -40 ΔF = -0.038 ppm(T - T)2 ± 10% F C2 0 -60 T = 25 °C 0 -80 -100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 °C AI02124 Figure 9. Clock calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B Doc ID 2410 Rev 9 15/25

Clock operations M48T02, M48T12 3.5 V noise and negative going transients CC I transients, including those produced by output switching, can produce voltage CC fluctuations, resulting in spikes on the V bus. These transients can be reduced if CC capacitors are used to store energy which stabilizes the V bus. The energy stored in the CC bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in Figure10 on page16) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V that drive it to values below V by as much as CC SS one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a Schottky diode from V to V (cathode connected to V , anode to V ). Schottky diode CC SS CC SS 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 10. Supply voltage protection VCC VCC 0.1μF DEVICE VSS AI02169 16/25 Doc ID 2410 Rev 9

M48T02, M48T12 Maximum ratings 4 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Absolute maximum ratings Symbol Parameter Value Unit T Ambient operating temperature 0 to 70 °C A T Storage temperature (V off, oscillator off) –40 to 85 °C STG CC T (1)(2) Lead solder temperature for 10 seconds 260 °C SLD V Input or output voltages –0.3 to 7 V IO V Supply voltage –0.3 to 7 V CC I Output current 20 mA O P Power dissipation 1 W D 1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries. 2. For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid damaging the crystal. Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode. Doc ID 2410 Rev 9 17/25

DC and AC parameters M48T02, M48T12 5 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions Parameter M48T02 M48T12 Unit Supply voltage (V ) 4.75 to 5.5 4.5 to 5.5 V CC Ambient operating temperature (T ) 0 to 70 0 to 70 °C A Load capacitance (C ) 100 100 pF L Input rise and fall times ≤ 5 ≤ 5 ns Input pulse voltages 0 to 3 0 to 3 V Input and output timing ref. voltages 1.5 1.5 V Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 11. AC testing load circuit 5V 1.8kΩ DEVICE UNDER OUT TEST 1kΩ CL = 100pF CL includes JIG capacitance AI01019 Table 8. Capacitance Symbol Parameter(1)(2) Min Max Unit C Input capacitance - 10 pF IN C (3) Input / output capacitance - 10 pF IO 1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested. 2. At 25 °C, f = 1 MHz. 3. Outputs deselected. 18/25 Doc ID 2410 Rev 9

M48T02, M48T12 DC and AC parameters Table 9. DC characteristics Symbol Parameter Test condition(1) Min Max Unit I Input leakage current 0V ≤ V ≤ V ±1 µA LI IN CC I (2) Output leakage current 0V ≤ V ≤ V ±1 µA LO OUT CC I Supply current Outputs open 80 mA CC I (3) Supply current (standby) TTL E = V 3 mA CC1 IH I (3) Supply current (standby) CMOS E = V – 0.2 V 3 mA CC2 CC V Input low voltage –0.3 0.8 V IL V Input high voltage 2.2 V + 0.3 V IH CC V Output low voltage I = 2.1 mA 0.4 V OL OL V Output high voltage I = –1 mA 2.4 V OH OH 1. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). A CC 2. Outputs deselected. 3. Measured with control bits set as follows: R = '1'; W, ST, FT = '0.' Figure 12. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO tF tDR tR tPD tFB tRB trec INPUTS RECOGNIZED DON'T CARE NOTE RECOGNIZED HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI00606 Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as V rises past V (min). Some systems may perform inadvertent WRITE cycles after V CC PFD CC rises above V (min) but before normal system operations begin. Even though a power on PFD reset is being applied to the processor, a reset condition may not occur until after the system clock is running. Doc ID 2410 Rev 9 19/25

DC and AC parameters M48T02, M48T12 Table 10. Power down/up AC characteristics Symbol Parameter(1) Min Max Unit t E or W at V before power down 0 - µs PD IH t (2) V (max) to V (min) V fall time 300 - µs F PFD PFD CC t (3) V (min) to V V fall time 10 - µs FB PFD SS CC t V (min) to V (max) V rise time 0 - µs R PFD PFD CC t V to V (min) V rise time 1 - µs RB SS PFD CC t E or W at V before power-up 2 - ms rec IH 1. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where A CC noted). 2. V (max) to V (min) fall time of less than t may result in deselection/write protection not occurring PFD PFD F until 200 µs after V passes V (min). CC PFD 3. V (min) to V fall time of less than t may cause corruption of RAM data. PFD SS FB Table 11. Power down/up trip points DC characteristics Symbol Parameter(1)(2) Min Typ Max Unit M48T02 4.5 4.6 4.75 V V Power-fail deselect voltage PFD M48T12 4.2 4.3 4.5 V V Battery backup switchover voltage 3.0 V SO t (3) Expected data retention time 10 YEARS DR 1. All voltages referenced to V . SS 2. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where A CC noted). 3. At 25 °C; V = 0 V. CC 20/25 Doc ID 2410 Rev 9

M48T02, M48T12 Package mechanical data 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline A2 A A1 L C B1 B e1 eA e3 D N E 1 PCDIP Note: Drawing is not to scale. Table 12. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mech. data mm inches Symb Typ Min Max Typ Min Max A 8.89 9.65 0.350 0.380 A1 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 34.29 34.80 1.350 1.370 E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 27.94 1.1 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 24 24 Doc ID 2410 Rev 9 21/25

Part numbering M48T02, M48T12 7 Part numbering Table 13. Ordering information scheme Example: M48T 02 –70 PC 1 Device type M48T Supply voltage and write protect voltage 02 = V = 4.75 to 5.5 V; V = 4.5 to 4.75 V CC PFD 12 = V = 4.5 to 5.5 V; V = 4.2 to 4.5 V CC PFD Speed –70 = 70 ns (M48T02/12) –150 = 150 ns (M48T02/12) –200 = 200 ns (M48T02/12)(1) Package PC = PCDIP24 Temperature range 1 = 0 to 70 °C Shipping method blank = ECOPACK® package, tubes 1. Not recommended for new design. Contact ST sales office for availability. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. 22/25 Doc ID 2410 Rev 9

M48T02, M48T12 Environmental information 8 Environmental information Figure 14. Recycling symbols This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Doc ID 2410 Rev 9 23/25

Revision history M48T02, M48T12 9 Revision history Table 14. Document revision history Date Revision Changes Jul-2000 1.0 First issue 13-Jul-2000 1.1 t change (Table10) rec 07-May-2001 2.0 Reformatted; temp. / voltage info. added to tables (Table8, 9, 3, 4, 10, 11) 14-May-2001 2.1 Note added to clock calibration section; table footnote correction (Table2) 16-Jul-2001 2.2 Basic formatting / content changes (cover page, Table8, 9) 20-May-2002 2.3 Add countries to disclaimer 26-Jun-2002 2.4 Add footnote to table (Table11) 28-Mar-2003 3.0 v2.2 template applied; test conditions updated (Table10) Reformatted; lead-free (Pb-free) package information update (Table6, 31-Mar-2004 4.0 13) 12-Dec-2005 5.0 Updated template, lead-free text, removed footnote (Table9, 13) Added lead-free second level interconnect information to cover page and 21-Sep-2007 6 Section6: Package mechanical data. Added Section8: Environmental information; updated text in Section6: 13-Jan-2009 7 Package mechanical data; minor formatting changes. 02-Aug-2010 8 Reformatted document; updated Section4, Table12, 13. Updated footnote 1 of Table6: Absolute maximum ratings; updated 07-Jun-2011 9 Section8: Environmental information. 24/25 Doc ID 2410 Rev 9

M48T02, M48T12 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 2410 Rev 9 25/25