M48T08 M48T08Y, M48T18 ® 5 V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM Features ■ Integrated ultra low power SRAM, real-time clock, power-fail control circuit, and battery ■ BYTEWIDE™ RAM-like clock access ■ BCD coded year, month, day, date, hours, minutes, and seconds ■ Typical clock accuracy of ±1 minute a month, at 25 °C 28 1 ■ Automatic power-fail chip deselect and WRITE protection PCDIP28 ■ WRITE protect battery/crystal VPFD = power-fail deselect voltage): CAPHAT™ – M48T08: V = 4.75 to 5.5 V; CC 4.5 V ≤ V ≤ 4.75 V PFD – M48T18/T08Y: V = 4.5 to 5.5 V; CC 4.2 V ≤ V ≤ 4.5 V PFD ■ Software controlled clock calibration for high SNAPHAT® accuracy applications battery/crystal ■ Self-contained battery and crystal in the CAPHAT™ DIP package ■ Packaging includes a 28-lead SOIC and SNAPHAT® top (to be ordered separately) ■ SOIC package provides direct connection for a snaphat top which contains the battery and crystal 28 1 ■ Pin and function compatible with DS1643 and JEDEC standard 8 K x 8 SRAMs SOH28 ■ RoHS compliant – Lead-free second level interconnect June 2011 Doc ID 2411 Rev 11 1/31 www.st.com 1

Contents M48T08, M48T08Y, M48T18 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 Power-fail interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 V noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 18 CC 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10. Power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data . . . . . . . . . . . . . 23 Table 13. SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT®, package mech. data. . . . . . . 24 Table 14. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package mech. data. . . . . 25 Table 15. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package mech. data. . . . 26 Table 16. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 17. SNAPHAT® battery table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Doc ID 2411 Rev 11 3/31

List of figures M48T08, M48T08Y, M48T18 List of figures Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. SOIC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. READ mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 7. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Crystal accuracy across temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. Clock calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10. Supply voltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11. AC testing load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline. . . . . . . . . . . . . . . . . 23 Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT®, package outline. . . 24 Figure 15. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package outline. . . . . . . . . 25 Figure 16. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package outline. . . . . . . . 26 Figure 17. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Description 1 Description The M48T08/18/08Y TIMEKEEPER® RAM is an 8 K x 8 non-volatile static RAM and real- time clock which is pin and function compatible with the DS1643. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory and real-time clock solution. The M48T08/18/08Y is a non-volatile pin and function equivalent to any JEDEC standard 8 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 28-pin, 600 mil DIP CAPHAT™ houses the M48T08/18/08Y silicon with a quartz crystal and a long-life lithium button cell in a single package. The 28-pin, 330 mil SOIC provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT® housing containing the battery and crystal. The unique design allows the SNAPHAT® battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT® housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT® housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT®) part number is “M4T28-BR12SH” or “M4T32-BR12SH”. Figure 1. Logic diagram VCC 13 8 A0-A12 DQ0-DQ7 W M48T08 M48T08Y E1 INT M48T18 E2 G VSS AI01020 Doc ID 2411 Rev 11 5/31

Description M48T08, M48T08Y, M48T18 Table 1. Signal names A0-A12 Address inputs DQ0-DQ7 Data inputs / outputs INT Power fail interrupt (open drain) E1 Chip enable 1 E2 Chip enable 2 G Output enable W WRITE enable V Supply voltage CC V Ground SS Figure 2. DIP connections INT 1 28 VCC A12 2 27 W A7 3 26 E2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 G M48T08 A2 8 M48T18 21 A10 A1 9 20 E1 A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 VSS 14 15 DQ3 AI01182 Figure 3. SOIC connections INT 1 28 VCC A12 2 27 W A7 3 26 E2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 G M48T08Y A2 8 21 A10 A1 9 20 E1 A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 VSS 14 15 DQ3 AI01021B 6/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Description Figure 4. Block diagram OSCILLATOR AND 8 x 8 BiPORT CLOCK CHAIN SRAM ARRAY 32,768 Hz CRYSTAL A0-A12 POWER DQ0-DQ7 8184 x 8 SRAM ARRAY LITHIUM CELL E1 VOLTAGE SENSE E2 AND VPFD SWITCHING W CIRCUITRY G VCC INT VSS AI01333 Doc ID 2411 Rev 11 7/31

Operation modes M48T08, M48T08Y, M48T18 2 Operation modes As Figure4 on page7 shows, the static memory array and the quartz-controlled clock oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE memory cells. The M48T08/18/08Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T08/18/08Y also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out-of-tolerance condition. When V is out CC of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V . As V falls below the CC CC battery backup switchover voltage (V ), the control circuitry connects the battery which SO maintains data and clock operation until valid power returns. Table 2. Operating modes Mode V E1 E2 G W DQ0-DQ7 Power CC Deselect V X X X High Z Standby IH Deselect 4.75 to 5.5 V X VIL X X High Z Standby WRITE or V V X V D Active IL IH IL IN READ 4.5 to 5.5 V V V V V D Active IL IH IL IH OUT READ V V V V High Z Active IL IH IH IH V to Deselect SO X X X X High Z CMOS standby V (min)(1) PFD Deselect ≤ V (1) X X X X High Z Battery backup mode SO 1. See Table11 on page22 for details. Note: X = V or V ;V = Battery backup switchover voltage. IH IL SO 8/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Operation modes 2.1 READ mode The M48T08/18/08Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip enable 1) is low, and E2 (chip enable 2) is high. The device architecture allows ripple- through access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t ) after the last address input signal is stable, providing that the E1, E2, and G AVQV access times are also satisfied. If the E1, E2 and G access times are not met, valid data will be available after the latter of the chip enable access times (t or t ) or output E1LQV E2HQV enable access time (t ). GLQV The state of the eight three-state data I/O signals is controlled by E1, E2 and G. If the outputs are activated before t , the data lines will be driven to an indeterminate state AVQV until t . If the address inputs are changed while E1, E2 and G remain active, output data AVQV will remain valid for output data hold time (t ) but will go indeterminate until the next AXQX address access. Figure 5. READ mode AC waveforms tAVAV A0-A12 VALID tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ E2 tE2HQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI00962 Note: WRITE enable (W) = high. Doc ID 2411 Rev 11 9/31

Operation modes M48T08, M48T08Y, M48T18 Table 3. READ mode AC characteristics M48T08/M48T18/T08Y Symbol Parameter(1) –100/–10 (T08Y) –150/–15 (T08Y) Unit Min Max Min Max t READ cycle time 100 150 ns AVAV t Address valid to output valid 100 150 ns AVQV t Chip enable 1 low to output valid 100 150 ns E1LQV t Chip enable 2 high to output valid 100 150 ns E2HQV t Output enable low to output valid 50 75 ns GLQV t Chip enable 1 low to output transition 10 10 ns E1LQX t Chip enable 2 high to output transition 10 10 ns E2HQX t Output enable low to output transition 5 5 ns GLQX t Chip enable 1 high to output Hi-Z 50 75 ns E1HQZ t Chip enable 2 low to output Hi-Z 50 75 ns E2LQZ t Output enable high to output Hi-Z 40 60 ns GHQZ t Address transition to output transition 5 5 ns AXQX Note: Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V A CC (except where noted). 2.2 WRITE mode The M48T08/18/08Y is in the WRITE mode whenever W, E1, and E2 are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2. The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low for a minimum of t or t from chip enable or t from WRITE enable prior to the E1HAX E2LAX WHAX initiation of another READ or WRITE cycle. Data-in must be valid t prior to the end of DVWH WRITE and remain valid for t afterward. G should be kept high during WRITE cycles to WHDX avoid bus contention; however, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs t after W falls. WLQZ 10/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Operation modes Figure 6. WRITE enable controlled, WRITE AC waveform tAVAV A0-A12 VALID tAVWH tAVE1L tWHAX E1 tAVE2H E2 tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA INPUT tDVWH AI00963 Figure 7. Chip enable controlled, WRITE AC waveforms tAVAV A0-A12 VALID tAVE1H tAVE1L tE1LE1H tE1HAX E1 tAVE2L tAVE2H tE2HE2L tE2LAX E2 tAVWL W tE1HDX tE2LDX DQ0-DQ7 DATA INPUT tDVE1H tDVE2L AI00964B Doc ID 2411 Rev 11 11/31

Operation modes M48T08, M48T08Y, M48T18 Table 4. WRITE mode AC characteristics M48T08/M48T18/T08Y Symbol Parameter(1) –100/–10 (T08Y) –150/–15 (T08Y) Unit Min Max Min Max t WRITE cycle time 100 150 ns AVAV t Address valid to WRITE enable low 0 0 ns AVWL t Address valid to chip enable 1 low 0 0 ns AVE1L t Address valid to chip enable 2 high 0 0 ns AVE2H t WRITE enable pulse width 80 100 ns WLWH t Chip enable 1 low to chip enable 1 high 80 130 ns E1LE1H t Chip enable 2 high to chip enable 2 low 80 130 ns E2HE2L t WRITE enable high to address transition 10 10 ns WHAX t Chip enable 1 high to address transition 10 10 ns E1HAX t Chip enable 2 low to address transition 10 10 ns E2LAX t Input valid to WRITE enable high 50 70 ns DVWH t Input valid to chip enable 1 high 50 70 ns DVE1H t Input valid to chip enable 2 low 50 70 ns DVE2L t WRITE enable high to input transition 5 5 ns WHDX t Chip enable 1 high to input transition 5 5 ns E1HDX t Chip enable 2 low to input transition 5 5 ns E2LDX t WRITE enable low to output Hi-Z 50 70 ns WLQZ t Address valid to WRITE enable high 80 130 ns AVWH t Address valid to chip enable 1 high 80 130 ns AVE1H t Address valid to chip enable 2 low 80 130 ns AVE2L t WRITE enable high to output transition 10 10 ns WHQX 1. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). A CC 12/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Operation modes 2.3 Data retention mode With valid V applied, the M48T08/18/08Y operates as a conventional BYTEWIDE™ static CC RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V falls within the V (max), V (min) window. All outputs CC PFD PFD become high impedance, and all inputs are treated as “Don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V (min), the PFD user can be assured the memory will be in a write protected state, provided the V fall time CC is not less than t . The M48T08/18/08Y may respond to transient noise spikes on V that F CC reach into the deselect window during the time the device is sampling V . Therefore, CC decoupling of the power supply lines is recommended. When V drops below V , the control circuit switches power to the internal battery which CC SO preserves data and powers the clock. The internal button cell will maintain data in the M48T08/18/08Y for an accumulated period of at least 10 years when V is less than V . CC SO Note: Requires use of M4T32-BR12SH SNAPHAT® top when using the SOH28 package. As system power returns and V rises above V , the battery is disconnected and the CC SO power supply is switched to external V . CC Write protection continues until V reaches V (min) plus t (min). E1 should be kept CC PFD rec high or E2 low as V rises past V (min) to prevent inadvertent WRITE cycles prior to CC PFD system stabilization. Normal RAM operation can resume t after V exceeds V (max). rec CC PFD For more information on battery storage life refer to the application note AN1012. 2.4 Power-fail interrupt pin The M48T08/18/08Y continuously monitors V . When V falls to the power-fail detect trip CC CC point, an interrupt is immediately generated. An internal clock provides a delay of between 10 µs and 40 µs before automatically deselecting the M48T08/18/08Y. The INT pin is an open drain output and requires an external pull-up resistor, even if the interrupt output function is not being used. Doc ID 2411 Rev 11 13/31

Clock operations M48T08, M48T08Y, M48T18 3 Clock operations 3.1 Reading the clock Updates to the TIMEKEEPER® registers should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, the seventh bit in the control register. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.' 3.2 Setting the clock The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a '1,' like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (on Table5). Resetting the WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits marked as '0' in Table5 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. See the application note AN923, “TIMEKEEPER® rolling Into the 21st century” for information on century rollover. 14/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Clock operations T able 5. Register map Data Function/range Address BCD format D7 D6 D5 D4 D3 D2 D1 D0 1FFFh 10 years Year Year 00-99 1FFEh 0 0 0 10 M Month Month 01-12 1FFDh 0 0 10 date Date Date 01-31 1FFCh 0 FT 0 0 0 Day Day 01-07 1FFBh 0 0 10 hours Hours Hours 00-23 1FFAh 0 10 minutes Minutes Minutes 00-59 1FF9h ST 10 seconds Seconds Seconds 00-59 1FF8h W R S Calibration Control Keys: S = SIGN bit FT = FREQUENCY TEST bit (set to '0' for normal clock operation) R = READ bit W = WRITE bit ST = STOP bit 0 = Must be set to '0' 3.3 Stopping and starting the oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit (ST) is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T08/18/08Y (in the PCDIP28 package) is shipped from STMicroelectronics with the STOP bit set to a '1.' When reset to a '0,' the M48T08/18/08Y oscillator starts within one second. Note: To guarantee oscillator startup after initial power-up, first write the STOP bit (ST) to '1,' then reset to '0.' 3.4 Calibrating the clock The M48T08/18/08Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. A typical M48T08/18/08Y is accurate within 1 minute per month at 25 °C without calibration. The devices are tested not to exceed ± 35 ppm (parts per million) oscillator frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T08/18/08Y improves to better than +1/–2 ppm at 25 °C. The oscillation rate of any crystal changes with temperature. Figure8 on page17 shows the frequency error that can be expected at various temperatures. Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The Doc ID 2411 Rev 11 15/31

Clock operations M48T08, M48T08Y, M48T18 M48T08/18/08Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure9 on page17. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration byte occupies the five lower order bits in the control register. This byte can be set to represent any value between 0 and 31 in binary form. The sixth bit is the sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T08/18/08Y may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of standard test equipment. When the frequency test (FT) bit, the seventh-most significant bit in the day register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB (DQ0) of the seconds register will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (WR001010) to be loaded into the calibration byte for correction. Note: Setting or changing the calibration byte does not affect the frequency test output frequency. The device must be selected and addresses must be stable at address 1FF9h when reading the 512 Hz on DQ0. The LSB of the seconds register is monitored by holding the M48T08/18/08Y in an extended READ of the seconds register, but without having the READ bit set. The FT bit MUST be reset to '0' for normal clock operations to resume. For more information on calibration, see the application note AN934, “TIMEKEEPER® calibration.” 16/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Clock operations Figure 8. Crystal accuracy across temperature ppm 20 0 -20 -40 ΔF = -0.038 ppm(T - T)2 ± 10% F C2 0 -60 T = 25 °C 0 -80 -100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 °C AI02124 Figure 9. Clock calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B Doc ID 2411 Rev 11 17/31

Clock operations M48T08, M48T08Y, M48T18 3.5 V noise and negative going transients CC I transients, including those produced by output switching, can produce voltage CC fluctuations, resulting in spikes on the V bus. These transients can be reduced if CC capacitors are used to store energy which stabilizes the V bus. The energy stored in the CC bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in Figure10) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V that drive it to values below V by as much as CC SS one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a Schottky diode from V to V (cathode connected to V , anode to V ). Schottky diode CC SS CC SS 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 10. Supply voltage protection VCC VCC 0.1µF DEVICE VSS AI02169 18/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Maximum ratings 4 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Absolute maximum ratings Symbol Parameter Value Unit T Ambient operating temperature 0 to 70 °C A T Storage temperature (V off, oscillator off) –40 to 85 °C STG CC T (1)(2)(3) Lead solder temperature for 10 seconds 260 °C SLD V Input or output voltages –0.3 to 7 V IO V Supply voltage –0.3 to 7 V CC I Output current 20 mA O P Power dissipation 1 W D 1. For DIP package, soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries. 2. For DIP packaged devices, ultrasound vibrations should not be used for post-solder cleaning to avoid damaging the crystal. 3. For SO package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above 255 °C must not exceed 30 seconds). Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode. Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT® sockets. Doc ID 2411 Rev 11 19/31

DC and AC parameters M48T08, M48T08Y, M48T18 5 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions Parameter M48T08 M48T18/T08Y Unit Supply voltage (V ) 4.75 to 5.5 4.5 to 5.5 V CC Ambient operating temperature (T ) 0 to 70 0 to 70 °C A Load capacitance (C ) 100 100 pF L Input rise and fall times ≤ 5 ≤ 5 ns Input pulse voltages 0 to 3 0 to 3 V Input and output timing ref. voltages 1.5 1.5 V Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 11. AC testing load circuit 5V 1.8kΩ DEVICE UNDER OUT TEST 1kΩ CL = 100pF CL includes JIG capacitance AI01019 Table 8. Capacitance Symbol Parameter(1)(2) Min Max Unit C Input capacitance - 10 pF IN C (3) Input / output capacitance - 10 pF IO 1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested. 2. At 25 °C, f = 1 MHz. 3. Outputs deselected. 20/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 DC and AC parameters Table 9. DC characteristics M48T08/M48T18/T08Y Symbol Parameter Test condition(1) Unit Min Max I Input leakage current 0V ≤ V ≤ V ±1 µA LI IN CC I (2) Output leakage current 0V ≤ V ≤ V ±1 µA LO OUT CC I Supply current Outputs open 80 mA CC I (3) Supply current (standby) TTL E1 = V E2 = V 3 mA CC1 IH, IL E1 = V – 0.2V, I (3) Supply current (standby) CMOS CC 3 mA CC2 E2 = V + 0.2V SS V Input low voltage –0.3 0.8 V IL V Input high voltage 2.2 V + 0.3 V IH CC Output low voltage I = 2.1 mA 0.4 V OL V OL Output low voltage (INT)(4) I = 0.5 mA 0.4 V OL V Output high voltage I = –1 mA 2.4 V OH OH 1. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). A CC 2. Outputs deselected. 3. Measured with control bits set as follows: R = '1'; W, ST, FT = '0.' 4. The INT pin is open drain. Figure 12. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO tF tDR tR tPD tFB tRB tPFX tPFH INT trec INPUTS RECOGNIZED DON'T CARE NOTE RECOGNIZED HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI00566 Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as V rises past V (min). Some systems may perform inadvertent WRITE CC PFD cycles after V rises above V (min) but before normal system operations begin. Even CC PFD though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running. Doc ID 2411 Rev 11 21/31

DC and AC parameters M48T08, M48T08Y, M48T18 Table 10. Power down/up AC characteristics Symbol Parameter(1) Min Max Unit t E1 or W at V or E2 at V before power-down 0 µs PD IH IL t (2) V (max) to V (min) V fall time 300 µs F PFD PFD CC t (3) V (min) to V V fall time 10 µs FB PFD SS CC t V (min) to V (max) V rise time 0 µs R PFD PFD CC t V to V (min) V rise time 1 µs RB SS PFD CC t E1 or W at V or E2 at V before power-up 1 ms rec IH IL t INT low to auto deselect 10 40 µs PFX t V (max) to INT high 120 µs PFH PFD 1. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where A CC noted). 2. V (max) to V (min) fall time of less than t may result in deselection/write protection not occurring PFD PFD F until 200 µs after V passes V (min). CC PFD 3. V (min) to V fall time of less than t may cause corruption of RAM data. PFD SS FB Table 11. Power down/up trip points DC characteristics Symbol Parameter(1)(2) Min Typ Max Unit M48T08 4.5 4.6 4.75 V V Power-fail deselect voltage PFD M48T18/T08Y 4.2 4.3 4.5 V V Battery backup switchover voltage 3.0 V SO t Expected data retention time 10(3) Years DR 1. All voltages referenced to V . SS 2. Valid for ambient operating temperature: T = 0 to 70 °C; V = 4.75 to 5.5 V or 4.5 to 5.5 V (except where A CC noted). 3. At 55 °C, V = 0 V; t = 8.5 years (typ) at 70 °C. Requires use of M4T32-BR12SH SNAPHAT® top when CC DR using the SOH28 package. 22/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Package mechanical data 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline A2 A A1 L C B1 B e1 eA e3 D N E 1 PCDIP Note: Drawing is not to scale. Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data mm inches Symb Typ Min Max Typ Min Max A 8.89 9.65 0.350 0.380 A1 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 39.37 39.88 1.550 1.570 E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 33.02 1.3 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 28 28 Doc ID 2411 Rev 11 23/31

Package mechanical data M48T08, M48T08Y, M48T18 Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT®, package outline A2 A C B e eB CP D N E H A1 α L 1 SOH-A Note: Drawing is not to scale. Table 13. SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT®, package mech. data mm inches Symb Typ Min Max Typ Min Max A 3.05 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 e 1.27 – – 0.050 – – eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 α 0° 8° 0° 8° N 28 28 CP 0.10 0.004 24/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Package mechanical data Figure 15. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package outline A2 A1 A A3 eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 14. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package mech. data mm inches Symb Typ Min Max Typ Min Max A 9.78 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 Doc ID 2411 Rev 11 25/31

Package mechanical data M48T08, M48T08Y, M48T18 Figure 16. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package outline A2 A1 A A3 eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package mech. data mm inches Symb Typ Min Max Typ Min Max A 10.54 0.415 A1 8.00 8.51 0.315 .0335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 .0710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 26/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Part numbering 7 Part numbering Table 16. Ordering information scheme Example: M48T 18 –100 PC 1 E Device type M48T Supply voltage and write protect voltage 08(1) = V = 4.75 to 5.5 V; V = 4.5 to 4.75 V CC PFD 18/08Y = V = 4.5 to 5.5 V; V = 4.2 to 4.5 V CC PFD Speed –100 = 100 ns –150 = 150 ns –10 = 100 ns (M48T08Y) Package PC(1) = PCDIP28 MH(2) = SOH28 Temperature range 1 = 0 to 70 °C Shipping method For SOH28: blank = Tubes (not for new design - use E) E = ECOPACK® package, tubes F = ECOPACK® package, tape & reel TR = Tape & reel (not for new design - use F) For PCDIP28: blank = ECOPACK® package, tubes 1. The M48T08/18 part is offered with the PCDIP28 (e.g., CAPHAT™) package only. 2. The SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered separately under the part number “M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in tape & reel form (see Table17). The M48T08Y part is offered in the SOH28 (SNAPHAT) package only. Caution: Do not place the SNAPHAT® battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Doc ID 2411 Rev 11 27/31

Part numbering M48T08, M48T08Y, M48T18 Table 17. SNAPHAT® battery table Part number Description Package M4T28-BR12SH Lithium battery (48 mAh) SNAPHAT® SH M4T32-BR12SH Lithium battery (120 mAh) SNAPHAT® SH 28/31 Doc ID 2411 Rev 11

M48T08, M48T08Y, M48T18 Environmental information 8 Environmental information Figure 17. Recycling symbols This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Doc ID 2411 Rev 11 29/31

Revision history M48T08, M48T08Y, M48T18 9 Revision history Table 18. Document revision history Date Revision Changes Dec-1999 1 First Issue From Preliminary Data to Datasheet; Battery Low Flag paragraph 07-Feb-2000 2 changed; 100ns speed class identifier changed (Table3, 4) 11-Jul-2000 2.1 t changed (Table10); Watchdog Timer paragraph changed FB Reformatted; SNAPHAT battery table added (Table17); added 16-Jul-2001 3 temp./voltage info. to tables (Table8, 9, 3, 4, 10, 11). 01-Aug-2001 3.1 Reference to App. Note corrected in “Calibrating the Clock” section 21-Dec-2001 3.2 Changes to text in document to reflect addition of M48T08Y option 06-Mar-2002 3.3 Fix Ordering Information table and add to footnote (Table16) 20-May-2002 3.4 Modify reflow time and temperature footnotes (Table6) 29-Aug-2002 3.5 t specification temperature updated (Table11) DR 28-Mar-2003 4 v2.2 template applied; updated test conditions (Table10) 10-Dec-2003 5 Reformatted Reformatted; Lead-free (Pb-free) information package update (Table6, 30-Mar-2004 6 16) 13-Dec-2005 7 Updated template, Lead-free information, removed footnote (Table9, 16) Reformatted; added lead-free second level interconnect information to 04-Jul-2007 8 cover page and Section6: Package mechanical data. Updated Table6, text in Section6: Package mechanical data; added 10-Feb-2009 9 Section8: Environmental information; minor formatting changes. 21-Jun-2010 10 Updated Section4, Table12; reformatted document. Updated footnote 1 of Table6: Absolute maximum ratings; updated 07-Jun-2011 11 Section8: Environmental information. 30/31 Doc ID 2411 Rev 11

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