M41T80 Serial access real-time clock with alarm Features ■ Counters for tenths/hundredths of seconds, 8 seconds, minutes, hours, day, date, month, year, and century ■ 32 KHz crystal oscillator integrating load 1 capacitance (12.5 pF) providing exceptional oscillator stability and high crystal series SO8 resistance operation 8-pin SOIC ■ Serial interface supports I2C bus (400 kHz) ■ 2.0 to 5.5 V clock operating voltage ■ 32 KHz square wave on power-up to drive a microcontroller in low-power mode ■ Programmable (1 Hz to 32 KHz) square wave ■ Programmable alarm and interrupt function ■ Low operating current of 200 µA ■ Operating temperature of –40 to 85 °C ■ ECOPACK® package available August 2011 Doc ID 9074 Rev 5 1/27 www.st.com 1

Contents M41T80 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2-Wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 Full-time 32 KHz square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 Preferred power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 Doc ID 9074 Rev 5

M41T80 List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Alarm repeat modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Square wave output frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6. Preferred power-on default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 7. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 10. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11. Crystal electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 12. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . 22 Table 13. Carrier tape dimensions for SO8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 14. Reel dimensions for 12 mm carrier tape - SO8 package (150 mils body width). . . . . . . . . 24 Table 15. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 16. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 9074 Rev 5 3/27

List of figures M41T80 List of figures Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. 8-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. READ mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 9. Alternative READ mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 11. Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12. AC measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical drawing. . . 22 Figure 14. Carrier tape for SO8 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 15. Reel schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4/27 Doc ID 9074 Rev 5

M41T80 Description 1 Description The M41T80 is a low power serial RTC with a built-in 32.768 kHz oscillator (external crystal controlled). Eight registers (see Table3: Clock register map on page14) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 registers provide status/control of alarm, 32 KHz output, and square wave functions. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. Functions available to the user include a time-of-day clock/calendar, alarm interrupts, 32 KHz output, and programmable square wave output. The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The M41T80 is supplied in an 8-pin SOIC. Figure 1. Logic diagram VCC XI XO IRQ/OUT/SQW M41T80 SCL F32K SDA VSS AI07005 T able 1. Signal names XI Oscillator input XO Oscillator output IRQ/OUT/SQW Interrupt / output driver / square wave (open drain) SDA Serial data input/output SCL Serial clock input F 32 KHz square wave output (open drain) 32K V Supply voltage CC V Ground SS Doc ID 9074 Rev 5 5/27

Description M41T80 Figure 2. 8-pin SOIC connections XI 1 8 VCC XO 2 7 IRQ/OUT/SQW(1) F32K(1) 3 M41T80 6 SCL VSS 4 5 SDA AI07006 1. Open drain output Figure 3. Block diagram REAL TIME CLOCK CALENDAR 32KHz CRYSTAL RTC W/ALARM OSCILLATOR AF IRQ/OUT/SQW(1) SDA SQUARE WAVE I2C INTERFACE SCL F32K(1) AI07007 1. Open drain output 6/27 Doc ID 9074 Rev 5

M41T80 Operation 2 Operation The M41T80 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 20 bytes contained in the device can then be accessed sequentially in the following order: ● 1st byte: tenths/hundredths of a second register ● 2nd byte: seconds register ● 3rd byte: minutes register ● 4th byte: century/hours register ● 5th byte: day register ● 6th byte: date register ● 7th byte: month register ● 8th byte: year register ● 9th byte: control register ● 10th byte: 32KE bit ● 11th - 16th bytes: alarm registers ● 17th - 19th bytes: reserved ● 20th byte: square wave register 2.1 2-Wire bus characteristics The bus is intended for communication between different IC’s. It consists of two lines: a bi- directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: ● Data transfer may be initiated only when the bus is not busy. ● During data transfer, the data line must remain stable whenever the clock line is high. ● Changes in the data line, while the clock line is high, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: 2.1.1 Bus not busy Both data and clock lines remain high. 2.1.2 Start data transfer A change in the state of the data line, from high to low, while the clock is high, defines the START condition. 2.1.3 Stop data transfer A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition. Doc ID 9074 Rev 5 7/27

Operation M41T80 2.1.4 Data valid The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called “master.” The devices that are controlled by the master are called “slaves.” 2.1.5 Acknowledge Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 4. Serial bus data transfer sequence DATA LINE STABLE DATA VALID CLOCK DATA START CHANGE OF STOP CONDITION DATA ALLOWED CONDITION AI00587 8/27 Doc ID 9074 Rev 5

M41T80 Operation Figure 5. Acknowledgement sequence CLOCK PULSE FOR START ACKNOWLEDGEMENT SCL FROM 1 2 8 9 MASTER DATA OUTPUT MSB LSB BY TRANSMITTER DATA OUTPUT BY RECEIVER AI00601 Figure 6. Bus timing requirements sequence SDA t t t BUF HD:STA HD:STA t t R F SCL t HIGH tSU:DAT tSU:STA tSU:STO P S t t SR P LOW HD:DAT AI00589 Doc ID 9074 Rev 5 9/27

Operation M41T80 T able 2. AC characteristics Sym Parameter(1) Min Typ Max Units f SCL clock frequency 0 400 kHz SCL t Clock low period 1.3 µs LOW t Clock high period 600 ns HIGH t SDA and SCL rise time 300 ns R t SDA and SCL fall time 300 ns F START condition hold time t 600 ns HD:STA (after this period the first clock pulse is generated) START condition setup time t 600 ns SU:STA (only relevant for a repeated start condition) t (2) Data setup time 100 ns SU:DAT t Data hold time 0 µs HD:DAT t STOP condition setup time 600 ns SU:STO Time the bus must be free before a new t 1.3 µs BUF transmission can start 1. Valid for ambient operating temperature: T = –40 to 85 °C; V = 2.0 to 5.5 V (except where A CC noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL. 2.2 READ mode In this mode the master reads the M41T80 slave after setting the slave address (Figure8: READ mode sequence). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge clock. The M41T80 slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to “An+2.” This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume due to a stop condition or when the pointer increments to any non-clock address (08h-13h). Note: This is true both in READ mode and WRITE mode. An alternate READ mode may also be implemented whereby the master reads the M41T80 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure9: Alternative READ mode sequence). 10/27 Doc ID 9074 Rev 5

M41T80 Operation Figure 7. Slave address location R/W START SLAVE ADDRESS A B S B M S L 1 1 0 1 0 0 0 AI00602 Figure 8. READ mode sequence T T R R BUS ACTIVITY: A W A W MASTER ST R/ ST R/ WORD SDA LINE S S DATA n DATA n+1 ADDRESS (An) K K K K K BUS ACTIVITY: C C C C C A A A A A SLAVE SLAVE ADDRESS ADDRESS P O T S DATA n+X P K C A O N AI00899 Figure 9. Alternative READ mode sequence T R P BMUASS TAECRTIVITY: STA R/W STO SDA LINE S DATA n DATA n+1 DATA n+X P K K K K K BUS ACTIVITY: C C C C C A A A A A O SLAVE N ADDRESS AI00895 Doc ID 9074 Rev 5 11/27

Operation M41T80 2.3 WRITE mode In this mode the master transmitter transmits to the M41T80 slave receiver. Bus protocol is shown in Figure10: WRITE mode sequence on page12. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address “An” will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T80 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure7: Slave address location on page11 and again after it has received the word address and each data byte. Figure 10. WRITE mode sequence T R P BUS ACTIVITY: A W O MASTER ST R/ ST WORD SDA LINE S DATA n DATA n+1 DATA n+X P ADDRESS (An) K K K K K BUS ACTIVITY: C C C C C A A A A A SLAVE ADDRESS AI00591 12/27 Doc ID 9074 Rev 5

M41T80 Clock operation 3 Clock operation The M41T80 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The 20-byte register map (see Table3: Clock register map on page14) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths of seconds, minutes, and hours are contained within the first four registers. Note: A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to “00,” and tenths/hundredths of seconds cannot be written to any value other than “00.” Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month and years. The ninth clock register is the control register. Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within four seconds (typically one second). The eight clock registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ. 3.1 Clock registers The M41T80 offers 20 internal registers which contain clock, alarm, 32 KHz, flag, square wave, and control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT™ cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a stop condition or when the pointer increments to any non-clock address (08h-13h). Clock and alarm registers store data in BCD. Control, 32 KHz, and square wave registers store data in binary format. Doc ID 9074 Rev 5 13/27

Clock operation M41T80 T able 3. Clock register map(1) Function/range BCD Addr format D7 D6 D5 D4 D3 D2 D1 D0 10s/100s 00h 0.1 seconds 0.01 seconds 00-99 of seconds 01h ST 10 seconds Seconds Seconds 00-59 02h 0 10 minutes Minutes Minutes 00-59 Century/ 03h CEB CB 10 hours Hours (24-hour format) 0-1/00-23 hours 04h 0 0 0 0 0 Day of week Day 01-7 05h 0 0 10 date Date: day of month Date 01-31 06h 0 0 0 10M Month Month 01-12 07h 10 years Year Year 00-99 08h OUT 0 0 0 0 0 0 0 Control 09h 32KE 0 0 0 0 0 0 0 32 KHz 0Ah AFE SQWE 0 Al 10M Alarm month Al month 01-12 0Bh RPT4 RPT5 AI 10 date Alarm date Al date 01-31 0Ch RPT3 0 AI 10 hour Alarm hour Al hour 00-23 0Dh RPT2 Alarm 10 minutes Alarm minutes Al min 00-59 0Eh RPT1 Alarm 10 seconds Alarm seconds Al sec 00-59 0Fh 0 AF 0 0 0 0 0 0 Flags 10h 0 0 0 0 0 0 0 0 Reserved 11h 0 0 0 0 0 0 0 0 Reserved 12h 0 0 0 0 0 0 0 0 Reserved 13h RS3 RS2 RS1 RS0 0 0 0 0 SQW 1. Keys: ST = Stop bit 0 = Must be set to '0' 32KE = Enable bit for 32 KHz output CEB = Enable for century bit CB = Century bit OUT = Data bit for OUT pin AFE = Alarm flag enable bit RPT1-RPT5 = Alarm repeat mode bits AF = Alarm flag (read only) SQWE = Square wave enable RS0-RS3 = SQW frequency select 14/27 Doc ID 9074 Rev 5

M41T80 Clock operation 3.2 Setting alarm clock registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table4: Alarm repeat modes shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set (and SQWE is '0.'), the alarm condition activates the IRQ/OUT/SQW pin. Note: If the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the “Alarm Seconds,” the address pointer will increment to the flag address, causing this situation to occur. The IRQ/OUT/SQW output is cleared by a READ to the flags register as shown in Figure11. A subsequent READ of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' Figure 11. Alarm interrupt reset waveform 0Eh 0Fh 10h ACTIVE FLAG IRQ/OUT/SQW HIGH-Z AI07021 T able 4. Alarm repeat modes RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting 1 1 1 1 1 Once per second 1 1 1 1 0 Once per minute 1 1 1 0 0 Once per hour 1 1 0 0 0 Once per day 1 0 0 0 0 Once per month 0 0 0 0 0 Once per year Doc ID 9074 Rev 5 15/27

Clock operation M41T80 T able 5. Square wave output frequency Square wave bits Square wave RS3 RS2 RS1 RS0 Frequency Units 0 0 0 0 None - 0 0 0 1 32.768 kHz 0 0 1 0 8.192 kHz 0 0 1 1 4.096 kHz 0 1 0 0 2.048 kHz 0 1 0 1 1.024 kHz 0 1 1 0 512 Hz 0 1 1 1 256 Hz 1 0 0 0 128 Hz 1 0 0 1 64 Hz 1 0 1 0 32 Hz 1 0 1 1 16 Hz 1 1 0 0 8 Hz 1 1 0 1 4 Hz 1 1 1 0 2 Hz 1 1 1 1 1 Hz 3.3 Full-time 32 KHz square wave output The M41T80 offers the user a special 32 KHz square wave function which defaults to output on the F pin (pin 3) as long as V is valid, and the oscillator is running (ST bit = '0'). This 32K CC function is available within four seconds of initial power-up and can only be disabled by setting the 32KE bit to '0' or the ST bit to '1.' If not used, the F pin should be disconnected 32K and allowed to float. Note: The F pin is an open drain which requires an external pull-up resistor. 32K 3.4 Century bit Bits D7 and D6 of clock register 03h contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. 16/27 Doc ID 9074 Rev 5

M41T80 Clock operation 3.5 Output driver pin When the AFE bit and SQWE bit are not set, the IRQ/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the control register. In other words, when D7 (OUT bit) of address location 08h is a '0,' then the IRQ/OUT/SQW pin will be driven low. Note: The IRQ/OUT/SQW pin is an open drain which requires an external pull-up resistor. 3.6 Preferred power-on default When powering the device up from ground (0 V), the following register bits are set to a '0' state: ST; AFE; and SQWE. The following bits are set to a '1' state: OUT and 32KE (see Table6: Preferred power-on default values on page17). T able 6. Preferred power-on default values Condition ST OUT AFE SQWE 32KE Power-up(1) 0 1 0 0 1 1. If V falls to a voltage, 0 V < V < 2.0 V, these bits should be rewritten by the user. CC CC Doc ID 9074 Rev 5 17/27

Maximum rating M41T80 4 Maximum rating Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. T able 7. Absolute maximum ratings Symbol Parameter Value Unit T Storage temperature (V off, oscillator off) –55 to 125 °C STG CC V Supply voltage –0.3 to 7 V CC T (1) Lead solder temperature for 10 seconds 260 °C SLD V Input or output voltages –0.3 to +6 V IO I Output current 20 mA O P Power dissipation 1 W D 1. For SO package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above 255 °C must not exceed 30 seconds). 18/27 Doc ID 9074 Rev 5

M41T80 DC and AC parameters 5 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. T able 8. Operating and AC measurement conditions (1) Parameter M41T80 Supply voltage (V ) 2.0 to 5.5 V CC Ambient operating temperature (T ) –40 to 85 °C A Load capacitance (C ) 100 pF L Input rise and fall times ≤ 50 ns Input pulse voltages 0.2V to 0.8V CC CC Input and output timing ref. voltages 0.3V to 0.7V CC CC 1. Output Hi-Z is defined as the point where data is no longer driven. Figure 12. AC measurement I/O waveform 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI02568 T able 9. Capacitance Symbol Parameter(1)(2) Min Max Unit C Input capacitance 7 pF IN C (3) Output capacitance 10 pF OUT t Low-pass filter input time constant (SDA and SCL) 50 ns LP 1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested. 2. At 25 °C, f = 1 MHz. 3. Outputs deselected. Doc ID 9074 Rev 5 19/27

DC and AC parameters M41T80 T able 10. DC characteristics Symbol Parameter Test condition(1) Min Typ Max Unit I Input leakage current 0 V ≤ V ≤ V ±1 µA LI IN CC I Output leakage current 0 V ≤ V ≤ V ±1 µA LO OUT CC 3.0 V 30 µA I Supply current Switch freq (SCL) = 400 kHz CC1 5.5 V 200 µA 32KE = 1 3.0 V 1.8 3.0 µA or 5.5 V 35 µA I (2) Supply current All inputs = VCC – 0.2 V SQWE = 1 CC2 (standby) Switch freq (SCL) = 0 Hz 32KE = 0 3.0 V 1.5 2.4 µA and 5.5 V 31 µA SQWE = 0 V Input low voltage –0.3 0.3V V IL CC V Input high voltage 0.7V V + 0.3 V IH CC CC Output low voltage I = 3.0 mA 0.4 V OL VOL Output low voltage I = 10 mA 0.4 V (open drain)(3) OL Pull-up supply voltage IRQ/OUT/SQW, F , SCL, SDA 5.5 V (open drain) 32K 1. Valid for ambient operating temperature: T = –40 to 85 °C; V = 2.0 to 5.5 V (except where noted). A CC 2. At 25 °C. 3. For IRQ/FT/OUT, RST, and 32 KHz pins (open drain) T able 11. Crystal electrical characteristics Sym Parameter(1) (2) Min Typ Max Units f Resonant frequency 32.768 kHz O R Series resistance 60 kΩ S C Load capacitance 12.5 pF L 1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. 2. Load capacitors are integrated within the M41T80. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 20/27 Doc ID 9074 Rev 5

M41T80 Package mechanical data 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 9074 Rev 5 21/27

Package mechanical data M41T80 Figure 13. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical drawing h x 45° A2 A c ccc b e 0.25 mm D GAUGE PLANE k 8 E1 E L 1 A1 L1 SO-A 1. Drawing is not to scale. T able 12. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 1.75 0.069 A1 0.10 0.25 0.004 0.010 A2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 D 4.90 4.80 5.00 0.193 0.189 0.197 E 6.00 5.80 6.20 0.236 0.228 0.244 E1 3.90 3.80 4.00 0.154 0.150 0.157 e 1.27 – – 0.050 – – h 0.25 0.50 0.010 0.020 k 0° 8° 0° 8° L 0.40 1.27 0.016 0.050 L1 1.04 0.041 22/27 Doc ID 9074 Rev 5

M41T80 Package mechanical data Figure 14. Carrier tape for SO8 package P0 E D P2 T A0 F TOP COVER TAPE W B0 CENTER LINES P1 OF CAVITY K0 USER DIRECTION OF FEED AM03073v1 Table 13. Carrier tape dimensions for SO8 package Bulk Package W D E P P F A B K P T Unit 0 2 0 0 0 1 qty 1.50 12.00 1.75 4.00 2.00 5.50 6.50 5.30 2.20 8.00 0.30 SO8 +0.10/ mm 2500 ±0.30 ±0.10 ±0.10 ±0.10 ±0.05 ±0.10 ±0.10 ±0.10 ±0.10 ±0.05 –0.00 Doc ID 9074 Rev 5 23/27

Package mechanical data M41T80 Figure 15. Reel schematic T 40mm min. Access hole At slot location B D C N A G measured Tape slot In core for Full radius At hub Tape start 2.5mm min.width AM04928v1 Table 14. Reel dimensions for 12 mm carrier tape - SO8 package (150 mils body width) A B D N T C G (max) (min) (min) (min) (max) 330 mm 13 mm 12.4 mm 1.5 mm 20.2 mm 60 mm 18.4 mm (13-inch) ± 0.2 mm + 2/–0 mm Note: The dimensions given in Table14 incorporate tolerances that cover all variations on critical parameters. 24/27 Doc ID 9074 Rev 5

M41T80 Part numbering 7 Part numbering T able 15. Ordering information scheme Example: M41T 80 M 6 E Device type M41T Supply voltage and write protect voltage 80 = V = 2.0 to 5.5 V CC Package M = SO8 Temperature range 6 = –40 °C to 85 °C Shipping method E = ECOPACK® package, tubes (1) F = ECOPACK® package, tape & reel 1. Shipping in tubes is not recommended for new design. Contact local ST sales office for availability. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Doc ID 9074 Rev 5 25/27

Revision history M41T80 8 Revision history T able 16. Revision history Date Revision Changes Oct-2002 1 First issue Reformatted; add lead-free information; update characteristics (Table7, 15-Jun-2004 2 Table10, Table15) Changed document to new template; added new features in Features on page1; updated package mechanical data in Section6: Package 29-Aug-2006 3 mechanical data; small text changes for entire document, ECOPACK® compliant. Updated Table7, 10, text in Section6; reformatted document, minor 15-Apr-2010 4 textual changes. Added footnote to Table15: Ordering information scheme concerning 03-Aug-2011 5 shipping method; added tape and reel specifications (Figure14, 15, Table13, 14). 26/27 Doc ID 9074 Rev 5

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