M41ST85W 2 3.0/3.3 V I C combination serial RTC, NVRAM supervisor and microprocessor supervisor Features SNAPHAT battery & crystal ■ Automatic battery switchover and WRITE protect for: – Internal serial RTC and – External low power SRAM (LPSRAM) ■ 400 kHz I2C serial interface 28 1 ■ 3.0/3.3 V operating voltage SOH28 – V = 2.7 to 3.6 V CC Embedded crystal ■ Ultralow battery supply current of 500 nA (max) ■ RoHS compliant – Lead-free second level interconnect Serial RTC features SOX28 ■ 400 kHz I2C ■ Power-on reset/low voltage detect ■ 44 bytes of general purpose NVRAM – Open drain reset output ■ Counters for: – Reset voltage, V = 2.60 V (nom) PFD – Seconds, minutes, hours, day, date, month, – Two reset input pins and year – Watchdog can be steered to reset output – Century – Tenths/hundredths of seconds NVRAM supervisor features – Clock calibration register allows ■ Non-volatizes external LPSRAM compensation for crystal variations over – Automatically switches to back-up battery temperature and deselects (write-protects) external ■ Programmable alarm with repeat modes LPSRAM via chip-enable gate – Functions in battery back-up mode – Power-fail deselect (write protect) voltage, ■ Power-down timestamp (HT bit) VPFD = 2.60 V (nom) – Switchover, V = 2.50 V (nom) ■ 2.5 to 5.5 V oscillator operating voltage SO ■ Battery monitor (battery low flag) Microprocessor supervisor features Other features ■ Programmable watchdog – 62.5 ms to 128 s time-out period ■ Programmable squarewave generator (1 Hz to 32 KHz) ■ Early power-fail warning circuit (PFI/PFO) with 1.25 V precision reference ■ –40°C to +85°C operation ■ Package options: – 28-lead SNAPHAT® IC (SOH28) SNAPHAT battery/crystal top to be ordered separately – 28-lead embedded crystal SOIC (SOX28) October 2011 Doc ID 7531 Rev 11 1/43 www.st.com 1

Contents M41ST85W Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 TIMEKEEPER® registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.6 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.8 Reset inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.9 Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.10 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.11 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.12 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.13 t bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 rec 3.14 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2/43 Doc ID 7531

M41ST85W Contents 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Doc ID 7531 3/43

List of tables M41ST85W List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. TIMEKEEPER® register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 3. Alarm repeat modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 4. Square wave output frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5. Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 6. t definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 rec Table 7. Default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 8. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 9. DC and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 12. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 13. Power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 14. SOH28 – 28-lead plastic small outline, battery SNAPHAT®, package mechanical data . . 34 Table 15. 4-pin SNAPHAT® housing for 48 mAh battery & crystal, mechanical data. . . . . . . . . . . . . 35 Table 16. 4-pin SNAPHAT® housing for 120 mAh battery & crystal, mechanical data. . . . . . . . . . . . 36 Table 17. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal, mechanical data . . . 37 Table 18. Carrier tape dimensions for SOH28 and SOX28 packages . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 19. Reel dimensions for 24 mm carrier tape (SOH28 and SOX28 packages) . . . . . . . . . . . . . 39 Table 20. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 21. SNAPHAT® battery/crystal table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 22. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4/43 Doc ID 7531

M41ST85W List of figures List of figures Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. 28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. 28-pin, 300 mil SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Hardware hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. Write cycle timing: RTC & external SRAM control signals . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11. Alternate read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 12. Write mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13. Crystal accuracy across temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14. Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15. Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 16. Backup mode alarm waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 17. RSTIN1 & RSTIN2 timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 18. AC testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 19. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 20. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 21. SOH28 – 28-lead plastic small outline, battery SNAPHAT®, package outline . . . . . . . . . . 34 Figure 22. 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package outline . . . . . . . . . . . . . 35 Figure 23. 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package outline . . . . . . . . . . . . 36 Figure 24. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal, package outline. . . . 37 Figure 25. Carrier tape for SOH28 and SOX28 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 26. Reel schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 27. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Doc ID 7531 5/43

Description M41ST85W 1 Description The M41ST85W is a combination serial real-time clock, microprocessor supervisor, and NVRAM supervisor. It is built in a low-power CMOS SRAM process and has a 64-byte memory space with 44 bytes of NVRAM and 20 memory-mapped RTC registers (see Table2 on page20). The RTC registers are configured in binary coded decimal (BCD) format. The M41ST85W combines a 400 kHz I2C serial RTC with an automatic backup battery switchover circuit for powering an external LPSRAM as well as the internal RTC. When power begins to fail, the switchover automatically connects to the backup battery to keep the RTC and external LPSRAM alive in the absence of system power. Access to the LPSRAM is also cut off via a chip-enable gate function, thereby write-protecting the memory. A programmable watchdog and power-on reset/low voltage detect function are the key elements in the microprocessor supervisor section. The real-time clock includes a built-in 32.768 kHz oscillator (crystal-controlled), which provides the time base for the timekeeping and calendar functions. Eight of the 20 clock registers provide the basic clock/calendar functions while the other 12 bytes provide status/control for the alarm, watchdog, and squarewave functions. RTC addresses and data are transferred serially via the two-line, bidirectional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41ST85W has a built-in power sense circuit which detects power failures and automatically switches to the backup battery when a power failure occurs. During an outage, the power to sustain the SRAM and clock operations is typically supplied by a small lithium button-cell battery as is the case when using the SNAPHAT® package option. Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm interrupts, watchdog timer, and programmable squarewave generator. Other features include a power-on reset as well as two additional debounce reset inputs (RSTIN1 and RSTIN2) which can also generate an output reset (RST). The eight registers for basic clock/calendar functions contain the century, year, month, date, day, hour, minute, second, and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The M41ST85W is offered in two 28-lead SOIC packages. The 300 mil SOH28 SNAPHAT® IC package mates with ST’s SNAPHAT battery/crystal top (ordered separately). SNAPHAT battery options include 48 mAh and 120 mAh. ST’s 300 mil SOX28 embedded crystal IC includes the 32 KHz crystal and is perfect for applications where a low profile is a must. The SOH28 SNAPHAT SOIC includes sockets with gold plated contacts at both ends for direct connection to the SNAPHAT top. The SNAPHAT battery/crystal top is inserted atop the IC package after the completion of the surface mount assembly process which avoids potential battery and crystal damage due to the high temperatures required for device surface-mounting. The unique design allows the battery to be replaced, thus extending the life of the RTC and NVRAM indefinitely. The SNAPHAT top is keyed to prevent reverse insertion. The SNAPHAT IC and SNAPHAT tops are shipped separately. The ICs are available in plastic anti-static tubes or in tape & reel form. The SNAPHAT tops are shipped in plastic anti-static tubes. The part numbers are 6/43 Doc ID 7531 Rev 11

M41ST85W Description M4T28-BR12SH1 (48 mAh) and M4T32-BR12SH1 (120 mAh). For the extended temperature requirement, the 120 mAh M4T32-BR12SH6 is available. For more information, see Table21 on page40. Caution: Do not place the SNAPHAT® battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. The 300 mil SOX embedded crystal SOIC typically requires a user-supplied battery for non- volatile operation. Capacitor backup can also be implemented with this package. Figure 1. Logic diagram (1) VCC VBAT SCL ECON SDA RST EX IRQ/FT/OUT RSTIN1 M41ST85W SQW RSTIN2 PFO WDI VOUT PFI VSS AI03658 1. For 28-pin, 300 mil embedded crystal SOIC only. Doc ID 7531 Rev 11 7/43

Description M41ST85W Table 1. Signal names E Conditioned chip enable output CON EX External chip enable IRQ/FT/OUT Interrupt/frequency test/out output (open drain) PFI Power fail input PFO Power fail output RST Reset output (open drain) RSTIN1 Reset 1 Input RSTIN2 Reset 2 Input SCL Serial clock input SDA Serial data input/output SQW Square wave output WDI Watchdog input V Supply voltage CC V Voltage output OUT V Ground SS V (1) Battery supply voltage BAT NC No connect NF No function 1. For 28-pin, 300 mil embedded crystal SOIC only. Figure 2. 28-pin SOIC connections SQW 1 28 VCC NC 2 27 EX NC 3 26 IRQ/FT/OUT NC 4 25 VOUT NC 5 24 NC NC 6 23 NC NC 7 22 PFI M41ST85W WDI 8 21 NC RSTIN1 9 20 SCL RSTIN2 10 19 NC NC 11 18 RST NC 12 17 NC PFO 13 16 SDA VSS 14 15 ECON AI03659 8/43 Doc ID 7531 Rev 11

M41ST85W Description Figure 3. 28-pin, 300 mil SOIC connections NF 1 28 VCC NF 2 27 EX NF 3 26 IRQ/FT/OUT NF 4 25 VOUT NC 5 24 NC NC 6 23 PFI NC 7 22 SCL M41ST85W SQW 8 21 NC WDI 9 20 NC RSTIN1 10 19 RST RSTIN2 11 18 NC PFO 12 17 SDA NC 13 16 ECON VSS 14 15 VBAT AI06370d Note: No function (NF) pins should be tied to V . Pins 1, 2, 3, and 4 are internally SS shorted together. Doc ID 7531 Rev 11 9/43

Description M41ST85W Figure 4. Block diagram REAL TIME CLOCK CALENDAR SDA 44 BYTES I2C USER RAM INTERFACE RTC w/ALARM AFE SCL & CALIBRATION (1) IRQ/FT/OUT WDS WATCHDOG (2) 32KHz Crystal OSCILLATOR SQUARE WAVE SQW WDI VCC VOUT VBAT BL VBL= 2.5V COMPARE VSO = 2.5V COMPARE VPFD = 2.65V COMPARE POR (1) RSTIN1 RST RSTIN2 EX ECON PFI COMPARE PFO 1.25V (Internal) AI03932 1. Open drain output. 2. Crystal integrated into SOIC package for MX package option. 10/43 Doc ID 7531 Rev 11

M41ST85W Description Figure 5. Hardware hookup Regulator M41ST85W Unregulated Voltage VIN VCC VCC VOUT VCC ECON E EX LPSRAM SCL U C M SDA m Fro WDI RSTIN1 RST To RST RSTIN2 SQW To LED Display Pushbutton R1 Reset PFO To NMI PFI (1) IRQ/FT/OUT To INT R2 VBAT VSS AI03660 1. Required for embedded crystal (MX) package only. Doc ID 7531 Rev 11 11/43

Operating modes M41ST85W 2 Operating modes The M41ST85W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order: 1. Tenths/hundredths of a second register 2. Seconds register 3. Minutes register 4. Century/hours register 5. Day register 6. Date register 7. Month register 8. Year register 9. Control register 10. Watchdog register 11 - 16. Alarm registers 17 - 19. Reserved 20. Square wave register 21 - 64. User RAM The M41ST85W clock continually monitors V for an out-of-tolerance condition. Should CC V fall below V , the device terminates an access in progress and resets the device CC PFD address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. When V falls CC below V , the device automatically switches over to the battery and powers down into an SO ultralow current mode of operation to conserve battery life. As system power returns and V rises above V , the battery is disconnected, and the power supply is switched to CC SO external V . CC Write protection continues until V reaches V (min) plus t (min). CC PFD rec For more information on battery storage life refer to application note AN1012. 2.1 2-wire bus characteristics The bus is intended for communication between different ICs. It consists of two lines: a bi- directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: ● Data transfer may be initiated only when the bus is not busy. ● During data transfer, the data line must remain stable whenever the clock line is high. ● Changes in the data line, while the clock line is high, will be interpreted as control signals. 12/43 Doc ID 7531 Rev 11

M41ST85W Operating modes Accordingly, the following bus conditions have been defined: 2.1.1 Bus not busy Both data and clock lines remain high. 2.1.2 Start data transfer A change in the state of the data line, from high to low, while the clock is high, defines the START condition. 2.1.3 Stop data transfer A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition. 2.1.4 Data valid The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called “master.” The devices that are controlled by the master are called “slaves.” 2.1.5 Acknowledge Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line high to enable the master to generate the STOP condition. Doc ID 7531 Rev 11 13/43

Operating modes M41ST85W Figure 6. Serial bus data transfer sequence DATA LINE STABLE DATA VALID CLOCK DATA START CHANGE OF STOP CONDITION DATA ALLOWED CONDITION AI00587 Figure 7. Acknowledgement sequence CLOCK PULSE FOR START ACKNOWLEDGEMENT SCL FROM 1 2 8 9 MASTER DATA OUTPUT MSB LSB BY TRANSMITTER DATA OUTPUT BY RECEIVER AI00601 Figure 8. Write cycle timing: RTC & external SRAM control signals EX tEXPD tEXPD ECON AI03663 14/43 Doc ID 7531 Rev 11

M41ST85W Operating modes 2.2 Read mode In this mode the master reads the M41ST85W slave after setting the slave address (see Figure9). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter (see Figure10 on page16). The address pointer is only incremented on reception of an acknowledge clock. The M41ST85W slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a stop condition or when the pointer increments to a non-clock or RAM address. Note: This is true both in READ mode and WRITE mode. An alternate READ mode may also be implemented whereby the master reads the M41ST85W slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure11 on page16). Figure 9. Slave address location R/W START SLAVE ADDRESS A B S B M S L 1 1 0 1 0 0 0 AI00602 Doc ID 7531 Rev 11 15/43

Operating modes M41ST85W Figure 10. Read mode sequence T T R R BUS ACTIVITY: A W A W MASTER ST R/ ST R/ WORD SDA LINE S S DATA n DATA n+1 ADDRESS (An) K K K K K BUS ACTIVITY: C C C C C A A A A A SLAVE SLAVE ADDRESS ADDRESS P O T S DATA n+X P AI00899 K C A O N Figure 11. Alternate read mode sequence T R P BMUASS TAECRTIVITY: STA R/W STO SDA LINE S DATA n DATA n+1 DATA n+X P K K K K K BUS ACTIVITY: C C C C C A A A A A O SLAVE N ADDRESS AI00895 16/43 Doc ID 7531 Rev 11

M41ST85W Operating modes 2.3 Write mode In this mode the master transmitter transmits to the M41ST85W slave receiver. Bus protocol is shown in Figure12. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M41ST85W slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte. Figure 12. Write mode sequence T R P BUS ACTIVITY: A W O MASTER ST R/ ST WORD SDA LINE S DATA n DATA n+1 DATA n+X P ADDRESS (An) K K K K K BUS ACTIVITY: C C C C C A A A A A SLAVE ADDRESS AI00591 2.4 Data retention mode With valid V applied, the M41ST85W can be accessed as described above with READ or CC WRITE cycles. Should the supply voltage decay, the M41ST85W will automatically deselect, write protecting itself (and any external SRAM) when V falls between V (max) and CC PFD V (min). This is accomplished by internally inhibiting access to the clock registers. At this PFD time, the reset pin (RST) is driven active and will remain active until V returns to nominal CC levels. External RAM access is inhibited in a similar manner by forcing E to a high level. CON This level is within 0.2 volts of the V . E will remain at this level as long as V BAT CON CC remains at an out-of-tolerance condition. When V falls below the battery backup CC switchover voltage (V ), power input is switched from the V pin to the SNAPHAT® SO CC battery, and the clock registers and external SRAM are maintained from the attached battery supply. All outputs become high impedance. The V pin is capable of supplying 100 µA of current OUT to the attached memory with less than 0.3 volts drop under this condition. On power-up, when V returns to a nominal value, write protection continues for t by inhibiting E . CC rec CON The RST signal also remains active during this time (see Figure20 on page33). Note: Most low power SRAMs on the market today can be used with the M41ST85W RTC SUPERVISOR. There are, however some criteria which should be used in making the final choice of an SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M41ST85W and SRAMs to be “Don’t Care” once V falls below V (min). The SRAM should also CC PFD guarantee data retention down to V = 2.0 volts. The chip enable access time must be CC sufficient to meet the system needs with the chip enable output propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to V . OUT Doc ID 7531 Rev 11 17/43

Operating modes M41ST85W If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0 volts. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the I value of BAT the M41ST85W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT® top of your choice can then be divided by this current to determine the amount of data retention available (see Table21 on page40). For a further more detailed review of lifetime calculations, please see application note AN1012. 18/43 Doc ID 7531 Rev 11

M41ST85W Clock operation 3 Clock operation The eight byte clock register (see Table2 on page20) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Note: A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to “00,” and tenths/hundredths of seconds cannot be written to any value other than “00.” Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month and years. The ninth clock register is the control register (this is described in the clock calibration section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. The eight clock registers may be read one byte at a time, or in a sequential block. The control register (address location 08h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ. 3.1 Power-down time-stamp When a power failure occurs, the halt update bit (HT) will automatically be set to a '1.' This will prevent the clock from updating the TIMEKEEPER® registers, and will allow the user to read the exact time of the power-down event. Resetting the HT bit to a '0' will allow the clock to update the TIMEKEEPER registers with the current time. For more information, see application note AN1572. ® 3.2 TIMEKEEPER registers The M41ST85W offers 20 internal registers which contain clock, alarm, watchdog, flag, square wave and control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT™ TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a stop condition or when the pointer increments to a non-clock or RAM address. TIMEKEEPER and alarm registers store data in BCD. control, watchdog and square wave registers store data in binary format. Doc ID 7531 Rev 11 19/43

Clock operation M41ST85W Table 2. TIMEKEEPER® register map Data Function/range Address D7 D6 D5 D4 D3 D2 D1 D0 BCD format 00h 0.1 seconds 0.01 seconds Seconds 00-99 01h ST 10 seconds Seconds Seconds 00-59 02h 0 10 minutes Minutes Minutes 00-59 03h CEB CB 10 hours Hours (24-hour format) Century/hours 0-1/00-23 04h TR 0 0 0 0 Day of week Day 01-7 05h 0 0 10 date Date: day of month Date 01-31 06h 0 0 0 10M Month Month 01-12 07h 10 years Year Year 00-99 08h OUT FT S Calibration Control 09h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog 0Ah AFE SQWE ABE Al 10M Alarm month Al month 01-12 0Bh RPT4 RPT5 AI 10 date Alarm date Al date 01-31 0Ch RPT3 HT AI 10 hour Alarm hour Al hour 00-23 0Dh RPT2 Alarm 10 minutes Alarm minutes Al min 00-59 0Eh RPT1 Alarm 10 seconds Alarm seconds Al sec 00-59 0Fh WDF AF 0 BL 0 0 0 0 Flags 10h 0 0 0 0 0 0 0 0 Reserved 11h 0 0 0 0 0 0 0 0 Reserved 12h 0 0 0 0 0 0 0 0 Reserved 13h RS3 RS2 RS1 RS0 0 0 0 0 SQW Keys: S = Sign bit RB0-RB1 = Watchdog resolution bits FT = Frequency test bit WDS = Watchdog steering bit ST = Stop bit ABE = Alarm in battery backup mode enable bit 0 = Must be set to zero RPT1-RPT5 = Alarm repeat mode bits BL = Battery low flag (read only) WDF = Watchdog flag (read only) BMB0-BMB4 = Watchdog multiplier bits AF = Alarm flag (read only) CEB = Century enable bit SQWE = Square wave enable CB = Century bit RS0-RS3 = SQW frequency OUT = Output level HT = Halt update bit AFE = Alarm flag enable flag TR = t bit rec 20/43 Doc ID 7531 Rev 11

M41ST85W Clock operation 3.3 Calibrating the clock The M41ST85W is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed +/–35 ppm (parts per million) oscillator frequency error at 25oC, which equates to about +/–1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25°C. The oscillation rate of crystals changes with temperature (see Figure13 on page22). Therefore, the M41ST85W design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure14 on page22. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the control register (08h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41ST85W may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in application note AN934, “TIMEKEEPER® calibration.” This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT/OUT pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of 01h) is '0,' the frequency test bit (FT, D6 of 08h) is '1,' the alarm flag enable bit (AFE, D7 of 0Ah) is '0,' and the watchdog steering bit (WDS, D7 of 09h) is '1' or the watchdog register (09h = 0) is reset. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test output frequency. The IRQ/FT/OUT pin is an open drain output which requires a pull-up resistor to V for CC proper operation. A 500 to 10 k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down. Doc ID 7531 Rev 11 21/43

Clock operation M41ST85W Figure 13. Crystal accuracy across temperature Frequency (ppm) 20 0 –20 –40 –60 ΔF= K x (T – T )2 –80 F O K = –0.036 ppm/°C2 ± 0.006 ppm/°C2 –100 T = 25°C ± 5°C –120 O –140 –160 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 Temperature °C AI07888 Figure 14. Calibration waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B 22/43 Doc ID 7531 Rev 11

M41ST85W Clock operation 3.4 Setting alarm clock registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M41ST85W is in the battery backup to serve as a system wake-up call. Bits RPT5–RPT1 put the alarm in the repeat mode of operation. Table3 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5–RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the alarm condition activates the IRQ/FT/OUT pin as shown in Figure15. To disable alarm, write '0' to the alarm date register and to RPT5–RPT1. Note: If the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the “Alarm Seconds,” the address pointer will increment to the flag address, causing this situation to occur. The IRQ/FT/OUT output is cleared by a READ to the flags register. A subsequent READ of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' The IRQ/FT/OUT pin can also be activated in the battery backup mode. The IRQ/FT/OUT will go low if an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the flag register at system boot-up to determine if an alarm was generated while the M41ST85W was in the deselect mode during power-up. Figure16 on page24 illustrates the backup mode alarm timing. Figure 15. Alarm interrupt reset waveform 0Eh 0Fh 10h ACTIVE FLAG IRQ/FT/OUT HIGH-Z AI03664 Table 3. Alarm repeat modes RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting 1 1 1 1 1 Once per second 1 1 1 1 0 Once per minute 1 1 1 0 0 Once per hour 1 1 0 0 0 Once per day 1 0 0 0 0 Once per month 0 0 0 0 0 Once per year Doc ID 7531 Rev 11 23/43

Clock operation M41ST85W Figure 16. Backup mode alarm waveform VCC VPFD VSO trec ABE, AFE Bits in Interrupt Register AF bit in Flags Register IRQ/FT/OUT HIGH-Z HIGH-Z AI03920 3.5 Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1 or 3 seconds). Note: The accuracy of the timer is within ± the selected resolution. If the processor does not reset the timer within the specified period, the M41ST85W sets the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset. The most significant bit of the watchdog register is the watchdog steering bit (WDS). When set to a '0,' the watchdog will activate the IRQ/FT/OUT pin when timed-out. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for t . The watchdog rec register, FT, AFE, ABE and SQWE bits will reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1.' The watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI) or 2) the microprocessor can perform a WRITE of the watchdog register. The time-out period then starts over. Note: The WDI pin should be tied to V if not used. SS In order to perform a software reset of the watchdog timer, the original time-out period can be written into the watchdog register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT/OUT 24/43 Doc ID 7531 Rev 11

M41ST85W Clock operation pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh). The watchdog function is automatically disabled upon power-up and the watchdog register is cleared. If the watchdog function is set to output to the IRQ/FT/OUT pin and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied. 3.6 Square wave output The M41ST85W offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table4. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah. Table 4. Square wave output frequency Square wave bits Square wave RS3 RS2 RS1 RS0 Frequency Units 0 0 0 0 None – 0 0 0 1 32.768 kHz 0 0 1 0 8.192 kHz 0 0 1 1 4.096 kHz 0 1 0 0 2.048 kHz 0 1 0 1 1.024 kHz 0 1 1 0 512 Hz 0 1 1 1 256 Hz 1 0 0 0 128 Hz 1 0 0 1 64 Hz 1 0 1 0 32 Hz 1 0 1 1 16 Hz 1 1 0 0 8 Hz 1 1 0 1 4 Hz 1 1 1 0 2 Hz 1 1 1 1 1 Hz 3.7 Power-on reset The M41ST85W continuously monitors V . When V falls to the power fail detect trip CC CC point, the RST pulls low (open drain) and remains low on power-up for t after V passes rec CC V (max). The RST pin is an open drain output and an appropriate pull-up resistor should PFD be chosen to control rise time. Doc ID 7531 Rev 11 25/43

Clock operation M41ST85W 3.8 Reset inputs (RSTIN1 & RSTIN2) The M41ST85W provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle. Table5 and Figure17 illustrate the AC reset characteristics of this function. Pulses shorter than t and t will not generate a reset condition. RSTIN1 and RSTIN2 are each RLRH1 RLRH2 internally pulled up to V through a 100 kΩ resistor. CC Figure 17. RSTIN1 & RSTIN2 timing waveforms RSTIN1 tRLRH1 RSTIN2 tRLRH2 RST (1) tR1HRH tR2HRH AI03665 Note: With pull-up resistor Table 5. Reset AC characteristics Symbol Parameter(1) Min Max Unit t (2) RSTIN1 low to RSTIN1 high 200 ns RLRH1 t (3) RSTIN2 low to RSTIN2 high 100 ms RLRH2 t (4) RSTIN1 high to RST high 40 200 ms R1HRH t (4) RSTIN2 high to RST high 40 200 ms R2HRH 1. Valid for ambient operating temperature: T = –40 to 85°C; V = 2.7 to 3.6 V (except where noted). A CC 2. Pulse width less than 50 ns will result in no RESET (for noise immunity). 3. Pulse width less than 20 ms will result in no RESET (for noise immunity). 4. Programmable (see Table6 on page28). 3.9 Power-fail input/output The power-fail input (PFI) is compared to an internal reference voltage (1.25 V). If PFI is less than the power-fail threshold (V ), the power-fail output (PFO) will go low. This function is PFI intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure5 on page11) to either the unregulated DC input (if it is available) or the regulated output of the V regulator. The CC voltage divider can be set up such that the voltage at PFI falls below V several PFI milliseconds before the regulated V input to the M41ST85W or the microprocessor drops CC below the minimum operating voltage. During battery backup, the power-fail comparator turns off and PFO goes (or remains) low. This occurs after V drops below V (min). When power returns, PFO is forced high, CC PFD irrespective of V for the write protect time (t ), which is the time from V (max) until the PFI rec PFD inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO 26/43 Doc ID 7531 Rev 11

M41ST85W Clock operation follows PFI. If the comparator is unused, PFI should be connected to V and PFO left SS unconnected. 3.10 Century bit Bits D7 and D6 of clock register 03h contain the Century Enable bit (CEB) and the Century bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. 3.11 Output driver pin When the FT bit, AFE bit and watchdog register are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of the control register. In other words, when D7 (OUT bit) and D6 (FT bit) of address location 08h are a '0,' then the IRQ/FT/OUT pin will be driven low. Note: The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor. 3.12 Battery low warning The M41ST85W automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal V is supplied. In order to insure data integrity during subsequent periods of CC battery backup mode, the battery should be replaced. The SNAPHAT® top may be replaced while V is applied to the device. CC Note: This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is disconnected. The M41ST85W only monitors the battery when a nominal V is applied to the device. CC Thus applications which require extensive durations in the battery backup mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. Doc ID 7531 Rev 11 27/43

Clock operation M41ST85W 3.13 t bit rec Bit D7 of clock register 04h contains the t bit (TR). t refers to the automatic rec rec continuation of the deselect time after V reaches V . This allows for a voltage settling CC PFD time before WRITEs may again be performed to the device after a power-down condition. The t bit will allow the user to set the length of this deselect time as defined by Table6. rec 3.14 Initial power-on defaults Upon initial application of power to the device, the following register bits are set to a '0' state: watchdog register, FT, AFE, ABE, SQWE, and TR. The following bits are set to a '1' state: ST, OUT, and HT (see Table7). Table 6. t definitions rec t time rec t bit (TR) STOP bit (ST) Units rec Min Max 0 0 96 98 ms 0 1 40 200(1) ms 1 X 50 2000 µs 1. Default setting Table 7. Default values Watchdog Condition TR ST HT Out FT AFE ABE SQWE register(1) Initial power-up(2) 0 1 1 1 0 0 0 0 0 Subsequent power-up UC UC 1 UC 0 0 0 0 0 (with battery backup)(3) 1. WDS, BMB0-BMB4, RB0, RB1. 2. State of other control bits undefined. 3. UC = Unchanged 28/43 Doc ID 7531 Rev 11

M41ST85W Maximum ratings 4 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 8. Absolute maximum ratings Symbol Parameter Value Unit Storage temperature (V off, oscillator SNAPHAT® –40 to 85 °C T CC STG off) SOIC –55 to 150 °C SOH28(1) 260 °C T Lead solder temperature for 10 seconds SLD SOX28(2) 240 °C V Input or output voltage –0.3 to V +0.3 V IO CC V Supply voltage –0.3 to 4.6 V CC I Output current 20 mA O P Power dissipation 1 W D 1. For SOH28 package, lead-free (pb-free) lead finish: reflow at peak temperature of 260°C (the time above 255°C must not exceed 30 seconds). 2. The SOX28 package has lead-free (pb-free) lead finish, but cannot be exposed to peak reflow temperature in excess of 240°C. Reflow at peak temperature of 240°C (the time above 235°C must not exceed 20 seconds). Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode. Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. Doc ID 7531 Rev 11 29/43

DC and AC parameters M41ST85W 5 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 9. DC and AC measurement conditions Parameter M41ST85W V supply voltage 2.7 to 3.6 V CC Ambient operating temperature –40 to 85°C Load capacitance (C ) 50 pF L Input rise and fall times ≤ 50 ns Input pulse voltages 0.2 to 0.8V CC Input and output timing ref. voltages 0.3 to 0.7V CC Note: Output High Z is defined as the point where data is no longer driven. Figure 18. AC testing input/output waveforms 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI02568 Table 10. Capacitance Symbol Parameter(1)(2) Min Max Unit C Input capacitance 7 pF IN C (3) Output capacitance 10 pF OUT t Low-pass filter input time constant (SDA and SCL) 50 ns LP 1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested. 2. At 25°C, f = 1 MHz. 3. Outputs are deselected. 30/43 Doc ID 7531 Rev 11

M41ST85W DC and AC parameters Table 11. DC characteristics M41ST85W Sym Parameter Test condition(1) Unit Min Typ Max Battery current OSC ON 400 500 nA I (2) T = 25°C, V = 0 V, V = 3 V BAT A CC BAT Battery current OSC OFF 50 nA I Supply current f = 400 kHz 0.75 mA CC1 SCL, SDA = V – 0.3 V I Supply current (standby) CC 0.50 mA CC2 or V + 0.3 V SS Input leakage current 0V ≤ V ≤ V ±1 µA I (3) IN CC LI Input leakage current (PFI) –25 2 25 nA I (4) Output leakage current 0V ≤ V ≤ V ±1 µA LO IN CC I (5) V current (active) V > V – 0.3 V 100 mA OUT1 OUT OUT1 CC I V current (battery backup) V > V – 0.3 V 100 µA OUT2 OUT OUT2 BAT V Input high voltage 0.7V V + 0.3 V IH CC CC V Input low voltage –0.3 0.3V V IL CC V Battery voltage 2.5 3.0 3.5(6) V BAT V Output high voltage(7) I = –1.0 mA 2.4 V OH OH Pull-up supply voltage (open drain) RST, IRQ/FT/OUT 3.6 V V (8) V (battery backup) I = –1.0 µA 2.5 2.9 3.5 V OHB OH OUT2 Output low voltage I = 3.0 mA 0.4 V OL V OL Output low voltage (open drain)(9) I = 10 mA 0.4 V OL V Power fail deselect 2.55 2.60 2.70 V PFD PFI input threshold V = 3 V(W) 1.225 1.250 1.275 V CC V PFI PFI hysteresis PFI rising 20 70 mV V Battery backup switchover 2.5 V SO 1. Valid for ambient operating temperature: T = –40 to 85°C; V = 2.7 to 3.6 V (except where noted). A CC 2. Measured with V and E open. OUT CON 3. RSTIN1 and RSTIN2 internally pulled-up to V through 100 kΩ resistor. WDI internally pulled-down to V through CC SS 100 kΩ resistor. 4. Outputs deselected. 5. External SRAM must match RTC supervisor chip V specification. CC 6. For rechargeable backup, V (max) may be considered V . BAT CC 7. For PFO and SQW pins (CMOS). 8. Conditioned output (E ) can only sustain CMOS leakage current in the battery backup mode. Higher leakage currents CON will reduce battery life. 9. For IRQ/FT/OUT, RST pins (open drain): if pulled-up to supply other than V , this supply must be equal to, or less than CC 3.0 V when V = 0 V (during battery backup mode). CC Doc ID 7531 Rev 11 31/43

DC and AC parameters M41ST85W Figure 19. Bus timing requirements sequence SDA tBUF tHD:STA tHD:STA tR tF SCL tHIGH tSU:DAT tSU:STA tSU:STO P S tLOW tHD:DAT SR P AI00589 Table 12. AC characteristics Symbol Parameter(1) Min Max Unit f SCL clock frequency 0 400 kHz SCL t Time the bus must be free before a new transmission can start 1.3 µs BUF t EX to E propagation delay 15 ns EXPD CON t SDA and SCL fall time 300 ns F t (2) Data hold time 0 µs HD:DAT t START condition hold time (after this period the first clock pulse is generated) 600 ns HD:STA t Clock high period 600 ns HIGH t Clock low period 1.3 µs LOW t SDA and SCL rise time 300 ns R t Data setup time 100 ns SU:DAT t START condition setup time (only relevant for a repeated start condition) 600 ns SU:STA t STOP condition setup time 600 ns SU:STO 1. Valid for ambient operating temperature: T = –40 to 85°C; V = 2.7 to 3.6 V (except where otherwise noted). A CC 2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL. 32/43 Doc ID 7531 Rev 11

M41ST85W DC and AC parameters Figure 20. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO tF tR tFB tRB tPD tDR trec PFO INPUTS RECOGNIZED DON'T CARE RECOGNIZED RST HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) ECON AI03661 Table 13. Power down/up AC characteristics Symbol Parameter(1) Min Typ Max Unit t (2) V (max) to V (min) V fall time 300 µs F PFD PFD CC t (3) V (min) to V V fall time 10 µs FB PFD SS CC t EX at V before power down 0 µs PD IH t PFI to PFO propagation delay 15 25 µs PFD t V (min) to V (max) V rise time 10 µs R PFD PFD CC t V to V (min) V rise time 1 µs RB SS PFD CC t (4) Power-up deselect time 40 200 ms rec 1. Valid for ambient operating temperature: T = –40 to 85°C; V = 2.7 to 3.6 V (except where otherwise noted). A CC 2. V (max) to V (min) fall time of less than t may result in deselection/write protection not occurring until PFD PFD F 200 µs after V passes V (min). CC PFD 3. V (min) to V fall time of less than t may cause corruption of RAM data. PFD SS FB 4. Programmable (see Table6 on page28) Doc ID 7531 Rev 11 33/43

Package mechanical data M41ST85W 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 21. SOH28 – 28-lead plastic small outline, battery SNAPHAT®, package outline A2 A C B e eB CP D N E H A1 α L 1 SOH-A Note: Drawing is not to scale. Table 14. S OH28 – 28-lead plastic small outline, battery SNAPHAT®, package mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 3.05 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 e 1.27 – – 0.050 – – eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 a 0° 8° 0° 8° N 28 28 CP 0.10 0.004 34/43 Doc ID 7531 Rev 11

M41ST85W Package mechanical data Figure 22. 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package outline A2 A1 A A3 eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 15. 4-pin SNAPHAT® housing for 48 mAh battery & crystal, mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 9.78 0.3850 A1 6.73 7.24 0.2650 0.2850 A2 6.48 6.99 0.2551 0.2752 A3 0.38 0.0150 B 0.46 0.56 0.0181 0.0220 D 21.21 21.84 0.8350 0.8598 E 14.22 14.99 0.5598 0.5902 eA 15.55 15.95 0.6122 0.6280 eB 3.20 3.61 0.1260 0.1421 L 2.03 2.29 0.0799 0.0902 Doc ID 7531 Rev 11 35/43

Package mechanical data M41ST85W Figure 23. 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package outline A2 A1 A A3 eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 16. 4-pin SNAPHAT® housing for 120 mAh battery & crystal, mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 10.54 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 36/43 Doc ID 7531 Rev 11

M41ST85W Package mechanical data Figure 24. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal, package outline D 14 1 h x 45° C E H 15 28 A2 A ddd B e A1 A1 α L SO-E Note: Drawing is not to scale. Table 17. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal, mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 2.44 2.69 0.096 0.106 A1 0.15 0.31 0.006 0.012 A2 2.29 2.39 0.090 0.094 B 0.41 0.51 0.016 0.020 C 0.20 0.31 0.008 0.012 D 17.91 18.01 0.705 0.709 ddd 0.10 0.004 E 7.57 7.67 0.298 0.302 e 1.27 – – 0.050 – – H 10.16 10.52 0.400 0.414 L 0.51 0.81 0.020 0.032 a 0° 8° 0° 8° N 28 28 Doc ID 7531 Rev 11 37/43

Package mechanical data M41ST85W Figure 25. Carrier tape for SOH28 and SOX28 package P0 E D P2 T A0 F TOP COVER TAPE W B0 CENTER LINES P1 OF CAVITY K0 USER DIRECTION OF FEED AM03073v1 Table 18. Carrier tape dimensions for SOH28 and SOX28 packages Bulk Package W D E P P F A B K P T Unit 0 2 0 0 0 1 Qty 1.50 24.00 1.75 4.00 2.00 11.50 12.90 18.70 3.20 16.00 0.30 SOH28 +0.10/ mm 936 ±0.30 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.05 –0.00 1.50 24.00 1.75 4.00 2.00 11.50 12.70 18.20 3.20 16.00 0.30 SOX28 +0.10/ mm 1000 ±0.30 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.05 –0.00 38/43 Doc ID 7531 Rev 11

M41ST85W Package mechanical data Figure 26. Reel schematic T 40mm min. Access hole At slot location B D C N A G measured Tape slot In core for Full radius At hub Tape start 2.5mm min.width AM04928v1 Table 19. Reel dimensions for 24 mm carrier tape (SOH28 and SOX28 packages) A B D N T Carrier tape C G (max) (min) (min) (min) (max) 24 mm 330 mm 13 mm 24.4 mm 1.5 mm 20.2 mm 60 mm 30.4 mm (SOH28, SOX28) (13-inch) ± 0.2 mm + 2/–0 mm Note: The dimensions given in Table19 incorporate tolerances that cover all variations on critical parameters. Doc ID 7531 Rev 11 39/43

Part numbering M41ST85W 7 Part numbering Table 20. Ordering information scheme Example: M41ST 85W MH 6 E Device type M41ST Supply voltage and write protect voltage 85W = V = 2.7 to 3.6 V; 2.55V ≤ V ≤ 2.70 V CC PFD Package MH(1) = SOH28 MX(2) = SOX28 Temperature range 6 = –40 to 85°C Shipping method For SOH28: E = ECOPACK® package, tubes(3) ® F = ECOPACK package, tape & reel For SOX28: Blank = ECOPACK® package, tubes(3) ® TR = ECOPACK package, tape & reel 1. The 28-pin SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered separately under the part number “M4TXX-BR12SHx” in plastic tube (see Table21). 2. The SOX28 package includes an embedded 32,768 Hz crystal. 3. Not recommended for new design. Contact local ST sales office for availability. Caution: Do not place the SNAPHAT® battery package “M4Txx-BR12SH” in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Table 21. SNAPHAT® battery/crystal table Part number Description Package ® M4T28-BR12SH Lithium battery (48 mAh) and crystal SNAPHAT top SH ® M4T32-BR12SH Lithium battery (120 mAh) and crystal SNAPHAT top SH 40/43 Doc ID 7531 Rev 11

M41ST85W Environmental information 8 Environmental information Figure 27. Recycling symbols This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Doc ID 7531 Rev 11 41/43

Revision history M41ST85W 9 Revision history Table 22. Document revision history Date Revision Changes Aug-2000 1 First issue 24-Aug-2000 1.1 Block diagram added (Figure4) 12-Oct-2000 1.2 t table removed, cross references corrected rec 18-Dec-2000 2 Reformatted, TOC added, and PFI input leakage current added (Table11) Addition of t information, table changed, one added (Table2, 6); changed PFI/PFO rec graphic (see Figure4); change to DC and AC characteristics, order information 18-Jun-2001 2.1 (Table11, 12, 20); note added to “Setting Alarm Clock Registers” section; added temp./voltage info. to tables (Table10, 11, 6, 12, 13); addition of default values (Table7) 22-Jun-2001 2.2 Note added to clock operation section 26-Jul-2001 3 Change in product maturity 07-Aug-2001 3.1 Improve text in “Setting the Alarm Clock” section 20-Aug-2001 3.2 Change V values in document PFD DC characteristics V changed; V changed; PFI hysteresis (PFI Rising) spec. 06-Sep-2001 3.3 BAT OHB added; and crystal electrical characteristics table removed (Table11, 6) Changed READ/WRITE mode sequences (Figure10, 12); change in V lower limit 03-Dec-2001 3.4 PFD for 5V (M41ST85Y) part only (Table11, 20) 01-May-2002 3.5 Change t definition (Table6); modify reflow time and temperature footnote (Table8) rec 03-Jul-2002 3.6 Modify DC characteristics table footnote, default values (Table11, 7) Added embedded crystal (MX) package option; corrected initial power-up condition 15-Nov-2002 3.7 (cover page, Figure1, 3, 4, 5, 24, Table1, 7, 20, ) 24-Jan-2003 3.8 Update diagrams (Figure4, 5, 24); update values (Table13, 5, 6, 7, ) 25-Feb20-03 4 New Si changes (Table13, 5, 6); corrected dimensions (Figure24; Table) Reformatted; correct dimensions; update Lead-free information (Figure20, 13, 16; 20-May-2004 5 Table8, 16, 20) 15-Jun-2004 6 Update characteristics; add package shipping (Figure3; Table1, 11, 20) 13-Sep-2004 7 Update maximum ratings (Table8) Updated template, Lead-free text, removed 5V references (Figure1, 2, 3, 4, 5; Table5, 10-Jan-2006 8 8, 9, 11, 12, 13, 20, 21) Reformatted document, minor textual changes; added lead-free second level 03-Oct-2007 9 interconnect information to cover page and Section6: Package mechanical data; updated Table8. Added Section8: Environmental information; updated Table8, Section6: Package 16-Dec-2008 10 mechanical data; minor reformatting. Updated Table20: Ordering information scheme as shipping in tubes is not 03-Oct-2011 11 recommended for new design; updated Section8: Environmental information; added Figure25, 26 and Table18, 19. 42/43 Doc ID 7531 Rev 11

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