To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry.

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Under development This document is under development and its contents are subject to change M16C/6N Group (M16C/6NK, M16C/6NM) REJ03B0058-0210 Renesas MCU Rev.2.10 Aug 25, 2006 1. Overview The M16C/6N Group (M16C/6NK, M16C/6NM) of MCUs are built using the high-performance silicon gate CMOS process using the M16C/60 Series CPU core and are packaged in 100-pin and 128-pin plastic molded LQFP. These MCUs operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Being equipped with two CAN (Controller Area Network) modules in the M16C/6N Group (M16C/6NK, M16C/6NM), the MCU is suited to drive automotive and industrial control systems. The CAN modules comply with the 2.0B specification. In addition, this MCU contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication equipment which requires high-speed arithmetic/logic operations. 1.1 Applications • Car audio and industrial control systems, other (Normal-ver. product) • Automotive, industrial control systems and other automobile, other (T/V-ver. product) Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition. Rev.2.10 Aug 25, 2006 page 1 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.2 Performance Overview Tables 1.1 and 1.2 list the Functions and Specifications for M16C/6N Group (M16C/6NK, M16C/6NM). Table 1.1 Functions and Specifications for M16C/6N Group (100-pin Version: M16C/6NK) Specification Item Normal-ver. T/V-ver. CPU Number of fundamental 91 instructions instructions Minimum instruction 41.7 ns (f(BCLK) = 24 MHz, 50.0 ns (f(BCLK) = 20 MHz, execution time 1/1 prescaler, without software wait) 1/1 prescaler, without software wait) Operating mode Single-chip, memory expansion, Single-chip mode and microprocessor modes Address space 1 Mbyte Memory capacity Refer to Table 1.3 Product Information Peripheral Ports Input/Output: 87 pins, Input: 1 pin Function Multifunction timers Timer A: 16 bits ✕ 5 channels Timer B: 16 bits ✕ 6 channels Three-phase motor control circuit Serial interfaces 3 channels Clock synchronous, UART, I2C-bus (1), IEBus (2) 2 channels Clock synchronous A/D converter 10-bit A/D converter: 1 circuit, 26 channels D/A converter 8 bits ✕ 2 channels DMAC 2 channels CRC calculation circuit CRC-CCITT CAN module 2 channels with 2.0B specification Watchdog timer 15 bits ✕ 1 channel (with prescaler) Interrupts Internal: 32 sources, External: 9 sources Software: 4 sources, Priority levels: 7 levels Clock generation circuits 4 circuits • Main clock oscillation circuit (*) • Sub clock oscillation circuit (*) • On-chip oscillator • PLL frequency synthesizer (*) Equipped with on-chip feedback resistor Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function Electrical Supply voltage VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz, Characteristics 1/1 prescaler, without software wait) 1/1 prescaler, without software wait) Consumption Mask ROM 21 mA (f(BCLK) = 24 MHz, - current PLL operation, no division) Flash memory 23 mA (f(BCLK) = 24 MHz, 21 mA (f(BCLK) = 20 MHz, PLL operation, no division) PLL operation, no division) Mask ROM 3 µA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low) Flash memory 0.8 µA (Stop mode, Topr = 25°C) Flash Memory Programming and erasure voltage 3.0 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V Version Programming and erasure endurance 100 times I/O I/O withstand voltage 5.0 V Characteristics Output current 5 mA Operating Ambient Temperature -40 to 85°C T version: -40 to 85°C V version: -40 to 125°C (option) Device Configuration CMOS high-performance silicon gate Package 100-pin molded-plastic LQFP NOTES: 1. I2C-bus is a trademark of Koninklijke Philips Electronics N.V. 2. IEBus is a trademark of NEC Electronics Corporation. option: All options are on request basis. Rev.2.10 Aug 25, 2006 page 2 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.2 Functions and Specifications for M16C/6N Group (128-pin Version: M16C/6NM) Specification Item Normal-ver. T/V-ver. CPU Number of fundamental 91 instructions instructions Minimum instruction 41.7 ns (f(BCLK) = 24 MHz, 50.0 ns (f(BCLK) = 20 MHz, execution time 1/1 prescaler, without software wait) 1/1 prescaler, without software wait) Operating mode Single-chip, memory expansion, Single-chip mode and microprocessor modes Address space 1 Mbyte Memory capacity Refer to Table 1.3 Product Information Peripheral Ports Input/Output: 113 pins, Input: 1 pin Function Multifunction timers Timer A: 16 bits ✕ 5 channels Timer B: 16 bits ✕ 6 channels Three-phase motor control circuit Serial interfaces 3 channels Clock synchronous, UART, I2C-bus (1), IEBus (2) 4 channels Clock synchronous A/D converter 10-bit A/D converter: 1 circuit, 26 channels D/A converter 8 bits ✕ 2 channels DMAC 2 channels CRC calculation circuit CRC-CCITT CAN module 2 channels with 2.0B specification Watchdog timer 15 bits ✕ 1 channel (with prescaler) Interrupts Internal: 34 sources, External: 12 sources Software: 4 sources, Priority levels: 7 levels Clock generation circuits 4 circuits • Main clock oscillation circuit (*) • Sub clock oscillation circuit (*) • On-chip oscillator • PLL frequency synthesizer (*) Equipped with on-chip feedback resistor Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function Electrical Supply voltage VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz, Characteristics 1/1 prescaler, without software wait) 1/1 prescaler, without software wait) Consumption Mask ROM 21 mA (f(BCLK) = 24 MHz, - current PLL operation, no division) Flash memory 23 mA (f(BCLK) = 24 MHz, 21 mA (f(BCLK) = 20 MHz, PLL operation, no division) PLL operation, no division) Mask ROM 3 µA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low) Flash memory 0.8 µA (Stop mode, Topr = 25°C) Flash Memory Programming and erasure voltage 3.0 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V Version Programming and erasure endurance 100 times I/O I/O withstand voltage 5.0 V Characteristics Output current 5 mA Operating Ambient Temperature -40 to 85°C T version: -40 to 85°C V version: -40 to 125°C (option) Device Configuration CMOS high-performance silicon gate Package 128-pin molded-plastic LQFP NOTES: 1. I2C-bus is a trademark of Koninklijke Philips Electronics N.V. 2. IEBus is a trademark of NEC Electronics Corporation. option: All options are on request basis. Rev.2.10 Aug 25, 2006 page 3 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.3 Block Diagram Figure 1.1 shows a Block Diagram. 8 8 8 8 8 8 8 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 P o Internal peripheral functions A/D converter System clock generation circuit Prt 8 (10 bits ✕ 8 channels XIN-XOUT 7 Expandable up to 26 channels) XCIN-XCOUT Timer (16 bits) PLL Ofrenq-cuheinpc oys scyilnlathtoersizer P UART or o Output (timer A): 5 Clock synchronous serial I/O Clock synchronous serial I/O Prt 7 Input (timer B): 6 (3 channels) (8 bits ✕ 4 channels) (4) 8 Three-phase motor CRC calculation circuit (CCITT) CAN module P control circuit (Polynomial: X16+X12+X5+1) (2 channels) Port 8 _ Watchdog timer M16C/60 Series CPU core Memory 5 (15 bits) R0H R0L SB ROM (1) P (2 cDhManAnCels) R1HRR23 R1L UISSPP RAM (2) P9ort 8 INTB A0 A1 PC P D/A converter Multiplier o (8 bits ✕ 2 channels) FB FLG Prt 1 8 0 Port P14 Port P13 Port P12 Port P11 (3) (3) (3) (3) NOTES: 1: ROM size depends on MCU type. 2 8 8 8 2: RAM size depends on MCU type. 3: Ports P11 to P14 are only in the 128-pin version. 4: 8 bits ✕ 2 channels in the 100-pin version. Figure 1.1 Block Diagram Rev.2.10 Aug 25, 2006 page 4 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.4 Product Information Table 1.3 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages. Table 1.3 Product Information As of Aug. 2006 Type No. ROM Capacity RAM Capacity Package Type (2) Remarks M306NKFHGP 384 K + 4 Kbytes 31 Kbytes PLQP0100KB-A Flash Normal-ver. M306NMFHGP PLQP0128KB-A memory M306NKFJGP 512 K + 4 Kbytes 31 Kbytes PLQP0100KB-A version (1) M306NMFJGP PLQP0128KB-A M306NKFHTGP (D) 384 K + 4 Kbytes 31 Kbytes PLQP0100KB-A T-ver. M306NMFHTGP (D) PLQP0128KB-A M306NKFJTGP 512 K + 4 Kbytes 31 Kbytes PLQP0100KB-A M306NMFJTGP PLQP0128KB-A M306NKFHVGP (D) 384 K + 4 Kbytes 31 Kbytes PLQP0100KB-A V-ver. M306NMFHVGP (D) PLQP0128KB-A M306NKFJVGP (D) 512 K + 4 Kbytes 31 Kbytes PLQP0100KB-A M306NMFJVGP (D) PLQP0128KB-A M306NKME-XXXGP 192 Kbytes 16 Kbytes PLQP0100KB-A Mask Normal-ver. M306NMME-XXXGP PLQP0128KB-A ROM M306NKMG-XXXGP 256 Kbytes 20 Kbytes PLQP0100KB-A version M306NMMG-XXXGP PLQP0128KB-A (D): Under development NOTES: 1. Data flash memory provides an additional 4 Kbytes of ROM capacity (block A). 2. The correspondence between new and old package types is as follows. PLQP0100KB-A: 100P6Q-A PLQP0128KB-A: 128P6Q-A Type No. M30 6N K M G T - XXX GP Package type: GP: Package PLQP0100KB-A (100P6Q-A) PLQP0128KB-A (128P6Q-A) ROM No. Omitted on flash memory version Characteristics (no): Normal-ver. T : T-ver. (Automotive 85°C version) V : V-ver.(Automotive 125°C version) ROM capacity: E: 192 Kbytes G: 256 Kbytes H: 384 Kbytes J: 512 Kbytes Memory type: M: Mask ROM version F : Flash memory version Shows the number of CAN module, pin count, etc. 6N Group M16C Family Figure 1.2 Type Number, Memory Size, and Package Rev.2.10 Aug 25, 2006 page 5 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.5 Pin Assignments Figures 1.3 and 1.4 show the Pin Assignment (Top View). Tables 1.4 to 1.8 list the List of Pin Names. 0)1)2)3)4)5)6) 0/-)1/D2/D3/D4/D5/D6/D7/D DDDDDDDD NT3NT4NT50/A0(/1/A1(/2/A2(/3/A3(/4/A4(/5/A5(/6/A6(/7/A7(/ D7) D11D12D13/ID14/ID15/IAN2_AN2_AN2_AN2_AN2_AN2_AN2_AN2_ A8(/-/ A9A10A11A12A13A14A15A16A17 1_3/1_4/1_5/1_6/1_7/2_0/2_1/2_2/2_3/2_4/2_5/2_6/2_7/SS3_0/CC23_1/3_2/3_3/3_4/3_5/3_6/3_7/4_0/4_1/ PPPPPPPPPPPPPVPVPPPPPPPPP 75747372717069686766656463626160595857565554535251 P1_2/D10 76 50 P4_2/A18 P1_1/D9 77 49 P4_3/A19 P1_0/D8 78 48 P4_4/CS0 P0_7/AN0_7/D7 79 47 P4_5/CS1 P0_6/AN0_6/D6 80 46 P4_6/CS2 P0_5/AN0_5/D5 81 45 P4_7/CS3 P0_4/AN0_4/D4 82 44 P5_0/WRL/WR P0_3/AN0_3/D3 83 43 P5_1/WRH/BHE P0_2/AN0_2/D2 84 42 P5_2/RD P0_1/AN0_1/D1 85 41 P5_3/BCLK P0_0/AN0_0/D0 86 40 P5_4/HLDA P10_7/AN7/KI3 87 M16C/6N Group 39 P5_5/HOLD P10_6/AN6/KI2 88 (M16C/6NK) 38 P5_6/ALE P10_5/AN5/KI1 89 37 P5_7/RDY/CLKOUT P10_4/AN4/KI0 90 36 P6_0/CTS0/RTS0 P10_3/AN3 91 35 P6_1/CLK0 P10_2/AN2 92 34 P6_2/RXD0/SCL0 P10_1/AN1 93 33 P6_3/TXD0/SDA0 AVSS 94 32 P6_4/CTS1/RTS1/CTS0/CLKS1 P10_0/AN0 95 31 P6_5/CLK1 VREF 96 30 P6_6/RXD1/SCL1 AVCC 97 29 P6_7/TXD1/SDA1 P9_7/ADTRG/SIN4 98 28 P7_0/TXD2/SDA2/TA0OUT P9_6/ANEX1/CTX0/SOUT4 99 27 P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P9_5/ANEX0/CRX0/CLK4 100 26 P7_2/CLK2/TA1OUT/V 12345678910111213141516171819202122232425 P9_4/DA1/TB4INP9_3/DA0/TB3INP9_2/TB2IN/SOUT3(1) P9_1/TB1IN/SIN3P9_0/TB0IN/CLK3BYTECNVSSP8_7/XCINP8_6/XCOUTRESETXOUTVSSXINVCC1P8_5/NMIP8_4/INT2/ZPP8_3/INT1P8_2/INT0P8_1/TA4IN/UP8_0/TA4OUT/U(SIN4)P7_7/TA3IN/CRX1P7_6/TA3OUT/CTX1P7_5/TA2IN/W(SOUT4)P7_4/TA2OUT/W(CLK4)_3/CTS2/RTS2/TA1IN/V 7 P NOTES: Package: PLQP0100KB-A (100P6Q-A) 1. P7_1 and P9_1 are N channel open-drain pins. 2. Not available the bus control pins (except CLKOUT pin) in T/V-ver.. Figure 1.3 Pin Assignments (Top View) (1) Rev.2.10 Aug 25, 2006 page 6 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.4 List of Pin Names for 100-Pin Package (1) Control Interrupt Analog CAN Module Bus Control Pin No. Port Timer Pin UART Pin Pin Pin Pin Pin Pin (1) 1 P9_4 TB4IN DA1 2 P9_3 TB3IN DA0 3 P9_2 TB2IN SOUT3 4 P9_1 TB1IN SIN3 5 P9_0 TB0IN CLK3 6 BYTE 7 CNVSS 8 XCIN P8_7 9 XCOUT P8_6 _____________ 10 RESET 11 XOUT 12 VSS 13 XIN 14 VCC1 ________ 15 P8_5 NMI _________ 16 P8_4 INT2 ZP _________ 17 P8_3 INT1 _________ 18 P8_2 INT0 ___ 19 P8_1 TA4IN/U 20 P8_0 TA4OUT/U (SIN4) 21 P7_7 TA3IN CRX1 22 P7_6 TA3OUT CTX1 ____ 23 P7_5 TA2IN/W (SOUT4) 24 P7_4 TA2OUT/W (CLK4) ___ ____________________ 25 P7_3 TA1IN/V CTS2/RTS2 26 P7_2 TA1OUT/V CLK2 27 P7_1 TA0IN/TB5IN RXD2/SCL2 28 P7_0 TA0OUT TXD2/SDA2 29 P6_7 TXD1/SDA1 30 P6_6 RXD1/SCL1 31 P6_5 CLK1 ___________________________ 32 P6_4 CTS1/RTS1/CTS0/CLKS1 33 P6_3 TXD0/SDA0 34 P6_2 RXD0/SCL0 35 P6_1 CLK0 ____________________ 36 P6_0 CTS0/RTS0 _________ 37 P5_7 RDY/CLKOUT 38 P5_6 ALE ___________ 39 P5_5 HOLD ___________ 40 P5_4 HLDA 41 P5_3 BCLK ______ 42 P5_2 RD __________________ 43 P5_1 WRH/BHE _______________ 44 P5_0 WRL/WR _______ 45 P4_7 CS3 _______ 46 P4_6 CS2 _______ 47 P4_5 CS1 _______ 48 P4_4 CS0 49 P4_3 A19 50 P4_2 A18 NOTE: 1. Not available the bus control pins (except CLKOUT pin; Pin No.37) in T/V-ver.. Rev.2.10 Aug 25, 2006 page 7 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.5 List of Pin Names for 100-Pin Package (2) Control Interrupt Analog CAN Module Bus Control Pin No. Port Timer Pin UART Pin Pin Pin Pin Pin Pin (1) 51 P4_1 A17 52 P4_0 A16 53 P3_7 A15 54 P3_6 A14 55 P3_5 A13 56 P3_4 A12 57 P3_3 A11 58 P3_2 A10 59 P3_1 A9 60 VCC2 61 P3_0 A8(/-/D7) 62 VSS 63 P2_7 AN2_7 A7(/D7/D6) 64 P2_6 AN2_6 A6(/D6/D5) 65 P2_5 AN2_5 A5(/D5/D4) 66 P2_4 AN2_4 A4(/D4/D3) 67 P2_3 AN2_3 A3(/D3/D2) 68 P2_2 AN2_2 A2(/D2/D1) 69 P2_1 AN2_1 A1(/D1/D0) 70 P2_0 AN2_0 A0(/D0/-) _________ 71 P1_7 INT5 D15 _________ 72 P1_6 INT4 D14 _________ 73 P1_5 INT3 D13 74 P1_4 D12 75 P1_3 D11 76 P1_2 D10 77 P1_1 D9 78 P1_0 D8 79 P0_7 AN0_7 D7 80 P0_6 AN0_6 D6 81 P0_5 AN0_5 D5 82 P0_4 AN0_4 D4 83 P0_3 AN0_3 D3 84 P0_2 AN0_2 D2 85 P0_1 AN0_1 D1 86 P0_0 AN0_0 D0 ______ 87 P10_7 KI3 AN7 ______ 88 P10_6 KI2 AN6 ______ 89 P10_5 KI1 AN5 ______ 90 P10_4 KI0 AN4 91 P10_3 AN3 92 P10_2 AN2 93 P10_1 AN1 94 AVSS 95 P10_0 AN0 96 VREF 97 AVCC ______________ 98 P9_7 SIN4 ADTRG 99 P9_6 SOUT4 ANEX1 CTX0 100 P9_5 CLK4 ANEX0 CRX0 NOTE: 1. Not available the bus control pins in T/V-ver.. Rev.2.10 Aug 25, 2006 page 8 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 0)1)2)3)4)5)6) 0/-)1/D2/D3/D4/D5/D6/D7/D DDDDDDDD NT3NT4NT50/A0(/1/A1(/2/A2(/3/A3(/4/A4(/5/A5(/6/A6(/7/A7(/ D7) 1_1/D91_2/D101_3/D111_4/D121_5/D13/I1_6/D14/I1_7/D15/I2_0/AN2_2_1/AN2_2_2/AN2_2_3/AN2_2_4/AN2_2_5/AN2_2_6/AN2_2_7/AN2_SS3_0/A8(/-/CC212_012_112_212_312_43_1/A93_2/A103_3/A113_4/A123_5/A133_6/A143_7/A154_0/A164_1/A174_2/A184_3/A194_4/CS04_5/CS14_6/CS24_7/CS3 PPPPPPPPPPPPPPPVPVPPPPPPPPPPPPPPPPPPPP 1021011009998979695949392919089888786858483828180797877767574737271706968676665 P1_0/D8 103 64 P12_5 P0_7/AN0_7/D7 104 63 P12_6 P0_6/AN0_6/D6 105 62 P12_7 P0_5/AN0_5/D5 106 61 P5_0/WRL/WR P0_4/AN0_4/D4 107 60 P5_1/WRH/BHE P0_3/AN0_3/D3 108 59 P5_2/RD P0_2/AN0_2/D2 109 58 P5_3/BCLK P0_1/AN0_1/D1 110 57 P13_0 P0_0/AN0_0/D0 111 56 P13_1 P11_7/SIN6 112 55 P13_2 P11_6/SOUT6 113 54 P13_3 P11_5/CLK6 114 53 P5_4/HLDA P11_4 115 M16C/6N Group 52 P5_5/HOLD P11_3 116 51 P5_6/ALE P11_2/SOUT5 117 (M16C/6NM) 50 P5_7/RDY/CLKOUT P11_1/SIN5 118 49 P13_4 P11_0/CLK5 119 48 P13_5/INT6 P10_7/AN7/KI3 120 47 P13_6/INT7 P10_6/AN6/KI2 121 46 P13_7/INT8 P10_5/AN5/KI1 122 45 P6_0/CTS0/RTS0 P10_4/AN4/KI0 123 44 P6_1/CLK0 P10_3/AN3 124 43 P6_2/RXD0/SCL0 P10_2/AN2 125 42 P6_3/TXD0/SDA0 P10_1/AN1 126 41 P6_4/CTS1/RTS1/CTS0/CLKS1 AVSS 127 40 P6_5/CLK1 P10_0/AN0 128 39 VSS 1234567891011121314151617181920212223242526272829303132333435363738 VREFAVCCP9_7/ADTRG/SIN4P9_6/ANEX1/CTX0/SOUT4P9_5/ANEX0/CRX0/CLK4P9_4/DA1/TB4INP9_3/DA0/TB3INP9_2/TB2IN/SOUT3(1) P9_1/TB1IN/SIN3P9_0/TB0IN/CLK3P14_1P14_0BYTECNVSSP8_7/XCINP8_6/XCOUTRESETXOUTVSSXINVCC1P8_5/NMIP8_4/INT2/ZPP8_3/INT1P8_2/INT0P8_1/TA4IN/UP8_0/TA4OUT/U(SIN4)P7_7/TA3IN/CRX1P7_6/TA3OUT/CTX1P7_5/TA2IN/W(SOUT4)P7_4/TA2OUT/W(CLK4)P7_3/CTS2/RTS2/TA1IN/VP7_2/CLK2/TA1OUT/V1/RXD2/SCL2/TA0IN/TB5INP7_0/TXD2/SDA2/TA0OUTP6_7/TXD1/SDA1VCC1P6_6/RXD1/SCL1 _ 7 P (1) NOTES: Package: PLQP0128KB-A (128P6Q-A) 1. P7_1 and P9_1 are N channel open-drain pins. 2. Not available the bus control pins (except CLKOUT pin) in T/V-ver.. Figure 1.4 Pin Assignments (Top View) (2) Rev.2.10 Aug 25, 2006 page 9 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.6 List of Pin Names for 128-Pin Package (1) Control Interrupt Analog CAN Module Bus Control Pin No. Port Timer Pin UART Pin Pin Pin Pin Pin Pin (1) 1 VREF 2 AVCC ______________ 3 P9_7 SIN4 ADTRG 4 P9_6 SOUT4 ANEX1 CTX0 5 P9_5 CLK4 ANEX0 CRX0 6 P9_4 TB4IN DA1 7 P9_3 TB3IN DA0 8 P9_2 TB2IN SOUT3 9 P9_1 TB1IN SIN3 10 P9_0 TB0IN CLK3 11 P14_1 12 P14_0 13 BYTE 14 CNVSS 15 XCIN P8_7 16 XCOUT P8_6 _____________ 17 RESET 18 XOUT 19 VSS 20 XIN 21 VCC1 ________ 22 P8_5 NMI _________ 23 P8_4 INT2 ZP _________ 24 P8_3 INT1 _________ 25 P8_2 INT0 ___ 26 P8_1 TA4IN/U 27 P8_0 TA4OUT/U (SIN4) 28 P7_7 TA3IN CRX1 29 P7_6 TA3OUT CTX1 ____ 30 P7_5 TA2IN/W (SOUT4) 31 P7_4 TA2OUT/W (CLK4) ___ ____________________ 32 P7_3 TA1IN/V CTS2/RTS2 33 P7_2 TA1OUT/V CLK2 34 P7_1 TA0IN/TB5IN RXD2/SCL2 35 P7_0 TA0OUT TXD2/SDA2 36 P6_7 TXD1/SDA1 37 VCC1 38 P6_6 RXD1/SCL1 39 VSS 40 P6_5 CLK1 ___________________________ 41 P6_4 CTS1/RTS1/CTS0/CLKS1 42 P6_3 TXD0/SDA0 43 P6_2 RXD0/SCL0 44 P6_1 CLK0 ____________________ 45 P6_0 CTS0/RTS0 _________ 46 P13_7 INT8 _________ 47 P13_6 INT7 _________ 48 P13_5 INT6 49 P13_4 _________ 50 P5_7 RDY/CLKOUT NOTE: 1. Not available the bus control pins (except CLKOUT pin; Pin No.50) in T/V-ver.. Rev.2.10 Aug 25, 2006 page 10 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.7 List of Pin Names for 128-Pin Package (2) Control Interrupt Analog CAN Module Bus Control Pin No. Port Timer Pin UART Pin Pin Pin Pin Pin Pin (1) 51 P5_6 ALE ___________ 52 P5_5 HOLD ___________ 53 P5_4 HLDA 54 P13_3 55 P13_2 56 P13_1 57 P13_0 58 P5_3 BCLK ______ 59 P5_2 RD __________________ 60 P5_1 WRH/BHE _______________ 61 P5_0 WRL/WR 62 P12_7 63 P12_6 64 P12_5 _______ 65 P4_7 CS3 _______ 66 P4_6 CS2 _______ 67 P4_5 CS1 _______ 68 P4_4 CS0 69 P4_3 A19 70 P4_2 A18 71 P4_1 A17 72 P4_0 A16 73 P3_7 A15 74 P3_6 A14 75 P3_5 A13 76 P3_4 A12 77 P3_3 A11 78 P3_2 A10 79 P3_1 A9 80 P12_4 81 P12_3 82 P12_2 83 P12_1 84 P12_0 85 VCC2 86 P3_0 A8(/-/D7) 87 VSS 88 P2_7 AN2_7 A7(/D7/D6) 89 P2_6 AN2_6 A6(/D6/D5) 90 P2_5 AN2_5 A5(/D5/D4) 91 P2_4 AN2_4 A4(/D4/D3) 92 P2_3 AN2_3 A3(/D3/D2) 93 P2_2 AN2_2 A2(/D2/D1) 94 P2_1 AN2_1 A1(/D1/D0) 95 P2_0 AN2_0 A0(/D0/-) _________ 96 P1_7 INT5 D15 _________ 97 P1_6 INT4 D14 _________ 98 P1_5 INT3 D13 99 P1_4 D12 100 P1_3 D11 NOTE: 1. Not available the bus control pins in T/V-ver.. Rev.2.10 Aug 25, 2006 page 11 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.8 List of Pin Names for 128-Pin Package (3) Control Interrupt Analog CAN Module Bus Control Pin No. Port Timer Pin UART Pin Pin Pin Pin Pin Pin (1) 101 P1_2 D10 102 P1_1 D9 103 P1_0 D8 104 P0_7 AN0_7 D7 105 P0_6 AN0_6 D6 106 P0_5 AN0_5 D5 107 P0_4 AN0_4 D4 108 P0_3 AN0_3 D3 109 P0_2 AN0_2 D2 110 P0_1 AN0_1 D1 111 P0_0 AN0_0 D0 112 P11_7 SIN6 113 P11_6 SOUT6 114 P11_5 CLK6 115 P11_4 116 P11_3 117 P11_2 SOUT5 118 P11_1 SIN5 119 P11_0 CLK5 ______ 120 P10_7 KI3 AN7 ______ 121 P10_6 KI2 AN6 ______ 122 P10_5 KI1 AN5 ______ 123 P10_4 KI0 AN4 124 P10_3 AN3 125 P10_2 AN2 126 P10_1 AN1 127 AVSS 128 P10_0 AN0 NOTE: 1. Not available the bus control pins in T/V-ver.. Rev.2.10 Aug 25, 2006 page 12 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.6 Pin Functions Tables 1.9 to 1.11 list the Pin Functions. Table 1.9 Pin Functions (100-pin and 128-pin Versions) (1) Signal Name Pin Name I/O Type Description Power supply VCC1, VCC2, I Apply 3.0 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS input VSS pin. The VCC apply condition is that VCC2 = VCC1 (1). Analog power AVCC, AVSS I Applies the power supply for the A/D converter. Connect the AVCC supply input pin to VCC1. Connect the AVSS pin to VSS. _____________ Reset input RESET I The MCU is in a reset state when applying “L” to the this pin. CNVSS (2) CNVSS I Switches processor mode. Connect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. External data BYTE I Switches the data bus in external memory space. The data bus bus width is 16-bit long when the this pin is held “L” and 8-bit long when select input (2) the this pin is held “H”. Set it to either one. Connect this pin to VSS when single-chip mode. Bus control D0 to D7 I/O Inputs and outputs data (D0 to D7) when these pins are set as pins (3) the separate bus. D8 to D15 I/O Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the separate bus. A0 to A19 O Output address bits (A0 to A19). A0/D0 to A7/D7 I/O Input and output data (D0 to D7) and output address bits (A0 to A7) by time-sharing when external 8-bit data bus are set as the multiplexed bus. A1/D0 to A8/D7 I/O Input and output data (D0 to D7) and output address bits (A1 to A8) by time-sharing when external 16-bit data bus are set as the multiplexed bus. _______ _______ _______ _______ _______ _______ CS0 to CS3 O Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to specify an external space. _______________ ________ _________ ______ ________ _____ ________ _________ WRL/WR O Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or _________________ ________ ______ WRH/BHE BHE, and WR can be switched by program. ______ ________ _________ _____ RD • WRL, WRH, and RD are selected ________ The WRL signal becomes “L” by writing data to an even address in an external memory space. _________ The WRH signal becomes “L” by writing data to an odd address in an external memory space. _____ The RD pin signal becomes “L” by reading data in an external memory space. ______ ________ _____ • WR, BHE, and RD are selected ______ The WR signal becomes “L” by writing data in an external memory space. _____ The RD signal becomes “L” by reading data in an external memory space. ________ The BHE signal becomes “L” by accessing an odd address. ______ ________ _____ Select WR, BHE, and RD for an external 8-bit data bus. ALE O ALE is a signal to latch the address. __________ __________ HOLD I While the HOLD pin is held “L”, the MCU is placed in a hold state. __________ __________ HLDA O In a hold state, HLDA outputs a “L” signal. ________ ________ RDY I While applying a “L” signal to the RDY pin, the MCU is placed in a wait state. I: Input O: Output I/O: Input/Output NOTES: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted. 2. Connect to VSS in T/V-ver.. 3. Not available the bus control pins in T/V-ver.. Rev.2.10 Aug 25, 2006 page 13 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.10 Pin Functions (100-pin and 128-pin Versions) (2) Signal Name Pin Name I/O Type Description Main clock XIN I I/O pins for the main clock oscillation circuit. Connect a ceramic input resonator or crystal oscillator between XIN and XOUT (1). Main clock XOUT O To use the external clock, input the clock from XIN and leave output XOUT open. Sub clock XCIN I I/O pins for a sub clock oscillation circuit. Connect a crystal input oscillator between XCIN and XCOUT (1). Sub clock XCOUT O To use the external clock, input the clock from XCIN and leave output XCOUT open. BCLK output (3) BCLK O Outputs the BCLK signal. Clock output CLKOUT O The clock of the same cycle as fC, f8, or f32 is output. ______ INT interrupt input NT0 to INT8 (2) I Input pins for the INT interrupt. _______ ________ _______ NMI interrupt NMI I Input pin for the NMI interrupt. input ______ ______ Key input KI0 to KI3 I Input pins for the key input interrupt. interrupt input Timer A TA0OUT to TA4OUT I/O These are timer A0 to timer A4 I/O pins. TA0IN to TA4IN I These are timer A0 to timer A4 input pins. ZP I Input pin for the Z-phase. Timer B TB0IN to TB5IN I These are timer B0 to timer B5 input pins. ___ ___ ____ Three-phase motor U, U, V, V, W, W O These are Three-phase motor control output pins. control output __________ __________ Serial interface CTS0 to CTS2 I These are transmit control input pins. __________ __________ RTS0 to RTS2 O These are receive control output pins. CLK0 to CLK6 (2) I/O These are transfer clock I/O pins. RXD0 to RXD2 I These are serial data input pins. SIN3 to SIN6 (2) I These are serial data input pins. TXD0 to TXD2 O These are serial data output pins. SOUT3 to SOUT6 (2) O These are serial data output pins. CLKS1 O This is output pin for transfer clock output from multiple pins function. I2C mode SDA0 to SDA2 I/O These are serial data I/O pins. SCL0 to SCL2 I/O These are transfer clock I/O pins. (however, SCL2 for the N-channel open drain output.) Reference VREF I Applies the reference voltage for the A/D converter and D/A voltage input converter. A/D converter AN0 to AN7 I Analog input pins for the A/D converter. AN0_0 to AN0_7 AN2_0 to AN2_7 _____________ ADTRG I This is an A/D trigger input pin. ANEX0 I/O This is the extended analog input pin for the A/D converter, and is the output in external op-amp connection mode. ANEX1 I This is the extended analog input pin for the A/D converter. D/A converter DA0, DA1 O These are the output pins for the D/A converter. CAN module CRX0, CRX1 I These are the input pins for the CAN module. CTX0, CTX1 O These are the output pins for the CAN module. I: Input O: Output I/O: Input/Output NOTES: 1. Ask the oscillator maker the oscillation characteristic. ________ ________ 2. INT6 to INT8, CLK5, CLK6, SIN5, SIN6, SOUT5, SOUT6 are only in the 128-pin version. 3. Not available the bus control pins in T/V-ver.. Rev.2.10 Aug 25, 2006 page 14 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.11 Pin Functions (100-pin and 128-pin Versions) (3) Signal Name Pin Name I/O Type Description I/O port P0_0 to P0_7 I/O 8-bit I/O ports in CMOS, having a direction register to select P1_0 to P1_7 an input or output. P2_0 to P2_7 Each pin is set as an input port or output port. An input port P3_0 to P3_7 can be set for a pull-up or for no pull-up in 4-bit unit by P4_0 to P4_7 program. P5_0 to P5_7 (however P7_1 and P9_1 for the N-channel open drain P6_0 to P6_7 output.) P7_0 to P7_7 P8_0 to P8_4 P8_6, P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_7 (1) P12_0 to P12_7 (1) P13_0 to P13_7 (1) P14_0, P14_1 (1) _______ Input port P8_5 I Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. I: Input O: Output I/O: Input/Output NOTE: 1. Ports P11 to P14 are only in the 128-pin version. Rev.2.10 Aug 25, 2006 page 15 of 81 REJ03B0058-02100

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two register banks. b31 b15 b8 b7 b0 R2 R0H (R0's high bits) R0L (R0's low bits) R3 R1H (R1's high bits) R1L (R1's low bits) Data Registers (1) R2 R3 A0 Address Registers (1) A1 FB Frame Base Registers (1) b19 b15 b0 INTBH INTBL Interrupt Table Register The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b19 b0 PC Program Counter b15 b0 USP User Stack Pointer ISP Interrupt Stack Pointer SB Static Base Register b15 b0 FLG Flag Register b15 b8b7 b0 IPL U I O B S Z D C Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level Reserved Area NOTE: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Registers 2.1 Data Registers (R0, R1, R2, and R3) The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) The A0 register consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0. In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0). Rev.2.10 Aug 25, 2006 page 16 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. 2.7 Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. 2.8 Flag Register (FLG) FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) This flag is used exclusively for debugging purpose. During normal use, set to 0. 2.8.3 Zero Flag (Z Flag) This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0. 2.8.4 Sign Flag (S Flag) This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0. 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is 0; register bank 1 is selected when this flag is 1. 2.8.6 Overflow Flag (O Flag) This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0. 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is set to 0 when the interrupt request is accepted. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is 0; USP is selected when the U flag is 1. The U flag is set to 0 when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt request is enabled. 2.8.10 Reserved Area When white to this bit, write 0. When read, its content is undefined. Rev.2.10 Aug 25, 2006 page 17 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 3. Memory 3. Memory Figure 3.1 shows a Memory Map. The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 512-Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh. As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs. The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 31-Kbyte internal RAM is allocated to the addresses from 00400h to 07FFFh. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The Special Function Registers (SFRs) are allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be accessed by user. The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS or JSRS instruction. For details, refer to M16C/60, M16C/20, M16C/Tiny Series Software Manual. In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. Use T/V-ver. in single-chip mode. The memory expansion and microprocessor modes cannot be used. 00000h SFR 00400h Internal RAM XXXXXh FFE00h Reserved area (1) 0F000h Internal ROM 0FFFFh (data flash) (3) Svpeecctoiar l tpaabglee 10000h External area 27000h Reserved area FFFDCh Undefined instruction 28000h Overflow Internal RAM Internal ROM (4) External area BRK instruction Capacity Address XXXXXh Capacity Address YYYYYh Address match 16 Kbytes 043FFh 192 Kbytes D0000h 80000h Reserved area (2) Single step 20 Kbytes 053FFh 256 Kbytes C0000h YYYYYh Osc dilelatteiocntio snto D/p w BaantCcdh rdeo-ogs tcimilleartion 31 Kbytes 07FFFh 384 Kbytes A0000h (prInotgerranmal aRreOaM) (4) NMI 512 Kbytes 80000h FFFFFh F F FFFh Reset NOTES: 1.During memory expansion mode or microprocessor mode, cannot be used. 2.In memory expansion mode, cannot be used. 3.As for the flash memory version, 4-Kbyte space (block A) exists. 4. When using the masked ROM version, write nothing to internal ROM area. 5.Shown here is a memory map for the case where the PM10 bit in the PM1 register is 1 (block A enabled, addresses 10000h to 26FFFh for CS2 area) and the PM13 bit in the PM1 register is 1 (internal RAM area is expanded over 192 Kbytes). * Not available memory expansion and microprocessor modes in T/V-ver.. And not available external area in T/V-ver.. Figure 3.1 Memory Map Rev.2.10 Aug 25, 2006 page 18 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) An SFR (Special Function Register) is a control register for a peripheral function. Tables 4.1 to 4.16 list the SFR Information. Table 4.1 SFR Information (1) (5) Address Register Symbol After Reset 0000h 0001h 0002h 0003h 00000000b (CNVSS pin is "L") 0004h Processor Mode Register 0 (1) PM0 00000011b (CNVSS pin is "H") (3) 0005h Processor Mode Register 1 PM1 00001000b 0006h System Clock Control Register 0 CM0 01001000b 0007h System Clock Control Register 1 CM1 00100000b 0008h Chip Select Control Register (4) CSR 00000001b 0009h Address Match Interrupt Enable Register AIER XXXXXX00b 000Ah Protect Register PRCR XX000000b 000Bh 000Ch Oscillation Stop Detection Register (2) CM2 0X000000b 000Dh 000Eh Watchdog Timer Start Register WDTS XXh 000Fh Watchdog Timer Control Register WDC 00XXXXXXb 0010h 00h 0011h Address Match Interrupt Register 0 RMAD0 00h 0012h X0h 0013h 0014h 00h 0015h Address Match Interrupt Register 1 RMAD1 00h 0016h X0h 0017h 0018h 0019h 001Ah 001Bh Chip Select Expansion Control Register (4) CSE 00h 001Ch PLL Control Register 0 PLC0 0001X010b 001Dh 001Eh Processor Mode Register 2 PM2 XXX00000b 001Fh 0020h XXh 0021h DMA0 Source Pointer SAR0 XXh 0022h XXh 0023h 0024h XXh 0025h DMA0 Destination Pointer DAR0 XXh 0026h XXh 0027h 0028h XXh DMA0 Transfer Counter TCR0 0029h XXh 002Ah 002Bh 002Ch DMA0 Control Register DM0CON 00000X00b 002Dh 002Eh 002Fh 0030h XXh 0031h DMA1 Source Pointer SAR1 XXh 0032h XXh 0033h 0034h XXh 0035h DMA1 Destination Pointer DAR1 XXh 0036h XXh 0037h 0038h XXh DMA1 Transfer Counter TCR1 0039h XXh 003Ah 003Bh 003Ch DMA1 Control Register DM1CON 00000X00b 003Dh 003Eh 003Fh X: Undefined NOTES: 1. Bits PM00 and PM01 in the PM0 register do not change at software reset, watchdog timer reset and oscillation stop detection reset. * Effective when memory expansion and microprocessor modes (= Normal-ver.). 2. Bits CM20, CM21, and CM27 in the CM2 register do not change at oscillation stop detection reset. 3. CNVSS pin = H is not available in T/V-ver.. Do not set a value. 4. These registers are not available in T/V-ver. 5. Blank spaces are reserved. No access is allowed. Rev.2.10 Aug 25, 2006 page 19 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.2 SFR Information (2) (2) Address Register Symbol After Reset 0040h 0041h CAN0/1 Wake-up Interrupt Control Register C01WKIC XXXXX000b 0042h CAN0 Successful Reception Interrupt Control Register C0RECIC XXXXX000b 0043h CAN0 Successful Transmission Interrupt Control Register C0TRMIC XXXXX000b 0044h INT3 Interrupt Control Register INT3IC XX00X000b Timer B5 Interrupt Control Register TB5IC 0045h XXXXX000b SI/O5 Interrupt Control Register (1) S5IC Timer B4 Interrupt Control Register TB4IC 0046h XXXXX000b UART1 Bus Collision Detection Interrupt Control Register U1BCNIC Timer B3 Interrupt Control Register TB3IC 0047h XXXXX000b UART0 Bus Collision Detection Interrupt Control Register U0BCNIC CAN1 Successful Reception Interrupt Control Register C1RECIC 0048h SI/O4 Interrupt Control Register S4IC XX00X000b INT5 Interrupt Control Register INT5IC CAN1 Successful Transmission Interrupt Control Register C1TRMIC 0049h SI/O3 Interrupt Control Register S3IC XX00X000b INT4 Interrupt Control Register INT4IC 004Ah UART2 Bus Collision Detection Interrupt Control Register U2BCNIC XXXXX000b 004Bh DMA0 Interrupt Control Register DM0IC XXXXX000b 004Ch DMA1 Interrupt Control Register DM1IC XXXXX000b 004Dh CAN0/1 Error Interrupt Control Register C01ERRIC XXXXX000b A/D Conversion Interrupt Control Register ADIC 004Eh XXXXX000b Key Input Interrupt Control Register KUPIC 004Fh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b 0050h UART2 Receive Interrupt Control Register S2RIC XXXXX000b 0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b 0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b 0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b 0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b 0055h Timer A0 Interrupt Control Register TA0IC XXXXX000b 0056h Timer A1 Interrupt Control Register TA1IC XXXXX000b Timer A2 Interrupt Control Register TA2IC 0057h XX00X000b INT7 Interrupt Control Register (1) INT7IC Timer A3 Interrupt Control Register TA3IC 0058h XX00X000b INT6 Interrupt Control Register (1) INT6IC 0059h Timer A4 Interrupt Control Register TA4IC XXXXX000b Timer B0 Interrupt Control Register TB0IC 005Ah XXXXX000b SI/O6 Interrupt Control Register (1) S6IC Timer B1 Interrupt Control Register TB1IC 005Bh XX00X000b INT8 Interrupt Control Register (1) INT8IC 005Ch Timer B2 Interrupt Control Register TB2IC XXXXX000b 005Dh INT0 Interrupt Control Register INT0IC XX00X000b 005Eh INT1 Interrupt Control Register INT1IC XX00X000b 005Fh INT2 Interrupt Control Register INT2IC XX00X000b 0060h XXh 0061h XXh 0062h XXh CAN0 Message Box 0: Identifier / DLC 0063h XXh 0064h XXh 0065h XXh 0066h XXh 0067h XXh 0068h XXh 0069h XXh CAN0 Message Box 0: Data Field 006Ah XXh 006Bh XXh 006Ch XXh 006Dh XXh 006Eh XXh CAN0 Message Box 0: Time Stamp 006Fh XXh 0070h XXh 0071h XXh 0072h XXh CAN0 Message Box 1: Identifier / DLC 0073h XXh 0074h XXh 0075h XXh 0076h XXh 0077h XXh 0078h XXh 0079h XXh CAN0 Message Box 1: Data Field 007Ah XXh 007Bh XXh 007Ch XXh 007Dh XXh 007Eh XXh CAN0 Message Box 1: Time Stamp 007Fh XXh X: Undefined NOTES: 1. These registers exist only in the 128-pin version. 2. Blank spaces are reserved. No access is allowed. Rev.2.10 Aug 25, 2006 page 20 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.3 SFR Information (3) Address Register Symbol After Reset 0080h XXh 0081h XXh 0082h XXh CAN0 Message Box 2: Identifier / DLC 0083h XXh 0084h XXh 0085h XXh 0086h XXh 0087h XXh 0088h XXh 0089h XXh CAN0 Message Box 2: Data Field 008Ah XXh 008Bh XXh 008Ch XXh 008Dh XXh 008Eh XXh CAN0 Message Box 2: Time Stamp 008Fh XXh 0090h XXh 0091h XXh 0092h XXh CAN0 Message Box 3: Identifier / DLC 0093h XXh 0094h XXh 0095h XXh 0096h XXh 0097h XXh 0098h XXh 0099h XXh CAN0 Message Box 3: Data Field 009Ah XXh 009Bh XXh 009Ch XXh 009Dh XXh 009Eh XXh CAN0 Message Box 3: Time Stamp 009Fh XXh 00A0h XXh 00A1h XXh 00A2h XXh CAN0 Message Box 4: Identifier / DLC 00A3h XXh 00A4h XXh 00A5h XXh 00A6h XXh 00A7h XXh 00A8h XXh 00A9h XXh CAN0 Message Box 4: Data Field 00AAh XXh 00ABh XXh 00ACh XXh 00ADh XXh 00AEh XXh CAN0 Message Box 4: Time Stamp 00AFh XXh 00B0h XXh 00B1h XXh 00B2h XXh CAN0 Message Box 5: Identifier / DLC 00B3h XXh 00B4h XXh 00B5h XXh 00B6h XXh 00B7h XXh 00B8h XXh 00B9h XXh CAN0 Message Box 5: Data Field 00BAh XXh 00BBh XXh 00BCh XXh 00BDh XXh 00BEh XXh CAN0 Message Box 5: Time Stamp 00BFh XXh X: Undefined Rev.2.10 Aug 25, 2006 page 21 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.4 SFR Information (4) Address Register Symbol After Reset 00C0h XXh 00C1h XXh 00C2h XXh CAN0 Message Box 6: Identifier / DLC 00C3h XXh 00C4h XXh 00C5h XXh 00C6h XXh 00C7h XXh 00C8h XXh 00C9h XXh CAN0 Message Box 6: Data Field 00CAh XXh 00CBh XXh 00CCh XXh 00CDh XXh 00CEh XXh CAN0 Message Box 6: Time Stamp 00CFh XXh 00D0h XXh 00D1h XXh 00D2h XXh CAN0 Message Box 7: Identifier / DLC 00D3h XXh 00D4h XXh 00D5h XXh 00D6h XXh 00D7h XXh 00D8h XXh 00D9h XXh CAN0 Message Box 7: Data Field 00DAh XXh 00DBh XXh 00DCh XXh 00DDh XXh 00DEh XXh CAN0 Message Box 7: Time Stamp 00DFh XXh 00E0h XXh 00E1h XXh 00E2h XXh CAN0 Message Box 8: Identifier / DLC 00E3h XXh 00E4h XXh 00E5h XXh 00E6h XXh 00E7h XXh 00E8h XXh 00E9h XXh CAN0 Message Box 8: Data Field 00EAh XXh 00EBh XXh 00ECh XXh 00EDh XXh 00EEh XXh CAN0 Message Box 8: Time Stamp 00EFh XXh 00F0h XXh 00F1h XXh 00F2h XXh CAN0 Message Box 9: Identifier / DLC 00F3h XXh 00F4h XXh 00F5h XXh 00F6h XXh 00F7h XXh 00F8h XXh 00F9h XXh CAN0 Message Box 9: Data Field 00FAh XXh 00FBh XXh 00FCh XXh 00FDh XXh 00FEh XXh CAN0 Message Box 9: Time Stamp 00FFh XXh X: Undefined Rev.2.10 Aug 25, 2006 page 22 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.5 SFR Information (5) Address Register Symbol After Reset 0100h XXh 0101h XXh 0102h XXh CAN0 Message Box 10: Identifier / DLC 0103h XXh 0104h XXh 0105h XXh 0106h XXh 0107h XXh 0108h XXh 0109h XXh CAN0 Message Box 10: Data Field 010Ah XXh 010Bh XXh 010Ch XXh 010Dh XXh 010Eh XXh CAN0 Message Box 10: Time Stamp 010Fh XXh 0110h XXh 0111h XXh 0112h XXh CAN0 Message Box 11: Identifier / DLC 0113h XXh 0114h XXh 0115h XXh 0116h XXh 0117h XXh 0118h XXh 0119h XXh CAN0 Message Box 11: Data Field 011Ah XXh 011Bh XXh 011Ch XXh 011Dh XXh 011Eh XXh CAN0 Message Box 11: Time Stamp 011Fh XXh 0120h XXh 0121h XXh 0122h XXh CAN0 Message Box 12: Identifier / DLC 0123h XXh 0124h XXh 0125h XXh 0126h XXh 0127h XXh 0128h XXh 0129h XXh CAN0 Message Box 12: Data Field 012Ah XXh 012Bh XXh 012Ch XXh 012Dh XXh 012Eh XXh CAN0 Message Box 12: Time Stamp 012Fh XXh 0130h XXh 0131h XXh 0132h XXh CAN0 Message Box 13: Identifier / DLC 0133h XXh 0134h XXh 0135h XXh 0136h XXh 0137h XXh 0138h XXh 0139h XXh CAN0 Message Box 13: Data Field 013Ah XXh 013Bh XXh 013Ch XXh 013Dh XXh 013Eh XXh CAN0 Message Box 13: Time Stamp 013Fh XXh X: Undefined Rev.2.10 Aug 25, 2006 page 23 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.6 SFR Information (6) (1) Address Register Symbol After Reset 0140h XXh 0141h XXh 0142h XXh CAN0 Message Box 14: Identifier /DLC 0143h XXh 0144h XXh 0145h XXh 0146h XXh 0147h XXh 0148h XXh 0149h XXh CAN0 Message Box 14: Data Field 014Ah XXh 014Bh XXh 014Ch XXh 014Dh XXh 014Eh XXh CAN0 Message Box 14: Time Stamp 014Fh XXh 0150h XXh 0151h XXh 0152h XXh CAN0 Message Box 15: Identifier /DLC 0153h XXh 0154h XXh 0155h XXh 0156h XXh 0157h XXh 0158h XXh 0159h XXh CAN0 Message Box 15: Data Field 015Ah XXh 015Bh XXh 015Ch XXh 015Dh XXh 015Eh XXh CAN0 Message Box 15: Time Stamp 015Fh XXh 0160h XXh 0161h XXh 0162h XXh CAN0 Global Mask Register C0GMR 0163h XXh 0164h XXh 0165h XXh 0166h XXh 0167h XXh 0168h XXh CAN0 Local Mask A Register C0LMAR 0169h XXh 016Ah XXh 016Bh XXh 016Ch XXh 016Dh XXh 016Eh XXh CAN0 Local Mask B Register C0LMBR 016Fh XXh 0170h XXh 0171h XXh 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh X: Undefined NOTE: 1. Blank spaces are reserved. No access is allowed. Rev.2.10 Aug 25, 2006 page 24 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.7 SFR Information (7) (2) Address Register Symbol After Reset 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h Flash Memory Control Register 1 (1) FMR1 0X00XX0Xb 01B6h 01B7h Flash Memory Control Register 0 (1) FMR0 00000001b 01B8h 00h 01B9h Address Match Interrupt Register 2 RMAD2 00h 01BAh X0h 01BBh Address Match Interrupt Enable Register 2 AIER2 XXXXXX00b 01BCh 00h 01BDh Address Match Interrupt Register 3 RMAD3 00h 01BEh X0h 01BFh X: Undefined NOTES: 1. These registers are included in the flash memory version. Cannot be accessed by users in the mask ROM version. 2. Blank spaces are reserved. No access is allowed. Rev.2.10 Aug 25, 2006 page 25 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.8 SFR Information (8) (3) Address Register Symbol After Reset 01C0h Timer B3, B4, B5 Count Start Flag TBSR 000XXXXXb 01C1h 01C2h XXh Timer A1-1 Register TA11 01C3h XXh 01C4h XXh Timer A2-1 Register TA21 01C5h XXh 01C6h XXh Timer A4-1 Register TA41 01C7h XXh 01C8h Three-Phase PWM Control Register 0 INVC0 00h 01C9h Three-Phase PWM Control Register 1 INVC1 00h 01CAh Three-Phase Output Buffer Register 0 IDB0 00111111b 01CBh Three-Phase Output Buffer Register 1 IDB1 00111111b 01CCh Dead Time Timer DTT XXh 01CDh Timer B2 Interrupt Generation Frequency Set Counter ICTB2 XXh 01CEh 01CFh Interrupt Source Select Register 2 IFSR2 X0000000b 01D0h XXh Timer B3 Register TB3 01D1h XXh 01D2h XXh Timer B4 Register TB4 01D3h XXh 01D4h XXh Timer B5 Register TB5 01D5h XXh 01D6h SI/O6 Transmit/Receive Register (1) S6TRR XXh 01D7h 01D8h SI/O6 Control Register (1) S6C 01000000b 01D9h SI/O6 Bit Rate Register (1) S6BRG XXh 01DAh SI/O3, 4, 5, 6 Transmit/Receive Register (2) S3456TRR XXXX0000b 01DBh Timer B3 Mode Register TB3MR 00XX0000b 01DCh Timer B4 Mode Register TB4MR 00XX0000b 01DDh Timer B5 Mode Register TB5MR 00XX0000b 01DEh Interrupt Source Select Register 0 IFSR0 00h 01DFh Interrupt Source Select Register 1 IFSR1 00h 01E0h SI/O3 Transmit/Receive Register S3TRR XXh 01E1h 01E2h SI/O3 Control Register S3C 01000000b 01E3h SI/O3 Bit Rate Register S3BRG XXh 01E4h SI/O4 Transmit/Receive Register S4TRR XXh 01E5h 01E6h SI/O4 Control Register S4C 01000000b 01E7h SI/O4 Bit Rate Register S4BRG XXh 01E8h SI/O5 Transmit/Receive Register (1) S5TRR XXh 01E9h 01EAh SI/O5 Control Register (1) S5C 01000000b 01EBh SI/O5 Bit Rate Register (1) S5BRG XXh 01ECh UART0 Special Mode Register 4 U0SMR4 00h 01EDh UART0 Special Mode Register 3 U0SMR3 000X0X0Xb 01EEh UART0 Special Mode Register 2 U0SMR2 X0000000b 01EFh UART0 Special Mode Register U0SMR X0000000b 01F0h UART1 Special Mode Register 4 U1SMR4 00h 01F1h UART1 Special Mode Register 3 U1SMR3 000X0X0Xb 01F2h UART1 Special Mode Register 2 U1SMR2 X0000000b 01F3h UART1 Special Mode Register U1SMR X0000000b 01F4h UART2 Special Mode Register 4 U2SMR4 00h 01F5h UART2 Special Mode Register 3 U2SMR3 000X0X0Xb 01F6h UART2 Special Mode Register 2 U2SMR2 X0000000b 01F7h UART2 Special Mode Register U2SMR X0000000b 01F8h UART2 Transmit/Receive Mode Register U2MR 00h 01F9h UART2 Bit Rate Register U2BRG XXh 01FAh XXh UART2 Transmit Buffer Register U2TB 01FBh XXh 01FCh UART2 Transmit/Receive Control Register 0 U2C0 00001000b 01FDh UART2 Transmit/Receive Control Register 1 U2C1 00000010b 01FEh XXh UART2 Receive Buffer Register U2RB 01FFh XXh X: Undefined NOTES: 1. These registers exist only in the 128-pin version. 2. Bits S5TRF and S6TRF in the S3456TRR register are used in the 128-pin version. 3. Blank spaces are reserved. No access is allowed. Rev.2.10 Aug 25, 2006 page 26 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.9 SFR Information (9) Address Register Symbol After Reset 0200h CAN0 Message Control Register 0 C0MCTL0 00h 0201h CAN0 Message Control Register 1 C0MCTL1 00h 0202h CAN0 Message Control Register 2 C0MCTL2 00h 0203h CAN0 Message Control Register 3 C0MCTL3 00h 0204h CAN0 Message Control Register 4 C0MCTL4 00h 0205h CAN0 Message Control Register 5 C0MCTL5 00h 0206h CAN0 Message Control Register 6 C0MCTL6 00h 0207h CAN0 Message Control Register 7 C0MCTL7 00h 0208h CAN0 Message Control Register 8 C0MCTL8 00h 0209h CAN0 Message Control Register 9 C0MCTL9 00h 020Ah CAN0 Message Control Register 10 C0MCTL10 00h 020Bh CAN0 Message Control Register 11 C0MCTL11 00h 020Ch CAN0 Message Control Register 12 C0MCTL12 00h 020Dh CAN0 Message Control Register 13 C0MCTL13 00h 020Eh CAN0 Message Control Register 14 C0MCTL14 00h 020Fh CAN0 Message Control Register 15 C0MCTL15 00h 0210h X0000001b CAN0 Control Register C0CTLR 0211h XX0X0000b 0212h 00h CAN0 Status Register C0STR 0213h X0000001b 0214h 00h CAN0 Slot Status Register C0SSTR 0215h 00h 0216h 00h CAN0 Interrupt Control Register C0ICR 0217h 00h 0218h 00h CAN0 Extended ID Register C0IDR 0219h 00h 021Ah XXh CAN0 Configuration Register C0CONR 021Bh XXh 021Ch CAN0 Receive Error Count Register C0RECR 00h 021Dh CAN0 Transmit Error Count Register C0TECR 00h 021Eh 00h CAN0 Time Stamp Register C0TSR 021Fh 00h 0220h CAN1 Message Control Register 0 C1MCTL0 00h 0221h CAN1 Message Control Register 1 C1MCTL1 00h 0222h CAN1 Message Control Register 2 C1MCTL2 00h 0223h CAN1 Message Control Register 3 C1MCTL3 00h 0224h CAN1 Message Control Register 4 C1MCTL4 00h 0225h CAN1 Message Control Register 5 C1MCTL5 00h 0226h CAN1 Message Control Register 6 C1MCTL6 00h 0227h CAN1 Message Control Register 7 C1MCTL7 00h 0228h CAN1 Message Control Register 8 C1MCTL8 00h 0229h CAN1 Message Control Register 9 C1MCTL9 00h 022Ah CAN1 Message Control Register 10 C1MCTL10 00h 022Bh CAN1 Message Control Register 11 C1MCTL11 00h 022Ch CAN1 Message Control Register 12 C1MCTL12 00h 022Dh CAN1 Message Control Register 13 C1MCTL13 00h 022Eh CAN1 Message Control Register 14 C1MCTL14 00h 022Fh CAN1 Message Control Register 15 C1MCTL15 00h 0230h X0000001b CAN1 Control Register C1CTLR 0231h XX0X0000b 0232h 00h CAN1 Status Register C1STR 0233h X0000001b 0234h 00h CAN1 Slot Status Register C1SSTR 0235h 00h 0236h 00h CAN1 Interrupt Control Register C1ICR 0237h 00h 0238h 00h CAN1 Extended ID Register C1IDR 0239h 00h 023Ah XXh CAN1 Configuration Register C1CONR 023Bh XXh 023Ch CAN1 Receive Error Count Register C1RECR 00h 023Dh CAN1 Transmit Error Count Register C1TECR 00h 023Eh 00h CAN1 Time Stamp Register C1TSR 023Fh 00h X: Undefined Rev.2.10 Aug 25, 2006 page 27 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.10 SFR Information (10) (1) Address Register Symbol After Reset 0240h 0241h 0242h XXh CAN0 Acceptance Filter Support Register C0AFS 0243h XXh 0244h XXh CAN1 Acceptance Filter Support Register C1AFS 0245h XXh 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh Peripheral Clock Select Register PCLKR 00h 025Fh CAN0/1 Clock Select Register CCLKR 00h 0260h XXh 0261h XXh 0262h CAN1 Message Box 0: Identifier / DLC XXh 0263h XXh 0264h XXh 0265h XXh 0266h XXh 0267h XXh 0268h XXh 0269h XXh CAN1 Message Box 0: Data Field 026Ah XXh 026Bh XXh 026Ch XXh 026Dh XXh 026Eh XXh CAN1 Message Box 0:Time Stamp 026Fh XXh 0270h XXh 0271h XXh 0272h XXh CAN1 Message Box 1: Identifier / DLC 0273h XXh 0274h XXh 0275h XXh 0276h XXh 0277h XXh 0278h XXh 0279h XXh CAN1 Message Box 1: Data Field 027Ah XXh 027Bh XXh 027Ch XXh 027Dh XXh 027Eh XXh CAN1 Message Box 1:Time Stamp 027Fh XXh X: Undefined NOTE: 1. Blank spaces are reserved. No access is allowed. Rev.2.10 Aug 25, 2006 page 28 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.11 SFR Information (11) Address Register Symbol After Reset 0280h XXh 0281h XXh 0282h XXh CAN1 Message Box 2: Identifier / DLC 0283h XXh 0284h XXh 0285h XXh 0286h XXh 0287h XXh 0288h XXh 0289h XXh CAN1 Message Box 2: Data Field 028Ah XXh 028Bh XXh 028Ch XXh 028Dh XXh 028Eh XXh CAN1 Message Box 2: Time Stamp 028Fh XXh 0290h XXh 0291h XXh 0292h XXh CAN1 Message Box 3: Identifier / DLC 0293h XXh 0294h XXh 0295h XXh 0296h XXh 0297h XXh 0298h XXh 0299h XXh CAN1 Message Box 3: Data Field 029Ah XXh 029Bh XXh 029Ch XXh 029Dh XXh 029Eh XXh CAN1 Message Box 3: Time Stamp 029Fh XXh 02A0h XXh 02A1h XXh 02A2h XXh CAN1 Message Box 4: Identifier / DLC 02A3h XXh 02A4h XXh 02A5h XXh 02A6h XXh 02A7h XXh 02A8h XXh 02A9h XXh CAN1 Message Box 4: Data Field 02AAh XXh 02ABh XXh 02ACh XXh 02ADh XXh 02AEh XXh CAN1 Message Box 4: Time Stamp 02AFh XXh 02B0h XXh 02B1h XXh 02B2h XXh CAN1 Message Box 5: Identifier / DLC 02B3h XXh 02B4h XXh 02B5h XXh 02B6h XXh 02B7h XXh 02B8h XXh 02B9h XXh CAN1 Message Box 5: Data Field 02BAh XXh 02BBh XXh 02BCh XXh 02BDh XXh 02BEh XXh CAN1 Message Box 5: Time Stamp 02BFh XXh X: Undefined Rev.2.10 Aug 25, 2006 page 29 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.12 SFR Information (12) Address Register Symbol After Reset 02C0h XXh 02C1h XXh 02C2h XXh CAN1 Message Box 6: Identifier / DLC 02C3h XXh 02C4h XXh 02C5h XXh 02C6h XXh 02C7h XXh 02C8h XXh 02C9h XXh CAN1 Message Box 6: Data Field 02CAh XXh 02CBh XXh 02CCh XXh 02CDh XXh 02CEh XXh CAN1 Message Box 6: Time Stamp 02CFh XXh 02D0h XXh 02D1h XXh 02D2h XXh CAN1 Message Box 7: Identifier / DLC 02D3h XXh 02D4h XXh 02D5h XXh 02D6h XXh 02D7h XXh 02D8h XXh 02D9h XXh CAN1 Message Box 7: Data Field 02DAh XXh 02DBh XXh 02DCh XXh 02DDh XXh 02DEh XXh CAN1 Message Box 7: Time Stamp 02DFh XXh 02E0h XXh 02E1h XXh 02E2h XXh CAN1 Message Box 8: Identifier / DLC 02E3h XXh 02E4h XXh 02E5h XXh 02E6h XXh 02E7h XXh 02E8h XXh 02E9h XXh CAN1 Message Box 8: Data Field 02EAh XXh 02EBh XXh 02ECh XXh 02EDh XXh 02EEh XXh CAN1 Message Box 8: Time Stamp 02EFh XXh 02F0h XXh 02F1h XXh 02F2h XXh CAN1 Message Box 9: Identifier / DLC 02F3h XXh 02F4h XXh 02F5h XXh 02F6h XXh 02F7h XXh 02F8h XXh 02F9h XXh CAN1 Message Box 9: Data Field 02FAh XXh 02FBh XXh 02FCh XXh 02FDh XXh 02FEh XXh CAN1 Message Box 9: Time Stamp 02FFh XXh X: Undefined Rev.2.10 Aug 25, 2006 page 30 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.13 SFR Information (13) Address Register Symbol After Reset 0300h XXh 0301h XXh 0302h XXh CAN1 Message Box 10: Identifier / DLC 0303h XXh 0304h XXh 0305h XXh 0306h XXh 0307h XXh 0308h XXh 0309h XXh CAN1 Message Box 10: Data Field 030Ah XXh 030Bh XXh 030Ch XXh 030Dh XXh 030Eh XXh CAN1 Message Box 10: Time Stamp 030Fh XXh 0310h XXh 0311h XXh 0312h XXh CAN1 Message Box 11: Identifier / DLC 0313h XXh 0314h XXh 0315h XXh 0316h XXh 0317h XXh 0318h XXh 0319h XXh CAN1 Message Box 11: Data Field 031Ah XXh 031Bh XXh 031Ch XXh 031Dh XXh 031Eh XXh CAN1 Message Box 11: Time Stamp 031Fh XXh 0320h XXh 0321h XXh 0322h XXh CAN1 Message Box 12: Identifier / DLC 0323h XXh 0324h XXh 0325h XXh 0326h XXh 0327h XXh 0328h XXh 0329h XXh CAN1 Message Box 12: Data Field 032Ah XXh 032Bh XXh 032Ch XXh 032Dh XXh 032Eh XXh CAN1 Message Box 12: Time Stamp 032Fh XXh 0330h XXh 0331h XXh 0332h XXh CAN1 Message Box 13: Identifier / DLC 0333h XXh 0334h XXh 0335h XXh 0336h XXh 0337h XXh 0338h XXh 0339h XXh CAN1 Message Box 13: Data Field 033Ah XXh 033Bh XXh 033Ch XXh 033Dh XXh 033Eh XXh CAN1 Message Box 13: Time Stamp 033Fh XXh X: Undefined Rev.2.10 Aug 25, 2006 page 31 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.14 SFR Information (14) (1) Address Register Symbol After Reset 0340h XXh 0341h XXh 0342h XXh CAN1 Message Box 14: Identifier / DLC 0343h XXh 0344h XXh 0345h XXh 0346h XXh 0347h XXh 0348h XXh 0349h XXh CAN1 Message Box 14: Data Field 034Ah XXh 034Bh XXh 034Ch XXh 034Dh XXh 034Eh XXh CAN1 Message Box 14: Time Stamp 034Fh XXh 0350h XXh 0351h XXh 0352h XXh CAN1 Message Box 15: Identifier / DLC 0353h XXh 0354h XXh 0355h XXh 0356h XXh 0357h XXh 0358h XXh 0359h XXh CAN1 Message Box 15: Data Field 035Ah XXh 035Bh XXh 035Ch XXh 035Dh XXh 035Eh XXh CAN1 Message Box 15: Time Stamp 035Fh XXh 0360h XXh 0361h XXh 0362h XXh CAN1 Global Mask Register C1GMR 0363h XXh 0364h XXh 0365h XXh 0366h XXh 0367h XXh 0368h XXh CAN1 Local Mask A Register C1LMAR 0369h XXh 036Ah XXh 036Bh XXh 036Ch XXh 036Dh XXh 036Eh XXh CAN1 Local Mask B Register C1LMBR 036Fh XXh 0370h XXh 0371h XXh 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh X: Undefined NOTE: 1. Blank spaces are reserved. No access is allowed. Rev.2.10 Aug 25, 2006 page 32 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.15 SFR Information (15) (2) Address Register Symbol After Reset 0380h Count Start Flag TABSR 00h 0381h Clock Prescaler Reset Flag CPSRF 0XXXXXXXb 0382h One-Shot Start Flag ONSF 00h 0383h Trigger Select Register TRGSR 00h 0384h Up/Down Flag UDF 00h (1) 0385h 0386h XXh Timer A0 Register TA0 0387h XXh 0388h XXh Timer A1 Register TA1 0389h XXh 038Ah XXh Timer A2 Register TA2 038Bh XXh 038Ch XXh Timer A3 Register TA3 038Dh XXh 038Eh XXh Timer A4 Register TA4 038Fh XXh 0390h XXh Timer B0 Register TB0 0391h XXh 0392h XXh Timer B1 Register TB1 0393h XXh 0394h XXh Timer B2 Register TB2 0395h XXh 0396h Timer A0 Mode Register TA0MR 00h 0397h Timer A1 Mode Register TA1MR 00h 0398h Timer A2 Mode Register TA2MR 00h 0399h Timer A3 Mode Register TA3MR 00h 039Ah Timer A4 Mode Register TA4MR 00h 039Bh Timer B0 Mode Register TB0MR 00XX0000b 039Ch Timer B1 Mode Register TB1MR 00XX0000b 039Dh Timer B2 Mode Register TB2MR 00XX0000b 039Eh Timer B2 Special Mode Register TB2SC XXXXXX00b 039Fh 03A0h UART0 Transmit/Receive Mode Register U0MR 00h 03A1h UART0 Bit Rate Register U0BRG XXh 03A2h XXh UART0 Transmit Buffer Register U0TB 03A3h XXh 03A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b 03A5h UART0 Transmit/Receive Control Register 1 U0C1 00XX0010b 03A6h XXh UART0 Receive Buffer Register U0RB 03A7h XXh 03A8h UART1 Transmit/Receive Mode Register U1MR 00h 03A9h UART1 Bit Rate Register U1BRG XXh 03AAh XXh UART1 Transmit Buffer Register U1TB 03ABh XXh 03ACh UART1 Transmit/Receive Control Register 0 U1C0 00001000b 03ADh UART1 Transmit/Receive Control Register 1 U1C1 00XX0010b 03AEh XXh UART1 Receive Buffer Register U1RB 03AFh XXh 03B0h UART Transmit/Receive Control Register 2 UCON X0000000b 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h DMA0 Request Source Select Register DM0SL 00h 03B9h 03BAh DMA1 Request Source Select Register DM1SL 00h 03BBh 03BCh XXh CRC Data Register CRCD 03BDh XXh 03BEh CRC Input Register CRCIN XXh 03BFh X: Undefined NOTES: 1. Bits TA2P to TA4P in the UDF register are set to 0 after reset. However, the contents in these bits are undefined when read. 2. Blank spaces are reserved. No access is allowed. Rev.2.10 Aug 25, 2006 page 33 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.16 SFR Information (16) (3) Address Register Symbol After Reset 03C0h XXh A/D Register 0 AD0 03C1h XXh 03C2h XXh A/D Register 1 AD1 03C3h XXh 03C4h XXh A/D Register 2 AD2 03C5h XXh 03C6h XXh A/D Register 3 AD3 03C7h XXh 03C8h XXh A/D Register 4 AD4 03C9h XXh 03CAh XXh A/D Register 5 AD5 03CBh XXh 03CCh XXh A/D Register 6 AD6 03CDh XXh 03CEh XXh A/D Register 7 AD7 03CFh XXh 03D0h 03D1h 03D2h 03D3h 03D4h A/D Control Register 2 ADCON2 00h 03D5h 03D6h A/D Control Register 0 ADCON0 00000XXXb 03D7h A/D Control Register 1 ADCON1 00h 03D8h D/A Register 0 DA0 00h 03D9h 03DAh D/A Register 1 DA1 00h 03DBh 03DCh D/A Control Register DACON 00h 03DDh 03DEh Port P14 Control Register (2) PC14 XX00XXXXb 03DFh Pull-Up Control Register 3 (2) PUR3 00h 03E0h Port P0 Register P0 XXh 03E1h Port P1 Register P1 XXh 03E2h Port P0 Direction Register PD0 00h 03E3h Port P1 Direction Register PD1 00h 03E4h Port P2 Register P2 XXh 03E5h Port P3 Register P3 XXh 03E6h Port P2 Direction Register PD2 00h 03E7h Port P3 Direction Register PD3 00h 03E8h Port P4 Register P4 XXh 03E9h Port P5 Register P5 XXh 03EAh Port P4 Direction Register PD4 00h 03EBh Port P5 Direction Register PD5 00h 03ECh Port P6 Register P6 XXh 03EDh Port P7 Register P7 XXh 03EEh Port P6 Direction Register PD6 00h 03EFh Port P7 Direction Register PD7 00h 03F0h Port P8 Register P8 XXh 03F1h Port P9 Register P9 XXh 03F2h Port P8 Direction Register PD8 00X00000b 03F3h Port P9 Direction Register PD9 00h 03F4h Port P10 Register P10 XXh 03F5h Port P11 Register (2) P11 XXh 03F6h Port P10 Direction Register PD10 00h 03F7h Port P11 Direction Register (2) PD11 00h 03F8h Port P12 Register (2) P12 XXh 03F9h Port P13 Register (2) P13 XXh 03FAh Port P12 Direction Register (2) PD12 00h 03FBh Port P13 Direction Register (2) PD13 00h 03FCh Pull-up Control Register 0 PUR0 00h 00000000b (1) 03FDh Pull-up Control Register 1 PUR1 00000010b 03FEh Pull-up Control Register 2 PUR2 00h 03FFh Port Control Register PCR 00h X: Undefined NOTES: 1.At hardware reset, the register is as follows: 00000000b where "L" is input to the CNVSS pin 00000010b where "H" is input to the CNVSS pin (CNVSS pin = H is not available in T/V-ver..) At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: 00000000b where the PM01 to PM00 bits in the PM0 register are 00b (single-chip mode) 00000010b where the PM01 to PM00 bits in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode) * Not available memory expansion and microprocessor modes in T/V-ver.. 2. These registers exist only in the128-pin version. 3. Blank spaces are reserved. No access is allowed. Rev.2.10 Aug 25, 2006 page 34 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) 5. Electrical Characteristics 5.1 Electrical Characteristics (Normal-ver.) Table 5.1 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit VCC Supply voltage (VCC1 = VCC2) VCC = AVCC –0.3 to 6.5 V AVCC Analog supply voltage VCC = AVCC –0.3 to 6.5 V _____________ VI Input RESET, CNVSS, BYTE, –0.3 to VCC+0.3 V voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, VREF, XIN P7_1, P9_1 –0.3 to 6.5 V VO Output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, –0.3 to VCC+0.3 V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XOUT P7_1, P9_1 –0.3 to 6.5 V Pd Power dissipation Topr = 25°C 700 mW Topr Operating ambient During MCU operation –40 to 85 °C temperature During flash memory program and 0 to 60 erase operation Tstg Storage temperature –65 to 150 °C NOTE: 1. Ports P11 to P14 are only in the 128-pin version. Rev.2.10 Aug 25, 2006 page 35 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Table 5.2 Recommended Operating Conditions (1) (1) Standard Symbol Parameter Unit Min. Typ. Max. VCC Supply voltage (VCC1 = VCC2) 3.0 5.0 5.5 V AVCC Analog supply voltage VCC V VSS Supply voltage 0 V AVSS Analog supply voltage 0 V VIH HIGH input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, 0.8 VCC VCC V voltage P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, _____________ XIN, RESET, CNVSS, BYTE P7_1, P9_1 0.8 VCC 6.5 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 0.8 VCC VCC V (During single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 0.5 VCC VCC (Data input during memory expansion and microprocessor modes) VIL LOW input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, 0 0.2 VCC V voltage P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to V P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, _____________ P14_0, P14_1, XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 0 0.2 VCC V (During single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 0 0.16 VCC V (Data input during memory expansion and microprocessor modes) IOH(peak) HIGH peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, –10.0 mA output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 IOH(avg) HIGH average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, –5.0 mA output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 IOL(peak) LOW peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, 10.0 mA output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 IOL(avg) LOW average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, 5.0 mA output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 NOTES: 1.Referenced to VCC = 3.0 to 5.5 V at Topr = –40 to 85°C unless otherwise specified. 2.Average output current values during 100 ms period. 3.The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be 80 mA max. The total IOL(peak) for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80 mA max. The total IOH(peak) for ports P0, P1, and P2 must be –40 mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be –40 mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be –40 mA max. The total IOH(peak) for ports P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be –40 mA max. 4.P11 to P14 are only in the 128-pin version. Rev.2.10 Aug 25, 2006 page 36 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Table 5.3 Recommended Operating Conditions (2) (1) Standard Symbol Parameter Unit Min. Typ. Max. f(XIN) Main clock input oscillation No wait Mask ROM version VCC = 3.0 to 5.5 V 0 16 MHz frequency (2) (3) (4) Flash memory version f(XCIN) Sub clock oscillation frequency 32.768 50 kHz f(Ring) On-chip oscillation frequency 1 MHz f(PLL) PLL clock oscillation frequency 16 24 MHz f(BCLK) CPU operation clock VCC = 3.0 to 5.5 V 0 24 MHz tsu(PLL) PLL frequency synthesizer stabilization wait time 20 ms NOTES: 1.Referenced to VCC = 3.0 to 5.5 V at Topr = –40 to 85°C unless z] Main clock input oscillation frequency H M (Mask ROM version / Flash memory otherwise specified. y [ version: no wait) 2.Relationship between main clock oscillation frequency and supply nc 16.0 e u voltage is shown right. eq 3.Execute program/erase of flash memory by VCC = 3.3 ± 0.3 V or m fr u m VCC = 5.0 ± 0.5 V. xi a m 4.When using 16 MHz and over, use PLL clock. PLL clock oscillation g n frequency which can be used is 16 MHz, 20 MHz or 24 MHz. ati er op 0.0 N) 3.0 5.5 f(XI VCC [V] (main clock: no division) Rev.2.10 Aug 25, 2006 page 37 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Table 5.4 Electrical Characteristics (1) (1) VCC = 5V Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. VOH HIGH output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –5 mA VCC-2.0 VCC V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VOH HIGH output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –200 µA VCC-0.3 VCC V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VOH HIGH output XOUT HIGHPOWER IOH = –1 mA 3.0 VCC V voltage LOWPOWER IOH = –0.5 mA 3.0 VCC HIGH output XCOUT HIGHPOWER With no load applied 2.5 V voltage LOWPOWER With no load applied 1.6 VOL LOW output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 5 mA 2.0 V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VOL LOW output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 200 µA 0.45 V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VOL LOW output XOUT HIGHPOWER IOL = 1 mA 2.0 V voltage LOWPOWER IOL = 0.5 mA 2.0 LOW output XCOUT HIGHPOWER With no load applied 0 V voltage LOWPOWER With no load applied 0 VT+-VT- Hysteresis _H__O___L__D__, _R__D___Y__, TA0IN to TA4IN, TB0IN to TB5IN, 0.2 1.0 V _________ _________ ________ ______________ __________ __________ INT0 to INT8, NMI, ADTRG, CTS0 to CTS2, SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK6, ______ ______ TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SIN3 to SIN6 VT+-VT- Hysteresis _R__E___S__E___T__ 0.2 2.5 V IIH HIGH input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 5 V 5.0 µA current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, ____________ XIN, RESET, CNVSS, BYTE IIL LOW input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V –5.0 µA current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, ____________ XIN, RESET, CNVSS, BYTE RPULLUP Pull-up P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V 30 50 170 kΩ resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 RfXIN Feedback resistance XIN 1.5 MΩ RfXCIN Feedback resistance XCIN 15 MΩ VRAM RAM retention voltage At stop mode 2.0 V NOTES: 1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified. ________ ________ 2. P11 to P14, INT6 to INT8, CLK5, CLK6, SIN5, and SIN6 are only in the 128-pin version. Rev.2.10 Aug 25, 2006 page 38 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Table 5.5 Electrical Characteristics (2) (1) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. ICC Power supply In single-chip mode, Mask ROM f(BCLK) = 24 MHz, 21 37 mA current the output pins are PLL operation, (VCC = 3.0 to 5.5 V) open and other pins No division are VSS. On-chip oscillation, 1 mA No division Flash memory f(BCLK) = 24 MHz, 23 39 mA PLL operation, No division On-chip oscillation, 1.8 mA No division Flash memory f(BCLK) = 10 MHz, 15 mA program VCC = 5 V Flash memory f(BCLK) = 10 MHz, 25 mA erase VCC = 5 V Mask ROM f(BCLK) = 32 kHz, 25 µA Low power dissipation mode, ROM (2) Flash memory f(BCLK) = 32 kHz, 25 µA Low power dissipation mode, RAM (2) f(BCLK) = 32 kHz, 420 µA Low power dissipation mode, Flash memory (2) Mask ROM On-chip oscillation, 50 µA Flash memory Wait mode f(BCLK) = 32 kHz, 8.5 µA Wait mode (3), Oscillation capacity High f(BCLK) = 32 kHz, 3.0 µA Wait mode (3), Oscillation capacity Low Stop mode, 0.8 3.0 µA Topr = 25°C NOTES: 1. Referenced to VCC = 3.0 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified. 2. This indicates the memory in which the program to be executed exists. 3. With one timer operated using fC32. Rev.2.10 Aug 25, 2006 page 39 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Table 5.6 A/D Conversion Characteristics (1) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. – Resolution VREF = VCC 10 Bit INL Integral 10 bits VREF ANEX0, ANEX1 input, AN0 to AN7 input, ±3 LSB nonlinearity = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input error = 5 V External operation amp connection mode ±7 LSB VREF ANEX0, ANEX1 input, AN0 to AN7 input, ±5 LSB = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 3.3 V External operation amp connection mode ±7 LSB 8 bits VREF = AVCC = VCC = 3.3 V ±2 LSB – Absolute 10 bits VREF ANEX0, ANEX1 input, AN0 to AN7 input, ±3 LSB accuracy = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 5 V External operation amp connection mode ±7 LSB VREF ANEX0, ANEX1 input, AN0 to AN7 input, ±5 LSB = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 3.3 V External operation amp connection mode ±7 LSB 8 bits VREF = AVCC = VCC = 3.3 V ±2 LSB DNL Differential nonlinearity error ±1 LSB – Offset error ±3 LSB – Gain error ±3 LSB RLADDER Resistor ladder VREF = VCC 10 40 kΩ tCONV 10-bit conversion time, VREF = VCC = 5 V, φAD = 10 MHz 3.3 µs sample & hold available 8-bit conversion time, VREF = VCC = 5 V, φAD = 10 MHz 2.8 µs sample & hold available tSAMP Sampling time 0.3 µs VREF Reference voltage 2.0 VCC V VIA Analog input voltage 0 VREF V NOTES: 1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified. 2. φAD frequency must be 10 MHz or less. 3. When sample & hold is disabled, φAD frequency must be 250 kHz or more in addition to a limit of NOTE 2. When sample & hold is enabled, φAD frequency must be 1 MHz or more in addition to a limit of NOTE 2. Table 5.7 D/A conversion Characteristics (1) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. – Resolution 8 Bits – Absolute accuracy 1.0 % tsu Setup time 3 µs RO Output resistance 4 10 20 kΩ IVREF Reference power supply input current (NOTE 2) 1.5 mA NOTES: 1.Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified. 2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h. The resistor ladder of the A/D converter is not included. Also, the IVREF will flow even if VREF is disconnected by the ADCON1 register. Rev.2.10 Aug 25, 2006 page 40 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Table 5.8 Flash Memory Version Electrical Characteristics (1) Standard Symbol Parameter Unit Min. Typ. Max. - Programming and erasure endurance (2) 100 cycle - Word program time (VCC = 5.0 V) 25 200 µs - Lock bit program time 25 200 µs - Block erase time 4-Kbyte block 0.3 4 s (VCC = 5.0 V) 8-Kbyte block 0.3 4 s 32-Kbyte block 0.5 4 s 64-Kbyte block 0.8 4 s - Erase all unlocked blocks time 4 ✕ n (3) s tps Flash memory circuit stabilization wait time 15 µs NOTES: 1. Referenced to VCC = 4.5 to 5.5 V, 3.0 to 3.6 V, Topr = 0 to 60°C unless otherwise specified. 2. Programming and erasure endurance refers to the number of times a block erase can be performed. If the programming and erasure endurance is n (n = 100), each block can be erased n times. For example, if a 4-Kbyte block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as one programming and erasure endurance. Data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 3. n denotes the number of blocks to erase. Table 5.9 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics (at Topr = 0 to 60°C) Flash Program, Erase Voltage Flash Read Operation Voltage VCC = 3.3 ± 0.3 V or 5.0 ± 0.5 V VCC = 3.0 to 5.5 V Table 5.10 Power Supply Circuit Timing Characteristics Measuring Standard Symbol Parameter Unit Condition Min. Typ. Max. td(P-R) Time for internal power supply stabilization during powering-on VCC = 3.0 to 5.5 V 2 ms td(R-S) STOP release time 150 µs td(W-S) Low power dissipation mode wait mode release time 150 µs td(P-R) Time for internal power supply VCC stabilization during powering-on td(P-R) CPU clock td(R-S) Interrupt for (a) Stop mode release STOP release time or (b) Wait mode release td(W-S) Low power dissipation mode CPU clock wait mode release time (a) td(R-S) (b) td(W-S) Figure 5.1 Power Supply Circuit Timing Diagram Rev.2.10 Aug 25, 2006 page 41 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC = 5 V (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) Table 5.11 External Clock Input (XIN Input) Standard Symbol Parameter Unit Min. Max. tC External clock input cycle time 62.5 ns tw(H) External clock input HIGH pulse width 25 ns tw(L) External clock input LOW pulse width 25 ns tr External clock rise time 15 ns tf External clock fall time 15 ns Table 5.12 Memory Expansion Mode and Microprocessor Mode Standard Symbol Parameter Unit Min. Max. tac1(RD-DB) Data input access time (for setting with no wait) (NOTE 1) ns tac2(RD-DB) Data input access time (for setting with wait) (NOTE 2) ns tac3(RD-DB) Data input access time (when accessing multiplexed bus area) (NOTE 3) ns tsu(DB-RD) Data input setup time 40 ns ________ tsu(RDY-BCLK) RDY input setup time 30 ns __________ tsu(HOLD-BCLK) HOLD input setup time 40 ns th(RD-DB) Data input hold time 0 ns ________ th(BCLK-RDY) RDY input hold time 0 ns __________ th(BCLK-HOLD) HOLD input hold time 0 ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 45 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: (n –0.5) ✕ 109 – 45 [ns] n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting. f(BCLK) 3. Calculated according to the BCLK frequency as follows: (n –0.5) ✕ 109 – 45 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting. f(BCLK) Rev.2.10 Aug 25, 2006 page 42 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC = 5 V (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) Table 5.13 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 100 ns tw(TAH) TAiIN input HIGH pulse width 40 ns tw(TAL) TAiIN input LOW pulse width 40 ns Table 5.14 Timer A Input (Gating Input in Timer Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 400 ns tw(TAH) TAiIN input HIGH pulse width 200 ns tw(TAL) TAiIN input LOW pulse width 200 ns Table 5.15 Timer A Input (External Trigger Input in One-shot Timer Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 200 ns tw(TAH) TAiIN input HIGH pulse width 100 ns tw(TAL) TAiIN input LOW pulse width 100 ns Table 5.16 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Standard Symbol Parameter Unit Min. Max. tw(TAH) TAiIN input HIGH pulse width 100 ns tw(TAL) TAiIN input LOW pulse width 100 ns Table 5.17 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(UP) TAiOUT input cycle time 2000 ns tw(UPH) TAiOUT input HIGH pulse width 1000 ns tw(UPL) TAiOUT input LOW pulse width 1000 ns tsu(UP-TIN) TAiOUT input setup time 400 ns th(TIN-UP) TAiOUT input hold time 400 ns Table 5.18 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 800 ns tsu(TAIN-TAOUT) TAiOUT input setup time 200 ns tsu(TAOUT-TAIN) TAiIN input setup time 200 ns Rev.2.10 Aug 25, 2006 page 43 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC = 5 V (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) Table 5.19 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(TB) TBiIN input cycle time (counted on one edge) 100 ns tw(TBH) TBiIN input HIGH pulse width (counted on one edge) 40 ns tw(TBL) TBiIN input LOW pulse width (counted on one edge) 40 ns tc(TB) TBiIN input cycle time (counted on both edges) 200 ns tw(TBH) TBiIN input HIGH pulse width (counted on both edges) 80 ns tw(TBL) TBiIN input LOW pulse width (counted on both edges) 80 ns Table 5.20 Timer B Input (Pulse Period Measurement Mode) Standard Symbol Parameter Unit Min. Max. tc(TB) TBiIN input cycle time 400 ns tw(TBH) TBiIN input HIGH pulse width 200 ns tw(TBL) TBiIN input LOW pulse width 200 ns Table 5.21 Timer B Input (Pulse Width Measurement Mode) Standard Symbol Parameter Unit Min. Max. tc(TB) TBiIN input cycle time 400 ns tw(TBH) TBiIN input HIGH pulse width 200 ns tw(TBL) TBiIN input LOW pulse width 200 ns Table 5.22 A/D Trigger Input Standard Symbol Parameter Unit Min. Max. _____________ tC(AD) ADTRG input cycle time (trigger able minimum) 1000 ns _____________ tw(ADL) ADTRG input LOW pulse width 125 ns Table 5.23 Serial Interface Standard Symbol Parameter Unit Min. Max. tc(CK) CLKi input cycle time 200 ns tw(CKH) CLKi input HIGH pulse width 100 ns tw(CKL) CLKi input LOW pulse width 100 ns td(C-Q) TXDi output delay time 80 ns th(C-Q) TXDi hold time 0 ns tsu(D-C) RXDi input setup time 70 ns th(C-D) RXDi input hold time 90 ns _______ Table 5.24 External Interrupt INTi Input Standard Symbol Parameter Unit Min. Max. _______ tw(INH) INTi input HIGH pulse width 250 ns _______ tw(INL) INTi input LOW pulse width 250 ns Rev.2.10 Aug 25, 2006 page 44 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC = 5 V (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 5.25 Memory Expansion Mode and Microprocessor Mode (for setting with no wait) Measuring Standard Symbol Parameter Unit Condition Min. Max. td(BCLK-AD) Address output delay time Figure 5.2 25 ns th(BCLK-AD) Address output hold time (in relation to BCLK) 4 ns th(RD-AD) Address output hold time (in relation to RD) 0 ns th(WR-AD) Address output hold time (in relation to WR) (NOTE 1) ns td(BCLK-CS) Chip select output delay time 25 ns th(BCLK-CS) Chip select output hold time (rin relation to BCLK) 4 ns td(BCLK-ALE) ALE signal output delay time 15 ns th(BCLK-ALE) ALE signal output hold time –4 ns td(BCLK-RD) RD signal output delay time 25 ns th(BCLK-RD) RD signal output hold time 0 ns td(BCLK-WR) WR signal output delay time 25 ns th(BCLK-WR) WR signal output hold time 0 ns td(BCLK-DB) Data output delay time (in relation to BCLK) 40 ns th(BCLK-DB) Data output hold time (in relation to BCLK) (3) 4 ns td(DB-WR) Data output delay time (in relation to WR) (NOTE 2) ns th(WR-DB) Data output hold time (rin relation to WR) (3) (NOTE 1) ns __________ td(BCLK-HLDA) HLDA output delay time 40 ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 10 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 40 [ns] f(BCLK) is 12.5 MHz or less. f(BCLK) 3.This standard value shows the timing when the output is off, and does not show hold time of data bus. R Hold time of data bus varies with capacitor volume DBi and pull-up (pull-down) resistance value. C Hold time of data bus is expressed in t = – CR ✕ ln (1 – V / V ) OL CC by a circuit of the right figure. For example, when VOL = 0.2 VCC, C = 30 pF, P0 P1 R =1 kΩ, hold time of output “L” level is P2 30 pF P3 t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns. P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 NOTE: 1. P11 to P14 are only in the 128-pin version. Figure 5.2 Port P0 to P14 Measurement Circuit Rev.2.10 Aug 25, 2006 page 45 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC = 5 V (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 5.26 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access) Measuring Standard Symbol Parameter Unit Condition Min. Max. td(BCLK-AD) Address output delay time Figure 5.2 25 ns th(BCLK-AD) Address output hold time (in relation to BCLK) 4 ns th(RD-AD) Address output hold time (in relation to RD) 0 ns th(WR-AD) Address output hold time (in relation to WR) (NOTE 1) ns td(BCLK-CS) Chip select output delay time 25 ns th(BCLK-CS) Chip select output hold time (in relation to BCLK) 4 ns td(BCLK-ALE) ALE signal output delay time 15 ns th(BCLK-ALE) ALE signal output hold time –4 ns td(BCLK-RD) RD signal output delay time 25 ns th(BCLK-RD) RD signal output hold time 0 ns td(BCLK-WR) WR signal output delay time 25 ns th(BCLK-WR) WR signal output hold time 0 ns td(BCLK-DB) Data output delay time (in relation to BCLK) 40 ns th(BCLK-DB) Data output hold time (rin relation to BCLK) (3) 4 ns td(DB-WR) Data output delay time (in relation to WR) (NOTE 2) ns th(WR-DB) Data output hold time (in relation to WR) (3) (NOTE 1) ns __________ td(BCLK-HLDA) HLDA output delay time 40 ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 10 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: (n – 0.5) ✕ 109 n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting. – 40 [ns] f(BCLK) When n = 1, f(BCLK) is 12.5 MHz or less. 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. R Hold time of data bus varies with capacitor volume DBi and pull-up (pull-down) resistance value. C Hold time of data bus is expressed in t = – CR ✕ ln (1 – V / V ) OL CC by a circuit of the right figure. For example, when V = 0.2 V , C = 30 pF, OL CC R =1 kΩ, hold time of output “L” level is t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 V / V ) = 6.7 ns. CC CC Rev.2.10 Aug 25, 2006 page 46 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC = 5 V (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 5.27 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) Measuring Standard Symbol Parameter Unit Condition Min. Max. td(BCLK-AD) Address output delay time Figure 5.2 25 ns th(BCLK-AD) Address output hold time (in relation to BCLK) 4 ns th(RD-AD) Address output hold time (in relation to RD) (NOTE 1) ns th(WR-AD) Address output hold time (in relation to WR) (NOTE 1) ns td(BCLK-CS) Chip select output delay time 25 ns th(BCLK-CS) Chip select output hold time (in relation to BCLK) 4 ns th(RD-CS) Chip select output hold time (in relation to RD) (NOTE 1) ns th(WR-CS) Chip select output hold time (in relation to WR) (NOTE 1) ns td(BCLK-RD) RD signal output delay time 25 ns th(BCLK-RD) RD signal output hold time 0 ns td(BCLK-WR) WR signal output delay time 25 ns th(BCLK-WR) WR signal output hold time 0 ns td(BCLK-DB) Data output delay time (in relation to BCLK) 40 ns th(BCLK-DB) Data output hold time (in relation to BCLK) 4 ns td(DB-WR) Data output delay time (in relation to WR) (NOTE 2) ns th(WR-DB) Data output hold time (in relation to WR) (NOTE 1) ns __________ td(BCLK-HLDA) HLDA output delay time 40 ns td(BCLK-ALE) ALE signal output delay time (in relation to BCLK) 15 ns th(BCLK-ALE) ALE signal output hold time (in relation to BCLK) –4 ns td(AD-ALE) ALE signal output delay time (in relation to Address) (NOTE 3) ns th(ALE-AD) ALE signal output hold time (in relation to Address) (NOTE 4) ns td(AD-RD) RD signal output delay from the end of Address 0 ns td(AD-WR) WR signal output delay from the end of Address 0 ns tdZ(RD-AD) Address output floating start time 8 ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 10 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: (n –0.5) ✕ 109 – 40 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting. f(BCLK) 3. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 25 [ns] f(BCLK) 4. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 15 [ns] f(BCLK) Rev.2.10 Aug 25, 2006 page 47 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) VCC = 5 V XIN input tr tw(H) tr tw(L) tc tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge th(TIN—UP)tsu(UP—TIN) is selected) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tC(TA) TAiIN input tsu(TAIN—TAOUT) tsu(TAIN—TAOUT) tsu(TAOUT—TAIN) TAiOUT input tsu(TAOUT—TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C—Q) TXDi td(C—Q) tsu(D—C) th(C—D) RXDi tw(INL) INTi input tw(INH) Figure 5.3 Timing Diagram (1) Rev.2.10 Aug 25, 2006 page 48 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 5 V (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY–BCLK) th(BCLK–RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD–BCLK) th(BCLK–HOLD) HOLD input HLDA output td(BCLK–HLDA) td(BCLK–HLDA) P0, P1, P2, Hi–Z P3, P4, P5_0 to P5_2 (1) NOTE: 1. The above pins are set to high-impedance regardless of the input level of the BYTE pin, the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register. Measuring conditions : VCC = 5 V Input timing voltage : Determined with VIL = 1.0 V, VIH = 4.0 V Output timing voltage: Determined with VOL = 2.5 V, VOH = 2.5 V Figure 5.4 Timing Diagram (2) Rev.2.10 Aug 25, 2006 page 49 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 5 V (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(RD-AD) 25ns.max -4ns.min 0ns.min ALE td(BCLK-RD) th(BCLK-RD) 25ns.max 0ns.min RD tac1(RD-DB) (0.5 ✕ tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) th(RD-DB) 40ns.min 0ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(WR-AD) 25ns.max -4ns.min (0.5 ✕ tcyc-10)ns.min ALE td(BCLK-WR) th(BCLK-WR) 25ns.max 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min Hi-Z DBi td(DB-WR) th(WR-DB) 1 (0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min tcyc= f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage: VOL = 0.4 V, VOH = 2.4 V Figure 5.5 Timing Diagram (3) Rev.2.10 Aug 25, 2006 page 50 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 5 V (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(RD-AD) 25ns.max -4ns.min 0ns.min ALE td(BCLK-RD) th(BCLK-RD) 25ns.max 0ns.min RD tac2(RD-DB) (1.5 ✕ tcyc-45)ns.max DBi Hi-Z th(RD-DB) tSU(DB-RD) 0ns.min 40ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(WR-AD) 25ns.max -4ns.min (0.5 ✕ tcyc-10)ns.min ALE td(BCLK-WR) th(BCLK-WR) 25ns.max 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min Hi-Z DBi td(DB-WR) th(WR-DB) 1 (0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min tcyc= f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage: VOL = 0.4 V, VOH = 2.4 V Figure 5.6 Timing Diagram (4) Rev.2.10 Aug 25, 2006 page 51 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 5 V (For 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) td(BCLK-CS) 4ns.min 25ns.max CSi td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE t2d5(nBsC.mLKax-ALE) th(BCLK-ALE) th(RD-AD) -4ns.min 0ns.min ALE td(BCLK-RD) th(BCLK-RD) 25ns.max 0ns.min RD tac2(RD-DB) (2.5 ✕ tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) th(RD-DB) 40ns.min 0ns.min Write timing tcyc BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(WR-AD) 25ns.max th(BCLK-ALE) (0.5 ✕ tcyc-10)ns.min -4ns.min ALE td(BCLK-WR) t0hn(sB.mCLinK-WR) 25ns.max WR, WRL WRH td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min DBi Hi-Z td(DB-WR) th(WR-DB) (1.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min 1 tcyc= f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage: VOL = 0.4 V, VOH = 2.4 V Figure 5.7 Timing Diagram (5) Rev.2.10 Aug 25, 2006 page 52 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 5 V (For 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) td(BCLK-CS) 4ns.min 25ns.max CSi td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE t2d5(nBsC.mLKax-ALE) th(BCLK-ALE) th(RD-AD) -4ns.min 0ns.min ALE td(BCLK-RD) th(BCLK-RD) 25ns.max 0ns.min RD tac2(RD-DB) (3.5 ✕ tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) th(RD-DB) 40ns.min 0ns.min Write timing tcyc BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE t2d5(nBsC.mLKax-ALE) th(BCLK-ALE) (t0h.(5W ✕R -tAcyDc)-10)ns.m in -4ns.min ALE td(BCLK-WR) th(BCLK-WR) 25ns.max 0ns.min WR, WRL WRH td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min DBi Hi-Z t(2d.(5D ✕B- WtcyRc)-40)ns.min (t0h.(5W ✕R -tDcyBc)-10)ns.min 1 tcyc= f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage: VOL = 0.4 V, VOH = 2.4 V Figure 5.8 Timing Diagram (6) Rev.2.10 Aug 25, 2006 page 53 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 5 V (For 1- or 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BC2L5Kns-C.mSa)x tcyc (0.5 ✕t htc(yRcD-1-C0)Sn)s.min th(4BnCs.LmKi-nCS) CSi td(0(A.5D ✕-A tLcEyc) -25)ns.min (t0h.(5A ✕LE t-cAyDc-)15)ns.min ADi Address Data input Address /DBi tdZ(RD-AD) 8ns.max th(RD-DB) tac3(RD-DB) tSU(DB-RD) 0ns.min (1.5 ✕ tcyc-45)ns.max 40ns.min td(AD-RD) td(BCLK-AD) 0ns.min th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(RD-AD) 25ns.max -4ns.min (0.5 ✕ tcyc-10)ns.min ALE td(BCLK-RD) th(BCLK-RD) 25ns.max 0ns.min RD Write timing BCLK td(BCLK-CS) tcyc th(WR-CS) th(BCLK-CS) (0.5 ✕ tcyc-10)ns.min 4ns.min 25ns.max CSi td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min ADi Address Data output Address /DBi td(AD-ALE) (1.5 ✕td t(cDyBc--W40R)n)s.min (0.5t h✕(W tcRy-cD-1B0))ns.min (0.5 ✕ tcyc-25)ns.min td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) td(AD-WR) th(WR-AD) 25ns.max -4ns.min 0ns.min (0.5 ✕ tcyc-10)ns.min ALE td(BCLK-WR) th(BCLK-WR) 25ns.max 0ns.min WR,WRL, WRH 1 tcyc= f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage: VOL = 0.4 V, VOH = 2.4 V Figure 5.9 Timing Diagram (7) Rev.2.10 Aug 25, 2006 page 54 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 5 V (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK th(RD-CS) th(BCLK-CS) td(BCLK-CS) (0.5 ✕ tcyc-10)ns.min 4ns.min 25ns.max CSi td(AD-ALE) (0.5 ✕ tcyc-25)ns.min th(ALE-AD) (0.5 ✕ tcyc-15)ns.min ADi /DBi Address Data input tdZ(RD-AD) th(RD-DB) td(BCLK-AD) td(AD-RD) 8ns.max tac3(RD-DB) tSU(DB-RD) 0ns.min th(BCLK-AD) ADi 25ns.max 0ns.min (2.5 ✕ tcyc-45)ns.max 40ns.min 4ns.min BHE (no multiplex) t2d5(nBsC.mLKax-ALE) th(BCLK-ALE) t(0h.(5R ✕D- tAcDyc)-10)ns.min -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 0ns.min 25ns.max RD Write timing tcyc BCLK t2d5(nBsC.mLKax-CS) (0.5 ✕ tcyc-t1h0(W)nRs.-mCiSn ) 4thn(sB.mCLinK-CS) CSi td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min ADi Address Data output /DBi (0t.d5( A✕D t-cAyLc-E2)5)ns.min td(DB-WR) th(WR-DB) (2.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE (no multiplex) t2d5(nBsC.mLKax-ALE) t-4hn(Bs.CmLiKn-ALE) td(AD-WR) t (h0(.W5 R✕- AtcDyc)-10)ns.min ALE 0ns.min th(BCLK-WR) td(BCLK-WR) 0ns.min WR, WRL 25ns.max WRH 1 tcyc= f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage: VOL = 0.4 V, VOH = 2.4 V Figure 5.10 Timing Diagram (8) Rev.2.10 Aug 25, 2006 page 55 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Table 5.28 Electrical Characteristics (1) VCC = 3.3 V Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. VOH HIGH output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –1 mA VCC-0.5 VCC V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VOH HIGH output XOUT HIGHPOWER IOH = –0.1 mA VCC-0.5 VCC V voltage LOWPOWER IOH = –50 µA VCC-0.5 VCC HIGH output XCOUT HIGHPOWER With no load applied 2.5 V voltage LOWPOWER With no load applied 1.6 VOL LOW output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 1 mA 0.5 V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VOL LOW output XOUT HIGHPOWER IOL = 0.1 mA 0.5 V voltage LOWPOWER IOL = 50 µA 0.5 LOW output XCOUT HIGHPOWER With no load applied 0 V voltage LOWPOWER With no load applied 0 _________ _______ VT+-VT- Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, 0.2 0.8 V ________ ________ _____________________________ _________ INT0 to INT8, NMI, ADTRG, CTS0 to CTS2, SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK6, _____ _____ TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SIN3 to SIN6 _____________ VT+-VT- Hysteresis RESET 0.2 1.8 V IIH HIGH input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 3.3 V 4.0 µA current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, ____________ XIN, RESET, CNVSS, BYTE IIL LOW input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V –4.0 µA current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, ____________ XIN, RESET, CNVSS, BYTE RPULLUP Pull-up P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V 50 100 500 kΩ resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 RfXIN Feedback resistance XIN 3.0 MΩ RfXCIN Feedback resistance XCIN 25 MΩ VRAM RAM retention voltage At stop mode 2.0 V NOTES: 1. Referenced to VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified. ________ ________ 2. P11 to P14, INT6 to INT8, CLK5, CLK6, SIN5, and SIN6 are only in the 128-pin version. Rev.2.10 Aug 25, 2006 page 56 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC = 3.3 V (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) Table 5.29 External Clock Input (XIN Input) Standard Symbol Parameter Unit Min. Max. tC External clock input cycle time 62.5 ns tw(H) External clock input HIGH pulse width 25 ns tw(L) External clock input LOW pulse width 25 ns tr External clock rise time 15 ns tf External clock fall time 15 ns Table 5.30 Memory Expansion Mode and Microprocessor Mode Standard Symbol Parameter Unit Min. Max. tac1(RD-DB) Data input access time (for setting with no wait) (NOTE 1) ns tac2(RD-DB) Data input access time (for setting with wait) (NOTE 2) ns tac3(RD-DB) Data input access time (when accessing multiplexed bus area) (NOTE 3) ns tsu(DB-RD) Data input setup time 50 ns ________ tsu(RDY-BCLK) RDY input setup time 40 ns __________ tsu(HOLD-BCLK) HOLD input setup time 50 ns th(RD-DB) Data input hold time 0 ns ________ th(BCLK-RDY) RDY input hold time 0 ns __________ th(BCLK-HOLD) HOLD input hold time 0 ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 60 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: (n –0.5) ✕ 109 – 60 [ns] n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting. f(BCLK) 3. Calculated according to the BCLK frequency as follows: (n –0.5) ✕ 109 – 60 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting. f(BCLK) Rev.2.10 Aug 25, 2006 page 57 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC = 3.3 V (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) Table 5.31 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 150 ns tw(TAH) TAiIN input HIGH pulse width 60 ns tw(TAL) TAiIN input LOW pulse width 60 ns Table 5.32 Timer A Input (Gating Input in Timer Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 600 ns tw(TAH) TAiIN input HIGH pulse width 300 ns tw(TAL) TAiIN input LOW pulse width 300 ns Table 5.33 Timer A Input (External Trigger Input in One-shot Timer Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 300 ns tw(TAH) TAiIN input HIGH pulse width 150 ns tw(TAL) TAiIN input LOW pulse width 150 ns Table 5.34 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Standard Symbol Parameter Unit Min. Max. tw(TAH) TAiIN input HIGH pulse width 150 ns tw(TAL) TAiIN input LOW pulse width 150 ns Table 5.35 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(UP) TAiOUT input cycle time 3000 ns tw(UPH) TAiOUT input HIGH pulse width 1500 ns tw(UPL) TAiOUT input LOW pulse width 1500 ns tsu(UP-TIN) TAiOUT input setup time 600 ns th(TIN-UP) TAiOUT input hold time 600 ns Table 5.36 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 2 µs tsu(TAIN-TAOUT) TAiOUT input setup time 500 ns tsu(TAOUT-TAIN) TAiIN input setup time 500 ns Rev.2.10 Aug 25, 2006 page 58 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC = 3.3 V (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) Table 5.37 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(TB) TBiIN input cycle time (counted on one edge) 150 ns tw(TBH) TBiIN input HIGH pulse width (counted on one edge) 60 ns tw(TBL) TBiIN input LOW pulse width (counted on one edge) 60 ns tc(TB) TBiIN input cycle time (counted on both edges) 300 ns tw(TBH) TBiIN input HIGH pulse width (counted on both edges) 120 ns tw(TBL) TBiIN input LOW pulse width (counted on both edges) 120 ns Table 5.38 Timer B Input (Pulse Period Measurement Mode) Standard Symbol Parameter Unit Min. Max. tc(TB) TBiIN input cycle time 600 ns tw(TBH) TBiIN input HIGH pulse width 300 ns tw(TBL) TBiIN input LOW pulse width 300 ns Table 5.39 Timer B Input (Pulse Width Measurement Mode) Standard Symbol Parameter Unit Min. Max. tc(TB) TBiIN input cycle time 600 ns tw(TBH) TBiIN input HIGH pulse width 300 ns tw(TBL) TBiIN input LOW pulse width 300 ns Table 5.40 A/D Trigger Input Standard Symbol Parameter Unit Min. Max. _____________ tC(AD) ADTRG input cycle time (trigger able minimum) 1500 ns _____________ tw(ADL) ADTRG input LOW pulse width 200 ns Table 5.41 Serial Interface Standard Symbol Parameter Unit Min. Max. tc(CK) CLKi input cycle time 300 ns tw(CKH) CLKi input HIGH pulse width 150 ns tw(CKL) CLKi input LOW pulse width 150 ns td(C-Q) TXDi output delay time 160 ns th(C-Q) TXDi hold time 0 ns tsu(D-C) RXDi input setup time 100 ns th(C-D) RXDi input hold time 90 ns _______ Table 5.42 External Interrupt INTi Input Standard Symbol Parameter Unit Min. Max. _______ tw(INH) INTi input HIGH pulse width 380 ns _______ tw(INL) INTi input LOW pulse width 380 ns Rev.2.10 Aug 25, 2006 page 59 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC = 3.3 V (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 5.43 Memory Expansion Mode and Microprocessor Mode (for setting with no wait) Measuring Standard Symbol Parameter Unit Condition Min. Max. td(BCLK-AD) Address output delay time Figure 5.11 30 ns th(BCLK-AD) Address output hold time (in relation to BCLK) 4 ns th(RD-AD) Address output hold time (in relation to RD) 0 ns th(WR-AD) Address output hold time (in relation to WR) (NOTE 1) ns td(BCLK-CS) Chip select output delay time 30 ns th(BCLK-CS) Chip select output hold time (in relation to BCLK) 4 ns td(BCLK-ALE) ALE signal output delay time 25 ns th(BCLK-ALE) ALE signal output hold time –4 ns td(BCLK-RD) RD signal output delay time 30 ns th(BCLK-RD) RD signal output hold time 0 ns td(BCLK-WR) WR signal output delay time 30 ns th(BCLK-WR) WR signal output hold time 0 ns td(BCLK-DB) Data output delay time (in relation to BCLK) 40 ns th(BCLK-DB) Data output hold time (in relation to BCLK) (3) 4 ns td(DB-WR) Data output delay time (in relation to WR) (NOTE 2) ns th(WR-DB) Data output hold time (in relation to WR) (3) (NOTE 1) ns __________ td(BCLK-HLDA) HLDA output delay time 40 ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 10 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 40 [ns] f(BCLK) is 12.5 MHz or less. f(BCLK) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. R Hold time of data bus varies with capacitor volume DBi and pull-up (pull-down) resistance value. C Hold time of data bus is expressed in t = – CR ✕ ln (1 – V / V ) OL CC by a circuit of the right figure. For example, when VOL = 0.2 VCC, C = 30 pF, P0 P1 R =1 kΩ, hold time of output “L” level is P2 30 pF P3 t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns. P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 NOTE: 1. P11 to P14 are only in the 128-pin version. Figure 5.11 Port P0 to P14 Measurement Circuit Rev.2.10 Aug 25, 2006 page 60 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC = 3.3 V (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 5.44 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access) Measuring Standard Symbol Parameter Unit Condition Min. Max. td(BCLK-AD) Address output delay time Figure 5.11 30 ns th(BCLK-AD) Address output hold time (in relation to BCLK) 4 ns th(RD-AD) Address output hold time (in relation to RD) 0 ns th(WR-AD) Address output hold time (in relation to WR) (NOTE 1) ns td(BCLK-CS) Chip select output delay time 30 ns th(BCLK-CS) Chip select output hold time (in relation to BCLK) 4 ns td(BCLK-ALE) ALE signal output delay time 25 ns th(BCLK-ALE) ALE signal output hold time –4 ns td(BCLK-RD) RD signal output delay time 30 ns th(BCLK-RD) RD signal output hold time 0 ns td(BCLK-WR) WR signal output delay time 30 ns th(BCLK-WR) WR signal output hold time 0 ns td(BCLK-DB) Data output delay time (in relation to BCLK) 40 ns th(BCLK-DB) Data output hold time (in relation to BCLK) (3) 4 ns td(DB-WR) Data output delay time (in relation to WR) (NOTE 2) ns th(WR-DB) Data output hold time (in relation to WR) (3) (NOTE 1) ns __________ td(BCLK-HLDA) HLDA output delay time 40 ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 10 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: (n – 0.5) ✕ 109 n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting. – 40 [ns] f(BCLK) When n = 1, f(BCLK) is 12.5 MHz or less. 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. R Hold time of data bus varies with capacitor volume DBi and pull-up (pull-down) resistance value. C Hold time of data bus is expressed in t = – CR ✕ ln (1 – V / V ) OL CC by a circuit of the right figure. For example, when V = 0.2 V , C = 30 pF, OL CC R =1 kΩ, hold time of output “L” level is t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 V / V ) = 6.7 ns. CC CC Rev.2.10 Aug 25, 2006 page 61 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC = 3.3 V (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 5.45 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) Measuring Standard Symbol Parameter Unit Condition Min. Max. td(BCLK-AD) Address output delay time Figure 5.11 50 ns th(BCLK-AD) Address output hold time (in relation to BCLK) 4 ns th(RD-AD) Address output hold time (in relation to RD) (NOTE 1) ns th(WR-AD) Address output hold time (in relation to WR) (NOTE 1) ns td(BCLK-CS) Chip select output delay time 50 ns th(BCLK-CS) Chip select output hold time (in relation to BCLK) 4 ns th(RD-CS) Chip select output hold time (in relation to RD) (NOTE 1) ns th(WR-CS) Chip select output hold time (in relation to WR) (NOTE 1) ns td(BCLK-RD) RD signal output delay time 40 ns th(BCLK-RD) RD signal output hold time 0 ns td(BCLK-WR) WR signal output delay time 40 ns th(BCLK-WR) WR signal output hold time 0 ns td(BCLK-DB) Data output delay time (in relation to BCLK) 50 ns th(BCLK-DB) Data output hold time (in relation to BCLK) 4 ns td(DB-WR) Data output delay time (in relation to WR) (NOTE 2) ns th(WR-DB) Data output hold time (in relation to WR) (NOTE 1) ns __________ td(BCLK-HLDA) HLDA output delay time 40 ns td(BCLK-ALE) ALE signal output delay time (in relation to BCLK) 25 ns th(BCLK-ALE) ALE signal output hold time (in relation to BCLK) –4 ns td(AD-ALE) ALE signal output delay time (in relation to Address) (NOTE 3) ns th(ALE-AD) ALE signal output hold time (rin relation to Address) (NOTE 4) ns td(AD-RD) RD signal output delay from the end of Address 0 ns td(AD-WR) WR signal output delay from the end of Address 0 ns tdZ(RD-AD) Address output floating start time 8 ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 10 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: (n –0.5) ✕ 109 – 50 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting. f(BCLK) 3. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 40 [ns] f(BCLK) 4. Calculated according to the BCLK frequency as follows: 0.5 ✕ 109 – 15 [ns] f(BCLK) Rev.2.10 Aug 25, 2006 page 62 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) VCC = 3.3 V XIN input tr tw(H) tr tw(L) tc tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge th(TIN—UP)tsu(UP—TIN) is selected) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tC(TA) TAiIN input tsu(TAIN—TAOUT) tsu(TAIN—TAOUT) tsu(TAOUT—TAIN) TAiOUT input tsu(TAOUT—TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C—Q) TXDi td(C—Q) tsu(D—C) th(C—D) RXDi tw(INL) INTi input tw(INH) Figure 5.12 Timing Diagram (1) Rev.2.10 Aug 25, 2006 page 63 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) VCC = 3.3 V Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY–BCLK) th(BCLK–RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD–BCLK) th(BCLK–HOLD) HOLD input HLDA output td(BCLK–HLDA) td(BCLK–HLDA) P0, P1, P2, Hi–Z P3, P4, P5_0 to P5_2 (1) NOTE: 1. The above pins are set to high-impedance regardless of the input level of the BYTE pin, the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register. Measuring conditions : VCC = 3.3 V Input timing voltage : Determined with VIL = 0.6 V, VIH = 2.7 V Output timing voltage: Determined with VOL = 1.65 V, VOH = 1.65 V Figure 5.13 Timing Diagram (2) Rev.2.10 Aug 25, 2006 page 64 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 3.3 V (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(RD-AD) 30ns.max -4ns.min 0ns.min ALE td(BCLK-RD) th(BCLK-RD) 30ns.max 0ns.min RD tac1(RD-DB) (0.5 ✕ tcyc-60)ns.max DBi Hi-Z tSU(DB-RD) th(RD-DB) 50ns.min 0ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(WR-AD) 30ns.max -4ns.min (0.5 ✕ tcyc-10)ns.min ALE td(BCLK-WR) th(BCLK-WR) 30ns.max 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min Hi-Z DBi td(DB-WR) th(WR-DB) 1 (0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min tcyc= f(BCLK) Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage: VOL = 1.65 V, VOH = 1.65 V Figure 5.14 Timing Diagram (3) Rev.2.10 Aug 25, 2006 page 65 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 3.3 V (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(RD-AD) 30ns.max -4ns.min 0ns.min ALE td(BCLK-RD) th(BCLK-RD) 30ns.max 0ns.min RD tac2(RD-DB) (1.5 ✕ tcyc-60)ns.max DBi Hi-Z th(RD-DB) tSU(DB-RD) 0ns.min 50ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(WR-AD) 30ns.max -4ns.min (0.5 ✕ tcyc-10)ns.min ALE td(BCLK-WR) th(BCLK-WR) 30ns.max 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min Hi-Z DBi td(DB-WR) th(WR-DB) 1 (0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min tcyc= f(BCLK) Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage: VOL = 1.65 V, VOH = 1.65 V Figure 5.15 Timing Diagram (4) Rev.2.10 Aug 25, 2006 page 66 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 3.3 V (For 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) td(BCLK-CS) 4ns.min 30ns.max CSi td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE t3d0(nBsC.mLKax-ALE) th(BCLK-ALE) th(RD-AD) -4ns.min 0ns.min ALE td(BCLK-RD) th(BCLK-RD) 30ns.max 0ns.min RD tac2(RD-DB) (2.5 ✕ tcyc-60)ns.max DBi Hi-Z tSU(DB-RD) th(RD-DB) 50ns.min 0ns.min Write timing tcyc BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(WR-AD) 30ns.max th(BCLK-ALE) (0.5 ✕ tcyc-10)ns.min -4ns.min ALE td(BCLK-WR) t0hn(sB.mCLinK-WR) 30ns.max WR, WRL WRH td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min DBi Hi-Z td(DB-WR) th(WR-DB) (1.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min 1 tcyc= f(BCLK) Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage: VOL = 1.65 V, VOH = 1.65 V Figure 5.16 Timing Diagram (5) Rev.2.10 Aug 25, 2006 page 67 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 3.3 V (For 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) td(BCLK-CS) 4ns.min 30ns.max CSi td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE t3d0(nBsC.mLKax-ALE) th(BCLK-ALE) th(RD-AD) -4ns.min 0ns.min ALE td(BCLK-RD) th(BCLK-RD) 30ns.max 0ns.min RD tac2(RD-DB) (3.5 ✕ tcyc-60)ns.max DBi Hi-Z tSU(DB-RD) th(RD-DB) 50ns.min 0ns.min Write timing tcyc BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE t3d0(nBsC.mLKax-ALE) th(BCLK-ALE) (t0h.(5W ✕R -tAcyDc)-10)ns.m in -4ns.min ALE td(BCLK-WR) th(BCLK-WR) 30ns.max 0ns.min WR, WRL WRH td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min DBi Hi-Z t(2d.(5D ✕B- WtcyRc)-40)ns.min (t0h.(5W ✕R -tDcyBc)-10)ns.min 1 tcyc= f(BCLK) Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage: VOL = 1.65 V, VOH = 1.65 V Figure 5.17 Timing Diagram (6) Rev.2.10 Aug 25, 2006 page 68 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 3.3 V (For 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BC4L0Kns-C.mSa)x tcyc (0.5 ✕t htc(yRcD-1-C0)Sn)s.min th(4BnCs.LmKi-nCS) CSi td(0(A.5D ✕-A tLcEyc) -40)ns.min (t0h.(5A ✕LE t-cAyDc-)15)ns.min ADi Address Data input Address /DBi tdZ(RD-AD) 8ns.max th(RD-DB) tac3(RD-DB) tSU(DB-RD) 0ns.min (1.5 ✕ tcyc-60)ns.max 50ns.min td(AD-RD) td(BCLK-AD) 0ns.min th(BCLK-AD) 40ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(RD-AD) 40ns.max -4ns.min (0.5 ✕ tcyc-10)ns.min ALE td(BCLK-RD) th(BCLK-RD) 40ns.max 0ns.min RD Write timing BCLK td(BCLK-CS) tcyc th(WR-CS) th(BCLK-CS) (0.5 ✕ tcyc-10)ns.min 4ns.min 40ns.max CSi td(BCLK-DB) th(BCLK-DB) 50ns.max 4ns.min ADi Address Data output Address /DBi td(AD-ALE) (1.5 ✕td t(cDyBc--W50R)n)s.min (0.5t h✕(W tcRy-cD-1B0))ns.min (0.5 ✕ tcyc-40)ns.min td(BCLK-AD) th(BCLK-AD) 40ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) td(AD-WR) th(WR-AD) 40ns.max -4ns.min 0ns.min (0.5 ✕ tcyc-10)ns.min ALE td(BCLK-WR) th(BCLK-WR) 40ns.max 0ns.min WR,WRL, WRH 1 tcyc= f(BCLK) Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage: VOL = 1.65 V, VOH = 1.65 V Figure 5.18 Timing Diagram (7) Rev.2.10 Aug 25, 2006 page 69 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 3.3 V (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK th(RD-CS) th(BCLK-CS) td(BCLK-CS) (0.5 ✕ tcyc-10)ns.min 6ns.min 40ns.max CSi td(AD-ALE) (0.5 ✕ tcyc-40)ns.min th(ALE-AD) (0.5 ✕ tcyc-15)ns.min ADi /DBi Address Data input tdZ(RD-AD) th(RD-DB) td(BCLK-AD) td(AD-RD) 8ns.max tac3(RD-DB) tSU(DB-RD) 0ns.min th(BCLK-AD) ADi 40ns.max 0ns.min (2.5 ✕ tcyc-60)ns.max 50ns.min 4ns.min BHE (no multiplex) t4d0(nBsC.mLKax-ALE) th(BCLK-ALE) t(0h.(5R ✕D- tAcDyc)-10)ns.min -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 0ns.min 40ns.max RD Write timing tcyc BCLK t4d0(nBsC.mLKax-CS) (0.5 ✕ tcyc-t1h0(W)nRs.-mCiSn ) 4thn(sB.mCLinK-CS) CSi td(BCLK-DB) th(BCLK-DB) 50ns.max 4ns.min ADi Address Data output /DBi (0t.d5( A✕D t-cAyLc-E4)0)ns.min td(DB-WR) th(WR-DB) (2.5 ✕ tcyc-50)ns.min (0.5 ✕ tcyc-10)ns.min td(BCLK-AD) th(BCLK-AD) 40ns.max 4ns.min ADi BHE (no multiplex) t4d0(nBsC.mLKax-ALE) t-4hn(Bs.CmLiKn-ALE) td(AD-WR) t (h0(.W5 R✕- AtcDyc)-10)ns.min ALE 0ns.min th(BCLK-WR) td(BCLK-WR) 0ns.min WR, WRL 40ns.max WRH 1 tcyc= f(BCLK) Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage: VOL = 1.65 V, VOH = 1.65 V Figure 5.19 Timing Diagram (8) Rev.2.10 Aug 25, 2006 page 70 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (T/V-ver.) 5.2 Electrical Characteristics (T/V-ver.) Table 5.46 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit VCC Supply voltage (VCC1 = VCC2) VCC = AVCC –0.3 to 6.5 V AVCC Analog supply voltage VCC = AVCC –0.3 to 6.5 V _____________ VI Input RESET, CNVSS, BYTE, –0.3 to VCC+0.3 V voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, VREF, XIN P7_1, P9_1 –0.3 to 6.5 V VO Output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, –0.3 to VCC+0.3 V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XOUT P7_1, P9_1 –0.3 to 6.5 V Pd Power dissipation Topr = 25°C 700 mW Topr Operating ambient During MCU operation T version: –40 to 85 °C temperature V version: –40 to 125 (option) During flash memory program and 0 to 60 erase operation Tstg Storage temperature –65 to 150 °C option: All options are on request basis. NOTE: 1. Ports P11 to P14 are only in the 128-pin version. Rev.2.10 Aug 25, 2006 page 71 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (T/V-ver.) Table 5.47 Recommended Operating Conditions (1) (1) Standard Symbol Parameter Unit Min. Typ. Max. VCC Supply voltage (VCC1 = VCC2) 4.2 5.0 5.5 V AVCC Analog supply voltage VCC V VSS Supply voltage 0 V AVSS Analog supply voltage 0 V VIH HIGH input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, 0.8 VCC VCC V voltage P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, _____________ P14_0, P14_1, XIN, RESET, CNVSS, BYTE P7_1, P9_1 0.8 VCC 6.5 V VIL LOW input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, 0 0.2 VCC V voltage P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, _____________ P14_0, P14_1, XIN, RESET, CNVSS, BYTE IOH(peak) HIGH peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, –10.0 mA output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 IOH(avg) HIGH average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, –5.0 mA output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 IOL(peak) LOW peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, 10.0 mA output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 IOL(avg) LOW average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, 5.0 mA output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 NOTES: 1.Referenced to VCC = 4.2 to 5.5 V at Topr = –40 to 85°C unless otherwise specified. 2.Average output current values during 100 ms period. 3.The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be 80 mA max. The total IOL(peak) for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80 mA max. The total IOH(peak) for ports P0, P1, and P2 must be –40 mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be –40 mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be –40 mA max. The total IOH(peak) for ports P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be –40 mA max. 4.P11 to P14 are only in the 128-pin version. Rev.2.10 Aug 25, 2006 page 72 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (T/V-ver.) Table 5.48 Recommended Operating Conditions (2) (1) Standard Symbol Parameter Unit Min. Typ. Max. f(XIN) Main clock input oscillation No wait Flash memory VCC = 4.2 to 5.5 V 0 16 MHz frequency (2) (3) (4) version f(XCIN) Sub clock oscillation frequency 32.768 50 kHz f(Ring) On-chip oscillation frequency 1 MHz f(PLL) PLL clock oscillation frequency 16 20 MHz f(BCLK) CPU operation clock VCC = 4.2 to 5.5 V 0 20 MHz tsu(PLL) PLL frequency synthesizer stabilization wait time 20 ms NOTES: 1.Referenced to VCC = 4.2 to 5.5 V at Topr = –40 to 85°C unless z] Main clock input oscillation frequency H M (Flash memory version: no wait) otherwise specified. y [ 2.Relationship between main clock oscillation frequency and supply nc 16.0 e u voltage is shown right. eq 3.Execute program/erase of flash memory by VCC = 5.0 ± 0.5 V. m fr u m 4.When using over 16 MHz, use PLL clock. PLL clock oscillation xi a m frequency which can be used is 16 MHz or 20 MHz. g n ati er op 0.0 N) 4.2 5.5 f(XI VCC [V] (main clock: no division) Rev.2.10 Aug 25, 2006 page 73 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (T/V-ver.) Table 5.49 Electrical Characteristics (1) (1) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. VOH HIGH output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –5 mA VCC-2.0 VCC V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VOH HIGH output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –200 µA VCC-0.3 VCC V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VOH HIGH output XOUT HIGHPOWER IOH = –1 mA 3.0 VCC V voltage LOWPOWER IOH = –0.5 mA 3.0 VCC HIGH output XCOUT HIGHPOWER With no load applied 2.5 V voltage LOWPOWER With no load applied 1.6 VOL LOW output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 5 mA 2.0 V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VOL LOW output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 200 µA 0.45 V voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VOL LOW output XOUT HIGHPOWER IOL = 1 mA 2.0 V voltage LOWPOWER IOL = 0.5 mA 2.0 LOW output XCOUT HIGHPOWER With no load applied 0 V voltage LOWPOWER With no load applied 0 _________ _________ VT+-VT- Hysteresis TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT8, 0.2 1.0 V ______________________ __________ __________ NMI, ADTRG, CTS0 to CTS2, SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK6, TA0OUT to TA4OUT, ______ ______ KI0 to KI3, RXD0 to RXD2, SIN3 to SIN6 _____________ VT+-VT- Hysteresis RESET 0.2 2.5 V IIH HIGH input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 5 V 5.0 µA current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, ____________ XIN, RESET, CNVSS, BYTE IIL LOW input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V –5.0 µA current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, ____________ XIN, RESET, CNVSS, BYTE RPULLUP Pull-up P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V 30 50 170 kΩ resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 RfXIN Feedback resistance XIN 1.5 MΩ RfXCIN Feedback resistance XCIN 15 MΩ VRAM RAM retention voltage At stop mode 2.0 V NOTES: 1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified. ________ ________ 2. P11 to P14, INT6 to INT8, CLK5, CLK6, SIN5, and SIN6 are only in the 128-pin version. Rev.2.10 Aug 25, 2006 page 74 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (T/V-ver.) Table 5.50 Electrical Characteristics (2) (1) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. ICC Power supply Output pins are open Flash memory f(BCLK) = 20 MHz, 21 36 mA current and other pins are VSS. PLL operation, (VCC = 4.2 to 5.5 V) No division On-chip oscillation, 1.8 mA No division Flash memory f(BCLK) = 10 MHz, 15 mA Program VCC = 5 V Flash memory f(BCLK) = 10 MHz, 25 mA Erase VCC = 5 V Flash memory f(BCLK) = 32 kHz, 25 µA Low power dissipation mode, RAM (2) f(BCLK) = 32 kHz, 420 µA Low power dissipation mode, Flash memory (2) Flash memory On-chip oscillation, 50 µA Wait mode f(BCLK) = 32 kHz, 8.5 µA Wait mode (3), Oscillation capacity High f(BCLK) = 32 kHz, 3.0 µA Wait mode (3), Oscillation capacity Low Stop mode, 0.8 3.0 µA Topr = 25°C NOTES: 1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified. 2. This indicates the memory in which the program to be executed exists. 3. With one timer operated using fC32. Rev.2.10 Aug 25, 2006 page 75 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (T/V-ver.) Table 5.51 A/D Conversion Characteristics (1) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. – Resolution VREF = VCC 10 Bit INL integral 10 bits VREF ANEX0, ANEX1 input, AN0 to AN7 input, ±3 LSB nonlinearity = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input erro = 5 V External operation amp connection mode ±7 LSB 8 bits VREF = AVCC = VCC = 5 V ±2 LSB – Absolute 10 bits VREF ANEX0, ANEX1 input, AN0 to AN7 input, ±3 LSB accuracy = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 5 V External operation amp connection mode ±7 LSB 8 bits VREF = AVCC = VCC = 5 V ±2 LSB DNL Differential nonlinearity error ±1 LSB – Offset error ±3 LSB – Gain error ±3 LSB RLADDER Resistor ladder VREF = VCC 10 40 kΩ tCONV 10-bit conversion time, VREF = VCC = 5 V, φAD = 10 MHz 3.3 µs sample & hold available 8-bit conversion time, VREF = VCC = 5 V, φAD = 10 MHz 2.8 µs sample & hold available tSAMP Sampling time 0.3 µs VREF Reference voltage 2.0 VCC V VIA Analog input voltage 0 VREF V NOTES: 1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified. 2. φAD frequency must be 10 MHz or less. 3. When sample & hold is disabled, φAD frequency must be 250 kHz or more in addition to a limit of NOTE 2. When sample & hold is enabled, φAD frequency must be 1 MHz or more in addition to a limit of NOTE 2. Table 5.52 D/A conversion Characteristics (1) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. – Resolution 8 Bits – Absolute accuracy 1.0 % tsu Setup time 3 µs RO Output tesistance 4 10 20 kΩ IVREF Reference power supply input current (NOTE 2) 1.5 mA NOTES: 1.Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified. 2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h. The resistor ladder of the A/D converter is not included. Also, the IVREF will flow even if VREF is disconnected by the ADCON1 register. Rev.2.10 Aug 25, 2006 page 76 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (T/V-ver.) Table 5.53 Flash Memory Version Electrical Characteristics (1) Standard Symbol Parameter Unit Min. Typ. Max. - Programming and erasure endurance (2) 100 cycle - Word program time (VCC = 5.0 V) 25 200 µs - Lock bit program time 25 200 µs - Block erase time 4-Kbyte block 0.3 4 s (VCC = 5.0 V) 8-Kbyte block 0.3 4 s 32-Kbyte block 0.5 4 s 64-Kbyte block 0.8 4 s - Erase all unlocked blocks time 4 ✕ n (3) s tps Flash memory circuit stabilization wait time 15 µs NOTES: 1. Referenced to VCC = 4.5 to 5.5 V, Topr = 0 to 60°C unless otherwise specified. 2. Programming and erasure endurance refers to the number of times a block erase can be performed. If the programming and erasure endurance is n (n = 100), each block can be erased n times. For example, if a 4-Kbyte block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as one programming and erasure endurance. Data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 3. n denotes the number of blocks to erase. Table 5.54 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics (at Topr = 0 to 60°C) Flash Program, Erase Voltage Flash Read Operation Voltage VCC = 5.0 ± 0.5 V VCC = 4.2 to 5.5 V Table 5.55 Power Supply Circuit Timing Characteristics Measuring Standard Symbol Parameter Unit Condition Min. Typ. Max. td(P-R) Time for internal power supply stabilization during powering-on VCC = 4.2 to 5.5 V 2 ms td(R-S) STOP release time 150 µs td(W-S) Low power dissipation mode wait mode release time 150 µs td(P-R) Time for internal power supply VCC stabilization during powering-on td(P-R) CPU clock td(R-S) Interrupt for (a) Stop mode release STOP release time or (b) Wait mode release td(W-S) Low power dissipation mode CPU clock wait mode release time (a) td(R-S) (b) td(W-S) Figure 5.20 Power Supply Circuit Timing Diagram Rev.2.10 Aug 25, 2006 page 77 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (T/V-ver.) Timing Requirements VCC = 5 V (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) Table 5.56 External Clock Input (XIN Input) Standard Symbol Parameter Unit Min. Max. tC External clock input cycle time 62.5 ns tw(H) External clock input HIGH pulse width 25 ns tw(L) External clock input LOW pulse width 25 ns tr External clock rise time 15 ns tf External clock fall time 15 ns Table 5.57 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 100 ns tw(TAH) TAiIN input HIGH pulse width 40 ns tw(TAL) TAiIN input LOW pulse width 40 ns Table 5.58 Timer A Input (Gating Input in Timer Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 400 ns tw(TAH) TAiIN input HIGH pulse width 200 ns tw(TAL) TAiIN input LOW pulse width 200 ns Table 5.59 Timer A Input (External Trigger Input in One-shot Timer Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 200 ns tw(TAH) TAiIN input HIGH pulse width 100 ns tw(TAL) TAiIN input LOW pulse width 100 ns Table 5.60 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Standard Symbol Parameter Unit Min. Max. tw(TAH) TAiIN input HIGH pulse width 100 ns tw(TAL) TAiIN input LOW pulse width 100 ns Table 5.61 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(UP) TAiOUT input cycle time 2000 ns tw(UPH) TAiOUT input HIGH pulse width 1000 ns tw(UPL) TAiOUT input LOW pulse width 1000 ns tsu(UP-TIN) TAiOUT input setup time 400 ns th(TIN-UP) TAiOUT input hold time 400 ns Table 5.62 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(TA) TAiIN input cycle time 800 ns tsu(TAIN-TAOUT) TAiOUT input setup time 200 ns tsu(TAOUT-TAIN) TAiIN input setup time 200 ns Rev.2.10 Aug 25, 2006 page 78 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (T/V-ver.) Timing Requirements VCC = 5 V (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) Table 5.63 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max. tc(TB) TBiIN input cycle time (counted on one edge) 100 ns tw(TBH) TBiIN input HIGH pulse width (counted on one edge) 40 ns tw(TBL) TBiIN input LOW pulse width (counted on one edge) 40 ns tc(TB) TBiIN input cycle time (counted on both edges) 200 ns tw(TBH) TBiIN input HIGH pulse width (counted on both edges) 80 ns tw(TBL) TBiIN input LOW pulse width (counted on both edges) 80 ns Table 5.64 Timer B Input (Pulse Period Measurement Mode) Standard Symbol Parameter Unit Min. Max. tc(TB) TBiIN input cycle time 400 ns tw(TBH) TBiIN input HIGH pulse width 200 ns tw(TBL) TBiIN input LOW pulse width 200 ns Table 5.65 Timer B Input (Pulse Width Measurement Mode) Standard Symbol Parameter Unit Min. Max. tc(TB) TBiIN input cycle time 400 ns tw(TBH) TBiIN input HIGH pulse width 200 ns tw(TBL) TBiIN input LOW pulse width 200 ns Table 5.66 A/D Trigger Input Standard Symbol Parameter Unit Min. Max. _____________ tC(AD) ADTRG input cycle time (trigger able minimum) 1000 ns _____________ tw(ADL) ADTRG input LOW pulse width 125 ns Table 5.67 Serial Interface Standard Symbol Parameter Unit Min. Max. tc(CK) CLKi Input cycle time 200 ns tw(CKH) CLKi Input HIGH pulse width 100 ns tw(CKL) CLKi Input LOW pulse width 100 ns td(C-Q) TXDi output delay time 80 ns th(C-Q) TXDi hold time 0 ns tsu(D-C) RXDi input setup time 70 ns th(C-D) RXDi input hold time 90 ns _______ Table 5.68 External Interrupt INTi Input Standard Symbol Parameter Unit Min. Max. _______ tw(INH) INTi input HIGH pulse width 250 ns _______ tw(INL) INTi input LOW pulse width 250 ns Rev.2.10 Aug 25, 2006 page 79 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics (T/V-ver.) VCC = 5 V XIN input tr tw(H) tr tw(L) tc tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge th(TIN—UP)tsu(UP—TIN) is selected) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tC(TA) TAiIN input tsu(TAIN—TAOUT) tsu(TAIN—TAOUT) tsu(TAOUT—TAIN) TAiOUT input tsu(TAOUT—TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C—Q) TXDi td(C—Q) tsu(D—C) th(C—D) RXDi tw(INL) INTi input tw(INH) Figure 5.21 Timing Diagram Rev.2.10 Aug 25, 2006 page 80 of 81 REJ03B0058-0210

Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP100-14x14-0.50 PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV 0.6g HD *1 D 75 51 NOTE) 1. DIMENSIONS "*1" AND "*2" 76 50 DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 *2E HE c1 c ReSfyemrebnocleDMimeinnsionN ion mMillimMetaerxs D 13.9 14.0 14.1 E 13.9 14.0 14.1 Terminal cross section A2 1.4 HD 15.8 16.0 16.2 100 26 ZE HAE 15.8 16.0 116.7.2 1 25 A1 0.05 0.1 0.15 Index mark bp 0.15 0.20 0.25 ZD F b1 0.18 c 0.09 0.145 0.20 A A2 c1 0.125 c 0° 8° e 0.5 e y *3 bp x A1 L1L yx 00..0088 ZD 1.0 Detail F ZE 1.0 L 0.35 0.5 0.65 L1 1.0 JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP128-14x20-0.50 PLQP0128KB-A 128P6Q-A 0.9g HD *1 D 102 65 103 64 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. bp 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. b1 c1 c E HE *2 Terminal cross section ReSfyemrebnocleDMimiennsioNn ion mMillimMetaexrs D 19.9 20.0 20.1 E 13.9 14.0 14.1 ZE A2 1.4 128 39 HD 21.8 22.0 22.2 HE 15.8 16.0 16.2 1 38 A 1.7 ZD Index mark F A A2 c bAp1 00..0157 00.1.2225 00..227 b1 0.20 c 0.09 0.145 0.20 A1 L c1 0.125 e y *3 bp x L1 e 0° 0.5 8° DetailF x 0.10 y 0.10 ZD 0.75 ZE 0.75 L 0.35 0.5 0.65 L1 1.0 Rev.2.10 Aug 25, 2006 page 81 of 81 REJ03B0058-0210

REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Data Sheet Description Rev. Date Page Summary 1.00 Jul. 20, 2004 – First edition issued 1.01 Nov. 01, 2004 – Revised edition issued * Revised parts and revised contents are as follows (except for expressional change). 30 Table 5.2 Recommended Operating Conditions (1) •I : Unit is revised from “V” to “mA”. OH(peak) 31 Table 5.3 Recommended Operating Conditions (2) •NOTE 3: “VCC = 3.0 ± 0.3 V” is revised to “VCC = 3.3 ± 0.3 V”. 32 Table 5.4 I , I : “P3_3” is revised to “P3_7” in Parameter. IH IL 35 Table 5.9: VCC = 3.0 ± 0.3 V” is revised to “VCC = 3.3 ± 0.3 V” in Flash Program, Erase Voltage. 1.10 Jul. 01, 2005 – Revised edition issued *The contents of product are revised. (T/V-ver. is added.) *Revised parts and revised contents are as follows (except for expressional change). 2 Table 1.1 Performance outline of M16C/6N Group (100-pin Version: M16C/6NM) • Performance outline of T/V-ver. is added. 3 Table 1.2 Performance outline of M16C/6N Group (128-pin Version: M16C/6NN) • Performance outline of T/V-ver. is added. 5 Table 1.3 Product List is revised. (T/V-ver. is added.) Figure 1.2 Type No., Memory Size, and Package: “Characteristics” is added. 13 FIgure 4.1 SFR Information (1): The value of After Reset in CM2 Register is revised. 19 Figure 4.7 SFR Information (7): NOTE 1 is revised. 32 Table 5.4 Electrical Characteristics (1) • Measuring Condition of V is revised from “L = –200µA” to “L = 200µA”. OL OL OL 33 Table 5.5 Electrical Characteristics (2): Mask ROM (5th item) • “f(XCIN)” is changed to “(f(BCLK)). 34 Table 5.6 A/D Conversion Characteristics: “Tolerance Level Impedance” is deleted. 2.10 Aug.25, 2006 – Revised edition issued * Memory expansion and microprocessor modes are added to Normal-ver.. *Electric Characteristics of T/V-ver. is added. *Revised parts and revised contents are as follows (except for expressional change). 1 1.1 Applications: Comment of T/V-ver. is added. 2 Table 1.1 Fuictions and Specifications for M16C/6N Group (100-pin version) • Operating Mode of Normal-ver. is revised. 3 Table 1.2 Fuictions and Specifications for M16C/6N Group (128-pin version) • Operating Mode of Normal-ver. is revised. 5 Table 1.3 Product Information • Status of development is revised and NOTES 1 and 2 are added. 6 Figure 1.3 Pin Assignments (1): Bus control pins are added and NOTE 2 is added. 7, 8 Tables 1.4 and 1.5 List of Pin Names for 100-pin package (1)(2) are added. 9 Figure 1.4 Pin Assignments (2): Bus control pins are added and NOTE 2 is added. 10 to 12 Tables 1.6 to 1.8 List of Pin Names for 128-pin package (1)(2)(3) are added. 13 to 15 Tables 1.9 to 1.11 Pin Functions (1)(2)(3) are revised. A-1

REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Data Sheet Description Rev. Date Page Summary 2.10 Aug.25, 2006 18 3. Memory: Last 2 sentences (In memory expansion ... / Use T-V-ver.) are added. Figure 3.1 Memory Map: NOTES 1 and 2 are added. 19 Table 4.1 SFR Information (1) • Value of After Reset in PM0 is revised. • CSR Register is added to 0008h. •CSE Register is added to 001Bh. • NOTES 1, 3 and 4 are added. 26 Table 4.8 SFR Information (8) • The value of After Reset in IDB0 register is revised. • The value of After Reset in IDB1 register is revised. 34 Table 4.16 SFR Information (16) • Value of After Reset in PUR1 is revised. • NOTE 1 is added. 36 Table 5.2 Recommended Operating Conditions (1) is partly revised. 37 Table 5.3 Recommended Operating Conditions (2) • Power supply ripple is deleted. (three items) Figure 5.1 Voltage Fluctuation Timing is deleted. 38 Table 5.4 Electrical Characteristics (1) __________ ________ • HOLD and RDY are added to Hysteresis. • Hysteresis XIN is deleted. 41 Table 5.8 Flash Memory Version Electrical Characteristics is revised. 42 Table 5.12 Memory Expansion Mode and Microprocessor Mode is added. 45 to 47 Switching Characteristics are added. 49 to 55 Figures 5.4 to 5.10 Timing Diagram (2) to (8) are added. 56 to 70 Characteristics of 3.3 V in Normal-ver. are added. 71 to 80 5.2 Electrical Characteristics (T/V-ver.) is added. A-2

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