M25P40 Serial Flash Embedded Memory Features M25P40 3V 4Mb Serial Flash Embedded Memory Features • Electronic signature – JEDEC-standard 2-byte signature (2013h) • SPI bus-compatible serial interface – Unique ID code (UID) with 16-byte read-only • 4Mb Flash memory space, available upon request • 75 MHz clock frequency (maximum) – RES command, one-byte signature (12h) for • 2.3V to 3.6V single supply voltage backward compatibility • Page program (up to 256 bytes) in 0.8ms (TYP) • More than 100,000 write cycles per sector • Erase capability • Automotive-grade parts available – Sector erase: 512Kb in 0.6 s (TYP) • Packages (RoHS-compliant) – Bulk erase: 4Mb in 4.5 s (TYP) – SO8N (MN) 150 mils • Write protection – SO8W (MW) 208 mils – Hardware write protection: protected area size – VFDFPN8 (MP) MLP8 6mm x 5mm defined by nonvolatile bits BP0, BP1, BP2 – UFDFPN8 (MC) MLP8 4mm x 3mm • Deep power-down: 1µA (TYP) – UFDFPN8 (MB) MLP8 2mm x 3mm CCMTD-1725822587-8430 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

M25P40 Serial Flash Embedded Memory Features Contents Important Notes and Warnings ......................................................................................................................... 6 Functional Description ..................................................................................................................................... 7 Signal Descriptions ........................................................................................................................................... 9 SPI Modes ...................................................................................................................................................... 10 Operating Features ......................................................................................................................................... 12 Page Programming ..................................................................................................................................... 12 Sector Erase, Bulk Erase .............................................................................................................................. 12 Polling during a Write, Program, or Erase Cycle ............................................................................................ 12 Active Power, Standby Power, and Deep Power-Down .................................................................................. 12 Status Register ............................................................................................................................................ 13 Data Protection by Protocol ........................................................................................................................ 13 Software Data Protection ............................................................................................................................ 13 Hardware Data Protection .......................................................................................................................... 13 Hold Condition .......................................................................................................................................... 15 Configuration and Memory Map ..................................................................................................................... 17 Memory Configuration and Block Diagram .................................................................................................. 17 Memory Map – 4Mb Density ........................................................................................................................... 18 Command Set Overview ................................................................................................................................. 19 WRITE ENABLE .............................................................................................................................................. 21 WRITE DISABLE ............................................................................................................................................. 22 READ IDENTIFICATION ................................................................................................................................. 23 READ STATUS REGISTER ................................................................................................................................ 25 WIP Bit ...................................................................................................................................................... 27 WEL Bit ...................................................................................................................................................... 27 Block Protect Bits ....................................................................................................................................... 27 SRWD Bit ................................................................................................................................................... 27 WRITE STATUS REGISTER .............................................................................................................................. 28 READ DATA BYTES ......................................................................................................................................... 30 READ DATA BYTES at HIGHER SPEED ............................................................................................................ 31 PAGE PROGRAM ............................................................................................................................................ 32 SECTOR ERASE .............................................................................................................................................. 33 BULK ERASE .................................................................................................................................................. 34 DEEP POWER-DOWN ..................................................................................................................................... 35 RELEASE from DEEP POWER-DOWN .............................................................................................................. 36 READ ELECTRONIC SIGNATURE .................................................................................................................... 37 Power-Up/Down and Supply Line Decoupling ................................................................................................. 38 Power-Up Timing and Write Inhibit Voltage Specifications ............................................................................... 40 Maximum Ratings and Operating Conditions .................................................................................................. 41 Electrical Characteristics ................................................................................................................................ 42 AC Characteristics .......................................................................................................................................... 44 Package Information ...................................................................................................................................... 52 Device Ordering Information .......................................................................................................................... 58 Standard Parts ............................................................................................................................................ 58 Automotive Parts ........................................................................................................................................ 59 Revision History ............................................................................................................................................. 60 Rev. H – 05/18 ............................................................................................................................................. 60 Rev. G – 05/13 ............................................................................................................................................. 60 Rev. F – 01/13 ............................................................................................................................................. 60 Rev. E – 08/12 ............................................................................................................................................. 60 Rev. D – 04/12 ............................................................................................................................................. 60 CCMTD-1725822587-8430 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Features Rev. C – 03/12 ............................................................................................................................................. 60 Rev. B – 02/12 ............................................................................................................................................. 60 Rev. A – 09/2011 .......................................................................................................................................... 60 CCMTD-1725822587-8430 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Features List of Figures Figure 1: Logic Diagram ................................................................................................................................... 7 Figure 2: Pin Connections: SO8, MLP8 ............................................................................................................. 8 Figure 3: SPI Modes Supported ...................................................................................................................... 10 Figure 4: Bus Master and Memory Devices on the SPI Bus ............................................................................... 11 Figure 5: Hold Condition Activation ............................................................................................................... 16 Figure 6: Block Diagram ................................................................................................................................ 17 Figure 7: WRITE ENABLE Command Sequence .............................................................................................. 21 Figure 8: WRITE DISABLE Command Sequence ............................................................................................. 22 Figure 9: READ IDENTIFICATION Command Sequence ................................................................................. 24 Figure 10: READ STATUS REGISTER Command Sequence .............................................................................. 25 Figure 11: Status Register Format ................................................................................................................... 25 Figure 12: Status Register Format ................................................................................................................... 26 Figure 13: WRITE STATUS REGISTER Command Sequence ............................................................................. 28 Figure 14: READ DATA BYTES Command Sequence ........................................................................................ 30 Figure 15: READ DATA BYTES at HIGHER SPEED Command Sequence ........................................................... 31 Figure 16: PAGE PROGRAM Command Sequence ........................................................................................... 32 Figure 17: SECTOR ERASE Command Sequence ............................................................................................. 33 Figure 18: BULK ERASE Command Sequence ................................................................................................. 34 Figure 19: DEEP POWER-DOWN Command Sequence ................................................................................... 35 Figure 20: RELEASE from DEEP POWER-DOWN Command Sequence ............................................................. 36 Figure 21: READ ELECTRONIC SIGNATURE Command Sequence .................................................................. 37 Figure 22: Power-Up Timing .......................................................................................................................... 39 Figure 23: AC Measurement I/O Waveform ..................................................................................................... 44 Figure 24: Serial Input Timing ........................................................................................................................ 50 Figure 25: Write Protect Setup and Hold during WRSR when SRWD=1 Timing ................................................. 50 Figure 26: Hold Timing .................................................................................................................................. 51 Figure 27: Output Timing .............................................................................................................................. 51 Figure 28: SO8N 150 mils Body Width ............................................................................................................ 52 Figure 29: SO8W 208 mils Body Width ............................................................................................................ 53 Figure 30: PDIP8 300 mils Body Width ............................................................................................................ 54 Figure 31: VFDFPN8 (MLP8) 6mm x 5mm ...................................................................................................... 55 Figure 32: UFDFPN8 (MLP8) 4mm x 3mm ...................................................................................................... 56 Figure 33: UFDFPN8 (MLP8) 2mm x 3mm ...................................................................................................... 57 CCMTD-1725822587-8430 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Features List of Tables Table 1: Signal Names ...................................................................................................................................... 7 Table 2: Signal Descriptions ............................................................................................................................. 9 Table 3: Protected Area Sizes .......................................................................................................................... 13 Table 4: Protected Area Sizes .......................................................................................................................... 13 Table 5: Protected Area Sizes .......................................................................................................................... 14 Table 6: Protected Area Sizes .......................................................................................................................... 14 Table 7: Protected Area Sizes .......................................................................................................................... 15 Table 8: Protected Area Sizes .......................................................................................................................... 15 Table 9: Sectors[7:0] ...................................................................................................................................... 18 Table 10: Command Set Codes ....................................................................................................................... 20 Table 11: READ IDENTIFICATION Data Out Sequence .................................................................................... 23 Table 12: Status Register Protection Modes ..................................................................................................... 29 Table 13: Power-Up Timing and V Threshold ............................................................................................... 40 WI Table 14: Absolute Maximum Ratings ............................................................................................................. 41 Table 15: Operating Conditions ...................................................................................................................... 41 Table 16: Data Retention and Endurance ........................................................................................................ 41 Table 17: DC Current Specifications (Device Grade 6) ..................................................................................... 42 Table 18: DC Voltage Specifications (Device Grade 6) ...................................................................................... 42 Table 19: DC Current Specifications (Device Grade 3) ..................................................................................... 42 Table 20: DC Voltage Specifications (Device Grade 3) ...................................................................................... 43 Table 21: Device Grade and AC Table Correlation ............................................................................................ 44 Table 22: AC Measurement Conditions ........................................................................................................... 44 Table 23: Capacitance .................................................................................................................................... 44 Table 24: Instruction Times, Process Technology ............................................................................................ 45 Table 25: AC Specifications (25 MHz, Device Grade 3, V [min]=2.7V) ............................................................. 45 CC Table 26: AC Specifications (50 MHz, Device Grade 6, V [min]=2.7V) ............................................................. 46 CC Table 27: AC Specifications (40 MHz, Device Grade 6, V [min]=2.3V) ............................................................. 47 CC Table 28: AC Specifications (75MHz, Device Grade 3 and 6, V [min]=2.7V) .................................................... 49 CC Table 29: Part Number Example ..................................................................................................................... 58 Table 30: Part Number Information Scheme ................................................................................................... 58 Table 31: Part Number Example ..................................................................................................................... 59 Table 32: Part Number Information Scheme ................................................................................................... 59 CCMTD-1725822587-8430 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this docu- ment if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi- cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib- utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non- automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con- ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in- demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo- nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ- mental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi- cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL- URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en- vironmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. CCMTD-1725822587-8430 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Functional Description Functional Description The M25P40 is an 4Mb (512Kb x 8) serial Flash memory device with advanced write- protection mechanisms accessed by a high-speed SPI-compatible bus. The device sup- ports high-performance commands for clock frequency up to 75MHz. The memory can be programmed 1 to 256 bytes at a time using the PAGE PROGRAM command. It is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes wide. The entire memory can be erased using the BULK ERASE command, or it can be erased one sector at a time using the SECTOR ERASE command. • Maximum frequency (READ DATA BYTES at HIGHER SPEED operation) in the stand- ard V range 2.7V to 3.6V equals 75MHz CC • Maximum frequency (READ DATA BYTES at HIGHER SPEED operation) in the exten- ded V range 2.3V to 2.7V equals 40MHz CC • UID/CFD protection feature Figure 1: Logic Diagram VCC DQ0 DQ1 C S# W# HOLD# VSS Table 1: Signal Names Signal Name Function Direction C Serial clock Input DQ0 Serial data input Input DQ1 Serial data output Output S# Chip select Input W# Write protect or enhanced program supply voltage Input HOLD# Hold Input V Supply voltage – CC V Ground – SS CCMTD-1725822587-8430 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Functional Description Figure 2: Pin Connections: SO8, MLP8 S# 1 8 VCC DQ1 2 7 HOLD# W# 3 6 C VSS 4 5 DQ0 There is an exposed central pad on the underside of the MLP8 package that is pulled internally to V , and must not be connected to any other voltage or signal line on the SS PCB. The Package Mechanical section provides information on package dimensions and how to identify pin 1. CCMTD-1725822587-8430 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Signal Descriptions Signal Descriptions Table 2: Signal Descriptions Signal Type Description DQ1 Output Serial data: The DQ1 output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock (C). DQ0 Input Serial data: The DQ0 input signal is used to transfer data serially into the device. It receives commands, addresses, and the data to be programmed. Values are latched on the rising edge of the serial clock (C). C Input Clock: The C input signal provides the timing of the serial interface. Commands, ad- dresses, or data present at serial data input (DQ0) is latched on the rising edge of the serial clock (C). Data on DQ1 changes after the falling edge of C. S# Input Chip select: When the S# input signal is HIGH, the device is deselected and DQ1 is at high impedance. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cy- cle is in progress, the device will be in the standby power mode (not the deep power- down mode). Driving S# LOW enables the device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any command. HOLD# Input Hold: The HOLD# signal is used to pause any serial communications with the device without deselecting the device. During the hold condition, DQ1 is High-Z. DQ0 and C are "Don’t Care." To start the hold condition, the device must be selected, with S# driven LOW. W#/V Input Write protect: The W#/V signal is both a control input and a power supply pin. The PP PP two functions are selected by the voltage range applied to the pin. If the W#/V input PP is kept in a low voltage range (0 V to V ) the pin is seen as a control input. The W# CC input signal is used to freeze the size of the area of memory that is protected against program or erase commands as specified by the values in BP2, BP1, and BP0 bits of the Status Register. V acts as an additional power supply if it is in the range of V , as PP PPH defined in the AC Measurement Conditions table. Avoid applying V to the W#/V PPH PP pin during a BULK ERASE operation. V Power Device core power supply: Source voltage. CC V Ground Ground: Reference for the V supply voltage. SS CC DNU – Do not use. CCMTD-1725822587-8430 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory SPI Modes SPI Modes These devices can be driven by a microcontroller with its serial peripheral interface (SPI) running in either of the following two SPI modes: • CPOL = 0, CPHA = 0 • CPOL = 1, CPHA = 1 For these two modes, input data is latched in on the rising edge of serial clock (C), and output data is available from the falling edge of C. The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring data: • C remains at 0 for (CPOL = 0, CPHA = 0) • C remains at 1 for (CPOL = 1, CPHA = 1) Figure 3: SPI Modes Supported CPOL CPHA 0 0 C 1 1 C DQ0 MSB DQ1 MSB Because only one device is selected at a time, only one device drives the serial data out- put (DQ1) line at a time, while the other devices are High-Z. An example of three devi- ces connected to an MCU on an SPI bus is shown here. CCMTD-1725822587-8430 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory SPI Modes Figure 4: Bus Master and Memory Devices on the SPI Bus VSS VCC R SDO SPI interface with SDI (CPOL, CPHA) = (0, 0) or (1, 1) SCK C VCC C VCC C VCC SPI Bus Master DQ1 DQ0 VSS DQ1 DQ0 VSS DQ1 DQ0 VSS R SPI memory R SPI memory R SPI memory device device device CS3 CS2 CS1 S# W# HOLD# S# W# HOLD# S# W# HOLD# Notes: 1. WRITE PROTECT (W#) and HOLD# should be driven HIGH or LOW as appropriate. 2. Resistors (R) ensure that the memory device is not selected if the bus master leaves the S# line High-Z. 3. The bus master may enter a state where all I/O are High-Z at the same time; for exam- ple, when the bus master is reset. Therefore, C must be connected to an external pull- down resistor so that when all I/O are High-Z, S# is pulled HIGH while C is pulled LOW. This ensures that S# and C do not go HIGH at the same time and that the tSHCH require- ment is met. 4. The typical value of R is 100kΩ, assuming that the time constant R × C (C = parasitic p p capacitance of the bus line) is shorter than the time during which the bus master leaves the SPI bus High-Z. 5. Example: Given that C = 50pF (R × C = 5μs), the application must ensure that the bus p p master never leaves the SPI bus High-Z for a time period shorter than 5μs. CCMTD-1725822587-8430 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Operating Features Operating Features Page Programming To program one data byte, two commands are required: WRITE ENABLE, which is one byte, and a PAGE PROGRAM sequence, which is four bytes plus data. This is followed by the internal PROGRAM cycle of duration t . To spread this overhead, the PAGE PRO- PP GRAM command allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided they lie in consecutive addresses on the same page of memory. To optimize timings, it is recommended to use the PAGE PROGRAM command to program all consecutive targeted bytes in a single sequence than to use several PAGE PROGRAM sequences with each containing only a few bytes. Sector Erase, Bulk Erase The PAGE PROGRAM command allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be ach- ieved a sector at a time using the SECTOR ERASE command, or throughout the entire memory using the BULK ERASE command. This starts an internal ERASE cycle of dura- tion t or t . The ERASE command must be preceded by a WRITE ENABLE command. SE BE Polling during a Write, Program, or Erase Cycle An improvement in the time to complete the following commands can be achieved by not waiting for the worst case delay (t , t , t , or t ). W PP SE BE • WRITE STATUS REGISTER • PROGRAM • ERASE (SECTOR ERASE, BULK ERASE) The write in progress (WIP) bit is provided in the status register so that the application program can monitor this bit in the status register, polling it to establish when the pre- vious WRITE cycle, PROGRAM cycle, or ERASE cycle is complete. Active Power, Standby Power, and Deep Power-Down When chip select (S#) is LOW, the device is selected, and in the ACTIVE POWER mode. When S# is HIGH, the device is deselected, but could remain in the ACTIVE POWER mode until all internal cycles have completed (PROGRAM, ERASE, WRITE STATUS REGISTER). The device then goes in to the STANDBY POWER mode. The device con- sumption drops to I . CC1 The DEEP POWER-DOWN mode is entered when the DEEP POWER-DOWN command is executed. The device consumption drops further to I . The device remains in this CC2 mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While in the DEEP POWER-DOWN mode, the device ignores all WRITE, PROGRAM, and ERASE commands. This provides an extra software protection mechanism when the device is not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or ERASE operations. For further information, see the DEEP POWER DOWN command. CCMTD-1725822587-8430 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Operating Features Status Register The status register contains a number of status and control bits that can be read or set (as appropriate) by specific commands. For a detailed description of the status register bits, see READ STATUS REGISTER (page 25). Data Protection by Protocol Non-volatile memory is used in environments that can include excessive noise. The fol- lowing capabilities help protect data in these noisy environments. Power on reset and an internal timer (t ) can provide protection against inadvertent PUW changes while the power supply is outside the operating specification. PROGRAM, ERASE, and WRITE STATUS REGISTER commands are checked before they are accepted for execution to ensure they consist of a number of clock pulses that is a multiple of eight. All commands that modify data must be preceded by a WRITE ENABLE command to set the write enable latch (WEL) bit. In addition to the low power consumption feature, the DEEP POWER-DOWN mode of- fers extra software protection since all PROGRAM, and ERASE commands are ignored when the device is in this mode. Software Data Protection Memory can be configured as read-only using the block protect bits (BP2, BP1, BP0) as shown in the Protected Area Sizes table. Hardware Data Protection Hardware data protection is implemented using the write protect signal applied on the W# pin. This freezes the status register in a read-only mode. In this mode, the block pro- tect (BP) bits and the status register write disable bit (SRWD) are protected. Table 3: Protected Area Sizes Status Register Content Memory Content BP Bit 1 BP Bit 0 Protected Area Unprotected Area 0 0 none All sectors (sectors 0 to 3) 0 1 Upper 4th (sector 3) Lower 3/4ths (sectors 0 to 2) 1 0 Upper half (sectors 2 and 3) Lower half (sectors 0 and 1) 1 1 All sectors (sectors 0 to 3) none Note: 1. 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command only if all block protect bits (BP1, BP0) are 0. Table 4: Protected Area Sizes Status Register Content Memory Content BP Bit 2 BP Bit 1 BP Bit 0 Protected Area Unprotected Area 0 0 0 none All sectors (sectors 0 to 7) CCMTD-1725822587-8430 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Operating Features Table 4: Protected Area Sizes (Continued) Status Register Content Memory Content BP Bit 2 BP Bit 1 BP Bit 0 Protected Area Unprotected Area 0 0 1 Upper 8th (sectors 7) Lower 7/8ths (sectors 0 to 6) 0 1 0 Upper 4th (sectors 6 and 7) Lower 3/4ths (sectors 0 to 5) 0 1 1 Upper half (sectors 4 to 7) Lower half (sectors 0 to 3) 1 0 0 All sectors (sectors 0 to 7) none 1 0 1 All sectors (sectors 0 to 7) none 1 1 0 All sectors (sectors 0 to 7) none 1 1 1 All sectors (sectors 0 to 7) none Note: 1. 0 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command only if all block protect bits (BP2, BP1, BP0) are 0. Table 5: Protected Area Sizes Status Register Content Memory Content BP Bit 2 BP Bit 1 BP Bit 0 Protected Area Unprotected Area 0 0 0 none All sectors (sectors 0 to 15) 0 0 1 Upper 16th (sector 15) Lower 15/16ths (sectors 0 to 14) 0 1 0 Upper 8th (sectors 14 and 15) Lower 7/8ths (sectors 0 to 13) 0 1 1 Upper 4th (sectors 12 to 15) Lower 3/4ths (sectors 0 to 11) 1 0 0 Upper half (sectors 8 to 15) Lower half (sectors 0 to 7) 1 0 1 All sectors (sectors 0 to 15) none 1 1 0 All sectors (sectors 0 to 15) none 1 1 1 All sectors (sectors 0 to 15) none Note: 1. 0 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command only if all block protect bits (BP2, BP1, BP0) are 0. Table 6: Protected Area Sizes Status Register Content Memory Content BP Bit 2 BP Bit 1 BP Bit 0 Protected Area Unprotected Area 0 0 0 none All sectors (sectors 0 to 31) 0 0 1 Upper 32nd (sector 31) Lower 31/32nds (sectors 0 to 30) 0 1 0 Upper 16th (sectors 30 and 31) Lower 15/16ths (sectors 0 to 29) 0 1 1 Upper 8th (sectors 28 to 31) Lower 7/8ths (sectors 0 to 27) 1 0 0 Upper 4th (sectors 24 to 31) Lower 3/4ths (sectors 0 to 23) 1 0 1 Upper half (sectors 16 to 31) Lower half (sectors 0 to 15) 1 1 0 All sectors (sectors 0 to 31) none CCMTD-1725822587-8430 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Operating Features Table 6: Protected Area Sizes (Continued) Status Register Content Memory Content BP Bit 2 BP Bit 1 BP Bit 0 Protected Area Unprotected Area 1 1 1 All sectors (sectors 0 to 31) none Note: 1. 0 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command only if all block protect bits (BP2, BP1, BP0) are 0. Table 7: Protected Area Sizes Status Register Content Memory Content BP Bit 2 BP Bit 1 BP Bit 0 Protected Area Unprotected Area 0 0 0 none All sectors (sectors 0 to 63) 0 0 1 Upper 64th (sector 63) Lower 63/64ths (sectors 0 to 62) 0 1 0 Upper 32nd (sectors 62 and 63) Lower 31/32nds (sectors 0 to 61) 0 1 1 Upper 16th (sectors 60 and 63) Lower 15/16ths (sectors 0 to 59) 1 0 0 Upper 8th (sectors 56 to 63) Lower 7/8ths (sectors 0 to 55) 1 0 1 Upper 4th (sectors 48 to 63) Lower 3/4ths (sectors 0 to 47) 1 1 0 Upper half (sectors 32 to 63) Lower half (sectors 0 to 31) 1 1 1 All sectors (sectors 0 to 63) none Note: 1. 0 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command only if all block protect bits (BP2, BP1, BP0) are 0. Table 8: Protected Area Sizes Status Register Content Memory Content BP Bit 2 BP Bit 1 BP Bit 0 Protected Area Unprotected Area 0 0 0 none All sectors (sectors 0 to 127) 0 0 1 Upper 64th (sectors 126 and 127) Lower 63/64ths (sectors 0 to 125) 0 1 0 Upper 32nd (sectors 124 to 127) Lower 31/32nds (sectors 0 to 123) 0 1 1 Upper 16th (sectors 120 to 127) Lower 15/16ths (sectors 0 to 119) 1 0 0 Upper 8th (sectors 112 to 127) Lower 7/8ths (sectors 0 to 111) 1 0 1 Upper 4th (sectors 96 to 127) Lower 3/4ths (sectors 0 to 95) 1 1 0 Upper half (sectors 64 to 127) Lower half (sectors 0 to 63) 1 1 1 All sectors (sectors 0 to 127) none Note: 1. The device is ready to accept a BULK ERASE command only if all block protect bits (BP2, BP1, BP0) are 0. Hold Condition The HOLD# signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal LOW does not terminate any WRITE STATUS REGISTER, PROGRAM, or ERASE cycle that is currently in progress. CCMTD-1725822587-8430 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Operating Features To enter the hold condition, the device must be selected, with S# LOW. The hold condi- tion starts on the falling edge of the HOLD# signal, if this coincides with serial clock (C) being LOW. The hold condition ends on the rising edge of the HOLD# signal, if this co- incides with C being LOW. If the falling edge does not coincide with C being LOW, the hold condition starts after C next goes LOW. Similarly, if the rising edge does not coin- cide with C being LOW, the hold condition ends after C next goes LOW. During the hold condition, DQ1 is HIGH impedance while DQ0 and C are Don’t Care. Typically, the device remains selected with S# driven LOW for the duration of the hold condition. This ensures that the state of the internal logic remains unchanged from the moment of entering the hold condition. If S# goes HIGH while the device is in the hold condition, the internal logic of the device is reset. To restart communication with the device, it is necessary to drive HOLD# HIGH, and then to drive S# LOW. This prevents the device from going back to the hold condition. Figure 5: Hold Condition Activation C HOLD# HOLD condition (standard use) HOLD condition (nonstandard use) CCMTD-1725822587-8430 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Configuration and Memory Map Configuration and Memory Map Memory Configuration and Block Diagram Each page of memory can be individually programmed; bits are programmed from 1 to 0. The device is sector or bulk-erasable, but not page-erasable; bits are erased from 0 to 1. The memory is configured as follows: • 524,288 bytes (8 bits each) • 8 sectors (512Kb, 65KB each) • 2048 pages (256 bytes each) Figure 6: Block Diagram HOLD# High Voltage W# Control Logic Generator S# C DQ0 I/O Shift Register DQ1 Address Register 256 Byte Status and Counter Data Buffer Register 7FFFFh er d o ec D Y 00000h 000FFh 256 bytes (page size) X Decoder CCMTD-1725822587-8430 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Memory Map – 4Mb Density Memory Map – 4Mb Density Table 9: Sectors[7:0] Address Range Sector Start End 7 0007 0000h 0007 FFFFh 6 0006 0000h 0006 FFFFh 5 0005 0000h 0005 FFFFh 4 0004 0000h 0004 FFFFh 3 0003 0000h 0003 FFFFh 2 0002 0000h 0002 FFFFh 1 0001 0000h 0001 FFFFh 0 0000 0000h 0000 FFFFh CCMTD-1725822587-8430 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Command Set Overview Command Set Overview All commands, addresses, and data are shifted in and out of the device, most significant bit first. Serial data inputs DQ0 and DQ1 are sampled on the first rising edge of serial clock (C) after chip select (S#) is driven LOW. Then, the one-byte command code must be shifted in to the device, most significant bit first, on DQ0 and DQ1, each bit being latched on the rising edges of C. Every command sequence starts with a one-byte command code. Depending on the command, this command code might be followed by address or data bytes, by address and data bytes, or by neither address or data bytes. For the following commands, the shifted-in command sequence is followed by a data-out sequence. S# can be driven HIGH after any bit of the data-out sequence is being shifted out. • READ DATA BYTES (READ) • READ DATA BYTES at HIGHER SPEED • READ STATUS REGISTER • READ IDENTIFICATION • RELEASE from DEEP POWER-DOWN For the following commands, S# must be driven HIGH exactly at a byte boundary. That is, after an exact multiple of eight clock pulses following S# being driven LOW, S# must be driven HIGH. Otherwise, the command is rejected and not executed. • PAGE PROGRAM • SECTOR ERASE • BULK ERASE • WRITE STATUS REGISTER • WRITE ENABLE • WRITE DISABLE All attempts to access the memory array are ignored during a WRITE STATUS REGISTER command cycle, a PROGRAM command cycle, or an ERASE command cycle. In addi- tion, the internal cycle for each of these commands continues unaffected. CCMTD-1725822587-8430 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Command Set Overview Table 10: Command Set Codes One-Byte Bytes Command Name Command Code Address Dummy Data WRITE ENABLE 0000 06h 0 0 0 0110 WRITE DISABLE 0000 04h 0 0 0 0100 READ IDENTIFICATION 1001 9Fh 0 0 1 to 20 1111 1001 9Eh 1110 READ STATUS REGISTER 0000 05h 0 0 1 to ∞ 0101 WRITE STATUS REGISTER 0000 01h 0 0 1 0001 READ DATA BYTES 0000 03h 3 0 1 to ∞ 0011 READ DATA BYTES at HIGHER SPEED 0000 0Bh 3 1 1 to ∞ 1011 PAGE PROGRAM 0000 02h 3 0 1 to 256 0010 SECTOR ERASE 1101 D8h 3 0 0 1000 BULK ERASE 1100 C7h 0 0 0 0111 DEEP POWER-DOWN 1011 B9h 0 0 0 1001 RELEASE from DEEP POWER-DOWN 1010 ABh 0 0 1 to ∞ 1011 CCMTD-1725822587-8430 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory WRITE ENABLE WRITE ENABLE The WRITE ENABLE command sets the write enable latch (WEL) bit. The WEL bit must be set before execution of every PROGRAM, ERASE, and WRITE com- mand. The WRITE ENABLE command is entered by driving chip select (S#) LOW, sending the command code, and then driving S# HIGH. Figure 7: WRITE ENABLE Command Sequence 0 1 2 3 4 5 6 7 C S# Command bits LSB DQ[0] 0 0 0 0 0 1 1 0 MSB DQ1 High-Z Don’t Care CCMTD-1725822587-8430 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory WRITE DISABLE WRITE DISABLE The WRITE DISABLE command resets the write enable latch (WEL) bit. The WRITE DISABLE command is entered by driving chip select (S#) LOW, sending the command code, and then driving S# HIGH. The WEL bit is reset under the following conditions: • Power-up • Completion of any ERASE operation • Completion of any PROGRAM operation • Completion of any WRITE STATUS REGISTER operation • Completion of WRITE DISABLE operation Figure 8: WRITE DISABLE Command Sequence 0 1 2 3 4 5 6 7 C S# Command bits LSB DQ[0] 0 0 0 0 0 1 0 0 MSB DQ1 High-Z Don’t Care CCMTD-1725822587-8430 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory READ IDENTIFICATION READ IDENTIFICATION The READ IDENTIFICATION command reads the following device identification data: • Manufacturer identification (1 byte): This is assigned by JEDEC. • Device identification (2 bytes): This is assigned by device manufacturer; the first byte indicates memory type and the second byte indicates device memory capacity. • A Unique ID code (UID) (17 bytes,16 available upon customer request): The first byte contains length of data to follow; the remaining 16 bytes contain optional Customized Factory Data (CFD) content. Table 11: READ IDENTIFICATION Data Out Sequence Manufacturer Device Identification UID Identification Memory Type Memory Capacity CFD Length CFD Content 20h 20h 12h 10h 16 bytes 13h 14h 15h 16h 17h 18h Note: 1. The CFD bytes are read-only and can be programmed with customer data upon demand. If customers do not make requests, the devices are shipped with all the CFD bytes pro- grammed to zero. A READ IDENTIFICATION command is not decoded while an ERASE or PROGRAM cy- cle is in progress and has no effect on a cycle in progress. The READ IDENTIFICATION command must not be issued while the device is in DEEP POWER-DOWN mode. The device is first selected by driving S# LOW. Then the 8-bit command code is shifted in and content is shifted out on DQ1 as follows: the 24-bit device identification that is stored in the memory, the 8-bit CFD length, followed by 16 bytes of CFD content. Each bit is shifted out during the falling edge of serial clock (C). The READ IDENTIFICATION command is terminated by driving S# HIGH at any time during data output. When S# is driven HIGH, the device is put in the STANDBY POWER mode and waits to be selected so that it can receive, decode, and execute commands. CCMTD-1725822587-8430 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory READ IDENTIFICATION Figure 9: READ IDENTIFICATION Command Sequence 0 7 8 15 16 31 32 C LSB DQ0 Command MSB LSB LSB LSB DQ1 High-Z D D D D D D OUT OUT OUT OUT OUT OUT MSB MSB MSB Manufacturer Device UID identification identification Don’t Care CCMTD-1725822587-8430 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory READ STATUS REGISTER READ STATUS REGISTER The READ STATUS REGISTER command allows the status register to be read. The status register may be read at any time, even while a PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress. When one of these cycles is in progress, it is recommen- ded to check the write in progress (WIP) bit before sending a new command to the de- vice. It is also possible to read the status register continuously. Figure 10: READ STATUS REGISTER Command Sequence 0 7 8 9 10 11 12 13 14 15 C LSB DQ0 Command MSB LSB DQ1 High-Z D D D D D D D D D OUT OUT OUT OUT OUT OUT OUT OUT OUT MSB Don’t Care Figure 11: Status Register Format b7 b0 SRWD 0 0 BP2 BP1 BP0 WEL WIP status register write protect block protect bits write enable latch bit write in progress bit CCMTD-1725822587-8430 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory READ STATUS REGISTER Figure 12: Status Register Format b7 b0 SRWD 0 0 0 BP1 BP0 WEL WIP status register write protect block protect bits write enable latch bit write in progress bit CCMTD-1725822587-8430 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory READ STATUS REGISTER WIP Bit The write in progress (WIP) bit indicates whether the memory is busy with a WRITE STATUS REGISTER cycle, a PROGRAM cycle, or an ERASE cycle. When the WIP bit is set to 1, a cycle is in progress; when the WIP bit is set to 0, a cycle is not in progress. WEL Bit The write enable latch (WEL) bit indicates the status of the internal write enable latch. When the WEL bit is set to 1, the internal write enable latch is set; when the WEL bit is set to 0, the internal write enable latch is reset and no WRITE STATUS REGISTER, PRO- GRAM, or ERASE command is accepted. Block Protect Bits The block protect bits are non-volatile. They define the size of the area to be software protected against PROGRAM and ERASE commands. The block protect bits are written with the WRITE STATUS REGISTER command. When one or more of the block protect bits is set to 1, the relevant memory area, as de- fined in the Protected Area Sizes table, becomes protected against PAGE PROGRAM and SECTOR ERASE commands. The block protect bits can be written provided that the hardware protected mode has not been set. The BULK ERASE command is executed on- ly if all block protect bits are 0. SRWD Bit The status register write disable (SRWD) bit is operated in conjunction with the write protect (W#/V ) signal. When the SRWD bit is set to 1 and W#/V is driven LOW, the PP PP device is put in the hardware protected mode. In the hardware protected mode, the non-volatile bits of the status register (SRWD, and the block protect bits) become read- only bits and the WRITE STATUS REGISTER command is no longer accepted for execu- tion. CCMTD-1725822587-8430 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory WRITE STATUS REGISTER WRITE STATUS REGISTER The WRITE STATUS REGISTER command allows new values to be written to the status register. Before the WRITE STATUS REGISTER command can be accepted, a WRITE EN- ABLE command must have been executed previously. After the WRITE ENABLE com- mand has been decoded and executed, the device sets the write enable latch (WEL) bit. The WRITE STATUS REGISTER command is entered by driving chip select (S#) LOW, followed by the command code and the data byte on serial data input (DQ0). The WRITE STATUS REGISTER command has no effect on b6, b5, b4, b1, and b0 of the sta- tus register. The status register b6, b5, and b4 are always read as "0". S# must be driven HIGH after the eighth bit of the data byte has been latched in. If not, the WRITE STATUS REGISTER command is not executed. Figure 13: WRITE STATUS REGISTER Command Sequence 0 7 8 9 10 11 12 13 14 15 C LSB LSB DQ0 Command DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB MSB As soon as S# is driven HIGH, the self-timed WRITE STATUS REGISTER cycle is initi- ated; its duration is tW. While the WRITE STATUS REGISTER cycle is in progress, the sta- tus register may still be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed WRITE STATUS REGISTER cycle, and is 0 when the cycle is completed. Also, when the cycle is completed, the WEL bit is reset. The WRITE STATUS REGISTER command allows the user to change the values of the block protect bits (BP2, BP1, BP0). Setting these bit values defines the size of the area that is to be treated as read-only, as defined in the Protected Area Sizes table. The WRITE STATUS REGISTER command also allows the user to set and reset the status register write disable (SRWD) bit in accordance with the write protect (W#/V ) signal. PP The SRWD bit and the W#/V signal allow the device to be put in the hardware protec- PP ted (HPM) mode. The WRITE STATUS REGISTER command is not executed once the HPM is entered. The options for enabling the status register protection modes are sum- marized here. CCMTD-1725822587-8430 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory WRITE STATUS REGISTER Table 12: Status Register Protection Modes Memory Content W#/V SRWD Protection Status Register Protected Unprotected PP Signal Bit Mode (PM) Write Protection Area Area Notes 1 0 Software Software protection Commands not Commands 1, 2, 3 0 0 protected mode accepted accepted (SPM) 1 1 0 1 Hardware Hardware protection Commands not Commands 3, 4, 5, protected mode accepted accepted (HPM) Notes: 1. Software protection: status register is writable (SRWD, BP2, BP1, and BP0 bit values can be changed) if the WRITE ENABLE command has set the WEL bit. 2. PAGE PROGRAM, SECTOR ERASE, and BULK ERASE commands are not accepted. 3. PAGE PROGRAM and SECTOR ERASE commands can be accepted. 4. Hardware protection: status register is not writable (SRWD, BP2, BP1, and BP0 bit values cannot be changed). 5. PAGE PROGRAM, SECTOR ERASE, and BULK ERASE commands are not accepted. When the SRWD bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the WEL bit has been set previously by a WRITE ENABLE command, regardless of whether the W#/V signal is driven HIGH or LOW. PP When the status register SRWD bit is set to 1, two cases need to be considered depend- ing on the state of the W#/V signal: PP • If the W#/V signal is driven HIGH, it is possible to write to the status register provi- PP ded that the WEL bit has been set previously by a WRITE ENABLE command. • If the W#/V signal is driven LOW, it is not possible to write to the status register even PP if the WEL bit has been set previously by a WRITE ENABLE command. Therefore, at- tempts to write to the status register are rejected, and are not accepted for execution. The result is that all the data bytes in the memory area that have been put in SPM by the status register block protect bits (BP2, BP1, BP0) are also hardware protected against data modification. Regardless of the order of the two events, the HPM can be entered in either of the fol- lowing ways: • Setting the status register SRWD bit after driving the W#/V signal LOW PP • Driving the W#/V signal LOW after setting the status register SRWD bit. PP The only way to exit the HPM is to pull the W#/V signal HIGH. If the W#/V signal is PP PP permanently tied HIGH, the HPM can never be activated. In this case, only the SPM is available, using the status register block protect bits (BP2, BP1, BP0). CCMTD-1725822587-8430 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory READ DATA BYTES READ DATA BYTES The device is first selected by driving chip select (S#) LOW. The command code for READ DATA BYTES is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of serial clock (C). Then the memory contents at that address is shifted out on serial data output (DQ1), each bit being shifted out at a maximum fre- quency fR during the falling edge of C. The first byte addressed can be at any location. The address is automatically incremen- ted to the next higher address after each byte of data is shifted out. Therefore, the entire memory can be read with a single READ DATA BYTES command. When the highest ad- dress is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The READ DATA BYTES command is terminated by driving S# HIGH. S# can be driven HIGH at any time during data output. Any READ DATA BYTES command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 14: READ DATA BYTES Command Sequence 0 7 8 C x C LSB A[MIN] DQ[0] Command MSB A[MAX] LSB DQ1 High-Z DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Don’t Care Note: 1. Cx = 7 + (A[MAX] + 1). CCMTD-1725822587-8430 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory READ DATA BYTES at HIGHER SPEED READ DATA BYTES at HIGHER SPEED The device is first selected by driving chip select (S#) LOW. The command code for the READ DATA BYTES at HIGHER SPEED command is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (C). Then the memory contents at that address are shifted out on serial data output (DQ1) at a maximum frequency fC, during the falling edge of C. The first byte addressed can be at any location. The address is automatically incremen- ted to the next higher address after each byte of data is shifted out. Therefore, the entire memory can be read with a single READ DATA BYTES at HIGHER SPEED command. When the highest address is reached, the address counter rolls over to 000000h, allow- ing the read sequence to be continued indefinitely. The READ DATA BYTES at HIGHER SPEED command is terminated by driving S# HIGH. S# can be driven HIGH at any time during data output. Any READ DATA BYTES at HIGHER SPEED command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 15: READ DATA BYTES at HIGHER SPEED Command Sequence 0 7 8 Cx C LSB A[MIN] DQ0 Command MSB A[MAX] LSB DQ1 High-Z DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Dummy cycles Don’t Care Note: 1. Cx = 7 + (A[MAX] + 1). CCMTD-1725822587-8430 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory PAGE PROGRAM PAGE PROGRAM The PAGE PROGRAM command allows bytes in the memory to be programmed, which means the bits are changed from 1 to 0. Before a PAGE PROGRAM command can be ac- cepted a WRITE ENABLE command must be executed. After the WRITE ENABLE com- mand has been decoded, the device sets the write enable latch (WEL) bit. The PAGE PROGRAM command is entered by driving chip select (S#) LOW, followed by the command code, three address bytes, and at least one data byte on serial data input (DQ0). If the eight least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page; that is, from the address whose eight least significant bits (A7-A0) are all zero. S# must be driven LOW for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without any effects on the other bytes of the same page. For optimized timings, it is recommended to use the PAGE PROGRAM command to program all consecutive targeted bytes in a single sequence rather than to use several PAGE PROGRAM sequences, each containing only a few bytes. S# must be driven HIGH after the eighth bit of the last data byte has been latched in. Otherwise the PAGE PROGRAM command is not executed. As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cy- cles's duration is t . While the PAGE PROGRAM cycle is in progress, the status register PP may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed PAGE PROGRAM cycle, and 0 when the cycle is completed. At some un- specified time before the cycle is completed, the write enable latch (WEL) bit is reset. A PAGE PROGRAM command is not executed if it applies to a page protected by the block protect bits BP2, BP1, and BP0. Figure 16: PAGE PROGRAM Command Sequence 0 7 8 C x C LSB A[MIN] LSB DQ[0] Command DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB A[MAX] MSB Note: 1. Cx = 7 + (A[MAX] + 1). CCMTD-1725822587-8430 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory SECTOR ERASE SECTOR ERASE The SECTOR ERASE command sets to 1 (FFh) all bits inside the chosen sector. Before the SECTOR ERASE command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The SECTOR ERASE command is entered by driving chip select (S#) LOW, followed by the command code, and three address bytes on serial data input (DQ0). Any address in- side the sector is a valid address for the SECTOR ERASE command. S# must be driven LOW for the entire duration of the sequence. S# must be driven HIGH after the eighth bit of the last address byte has been latched in. Otherwise the SECTOR ERASE command is not executed. As soon as S# is driven HIGH, the self-timed SECTOR ERASE cycle is initiated; the cycle's duration is t . While the SE SECTOR ERASE cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SECTOR ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is completed, the WEL bit is reset. A SECTOR ERASE command is not executed if it applies to a sector that is hardware or software protected. Figure 17: SECTOR ERASE Command Sequence 0 7 8 C x C LSB A[MIN] DQ0 Command MSB A[MAX] Note: 1. Cx = 7 + (A[MAX] + 1). CCMTD-1725822587-8430 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory BULK ERASE BULK ERASE The BULK ERASE command sets all bits to 1 (FFh). Before the BULK ERASE command can be accepted, a WRITE ENABLE command must have been executed previously. Af- ter the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The BULK ERASE command is entered by driving chip select (S#) LOW, followed by the command code on serial data input (DQ0). S# must be driven LOW for the entire dura- tion of the sequence. S# must be driven HIGH after the eighth bit of the command code has been latched in. Otherwise the BULK ERASE command is not executed. As soon as S# is driven HIGH, the self-timed BULK ERASE cycle is initiated; the cycle's duration is t . While the BULK BE ERASE cycle is in progress, the status register may be read to check the value of the write In progress (WIP) bit. The WIP bit is 1 during the self-timed BULK ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is completed, the WEL bit is reset. The BULK ERASE command is executed only if all block protect (BP2, BP1, BP0) bits are 0. The BULK ERASE command is ignored if one or more sectors are protected. Figure 18: BULK ERASE Command Sequence 0 7 C LSB DQ0 Command MSB CCMTD-1725822587-8430 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory DEEP POWER-DOWN DEEP POWER-DOWN Executing the DEEP POWER-DOWN command is the only way to put the device in the lowest power consumption mode, the DEEP POWER-DOWN mode. The DEEP POWER- DOWN command can also be used as a software protection mechanism while the de- vice is not in active use because in the DEEP POWER-DOWN mode the device ignores all WRITE, PROGRAM, and ERASE commands. Driving chip select (S#) HIGH deselects the device, and puts it in the STANDBY POWER mode if there is no internal cycle currently in progress. Once in STANDBY POWER mode, the DEEP POWER-DOWN mode can be entered by executing the DEEP POWER- DOWN command, subsequently reducing the standby current from I to I . CC1 CC2 To take the device out of DEEP POWER-DOWN mode, the RELEASE from DEEP POW- ER-DOWN command must be issued. Other commands must not be issued while the device is in DEEP POWER-DOWN mode. The DEEP POWER-DOWN mode stops auto- matically at power-down. The device always powers up in STANDBY POWER mode. The DEEP POWER-DOWN command is entered by driving S# LOW, followed by the command code on serial data input (DQ0). S# must be driven LOW for the entire dura- tion of the sequence. S# must be driven HIGH after the eighth bit of the command code has been latched in. Otherwise the DEEP POWER-DOWN command is not executed. As soon as S# is driven HIGH, it requires a delay of t before the supply current is reduced to I and the DP CC2 DEEP POWER-DOWN mode is entered. Any DEEP POWER-DOWN command issued while an ERASE, PROGRAM, or WRITE cy- cle is in progress is rejected without any effect on the cycle that is in progress. Figure 19: DEEP POWER-DOWN Command Sequence 0 7 C tDP LSB DQ0 Command MSB Standby Mode Deep Power-Down Mode Don’t Care CCMTD-1725822587-8430 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory RELEASE from DEEP POWER-DOWN RELEASE from DEEP POWER-DOWN Once the device has entered DEEP POWER-DOWN mode, all commands are ignored ex- cept RELEASE from DEEP POWER-DOWN and READ ELECTRONIC SIGNATURE. Exe- cuting either of these commands takes the device out of the DEEP POWER-DOWN mode. The RELEASE from DEEP POWER-DOWN command is entered by driving chip select (S#) LOW, followed by the command code on serial data input (DQ0). S# must be driven LOW for the entire duration of the sequence. The RELEASE from DEEP POWER-DOWN command is terminated by driving S# HIGH. Sending additional clock cycles on serial clock C while S# is driven LOW causes the command to be rejected and not executed. After S# has been driven HIGH, followed by a delay, t , the device is put in the STAND- RES BY mode. S# must remain HIGH at least until this period is over. The device waits to be selected so that it can receive, decode, and execute commands. Any RELEASE from DEEP POWER-DOWN command issued while an ERASE, PRO- GRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 20: RELEASE from DEEP POWER-DOWN Command Sequence 0 7 C tRDP LSB DQ0 Command MSB DQ1 High-Z Deep Power-Down Mode Standby Mode Don’t Care CCMTD-1725822587-8430 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory READ ELECTRONIC SIGNATURE READ ELECTRONIC SIGNATURE Once the device enters DEEP POWER-DOWN mode, all commands are ignored except READ ELECTRONIC SIGNATURE and RELEASE from DEEP POWER-DOWN. Executing either of these commands takes the device out of the DEEP POWER-DOWN mode. The READ ELECTRONIC SIGNATURE command is entered by driving chip select (S#) LOW, followed by the command code and three dummy bytes on serial data input (DQ0) . Each bit is latched in on the rising edge of serial clock C. The 8-bit electronic signature is shifted out on serial data output DQ1 on the falling edge of C; S# must be driven LOW the entire duration of the sequence for the electronic signature to be read. However, driving S# HIGH after the command code, but before the entire 8-bit electron- ic signature has been output for the first time, still ensures that the device is put into STANDBY mode. Except while an ERASE, PROGRAM, or WRITE STATUS REGISTER cycle is in progress, the READ ELECTRONIC SIGNATURE command provides access to the 8-bit electronic signature of the device, and can be applied even if DEEP POWER-DOWN mode has not been entered. The READ ELECTRONIC SIGNATURE command is not executed while an ERASE, PROGRAM, or WRITE STATUS REGISTER cycle is in progress and has no effect on the cycle in progress. The READ ELECTRONIC SIGNATURE command is terminated by driving S# high after the electronic signature has been read at least once. Sending additional clock cycles C while S# is driven LOW causes the electronic signature to be output repeatedly. If S# is driven HIGH, the device is put in STANDBY mode immediately unless it was pre- viously in DEEP POWER-DOWN mode. If previously in DEEP POWER-DOWN mode, the device transitions to STANDBY mode with delay as described here. Once in STANDBY mode, the device waits to be selected so that it can receive, decode, and execute instruc- tions. • If S# is driven HIGH before the electronic signature is read, transition to STANDBY mode is delayed by tRES1, as shown in the RELEASE from DEEP POWER-DOWN com- mand sequence. S# must remain HIGH for at least tRES1(max). • If S# is driven HIGH after the electronic signature is read, transition to STANDBY mode is delayed by tRES2. S# must remain HIGH for at least tRES2(max). Figure 21: READ ELECTRONIC SIGNATURE Command Sequence 0 7 8 Cx C tRES2 LSB DQ0 Command MSB Electronic Signature LSB DQ1 High-Z DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Dummy cycles Deep Power-Down Standby Don’t Care Note: 1. Cx = 7 + (A[MAX] + 1). CCMTD-1725822587-8430 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Power-Up/Down and Supply Line Decoupling Power-Up/Down and Supply Line Decoupling At power-up and power-down, the device must not be selected; that is, chip select (S#) must follow the voltage applied on V until V reaches the correct value: CC CC • V at power-up, and then for a further delay of t CC,min VSL • V at power-down SS A safe configuration is provided in the SPI Modes section. To avoid data corruption and inadvertent write operations during power-up, a power- on-reset (POR) circuit is included. The logic inside the device is held reset while V is CC less than the POR threshold voltage, V – all operations are disabled, and the device WI does not respond to any instruction. Moreover, the device ignores the following instruc- tions until a time delay of tPUW has elapsed after the moment that V rises above the CC V threshold: WI • WRITE ENABLE • PAGE PROGRAM • SECTOR ERASE • BULK ERASE • WRITE STATUS REGISTER However, the correct operation of the device is not guaranteed if, by this time, V is still CC below V . No WRITE STATUS REGISTER, PROGRAM, or ERASE instruction should CC.min be sent until: • tPUW after V has passed the V threshold CC WI • tVSL after V has passed the V level CC CC,min If the time, tVSL, has elapsed, after V rises above V , the device can be selected CC CC,min for READ instructions even if the tPUW delay has not yet fully elapsed. V must be applied only when V is stable and in the V to V voltage PPH CC CC,min CC,max range. CCMTD-1725822587-8430 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Power-Up/Down and Supply Line Decoupling Figure 22: Power-Up Timing V CC V CC,max PROGRAM, ERASE, and WRITE commands are rejected by the device Chip selection not allowed V CC,min tVSL READ access allowed Device fully RESET state accessible of the device V WI tPUW Time After power-up, the device is in the following state: • Standby power mode (not the deep power-down mode) • Write enable latch (WEL) bit is reset • Write in progress (WIP) bit is reset • Write lock bit = 0 • Lock down bit = 0 Normal precautions must be taken for supply line decoupling to stabilize the V sup- CC ply. Each device in a system should have the V line decoupled by a suitable capacitor CC close to the package pins; generally, this capacitor is of the order of 100 nF. At power-down, when V drops from the operating voltage to below the POR threshold CC voltage V , all operations are disabled and the device does not respond to any instruc- WI tion. Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress, some data corruption may result. CCMTD-1725822587-8430 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Power-Up Timing and Write Inhibit Voltage Specifications Power-Up Timing and Write Inhibit Voltage Specifications Table 13: Power-Up Timing and V Threshold WI Symbol Parameter Min Max Unit t V (min) to S# LOW 10 – μs VSL CC t Time delay to write instruction 1.0 10 ms PUW V Write Inhibit voltage (device grade 3) 1.0 2.1 V WI V Write Inhibit voltage (device grade 6) 1.0 2.1 V WI Note: 1. Parameters are characterized only. If the time, t , has elapsed, after V rises above V (min), the device can be selected VSL CC CC for READ instructions even if the t delay has not yet fully elapsed. PUW V must be applied only when V is stable and in the V min to V max voltage PPH CC CC CC range. CCMTD-1725822587-8430 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Maximum Ratings and Operating Conditions Maximum Ratings and Operating Conditions Caution: Stressing the device beyond the absolute maximum ratings may cause perma- nent damage to the device. These are stress ratings only and operation of the device be- yond any specification or condition in the operating sections of this data sheet is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 14: Absolute Maximum Ratings Symbol Parameter Min Max Units Notes T Storage temperature –65 150 °C STG T Lead temperature during soldering — See note °C 1 LEAD V Input and output voltage (with respect to –0.6 V +0.6 V 2 IO CC ground) V Supply voltage –0.6 4.0 V CC V Electrostatic discharge voltage (human body –2000 2000 V 3 ESD model) Notes: 1. The TLEAD signal is compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb as- sembly), the Micron RoHS-compliant 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. The minimum voltage may reach the value of –2V for no more than 20ns during transi- tions; the maximum may reach the value of V +2V for no more than 20ns during tran- CC sitions. 3. The V signal: JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω). ESD Table 15: Operating Conditions Symbol Parameter Min Max Unit V Supply voltage 2.3 3.6 V CC T Ambient operating temperature (grade 6) –40 85 °C A T Ambient operating temperature (grade 3) –40 125 °C A Table 16: Data Retention and Endurance Parameter Condition Min Max Unit Program/erase cycles Grade 6, Grade 3 100,000 – Cycles per unit Data retention at 55°C 20 – Years CCMTD-1725822587-8430 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Electrical Characteristics Electrical Characteristics Table 17: DC Current Specifications (Device Grade 6) Symbol Parameter Test Conditions Min Max Units I Input leakage current – – ±2 µA LI I Output leakage current – – ±2 µA LO I Standby current S# = V , V = V or V – 50 µA CC1 CC IN SS CC I Deep power-down current S# = V , V = V or V – 10 µA CC2 CC IN SS CC I Operating current (READ) C = 0.1V / 0.9V at 40 MHz, 50 MHz, – 8 mA CC3 CC CC and 75 MHz, DQ1 = open C = 0.1V / 0.9V at 25 MHz and 33 – 4 mA CC CC MHz, DQ1 = open I Operating current S# = V – 15 mA CC4 CC (PAGE PROGRAM) I Operating current S# = V – 15 mA CC5 CC (WRITE STATUS REGISTER) I Operating current S# = V – 15 mA CC6 CC (SECTOR ERASE) I Operating current S# = V – 15 mA CC7 CC (BULK ERASE) Table 18: DC Voltage Specifications (Device Grade 6) Symbol Parameter Test Conditions Min Max Units V Input LOW voltage – –0.5 0.3V V IL CC V Input HIGH voltage – 0.7V V +0.4 V IH CC CC V Output LOW voltage I = 1.6mA – 0.4 V OL OL V Output HIGH voltage I = –100µA V –0.2 – V OH OH CC Table 19: DC Current Specifications (Device Grade 3) Symbol Parameter Test Conditions Min Max Units I Input leakage current – – ±2 µA LI I Output leakage current – – ±2 µA LO I Standby current S# = V , V = V or V – 100 µA CC1 CC IN SS CC I Deep power-down current S# = V , V = V or V – 50 µA CC2 CC IN SS CC I Operating current (READ) C = 0.1V / 0.9V at 40 MHz, 50 MHz, – 8 mA CC3 CC CC and 75 MHz, DQ1 = open C = 0.1V / 0.9V at 25 MHz and 33 – 4 mA CC CC MHz, DQ1 = open I Operating current S# = V – 15 mA CC4 CC (PAGE PROGRAM) CCMTD-1725822587-8430 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Electrical Characteristics Table 19: DC Current Specifications (Device Grade 3) (Continued) Symbol Parameter Test Conditions Min Max Units I Operating current S# = V – 15 mA CC5 CC (WRITE STATUS REGISTER) I Operating current S# = V – 15 mA CC6 CC (SECTOR ERASE) I Operating current S# = V – 15 mA CC7 CC (BULK ERASE) Table 20: DC Voltage Specifications (Device Grade 3) Symbol Parameter Test Conditions Min Max Units V Input LOW voltage – –0.5 0.3V V IL CC V Input HIGH voltage – 0.7V V +0.4 V IH CC CC V Output LOW voltage I = 1.6mA – 0.4 V OL OL V Output HIGH voltage I = –100µA V –0.2 – V OH OH CC CCMTD-1725822587-8430 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory AC Characteristics AC Characteristics In the following AC specifications, output HIGH-Z is defined as the point where data out is no longer driven; however, this is not applicable to the M25PX64 device. Table 21: Device Grade and AC Table Correlation 110nm Device Grade V [min] f[max] AC Table CC Grade 3 2.7V 75MHz Table 28 (page 49) Grade 6 2.3V 40MHz Table 27 (page 47) Grade 6 2.7V 75MHz Table 28 (page 49) Table 22: AC Measurement Conditions Symbol Parameter Min Max Unit C Load capacitance 30 30 pF L Input rise and fall times – 5 ns Input pulse voltages 0.2V 0.8V V CC CC Input timing reference voltages 0.3V 0.7V V CC CC Output timing reference voltages V / 2 V / 2 V CC CC Figure 23: AC Measurement I/O Waveform Input levels Input and output timing reference levels 0.8V 0.7V CC CC 0.5V CC 0.2V 0.3V CC CC Table 23: Capacitance Symbol Parameter Test condition Min Max Unit Notes C Output capacitance (DQ1) V = 0 V – 8 pF 1 OUT OUT C Input capacitance (other pins) V = 0 V – 6 pF IN IN Note: 1. Values are sampled only, not 100% tested, at TA=25°C and a frequency of 25MHz. CCMTD-1725822587-8430 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory AC Characteristics Table 24: Instruction Times, Process Technology Symbol Parameter Min Typ Max Units Notes t WRITE STATUS REGISTER cycle time – 1.3 15 ms W t PAGE PROGRAM cycle time (256 bytes) – 0.8 5 ms 2 PP t PAGE PROGRAM cycle time (n bytes) – int (n/8) x PP 0.025 t SECTOR ERASE cycle time – 0.6 3 s SE t BULK ERASE cycle time – 4.5 10 s BE Notes: 1. Applies to the entire table: 110nm technology devices are identified by the process iden- tification digit 4 in the device marking and the process letter B in the part number. 2. When using the PAGE PROGRAM command to program consecutive bytes, optimized timings are obtained in one sequence that includes all the bytes rather than in several sequences of only a few bytes (1 < n < 256). Table 25: AC Specifications (25 MHz, Device Grade 3, V [min]=2.7V) CC Symbol Alt. Parameter Min Typ Max Unit Notes f f Clock frequency for commands (See note) D.C. – 25 MHz 1 C C f – Clock frequency for READ command D.C. – 20 MHz R t t Clock HIGH time 18 – – ns 2 CH CLH t t Clock LOW time 18 – – ns 2 CL CLL t – Clock rise time (peak to peak) 0.1 – – V/ns 3, 4 CLCH t – Clock fall time (peak to peak) 0.1 – – V/ns 3, 4 CHCL t t S# active setup time (relative to C) 10 – – ns SLCH CSS t — S# not active hold time (relative to C) 10 – – ns CHSL t t Data in setup time 5 – – ns DVCH DSU t t Data in hold time 5 – – ns CHDX DH t – S# active hold time (relative to C) 10 – – ns CHSH t – S# not active setup time (relative to C) 10 – – ns SHCH t t S# deselect time 100 – – ns SHSL CSH t t Output disable time – – 15 ns 3 SHQZ DIS t t Clock LOW to output valid – – 15 ns CLQV V t t Output hold time 0 – – ns CLQX HO t – HOLD# setup time (relative to C) 10 – – ns HLCH t – HOLD# hold time (relative to C) 10 – – ns CHHH t – HOLD# setup time (relative to C) 10 – – ns HHCH t – HOLD# hold time (relative to C) 10 – – ns CHHL t t HOLD# to output LOW-Z – – 15 ns 3 HHQX LZ t t HOLD# to output HIGH-Z – – 20 ns 3 HLQZ HZ t – WRITE PROTECT setup time 20 – – ns 5 WHSL t – WRITE PROTECT hold time 100 – – ns 5 SHWL CCMTD-1725822587-8430 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory AC Characteristics Table 25: AC Specifications (25 MHz, Device Grade 3, V [min]=2.7V) (Continued) CC Symbol Alt. Parameter Min Typ Max Unit Notes t – S# HIGH to DEEP POWER-DOWN mode – – 3 μs 3 DP t – S# HIGH to STANDBY without electronic signature read – – 30 μs 3 RES1 t – S# HIGH to STANDBY with electronic signature read – – 30 μs 3 RES2 Notes: 1. READ DATA BYTES at HIGHER SPEED, PAGE PROGRAM, SECTOR ERASE, BLOCK ERASE, DEEP POWER-DOWN, READ ELECTRONIC SIGNATURE, WRITE ENABLE/DISABLE, READ ID, READ/WRITE STATUS REGISTER 2. The t and t signals must be greater than or equal to 1/f . CH CL C 3. The t , t , t , t , t , t , t , and t signal values are guaranteed by CLCH CHCL SHQZ HHQX HLQZ DP RES1 RES2 characterization, not 100% tested in production. 4. The t and t signals clock rise and fall time values are expressed as a slew-rate. CLCH CHCL 5. The t and t signals are only applicable as a constraint for a WRITE STATUS REGIS- WHSL SHWL TER command when SRWD bit is set at 1. Table 26: AC Specifications (50 MHz, Device Grade 6, V [min]=2.7V) CC Symbol Alt. Parameter Min Typ Max Unit Notes f f Clock frequency for commands (See note) D.C. – 50 MHz 1 C C f – Clock frequency for READ command D.C. – 25 MHz R t t Clock HIGH time 9 – – ns 2 CH CLH t t Clock LOW time 9 – – ns 2 CL CLL t – Clock rise time (peak to peak) 0.1 – – V/ns 3, 4 CLCH t – Clock fall time (peak to peak) 0.1 – – V/ns 3, 4 CHCL t t S# active setup time (relative to C) 5 – – ns SLCH CSS t — S# not active hold time (relative to C) 5 – – ns CHSL t t Data in setup time 2 – – ns DVCH DSU t t Data in hold time 5 – – ns CHDX DH t – S# active hold time (relative to C) 5 – – ns CHSH t – S# not active setup time (relative to C) 5 – – ns SHCH t t S# deselect time 100 – – ns SHSL CSH t t Output disable time – – 8 ns 3 SHQZ DIS t t Clock LOW to output valid – – 8 ns CLQV V t t Output hold time 0 – – ns CLQX HO t – HOLD# setup time (relative to C) 5 – – ns HLCH t – HOLD# hold time (relative to C) 5 – – ns CHHH t – HOLD# setup time (relative to C) 5 – – ns HHCH t – HOLD# hold time (relative to C) 5 – – ns CHHL t t HOLD# to output LOW-Z – – 8 ns 3 HHQX LZ t t HOLD# to output HIGH-Z – – 8 ns 3 HLQZ HZ t – WRITE PROTECT setup time 20 – – ns 5 WHSL t – WRITE PROTECT hold time 100 – – ns 5 SHWL CCMTD-1725822587-8430 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory AC Characteristics Table 26: AC Specifications (50 MHz, Device Grade 6, V [min]=2.7V) (Continued) CC Symbol Alt. Parameter Min Typ Max Unit Notes t – S# HIGH to DEEP POWER-DOWN mode – – 3 μs 3 DP t – S# HIGH to STANDBY without electronic signature read – – 30 μs 3 RES1 t – S# HIGH to STANDBY with electronic signature read – – 30 μs 3 RES2 Notes: 1. READ DATA BYTES at HIGHER SPEED, PAGE PROGRAM, SECTOR ERASE, BLOCK ERASE, DEEP POWER-DOWN, READ ELECTRONIC SIGNATURE, WRITE ENABLE/DISABLE, READ ID, READ/WRITE STATUS REGISTER 2. The t and t signals must be greater than or equal to 1/f . CH CL C 3. The t , t , t , t , t , t , t , and t signal values are guaranteed by CLCH CHCL SHQZ HHQX HLQZ DP RES1 RES2 characterization, not 100% tested in production. 4. The t and t signals clock rise and fall time values are expressed as a slew-rate. CLCH CHCL 5. The t and t signals are only applicable as a constraint for a WRITE STATUS REGIS- WHSL SHWL TER command when SRWD bit is set at 1. Table 27: AC Specifications (40 MHz, Device Grade 6, V [min]=2.3V) CC Symbol Alt. Parameter Min Typ Max Unit Notes f f Clock frequency for commands (See note) D.C. – 40 MHz 2 C C f – Clock frequency for READ command D.C. – 25 MHz R t t Clock HIGH time 11 – – ns 3 CH CLH t t Clock LOW time 11 – – ns 3 CL CLL t – Clock rise time (peak to peak) 0.1 – – V/ns 4, 5 CLCH t – Clock fall time (peak to peak) 0.1 – – V/ns 4, 5 CHCL t t S# active setup time (relative to C) 5 – – ns SLCH CSS t — S# not active hold time (relative to C) 5 – – ns CHSL t t Data in setup time 2 – – ns DVCH DSU t t Data in hold time 5 – – ns CHDX DH t – S# active hold time (relative to C) 5 – – ns CHSH t – S# not active setup time (relative to C) 5 – – ns SHCH t t S# deselect time 100 – – ns SHSL CSH t t Output disable time – – 8 ns 4 SHQZ DIS t t Clock LOW to output valid – – 8 ns CLQV V t t Output hold time 0 – – ns CLQX HO t – HOLD# setup time (relative to C) 5 – – ns HLCH t – HOLD# hold time (relative to C) 5 – – ns CHHH t – HOLD# setup time (relative to C) 5 – – ns HHCH t – HOLD# hold time (relative to C) 5 – – ns CHHL t t HOLD# to output LOW-Z – – 8 ns 4 HHQX LZ t t HOLD# to output HIGH-Z – – 8 ns 4 HLQZ HZ t – WRITE PROTECT setup time 20 – – ns 6 WHSL t – WRITE PROTECT hold time 100 – – ns 6 SHWL CCMTD-1725822587-8430 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory AC Characteristics Table 27: AC Specifications (40 MHz, Device Grade 6, V [min]=2.3V) (Continued) CC Symbol Alt. Parameter Min Typ Max Unit Notes t – S# HIGH to DEEP POWER-DOWN mode – – 3 μs 4 DP t – S# HIGH to STANDBY without electronic signature read – – 30 μs 4 RES1 t – S# HIGH to STANDBY with electronic signature read – – 30 μs 4 RES2 Notes: 1. Applies to entire table: Maximum frequency in the VCC range 2.3V to 2.7V is 40MHz. 2. READ DATA BYTES at HIGHER SPEED, PAGE PROGRAM, SECTOR ERASE, BLOCK ERASE, DEEP POWER-DOWN, READ ELECTRONIC SIGNATURE, WRITE ENABLE/DISABLE, READ ID, READ/WRITE STATUS REGISTER 3. The t and t signals must be greater than or equal to 1/f . CH CL C 4. The t , t , t , t , t , t , t , and t signal values are guaranteed by CLCH CHCL SHQZ HHQX HLQZ DP RES1 RES2 characterization, not 100% tested in production. 5. The t and t signals clock rise and fall time values are expressed as a slew-rate. CLCH CHCL 6. The t and t signals are only applicable as a constraint for a WRITE STATUS REGIS- WHSL SHWL TER command when SRWD bit is set at 1. CCMTD-1725822587-8430 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory AC Characteristics Table 28: AC Specifications (75MHz, Device Grade 3 and 6, V [min]=2.7V) CC Symbol Alt. Parameter Min Typ Max Unit Notes f f Clock frequency for all commands (except READ) D.C. – 75 MHz C C f – Clock frequency for READ command D.C. – 33 MHz R t t Clock HIGH time 6 – – ns 3 CH CLH t t Clock LOW time 6 – – ns 3, 4 CL CLL t – Clock rise time (peak to peak) 0.1 – – V/ns 5, 6 CLCH t – Clock fall time (peak to peak) 0.1 – – V/ns 5, 6 CHCL t t S# active setup time (relative to C) 5 – – ns SLCH CSS t S# not active hold time (relative to C) 5 – – ns CHSL t t Data In setup time 2 – – ns DVCH DSU t t Data In hold time 5 – – ns CHDX DH t – S# active hold time (relative to C) 5 – – ns CHSH t – S# not active setup time (relative to C) 5 – – ns SHCH t t S# deselect time 100 – – ns SHSL CSH t t Output disable time – – 8 ns 5 SHQZ DIS t t Clock LOW to output valid under 30 pF – – 8 ns CLQV V Clock LOW to output valid under 10 pF – – 6 ns t t Output hold time 0 – – ns CLQX HO t – HOLD# setup time (relative to C) 5 – – ns HLCH t – HOLD# hold time (relative to C) 5 – – ns CHHH t – HOLD# setup time (relative to C) 5 – – ns HHCH t – HOLD# hold time (relative to C) 5 – – ns CHHL t t HOLD# to output LOW-Z – – 8 ns 5 HHQX LZ t t HOLD# to output HIGH-Z – – 8 ns 5 HLQZ HZ t – WRITE PROTECT setup time 20 – – ns 7 WHSL t – WRITE PROTECT hold time 100 – – ns 7 SHWL t – S# HIGH to DEEP POWER-DOWN mode – – 3 μs 5 DP t – S# HIGH to STANDBY without READ ELECTRONIC SIGNA- – – 30 μs 5 RES1 TURE t – S# HIGH to STANDBY with READ ELECTRONIC SIGNATURE – – 30 μs 5 RES2 Notes: 1. Applies to entire table: 110nm technology devices are identified by the process identifi- cation digit 4 in the device marking and the process letter B in the part number. 2. Applies to entire table: the AC specification values shown here are allowed only on the VCC range 2.7V to 3.6V. Maximum frequency in the VCC range 2.3V to 2.7V is 40MHz. 3. The t and t signal values must be greater than or equal to 1/f . CH CL C 4. Typical values are given for T = 25°C. A 5. The t , t , t , t , t , t , and t signal values are guaranteed by charac- CLCH CHCL SHQZ HHQX HLQZ DP RDP terization, not 100% tested in production. 6. The t and t signals clock rise and fall time values are expressed as a slew-rate. CLCH CHCL CCMTD-1725822587-8430 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory AC Characteristics 7. The t and t signal values are only applicable as a constraint for a WRITE STATUS WHSL SHWL REGISTER command when SRWD bit is set at 1. Figure 24: Serial Input Timing tSHSL S# tCHSL tSLCH tCHSH tSHCH C tDVCH tCHCL tCHDX tCLCH DQ0 MSB IN LSB IN high impedance DQ1 Figure 25: Write Protect Setup and Hold during WRSR when SRWD=1 Timing W#/VPP tSHWL tWHSL S# C DQ0 high impedance DQ1 CCMTD-1725822587-8430 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory AC Characteristics Figure 26: Hold Timing S# tHLCH tCHHL tHHCH C tCHHH tHLQZ tHHQX DQ1 DQ0 HOLD# Figure 27: Output Timing S# tCH C tCLQV tCLQV tCL tSHQZ tCLQX tCLQX DQ1 LSB OUT tQLQH tQHQL ADDRESS DQ0 LSB IN CCMTD-1725822587-8430 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Package Information Package Information Figure 28: SO8N 150 mils Body Width 0.25 MIN/ x 45° 0.50 MAX 1.75 MAX/ 1.25 MIN 0.17 MIN/ 0.23 MAX 0.10 MAX 0.28 MIN/ 0.48 MAX 1.27 TYP 0.25mm 4.90 ±0.10 Gauge plane 0o MIN/ 8o MAX 8 6.00 ±0.20 3.90 ±0.10 1 0.10 MIN/ 0.40 MIN/ 0.25 MAX 1.27 MAX 1.04 TYP Notes: 1. The 1 that appears in the top view of the package indicates the position of pin 1. 2. Drawing is not to scale. CCMTD-1725822587-8430 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Package Information Figure 29: SO8W 208 mils Body Width 1.70 MIN/ 1.78 MIN/ 1.91 MAX 2.16 MAX 0.15 MIN/ 0.25 MAX 0.36 MIN/ 0.48 MAX 0.1 MAX 1.27 TYP 5.08 MIN/ 5.49 MAX 7.70 MIN/ 8.10 MAX 5.08 MIN/ 5.49 MAX 1 0.05 MIN/ 0.25 MAX 0º MIN/ 0.5 MIN/ 10º MAX 0.8 MAX Note: 1. Drawing is not to scale. CCMTD-1725822587-8430 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Package Information Figure 30: PDIP8 300 mils Body Width -0.25 1.52 ±0.05 7.87 3.30 ±0.20 +0.38 4.80 MAX -0.38 3.30 0.50 MIN +0.51 0.21 MIN/ 0.38 MIN 2.54 TYP 0.35 MAX 7.62 TYP -1.18 8.80 9.20 ±0.10 +2.10 8 6.35 ±0.10 1 CCMTD-1725822587-8430 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Package Information Figure 31: VFDFPN8 (MLP8) 6mm x 5mm 0.15 C A A 6 TYP 0.10 MAX/ B 0 MIN 5.75 TYP B A 4.75 TYP Pin one C indicator +0.30 1.27 M 5 TYP 4 -0.20 TYP 0 1 0. 2x 0.10 C B B +0.08 C 0.10 C A 3.40 ±0.20 0.40 -0.05 5 +0.15 1 0.60 0. -0.10 θ 12° 0.05 +0.15 0.85 -0.05 0.20 TYP 0.65 TYP C 0 MIN/ 0.05 MAX Note: 1. Drawing is not to scale. CCMTD-1725822587-8430 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Package Information Figure 32: UFDFPN8 (MLP8) 4mm x 3mm 0.80 ±0.10 Datum A 4.00 ±0.10 A 1 2 3 4 B 8 x (0.60 ±0.05) Datum B 0.20 ±0.10 0.20 DIA TYP 3.00 ±0.10 (See note 1) 8 x (0.30 ±0.05) See detail A 2X 0.10 C 8 7 6 5 0.10 M C A B 1 2 2X 0.10 C 0.80 TYP 0.05 M C Top View Bottom View Datum A or B -0.10 0.55 +0.05 // 0.10 C C 0.60 ±0.05 0.05 C Seating Plane -0.02 0.02 0.80 TYP Terminal Tip +0.03 0.127 MIN/ 0.40 TYP 0.15 MAX Side View Even Terminal/Side Detail A Notes: 1. The dimension 0.30 ±0.05 applies to the metallic terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimensions should not be measured in that radius area. 2. Maximum package warping is 0.05mm; maximum allowable burrs is 0.076mm in all di- rections; the bilateral coplanarity zone applies to the exposed heat sink slug as well as to the terminals. 3. Drawing is not to scale. CCMTD-1725822587-8430 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Package Information Figure 33: UFDFPN8 (MLP8) 2mm x 3mm -0.10 -0.05 2.00 0.50 TYP 0.25 +0.10 +0.05 0.15 MAX 0.30 MIN 3.00 +-00..1100 0.20 +-00..1100 -0.05 0.45 +0.05 -0.10 1.60 -0.10 +0.10 0.55 +0.05 0.08 MAX -0.02 0.02 +0.03 Note: 1. Drawing is not to scale. CCMTD-1725822587-8430 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Device Ordering Information Device Ordering Information Standard Parts Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at micron.com. To com- pare features and specifications by device type, visit micron.com/products. Contact the factory for devices not found. For more information on how to identify products and top-side marking by the process identification letter, refer to technical note TN-12-24, "Serial Flash Memory Device Marking for the M25P, M25PE, M25PX, and N25Q Product Families." Table 29: Part Number Example Part Number Category Device Security Operating Device Packing Plating Automotive Type Density Features Voltage Package Grade Option Technology Lithography Grade M25P 40 – V MN 6 T P B A Table 30: Part Number Information Scheme Part Number Category Category Details Notes Device type M25P = Serial Flash memory for code storage Density 40 = 4Mb (512Kb x 8) Security features – = no extra security 1 Operating voltage V = V = 2.7V to 3.6V 2 CC Package MN = SO8N (150 mils width) MW = SO8W (208 mils width) MP = VFDFPN8 6mm x 5mm (MLP8) MB = UFDFPN8 2mm x 3mm (MLP8) MC = UFDFPN8 4mm x 3mm (MLP8) Device Grade 6 = Industrial temperature range: –40°C to 85°C. Device tested with standard test flow. 3 = Automotive temperature range: –40°C to 125°C. Device tested with high reliability 3, 4 test flow. Packing Option – = Standard packing tube T = Tape and reel packing Plating technology P or G = RoHS compliant Lithography B = 110nm technology, Fab 13 diffusion plant Automotive Grade A = Automotive: –40°C to 85°C part. Only with temperature grade 6. Device tested with 3 high reliability test flow. – = Automotive: –40°C to 125°C. Only with temperature grade 3. Notes: 1. Secure options are available upon customer request. CCMTD-1725822587-8430 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Device Ordering Information 2. Maximum frequency device operation in the extended Vcc range (2.3V to 2.7V) is only on the 40 MHz device. 3. Micron recommends the use of the automotive grade device in the automotive environ- ment, autograde 6 and grade 3. 4. Device grade 3 is available in an SO8 RoHS compliant package. Automotive Parts Table 31: Part Number Example Part Number Category Device Security Operating Device Packing Plating Automotive Type Density Features Voltage Package Grade Option Technology Lithography Grade M25P 40 – V MN 6 T P B A Table 32: Part Number Information Scheme Part Number Category Category Details Notes Device type M25P = Serial Flash memory for code storage Density 40 = 4Mb (512Kb x 8) Security features – = no extra security Operating voltage V = V = 2.7V to 3.6V 1 CC Package MN = SO8N (150 mils width) MB = UFDFPN8 2mm x 3mm (MLP8) Device Grade 6 = Industrial temperature range: –40°C to 85°C. Device tested with high reliability test flow. 3 = Automotive temperature range: –40°C to 125°C. Device tested with high reliability 2 test flow. Packing Option – = Standard packing tube T = Tape and reel packing Plating technology P or G = RoHS compliant Lithography B = 110nm technology, Fab 13 diffusion plant Automotive Grade A = Automotive: –40°C to 85°C part. Only with temperature grade 6. Device tested with 2 high reliability test flow. – = Automotive: –40°C to 125°C. Only with temperature grade 3. Notes: 1. Maximum frequency device operation in the extended Vcc range (2.3V to 2.7V) is only on the 40 MHz device. 2. Micron recommends the use of the automotive grade device in the automotive environ- ment, autograde 6 and grade 3. CCMTD-1725822587-8430 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Revision History Revision History Rev. H – 05/18 • Added Important Notes and Warnings section for further clarification aligning to in- dustry standards Rev. G – 05/13 • Reset Revision History to begin with Micron rebrand. • Removed all lithography information except for 110nm. Rev. F – 01/13 • Removed part numbers from page 1. • Updated READ Identification in the Command Set Codes table to include 9Eh infor- mation. • Updated SO8W 208 mils Body Width drawing. • Deleted DFN8 6mm x 5mm drawing. • Updated Device Ordering Information section. Rev. E – 08/12 • Updated Command Set to include RELEASE FROM DEEP POWER-DOWN. • Updated Memory Map to eliminate the 64KB block box. Rev. D – 04/12 • Updated dimensions for MB package in the Part Number Information Scheme table in Device Ordering Information. • In Signal Names table, changed direction column for DQ0 and DQ1 to input and out- put respectively. • Changed the Write Disable Command Sequenced graphic. • Revised Write Status Register topic. • Revised Power-Up/Down and Supply Line Decoupling topic. • Revised DFN8 6mm x 5mm package figure. Rev. C – 03/12 • Updated dimensions for MC package in the Part Number Information Scheme table in Device Ordering Information. Rev. B – 02/12 • Corrected error in SO8N package drawing. Rev. A – 09/2011 • Applied Micron branding. CCMTD-1725822587-8430 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.

M25P40 Serial Flash Embedded Memory Revision History 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. CCMTD-1725822587-8430 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. m25p40.pdf - Rev. H 05/18 EN © 2011 Micron Technology, Inc. All rights reserved.