LTM9011-14/ LTM9010-14/LTM9009-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Octal ADCs FEATURES DESCRIPTION n 8-Channel Simultaneous Sampling ADC The LTM®9011-14/LTM9010-14/LTM9009-14 are 8-chan- n 73.1dB SNR nel, simultaneous sampling 14-bit A/D converters designed n 88dB SFDR for digitizing high frequency, wide dynamic range signals. n Low Power: 140mW/113mW/94mW per Channel AC performance includes 73.1dB SNR and 88dB spurious n Single 1.8V Supply free dynamic range (SFDR). Low power consumption per n Serial LVDS Outputs: 1 or 2 Bits per Channel channel reduces heat in high channel count applications. n Selectable Input Ranges: 1V to 2V Integrated bypass capacitance and flow-through pinout P-P P-P n 800MHz Full Power Bandwidth S/H reduces overall board space requirements. n Shutdown and Nap Modes DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) n Serial SPI Port for Configuration and no missing codes over temperature. The transition n Internal Bypass Capacitance, No External noise is a low 1.2LSB . RMS Components The digital outputs are serial LVDS to minimize the num- n 140-Pin (11.25mm × 9mm) BGA Package ber of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit APPLICATIONS per channel option (1-lane mode). n Communications The ENC+ and ENC– inputs may be driven differentially n Cellular Base Stations or single-ended with a sine wave, PECL, LVDS, TTL, or n Software Defined Radios CMOS inputs. An internal clock duty cycle stabilizer al- n Portable Medical Imaging lows high performance at full speed for a wide range of n Multichannel Data Acquisition clock duty cycles. n Nondestructive Testing All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION 1.8V 1.8V LTM9011-14, 125Msps, VDD OVDD 2-Tone FFT, fIN = 70MHz and 75MHz CHANNEL 1 14-BIT OUT1A 0 ANALOG S/H INPUT ADC CORE OUT1B –10 –20 CHANNEL 2 14-BIT OUT2A –30 ANINALPOUGT S/H ADC CORE OUT2B FS)–40 • • • • • • SERDIAATLAIZER • • • • • • SLOVEUDRTSIPAULTIZSED TUDE (dB––6500 CHAANNNAELLO G8 S/H AD1C4 -CBOITRE OOUUTT88AB AMPLI––7800 INPUT –90 DATA –100 CLOCK ENCODE PLL OUT –110 INPUT FRAME –120 0 10 20 30 40 50 60 FREQUENCY (MHz) GND GND 9009101114 TA01b 9009101114 TA01 Rev D 1 Document Feedback For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) TOP VIEW Supply Voltages V , OV ................................................–0.3V to 2V DD DD A Analog Input Voltage (A +, A –, IN IN B PAR/SER, SENSE) (Note 3) ..........–0.3V to (V + 0.2V) DD C Digital Input Voltage (ENC+, ENC–, CS, D SDI, SCK) (Note 4) ....................................–0.3V to 3.9V E SDO (Note 4) .............................................–0.3V to 3.9V F Digital Output Voltage ................–0.3V to (OV + 0.3V) DD G Operating Temperature Range H LTM9011C, LTM9010C, LTM9009C .........0°C to 70°C J LTM9011I, LTM9010I, LTM9009I .........–40°C to 85°C K Storage Temperature Range ..................–55°C to 125°C L M N P 1 2 3 4 5 6 7 8 9 10 BGA PACKAGE 140-LEAD (11.25mm × 9.00mm × 2.72mm) TJMAX = 150°C, θJA = 30°C/W, θJC = 25°C/W, θJB = 15°C/W, θJCbottom = 12°C/W ORDER INFORMATION http://www.linear.com/product/LTM9011-14#orderinfo LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM9011CY-14#PBF LTM9011CY-14#PBF LTM9011Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C LTM9011IY-14#PBF LTM9011IY-14#PBF LTM9011Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C LTM9010CY-14#PBF LTM9010CY-14#PBF LTM9010Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C LTM9010IY-14#PBF LTM9010IY-14#PBF LTM9010Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C LTM9009CY-14#PBF LTM9009CY-14#PBF LTM9009Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C LTM9009IY-14#PBF LTM9009IY-14#PBF LTM9009Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev D 2 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 5) A LTM9011-14 LTM9010-14 LTM9009-14 PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Resolution (No Missing Codes) l 14 14 14 Bits Integral Linearity Error Differential Analog Input (Note 6) l –4.1 ±1.2 4.1 –3.25 ±1 3.25 –2.75 ±1 2.75 LSB Differential Linearity Error Differential Analog Input l –0.9 ±0.3 0.9 –0.8 ±0.3 0.8 –0.8 ±0.3 0.8 LSB Offset Error (Note 7) l –12 ±3 12 –12 ±3 12 –12 ±3 12 mV Gain Error Internal Reference –1.3 –1.3 –1.3 %FS External Reference l –2.6 –1.3 0 –2.6 –1.3 0 –2.6 –1.3 0 %FS Offset Drift ±20 ±20 ±20 µV/°C Full-Scale Drift Internal Reference ±35 ±35 ±35 ppm/°C External Reference ±25 ±25 ±25 ppm/°C Gain Matching External Reference ±0.2 ±0.2 ±0.2 %FS Offset Matching ±3 ±3 ±3 mV Transition Noise External Reference 1.2 1.2 1.2 LSB RMS ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 5) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Analog Input Range (A + – A –) 1.7V < V < 1.9V l 1 to 2 V IN IN IN DD P-P V Analog Input Common Mode (A + + A –)/2 Differential Analog Input (Note 8) l V – 100mV V V + 100mV V IN(CM) IN IN CM CM CM V External Voltage Reference Applied to SENSE External Reference Mode l 0.625 1.250 1.300 V SENSE I Analog Input Common Mode Current Per Pin, 125Msps 155 µA INCM Per Pin, 105Msps 130 µA Per Pin, 80Msps 100 µA I Analog Input Leakage Current 0 < A +, A – < V ,No Encode l –1 1 µA IN1 IN IN DD I PAR/SER Input Leakage Current 0 < PAR/SER < V l –3 3 µA IN2 DD I SENSE Input Leakage Current 0.625 < SENSE < 1.3V l –6 6 µA IN3 t Sample-and-Hold Acquisition Delay Time 0 ns AP t Sample-and-Hold Acquisition Delay Jitter 0.15 ps JITTER RMS CMRR Analog Input Common Mode Rejection Ratio 80 dB BW-3B Full-Power Bandwidth Figure 6 Test Circuit 800 MHz Rev D 3 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. A = –1dBFS. (Note 5) A IN LTM9011-14 LTM9010-14 LTM9009-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS SNR Signal-to-Noise Ratio 5MHz Input 73.1 73 73 dBFS 70MHz Input l 70.8 73 70.6 72.9 69.7 72.9 dBFS 140MHz Input 72.6 72.6 72.5 dBFS SFDR Spurious Free Dynamic Range 5MHz Input 88 88 88 dBFS 2nd or 3rd Harmonic 70MHz Input l 69 85 71 85 74 85 dBFS 140MHz Input 82 82 82 dBFS Spurious Free Dynamic Range 5MHz Input 90 90 90 dBFS 4th Harmonic or Higher 70MHz Input l 81 90 81 90 82 90 dBFS 140MHz Input 90 90 90 dBFS S/(N+D) Signal-to-Noise Plus 5MHz Input 73 73 72.9 dBFS Distortion Ratio 70MHz Input l 68.4 72.6 69.7 72.6 69.6 72.6 dBFS 140MHz Input 72 72 72 dBFS Crosstalk, Near Channel 10MHz Input (Note 12) –90 –90 –90 dBc Crosstalk, Far Channel 10MHz Input (Note 12) –105 –105 –105 dBc INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. A = –1dBFS. (Note 5) A IN PARAMETER CONDITIONS MIN TYP MAX UNITS V Output Voltage I = 0 0.5 • V – 25mV 0.5 • V 0.5 • V + 25mV V CM OUT DD DD DD V Output Temperature Drift ±25 ppm/°C CM V Output Resistance –600µA < I < 1mA 4 Ω CM OUT V Output Voltage I = 0 1.225 1.250 1.275 V REF OUT V Output Temperature Drift ±25 ppm/°C REF V Output Resistance –400µA < I < 1mA 7 Ω REF OUT V Line Regulation 1.7V < V < 1.9V 0.6 mV/V REF DD Rev D 4 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 5) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) V Differential Input Voltage (Note 8) l 0.2 V ID V Common Mode Input Voltage Internally Set 1.2 V ICM Externally Set (Note 8) l 1.1 1.6 V V Input Voltage Range ENC+, ENC– to GND l 0.2 3.6 V IN R Input Resistance (See Figure 10) 10 kΩ IN C Input Capacitance 3.5 pF IN Single-Ended Encode Mode (ENC– Tied to GND) V High Level Input Voltage V = 1.8V l 1.2 V IH DD V Low Level Input Voltage V = 1.8V l 0.6 V IL DD V Input Voltage Range ENC+ to GND l 0 3.6 V IN R Input Resistance (See Figure 11) 30 kΩ IN C Input Capacitance 3.5 pF IN DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) V High Level Input Voltage V = 1.8V l 1.3 V IH DD V Low Level Input Voltage V = 1.8V l 0.6 V IL DD I Input Current V = 0V to 3.6V l –10 10 µA IN IN C Input Capacitance 3 pF IN SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used) R Logic Low Output Resistance to GND V = 1.8V, SDO = 0V 200 Ω OL DD I Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA OH C Output Capacitance 3 pF OUT DIGITAL DATA OUTPUTS V Differential Output Voltage 100Ω Differential Load, 3.5mA Mode l 247 350 454 mV OD 100Ω Differential Load, 1.75mA Mode l 125 175 250 mV V Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode l 1.125 1.250 1.375 V OS 100Ω Differential Load, 1.75mA Mode l 1.125 1.250 1.375 V R On-Chip Termination Resistance Termination Enabled, OV = 1.8V 100 Ω TERM DD Rev D 5 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 9) A LTM9011-14 LTM9010-14 LTM9009-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS V Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DD OV Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DD I Analog Supply Current Sine Wave Input l 582 632 476 508 395 450 mA VDD I Digital Supply Current 2-Lane Mode, 1.75mA Mode l 54 62 52 62 50 58 mA OVDD 2-Lane Mode, 3.5mA Mode l 98 108 96 106 94 104 mA P Power Dissipation 2-Lane Mode, 1.75mA Mode l 1145 1249 950 1026 801 914 mW DISS 2-Lane Mode, 3.5mA Mode l 1224 1332 1030 1105 880 997 mW P Sleep Mode Power 2 2 2 mW SLEEP P Nap Mode Power 170 170 170 mW NAP P Power Decrease With Single-Ended Encode Mode Enabled 40 40 40 mW DIFFCLK (No Decrease for Sleep Mode) TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 5) A LTM9011-14 LTM9010-14 LTM9009-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS f Sampling Frequency (Notes 10,11) l 5 125 5 105 5 80 MHz S t ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 100 4.52 4.76 100 5.93 6.25 100 ns ENCL Duty Cycle Stabilizer On l 2 4 100 2 4.76 100 2 6.25 100 ns t ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 100 4.52 4.76 100 5.93 6.25 100 ns ENCH Duty Cycle Stabilizer On l 2 4 100 2 4.76 100 2 6.25 100 ns t Sample-and-Hold 0 0 0 ns AP Acquisition Delay Time SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (R = 100Ω Differential, C = 2pF to GND on Each Output) TERM L t Serial Data Bit Period 2-Lanes, 16-Bit Serialization 1/(8 • f ) s SER S 2-Lanes, 14-Bit Serialization 1/(7 • f ) s S 2-Lanes, 12-Bit Serialization 1/(6 • f ) s S 1-Lane, 16-Bit Serialization 1/(16 • f ) s S 1-Lane, 14-Bit Serialization 1/(14 • f ) s S 1-Lane, 12-Bit Serialization 1/(12 • f ) s S t FR to DCO Delay (Note 8) l 0.35 • t 0.5 • t 0.65 • t s FRAME SER SER SER t DATA to DCO Delay (Note 8) l 0.35 • t 0.5 • t 0.65 • t s DATA SER SER SER t Propagation Delay (Note 8) l 0.7n + 2 • t 1.1n + 2 • t 1.5n + 2 • t s PD SER SER SER t Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns R t Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns F DCO Cycle-Cycle Jitter t = 1ns 60 ps SER P-P Pipeline Latency 6 Cycles Rev D 6 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 5) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SPI Port Timing (Note 8) t SCK Period Write Mode l 40 ns SCK Read Back Mode, C = 20pF, l 250 ns SDO R = 2k PULLUP t CS to SCK Setup Time l 5 ns S t SCK to CS Setup Time l 5 ns H t SDI Setup Time l 5 ns DS t SDI Hold Time l 5 ns DH t SCK Falling to SDO Valid Read Back Mode, C = 20pF, l 125 ns DO SDO R = 2k PULLUP Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: Offset error is the offset voltage measured from –0.5 LSB when may cause permanent damage to the device. Exposure to any Absolute the output code flickers between 00 0000 0000 0000 and 11 1111 1111 Maximum Rating condition for extended periods may affect device 1111 in 2’s complement output mode. reliability and lifetime. Note 8: Guaranteed by design, not subject to test. Note 2: All voltage values are with respect to GND (unless otherwise Note 9: V = OV = 1.8V, f = 125MHz (LTM9011), 105MHz DD DD SAMPLE noted). (LTM9010), or 80MHz (LTM9009), 2-lane output mode, differential Note 3: When these pin voltages are taken below GND or above VDD, they ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential will be clamped by internal diodes. This product can handle input currents drive, unless otherwise noted. The supply current and power dissipation of greater than 100mA below GND or above V without latchup. specifications are totals for the entire device, not per channel. DD Note 4: When these pin voltages are taken below GND they will be Note 10: Recommended operating conditions. clamped by internal diodes. When these pin voltages are taken above VDD Note 11: The maximum sampling frequency depends on the speed grade they will not be clamped by internal diodes. This product can handle input of the part and also which serialization mode is used. The maximum serial currents of greater than 100mA below GND without latchup. data rate is 1000Mbps so t must be greater than or equal to 1ns. SER Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTM9011), 105MHz Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.7 to Ch.8. (LTM9010), or 80MHz (LTM9009), 2-lane output mode, differential ENC+/ Far-channel crosstalk refers to Ch.1 to Ch.7, Ch.1 to Ch.8, Ch.2 to Ch.7, and ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless Ch.2 to Ch.8. otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Rev D 7 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization* tAP N+1 ANALOG N INPUT ENC– tENCH tENCL ENC+ DCO– tSER DCO+ FR– tFRAME tDATA tSER FR+ OUT#A– tPD tSER D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 OUT#A+ OUT#B– D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 9009101114 TD01 *SEE THE DIGITAL OUTPUTS SECTION 2-Lane Output Mode, 14-Bit Serialization tAP ANALOG N+2 N INPUT N+1 ENC– tENCH tENCL ENC+ DCO– tSER DCO+ FR– tFRAME tDATA tSER FR+ OUT#A– tPD tSER D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 OUT#A+ OUT#B– D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 9009101114 TD02 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– Rev D 8 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TIMING DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization tAP ANALOG N N+1 INPUT ENC– tENCH tENCL ENC+ DCO– tSER DCO+ FR+ tFRAME tDATA tSER FR– OUT#A– tPD tSER D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 OUT#A+ OUT#B– D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 9009101114 TD03 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG N+1 N INPUT ENC– tENCH tENCL ENC+ DCO– tSER DCO+ FR– tFRAME tDATA tSER FR+ OUT#A– tPD tSER D1 D0 0 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 D13 D12 D11 D10 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 9009101114 TD04 OUT#B+, OUT#B– ARE DISABLED Rev D 9 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TIMING DIAGRAMS 1-Lane Output Mode, 14-Bit Serialization tAP ANALOG N+1 N INPUT ENC– tENCH tENCL ENC+ DCO– tSER DCO+ FR– tFRAME tDATA tSER FR+ OUT#A– tPD tSER D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-49009101114 TD06 OUT#B+, OUT#B– ARE DISABLED 1-Lane Output Mode, 12-Bit Serialization tAP ANALOG N+1 N INPUT ENC– tENCH tENCL ENC+ DCO– tSER DCO+ FR– tFRAME tDATA tSER FR+ OUT#A– tPD tSER D5 D4 D3 D2 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 9009101114 TD07 OUT#B+, OUT#B– ARE DISABLED Rev D 10 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TIMING DIAGRAMS SPI Port Timing (Readback Mode) tS tDS tDH tSCK tH CS SCK tDO SDI R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX SDO D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE SPI Port Timing (Write Mode) CS SCK SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO HIGH IMPEDANCE 9009101114 TD08 Rev D 11 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9011-14: Integral LTM9011-14: Differential LTM9011-14: 8k Point FFT, Nonlinearity (INL) Nonlinearity (DNL) f = 5MHz, –1dBFS, 125Msps IN 2.0 1.0 0 1.5 0.8 –10 –20 0.6 1.0 –30 ROR (LSB) 0.05 ROR (LSB) 00..042 UDE (dBFS)–––564000 R R T INL E–0.5 DNL E––00..42 AMPLI––7800 –1.0 –90 –0.6 –100 –1.5 –0.8 –110 –2.0 –1.0 –120 0 4096 8192 12288 16384 0 4096 8192 12288 16384 0 10 20 30 40 50 60 OUTPUT CODE OUTPUT CODE FREQUENCY (MHz) 9009101114 G01 9009101114 G02 9009101114 G03 LTM9011-14: 8k Point FFT, LTM9011-14: 8k Point FFT, LTM9011-14: 8k Point FFT, f = 30MHz, –1dBFS, 125Msps f = 70MHz, –1dBFS, 125Msps f = 140MHz, –1dBFS, 125Msps IN IN IN 0 0 0 –10 –10 –10 –20 –20 –20 –30 –30 –30 FS)–40 FS)–40 FS)–40 B B B E (d–50 E (d–50 E (d–50 UD–60 UD–60 UD–60 T T T LI–70 LI–70 LI–70 P P P AM–80 AM–80 AM–80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 9009101114 G04 9009101114 G05 9009101114 G06 LTM9011-14: 8k Point 2-Tone FFT, f = 70MHz, 75MHz, –7dBFS per LTM9011-14: Shorted Input IN Tone, 125Msps Histogram 0 6000 –10 –20 5000 –30 FS)–40 4000 B E (d–50 NT UD–60 OU3000 LIT–70 C P M A–80 2000 –90 –100 1000 –110 –120 0 0 10 20 30 40 50 60 8178 8180 8182 8184 8186 FREQUENCY (MHz) OUTPUT CODE 9009101114 G07 9009101114 G08 Rev D 12 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9011-14: SNR vs Input LTM9011-14: SFDR vs Input Frequency, –1dBFS, 2V Range, Frequency, –1dBFS, 2V Range, LTM9011-14: SFDR vs Input Level, 125Msps 125Msps fIN = 70MHz, 2V Range, 125Msps 74 95 110 dBFS 100 73 90 90 72 S) 80 SNR (dBFS) 776109 SFDR (dBFS) 8850 R (dBc AND dBF 65470000 dBc 75 D F 68 S 30 70 20 67 10 66 65 0 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) INPUT LEVEL (dBFS) 9009101114 G09 9009101114 G10 9009101114 G11 LTM9011-14: SNR vs Input Level, LTM9011-14: I vs Sample Rate, VDD f = 70MHz, 2V Range, 125Msps 5MHz Sine Wave Input, –1dBFS IN 80 580 dBFS 70 560 60 540 S) dBc F dB 50 520 D A) N m c A 40 (D500 B D d V R ( 30 I 480 N S 20 460 10 440 0 420 –60 –50 –40 –30 –20 –10 0 0 25 50 75 100 125 INPUT LEVEL (dBFS) SAMPLE RATE (Msps) 9009101114 G12 9009101114 G13 IOVDD vs Sample Rate, 5MHz Sine LTM9011-14: SNR vs SENSE, Wave Input, –1dBFS f = 5MHz, –1dBFS IN 100 74 2-LANE, 3.5mA 73 80 72 mA) 60 1-LANE, 3.5mA BFS) 71 (DD 2-LANE, 1.75mA R (d 70 V N IO 40 S 69 1-LANE, 1.75mA 68 20 67 0 66 0 25 50 75 100 125 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 SAMPLE RATE (Msps) SENSE PIN (V) 9009101114 G14 9009101114 G15 Rev D 13 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9010-14: Integral Nonlinearity LTM9010-14: Differential LTM9010-14: 8k Point FFT, (INL) Nonlinearity (DNL) f = 5MHz, –1dBFS, 105Msps IN 2.0 1.0 0 1.5 0.8 –10 –20 0.6 1.0 –30 ROR (LSB) 0.05 ROR (LSB) 00..042 UDE (dBFS)–––654000 R R T INL E–0.5 DNL E––00..42 AMPLI––7800 –1.0 –90 –0.6 –100 –1.5 –0.8 –110 –2.0 –1.0 –120 0 4096 8192 12288 16384 0 4096 8192 12288 16384 0 10 20 30 40 50 OUTPUT CODE OUTPUT CODE FREQUENCY (MHz) 9009101114 G16 9009101114 G17 9009101114 G18 LTM9010-14: 8k Point FFT, LTM9010-14: 8k Point FFT, LTM9010-14: 8k Point FFT, f = 30MHz, –1dBFS, 105Msps f = 70MHz, –1dBFS, 105Msps f = 140MHz, –1dBFS, 105Msps IN IN IN 0 0 0 –10 –10 –10 –20 –20 –20 –30 –30 –30 BFS)–40 BFS)–40 BFS)–40 UDE (d––6500 UDE (d––6500 UDE (d––6500 PLIT–70 PLIT–70 PLIT–70 AM–80 AM–80 AM–80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 9009101114 G19 9009101114 G20 9009101114 G21 LTM9010-14: 8k Point 2-Tone FFT, f = 70MHz, 75MHz, –7dBFS per LTM9010-14: Shorted Input IN Tone, 105Msps Histogram 0 6000 –10 –20 5000 –30 FS)–40 4000 B E (d–50 NT UD–60 OU3000 LIT–70 C P M A–80 2000 –90 –100 1000 –110 –120 0 0 10 20 30 40 50 8195 8197 8199 8201 8203 FREQUENCY (MHz) OUTPUT CODE 9009101114 G22 9009101114 G23 Rev D 14 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9010-14: SNR vs Input LTM9010-14: SFDR vs Input Frequency, –1dBFS, 2V Range, Frequency, –1dBFS, 2V Range, LTM9010-14: SFDR vs Input Level, 105Msps 105Msps f = 70MHz, 2V Range, 105Msps IN 74 95 110 dBFS 100 73 90 90 72 S) 80 SNR (dBFS) 776109 SFDR (dBFS) 8850 R (dBc AND dBF 65470000 dBc 75 D F 68 S 30 70 20 67 10 66 65 0 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) INPUT LEVEL (dBFS) 9009101114 G24 9009101114 G25 9009101114 G26 LTM9010-14: I vs Sample Rate, LTM9010-14: SNR vs SENSE, VDD 5MHz Sine Wave Input, –1dBFS f = 5MHz, –1dBFS IN 460 74 73 440 72 420 mA) 400 BFS) 71 (VDD380 NR (d 70 I S 69 360 68 340 67 320 66 0 25 50 75 100 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 SAMPLE RATE (Msps) SENSE PIN (V) 9009101114 G27 9009101114 G28 Rev D 15 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9009-14: Integral Nonlinearity LTM9009-14: Differential LTM9009-14: 8k Point FFT, (INL) Nonlinearity (DNL) f = 5MHz, –1dBFS, 80Msps IN 2.0 1.0 0 0.8 –10 1.5 –20 0.6 1.0 –30 INL ERROR (LSB)–00..505 DNL ERROR (LSB)––0000....42042 AMPLITUDE (dBFS)–––––7685400000 –1.0 –90 –0.6 –100 –1.5 –0.8 –110 –2.0 –1.0 –120 0 4096 8192 12288 16384 0 4096 8192 12288 16384 0 10 20 30 40 OUTPUT CODE OUTPUT CODE FREQUENCY (MHz) 9009101114 G29 9009101114 G30 9009101114 G31 LTM9009-14: 8k Point FFT, LTM9009-14: 8k Point FFT, LTM9009-14: 8k Point FFT, f = 30MHz, –1dBFS, 80Msps f = 70MHz, –1dBFS, 80Msps f = 140MHz, –1dBFS, 80Msps IN IN IN 0 0 0 –10 –10 –10 –20 –20 –20 –30 –30 –30 BFS)–40 BFS)–40 BFS)–40 UDE (d––6500 UDE (d––6500 UDE (d––6500 PLIT–70 PLIT–70 PLIT–70 AM–80 AM–80 AM–80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 0 10 20 30 40 0 10 20 30 40 0 10 20 30 40 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 9009101114 G32 9009101114 G33 9009101114 G34 LTM9009-14: 8k Point 2-Tone FFT, f = 70MHz, 75MHz, –7dBFS per LTM9009-14: Shorted Input IN Tone, 80Msps Histogram 0 6000 –10 –20 5000 –30 FS)–40 4000 B E (d–50 NT UD–60 OU3000 LIT–70 C P M A–80 2000 –90 –100 1000 –110 –120 0 0 10 20 30 40 8184 8186 8188 8190 8192 FREQUENCY (MHz) OUTPUT CODE 9009101114 G35 9009101114 G36 Rev D 16 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9009-14: SNR vs Input LTM9009-14: SFDR vs Input Frequency, –1dBFS, 2V Range, Frequency, –1dBFS, 2V Range, LTM9009-14: SFDR vs Input Level, 80Msps 80Msps fIN = 70MHz, 2V Range, 80Msps 74 95 110 73 90 100 dBFS 90 72 S) 80 85 F SNR (dBFS) 776109 SFDR (dBFS) 8705 DR (dBc AND dB 65470000 dBc F 68 S 30 70 20 67 10 66 65 0 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) INPUT LEVEL (dBFS) 9009101114 G37 9009101114 G38 9009101114 G39 LTM9009-14: IVDD vs Sample Rate, LTM9009-14: SNR vs SENSE, DCO Cycle-Cycle Jitter vs Serial 5MHz Sine Wave Input, –1dBFS f = 5MHz, –1dBFS Data Rate IN 380 74 350 73 300 360 72 R (ps) 250 I (mA)VDD334200 SNR (dBFS) 767190 O-PEAK JITTE 210500 T K- A 100 68 E 300 P 67 50 280 66 0 0 20 40 60 80 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 0 200 400 600 800 1000 SAMPLE RATE (Msps) SENSE PIN (V) SERIAL DATA RATE (Mbps) 9009101114 G40 9009101114 G41 9009101114 G42 Rev D 17 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 PIN FUNCTIONS A + (B2): Channel 1 Positive Differential Analog Input. A + (N1): Channel 8 Positive Differential Analog Input. IN1 IN8 A – (B1): Channel 1 Negative Differential Analog Input. A – (N2): Channel 8 Negative Differential Analog Input IN1 IN8 V (B3): Common Mode Bias Output, Nominally Equal V (D3, D4, E3, E4, K3, K4, L3, L4): 1.8V Analog Power CM14 DD to V /2. V should be used to bias the common mode Supply. V is internally bypassed to ground with 0.1μF DD CM DD of the analog inputs of channels 1 and 4. V is internally ceramic capacitors. CM bypassed to ground with a 0.1µF ceramic capacitor. No ENC+ (P5): Encode Input. Conversion starts on the rising external capacitance is required. edge. A + (C2): Channel 2 Positive Differential Analog Input. IN2 ENC– (P6): Encode Complement Input. Conversion starts A – (C1): Channel 2 Negative Differential Analog Input. on the falling edge. IN2 A + (E2): Channel 3 Positive Differential Analog Input. CSA (L5): In serial programming mode, (PAR/SER = 0V), IN3 CSA is the serial interface chip select input for registers A – (E1): Channel 3 Negative Differential Analog Input. IN3 controlling channels 1, 4, 5 and 8. When CS is low, SCK VCM23 (F3): Common Mode Bias Output, Nominally Equal is enabled for shifting data on SDI into the mode con- to VDD/2. VCM should be used to bias the common mode trol registers. In parallel programming mode (PAR/SER of the analog inputs of channels 2 and 3. VCM is internally = VDD), CS selects 2-lane or 1-lane output mode. CS can bypassed to ground with a 0.1µF ceramic capacitor. No be driven with 1.8V to 3.3V logic. external capacitance is required. CSB (M5): In serial programming mode, (PAR/SER = 0V), AIN4+ (G2): Channel 4 Positive Differential Analog Input. CSB is the serial interface chip select input for registers A – (G1): Channel 4 Negative Differential Analog Input. controlling channels 2, 3, 6 and 7. When CS is low, SCK IN4 is enabled for shifting data on SDI into the mode con- A + (H1): Channel 5 Positive Differential Analog Input. IN5 trol registers. In parallel programming mode (PAR/SER AIN5– (H2): Channel 5 Negative Differential Analog Input. = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. V (J3): Common Mode Bias Output, Nominally Equal CM67 to V /2. V should be used to bias the common mode SCK (L6): In serial programming mode, (PAR/SER = 0V), DD CM of the analog inputs of channels 6 and 7. V is internally SCK is the serial interface clock input. In parallel pro- CM bypassed to ground with a 0.1µF ceramic capacitor. No gramming mode (PAR/SER = VDD), SCK selects 3.5mA external capacitance is required. or 1.75mA LVDS output currents. SCK can be driven with 1.8V to 3.3V logic. A + (K1): Channel 6 Positive Differential Analog Input. IN6 SDI (M6): In serial programming mode, (PAR/SER = A – (K2): Channel 6 Negative Differential Analog Input. IN6 0V), SDI is the serial interface data Input. Data on SDI A + (M1): Channel 7 Positive Differential Analog Input. is clocked into the mode control registers on the rising IN7 edge of SCK. In parallel programming mode (PAR/SER = A – (M2): Channel 7 Negative Differential Analog Input. IN7 V ), SDI can be used to power down the part. SDI can DD VCM58 (N3): Common Mode Bias Output, Nominally Equal be driven with 1.8V to 3.3V logic. to V /2. V should be used to bias the common mode DD CM GND (See Pin Configuration Table): ADC Power Ground. of the analog inputs of channels 5 and 8. V is internally CM Use multiple vias close to pins. bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required. Rev D 18 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 PIN FUNCTIONS OV (G9, G10): Output Driver Supply. OV is internally LVDS Outputs DD DD bypassed to ground with a 0.1µF ceramic capacitor. All pins in this section are differential LVDS outputs. SDOA (E6): In serial programming mode, (PAR/SER = 0V), The output current level is programmable. There is an SDOA is the optional serial interface data output for reg- optional internal 100Ω termination resistor between the isters controlling channels 1, 4, 5 and 8. Data on SDO is pins of each LVDS output pair. read back from the mode control registers and can be OUT1A–/OUT1A+, OUT1B–/OUT1B+ (E7/E8, C8/D8): latched on the falling edge of SCK. SDO is an open-drain Serial Data Outputs for Channel 1. In 1-lane output mode N-channel MOSFET output that requires an external 2k only OUT1A–/OUT1A+ are used. pull-up resistor from 1.8V to 3.3V. If read back from the mode control registers is not needed, the pull-up resis- OUT2A–/OUT2A+, OUT2B–/OUT2B+ (B8/A8, D7/C7): tor is not necessary and SDO can be left unconnected. In Serial Data Outputs for Channel 2. In 1-lane output mode parallel programming mode (PAR/SER = V ), SDOA is an only OUT2A–/OUT2A+ are used. DD input that enables internal 100Ω termination resistors on OUT3A–/OUT3A+, OUT3B–/OUT3B+ (D10/D9, E10/E9): the digital outputs of channels 1, 4, 5 and 8. When used Serial Data Outputs for Channel 3. In 1-lane output mode as an input, SDO can be driven with 1.8V to 3.3V logic only OUT3A–/OUT3A+ are used. through a 1k series resistor. OUT4A–/OUT4A+, OUT4B–/OUT4B+ (C9/C10, F7/F8): SDOB (D6): Serial Data Output Pin for Channels 2, 3, 6 Serial Data Outputs for Channel 4. In 1-lane output mode and 7. See description for SDOA. only OUT4A–/OUT4A+ are used. PAR/SER (A7): Programming Mode Selection Pin. Connect OUT5A–/OUT5A+, OUT5B–/OUT5B+ (J8/J7, K8/K7): Serial to ground to enable the serial programming mode. CSA, Data Outputs for Channel 5. In 1-lane output mode only CSB, SCK, SDI, SDOA and SDOB become a serial interface OUT5A–/OUT5A+ are used. that control the A/D operating modes. Connect to V to DD OUT6A–/OUT6A+, OUT6B–/OUT6B+ (K9/K10, L9/L10): enable parallel programming mode where CSA, CSB, SCK, Serial Data Outputs for Channel 6. In 1-lane output mode SDI, SDOA and SDOB become parallel logic inputs that only OUT6A–/OUT6A+ are used. control a reduced set of the A/D operating modes. PAR/ SER should be connected directly to ground or the VDD OUT7A–/OUT7A+, OUT7B–/OUT7B+ (M7/L7, P8/N8): of the part and not be driven by a logic signal. Serial Data Outputs for Channel 7. In 1-lane output mode only OUT7A–/OUT7A+ are used. V (B6): Reference Voltage Output. V is internally REF REF bypassed to ground with a 1μF ceramic capacitor, nomi- OUT8A–/OUT8A+, OUT8B–/OUT8B+ (L8/M8, M10/M9): nally 1.25V. Serial Data Outputs for Channel 8. In 1-lane output mode only OUT8A–/OUT8A+ are used. SENSE (C5): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V FRA–/FRA+ (H7/H8): Frame Start Outputs for Channels input range. Connecting SENSE to ground selects the 1, 4, 5 and 8. internal reference and a ±0.5V input range. An external FRB–/FRB+ (J9/J10): Frame Start Outputs for Channels reference between 0.625V and 1.3V applied to SENSE 2, 3, 6 and 7. selects an input range of ±0.8 • V . SENSE is inter- SENSE nally bypassed to ground with a 0.1µF ceramic capacitor. DCOA–/DCOA+ (G8/G7): Data Clock Outputs for Channels 1, 4, 5 and 8. DCOB–/DCOB+ (F10, F9): Data Clock Outputs for Chan- nels 2, 3, 6 and 7. Rev D 19 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 PIN CONFIGURATION TABLE 1 2 3 4 5 6 7 8 9 10 A GND GND GND GND GND GND PAR/SER OUT2A+ GND GND B A – A + V GND GND V GND OUT2A– GND GND IN1 IN1 CM14 REF C A – A + GND GND SENSE GND OUT2B+ OUT1B– OUT4A– OUT4A+ IN2 IN2 D GND GND V V GND SDOB OUT2B– OUT1B+ OUT3A+ OUT3A– DD DD E A – A + V V GND SDOA OUT1A– OUT1A+ OUT3B+ OUT3B– IN3 IN3 DD DD F GND GND V GND GND GND OUT4B– OUT4B+ DCOB+ DCOB– CM23 G A – A + GND GND GND GND DCOA+ DCOA– OV OV IN4 IN4 DD DD H A + A – GND GND GND GND FRA– FRA+ GND GND IN5 IN5 J GND GND V GND GND GND OUT5A+ OUT5A– FRB– FRB+ CM67 K A + A – V V GND GND OUT5B+ OUT5B– OUT6A– OUT6A+ IN6 IN6 DD DD L GND GND V V CSA SCK OUT7A+ OUT8A– OUT6B– OUT6B+ DD DD M A + A – GND GND CSB SDI OUT7A– OUT8A+ OUT8B+ OUT8B– IN7 IN7 N A + A – V GND GND GND GND OUT7B+ GND GND IN8 IN8 CM58 P GND GND GND GND ENC+ ENC– GND OUT7B– GND GND Top View of BGA Package (Looking Through Component). Rev D 20 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 FUNCTIONAL BLOCK DIAGRAM VDD = 1.8V OVDD = 1.8V ANACLHO G1 S/H AD1C4 -CBOITRE OOOUUUTTT111AAB+–+ INPUT OUT1B– ANACLHO G2 S/H AD1C4 -CBOITRE OOOUUUTTT222AAB+–+ INPUT OUT2B– ANACLHO G3 S/H AD1C4 -CBOITRE OOOUUUTTT333AAB+–+ INPUT OUT3B– ANACLHO G4 S/H AD1C4 -CBOITRE OOOUUUTTT444AAB+–+ INPUT OUT4B– DATA SERIALIZER ANACLHO G5 S/H AD1C4 -CBOITRE OOOUUUTTT555AAB+–+ INPUT OUT5B– ANACLHO G6 S/H AD1C4 -CBOITRE OOOUUUTTT666AAB+–+ INPUT OUT6B– ANACLHO G7 S/H AD1C4 -CBOITRE OOOUUUTTT777AAB+–+ INPUT OUT7B– ANACLHO G8 S/H AD1C4 -CBOITRE OOOUUUTTT888AAB+–+ INPUT OUT8B– ENC+ DCOA± PLL DCOB± FRA± ENC– FRB± 1.25V REFERENCE SDOA SDOB VREF REFH REFL MODE SDI RANGE CONTROL SCK SELECT REGISTERS CSA CSB PAR/SER REF VDD/2 BUFFER DIFF REF AMP GND 9009101114 F01 SENSE VCM14 VCM58 VCM23 VCM67 Figure 1. Figure 1. Functional Block Diagram Rev D 21 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION CONVERTER OPERATION INPUT DRIVE CIRCUITS The LTM9011-14/LTM9010-14/LTM9009-14 are low Input Filtering power, 8-channel, 14-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The If possible, there should be an RC low pass filter right at analog inputs should be driven differentially. The encode the analog inputs. This lowpass filter isolates the drive cir- input can be driven differentially for optimal jitter perfor- cuitry from the A/D sample-and-hold switching, and also mance, or single-ended for lower power consumption. limits wideband noise from the drive circuitry. Figure 3 The digital outputs are serial LVDS to minimize the num- shows an example of an input RC filter. The RC component ber of data lines. Each channel outputs two bits at a time values should be chosen based on the application’s input (2-lane mode). At lower sampling rates there is a one bit frequency. per channel option (1-lane mode). Many additional fea- Transformer Coupled Circuits tures can be chosen by programming the mode control registers through a serial SPI port. Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center ANALOG INPUT tap is biased with VCM, setting the A/D input at its opti- mal DC level. At higher input frequencies a transmission The analog inputs are differential CMOS sample-and-hold line balun transformer (Figures 4 to 6) has better balance, circuits (Figure 2). The inputs should be driven differen- resulting in lower A/D distortion. tially around a common mode voltage set by the appropri- ate V output pins, which are nominally V /2. For the CM DD 2V input range, the inputs should swing from V – 0.5V CM 50Ω VCM to V + 0.5V. There should be 180° phase difference CM 0.1µF between the inputs. 0.1µF T1 ANALOG 1:1 25Ω AIN+ The eight channels are simultaneously sampled by a INPUT LTM9011-14 shared encode circuit (Figure 2). 25Ω 0.1µF 12pF 25Ω LTM9011-14 VDD 25Ω AIN– CSAMPLE T1: MA/COM MABAES0060 10Ω 2R5OΩN 3.5pF RESISTORS, CAPACITORS 9009101114 F03 AIN+ ARE 0402 PACKAGE SIZE CPARASITIC 1.8pF VDD CSAMPLE Figure 3. Analog Input Circuit Using a Transformer. RON 3.5pF 10Ω 25Ω Recommended for Input Frequencies from 5MHz to 70MHz AIN– VDD CPARASITIC 1.8pF 1.2V 10k ENC+ ENC– 10k 1.2V 9009101114 F02 Figure 2. Equivalent Input Circuit. Only One of the Eight Analog Channels Is Shown Rev D 22 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Amplifier Circuits At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain Figure 7 shows the analog input being driven by a high block is single-ended, then a transformer circuit (Figures speed differential amplifier. The output of the amplifier is 4 to 6) should convert the signal to differential before AC-coupled to the A/D so the amplifier’s output common driving the A/D. mode voltage can be optimally set to minimize distortion. See back page for a DC-coupled example. 50Ω VCM 50Ω VCM 0.1µF 0.1µF 0.1µF 0.1µF ANALOG T2 AIN+ ANALOG T2 AIN+ INPUT T1 LTM9011-14 INPUT T1 LTM9011-14 25Ω 0.1µF 25Ω 0.1µF 4.7pF 1.8pF 0.1µF 25Ω 0.1µF 25Ω AIN– AIN– 9009101114 F04 9009101114 F05 T1: MA/COM MABA-007159-000000 T1: MA/COM MABA-007159-000000 T2: MA/COM MABAES0060 T2: COILCRAFT WBC1-1LB RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 4. Recommended Front End Circuit for Input Figure 5. Recommended Front End Circuit for Input Frequencies from 70MHz to 170MHz Frequencies from 170MHz to 300MHz 50Ω VCM VCM 0.1µF HIGH SPEED 0.1µF 0.1µF DIFFERENTIAL0.1µF 200Ω 200Ω ANALOG 2.7nH AIN+ AMPLIFIER 25Ω AIN+ INPUT 25Ω 0.1µF LTM9011-14 ANIANLPOUGT + + LTM9011-14 T1 12pF 0.1µF 25Ω 2.7nH AIN– – – 0.1µF 25Ω AIN– 9009101114 F06 9009101114 F07 T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 6. Recommended Front End Circuit for Input Figure 7. Front End Circuit Using a High Speed Frequencies Above 300MHz Differential Amplifier Rev D 23 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Reference The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range The LTM9011-14/LTM9010-14/LTM9009-14 has an inter- will then be 1.6 • V . The reference is shared by all nal 1.25V voltage reference. For a 2V input range using SENSE eight ADC channels, so it is not possible to independently the internal reference, connect SENSE to V . For a 1V DD adjust the input range of individual channels. input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, The V , SENSE, REFH and REFL pins are internally REF apply a 1.25V reference voltage to SENSE (Figure 9). bypassed, as shown in Figure 8. VREF LTM9011-14 1.25V 5Ω 1.25V BANDGAP REFERENCE 1µF 0.625V RANGE DETECT AND CONTROL TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; SENSE RA0N.6G5EV =< 1V.S6E •N VSSE E<N S1E.3 F0O0RV 0.1µF INTERNAL ADC BUFFER 0.1µF HIGH REFERENCE REFH 2.2µF 0.1µF 0.8x DIFF AMP 0.1µF REFL INTERNAL ADC LOW REFERENCE 9009101114 F08 Figure 8. Reference Circuit LTM9011-14 1.25V EXTERNAL SENSE REFERENCE 1µF 9009101114 F09 Figure 9. Using an External 1.25V Reference Rev D 24 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Encode Input The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken The signal quality of the encode inputs strongly affects above V (up to 3.6V), and the common mode range is the A/D noise performance. The encode inputs should DD from 1.1V to 1.6V. In the differential encode mode, ENC– be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes should stay at least 200mV above ground to avoid falsely of operation for the encode inputs: the differential encode triggering the single-ended encode mode. For good jitter mode (Figure 10), and the single-ended encode mode performance ENC+ should have fast rise and fall times. (Figure 11). The single-ended encode mode should be used with The differential encode mode is recommended for sinu- CMOS encode inputs. To select this mode, ENC– is con- soidal, PECL, or LVDS encode inputs (Figures 12 and 13). nected to ground and ENC+ is driven with a square wave LTM9011-14 VDD DIFFERENTIAL COMPARATOR VDD 15k ENC+ LTM9011-14 1.8V TO ENC– 3.3V ENC+ 30k 0V ENC– 30k CMOS LOGIC BUFFER 9009101114 F10 9009101114 F11 Figure 10. Equivalent Encode Input Circuit Figure 11. Equivalent Encode Input Circuit for for Differential Encode Mode Single-Ended Encode Mode 0.1µF T1 ENC+ LTM9011-14 0.1µF 50Ω ENC+ 100Ω PECL OR 0.1µF 50Ω LVDS LTM9011-14 CLOCK 0.1µF 0.1µF ENC– ENC– 9009101114 F12 9009101114 F13 T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 12. Sinusoidal Encode Drive Figure 13. PECL or LVDS Encode Drive Rev D 25 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION encode input. ENC+ can be taken above V (up to 3.6V) serialization (see the Timing Diagrams section for details). DD so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ Note that with 12-bit serialization the two LSBs are not threshold is 0.9V. For good jitter performance ENC+ available—this mode is included for compatibility with should have fast rise and fall times. 12-bit versions of these parts. The output data should be latched on the rising and falling Clock PLL and Duty Cycle Stabilizer edges of the data clock out (DCO). A data frame output The encode clock is multiplied by an internal phase-locked (FR) can be used to determine when the data from a new loop (PLL) to generate the serial digital output data. If the conversion result begins. In the 2-lane, 14-bit serialization encode signal changes frequency or is turned off, the PLL mode, the frequency of the FR output is halved. requires 25µs to lock onto the input clock. The maximum serial data rate for the data outputs is A clock duty cycle stabilizer circuit allows the duty cycle 1Gbps, so the maximum sample rate of the ADC will de- of the applied encode signal to vary from 30% to 70%. pend on the serialization mode as well as the speed grade In the serial programming mode it is possible to disable of the ADC (see Table 1). The minimum sample rate for the duty cycle stabilizer, but this is not recommended. In all serialization modes is 5Msps. the parallel programming mode the duty cycle stabilizer is always enabled. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode volt- DIGITAL OUTPUTS age. An external 100Ω differential termination resistor is required for each LVDS output pair. The termination The digital outputs of the LTM9011-14/LTM9010-14/ resistors should be located as close as possible to the LTM9009-14 are serialized LVDS signals. Each channel LVDS receiver. outputs two bits at a time (2-lane mode). At lower sam- pling rates there is a one bit per channel option (1-lane The outputs are powered by OV which is independent DD mode). The data can be serialized with 16, 14, or 12-bit from the A/D core power. Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTM9011-14. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTM9010-14) or 80MHz (LTM9009-14). MAXIMUM SAMPLING SERIALIZATION MODE FREQUENCY, f (MHz) DCO FREQUENCY FR FREQUENCY SERIAL DATA RATE S 2-Lane 16-Bit Serialization 125 4 • f f 8 • f S S S 2-Lane 14-Bit Serialization 125 3.5 • f 0.5 • f 7 • f S S S 2-Lane 12-Bit Serialization 125 3 • f f 6 • f S S S 1-Lane 16-Bit Serialization 62.5 8 • f f 16 • f S S S 1-Lane 14-Bit Serialization 71.4 7 • f f 14 • f S S S 1-Lane 12-Bit Serialization 83.3 6 • f f 12 • f S S S Rev D 26 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Programmable LVDS Output Current Table 2. Output Codes vs Input Voltage A + – A – D13-D0 D13-D0 The default output driver current is 3.5mA. This current IN IN (2V RANGE) (OFFSET BINARY) (2’s COMPLEMENT) can be adjusted by control register A2 in the serial pro- >1.000000V 11 1111 1111 1111 01 1111 1111 1111 gramming mode. Available current levels are 1.75mA, +0.999878V 11 1111 1111 1111 01 1111 1111 1111 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the par- +0.999756V 11 1111 1111 1110 01 1111 1111 1110 allel programming mode, the SCK pin can select either +0.000122V 10 0000 0000 0001 00 0000 0000 0001 3.5mA or 1.75mA. +0.000000V 10 0000 0000 0000 00 0000 0000 0000 –0.000122V 01 1111 1111 1111 11 1111 1111 1111 Optional LVDS Driver Internal Termination –0.000244V 01 1111 1111 1110 11 1111 1111 1110 In most cases, using just an external 100Ω termina- –0.999878V 00 0000 0000 0001 10 0000 0000 0001 tion resistor will give excellent LVDS signal integrity. In –1.000000V 00 0000 0000 0000 10 0000 0000 0000 addition, an optional internal 100Ω termination resistor <–1.000000V 00 0000 0000 0000 10 0000 0000 0000 can be enabled by serially programming mode con- trol register A2. The internal termination helps absorb Digital Output Randomizer any reflections caused by imperfect termination at the Interference from the A/D digital outputs is sometimes receiver. When the internal termination is enabled, the unavoidable. Digital interference may be from capacitive output driver current is doubled to maintain the same or inductive coupling or coupling through the ground output voltage swing. In the parallel programming plane. Even a tiny coupling factor can cause unwanted mode the SDO pin enables internal termination. Internal tones in the ADC output spectrum. By randomizing the termination should only be used with 1.75mA, 2.1mA or digital output before it is transmitted off chip, these 2.5mA LVDS output current modes. unwanted tones can be randomized which reduces the unwanted tone amplitude. DATA FORMAT The digital output is randomized by applying an exclusive- Table 2 shows the relationship between the analog input OR logic operation between the LSB and all other data voltage and the digital data output bits. By default the output bits. To decode, the reverse operation is applied output data format is offset binary. The 2’s complement —an exclusive-OR operation is applied between the format can be selected by serially programming mode LSB and all other bits. The FR and DCO outputs are not control register A1. affected. The output randomizer is enabled by serially programming mode control register A1. Rev D 27 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Digital Output Test Pattern DEVICE PROGRAMMING MODES To allow in-circuit testing of the digital interface to the The operating modes of the LTM9011-14/LTM9010-14/ A/D, there is a test mode that forces the A/D data outputs LTM9009-14 can be programmed by either a parallel (D13-D0) of all channels to known values. The digital interface or a simple serial interface. The serial interface output test patterns are enabled by serially programming has more flexibility and can program all available modes. mode control registers A3 and A4. When enabled, the test The parallel interface is more limited and can only pro- patterns override all other formatting modes: 2’s comple- gram some of the more commonly used modes. ment and randomizer. Parallel Programming Mode Output Disable To use the parallel programming mode, PAR/SER should The digital outputs may be disabled by serially program- be tied to V . The CS, SCK, SDI and SDO pins are binary DD ming mode control register A2. The current drive for all logic inputs that set certain operating modes. These pins digital outputs including DCO and FR are disabled to save can be tied to V or ground, or driven by 1.8V, 2.5V, or DD power or enable in-circuit testing. When disabled the com- 3.3V CMOS logic. When used as an input, SDO should mon mode of each output pair becomes high impedance, be driven through a 1k series resistor. Table 3 shows the but the differential impedance may remain low. modes set by CS, SCK, SDI and SDO. Sleep and Nap Modes Table 3. Parallel Programming Mode Control Bits (PAR/SER = V ) DD The A/D may be placed in sleep or nap modes to con- Pin DESCRIPTION serve power. In sleep mode the entire device is powered CS 2-Lane / 1-Lane Selection Bit down, resulting in 2mW power consumption. Sleep mode 0 = 2-Lane, 16-Bit Serialization Output Mode is enabled by mode control register A1 (serial program- 1 = 1-Lane, 14-Bit Serialization Output Mode ming mode), or by SDI (parallel programming mode). The SCK LVDS Current Selection Bit time required to recover from sleep mode is about 2ms. 0 = 3.5mA LVDS Current Mode In nap mode any combination of A/D channels can be 1 = 1.75mA LVDS Current Mode powered down while the internal reference circuits and the SDI Power Down Control Bit PLL stay active, allowing faster wakeup than from sleep 0 = Normal Operation 1 = Sleep Mode mode. Recovering from nap mode requires at least 100 SDO Internal Termination Selection Bit clock cycles. If the application demands very accurate DC 0 = Internal Termination Disabled settling then an additional 50µs should be allowed so the 1 = Internal Termination Enabled on-chip references can settle from the slight temperature shift caused by the change in supply current as the A/D Serial Programming Mode leaves nap mode. Nap mode is enabled by mode control register A1 in the serial programming mode. To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control reg- isters. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising Rev D 28 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION edges of SCK. Any SCK rising edges after the first 16 bits (A6:A0) will be read back on the SDO pin (see the are ignored. The data transfer ends when CS is taken Timing Diagrams section). During a read back command high again. the register is not updated and data on SDI is ignored. The first bit of the 16-bit input word is the R/W bit. The The SDO pin is an open-drain output that pulls to ground next seven bits are the address of the register (A6:A0). with a 200Ω impedance. If register data is read back The final eight bits are the register data (D7:D0). through SDO, an external 2k pull-up resistor is required. If the R/W bit is low, the serial data (D7:D0) will be writ- If serial data is only written and read back is not needed, ten to the register set by the address bits (A6:A0). If the then SDO can be left floating and no pull-up resistor R/W bit is high, data in the register set by the address is needed. Table 4 shows a map of the mode control registers. Table 4. Serial Programming Mode Register Map (PAR/SER = GND) REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 D6 D5 D4 D3 D2 D1 D0 RESET X X X X X X X Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7 RESET Software Reset Bit 0 = Not Used 1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. After the Reset SPI Write Command Is Complete, Bit D7 Is Automatically Set Back to Zero. The Reset Register Is Write Only. Bits 6-0 Unused, Don’t Care Bits. REGISTER A1 (CSA): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSA = GND) D7 D6 D5 D4 D3 D2 D1 D0 DCSOFF RAND TWOSCOMP SLEEP NAP_8 NAP_5 NAP_4 NAP_1 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended. Bit 6 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 5 TWOSCOMP Two’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two’s Complement Data Format Bits 4-0 SLEEP: NAP_X Sleep/Nap Mode Control Bits 00000 = Normal Operation 0XXX1 = Channel 1 in Nap Mode 0XX1X = Channel 4 in Nap Mode 0X1XX = Channel 5 in Nap Mode 01XXX = Channel 8 in Nap Mode 1XXXX = Sleep Mode. Channels 1, 4, 5 and 8 Are Disabled Note: Any Combination of Channels Can Be Placed in Nap Mode. Rev D 29 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION REGISTER A1 (CSB): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSB = GND) D7 D6 D5 D4 D3 D2 D1 D0 DCSOFF RAND TWOSCOMP SLEEP NAP_7 NAP_6 NAP_3 NAP_2 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended. Bit 6 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 5 TWOSCOMP Two’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two’s Complement Data Format Bits 4-0 SLEEP: NAP_4:NAP_1 Sleep/Nap Mode Control Bits 00000 = Normal Operation 0XXX1 = Channel 2 in Nap Mode 0XX1X = Channel 3 in Nap Mode 0X1XX = Channel 6 in Nap Mode 01XXX = Channel 7 in Nap Mode 1XXXX = Sleep Mode. Channels 2, 3, 6 and 7 Are Disabled Note: Any Combination of Channels Can Be Placed in Nap Mode. REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 D6 D5 D4 D3 D2 D1 D0 ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE2 OUTMODE1 OUTMODE0 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bits 7-5 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current Bit 4 TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current Is 2x the Current Set by ILVDS2:ILVDS0. Internal Termination Should Only Be Used with 1.75mA, 2.1mA or 2.5mA LVDS Output Current Modes. Bit 3 OUTOFF Output Disable Bit 0 = Digital Outputs Are Enabled. 1 = Digital Outputs Are Disabled. Bits 2-0 OUTMODE2:OUTMODE0 Digital Output Mode Control Bits 000 = 2-Lanes, 16-Bit Serialization 001 = 2-Lanes, 14-Bit Serialization 010 = 2-Lanes, 12-Bit Serialization 011 = Not Used 100 = Not Used 101 = 1-Lane, 14-Bit Serialization 110 = 1-Lane, 12-Bit Serialization 111 = 1-Lane, 16-Bit Serialization Rev D 30 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h) D7 D6 D5 D4 D3 D2 D1 D0 OUTTEST X TP13 TP12 TP11 TP10 TP9 TP8 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7 OUTTEST Digital Output Test Pattern Control Bit 0 = Digital Output Test Pattern Off 1 = Digital Output Test Pattern On Bit 6 Unused, Don’t Care Bit. Bit 5-0 TP13:TP8 Test Pattern Data Bits (MSB) TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8. REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h) D7 D6 D5 D4 D3 D2 D1 D0 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7-0 TP7:TP0 Test Pattern Data Bits (LSB) TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB). Software Reset Bypass capacitors are integrated inside the package; addi- tional capacitance is optional. If serial programming is used, the mode control regis- ters should be programmed as soon as possible after The analog inputs, encode signals, and digital outputs the power supplies turn on and are stable. The first serial should not be routed next to each other. Ground fill and command must be a software reset which will reset all grounded vias should be used as barriers to isolate these register data bits to logic 0. To perform a software reset, signals from each other. bit D7 in the reset register is written with a logic 1. After The pin assignments of the LTM9011-14/LTM9010-14/ the reset SPI write command is complete, bit D7 is auto- LTM9009-14 allow a flow-through layout that makes it matically set back to zero. possible to use multiple parts in a small area when a large number of ADC channels are required. The LTM9011 GROUNDING AND BYPASSING module has similar layout rules to other BGA pack- ages. The layout can be implemented with 6mil blind The LTM9011-14/LTM9010-14/LTM9009-14 requires vias and 5mil traces. The pinout has been designed to a printed circuit board with a clean unbroken ground minimize the space required to route the analog and plane. A multilayer board with an internal ground plane digital traces. The analog and digital traces can essen- in the first layer beneath the ADC is recommended. tially be routed within the width of the package. This Layout for the printed circuit board should ensure that allows multiple packages to be located close together digital and analog signal lines are separated as much for high channel count applications. Trace lengths as possible. In particular, care should be taken not to for the analog inputs and digital outputs should be run any digital track alongside an analog signal track or matched as well as possible. underneath the ADC. Rev D 31 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Table 5 lists the trace lengths for the analog inputs and HEAT TRANSFER digital outputs inside the package from the die pad to the Most of the heat generated by the LTM9011-14/LTM9010-14/ package pad. These should be added to the PCB trace LTM9009-14 is transferred from the die through the bot- lengths for best matching. tom of the package onto the printed circuit board. The The material used for the substrate is BT (bismaleimide- ground pins should be connected to the internal ground planes by multiple vias. triazine), supplied by Mitsubishi Gas and Chemical. In the DC to 125MHz range, the speed for the analog input signals is 198ps/in or 7.795ps/mm. The speed for the digital outputs is 188.5ps/in or 7.417ps/mm. Table 5. Internal Trace Lengths LENGTH LENGTH LENGTH LENGTH PIN NAME (mm) PIN NAME (mm) PIN NAME (mm) PIN NAME (mm) E7 OUT1A– 1.775 K8 OUT5B– 0.379 E1 A – 2.491 F10 DCOB– 1.811 IN3 E8 OUT1A+ 1.947 K7 OUT5B+ 0.528 E2 A + 2.505 F9 DCOB+ 1.812 IN3 C8 OUT1B– 1.847 K9 OUT6A– 1.866 G1 A – 3.376 H7 FRA– 1.117 IN4 D8 OUT1B+ 1.850 K10 OUT6A+ 1.865 G2 A + 3.372 H8 FRA+ 1.038 IN4 B8 OUT2A– 3.233 L9 OUT6B– 2.268 H2 A – 3.301 J9 FRB– 1.644 IN5 A8 OUT2A+ 3.246 L10 OUT6B+ 2.267 H1 A + 3.346 J10 FRB+ 1.643 IN5 D7 OUT2B– 0.179 M7 OUT7A– 1.089 K2 A – 2.506 A7 PAR/SER 3.838 IN6 C7 OUT2B+ 1.127 L7 OUT7A+ 0.179 K1 A + 2.533 L6 SCK 0.240 IN6 D10 OUT3A– 2.126 P8 OUT7B– 3.281 M2 A – 3.198 E6 SDOA 0.453 IN7 D9 OUT3A+ 2.177 N8 OUT7B+ 3.149 M1 A + 3.214 D6 SDOB 0.274 IN7 E10 OUT3B– 1.811 L8 OUT8A– 1.862 N2 A – 4.726 M6 SDI 1.069 IN8 E9 OUT3B+ 1.812 M8 OUT8A+ 1.847 N1 A + 4.691 B3 V 3.914 IN8 CM14 C9 OUT4A– 3.199 M10 OUT8B– 4.021 P6 ENC– 4.106 F3 V 0.123 CM23 C10 OUT4A+ 3.196 M9 OUT8B+ 4.016 P5 ENC+ 4.106 J3 V 0.079 CM67 F7 OUT4B– 0.706 B1 A – 4.689 L5 CSA 0.919 N3 V 3.915 IN1 CM58 F8 OUT4B+ 0.639 B2 A + 4.709 M5 CSB 1.162 IN1 J8 OUT5A– 0.392 C1 A – 4.724 G8 DCOA– 1.157 IN2 J7 OUT5A+ 0.436 C2 A + 4.769 G7 DCOA+ 1.088 IN2 Rev D 32 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL APPLICATIONS Silkscreen Top Top Side Rev D 33 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL APPLICATIONS Inner Layer 2 Inner Layer 3 Rev D 34 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL APPLICATIONS Inner Layer 4 Inner Layer 5 Rev D 35 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL APPLICATIONS Bottom Side Silkscreen Bottom Rev D 36 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL APPLICATION TERM1EN23DISJP3 +OUT1A–OUT1A+OUT1B–OUT1B+OUT2A–OUT2A+OUT2B–OUT2B+OUT3A–OUT3A+OUT3B–OUT3B+OUT4A–OUT4A+OUT4B–OUT4B+OUT5A–OUT5A+OUT5B–OUT5B+OUT6A–OUT6A+OUT6B–OUT6B+OUT7A–OUT7A+OUT7B–OUT7B+FRA–FRA+FRB–FRB+DCOA–DCOA+DCOB–DCOB 9009101114 TA02 +1.8V R1LANE1k11 LANE+1.8V3.3 AUXCSB23R4R32 LANE10k1kJP3SDOAR531.6k1%3.3 AUX+1.8V R8R11TERM1k10k1ENSDOB23R13DIS31.6kJP61% 566MDEE8+OUT1ACSBSDOASDOBE7–OUT1AD8+OUT1BC8–OUT1BA8+OUT2AB8–OUT2AC7+OUT2BD7–OUT2BD9+OUT3AD10–OUT3AE9+OUT3BE10–OUT3BC10+OUT4AC9–OUT4AF8+OUT4BF7–OUT4BJ7+OUT5AJ8–OUT5AK7+OUT5BK8–OUT5BK10+OUT6AK9–OUT6AL10+OUT6BL9–OUT6BM8+OUT7AL8–OUT7AM9+OUT7BM10–OUT7BH8+FRAH7–FRAJ10+FRBJ9–FRBG7+DCOAG8–DCOAF9+DCOBF10–DCOB DDDDDDDDDDDDDDDDNNNNNNNNNNNNNNNNGGGGGGGGGGGGGGGG 9990909712347000NPPPPPA1B1H1N1P1ABHNP A DNG 6N 5L CS DNG 5N V R21k CSA V R71k SCK 6L SCK DDDNNNGGG 344MMN +1.8 LANE1 LANE 2 LANEJP2 +1.8 ILVDS11.7mA233.5mAMOSIJP5 6M SCI LTM9011-14 DDDDDDDDDDDDNNNNNNNNNNNNGGGGGGGGGGGG 456124565612HHHJJJJJKKLL LTM9011-14 Schematic +1.8V EXT REFR6PAR/SERE11kR9R101PAR100Ω1k2PAR/SER+1.8V3C1SER2.2µF, 0603JP4 756ACB PAR/SERSENSEVREF B2+AIN1B1–AIN1B3VCM14C2+AIN2C1–AIN2E2+AIN3E1–AIN3F3VCM23G2+AIN4G1–AIN4H2+AIN5H1–AIN5J3VCM67K1+AIN6K2–AIN6M1+AIN7M2–AIN7N1+AIN8N2–AIN8N3VCM58P5+ENCP6–ENCD3+1.8VD4+1.8VE3+1.8VE4+1.8VK3+1.8VK4+1.8VL3+1.8VL4+1.8VG9+1.8VOG10+1.8VO DDDDDDDDDDDDDDDDDDDDDDDDDDNNNNNNNNNNNNNNNNNNNNNNNNNNGGGGGGGGGGGGGGGGGGGGGGGGGG 12345645734612551245634563AAAAAABBBCCCDDDEFFFFFGGGGH FB1BLM31PG330SN1L+1.8V+C13R28100µFFB23k10VBLM31PG330SN1L+1.8VOC140.1µF +AIN1–AIN1VCM14+AIN2–AIN2+AIN3–AIN3VCM23+AIN4–AIN4+AIN5–AIN5VCM67+AIN6–AIN6+AIN7–AIN7+AIN8–AIN8VCM58+ENC–ENC+1.8V C111µF0603 R32C150Ω(OPT)0603 R38C18C19R370Ω(OPT)(OPT)100Ω0603 C23(OPT) (SAME FOR OTHER CHANNELS) L1R14OPT)(OPT) C2(OPT)R235.1ΩR20R24C7100ΩR22(OPT)4.7pF49.9Ω1% R21R18C549.9Ω(OPT)4.7pF1% R25R17(OPT)5.1Ω +1.8VO LT3080EDD17OUTIN28OUTIN3R29OUT95180kOUTVCTRL1%46NCSETC560.1µF ( R30R310Ω0Ω06030805+INR36R37C170Ω0Ω(OPT)06030805–IN R48100ΩVCM14 R27R26+1.8V(OPT)(OPT) C4T1R190.01µFMABA-J2100Ω007159-000000152C6C9C80.01µF0.01µF340.01µF(OPT) R16R15J1(OPT)(OPT) C30.01µF E3+V3V TO 6VC10C124.7µFE41µF6.3VGND06030603 +K +K CL CL Rev D 37 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM9011-14#packaging for the most recent package drawings. SEE NOTESG7ebPIN 1 ADETAIL A B C bD E F GFH J K L M NeP 10987654321SEE NOTESPACKAGE BOTTOM VIEW3 NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 BALL DESIGNATION PER JESD MS-028 AND JEP95 4DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu OR Sn Pb EUTECTIC 7PACKAGE ROW AND COLUMN LABELING MAY VARY !AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY LTMXXXXXXµModule OMPONENTPIN “A1” TRAY PIN 1BEVELPACKAGE IN TRAY LOADING ORIENTATIONBGA 140 1116 REV C C m) BGA Package140-Lead (11.25mm 9.00mm 2.72m××(Reference LTC DWG # 05-08-1849 Rev C) ZA A2 A1 ccc Z b1MOLDCAP SUBSTRATE H1H2 ZZ bbDETAIL Bb // Øb (140 PLACES) MXYZdddMZeee DETAIL BPACKAGE SIDE VIEW DETAIL A DIMENSIONS YMBOLNOMMAXNOTESMINA2.722.872.57BALL HTA10.400.450.35A22.322.422.22BALL DIMENSIONb0.500.550.45PAD DIMENSIONb10.400.430.37D11.25E9.0e0.80F10.40G7.2SUBSTRATE THK0.37H10.320.27MOLD CAP HT2.05H22.001.950.15aaa0.10bbb0.12ccc0.15ddd0.08eeeTOTAL NUMBER OF BALLS: 140 S aaa Z 0.000 Y D X 5.200 4.400 3.600 2.800 2.000 1.200 0.400 0.400 1.200 2.000 2.800 3.600 4.400 5.200 006.3 008.2 000.2 T U E PACKAGE TOP VIEW 000.0000000002442....1001 UGGESTED PCB LAYOTOP VIEW 000.2 S PIN “A1”CORNER 4 008.2 006.3 Z aaa 0.4 Ø 140x Rev D 38 For more information www.analog.com

LTM9011-14/ LTM9010-14/LTM9009-14 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 9/11 Updated Functional Block Diagram. 21 B 3/15 Removed mention of OGND. 26 C 2/17 Fixed V channel pairs: V changed to V , V changed to V , V changed to V , V 18, 20, 21, 32, CM CM12 CM14 CM34 CM23 CM56 CM67 CM78 changed to V . 37, 40 CM58 Corrected pin names for ENC and OUTXX. 20, 32, 37, 40 D 4/18 Corrected J3/N3 pin names. 20 Rev D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog 39 Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license Fiso gr rmanoterde biyn fimorpmlicaattiioonn owr wotwhe.arwniasleo ugn.cdoerm any patent or patent rights of Analog Devices.

LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL APPLICATION Single-Ended to Differential Conversion Using LTC6409 and 50MHz Lowpass Filter (Only One Channel Shown). Filter for Use at 92.16Msps 3.3V 0.8pF 1.8V 0.1µF 1.8V 150Ω 474Ω C5 B6 66.9Ω IN+ +V+ OUT– 37.4Ω 16880pnFH 1501p8F0nH 75Ω B2 AIN1+ SENSE VDD VREF OVDDOUT1A+ E8 0.1µF IN– –LTC6409 68pF 150pF 33pF 100pF B1 AIN1– OUT1A– E7 150Ω SHDN O4U74TΩ+VOCM 37.4Ω 180nH 180nH 75Ω B3 VCM14 D• • •CO+ G7 0.8pF C2 AIN2+ LTM9010-14 DCO– G8 49.9Ω 66.9Ω C1 AIN2– FR+ H8 GND F2 AIN3+ FR– H7 50Ω F1 AIN3– F3 VCM23 G2 AIN4+ G1 • AIN4– • • N1 AIN8+ N2 AIN8– +ENC –ENC P5 P6 9009101114 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC2170-14/LTC2171-14/ 14-Bit, 25Msps/40Msps/65Msps 178mW/234mW/360mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, LTC2172-14 1.8V Quad ADCs, Ultralow Power 7mm × 8mm QFN-52 LTC2170-12/LTC2171-12/ 12-Bit, 25Msps/40Msps/65Msps 178mW/234mW/360mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, LTC2172-12 1.8V Quad ADCs, Ultralow Power 7mm × 8mm QFN-52 LTC2173-12/LTC2174-12/ 12-Bit, 80Msps/105Msps/125Msps 412mW/481mW/567mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, LTC2175-12 1.8V Quad ADCs, Ultralow Power 7mm × 8mm QFN-52 LTC2173-14/LTC2174-14/ 14-Bit, 80Msps/105Msps/125Msps 412mW/481mW/567mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, LTC2175-14 1.8V Quad ADCs, Ultralow Power 7mm × 8mm QFN-52 Amplifiers/Filters LTC6412 800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Variable Gain Amplifier Figure, 4mm × 4mm QFN-24 LTC6420-20 1.8GHz Dual Low Noise, Low Distortion Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier, Differential ADC Drivers for 300MHz IF 3mm × 4mm QFN-20 LTC6421-20 1.3GHz Dual Low Noise, Low Distortion Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier, Differential ADC Drivers 3mm × 4mm QFN-20 LTC6605-7/LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz Filters Dual Matched 2nd Order Lowpass Filters with Differential Drivers, LTC6605-14 with ADC Drivers Pin-Programmable Gain, 6mm × 3mm DFN-22 Signal Chain Receivers LTM9002 14-Bit Dual Channel IF/Baseband Receiver Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers Subsystem Rev D 40 D16880-0-5/18(D) www.analog.com For more information www.analog.com  ANALOG DEVICES, INC. 2011-2018