LTM8062/LTM8062A 32V , 2A µModule Power IN Tracking Battery Chargers FeaTures DescripTion n Complete Battery Charger System The LTM®8062/LTM8062A are complete 32V , 2A IN n Input Supply Voltage Regulation Loop for Peak µModule® power tracking battery chargers. The LTM8062/ Power Tracking in MPPT (Maximum Peak Power LTM8062A provide a constant-current/constant-voltage Tracking) Solar Applications charge characteristic, a 2A maximum charge current, and n Resistor Programmable Float Voltage Up to 14.4V employ a 3.3V float voltage feedback reference, so any on the LTM8062 and 18.8V on the LTM8062A desired battery float voltage up to 14.4V for the LTM8062 n Wide Input Voltage Range: 4.95V to 32V and up to 18.8V for the LTM8062A can be programmed (40V Abs Max) with a resistor divider. n 2A Charge Current The LTM8062/LTM8062A employ an input voltage regula- n Accommodates Li-Ion/Polymer, LiFePO , SLA 4 tion loop, which reduces charge current if the input volt- n Integrated Input Reverse Voltage Protection age falls below a programmed level, set with a resistor n User Selectable Termination: C/10 or Termination divider. When the LTM8062/LTM8062A are powered by a Timer solar panel, this input regulation loop is used to maintain n 0.75% Float Voltage Reference Accuracy the panel at peak output power. The LTM8062/LTM8062A n 9mm × 15mm × 4.32mm LGA Package also feature preconditioning trickle charge, bad battery detection, a choice of termination schemes and automatic applicaTions restart. n Industrial Handheld Instruments The LTM8062/LTM8062A are packaged in a thermally en- n 12V to 24V Automotive and Heavy Equipment hanced, compact (9mm × 15mm × 4.32mm) over-molded n Desktop Cradle Chargers land grid array (LGA) package suitable for automated n Solar Power Battery Charging assembly by standard surface mount equipment. The LTM8062/LTM8062A are RoHS compliant. L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion 2A LiFePO µModule Battery Charger Charge Current vs Battery Voltage 4 2500 6V TO 3V2IVN VINA LTM8062 BAT NORMAL CHARGING 2000 VIN BIAS mA) VINREG CHRG 274k ENT (1500 RUN FAULT 1-CELL RR 4.7µF TMR ADJ L(3iF.6eVP)O4 NG CU1000 NTC GI 2.87M AR H GND C 500 PRECONDITION 8062 TA01a TERMINATION 0 0 1 2 3 4 BATTERY VOLTAGE (V) 8062 TA01b 8062fd 1 For more information www.linear.com/LTM8062

LTM8062/LTM8062A absoluTe MaxiMuM raTings pin conFiguraTion (Note 1) V , V ...................................................................40V TOP VIEW INA IN V , RUN, CHRG, FAULT ......................V + 0.5, 40V BIASADJ FAULTCHRGGND INREG IN 7 TMR, NTC ................................................................2.5V BAT BANK 2 NTCTMR RUNVINREG 6 BAT (LTM8062) .........................................................15V BAT (LTM8062A) ......................................................20V 5 VINA BANK 3 BIAS ..........................................................................10V 4 BANK 1 ADJ .............................................................................5V 3 Maximum Internal Operating Temperature GND BANK 4 2 (Note 2) .................................................................125°C VIN 1 Maximum Body Solder Temperature .....................245°C A B C D E F G H J K L LGA PACKAGE 77-LEAD (15mm × 9mm × 4.32mm) TJMAX = 125°C, θJA = 17.0°C/W, θJCbottom = 6.1°C/W, θJCtop = 16.2°C/W, θJB = 11.2°C/W, WEIGHT = 1.7g θ VALUES DETERMINED PER JEDEC 51-9, 51-12 orDer inForMaTion LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM8062EV#PBF LTM8062EV#PBF LTM8062V 77-Lead (15mm × 9mm × 4.32mm) LGA –40°C to 125°C LTM8062IV#PBF LTM8062IV#PBF LTM8062V 77-Lead (15mm × 9mm × 4.32mm) LGA –40°C to 125°C LTM8062AEV#PBF LTM8062AEV#PBF LTM8062AV 77-Lead (15mm × 9mm × 4.32mm) LGA –40°C to 125°C LTM8062AIV#PBF LTM8062AIV#PBF LTM8062AV 77-Lead (15mm × 9mm × 4.32mm) LGA –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ 8062fd 2 For more information www.linear.com/LTM8062

LTM8062/LTM8062A elecTrical characTerisTics The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at T = 25°C. RUN = 2V. A PARAMETER CONDITIONS MIN TYP MAX UNITS V Maximum Operating Voltage 32 V IN V Start Voltage V = 4.2V (Note 3) 7.5 V IN BAT V OVLO Threshold V Rising 32 35 40 V IN IN V OVLO Hysteresis 1 V IN V UVLO Threshold V Rising 4.6 4.95 V IN IN V UVLO Hysteresis 0.3 V IN V to V Diode Forward Voltage Drop V Current = 2A 0.55 V INA IN INA Maximum BAT Float Voltage LTM8062 14.7 V LTM8062A 19.3 V Input Supply Current Standby Mode 85 µA RUN = 0, V = 15V 18 µA INREG Maximum BAT Charging Current (Note 4) 1.8 2.1 A ADJ Float Reference Voltage 3.275 3.3 3.325 V l 3.25 3.34 V ADJ Recharge Threshold Voltage Threshold Relative to ADJ Float Reference 82.5 mV ADJ Precondition Threshold Voltage ADJ Rising 2.3 V ADJ Precondition Threshold Hysteresis Voltage Relative to ADJ Precondition Threshold 95 mV ADJ Input Bias Current Charging Terminated 65 nA CV Operation 110 nA V Reference Voltage ADJ = 3V, I = 1A l 2.61 2.7 2.83 V INREG BAT V Bias Current V = 2.7V 27 µA INREG INREG NTC Range Limit (High) Voltage V Rising 1.25 1.36 1.45 V NTC NTC Range Limit (Low) Voltage V Falling 0.27 0.29 0.315 V NTC NTC Disable Impedance 250 500 kΩ NTC Bias Current V = 0.8V 45 53 µA NTC NTC Threshold Hysteresis For Both High and Low Range Limits 20 % RUN Threshold Voltage V Rising 1.15 1.20 1.25 V RUN RUN Hysteresis Voltage 120 mV RUN Input Bias Current –10 nA CHRG, FAULT Output Low Voltage 10mA Load 0.4 V TMR Charge/Discharge Current 25 µA TMR Disable Threshold Voltage 0.25 V Operating Frequency 0.85 1 1.15 MHz Note 1: Stresses beyond those listed under Absolute Maximum Ratings the maximum internal temperature is determined by specific operating may cause permanent damage to the device. Exposure to any Absolute conditions in conjunction with board layout, the rated package thermal Maximum Rating condition for extended periods may affect device resistance and other environmental factors. reliability and lifetime. Note 3: This parameter is valid for programmed output battery float Note 2: The LTM8062E/LTM8062AE are guaranteed to meet performance voltages ≤ 4.2V. For other float voltages, V Start is 3.3V above the IN specifications from 0°C to 125°C internal. Specifications over the full programmed output battery float voltage. This parameter is guaranteed by –40°C to 125°C internal operating temperature range are assured by design, characterization, and correlation with statistical process controls. design, characterization and correlation with statistical process controls. Note 4: The maximum BAT charging current is reduced by thermal The LTM8062I/LTM8062AI are guaranteed to meet specifications over foldback. See the Typical Performance Characteristics for details. the full –40°C to 125°C internal operating temperature range. Note that 8062fd 3 For more information www.linear.com/LTM8062

LTM8062/LTM8062A Typical perForMance characTerisTics T = 25°C, unless otherwise noted. A Efficiency vs I , 4.2V Float Efficiency vs I , 7.2V Float Efficiency vs I , 8.4V Float BAT BAT BAT 84 87 88 82 86 VINA = 12V 87 VINA = 12V VINA = 24V 80 85 86 %) VINA = 24V %) %) CIENCY ( 7768 CIENCY ( 8834 VINA = 24V CIENCY ( 8845 VINA = 12V EFFI EFFI EFFI 74 82 83 72 81 82 70 80 81 0 500 1000 1500 2000 0 500 1000 1500 2000 0 500 1000 1500 2000 2500 IBAT (mA) IBAT (mA) IBAT (mA) 8062 G01 8062 G02 8062 G03 Efficiency vs I , 14.4V Float Efficiency vs I , 18.8V Float ADJ Float Voltage vs Temperature BAT BAT 90 93 3.280 VINA = 24V 89 92 VINA = 24V Y (%) 8878 Y (%) 9901 LTAGE (V) 3.275 C C O N 86 N V CIE CIE 89 AT EFFI 85 EFFI 88 DJ FLO 3.270 84 A 83 87 82 86 3.265 0 500 1000 1500 2000 0 500 1000 1500 2000 –50 –25 0 25 50 75 100 125 IBAT (mA) IBAT (mA) TEMPERATURE (°C) 8062 G04 8062 G23 8062 G05 I vs I , 4.2V Float I vs I , 7.2V Float I vs I , 8.4V Float BIAS BAT BIAS BAT BIAS BAT 25 45 50 40 45 20 40 35 VINA = 12V 30 VINA = 12V 35 VINA = 12V mA) 15 mA) 25 mA) 30 I (BIAS 10 I (BIAS 20 I (BIAS 2205 15 VINA = 24V VINA = 24V 15 5 10 10 VINA = 24V 5 5 0 0 0 0 500 1000 1500 2000 0 500 1000 1500 2000 0 500 1000 1500 2000 IBAT (mA) IBAT (mA) IBAT (mA) 8062 G06 8062 G07 8062 G08 8062fd 4 For more information www.linear.com/LTM8062

LTM8062/LTM8062A Typical perForMance characTerisTics T = 25°C, unless otherwise noted. A I vs I , 14.4V Float I vs I , 18.8V Float Input Current vs I , 4.2V Float BIAS BAT BIAS BAT BAT 45 50 900 VINA = 24V 40 45 800 40 35 700 VINA = 24V 35 A) VINA = 12V 30 m 600 mA) 25 mA) 30 ENT ( 500 I (BIAS 20 I (BIAS 2205 T CURR 400 15 15 INPU 300 VINA = 24V 10 10 200 5 5 100 0 0 0 0 500 1000 1500 2000 0 500 1000 1500 2000 0 500 1000 1500 2000 IBAT (mA) IBAT (mA) IBAT (mA) 8062 G09 8062 G24 8062 G10 Input Current vs I , 7.2V Float Input Current vs I , 8.4V Float Input Current vs I , 14.4V Float BAT BAT BAT 1400 1600 1400 1200 1400 1200 VINA = 12V VINA = 12V 1200 A)1000 A) A)1000 m m m NT ( 800 NT (1000 NT ( 800 RRE RRE 800 RRE VINA = 24V CU 600 CU CU 600 NPUT 400 NPUT 600 VINA = 24V NPUT 400 I VINA = 24V I 400 I 200 200 200 0 0 0 0 500 1000 1500 2000 0 500 1000 1500 2000 2500 0 500 1000 1500 2000 IBAT (mA) IBAT (mA) IBAT (mA) 8062 G11 8062 G12 8062 G13 Input Current vs IBAT, 18.8V Float IQ vs VINA, RUN = 0V, VINREG Open Maximum IBAT vs ADJ 1600 250 2500 VINA = 24V 1400 200 2000 mA)1200 A) UT CURRENT (1806000000 I (µA)Q 110500 XIMUM I (mBAT11050000 P A N M I 400 50 500 200 0 0 0 0 500 1000 1500 2000 0 10 20 30 40 0 0.5 1 1.5 2 2.5 3 3.5 IBAT (mA) VINA (V) ADJ VOLTAGE (V) 8062 G25 8062 G14 8062 G15 8062fd 5 For more information www.linear.com/LTM8062

LTM8062/LTM8062A Typical perForMance characTerisTics T = 25°C, unless otherwise noted. A Maximum Charge Current Temperature Rise vs I , BAT Maximum I vs V vs Temperature 4.2V Float Voltage BAT INREG 2500 2000 25 2000 1600 20 (mA)BAT1500 RENT (mA)1200 E RISE (°C) 15 M I UR UR VINA = 24V MAXIMU1000 CHARGE C 800 TEMPERAT 10 VINA = 12V 500 400 5 0 0 0 2 2.5 3 3.5 –40 –20 0 20 40 60 80 100 120 0 500 1000 1500 2000 VINREG (V) TEMPERATURE (°C) IBAT (mA) 8062 G16 8062 G17 8062 G18 Temperature Rise vs IBAT, Temperature Rise vs IBAT, Temperature Rise vs IBAT, 7.2V Float Voltage 8.4V Float Voltage 14.4V Float Voltage 30 30 40 35 25 25 SE (°C) 20 SE (°C) 20 VINA = 12V SE (°C) 2350 E RI VINA = 24V E RI E RI VINA = 24V R 15 R 15 R 20 U U U RAT VINA = 12V RAT VINA = 24V RAT 15 PE 10 PE 10 PE M M M E E E 10 T T T 5 5 5 0 0 0 0 500 1000 1500 2000 0 500 1000 1500 2000 0 500 1000 1500 2000 IBAT (mA) IBAT (mA) IBAT (mA) 8062 G19 8062 G20 8062 G21 Temperature Rise vs I , V Standby Mode Current BAT IN 18.8V Float Voltage vs Temperature Minimum V vs V 1.7A Load IN BAT 45 6 25 VINA = 24V 40 mA) 5 20 SE (°C) 3305 RRENT ( 4 RATURE RI 2205 Y MODE CU 3 VINA = 12VVINA = 24V V (V)IN 1105 MPE 15 NDB 2 E A T 10 ST 5 N 1 5 VI 0 0 0 0 500 1000 1500 2000 –50 0 50 100 0 5 10 15 20 IBAT (mA) TEMPERATURE (°C) VBAT (V) 8062 G26 8062 G22 8062 G27 8062fd 6 For more information www.linear.com/LTM8062

LTM8062/LTM8062A pin FuncTions GND (Bank 1, Pin L7): Power and Signal Ground Return. of the temperature thresholds. The temperature monitoring function remains enabled while thermistor resistance to BAT (Bank 2): Battery Charge Current Output Bus. The ground is less than 250kΩ. If this function is not desired, charge function operates to achieve the final float voltage leave the NTC pin unconnected. at this pin. The auto-restart feature initiates a new charging cycle when the voltage at the ADJ pin falls 2.5% below ADJ (Pin H7): Battery Float Voltage Feedback Input. The the float voltage. Once the charge cycle is terminated, the charge function operates to achieve a final float voltage of input bias current of the BAT pin is reduced to minimize 3.3V on this pin. The output battery float voltage (V ) BAT(FLT) battery discharge while the charger remains connected. is programmed using a resistor divider. V can be BAT(FLT) programmed up to 14.4V. The auto-restart feature initi- V (Bank 3): Anode of input reverse protection Schottky INA ates a new charging cycle when the voltage at the ADJ diode. Connect the input power here if input reverse volt- pin falls 2.5% below the float voltage reference. The ADJ age protection is desired. pin input bias current is 110nA. Using a resistor divider VIN (Bank 4): Charger Input Supply. Decouple with at least with an equivalent input resistance at the ADJ pin of 250k 4.7µF to GND. Connect the input power here if no input compensates for input bias current error. Required resistor reverse voltage protection is needed. values to program desired V follow the equations: BAT(FLT) BIAS (Pin G7): The BIAS pin connects to the internal 5 V •2.5•10 power bus. In most cases connect to V . If this is not BAT(FLT) BAT R1= (Ω) desirable, connect to a power source greater than 2.8V 3.3 and less than 10V. 5 R1•2.5•10 R2= (Ω) CHRG (Pin K7): Open-Collector Charger Status Output; 5 R1−(2.5•10 ) typically pulled up through a resistor to a reference voltage. This status pin can be pulled up to voltages as R1 is connected from BAT to ADJ, and R2 is connected high as V and can sink currents up to 10mA. During IN from ADJ to ground. a battery charging cycle, CHRG is pulled low. When the FAULT (Pin J7): Open-Collector Fault Status Output; typi- charge current falls below C/10, the CHRG pin becomes cally pulled up through a resistor to a reference voltage. high impedance. If the internal timer is used for termina- This status pin can be pulled up to voltages as high as tion, the pin stays low during the charging cycle until the V and can sink currents up to 10mA. This pin indicates charge current drops below a C/10 rate, approximately IN charge cycle fault conditions during a battery charging 200mA, even though the charger will continue to top off cycle. A temperature fault causes this pin to be pulled the battery until the end-of-charge timer terminates the low. If the internal timer is used for termination, a bad bat- charge cycle. A temperature fault also causes this pin to tery fault also causes this pin to be pulled low. If no fault be pulled low (see the Applications Information section). conditions exist, the FAULT pin remains high impedance NTC (Pin H6): Battery Temperature Monitor Pin. This pin (see the Applications Information section). is the input to the NTC (negative temperature coefficient) TMR (Pin J6): End-Of-Cycle Timer Programming Pin. thermistor temperature monitoring circuit. This function is If a timer-based charge termination is desired, connect enabled by connecting a 10kΩ, B = 3380 NTC thermistor a capacitor from this pin to ground. Full charge end-of from the NTC pin to ground. The pin sources 50μA, and cycle time (in hours) is programmed with this capacitor monitors the voltage across the 10kΩ thermistor. When the following the equation: voltage on this pin is above 1.36V (T < 0°C) or below 0.29V (T > 40°C), charging is disabled and the CHRG and FAULT t = C • 4.4 • 106 EOC TIMER pins are both pulled low. If the internal timer termination is A bad battery fault is generated if the battery does not being used, the timer is paused, suspending the charging reach the precondition threshold voltage within one-eighth cycle. Charging resumes when the voltage on NTC returns of t , or: to within the 0.29V to 1.36V active region. There is approxi- EOC mately 5°C of temperature hysteresis associated with each t = C • 5.5 • 105 PRE TIMER 8062fd 7 For more information www.linear.com/LTM8062

LTM8062/LTM8062A pin FuncTions A 0.68μF capacitor is often used, which generates a timer the maximum charge current required to maintain the EOC at three hours, and a precondition limit time of 22.5 programmed operational V voltage, through maintain- IN minutes. If a timer-based termination is not desired, the ing the voltage on V at or above 2.7V. If the voltage INREG timer function can be disabled by connecting the TMR regulation feature is not used, connect the pin to V . IN pin to ground. With the timer function disabled, charging RUN (Pin K6): Precision Threshold Enable Input Pin. The terminates when the charge current drops below a C/10 RUN threshold is 1.25V (rising), with 120mV of input hys- rate, approximately 200mA. teresis. When in shutdown mode, all charging functions are V (Pin L6): Input Voltage Regulation Reference. The disabled. The precision threshold allows use of the RUN INREG maximum charge current is reduced when this pin is below pin to incorporate UVLO functions. If the RUN pin is pulled 2.7V. There is a 100k resistor to GND. Connecting a resis- below 0.4V, the IC enters a low current shutdown mode tor from V to this pin sets the minimum operational V where the V pin current is reduced to 15μA. Typical RUN IN IN IN voltage. This is typically used to program the peak power pin input bias current is 10nA. If the shutdown function is voltage for a solar panel. The LTM8062/LTM8062A servo not desired, connect the pin to the V pin. IN block DiagraM VINA VIN SENSE 8.2µH RESISTOR BAT 0.1µF 0.1µF 10µF (LTM8062) 2.2µF (LTM8062A) BIAS VINREG 100k INTERNAL COMPENSATION RUN CURRENT ADJ MODE BATTERY ADJ MANAGEMENT CONTROLLER TMR NTC GND FAULT CHRG 8062 BD 8062fd 8 For more information www.linear.com/LTM8062

LTM8062/LTM8062A operaTion The LTM8062/LTM8062A are complete monolithic, mid- also contain an internal charge cycle control timer, for power, power tracking battery chargers, addressing timer-based termination. When using the internal timer, high input voltage applications with solutions that use a the charge cycle can continue beyond the C/10 level to minimum of external components. The products can be top-off the battery. The charge cycle terminates when programmed for float voltages between 3.3V and 14.4V the programmed time elapses, about three hours for a (LTM8062) or between 3.3V and 18.8V (LTM8062A) with 0.68µF timer capacitor. The CHRG status pin continues just two external resistors, operating under a 1MHz fixed to signal charging at a C/10 or greater rate, regardless of frequency, average current mode step-down architecture. A which termination scheme is used. When the timer-based 2A power Schottky diode is integrated within the μModule scheme is used, the LTM8062/LTM8062A also support bad charger for reverse input voltage protection. A wide input battery detection, which triggers a system fault if a battery range allows the operation to full charge from an input stays in precondition mode for more than one-eighth of voltage up to 32V. A precision threshold on the RUN pin the total programmed charge cycle time. allows the implementation of a UVLO feature by using a Once charging terminates and the LTM8062/LTM8062A are simple resistor network. The charger can also be put into not actively charging, the charger automatically enters a a low current shutdown mode, in which the input supply low current standby mode in which supply bias currents bias is reduced to only 15μA. are reduced to 85μA. If the battery voltage drops 2.5% The LTM8062/LTM8062A employ an input voltage regula- from the full charge float voltage, the LTM8062/LTM8062A tion loop, which reduces charge current if a monitored engage an automatic charge cycle restart. The IC also au- input voltage falls below a programmed level at the V tomatically restarts a new charge cycle after a bad-battery INREG pin. There is a 1% 100k resistor to GND at this pin. When fault once the failed battery is removed and replaced with the LTM8062/LTM8062A are powered by a solar panel, another battery. The LTM8062/LTM8062A contain a bat- the input regulation loop is used to maintain the panel at tery temperature monitoring circuit. This feature, using a peak output power. The LTM8062/LTM8062A automatically thermistor, monitors battery temperature and will not allow enter a battery precondition mode if the sensed battery charging to begin, or will suspend charging, and signal voltage is very low. In this mode, the charge current is a fault condition if the battery temperature is outside a reduced to 300mA. Once the battery voltage climbs above safe charging range. The LTM8062/LTM8062A contain the internally set precondition threshold (2.3V at the ADJ two digital open-collector outputs, CHRG and FAULT, pin), the μModule charger automatically increases the which provide charger status and signal fault conditions. maximum charge current to the full programmed value. These binary coded pins signal battery charging, standby or shutdown modes, battery temperature faults and bad The LTM8062/LTM8062A can use a charge current based battery faults. For reference, C/10 and TMR based charg- C/10 termination scheme, which ends a charge cycle ing cycles are shown in Figures 1 and 2. when the battery charge current falls to one-tenth the programmed charge current. The LTM8062/LTM8062A 8062fd 9 For more information www.linear.com/LTM8062

LTM8062/LTM8062A operaTion FLOAT VOLTAGE RECHARGE THRESHOLD BATTERY VOLTAGE PRECONDITION THRESHOLD MAXIMUM CHARGE CURRENT BATTERY CHARGE CURRENT PRECONDITION CURRENT C/10 0 AMPS 1 CHRG 0 FAULT 1 0 1 RUN 0 8062 F01 Figure 1. Typical C/10 Terminated Charge Cycle (TMR Grounded, Time Not to Scale) FLOAT VOLTAGE RECHARGE THRESHOLD BATTERY VOLTAGE PRECONDITION THRESHOLD MAXIMUM CHARGE CURRENT BATTERY CHARGE CURRENT PRECONDITION CURRENT C/10 CURRENT 1 CHRG 0 FAULT 1 0 1 RUN 0 < tEOC/8 tEOC AUTOMATIC RESTART 8062 F02 Figure 2. Typical EOC (Timer-Based) Terminated Charge Cycle (Capacitor Connected to TMR, Time Not to Scale) 8062fd 10 For more information www.linear.com/LTM8062

LTM8062/LTM8062A applicaTions inForMaTion For most applications, the design process is straight V Input Supply IN forward, summarized as follows: The LTM8062/LTM8062A are biased directly from the 1. Look at Table 1 and find the row that has the desired charger input supply through the V pin. This pin pro- IN input voltage range and battery float voltage. vides large switched currents, so a high quality low ESR decoupling capacitor is recommended to minimize volt- 2. Apply the recommended C and R values. IN ADJ age glitches on V . 4.7μF is typically adequate for most IN 3. Connect BIAS as indicated. charger applications. While these component combinations have been tested Reverse Protection Diode for proper operation, it is incumbent upon the user to verify proper operation over the intended system’s line, The LTM8062/LTM8062A integrate a high voltage power load and environmental conditions. Bear in mind that the Schottky diode to provide input reverse voltage protec- maximum output current is limited by junction tempera- tion. The anode of this diode is connected to V , and INA ture, the relationship between the input and output voltage the cathode is connected to V . There is a small amount IN magnitude and polarity and other factors. Please refer to of capacitance at each end; please see the Block Diagram. the graphs in the Typical Performance Characteristics The integrated diode can also be used to block battery section for guidance. discharge leakage paths. The LTM8062/LTM8062A switch Table 1. Recommended Component Values and Configuration and drive circuitry are designed to stand off some reverse (T = 25°C) voltage from BAT to V , but leakage paths exist that can A IN R R put a small load on the battery if V falls below BAT. ADJ1 ADJ2 IN TOP BOTTOM Specifically, the RUN pin has a small bias current and V RANGE (V)* V (V) C (kΩ) (kΩ) IN BAT IN there is a 100k resistor tied to V to GND. If either INREG 6 to 32 3.6 4.7µF 1206 X7R 50V 274 2870 of these pins is connected to V when it is below BAT, IN 6 to 32 4.1 4.7µF 1206 X7R 50V 312 1260 it can present a small but finite discharge current to the 6 to 32 4.2 4.7µF 1206 X7R 50V 320 1150 battery. This discharge current may be blocked by the 6.25 to 32 4.7 4.7µF 1206 X7R 50V 357 835 integrated Schottky diode if the RUN and V circuits INREG 9.5 to 32 7.05 4.7µF 1206 X7R 50V 530 464 are tied to V . INA 9.75 to 32 7.2 4.7µF 1206 X7R 50V 549 459 11 to 32 8.2 4.7µF 1206 X7R 50V 626 417 Input Supply Voltage Regulation 11.5 to 32 8.4 4.7µF 1206 X7R 50V 642 412 The LTM8062/LTM8062A contain a voltage monitor pin 12.75 to 32 9.4 4.7µF 1206 X7R 50V 715 383 that enables programming a minimum operational volt- 16.5 to 32 12.3 4.7µF 1206 X7R 50V 942 344 age. There is a 1% 100k resistor from V to GND. INREG 17 to 32 12.6 4.7µF 1206 X7R 50V 965 340 Connecting a resistor from V to the V pin enables IN INREG 18.25 to 32 13.5 4.7µF 1206 X7R 50V 1020 328 programming of minimum input supply voltage, typically 19 to 32 14.08 4.7µF 1206 X7R 50V 1090 332 used to program the peak power voltage for a solar panel. 19.5 to 32 14.42 4.7µF 1206 X7R 50V 1110 328 Maximum charge current is reduced when the V pin INREG 23 to 32 16.4 4.7µF 1206 X7R 50V 1240 312 is below the regulation threshold of 2.7V. 23.5 to 32 16.8 4.7µF 1206 X7R 50V 1270 309 If the V function is not used, and if the input supply 26 to 32 18.8 4.7µF 1206 X7R 50V 1420 301 INREG cannot provide enough power to satisfy the requirements *Operating range, V must be 3.3V above V to start. Input bulk IN BAT capacitance is required. of an LTM8062/LTM8062A charger, the input supply voltage 8062fd 11 For more information www.linear.com/LTM8062

LTM8062/LTM8062A applicaTions inForMaTion will collapse. A minimum operating supply voltage can physically located far from the battery and the added line thus be programmed by monitoring the supply through impedance may interfere with the control loop. Case 2: a resistor divider, such that the desired minimum voltage the battery ESR is very small or very large; the LTM8062/ corresponds to 2.7V at the V pin. The LTM8062/ LTM8062A controller is designed for a wide range, but some INREG LTM8062A servo the maximum output charge current to battery packs have an ESR outside of this range. Case 3: maintain the voltage on V at or above 2.7V. there is no battery at all. As the charger is designed to INREG work with the ESR of the battery, the output may oscillate Programming of the desired minimum voltage is accom- if no battery is present. plished by connecting a resistor as shown in Figure 3. The optimum ESR is about 100mΩ, but ESR values both 100V –270 R = IN k higher and lower will work. Table 2 shows a sample of IN 2.7 parts successfully tested by Linear Technology: If the voltage regulation feature is not used, connect the Table 2 VINREG pin to VIN. PART NUMBER DESCRIPTION MANUFACTURER 16TQC22M 22µF, 16V, POSCAP Sanyo 35SVPD18M 18µF, 35V, OS-CON Sanyo LTM8062 INPUT SUPPLY VIN TPSD226M025R0100 22µF, 25V Tantalum AVX RIN T495D226K025AS 22µF, 25V, Tantalum Kemet VINREG TPSC686M006R0150 68µF, 6V, Tantalum AVX 8062 F03 TPSB476M006R0250 47µF, 6V, Tantalum AVX Figure 3. Resistive Divider Sets Minimum V APXE100ARA680ME61G 68µF, 10V Aluminum Nippon Chemicon IN APS-150ELL680MHB5S 68µF, 25V Aluminum Nippon Chemicon BIAS Pin Considerations If system constraints preclude the use of electrolytic ca- The BIAS pin is used to provide drive power for the in- pacitors, a series R-C network may be used. Use a ceramic ternal power switching stage and operate other internal capacitor of at least 22µF and an equivalent resistance of circuitry. For proper operation, it must be powered by at 100mΩ. An example of this is shown in the Typical Ap- least 2.8V and no more than the absolute maximum rat- plications section. ing of 10V. In most applications, connect BIAS to BAT. If there is no BIAS supply available or the battery voltage is MPPT Temperature Compensation below 2.8V, the internal switch requires more headroom A typical solar panel is comprised of a number of series- from V for proper operation. Please refer to the Typical IN connected cells, each cell being a forward-biased p-n junc- Performance Characteristics curves for minimum start and tion. As such, the open-circuit voltage (V ) of a solar cell OC running requirements under various battery conditions. has a temperature coefficient that is similar to a common When charging a 2-cell battery using a relatively high p-n diode, or about –2mV/°C. The peak power point voltage input voltage, the LTM8062/LTM8062A power dissipation (V ) for a crystalline solar panel can be approximated as MP can be reduced by connecting BIAS to a voltage between a fixed voltage below V , so the temperature coefficient OC 2.8V and 3.3V. for the peak power point is similar to that of V . OC Output Capacitance Panel manufacturers typically specify the 25°C values for V , V , and the temperature coefficient for V , making In many applications, the internal BAT capacitance of the OC MP OC determination of the temperature coefficient for V of a LTM8062/LTM8062A is sufficient for proper operation. MP typical panel straight forward. The LTM8062/LTM8062A There are cases, however, where it may be necessary to employs a feedback network to program the V input add capacitance or otherwise modify the output imped- IN regulation voltage. Manipulation of the network makes for ance of the LTM8062/LTM8062A. Case 1: the µModule is 8062fd 12 For more information www.linear.com/LTM8062

LTM8062/LTM8062A applicaTions inForMaTion efficient implementation of various temperature compensa- As the temperature coefficient for V is similar to that MP tion schemes for a maximum peak power tracking (MPPT) of V , the specified temperature coefficient for V OC OC application. As the temperature characteristic for a typical (TC) of –78mV/°C and the specified peak power voltage solar panel V voltage is highly linear, a simple solution (V (25°C)) of 17.6V can be inserted into the equations to MP MP for tracking that characteristic can be implemented using a calculate the appropriate resistor values for the temperature Linear Technology LM234 3-terminal temperature sensor. compensation network in Figure 4. Initially, determine the This creates an easily programmable, linear temperature R value using the following equation: SET dependent characteristic. In the circuit shown in Figure 4,  1 0.0677 R =100 + – SET  –78mV/°C•4405 2.7  100V (25°C)   MP –100  V  17.6  R = INREG kΩ kΩ⇒4.12kΩ IN  100000•0.0677  –78mV/°C•4405•2.7 1–  V •R   INREG SET  Then, R can be determined using the calculated R IN SET  1 0.0677 value: R =100 + – SET  TC•4405 V  INREG  100•17.6V  –100   2.7 V (25°C)  R = kΩ⇒1400kΩ MP kΩ IN  1–100000•0.0677 TC•4405•V INREG  2.7•4120  where TC = temperature coefficient (in V/°C), and Battery Voltage Temperature Compensation V (25°C) = maximum power voltage at 25°C. MP Some battery chemistries have charge voltage require- VIN ments that vary with temperature. Lead-acid batteries in LINEAR particular experience a significant change in charge volt- TECHNOLOGY V+ LM234 age requirements as temperature changes. For example, RIN V– R RSET VIN manufacturers of large lead-acid batteries recommend a float charge of 2.25V/cell at 25°C. This battery float VINREG voltage, however, has a temperature coefficient which is LTM8062 typically specified at –3.3mV/°C per cell. 8062 F04 In a manner similar to the MPPT temperature correction Figure 4. MPPT Temperature Compensation Network outlined previously, implementation of linear battery charge voltage temperature compensation can be accomplished by For example, given a common 36-cell solar panel that has incorporating a Linear Technology LM234 into the output the following specified characteristics: feedback network. For example, a 6-cell lead acid battery Open Circuit Voltage (VOC) = 21.7V has a float charge voltage that is commonly specified at Maximum Power Voltage (V ) = 17.6V 2.25V/cell at 25°C, or 13.5V, and a –3.3mV/°C per cell tem- MP perature coefficient, or –19.8mV/°C. Using the feedback Open-Circuit Voltage Temperature Coefficient (V ) OC = –78mV/°C 8062fd 13 For more information www.linear.com/LTM8062

LTM8062/LTM8062A applicaTions inForMaTion network shown in Figure 5, with the desired temperature While the circuit in Figure 5 creates a linear tempera- coefficient (TC) and 25°C float voltage (V (25°C)) ture characteristic that follows a typical –3.3mV/°C per FLOAT specified, and using a convenient value of 2.4k for R , cell lead-acid specification, the theoretical float charge SET necessary resistor values follow the relations: voltage characteristic is slightly nonlinear. This nonlinear characteristic follows the relation: R = –R • (TC • 4405) FB1 SET = –2.4k • (–0.0198 • 4405) ⇒ 210kΩ VFLOAT = 4 • 10–5 (T2) – 6 • 10–3(T) + 2.375 (with a 2.18V minimum) R R = FB1 FB2 V (25°C)+R •(0.0674/R ) where T = temperature in °C. A thermistor-based network FLOAT FB1 SET -1 can be used to approximate the nonlinear ideal tempera- V FB ture characteristic across a reasonable operating range, 210k as shown in Figure 6. = 13.5+210k•(0.0674/2.4k) -1 3.3 BAT ⇒43kΩ + 196k 6-CELL LEAD-ACID R = 250k – R ||R LTM8062 BATTERY FB3 FB1 FB2 = 250k – 210k||43k ⇒ 215kΩ 198k 69k 22k B = 3380 (see the Battery Float Voltage Programming section) ADJ 69k 8062 F06a BAT + V+ LINEAR 14.8 LTM8062 R21FB01k R TECHNOLOGY 6-CELL 14.6 RFB3 R2S.4EkT V– LM234 LBEAATTDE-ARYCID 14.4 215k ADJ 14.2 RFB2 V) 14.0 43k 8062 F05a (OAT13.8 THEORETICAL VFLOAT VFL13.6 14.3 13.4 14.2 13.2 PROGRAMMED VBAT(FLOAT) 13.0 14.0 13.8 –19.8mV/°C 12.8–10 0 10 20 30 40 50 60 (V)AT13.6 TEMPERATURE (°C) 8062 F06b O VFL13.4 13.2 Figure 6. Thermistor-Based Temperature Compensation Network Programs V to Closely Match Ideal Lead-Acid Float Charge 13.0 FLOAT Voltage for 6-Cell Charger 12.8 12.6 Status Pins –10 0 10 20 30 40 50 60 TEMPERATURE (°C) The LTM8062/LTM8062A report charger status through 8062 F05b two open-collector outputs, the CHRG and FAULT pins. Figure 5. Lead-Acid 6-Cell Float Charge Voltage vs Temperature These pins can be pulled up as high as V , and can sink with a –19.8mV/°C Temperature Coefficient Using LM234 with IN the Feedback Network up to 10mA. The CHRG pin indicates that the charger is delivering current at greater than a C/10 rate, or one-tenth 8062fd 14 For more information www.linear.com/LTM8062

LTM8062/LTM8062A applicaTions inForMaTion of the programmed charge current. The FAULT pin signals TMR pin to ground. The timer cycle time span (t ) is EOC bad-battery and NTC faults. These pins are binary coded, determined by C in the equation: TIMER as shown in Table 3. C = t • 2.27 • 10–7 (Hours) TIMER EOC Table 3. Status Pin State When charging at a 1C rate, t is commonly set to three EOC CHRG FAULT STATUS hours, which requires a 0.68μF capacitor. High High Not Charging—Standby or Shutdown Mode The CHRG status pin continues to signal charging, regard- High Low Bad-Battery Fault (Precondition Timeout/EOC Failure) less of which termination scheme is used. When timer Low High Normal Charging at C/10 or Greater termination is used, the CHRG status pin is pulled low Low Low NTC Fault (Pause) during a charge cycle until the charge current falls below If the battery is removed from an LTM8062/LTM8062A the C/10 threshold. The charger continues to top off the charger that is configured for C/10 termination, a low battery until timer EOC, when the LTM8062/LTM8062A amplitude sawtooth waveform appears at the charger terminate the charge cycle and enters standby mode. output, due to cycling between termination and recharge Termination at the end of the timer cycle only occurs if the events. This cycling results in pulsing at the CHRG output. charge cycle was successful. A successful charge cycle An LED connected to this pin will exhibit a blinking pat- occurs when the battery is charged to within 2.5% of the tern, indicating to the user that a battery is not present. full-charge float voltage. If a charge cycle is not success- The frequency of this blinking pattern is dependent on the ful at EOC, the timer cycle resets and charging continues output capacitance. for another full timer cycle. When V drops 2.5% from BAT C/10 Charge Termination the full-charge float voltage, whether by battery loading or replacement of the battery, the charger automatically The LTM8062/LTM8062A support a low current-based resets and starts charging. termination scheme, where a battery charge cycle termi- nates when the charge current falls below one-tenth the Preconditioning and Bad-Battery Fault programmed charge current, or approximately 200mA. The LTM8062/LTM8062A have a precondition mode, where This termination mode is engaged by shorting the TMR pin the charge current is limited to 15% of the maximum to ground. When C/10 termination is used, an LTM8062/ charge current, or approximately 300mA. Precondition LTM8062A charger sources battery charge current as mode is engaged if the voltage on the BAT pin is below the long as the average current level remains above the C/10 precondition threshold, or approximately 70% of the float threshold. As the full-charge float voltage is achieved, the voltage. Once the BAT voltage rises above the precondition charge current falls until the C/10 threshold is reached, threshold, normal full-current charging can commence. The at which time the charger terminates and the LTM8062/ LTM8062/LTM8062A incorporate 90mV hysteresis to avoid LTM8062A enter standby mode. The CHRG status pin fol- spurious mode transitions. lows the charger cycle and is high impedance when the charger is not actively charging. There is no provision for Bad-battery detection is engaged when the internal timer bad-battery detection if C/10 termination is used. is used for termination (capacitor tied to TMR). This fault detection feature is designed to identify failed cells. A Timer Charge Termination bad-battery fault is triggered when the voltage on BAT The LTM8062/LTM8062A support a timer-based termina- remains below the precondition threshold for greater tion scheme, where a battery charge cycle terminates after than one-eighth of a full timer cycle (one-eighth EOC). A a specific amount of time elapses. Timer termination is bad-battery fault is also triggered if a normally charging engaged when a capacitor (C ) is connected from the battery re-enters precondition mode after one-eighth EOC. TIMER 8062fd 15 For more information www.linear.com/LTM8062

LTM8062/LTM8062A applicaTions inForMaTion When a bad-battery fault is triggered, the charge cycle Thermal Foldback is suspended, and the CHRG status pin becomes high The LTM8062/LTM8062A contains a thermal fold- impedance. The FAULT pin is pulled low to signal that a back protection feature that reduces charge current fault has been detected. as the IC junction temperature approaches 125°C. In Cycling the charger’s power or shutdown function initiates most cases, on-chip temperatures servo such that a new charge cycle, but the LTM8062/LTM8062A chargers any overtemperature conditions are relieved with do not require a manual reset. Once a bad-battery fault only slight reductions in maximum charge current. In is detected, a new timer charge cycle initiates if the BAT some cases, the thermal foldback protection feature pin exceeds the precondition threshold voltage. During can reduce charge currents below the C/10 threshold. a bad-battery fault, a small current is sourced from the In applications that use C/10 termination (TMR = 0V), charger; removing the failed battery allows the charger the LTM8062/LTM8062A will suspend charging and en- output voltage to rise above the preconditioning threshold ter standby mode until the overtemperature condition is voltage and initiate a charge cycle reset. A new charge relieved. cycle is started by connecting another battery to the charger output. PCB Layout Most of the headaches associated with PCB layout have Battery Temperature Fault: NTC been alleviated or even eliminated by the high level of The LTM8062/LTM8062A can accommodate battery tem- LTM8062/LTM8062A integration. The LTM8062/LTM8062A perature monitoring by using an NTC (negative tempera- is nevertheless a switching power supply, and care must be ture coefficient) thermistor close to the battery pack. The taken to minimize EMI and ensure proper operation. Even temperature monitoring function is enabled by connecting with the high level of integration, you may fail to achieve a 10kΩ, β ≈ 3380 NTC thermistor from the NTC pin to specified operation with a haphazard or poor layout. See ground. If the NTC function is not desired, leave the pin Figure 7 for a suggested layout. Ensure that the grounding open. The NTC pin sources 50μA, and monitors the voltage and heat sinking are acceptable. dropped across the 10kΩ thermistor. When the voltage on this pin is above 1.36V (0°C) or below 0.29V (40°C), ADJ tLhTeM b8a0tt6e2rAy ttermigpgeerra atnu rNe TisC o fuatu oltf. rTahneg eN, TanCd f athuelt LcToMn8d0it6io2n/ BAT NTCFAULTTMRCHRG GND remains until the voltage on the NTC pin corresponds to (OPTIONAL) a temperature within the 0°C to 40°C range. Both hot and RUNVINREG cold thresholds incorporate 20% hysteresis, which equates CBAT to about 5°C. If higher operational charging temperatures are desired, the temperature range can be expanded by adding series resistance to the 10k NTC resistor. Adding VINA a 909Ω resistor will increase the effective temperature threshold to 45°C, for example. During an NTC fault, charging is halted and both status GND CIN pins are pulled low. If timer termination is enabled, the VIN timer count is suspended and held until the fault condi- THERMAL VIAS 8062 F07 tion is cleared. Figure 7. Suggested Layout and Via Placement 8062fd 16 For more information www.linear.com/LTM8062

LTM8062/LTM8062A applicaTions inForMaTion 1. Place the C capacitor as close as possible to the V installing a small resistor in series with V , but the most IN IN IN and GND connection of the LTM8062/LTM8062A. popular method of controlling input voltage overshoot is to add an electrolytic bulk capacitor to the V net. This 2. If used, place the C capacitor as close as possible to IN BAT capacitor’s relatively high equivalent series resistance the BAT and GND connection of the LTM8062/LTM8062A. damps the circuit and eliminates the voltage overshoot. 3. Place the CIN and CBAT (if used) capacitors such that their The extra capacitor improves low frequency ripple filter- ground current flows directly adjacent or underneath ing and can slightly improve the efficiency of the circuit, the LTM8062/LTM8062A. though it is physically large. 4. Connect all of the GND connections to as large a copper Parallel Operation pour or plane area as possible on the top layer. Avoid breaking the ground connection between the external If more current is desired, multiple LTM8062/LTM8062As components and the LTM8062/LTM8062A. may be paralleled, as shown in the Typical Applications section. When doing so, bear in mind the following: 5. For good heat sinking, use vias to connect the GND copper area to the board’s internal ground planes. 1. Each LTM8062/LTM8062A ADJ pin requires 250k input Liberally distribute these GND vias to provide both a resistance as described in the ADJ pin function descrip- good ground connection and thermal path to the internal tion. Table 1 gives the recommended resistor network planes of the printed circuit board. Pay attention to the for a single LTM8062/LTM8062A. If using more than location and density of the thermal vias in Figure 5. The one, either apply one network of the appropriate value LTM8062/LTM8062A can benefit from the heat-sinking to each LTM8062/LTM8062A’s ADJ pin or apply a single afforded by vias that connect to internal GND planes at network, each resistor value divided by the number of these locations, due to their proximity to internal power paralleled LTM8062/LTM8062As and connect all of the handling components. The optimum number of thermal ADJ pins together. vias depends upon the printed circuit board design. 2. Tie the BAT outputs directly together. Apply the same For example, a board might use very small via holes. output capacitance to each LTM8062/LTM8062A as if It should employ more thermal vias than a board that it were used as a single device and not paralleled. uses larger holes. 3. The individual LTM8062/LTM8062As may not share Hot-Plugging Safely current equally as the battery nears the float voltage. The small size, robustness and low impedance of ceramic Thermal Considerations capacitors make them an attractive option for the input bypass capacitor of LTM8062/LTM8062A. However, these The thermal performance of the LTM8062/LTM8062A is capacitors can cause problems if the LTM8062/LTM8062A given in the Typical Performance Characteristics section. are plugged into a live input supply (see Application Note These curves were generated by the LTM8062/LTM8062A mounted to a 58cm2 4-layer FR4 printed circuit board. 88 for a complete discussion). The low loss ceramic Boards of other sizes and layer count can exhibit differ- capacitor combined with stray inductance in series with ent thermal behavior, so it is incumbent upon the user to the power source forms an underdamped tank circuit, verify proper operation over the intended system’s line, and the voltage at the V pin of the LTM8062/LTM8062A IN load and environmental operating conditions. can ring to more than twice the nominal input voltage, possibly exceeding the LTM8062/LTM8062A’s rating and For increased accuracy and fidelity to the actual application, damage the part. If the input supply is poorly controlled many designers use FEA to predict thermal performance. or the user will be plugging the LTM8062/LTM8062A into To that end, the Pin Configuration section of the data sheet an energized supply, the input network should be designed typically gives four thermal coefficients: to prevent this overshoot. This can be accomplished by 8062fd 17 For more information www.linear.com/LTM8062

LTM8062/LTM8062A applicaTions inForMaTion 1. θ : Thermal resistance from junction to ambient. 3. θ is determined with nearly all of the component JA JCtop power dissipation flowing through the top of the pack- 2. θ : Thermal resistance from junction to the bot- JCbottom age. As the electrical connections of the typical µModule tom of the product case. device are on the bottom of the package, it is rare for an 3. θJCtop: Thermal resistance from junction to top of the application to operate such that most of the heat flows product case. from the junction to the top of the part. As in the case of θ , this value may be useful for comparing 4. θ : Thermal resistance from junction to the printed JCbottom JB packages but the test conditions don’t generally match circuit board. the user’s application. While the meaning of each of these coefficients may seem 4. θ is the junction-to-board thermal resistance where to be intuitive, JEDEC has defined each to avoid confusion JB almost all of the heat flows through the bottom of the and inconsistency. These definitions are given in JESD µModule device and into the board, and is really the 51-12, and are quoted or paraphrased below: sum of the θ and the thermal resistance of the JCbottom 1. θJA is the natural convection junction-to-ambient air bottom of the part through the solder joints and through thermal resistance measured in a one cubic foot sealed a portion of the board. The board temperature is mea- enclosure. This environment is sometimes referred to as sured a specified distance from the package, using a “still air” although natural convection causes the air to two sided, two layer board. This board is described in move. This value is determined with the part mounted to JESD 51-9. a JESD 51-9 defined test board, which does not reflect The most appropriate way to use the coefficients is when an actual application or viable operating condition. running a detailed thermal analysis, such as FEA, which 2. θJCbottom is the junction-to-board thermal resistance considers all of the thermal resistances simultaneously. with all of the component power dissipation flowing None of them can be individually used to accurately pre- through the bottom of the package. In the typical dict the thermal performance of the product, so it would µModule device, the bulk of the heat flows out the bot- be inappropriate to attempt to use any one coefficient to tom of the package, but there is always heat flow out correlate to the junction temperature versus load graphs into the ambient environment. As a result, this thermal given in the Typical Performance Characteristics. resistance value may be useful for comparing packages A graphical representation of these thermal resistances but the test conditions don’t generally match the user’s is given in Figure 8. application. JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD) JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT RESISTANCE RESISTANCE JUNCTION-TO-BOARD RESISTANCE JUNCTION AMBIENT JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT (BOTTOM) RESISTANCE RESISTANCE RESISTANCE 80421 F08 µMODULE DEVICE Figure 8. Thermal Resistances Among µModule Device Printed Circuit Board and Ambient Environment 8062fd 18 For more information www.linear.com/LTM8062

LTM8062/LTM8062A applicaTions inForMaTion The blue resistances are contained within the µModule flow out of the LTM8062/LTM8062A is through the bottom device, and the green are outside. of the module and the LGA pads into the printed circuit board. Consequently a poor printed circuit board design The die temperature of the LTM8062/LTM8062A must be can cause excessive heating, resulting in impaired perfor- lower than the maximum rating of 125°C, so care should mance or reliability. Please refer to the PCB Layout section be taken in the layout of the circuit to ensure good heat for printed circuit board design suggestions. sinking of the LTM8062/LTM8062A. The bulk of the heat Typical applicaTions Basic 2A, 2-Cell LiFePO Battery Charger with C/10 Termination 4 9.5V TO 32VVDINC VINA LTM8062 BAT VIN BIAS + (OPTIONAL ELECTROLYTIC VINREG CHRG 549k 2L-iFCeEPLOL4 CAPACITOR) RUN FAULT (2× 3.6V) 4.7µF BATTERY TMR ADJ NTC 459k GND 8062 TA02 Basic 2A, 4-Cell Li-Ion Battery Charger with C/10 Termination 22V TO 32VVDINC VINA LTM8062A BAT VIN 4-CELL 4.7µF + (OPTIONAL Li-Ion VINREG CHRG 1.24M ELECTROLYTIC (4 × 4.1V) RUN FAULT CAPACITOR) BATTERY PACK TMR ADJ NTC BIAS 312k GND 8062 TA06 EXTERNAL 3.3V 8062fd 19 For more information www.linear.com/LTM8062

LTM8062/LTM8062A Typical applicaTions 2A Solar Panel Power Manager with 8.4V Lithium Ion Battery Pack and 16V Peak Power Tracking VIN LTM8062 SOLAR VINA BAT POWER UNIT VIN BIAS 499k VINREG CHRG 642k 2-CELL RUN FAULT + Li-ION 4.7µF (OPTIONAL (2× 4.2V) NTC TMR ADJ ELECTROLYTIC BATTERY 10k CAPACITOR) B = 3380 NTC 412k GND 8062 TA03 Three LTM8062s Operating In Parallel to Produce Higher Charge Current BAT 7.2V, 6A + C2 22µF GND 12V TO 32V VINA VINA VINA VIN BAT VIN BAT VIN BAT LTM8062EV R1 + C1 LTM8062EV R2 + C3 LTM8062EV R3 549k 549k 549k GND VINREG BIAS 0.1% 22µF VINREG BIAS 0.1% 22µF VINREG BIAS 0.1% RUN ADJ RUN ADJ RUN ADJ R4 R5 R6 NTC CHRG 459k NTC CHRG 459k NTC CHRG 459k 0.1% 0.1% 0.1% FAULT FAULT FAULT TMR GND TMR GND TMR GND C6 C4 C5 8062 TA05 10µF 10µF 10µF 35V 35V 35V C4, C5, C6; MURATA, GRM32ER7YA106KA12L C1, C2, C3; POS-CAP 16TQC22M 8062fd 20 For more information www.linear.com/LTM8062

LTM8062/LTM8062A package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. PAD 1DIA (0.635) RIENTATION LGA 77 0909 REV A A B C D E F G H J K L G O N 1 DI A O 2 VIEW RAY L 345 7.62BSC KAGE BOTTOM LTMXXXXXXModuleµ PACKAGE IN T C A DETAIL A 67 P 12.70BSC 1.27BSC PADSSEE NOTES 3 COMPONENTPIN “A1” TRAY PIN 1BEVEL LGA Package77-Lead (15mm 9mm 4.32mm)××(Reference LTC DWG # 05-08-1856 Rev A) 4.22 – 4.42 MOLDSUBSTRATECAP 0.27 – 0.373.95 – 4.05 ZZ bbb // DETAIL B DETAIL B 0.635 ±0.025 SQ. 76x SYXeee DETAIL A NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 LAND DESIGNATION PER JESD MO-222, SPP-010 4DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 77 SYMBOLTOLERANCE aaa0.15 bbb0.10 eee0.05 aaa Z Y 15BSC X 018.3 045.2 UT W O P VIE 55275895..01 072.1 B LAYW 9BSC KAGE TO 007020..10 STED PCTOP VIE C E A G P G 045.2 U S 5294.3 018.3 5721.4 aaa Z PAD 1CORNER 4 6.350 5.080 3.810 2.540 1.270 0.000 0.95251.2701.5875 2.540 3.810 5.080 6.350 8062fd 21 For more information www.linear.com/LTM8062

LTM8062/LTM8062A package DescripTion Table 3. Pin Assignment Table (Arranged by Pin Number) PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME A1 GND B1 GND C1 GND D1 GND E1 GND F1 GND A2 GND B2 GND C2 GND D2 GND E2 GND F2 GND A3 GND B3 GND C3 GND D3 GND E3 GND F3 GND A4 GND B4 GND C4 GND D4 GND E4 GND F4 GND A5 GND B5 GND C5 GND D5 GND E5 GND F5 GND A6 BAT B6 BAT C6 BAT D6 BAT E6 BAT F6 BAT A7 BAT B7 BAT C7 BAT D7 BAT E7 BAT F7 BAT PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME G1 GND H1 GND J1 GND K1 V L1 V IN IN G2 GND H2 GND J2 GND K2 V L2 V IN IN G3 GND H3 GND J3 GND K3 V L3 V IN IN G4 GND H4 GND J4 GND K4 V L4 V INA INA G5 GND H5 GND J5 GND K5 V L5 V INA INA G6 GND H6 NTC J6 TMR K6 RUN L6 V INREG G7 BIAS H7 ADJ J7 FAULT K7 CHRG L7 GND package phoTos 8062fd 22 For more information www.linear.com/LTM8062

LTM8062/LTM8062A revision hisTory REV DATE DESCRIPTION PAGE NUMBER A 3/11 Updated Electrical Characteristics section 3 Updated V (Pin L6) description 7 INREG Updated Block Diagram 8 Updated Operation section 8 Updated Figures 2, 7 9, 15 Updated Applications Information 10, 11, 12, 13 Updated/Added Typical Applications 18, 22 B 8/11 Added LTM8062A parts. Reflected throughout the data sheet 1-24 C 12/11 Added graph G27 6 Updated Typical Applications 19 D 7/13 Correct R and R equations 13 W SET 8062fd 23 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconneFcotiro nm oof rites cinirfcouritms aast idoens cwribwewd .hleinreeianr w.cioll mno/tL iTnfMrin8g0e6 o2n existing patent rights.

LTM8062/LTM8062A Typical applicaTion 2A Solar Panel Power Manager for Charging 2-Cell 8.4V Lithium-Ion Battery, Featuring Three Hour Charge Time and 16V Peak Power Tracking. Battery Powers Two µModule Regulators VIN LTM8062 SOLAR VINA BAT LTM8023 VOUT POWER UNIT VIN BIAS VINREG CHRG 499k 642k 2-CELL RUN FAULT Li-Ion 4.7µF (2× 4.2V) NTC TMR ADJ BATTERY 10k LTM8021 VOUT B = 3380 0.68µF NTC 412k GND 8062 TA04 relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTM4601/ 12A DC/DC µModule Regulator with PLL, Output Synchronizable, PolyPhase Operation, LTM4601-1 Version has no Remote LTM4601A Tracking/Margining and Remote Sensing Sensing LTM4618 6A DC/DC µModule Regulator 4.5V ≤ VIN ≤ 26.5V, 0.8V ≤ VOUT ≤ 5V, 9mm × 15mm × 4.32mm LGA LTM4604A 4A Low VIN DC/DC µModule Regulator 2.375V ≤ VIN ≤ 5.5V, 0.8V ≤ VOUT ≤ 5V, 9mm × 15mm × 2.3mm LGA LTM4608A 8A Low VIN DC/DC µModule Regulator 2.7V ≤ VIN ≤ 5.5V, 0.6V ≤ VOUT ≤ 5V, 9mm × 15mm × 2.8mm LGA LTM8020 200mA, 36V DC/DC µModule Regulator EN55022 Class B Compliant, Fixed 450kHz Frequency, 1.25V ≤ V ≤ 5V, OUT 6.25mm × 6.25mm × 2.32mm LGA LTM8022 1A, 36V DC/DC µModule Regulator Adjustable Frequency, 0.8V ≤ VOUT ≤ 10V, 9mm × 11.25mm × 2.82mm LGA, Pin Compatible to the LTM8023 LTM8023 2A, 36V DC/DC µModule Regulator Adjustable Frequency, 0.8V ≤ VOUT ≤ 10V, 9mm × 11.25mm × 2.82mm LGA, Pin Compatible to the LTM8022 LTM8025 3A, 36V DC/DC µModule Regulator 0.8V ≤ VOUT ≤ 24V, 9mm × 15mm × 4.32mm LGA LTM8021 500mA, 36V DC/DC µModule Regulator EN55022 Class B Compliant, Fixed 1.1MHz Frequency, 0.8V ≤ V ≤ 5V, OUT 6.25mm × 11.25mm × 2.82mm LGA LTM8042/ 1A/350mA µModule LED Driver 3V ≤ V ≤ 30V, V Up to 28V, Buck, Boost or Buck-Boost Operation IN LED LTM8042-1 9mm × 15mm × 2.82mm LGA 8062fd 24 Linear Technology Corporation LT 0713 REV D • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTM8062 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTM8062  LINEAR TECHNOLOGY CORPORATION 2010