LTC6995-1/LTC6995-2 TimerBlox: Long Timer, Low Frequency Oscillator FeaTures DescripTion n Period Range: 1ms to 9.5 Hours The LTC®6995 is a silicon oscillator with a programmable n Timing Reset by Power-On or Reset Input period range of 1.024ms to 9.54 hours (29.1µHz to 977Hz), n Configured with 1 to 3 Resistors specifically intended for long duration timing events. The n <1.5% Maximum Frequency Error LTC6995 is part of the TimerBlox® family of versatile n Programmable Output Polarity silicon timing devices. n 2.25V to 5.5V Single Supply Operation A single resistor, R , programs the LTC6995’s internal SET n 55µA to 80µA Supply Current master oscillator frequency. The output clock period (2ms to 9.5hr Clock Period) is determined by this master oscillator and an internal n 500µs Start-Up Time frequency divider, N , programmable to eight settings DIV n CMOS Output Driver Sources/Sinks 20mA from 1 to 221. n –55°C to 125°C Operating Temperature Range n Available in Low Profile (1mm) SOT-23 (ThinSOT™) t =NDIV •RSET •1.024ms, N =1,8,64,...,221 OUT DIV and 2mm × 3mm DFN Packages 50kΩ When oscillating, the LTC6995 generates a 50% duty applicaTions cycle square wave output. A reset function is provided to stop the master oscillator and clear internal dividers. n Power-On Reset Timer Removing reset initiates a full output clock cycle which is n Long Time One Shot useful for programmable power-on reset and watchdog n “Heartbeat” Timers timer applications. n Watchdog Timers n Periodic “Wake-Up” Call The LTC6995 has two versions of reset functionality. The n High Vibration, High Acceleration Environments reset input is active high for the LTC6995-1 and active low L, LT, LTC, LTM, Linear Technology, TimerBlox and the Linear logo are registered trademarks for the LTC6995-2. The polarity of the output when reset and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the is selectable for both versions. property of their respective owners. OUTPUT (OSCILLATOR START STATE) RST/RST POLARITY LTC6995-1 LTC6995-2 0 0 Oscillating (Low) 0 (Reset) 1 0 0 (Reset) Oscillating (Low) 0 1 Oscillating (High) 1 (Reset) 1 1 1 (Reset) Oscillating (High) Typical applicaTion Active Low Power-On Reset Timer RST OUT V+ LTC6995-1 GND V+ V+ 5 SECONDS 1M 0.1µF OUT 1/2 tOUT TIMER STOPPED SET DIV POWER-ON RESET 118k 392k (1ms TO 4.8 HOURS) 699512 TA01 699512fa 1 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 absoluTe MaxiMuM raTings (Note 1) Supply Voltage (V+) to GND ........................................6V Specified Temperature Range (Note 3) Maximum Voltage LTC6995C ................................................0°C to 70°C on Any Pin ................(GND – 0.3V) ≤ V ≤ (V+ + 0.3V) LTC6995I .............................................–40°C to 85°C PIN Operating Temperature Range (Note 2) LTC6995H ..........................................–40°C to 125°C LTC6995C ............................................–40°C to 85°C LTC6995MP .......................................–55°C to 125°C LTC6995I .............................................–40°C to 85°C Junction Temperature ...........................................150°C LTC6995H ..........................................–40°C to 125°C Storage Temperature Range ..................–65°C to 150°C LTC6995MP .......................................–55°C to 125°C Lead Temperature (Soldering, 10 sec) S6 Package ...........................................................300°C pin conFiguraTion LTC6995-1/LTC6995-2 LTC6995-1/LTC6995-2 TOP VIEW TOP VIEW V+ 1 6 OUT 7 RST/RST 1 6 OUT DIV 2 5 GND GND GND 2 5 V+ SET 3 4 RST/RST SET 3 4 DIV DCB PACKAGE S6 PACKAGE 6-LEAD (2mm × 3mm) PLASTIC DFN 6-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 64°C/W, θJC = 9.6°C/W TJMAX = 150°C, θJA = 192°C/W, θJC = 51°C/W EXPOSED PAD (PIN 7) CONNECTED TO GND, PCB CONNECTION OPTIONAL orDer inForMaTion Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6995CDCB-1#TRMPBF LTC6995CDCB-1#TRPBF LGJM 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C LTC6995IDCB-1#TRMPBF LTC6995IDCB-1#TRPBF LGJM 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C LTC6995HDCB-1#TRMPBF LTC6995HDCB-1#TRPBF LGJM 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C LTC6995CDCB-2#TRMPBF LTC6995CDCB-2#TRPBF LGJP 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C LTC6995IDCB-2#TRMPBF LTC6995IDCB-2#TRPBF LGJP 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C LTC6995HDCB-2#TRMPBF LTC6995HDCB-2#TRPBF LGJP 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C LTC6995CS6-1#TRMPBF LTC6995CS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 0°C to 70°C LTC6995IS6-1#TRMPBF LTC6995IS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 –40°C to 85°C LTC6995HS6-1#TRMPBF LTC6995HS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 –40°C to 125°C LTC6995MPS6-1#TRMPBF LTC6995MPS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 –55°C to 125°C LTC6995CS6-2#TRMPBF LTC6995CS6-2#TRPBF LTGJQ 6-Lead Plastic TSOT-23 0°C to 70°C LTC6995IS6-2#TRMPBF LTC6995IS6-2#TRPBF LTGJQ 6-Lead Plastic TSOT-23 –40°C to 85°C LTC6995HS6-2#TRMPBF LTC6995HS6-2#TRPBF LTGJQ 6-Lead Plastic TSOT-23 –40°C to 125°C LTC6995MPS6-2#TRMPBF LTC6995MPS6-2#TRPBF LTGJQ 6-Lead Plastic TSOT-23 –55°C to 125°C TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 699512fa 2 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V for LTC6995-1, A RST = V+ for LTC6995-2, DIVCODE = 0 to 15 (N = 1 to 221), R = 50k to 800k, R = 5k, C = 5pF unless otherwise noted. DIV SET LOAD LOAD SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t Output Clock Period 1.024m 34,360 Seconds OUT f Output Frequency 29.1µ 977 Hz OUT ∆f Frequency Accuracy (Note 4) 29.1µHz ≤ f ≤ 977Hz ±0.8 ±1.5 % OUT OUT l ±2.2 % ∆f /∆T Frequency Drift Over Temperature l ±0.005 %/°C OUT ∆f /∆V+ Frequency Drift Over Supply V+ = 4.5V to 5.5V l 0.23 0.55 %/V OUT V+ = 2.25V to 4.5V l 0.06 0.16 %/V Long-Term Frequency Stability (Note 11) 90 ppm/√kHr Period Jitter (Note 10) N = 1 15 ppm DIV RMS N = 8 7 ppm DIV RMS BW Frequency Modulation Bandwidth 0.4 • f Hz OUT t Frequency Change Settling Time (Note 9) 1 Cycle S Analog Inputs V Voltage at SET Pin l 0.97 1.00 1.03 V SET ∆V /∆T V Drift Over Temperature l ±75 µV/°C SET SET R Frequency-Setting Resistor l 50 800 kΩ SET V DIV Pin Voltage l 0 V+ V DIV ∆V /∆V+ DIV Pin Valid Code Range (Note 5) Deviation from Ideal l ±1.5 % DIV V /V+ = (DIVCODE + 0.5)/16 DIV DIV Pin Input Current l ±10 nA Power Supply V+ Operating Supply Voltage Range l 2.25 5.5 V Power-On Reset Voltage l 1.95 V I Supply Current R = ∞, R = 50k V+ = 5.5V l 135 170 µA S L SET V+ = 2.25V l 105 135 µA R = ∞, R = 100k V+ = 5.5V l 100 130 µA L SET V+ = 2.25V l 80 105 µA R = ∞, R = 800k V+ = 5.5V l 65 100 µA L SET V+ = 2.25V l 55 85 µA R = ∞, I = 0µA V+ = 5.5V 60 µA L SET V+ = 2.25V 52 µA 699512fa 3 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V for LTC6995-1, A RST = V+ for LTC6995-2, DIVCODE = 0 to 15 (N = 1 to 221), R = 50k to 800k, R = ∞, C = 5pF unless otherwise noted. DIV SET LOAD LOAD SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital I/O RST Pin Input Capacitance 2.5 pF RST Pin Input Current RST = 0V to V+ ±10 nA V High Level RST Pin Input Voltage (Note 6) l 0.7 • V+ V IH V Low Level RST Pin Input Voltage (Note 6) l 0.3 • V+ V IL I Output Current V+ = 2.7V to 5.5V ±20 mA OUT(MAX) V High Level Output Voltage (Note 7) V+ = 5.5V I = –1mA l 5.45 5.48 V OH OUT I = –16mA l 4.84 5.15 V OUT V+ = 3.3V I = –1mA l 3.24 3.27 V OUT I = –10mA l 2.75 2.99 V OUT V+ = 2.25V I = –1mA l 2.17 2.21 V OUT I = –8mA l 1.58 1.88 V OUT V Low Level Output Voltage (Note 7) V+ = 5.5V I = 1mA l 0.02 0.04 V OL OUT I = 16mA l 0.26 0.54 V OUT V+ = 3.3V I = 1mA l 0.03 0.05 V OUT I = 10mA l 0.22 0.46 V OUT V+ = 2.25V I = 1mA l 0.03 0.07 V OUT I = 8mA l 0.26 0.54 V OUT t Reset Propagation Delay V+ = 5.5V 16 ns RST V+ = 3.3V 24 ns V+ = 2.25V 40 ns t Minimum Input Pulse Width V+ = 3.3V 5 ns WIDTH t Output Rise Time (Note 8) V+ = 5.5V 1.1 ns r V+ = 3.3V 1.7 ns V+ = 2.25V 2.7 ns t Output Fall Time (Note 8) V+ = 5.5V 1.0 ns f V+ = 3.3V 1.6 ns V+ = 2.25V 2.4 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: To conform to the Logic IC Standard, current out of a pin is may cause permanent damage to the device. Exposure to any Absolute arbitrarily given a negative value. Maximum Rating condition for extended periods may affect device Note 8: Output rise and fall times are measured between the 10% and the reliability and lifetime. 90% power supply levels with 5pF output load. These specifications are Note 2: The LTC6995C is guaranteed functional over the operating based on characterization. temperature range of –40°C to 85°C. Note 9: Settling time is the amount of time required for the output to settle Note 3: The LTC6995C is guaranteed to meet specified performance from within ±1% of the final frequency after a 0.5× or 2× change in ISET . 0°C to 70°C. The LTC6995C is designed, characterized and expected to Note 10: Jitter is the ratio of the deviation of the period to the mean of the meet specified performance from –40°C to 85°C but it is not tested or period. This specification is based on characterization and is not 100% QA sampled at these temperatures. The LTC6995I is guaranteed to meet tested. specified performance from –40°C to 85°C. The LTC6995H is guaranteed Note 11: Long-term drift of silicon oscillators is primarily due to the to meet specified performance from –40°C to 125°C. The LTC6995MP is movement of ions and impurities within the silicon and is tested at 30°C guaranteed to meet specified performance from –55°C to 125°C. under otherwise nominal operating conditions. Long-term drift is specified Note 4: Frequency accuracy is defined as the deviation from the fOUT as ppm/√kHr due to the typically nonlinear nature of the drift. To calculate equation, assuming RSET is used to program the frequency. drift for a set time period, translate that time into thousands of hours, take Note 5: See Operation section, Table 1 and Figure 2 for a full explanation the square root and multiply by the typical drift number. For instance, a of how the DIV pin voltage selects the value of DIVCODE. year is 8.77kHr and would yield a drift of 266ppm at 90ppm/√kHr. Drift without power applied to the device may be approximated as 1/10th of the Note 6: The RST pin has hysteresis to accommodate slow rising or falling signals. The threshold voltages are proportional to V+. Typical values can drift with power, or 9ppm/√kHr for a 90ppm/√kHr device. be estimated at any supply voltage using V ≈ 0.55 • V+ + 185mV RST(RISING) and V ≈ 0.48 • V+ – 155mV. RST(FALLING) 699512fa 4 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 Typical perForMance characTerisTics V+ = 3.3V, R = 200k, T = 25°C unless otherwise noted. SET A Frequency Error vs Temperature Frequency Error vs Temperature Frequency Error vs Temperature 3 3 3 GUARANTEED MAX OVER TEMPERATURE GUARANTEED MAX OVER TEMPERATURE GUARANTEED MAX OVER TEMPERATURE 2 2 2 RSET = 50k RSET = 200k RSET = 800k 3 PARTS 3 PARTS 3 PARTS 1 1 1 %) %) %) OR ( 0 OR ( 0 OR ( 0 R R R R R R E E E –1 –1 –1 –2 GUARANTEED MIN OVER TEMPERATURE –2 GUARANTEED MIN OVER TEMPERATURE –2 GUARANTEED MIN OVER TEMPERATURE –3 –3 –3 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 699512 G01 699512 G02 699512 G03 Frequency Error vs R Frequency Drift vs Supply Voltage Typical V Distribution SET SET 3 0.5 250 2 LOTS GUARANTEED MAX OVER TEMPERATURE 0.4 DFN AND SOT-23 2 1274 UNITS 3 PARTS 0.3 200 1 0.2 TS %) %) 0.1 UNI 150 ERROR ( 0 DRIFT (–0.10 MBER OF 100 –1 U –0.2 N REFERENCED TO V+ = 4.5V –2 GUARANTEED MIN OVER TEMPERATURE –0.3 RSET = 50k 50 –0.4 RSET = 200k RSET = 800k –3 –0.5 0 0 200 400 600 800 2 3 4 5 6 0.98 0.988 0.996 1.004 1.012 1.02 RSET (kΩ) SUPPLY VOLTAGE (V) VSET (V) 699512 G04 699512 G05 699512 G06 V Drift vs I V Drift vs Supply V vs Temperature SET SET SET SET 1.0 1.0 1.020 3 PARTS 0.8 0.8 1.015 0.6 0.6 1.010 0.4 0.4 mV) 0.2 mV) 0.2 V) 1.005 V (SET–0.02 DRIFT (–0.02 V (SET10..090905 –0.4 –0.4 0.990 –0.6 –0.6 –0.8 –0.8 0.985 REFERENCED TO ISET = 10µA REFERENCED TO V+ = 4V –1.0 –1.0 0.980 0 5 10 15 20 2 3 4 5 6 –50 –25 0 25 50 75 100 125 ISET (µA) SUPPLY (V) TEMPERATURE (°C) 699512 G07 699512 G08 699512 G09 699512fa 5 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 Typical perForMance characTerisTics V+ = 3.3V, R = 200k, T = 25°C unless otherwise noted. SET A Supply Current Supply Current vs Supply Voltage Supply Current vs Temperature vs RST Pin Voltage 150 150 250 RSET = 800k RSET = 50k PLY CURRENT (µA)11702505 RSET = 100kRSET = 200k PLY CURRENT (µA)11270550 255.5VVV,, ,RR RSSSEEETTT == = 18 1000000kkk PLY CURRENT (µA) 210500 RST FRASLTL3 IF.NA3GVLLIN5GV 5RVST R3RI.SS3ITVN RGISING R SUP 50 RSET = 800k R SUP 50 2.5V, RSET = 800k R SUP 100 E E E W W W O O O 50 P 25 P 25 P 0 0 0 2 3 4 5 6 –50 –25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1.0 SUPPLY VOLTAGE (V) TEMPERATURE (°C) VRST/V+ (V/V) 699512 G10 699512 G11 699512 G12 RST Threshold Voltage Supply Current vs R Typical I Current Limit vs V+ vs Supply Voltage SET SET 150 1000 3.5 SET PIN SHORTED TO GND NT (µA)125 V+ = 5V 800 V) 32..05 POSITIVE-GOING RE100 E ( R SUPPLY CUR 5705 VV++ == 23..53VV I (µA)SET460000 ST PIN VOLTAG 21..05 NEGATIVE-GOING E R 1.0 W O 200 P 25 0.5 0 0 0 0 200 400 600 800 2 3 4 5 6 2 3 4 5 6 RSET (kΩ) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 699512 G14 699512 G15 699512 G13 Reset Propagation Delay (t ) Rise and Fall Time Typical Frequency Error RST vs Supply Voltage vs Supply Voltage vs Time (Long-Term Drift) 50 3.0 200 CLOAD = 5pF CLOAD = 5pF 65 UNITS 45 150 SOT-23 AND DFN PARTS 40 2.5 TA = 30°C ns) m) 100 ATION DELAY ( 32230055 FALL TIME (ns) 12..50 tFAtRLILSE REQUENCY (pp 500 PROPAG 1150 RISE/ 1.0 DELTA F–1–0500 0.5 5 –150 0 0 –200 2 3 4 5 6 2 3 4 5 6 0 400 800 1200 1600 2000 2400 2800 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TIME (h) 699512 G17 699512 G18 699512 G16 699512fa 6 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 Typical perForMance characTerisTics V+ = 3.3V, R = 200k, T = 25°C unless otherwise noted. SET A Output Resistance Typical LTC6995-1 Start-Up with vs Supply Current POL = 1 50 45 V+ 40 Ω) 5V/DIV E ( 35 RST C OUTPUT SOURCING CURRENT AN 30 5V/DIV RESET RELEASED, T ESIS 25 5V/ODUIVT OUTPUT RESET 100Hz OUTPUT CLOCK T R 20 4ms START-UP PU V+ = 5V 5ms/DIV 699512 G20 T 15 OUTPUT SINKING CURRENT U DIVCODE = 15 O 10 RSET = 499k 5 0 2 3 4 5 6 SUPPLY VOLTAGE (V) 699512 G19 pin FuncTions (DCB/S6) V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This sup- 50ppm/°C or better temperature coefficient. For lower ac- ply should be kept free from noise and ripple. It should be curacy applications an inexpensive 1% thick film resistor bypassed directly to the GND pin with a 0.1µF capacitor. may be used. DIV (Pin 2/Pin 4): Programmable Divider and Polarity Limit the capacitance on the SET pin to less than 10pF Input. An internal A/D converter (referenced to V+) moni- to minimize jitter and ensure stability. Capacitance less tors the DIV pin voltage (V ) to determine a 4-bit result than 100pF maintains the stability of the feedback circuit DIV (DIVCODE). V may be generated by a resistor divider regulating the V voltage. DIV SET between V+ and GND. Use 1% resistors to ensure an ac- curate result. The DIV pin and resistors should be shielded RST OUT from the OUT pin or any other traces that have fast edges. LTC6995-1/ V+ Limit the capacitance on the DIV pin to less than 100pF LTC6995-2 GND V+ so that VDIV settles quickly. The MSB of DIVCODE (POL) C1 0.1µF R1 determines the polarity of the OUT pin. SET DIV SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage RSET 699512 PF R2 on the SET pin (V ) is regulated to 1V above GND. The SET amount of current sourced from the SET pin (I ) pro- SET grams the master oscillator frequency. The I current RST or RST (Pin 4/Pin 1): Output Reset. The reset input SET range is 1.25µA to 20µA. The output oscillation will stop is used to stop the output oscillator and to clear internal if I drops below approximately 500nA. A resistor con- dividers. When reset is released the oscillator starts with SET nected between SET and GND is the most accurate way to a full half period time interval. The output logic state when set the frequency. For best performance, use a precision reset is determined by the programmed DIVCODE. The metal or thin film resistor of 0.5% or better tolerance and LTC6995-1 has an active high RST input. The LTC6995-2 has an active low RST input. 699512fa 7 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 pin FuncTions (DCB/S6) GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground 30Ω. When driving an LED or other low impedance load plane for best performance. a series output resistor should be used to limit source/ sink current to 20mA. OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings from GND to V+ with an output resistance of approximately block DiagraM (S6 package pin numbers shown) 5 V+ R1 POL BIT DIV 4-BIT A/D DIGITAL 4 CONVERTER FILTER R2 MASTER OSCILLATOR tMASTER = 510µksΩ (cid:127) VISSEETT MCLK DFIVIXIDEDER PROGDRIVAIMDEMRABLE POOULTAPRUITTY OUT 6 ÷ 1024 ÷1, 8, 64, 512 tOUT 4096, 215, 218, 221 HALT OSCILLATOR DIVIDER OUTPUT RESET IF ISET < 500nA ISET + POR – LTC6995-2 + ONLY VSET = 1V – 1V SET GND RST 3 22 1 699512 BD ISET RSET 699512fa 8 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 operaTion The LTC6995 is built around a master oscillator with a DIVCODE 1MHz maximum frequency. The oscillator is controlled The DIV pin connects to an internal, V+ referenced 4-bit A/D by the SET pin current (I ) and voltage (V ), with a SET SET converter that determines the DIVCODE value. DIVCODE 1MHz • 50k conversion factor that is accurate to ±0.8% programs two settings on the LTC6995: under typical conditions. 1. DIVCODE determines the output frequency divider set- 1 I fMASTER= =1MHz•50kΩ• SET ting, NDIV . t V MASTER SET 2. DIVCODE determines the polarity of the RST and OUT A feedback loop maintains V at 1V ±30mV, leaving I pins, via the POL bit. SET SET as the primary means of controlling the output frequency. V may be generated by a resistor divider between V+ DIV The simplest way to generate I is to connect a resistor SET and GND as shown in Figure 1. (R ) between SET and GND, such that I = V /R . SET SET SET SET The master oscillator equation reduces to: 2.25V TO 5.5V 1 1MHz•50kΩ V+ f = = MASTER LTC6995 R1 t R MASTER SET DIV From this equation, it is clear that V drift will not affect R2 SET the output frequency when using a single program resistor GND (R ). Error sources are limited to R tolerance and 699512 F01 SET SET the inherent frequency accuracy ∆fOUT of the LTC6995. Figure 1. Simple Technique for Setting DIVCODE R may range from 50k to 800k (equivalent to I SET SET Table 1 offers recommended 1% resistor values that ac- between 1.25µA and 20µA). curately produce the correct voltage division as well as the Before reaching the OUT pin, the oscillator frequency corresponding N and POL values for the recommended DIV passes through a fixed ÷1024 divider. The LTC6995 also resistor pairs. Other values may be used as long as: includes a programmable frequency divider which can 1. The V /V+ ratio is accurate to ±1.5% (including resis- further divide the frequency by 1, 8, 64, 512, 4096, 215, DIV tor tolerances and temperature effects) 218 or 221. The divider ratio N is set by a resistor divider DIV attached to the DIV pin. 2. The driving impedance (R1||R2) does not exceed 500kΩ. 1MHz•50kΩ I If the voltage is generated by other means (i.e., the output f = • SET , or OUT 1024•N V of a DAC) it must track the V+ supply voltage. The last DIV SET column in Table 1 shows the ideal ratio of V to the DIV 1 N V supply voltage, which can also be calculated as: t = = DIV • SET •1.024ms OUT f 50kΩ I OUT SET VDIV =DIVCODE+0.5±1.5% with R in place of V /I the equation reduces to: V+ 16 SET SET SET N •R For example, if the supply is 3.3V and the desired DIVCODE t = DIV SET •1.024ms OUT is 4, V = 0.281 • 3.3V = 928mV ± 50mV. 50kΩ DIV Figure 2 illustrates the information in Table 1, showing that N is symmetric around the DIVCODE midpoint. DIV 699512fa 9 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 operaTion Table 1. DIVCODE Programming DIVCODE POL N RECOMMENDED t R1 (kΩ) R2 (kΩ) V /V+ DIV OUT DIV 0 0 1 1.024ms to 16.384ms Open Short ≤0.03125 ±0.015 1 0 8 8.192ms to 131ms 976 102 0.09375 ±0.015 2 0 64 65.5ms to 1.05sec 976 182 0.15625 ±0.015 3 0 512 524ms to 8.39sec 1000 280 0.21875 ±0.015 4 0 4,096 4.19sec to 67.1sec 1000 392 0.28125 ±0.015 5 0 32,768 33.6sec to 537sec 1000 523 0.34375 ±0.015 6 0 262,144 268sec to 4,295sec 1000 681 0.40625 ±0.015 7 0 2,097,152 2,147sec to 34,360sec 1000 887 0.46875 ±0.015 8 1 2,097,152 2,147sec to 34,360sec 887 1000 0.53125 ±0.015 9 1 262,144 268sec to 4,295sec 681 1000 0.59375 ±0.015 10 1 32,768 33.6sec to 537sec 523 1000 0.65625 ±0.015 11 1 4,096 4.19sec to 67.1sec 392 1000 0.71875 ±0.015 12 1 512 524ms to 8.39sec 280 1000 0.78125 ±0.015 13 1 64 65.5ms to 1.05sec 182 976 0.84375 ±0.015 14 1 8 8.192ms to 131ms 102 976 0.90625 ±0.015 15 1 1 1.024ms to 16.384ms Short Open ≥0.96875 ±0.015 POL BIT = 0 POL BIT = 1 10000 7 8 1000 6 9 100 5 10 S) D 4 11 ON 10 C SE 3 12 (UT 1 tO 2 13 0.1 1 14 0.01 0 15 0.001 0V 0.5•V+ V+ INCREASING VDIV 699512 F02 Figure 2. Frequency Range and POL Bit vs DIVCODE 699512fa 10 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 operaTion Reset and Polarity Bit Functions With the POL bit programmed to be 0, the output will be forced low when reset. When reset is released by chang- The Reset input, RST for the LTC6995-1 and RST for the ing state, the oscillator starts. The next rising edge at the LTC6995-2, forces the output to a fixed state and resets output follows a precise half cycle delay. the internal clock dividers. The output state when reset is determined by the polarity bit as selected by through the With the POL bit programmed to be 1, the output will be DIVCODE setting. forced high when reset. When reset is released by chang- ing state, the oscillator starts. The next falling edge at the OUTPUT (OSCILLATOR START STATE) output follows a precise half cycle delay. RST/RST POLARITY LTC6995-1 LTC6995-2 0 0 Oscillating (Low) 0 (Reset) 1 0 0 (Reset) Oscillating (Low) 0 1 Oscillating (High) 1 (Reset) 1 1 1 (Reset) Oscillating (High) tWIDTH tWIDTH RST RST tRST tRST OUT REMAINS LOW OUT REMAINS LOW OUT OUT WHILE RST IS HIGH WHILE RST IS LOW tOUT tOUT 699512 F03 1/2 tOUT 1/2 tOUT LTC6995-1 LTC6995-2 Figure 3. Reset Timing Diagram (POL Bit = 0) tWIDTH tWIDTH RST RST tRST tRST OUT REMAINS HIGH OUT REMAINS HIGH OUT OUT WHILE RST IS LOW WHILE RST IS HIGH tOUT tOUT 699512 F04 1/2 tOUT 1/2 tOUT LTC6995-1 LTC6995-2 Figure 4. Reset Timing Diagram (POL Bit = 1) 699512fa 11 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 operaTion Changing DIVCODE After Start-Up voltages are not stable. For this reason, it is recommended to minimize the capacitance on the DIV pin so it will prop- Following start-up, the A/D converter will continue moni- erly track V+. Less than 100pF will not affect performance. toring V for changes. The LTC6995 will respond to DIV DIVCODE changes in less than one cycle. Start-Up Behavior t < 500 • t < t DIVCODE MASTER OUT When first powered up, the output is held low. If the polarity The output may have an inaccurate pulse width during the is set for non-inversion (POL = 0) and the output is enabled frequency transition. But the transition will be glitch-free at the end of the start-up time, OUT will begin oscillating. and no high or low pulse can be shorter than the mas- If the output is being reset (RST = 1 for LTC6995-1 and ter clock period. A digital filter is used to guarantee the RST = 0 for LTC6995-2) at the end of the start-up time, DIVCODE has settled to a new value before making changes it will remain low due to the POL bit = 0. When reset is to the output. released the oscillator starts and the output remains low for precisely one half cycle of the programmed period. Start-Up Time In inverted operation (POL = 1), the start-up sequence is When power is first applied, the power-on reset (POR) similar. However, the LTC6995 does not know the correct circuit will initiate the start-up time, tSTART . A supply DIVCODE setting when first powered up, so the output voltage of typically 1.4V (1.2V to 1.5V over temperature) defaults low. At the end of t , the value of DIVCODE is START initiates the start-up sequence. The OUT pin is held low recognized and OUT goes high (inactive) because POL = 1. during this time. The typical value for tSTART ranges from If the output is being reset (RST = 1 for LTC6995-1 and 0.5ms to 8ms depending on the master oscillator frequency RST = 0 for LTC6995-2) at the end of the start-up time, (independent of NDIV): it will remain high due to the POL bit = 1. When reset is released the oscillator starts and the output remains high t = 500 • t START(TYP) MASTER for precisely one half cycle of the programmed period. During start-up, the DIV pin A/D converter must deter- Figures 7 to 10 detail the possible start-up sequences. mine the correct DIVCODE before the output is enabled. The start-up time may increase if the supply or DIV pin DIV V+ 200mV/DIV 1V/DIV OUT 500µs 1V/DIV OUT 1V/DIV V+ = 3.3V 10ms/DIV 699512 V+ = 2.5V 250µs/DIV 699512 F06 RSET = 200k F05 DIVCODE = 15 RSET = 50k Figure 5. DIVCODE Change from 1 to 0 Figure 6. Typical Start-Up LTC6995-1 with RST = 0V 699512fa 12 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 operaTion RST RST OUT OUT tSTART tOUT tSTART tOUT 1/2 tOUT 1/2 tOUT LTC6995-1 LTC6995-2 699512 F07 Figure 7. Start-Up Timing Diagram (Reset = 0, POL Bit = 0) RST RST OUT OUT tSTART tOUT tSTART tOUT 1/2 tOUT 1/2 tOUT LTC6995-1 LTC6995-2 699512 F08 Figure 8. Start-Up Timing Diagram (Reset = 1, POL Bit = 0) RST RST OUT OUT tSTART tOUT tSTART tOUT 1/2 tOUT 1/2 tOUT LTC6995-1 LTC6995-2 699512 F09 Figure 9. Start-Up Timing Diagram (Reset = 0, POL Bit = 1) RST RST OUT OUT tSTART tOUT tSTART tOUT 1/2 tOUT 1/2 tOUT LTC6995-1 LTC6995-2 699512 F10 Figure 10. Start-Up Timing Diagram (Reset = 1, POL Bit = 1) 699512fa 13 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 applicaTions inForMaTion Basic Operation Example: Design a 1Hz oscillator with minimum power consumption, an active-high reset input, and the OUT pin The simplest and most accurate method to program the low during reset. LTC6995 is to use a single resistor, R , between the SET SET and GND pins. The design procedure is a 3-step Step 1: Select the LTC6995 Version and POL Bit Setting process. First select the POL bit setting and N value, DIV For active-high reset select the LTC6995-1. For OUT low then calculate the value for the R resistor. SET during reset choose POL bit = 0. Step 1: Select the LTC6995 Version and POL Bit Setting Step 2: Select the N Frequency Divider Value DIV Determine if the application requires an active-high, LTC6995-1 or active-low, LTC6995-2 reset function. Choose an NDIV value that meets the requirements of Otherwise the two versions share identical functionality. Equation (1), using tOUT = 1000ms: The OUT pin polarity depends on the setting of the POL 61.04 ≤ NDIV ≤ 976.6 bit. To force OUT = 0 during reset, choose POL bit = 0. To Potential settings for N include 64 and 512. N = 64 DIV DIV force OUT = 1 during reset, choose POL bit = 1. is the best choice, as it minimizes supply current by us- ing a large R resistor. POL = 0 and N = 64 requires SET DIV Step 2: Select the N Frequency Divider Value DIV DIVCODE = 2. Using Table 1, choose R1 = 976k and As explained earlier, the voltage on the DIV pin sets the R2 = 182k values to program DIVCODE = 2. DIVCODE which determines both the POL bit and the N DIV value. For a given output clock period, NDIV should be Step 3: Select RSET selected to be within the following range. Calculate the correct value for R using Equation (2). SET t t OUT ≤N ≤ OUT 50k 1000ms DIV (1) R = • =763k 16.384ms 1.024ms SET 1.024ms 64 To minimize supply current, choose the lowest N value DIV Since 763k is not available as a standard 1% resistor, (generally recommended). Alternatively, use Table 1 substitute 768k if a –0.7% frequency shift is acceptable. as a guide to select the best N value for the given DIV Otherwise, select a parallel or series pair of resistors such application. as 576k + 187k to attain a more precise resistance. With POL already chosen, this completes the selection of The completed design is shown in Figure 11. DIVCODE. Use Table 1 to select the proper resistor divider or V /V+ ratio to apply to the DIV pin. DIV Step 3: Calculate and Select R RST RST OUT SET LTC6995-1 2.25V TO 5.5V The final step is to calculate the correct value for R SET GND V+ using the following equation. R1 976k 50k t SET DIV DIVCODE = 2 RSET = • OUT 1 (2) RSET R2 1.024ms NDIV 763k 182k 699512 F11 Select the standard resistor value closest to the calculated Figure 11. 1Hz Oscillator value. 699512fa 14 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 applicaTions inForMaTion Power-On Reset (POR) Function When power is applied to the LTC6995 the output is held RST OUT POR LTC6995-1 low for t , then takes on the value of the POL bit as the START clock cycle begins. If POL = 0 (DIVCODE < 8) the output GND V+ 2.25V TO 5.5V will remain low for a programmable interval of tSTART + R19S1EkT R1M1 0.1µF 1/2 t , assuming the RST pin is inactive. This makes the SET DIV OUT R2 LTC6995 useful as a programmable long-time power-on RST = V+ FOR LTC6995-2 280k reset (POR), with the low output used to hold a system in reset for a fixed period after power is applied. Timing tPOR = 1 SECOND FOR VALUES SHOWN POL = 0 begins when the V+ supply exceeds approximately 1.4V. DIVCODE = 3 NDIV = 512 To prevent additional output transitions after the initial POR time, the oscillator can be disabled by removing the SET V+ tSTART pin current. This prevents the internal master oscillator ~1.4V STARTS TIMER output from clocking the frequency dividers or output, OUT tDELAY while keeping it biased so it can resume operation quickly. POL = 0 (1/2 tOUT) TIMER STOPPED The easiest way to implement this feature is to connect POWER-ON RESET 699512 F12 R between the SET and OUT pins. SET Figure 12. Active Low Power-On Reset Figure 12 shows the basic power-on reset function. When (1 Second Interval Example) the half cycle times out, the output goes high, eliminates the SET pin current, and stops additional OUT pin transi- tions. The output remains high until the device is reset by driving the RST input or power is cycled off then back on. The POR interval is only one half of an oscillator period so component selection is slightly different. Table 2 provides the component values required for one half cycle time intervals. Timing starts after a short startup delay time following the application of the V+ supply. Table 2. Power-On Reset (POR). One Shot, One Half Cycle Delay Programming Output Low During Time Interval, POL = 0 DIVCODE t TIME INTERVAL (1/2 t ) R1 (kΩ) R2 (kΩ) ~R (kΩ) DELAY OUT SET 0 512µs to 8.2ms Open Short t • 97.6 DELAY(MS) 1 4.1ms to 65.5ms 976 102 t • 12.2 DELAY(MS) 2 32.8ms to 524.3ms 976 182 t • 1.5 DELAY(MS) 3 262.1ms to 4.2sec 1000 280 t • 190.7 DELAY(SEC) 4 2.1sec to 33.6sec 1000 392 t • 23.8 DELAY(SEC) 5 16.8sec to 4.5min 1000 523 t • 178.6 DELAY(MIN) 6 2.2min to 35.8min 1000 681 t • 22.7 DELAY(MIN) 7 17.9min to 4.8hrs 1000 887 t • 167.6 DELAY(HR) Note: Power-On Reset Time = t + t DELAY START 699512fa 15 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 applicaTions inForMaTion For shorter power-on reset times (1ms to 73ms) the timer Long Timer One Shots and Delay Generators startup delay becomes a significant part of the total POR The POR circuit of Figure 12 is also useful when the reset time. To take this delay into account the value for R can SET inputs are driven. This creates edge triggered timing events be modified from the values shown in Table 2. For a POR that are active low and can either be re-triggered or can time in the range from 1ms to 16ms (DIVCODE = 0), R SET stop after one programmed interval. The programmed should be t (ms) • 49.5. For a POR time in the range POR time interval can range from only 500µs to over 4 hours from 4.5ms to 73ms (DIVCODE = 1), R is t (ms) • SET POR with just resistor value changes. 10.9. For longer POR times (DIVCODE 2 through 7) the startup time is insignificant. After power on, the delay fol- The circuits in Figure 13 show how a POR or active low lowing a reset condition will be in the same range as shown interval can be re-started to provide a full system reset time. for t in Table 2 for these two DIVCODE selections. DELAY The Figure 14 circuit requires an indication from the For short POR times, a more precise estimation of the system being reset that it is ready before timing out. The startup time can be found from the following: LTC6995-2 can accommodate an active high OK signal. R (kΩ) By forcing a reset condition at power on the LTC6995 can t (µs)=(256+16•(12–DIVCODE)) SET START be used to create a long time delayed rising edge triggered 50 by either a falling edge signal (LTC6995-1) or a rising edge +80 signal (LTC6995-2) as show in Figure 15. Supply bounce resets the internal timer so the POR circuit automatically debounces supply noise. POR timing starts from the time that the V+ supply has reached approximately 1.4 volts. V+ V+ 100k RST OUT POR RST OUT POR 100k LTC6995-1 LTC6995-2 GND V+ V+ GND V+ V+ 0.1µF 0.1µF R1 R1 RSET RSET SET DIV SET DIV R2 R2 ACTIVE HIGH RESET ACTIVE LOW RESET V+ V+ RESET RESET RST RST OUT tSTART + TIMER OUT tSTART + TIMER POL = 0 1/2 tOUT 1/2 tOUT STOPPED POL = 0 1/2 tOUT 1/2 tOUT STOPPED POR TIMER POR POR TIMER POR STOPPED STOPPED 699512 F13 Figure 13. System Resets On Command with Full POR Time Interval. Reset Pulse Is Debounced Automatically 699512fa 16 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 applicaTions inForMaTion SYSTEM OK V+ POR RST OUT SYSTEM LTC6995-1 RST SYSTEM OK GND V+ V+ 0.1µF R1 RSET OUT tSTART + TIMER SET DIV POL = 0 1/2 tOUT 1/2 tOUT STOPPED R2 POR POR EXTENDED POR 699512 F14 Figure 14. Extended POR. Timer Reset During Initial POR Interval. Full POR Interval Provided Once System Signals the OK TRIGGER RST OUT OUTPUT TRIGGER RST OUT OUTPUT LTC6995-1 LTC6995-2 GND V+ V+ GND V+ V+ 0.1µF 0.1µF R1 R1 RSET RSET SET DIV SET DIV FALLING EDGE TRIGGERED R2 RISING EDGE TRIGGERED R2 POL = 0 POL = 0 V+ V+ TRIGGER TRIGGER OUTPUT OUTPUT 1/2 tOUT 1/2 tOUT 1/2 tOUT 1/2 tOUT 699512 F15 Figure 15. Long Time Delayed Rising Edge. Delay Time Can Range from 500µs to 4.8 Hours 699512fa 17 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 applicaTions inForMaTion Watchdog Timers returns to issuing watchdog pulses. Figure 16 shows the timing for this application. Using the same circuits as shown in Figure 15 with pe- riodic pulsing of the reset input can create an effective Watchdog timers are used to detect if a system operating watchdog timer. A watchdog pulse is required from a software is diverted from the designed program sequence system within each timing interval. The watchdog timeout for any reason. It is always a possibility that the software interval can be programmed from 500µs to 4.8 hours. If a could get stuck in a way that keeps the watchdog pulse in pulse is missed the output goes high to indicate that the the state that holds the timer in the reset so it can never system software may be caught in an infinite loop. This time out. In this condition the watchdog timer is ineffective high level can be used to initiate software diagnostic or and will never force corrective action. To help to prevent restart procedures. The LTC6995 internal clock stops and this a second one shot can be used to reset the watchdog the output remains high until the software recovers and timer as shown in Figure 17. V+ MISSED PULSE RST (LTC6995-1) WATCHDOG PULSES RST (LTC6995-2) OUTPUT SERVICE WATCHDOG TIMER RESTARTS TIMEOUT RESUME 699512 F16 Figure 16. Watchdog Timer. Same Circuits as Shown in Figure 15 100µs ONE SHOT 50ms WATCHDOG TIMER SYSTEM POSITIVE TRG OUT RST OUT OUTPUT WATCHDOG PULSE LTC6993-1 LTC6995-1 GND V+ V+ GND V+ V+ RSET R1 0.1µF 604k 976k SET DIV SET DIV RSET R2 619k 102k RISING EDGE TRIGGERED FALLING EDGE TRIGGERED POSITIVE OUTPUT PULSE POL = 0 DIVCODE = 1 DIVCODE = 1 699512 F17 Figure 17. Extra-Reliable Watchdog Timer. Allows Timeout if System Watchdog Pulse Gets Stuck in the Timer Reset State. Both Timer Devices Can Share the Same DIVCODE Setting 699512fa 18 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 applicaTions inForMaTion Gated Oscillators A simple application of this technique allows the LTC6995 output to reset itself, producing a well-controlled pulse The reset input (RST) clears all internal dividers so that, once each cycle. Figures 19a and 19b show circuits that when released, the output will start clocking with a full produce approximately 1µs pulses once a minute. The only programmed period. This edge can be used to gate the difference is the version of LTC6995 used and the POL output ON and OFF at a known starting point for the clock. bit setting, which controls whether the pulse is positive Circuits which count clock cycles for further timing pur- or negative. poses will always have an accurate count of full cycles until reset. The output clock is always at 50% duty cycle Voltage Controlled Frequency and the period of each cycle can range from 1ms to 9.5 hours. Depending on the polarity bit selection the output With one additional resistor, the LTC6995 output frequency clock can start high or low as shown in Figure 18. can be manipulated by an external voltage. As shown in Figure 20, voltage V sources/sinks a current through CTRL Self-Resetting Circuits R to vary the I current, which in turn modulates the VCO SET output frequency as described in Equation (3). The RST pin has hysteresis to accommodate slow-changing input voltages. Furthermore, the trip points are proportional 1MHz(cid:127)50kΩ  R V  f = (cid:127) 1+ VCO – CTRL (3) to the supply voltage (see Note 6 and the RST Threshold OUT   1024(cid:127)N (cid:127)R  R V  DIV VCO SET SEET Voltage vs Supply Voltage curve in Typical Performance Characteristics). This allows an RC time constant at the RST input to generate a delay that is nearly independent of the supply voltage. LTC6995-1 LTC6995-2 ACTIVE HIGH RESET ACTIVE LOW RESET RST FALLING EDGE STARTS THE CLOCK RST RISING EDGE STARTS THE CLOCK RST RST OUT OUT POL = 0 1/2 tOUT POL = 0 1/2 tOUT OUT 1/2 tOUT OUT 1/2 tOUT POL = 1 POL = 1 699512 F18 Figure 18. Gated Oscillators. First One-Half Cycle Time Always Accurate 699512fa 19 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 applicaTions inForMaTion OUT RPW RST OUT 2.26k LTC6995-1 V+ RST OUT CPW LTC6995-1 GND V+ 470pF 2.25V TO 5.5V C1 GND V+ RVCO 0.1µF R1 RSET R1 0.1µF VCTRL SET DIV 178k 1M SET DIV RSET R2 R2 699512 F20 523k Figure 20. Voltage-Controlled Oscillator ( VRST(RISING)) tPULSE = –RPW • CPW • In1– V+ Digital Frequency Control tPULSE ≈ –2.26kΩ • 470pF • In(1 – 0.61) tPULSE ≈ 1µs The control voltage can be generated by a DAC (digital- 1µs PULSE WIDTH to-analog converter), resulting in a digitally-controlled 60 SECONDS frequency. Many DACs allow for the use of an external reference. If such a DAC is used to provide the V CTRL 699512 F19a voltage, the V dependency can be eliminated by buffer- SET Figure 19a. Self-Resetting Circuit (DIVCODE = 5) ing VSET and using it as the DAC’s reference voltage, as shown in Figure 21. The DAC’s output voltage now tracks any V variation and eliminates it as an error source. SET OUT The SET pin cannot be tied directly to the reference input R2.P2W6k of the DAC because the current drawn by the DAC’s REF RST OUT input would affect the frequency. CPW LTC6995-2 470pF 2.25V TO 5.5V GND V+ ISET Extremes (Master Oscillator Frequency Extremes) RSET R1 0.1µF 178k 523k When operating with I outside of the recommended SET SET DIV 1.25µA to 20µA range, the master oscillator operates R2 1M outside of the 62.5kHz to 1MHz range in which it is most accurate. (VRST(FALLING)) tPULSE = –RPW • CPW • In V+ The oscillator can still function with reduced accuracy for tPULSE ≈ –2.26kΩ • 470pF • In(0.43) I < 1.25µA. At approximately 500nA, the oscillator output tPULSE ≈ 0.9µs SET will be frozen in its current state. The output could halt in 0.9µs PULSE WIDTH 60 SECONDS a high or low state. This avoids introducing short pulses when frequency modulating a very low frequency output. 699512 F19b At the other extreme, it is not recommended to operate Figure 19b. Self-Resetting Circuit (DIVCODE = 10) the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer. 699512fa 20 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 applicaTions inForMaTion RST OUT LTC6995-1 V+ V+ GND V+ 0.1µF C1 0.1µF R1 + SET DIV 1/2 LTC6078 R2 V+ – 0.1µF ( ) VCC REF fOUT = 10214M (cid:127)H Nz D(cid:127)I V5 0(cid:127)k RΩVCO(cid:127) 1 +RRVSCEOT–4D0I9N6 DIN RVCO DIN = 0 TO 4095 µP CLK LTC1659 VOUT CS/LD RSET GND 699512 F21 Figure 21. Digitally-Controlled Oscillator Frequency Modulation and Settling Time and by following a few rules, the expected performance is easily achieved. Adequate supply bypassing and proper The LTC6995 will respond to changes in I up to a –3dB SET PCB layout are important to ensure this. bandwidth of 0.4 • f . OUT Figure 22 shows example PCB layouts for both the TSOT-23 Following a 2× or 0.5× step change in I , the output SET and DFN packages using 0603 sized passive components. frequency takes less than one cycle to settle to within 1% The layouts assume a two layer board with a ground plane of the final value. layer beneath and around the LTC6995. These layouts are a guide and need not be followed exactly. Power Supply Current 1. Connect the bypass capacitor, C1, directly to the V+ and The power supply current varies with frequency, supply GND pins using a low inductance path. The connection voltage and output loading. It can be estimated under from C1 to the V+ pin is easily done directly on the top any condition using the following equation. This equation layer. For the DFN package, C1’s connection to GND is ignores C (valid for C < 1nF) and assumes the LOAD LOAD also simply done on the top layer. For the TSOT-23, OUT output has 50% duty cycle. can be routed through the C1 pads to allow a good C1 V+ V+ GND connection. If the PCB design rules do not allow I ≈V+ •f •7.8pF+ + S(TYP) MASTER 420kΩ 2•R that, C1’s GND connection can be accomplished through LOAD multiple vias to the ground plane. Multiple vias for both +1.8•I +50µA the GND pin connection to the ground plane and the SET C1 connection to the ground plane are recommended Supply Bypassing and PCB Layout Guidelines to minimize the inductance. Capacitor C1 should be a The LTC6995 is a 2.2% accurate silicon oscillator when 0.1µF ceramic capacitor. used in the appropriate manner. The part is simple to use 699512fa 21 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 applicaTions inForMaTion RST OUT LTC6995-1 GND V+ V+ C1 0.1µF R1 SET DIV RSET R2 V+ C1 V+ R1 C1 V+ OUT RST OUT DIV GND GND V+ R2 SET RST SET DIV R1 RSET RSET R2 699512 F22 DFN PACKAGE TSOT-23 PACKAGE Figure 22. Supply Bypassing and PCB Layout 2. Place all passive components on the top side of the 4. Connect R directly to the GND pin. Using a long path SET board. This minimizes trace inductance. or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is 3. Place R as close as possible to the SET pin and SET recommended and easy to apply. make a direct, short connection. The SET pin is a current summing node and currents injected into this 5. Use a ground trace to shield the SET pin. This provides pin directly modulate the operating frequency. Having another layer of protection from radiated signals. a short connection minimizes the exposure to signal 6. Place R1 and R2 close to the DIV pin. A direct, short pickup. connection to the DIV pin minimizes the external signal coupling. 699512fa 22 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 Typical applicaTions Timed Power Switches, Auto Shutoff After One Hour P-CHANNEL MOSFET * 3V TO 36V TO LOAD 5V COUT CURRENT DEPENDS LTC4412HV ON PMOS SELECTION 0.1µF VIN SENSE PUSH TO ACTIVATE GND GATE LOW = ON CTL STAT HIGH = OFF RST OUT *DRAIN-SOURCE DIODE OF MOSFET 100k LTC6995-1 GND V+ 5V RSET R1 0.1µF 169k SET DIV 1M 2.6V TO 5.5V IN OUT TUOP LTOOA 2D.6A R2 1µF GNDLTC4411 4C.O7UµTF ACTIVE HIGH RESET 887k 1/2 tOUT = 1 HOUR CTL STAT 699512 TA08 5 Second On/Off Timed Relay Driver 12V 0.1µF L C D1 1N4148 NO RESET 1 R4 RUN 10k COTO 1022 RELAY RELAY ENABLE RST OUT Q1 9001-12-01 2N2219A LTC6995-1 5V GND V+ R1 C2 1M 0.1µF SET DIV R2 R3 392k 118k 699512 TA02 699512fa 23 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 Typical applicaTions 1.5ms Radio Control Servo Reference Pulse Generator 5V 20ms 1.5ms FRAME RATE REFERENCE R7 10k GENERATOR 20ms PERIOD PULSE RESET = OPEN RST OUT TRIG OUT 1.5ms PULSE RUN = GND LTC6995-1 LTC6993-1 5V 5V GND V+ GND V+ C1 C2 R4 0.01µF R1 0.1µF 976k 1M SET DIV SET DIV R6 R5 R3 R2 121k 102k 146k 280k 699512 TA03 Cycling (10 Seconds On/Off) Symmetrical Power Supplies M2 Si4435DY 15VIN 15VOUT R6 20k R2 R11 1k 5k M3 RST OUT Si9410 LTC6995-1 GND V+ 5V R8 C1 1M 0.1µF SET DIV M4 Si4435DY R10 R9 237k 392k R3 R1 50k 100k –15VIN –15VOUT M1 Si9410 699512 TA04 Isolated AC Load Flasher 5V 0.1µF R103k 5 R4 U2 R5 40W LAMP OPEN = OFF 1 V+ 6 215Ω 1 MOC3041M 6 5.94k HOT RST OUT GND = ON 117V AC LTC6995-1 R1 R7 2 3 SET DIV 4 1M 5V U3 100Ω 2R3S7EkT GND2 R3922k CRZOESRSOING 4 R6 NTE5642 C0.2022µF 10k NEUTRAL 10 SECONDS ON/OFF AC 699512 TA05 ISOLATION BARRIER = 7500V 699512fa 24 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 Typical applicaTions Interval (Wiper) Timer 2s 5s 15s 5V 30s V+ 1m 2m 4m OFF RST OUT TRIG OUT OUTPUT 24.9k LTC6995-1 LTC6993-1 2s 2s GND V+ V+ GND V+ V+ 178k 5s 0.1µF 0.1µF tINTERVAL 15s 1M 1M 30s 2 SECONDS TO 59k SET DIV SET DIV 4 MINUTES 1m 2m 383k 681k 29.4k 4m OFF 2s 699512 TA06 90.9k 2s 280k 5s 15s 30s 113k 1m 2m 133k 4m OFF 154k Adjustable Time Lapse Photography Intervalometer SHUTTER OPEN TIME LAPSE TIME LAPSE RST OUT TRG OUT OUTPUT LTC6995-1 LTC6993-3 GND V+ V+ GND V+ V+ 0.1µF 1M 66.5k 3s TO 30m TO 56.2k SET DIV 30s 3Hrs SET DIV SHORT SHORT 1M 2M LONG TIMER 30s TO 3m TO 1M 2M NON-RETRIGGERABLE LONG 3s TO 3Hrs 392k 3m 30m 967k LONG ONE SHOT TIMER 0.3s TO 30s 523k 681k 0.3s TO 3s TO 3s 30s 681k 887k 1M TIME LAPSE EXPOSURE TIME 699512 TA09 699512fa 25 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 0.95 2.90 BSC MAX REF (NOTE 4) 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1(.5N0O T–E 1 4.7)5 PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT 0.30 – 0.45 0.95 BSC PER IPC CALCULATOR 6 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 1.90 BSC (NOTE 3) S6 TSOT-23 0302 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 2. DRAWING NOT TO SCALE 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 3. DIMENSIONS ARE INCLUSIVE OF PLATING 6. JEDEC PACKAGE REFERENCE IS MO-193 DCB Package 6-Lead Plastic DFN (2mm × 3mm) (Reference LTC DWG # 05-08-1715 Rev A) 2.00 ±0.10 R = 0.115 0.40 ±0.10 (2 SIDES) TYP R = 0.05 4 6 0.70 ±0.05 TYP PACKAGE 3.55 ±0.05 1.65 ±0.05 OUTLINE 3.00 ±0.10 1.65 ±0.10 (2 SIDES) (2 SIDES) (2 SIDES) 2.15 ±0.05 PIN 1 BAR PIN 1 NOTCH TOP MARK R0.20 OR 0.25 (SEE NOTE 6) × 45° CHAMFER 3 1 (DCB6) DFN 0405 0.25 ±0.05 0.25 ±0.05 0.50 BSC 0.200 REF 0.75 ±0.05 0.50 BSC 1.35 ±0.05 1.35 ±0.10 (2 SIDES) (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 2. DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED 3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 699512fa 26 For more information www.linear.com/LTC6995-1

LTC6995-1/LTC6995-2 revision hisTory REV DATE DESCRIPTION PAGE NUMBER A 09/13 Grammatical corrections 1, 4, 8, 16 Correction to Master Oscillator, Block Diagram 8 Divcode changed from 4 to 5, Figure 19a 20 Divcode changed from 11 to 10, Figure 19b 20 LTC6995 block identified as LTC6995-1, Figure 21 and Figure 22 21, 22 Replace V+ with 5V, Sentry Time schematic 28 699512fa 27 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnFeoctrio mn oofr iets i cnifrocurimts aatsi odnes cwriwbewd. lhienreeainr. wcoillm no/Lt TinCfr6in9g9e5 o-n1 existing patent rights.

LTC6995-1/LTC6995-2 Typical applicaTion Sentry Timer 5V Q CLK 5V FF Q D 5V 100k CLR PUSH BUTTON RST OUT EVERY 4 HOURS OR ALARM SOUNDS LTC6995-2 15Ω GND V+ 5V 800Hz 4 HOUR TIMER ALARM TONE R1 DIVCODE = 7 DIVCODE = 0 887k SET DIV R2 32Ω 49.9k 60.4k 332k 75k 699512 TA07 relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTC1799 1MHz to 33MHz ThinSOT Silicon Oscillator Wide Frequency Range LTC6900 1MHz to 20MHz ThinSOT Silicon Oscillator Low Power, Wide Frequency Range LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillators Micropower, I = 35µA at 400kHz SUPPLY LTC6930 Fixed Frequency Oscillator, 32.768kHz to 8.192MHz 0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz LTC6990 TimerBlox: Voltage-Controlled Silicon Oscillator Fixed-Frequency or Voltage-Controlled Operation LTC6991 TimerBlox: Very Low Frequency Oscillator with Reset Cycle Time from 1ms to 9.5 Hours, No Capacitors, 2.2% Accurate LTC6992 TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) Simple PWM with Wide Frequency Range LTC6993 TimerBlox: Monostable Pulse Generator (One Shot) Resistor Programmable Pulse Width of 1µs to 34sec LTC6994 TimerBlox: Delay Block/Debouncer Delays Rising, Falling or Both Edges 1µs to 34sec 699512fa 28 Linear Technology Corporation LT 0913 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC6995-1 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC6995-1  LINEAR TECHNOLOGY CORPORATION 2013

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