LTC6802-2 Multicell Addressable Battery Stack Monitor FeaTures DescripTion n Measures Up to 12 Li-Ion Cells in Series (60V Max) The LTC®6802-2 is a complete battery monitoring IC that n Stackable Architecture Enables Monitoring High includes a 12-bit ADC, a precision voltage reference, a Voltage Battery Stacks high voltage input multiplexer and a serial interface. Each n Individually Addressable with 4-Bit Address LTC6802-2 can measure 12 series connected battery cells, n 0.25% Maximum Total Measurement Error with a total input voltage up to 60V. The voltage on all 12 n 13ms to Measure All Cells in a System input channels can be measured within 13ms. n Cell Balancing: Many LTC6802-2 devices can be stacked to measure the On-Chip Passive Cell Balancing Switches voltage of each cell in a long battery string. Each LTC6802-2 Provision for Off-Chip Passive Balancing has an individually addressable serial interface, allowing n Two Thermistor Inputs Plus Onboard up to 16 LTC6802-2 devices to interface to one control Temperature Sensor processor and operate simultaneously. n 1MHz Serial Interface with Packet Error Checking n High EMI Immunity To minimize power, the LTC6802-2 offers a measure mode n Delta-Sigma Converter With Built-In Noise Filter to monitor each cell for overvoltage and undervoltage n Open-Wire Connection Fault Detection conditions. A standby mode is also provided to reduce n Low Power Modes supply current to 50µA. n 44-Lead SSOP Package Each cell input has an associated MOSFET switch that can discharge any overcharged cell. applicaTions The related LTC6802-1 offers a serial interface that allows n Electric and Hybrid Electric Vehicles the serial ports of multiple LTC6802-1 devices to be daisy n High Power Portable Equipment chained without opto-couplers or isolators. n Backup Battery Systems L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n High Voltage Data Acquisition Systems Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion Measurement Error Over NEXT 12-CELL Extended Temperature PACK ABOVE LTC6802-2 V+ 0.30 DIE TEMP 7 REPRESENTATIVE UNITS + 0.25 VS = 43.2V 0.20 CELL VOLTAGE 3.6V SERIAL DATA %) 0.15 REGISTERS R ( AND O 0.10 B1A2T-TCEERLYL MUX CONTROL 4A-DBDITRESS ENT ERR 0.005 STRING + EM–0.05 R U–0.10 ∆1∑2 -ABDITC MEAS–0.15 + –0.20 –0.25 V– VOLTAGE –0.30 EXTERNAL REFERENCE –50 –25 0 25 50 75 100 125 NEXT 12-CELL TEMP TEMPERATURE (°C) PACK BELOW 68022 TA01a 68022 TA01b 100k 100k NTC 68022fa 

LTC6802-2 absoluTe MaxiMuM raTings pin conFiguraTion (Note 1) Total Supply Voltage (V+ to V–) .................................60V TOP VIEW Input Voltage (Relative to V–) V+ 1 44 CSBI C1 ............................................................–0.3V to 9V C12 2 43 SDO C12 ..........................................V+ – 0.6V to V+ + 0.3V S12 3 42 SDI C11 4 41 SCKI Cn (Note 5) .........................–0.3V to Min (9 • n, 60V) S11 5 40 A3 Sn (Note 5) .........................–0.3V to Min (9 • n, 60V) C10 6 39 A2 All Other Pins ...........................................–0.3V to 7V S10 7 38 A1 Voltage Between Inputs C9 8 37 A0 Cn to Cn – 1 .............................................–0.3V to 9V S9 9 36 GPIO2 Sn to Cn – 1 .............................................–0.3V to 9V C8 10 35 GPIO1 C12 to C8 ...............................................–0.3V to 25V S8 11 34 WDTB C8 to C4 .................................................–0.3V to 25V C7 12 33 MMB C4 to V– .................................................–0.3V to 25V S7 13 32 TOS Operating Temperature Range..................–40°C to 85°C C6 14 31 VREG Specified Temperature Range ..................–40°C to 85°C S6 15 30 VREF Junction Temperature ...........................................150°C C5 16 29 VTEMP2 Storage Temperature Range ...................–65°C to 150°C S5 17 28 VTEMP1 C4 18 27 NC *n = 1 to 12 S4 19 26 V– C3 20 25 S1 S3 21 24 C1 C2 22 23 S2 G PACKAGE 44-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 70°C/W orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC6802IG-2#PBF LTC6802IG-2#TRPBF LTC6802G-2 44-Lead Plastic SSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 68022fa 

LTC6802-2 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted. A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Specifications V Measurement Resolution Quantization of the ADC l 1.5 mV/Bit ACC ADC Offset Voltage (Note 2) l –0.5 0.5 mV ADC Gain Error (Note 2) –0.12 0.12 % l –0.22 0.22 % V Total Measurement Error (Note 4) ERR V = 0V 0.8 mV CELL V = 2.3V –2.8 2.8 mV CELL V = 2.3V l –5.1 5.1 mV CELL V = 3.6V –4.3 4.3 mV CELL V = 3.6V l –7.9 7.9 mV CELL V = 4.2V –5 5 mV CELL V = 4.2V l –9.2 9.2 mV CELL V = 4.6V ±8 mV CELL V = 2.3V l –5.1 5.1 mV TEMP V = 3.6V l –7.9 7.9 mV TEMP V = 4.2V l –9.2 9.2 mV TEMP V Cell Voltage Range Full-Scale Voltage Range 5 V CELL VCM Common Mode Voltage Range Measured Range of Inputs Cn for <0.25% Gain Error, n = 3 to 11 l 3.7 5 • n V Relative to V– Range of Input C3 for <1% Gain Error l 1.8 15 V Range of Input C2 for <0.25% Gain Error l 1.2 10 V Range of Input C1 for <0.25% Gain Error l 0 5 V Overvoltage (OV) Detection Level Programmed for 4.2V l 4.182 4.200 4.218 V Undervoltage (UV) Detection Level Programmed for 2.3V l 2.290 2.300 2.310 V Die Temperature Measurement Error Error in Measurement at 125°C 3 °C V Reference Pin Voltage R = 100k to V– 3.020 3.065 3.110 V REF LOAD l 3.015 3.065 3.115 V Reference Voltage Temperature 8 ppm/°C Coefficient Reference Voltage Thermal Hysteresis 25°C to 85°C and 25°C to –40°C 100 ppm Reference Voltage Long-Term Drift 60 ppm/√kHr V Regulator Pin Voltage 10 < V+ < 50, No Load l 4.5 5.0 5.5 V REG I = 4mA l 4.1 4.8 V LOAD Regulator Pin Short-Circuit Current Limit l 5 8 mA V Supply Voltage, V+ Relative to V– V Specifications Met l 10 50 V S ERR Timing Specifications Met l 4 50 V I Input Bias Current In/Out of Pins C1 Through C12 B When Measuring Cells l –10 10 µA When Not Measuring Cells 1 nA I Supply Current, Active Current Into the V+ Pin When Measuring Voltages with 0.8 1.1 mA S the ADC l 1.2 mA I Supply Current, Monitor Mode Average Current Into the V+ Pin While Monitoring for M UV and OV Conditions Continuous Monitoring (CDC = 2) 800 µA Monitor Every 130ms (CDC = 5) 225 µA Monitor Every 500ms (CDC = 6) 150 µA Monitor Every 2 Seconds (CDC = 7) 100 µA I Supply Current, Idle Current Into the V+ Pin When Idle 37.5 62.5 82.5 µA QS All Serial Port Pins at Logic ‘1’ l 32.5 87.5 µA 68022fa 

LTC6802-2 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted. A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Discharge Switch On-Resistance V > 3V (Note 3) l 10 20 Ω CELL Temperature Range l –40 85 °C Thermal Shutdown Temperature 145 °C Thermal Shutdown Hysteresis 5 °C Timing Specifications t Measurement Cycle Time Time Required to Measure 11 or 12 Cells l 11 13 16 ms CYCLE Time Required to Measure Up to 10 Cells l 9.2 11 13.5 ms Time Required to Measure 1 Cell 1 1.2 1.5 ms t SDI Valid to SCKI Rising Setup l 10 ns 1 t SDI Valid to SCKI Rising Hold l 250 ns 2 t SCKI Low l 400 ns 3 t SCKI High l 400 ns 4 t CSBI Pulse Width l 400 ns 5 t SCKI Rising to CSBI Rising l 100 ns 6 t CSBI Falling to SCKI Rising l 100 ns 7 t SCKI Falling to SDO Valid l 250 ns 8 Clock Frequency l 1 MHz Watchdog Timer Time-Out Period l 1 2.5 s Digital I/O Specifications V Digital Voltage Input High l 2 V IH V Digital Voltage Input Low l 0.8 V IL V Digital Voltage Output Low Sinking 500µA l 0.3 V OL Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: V refers to the voltage applied across the following pin CELL may cause permanent damage to the device. Exposure to any Absolute combinations: Cn to Cn – 1 for n = 2 to 12, C1 to V–. VTEMP refers to the Maximum Rating condition for extended periods may affect device voltage applied from V or V to V– TEMP1 TEMP2 reliability and lifetime. Note 5: These absolute maximum ratings apply provided that the voltage Note 2: The ADC specifications are guaranteed by the total measurement between inputs do not exceed their absolute maximum ratings. error (V ) specification. ERR Note 3: Due to the contact resistance of the production tester, this specification is tested to relaxed limits. The 20Ω limit is guaranteed by design. 68022fa 

LTC6802-2 Typical perForMance characTerisTics Cell Measurement Total Cell Measurement Total Unadjusted Error vs Input Measurement Gain Error Unadjusted Error Resistance Hysteresis 10 10 25 TA = –40°C TA = 85°C TO 25°C 8 TA = 25°C 0 mV) 6 TA = 85°C mV) 20 R ( TA = 125°C R ( –10 RO 4 RO –20 TS STED ER 02 STED ER –30 R OF UNI15 DJU –2 DJU –40 RS = 1k MBE10 TOTAL UNA ––46 TOTAL UNA ––6500 RS IN SERRRRISSSE S=== 251Wkk0IkTH Cn AND Cn– 1 NU 5 –8 –70 NO EXTERNAL CAPACITANCE ON Cn AND Cn – 1 –10 –80 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –250–200–150–100–50 0 50 100 150 200 CELL VOLTAGE (V) CELL VOLTAGE (V) CHANGE IN GAIN ERROR (ppm) 68022 G09 68022 G10 68022 G20 Measurement Gain Error Cell Measurement Common Mode ADC Normal Mode Rejection vs Hysteresis Rejection Frequency 20 0 0 TA = –45°C TO 25°C VCM(IN) = 5VP-P 18 72dB REJECTION –10 CORRESPONDS TO –10 16 LESS THAN 1 BIT S14 –20 AT ADC OUTPUT –20 R OF UNIT1120 TION (db)–30 TION (db)–30 MBE 8 EJEC–40 EJEC–40 U R R N 6 –50 –50 4 –60 –60 2 0 –70 –70 –250–200–150–100–50 0 50 100 150 200 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k CHANGE IN GAIN ERROR (ppm) FREQUENCY (Hz) FREQUENCY (Hz) 68022 G21 68022 G15 68022 G14 ADC INL ADC DNL Cell Input Bias Current in Standby 2.0 1.0 50 0.8 1.5 40 0.6 1.0 A) 0.4 T (n 30 INL (BITS)–00..505 DNL (BITS) –00..202 BIAS CURREN 20 C12 C1 –1.0 –0.4 C PIN 10 –0.6 0 –1.5 –0.8 C2 TO C11 –2.0 –1.0 –10 0 1 2 3 4 5 0 1 2 3 4 5 –40 –20 0 20 40 60 80 100 120 INPUT (V) INPUT (V) TEMPERATURE (°C) 68022 G05 68022 G06 68022 G03 68022fa 

LTC6802-2 Typical perForMance characTerisTics Cell Input Bias Current During Supply Current vs Supply Voltage Supply Current vs Supply Voltage Conversion Standby in CDC = 2 2.70 60 0.90 CELL INPUT = 3.6V CDC = 2 (CONTINUOUS CELL CONVERSIONS) 2.65 A) 50 0.85 µ C PIN BIAS CURRENT (µA) 22222.....6554405005 STANDBY SUPPLY CURRENT ( 43210000 TTAA == –2450°C°C SUPPLY CURRENT (mA) 0000....87760505 TTTAAA === 82–554°°0CC°C TA = 85°C 2.35 0 0.60 –40 –20 0 20 40 60 80 100 120 0 10 20 30 40 50 60 0 10 20 30 40 50 60 TEMPERATURE (°C) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 68022 G04 68022 G01 68022 G02 Internal Die Temperature External Temperature Measurement vs Ambient Measurement Total Unadjusted V Output Voltage vs REF Temperature Error vs Input Temperature E L DIE TEMPERATURTEMPERATURE (°C) 5423 VS = 43.2V RROR (mV) 1005 333...000766086 CE BETWEEN INTERNAEMENT AND AMBIENT –––02113 DEVICE IN STANDBY PRIOR TO TOTAL UNADJUSTED E––1–1550 TTAA == –2450°C°C V (V)REF 3333....000066654028 ENUR –4 MAKING DIE MEASUREMENTS TA = 85°C DIFFERMEAS –5–50 –25 0TO M25INIMI5Z0E SEL7F5 HEA1T0IN0G 125 –200 0.5 1T.A0 = 11.055°2C.0 2.5 3.0 3.5 4.0 4.5 5.0 3.056–505 RE–P2R5ESEN0TATIV2E5 UNIT5S0 75 100 125 AMBIENT TEMPERATURE (°C) TEMPERATURE INPUT VOLTAGE (V) TEMPERATURE (°C) 68022 G12 68022 G13 68022 G22 V Load Regulation V Line Regulation V Load Regulation REF REF REG 3.09 3.074 5.4 NO EXTERNAL LOAD ON VREF, CDC = 2 (CONTINUOUS CELL CONVERSIONS) 3.072 5.2 3.08 3.070 5.0 TA = 85°C 3.07 TA = 25°C V (V)REF3.06 V (V)REF 33..006686 TA = 85°C V (V)REG 44..86 TTAA = = – 2450°°CC 3.064 TA = –40°C 4.4 3.05 TA = –40°C TA = 25°C 3.062 4.2 TA = 85°C 3.04 3.060 4.0 0 10 100 1000 0 10 20 30 40 50 60 0 1 2 3 4 5 6 7 8 9 10 SOURCING CURRENT (µA) SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 68022 G07 68022 G08 68022 G16 68022fa 

LTC6802-2 Typical perForMance characTerisTics Internal Discharge Resistance vs V Line Regulation Cell Voltage REG 5.5 50 TA = –45°C 5.0 TA = 85°C CE (Ω) 434550 TTTAAA === 281550°°5CC°C (V)G 4.5 TA = 25°C TA = –40°C ESISTAN 2350 VRE 4.0 GE R 20 R A H 15 C S 3.5 DI 10 NO EXTERNAL LOAD ON VREG, CDC = 2 5 (CONTINUOUS CELL CONVERSIONS) 3.0 0 5 15 25 35 45 55 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) CELL VOLTAGE (V) 68022 G17 68022 G11 Die Temperature Increase vs Discharge Current in Internal FET Cell Conversion Time 50 13.20 ALL 12 CELLS AT 3.6V C) 45 VS = 43.2V 13.15 E (° 40 TA = 25°C UR s)13.10 T 35 m MPERA 30 12 CELLS TIME (13.05 DIE TE 2250 DISCHARGING 6D ICSECLHLASRGING RSION 13.00 ASE IN 15 1 CELL CONVE1122..9905 RE 10 DISCHARGING C N 12.85 I 5 0 12.80 0 10 20 30 40 50 60 70 80 –40 –20 0 20 40 60 80 100 120 DISCHARGE CURRENT PER CELL (mA) TEMPERATURE (°C) 68022 G18 68022 G19 68022fa 

LTC6802-2 pin FuncTions V+ (Pin 1): Tie Pin 1 to the most positive potential in V (Pin 30): 3.075V Voltage Reference Output. This pin REF the battery stack. V+ must be approximately the same should be bypassed with a 1µF capacitor. The V pin can REF potential as C12. drive a 100k resistive load connected to V–. Larger loads should be buffered with an LT6003 op amp, or similar C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1 device. (Pins 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24): C1 through C12 are the inputs for monitoring battery cell V (Pin 31): Linear Voltage Regulator Output. This pin REG voltages. Up to 12 cells can be monitored. The lowest should be bypassed with a 1µF capacitor. The V is REG potential is tied to the V– pin. The next lowest potential capable of sourcing up to 4mA to an external load. The is tied to C1 and so forth. See the figures in the Applica- V pin does not sink current. REG tions Information section for more details on connecting TOS (Pin 32): Top of Stack Input. The TOS pin can be tied batteries to the LTC6802-2. to V or V– for the LTC6802-2. The state of the TOS pin REG S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 alters the operation of the SDO pin in the toggle polling (Pins 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25): S1 though mode. See the Serial Port description. S12 pins are used to balance battery cells. If one cell in a MMB (Pin 33): Monitor Mode Input (Active Low). When series becomes over charged, an S output can be used to MMB is low (same potential as V–), the LTC6802-2 discharge the cell. Each S output is an internal N-channel goes into monitor mode. See Modes of Operation in the MOSFET for discharging. See the Block Diagram. The NMOS Applications Information section. has a maximum on-resistance of 20Ω. An external resistor should be connected in series with the NMOS to dissipate WDTB (Pin 34): Watchdog Timer Output (Active Low). If heat outside of the LTC6802-2 package. When using the there is no activity on the SCKI pin for 2.5 seconds, the internal MOSFETs to discharge cells, the die temperature WDTB output is asserted. The WDTB pin is an open-drain should be monitored. See Power Dissipation and Thermal NMOS output. When asserted it pulls the output down Shutdown in the Applications Information section. to V– and resets the configuration register to its default state. See Watchdog Timer Circuit in the Applications The S pins also feature an internal 10k pull-up resistor. This Information section. allows the S pins to be used to drive the gates of external P-channel MOSFETs for higher discharge capability. GPIO1, GPIO2 (Pins 35, 36): General Purpose Input/Out- put. The operation of these pins depends on the state of V– (Pin 26): Connect V– to the most negative potential in the MMB pin. the series of cells. When MMB is high, the pins behave as traditional GPIOs. NC (Pin 27): Pin 27 is internally connected to V– through By writing a “0” to a GPIO configuration register bit, the 10Ω. Pin 27 can be left unconnected or connect Pin 27 open drain output is activated and the pin is pulled to V–. to Pin 26 on the PCB. By writing a logic “1” to the configuration register bit, the V , V (Pins 28, 29): Temperature Sensor Inputs. corresponding GPIO pin is high impedance. An external TEMP1 TEMP2 The ADC will measure the voltage on V with respect resistor is needed to pull the pin up to V . TEMPx REG to V– and store the result in the TMP register. The ADC By reading the configuration register locations GPIO1 measurements are relative to the V pin voltage. Therefore REF and GPIO2, the state of the pins can be determined. For a simple thermistor and resistor combination connected example, if a “0” is written to register bit GPIO1, a “0” to the V pin can be used to monitor temperature. The REF is always read back because the output NMOSFET pulls V inputs can also be general purpose ADC inputs. TEMP Pin 35 to V–. If a “1” is written to register bit GPIO1, the 68022fa 

LTC6802-2 pin FuncTions pin becomes high impedance. Either a “1” or a “0” is read SCKI (Pin 41): Serial Clock Input. The SCKI pin inter- back, depending on the voltage present at Pin 35. The faces to any logic gate (TTL levels). See Serial Port in the GPIOs make it possible to turn on/off circuitry around Applications Information section. the LTC6802-2, or read logic values from a circuit around SDI (Pin 42): Serial Data Input. The SDI pin interfaces to the LTC6802-2. any logic gate (TTL levels). See Serial Port in the Applica- When the MMB pin is low, the GPIO pins and the WDTB tions Information section. pin are treated as inputs that set the number of cells to SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS be monitored. See Monitor Mode in the Applications open drain output and requires an external resistor pull-up. Information section. See Serial Port in the Applications Information section. A0, A1, A2, A3 (Pins 37, 38, 39, 40): Address Inputs. CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI These pins are tied to V or V–. The state of the address REG pin interfaces to any logic gate (TTL levels). See Serial pins (V = 1, V– = 0) determines the LTC6802-2 address. REG Port in the Applications Information section. See LTC6802-2 Address Commands in the Serial Port subsection of the Applications Information section. block DiagraM 1 V+ 2 C12 REGULATOR VREG 31 10k S12 3 WATCHDOG WDTB 34 TIMER C11 4 A3 40 A2 39 10k A1 38 21 S3 12 RESULTS A0 37 MUX ∆∑ A/D CONVERTER REGISTER CSBI AND 44 22 C2 COMMUNICATIONS SDO 43 10k SDI 42 S2 23 SCKI 41 C1 24 REFERENCE GPIO2 36 10k GPIO1 S1 35 25 CONTROL MMB 33 V– TOS 26 32 10Ω NC 27 DIE EXTERNAL TEMP TEMP VTEMP1 VTEMP2 VREF 28 29 30 68022BD 68022fa 

LTC6802-2 TiMing DiagraM Timing Diagram of the Serial Interface t1 t4 t6 t2 t3 t7 SCKI SDI D3 D2 D1 D0 D7… D4 D3 t5 CSBI t8 SDO D4 D3 D2 D1 D0 D7… D4 D3 PREVIOUS COMMAND CURRENT COMMAND 68022TD operaTion THEORY OF OPERATION the LTC6802-2 makes no decisions about turning on/off the internal MOSFETs. This is completely controlled by The LTC6802-2 is a data acquisition IC capable of mea- the host processor. The host processor writes values to a suring the voltage of 12 series connected battery cells. configuration register inside the LTC6802-2 to control the An input multiplexer connects the batteries to a 12-bit switches. The watchdog timer on the LTC6802-2 can be delta-sigma analog to digital converter (ADC). An internal used to turn off the discharge switches if communication 5ppm voltage reference combined with the ADC give the with the host processor is interrupted. LTC6802-2 its outstanding measurement accuracy. The inherent benefits of the delta-sigma ADC vs other types of ADCs (e.g. successive approximation) are explained OPEN-CONNECTION DETECTION in Advantages of Delta-Sigma ADCs in the Applications When a cell input (C pin) is open, it affects 2-cell measure- Information section. ments. Figure 2 shows an open connection to C3, in an Communication between the LTC6802-2 and a host pro- application without external filtering between the C pins and cessor is handled by a SPI compatible serial interface. the cells. During normal ADC conversions (that is, using Multiple LTC6802-2s can be connected to a single serial the STCVAD command), the LTC6802 will give near zero interface. This is shown in Figure 1. The LTC6802-2s are readings for B3 and B4 when C3 is open. The zero reading isolated from one another using digital isolators. A unique for B3 occurs because during the measurement of B3, addressing scheme allows all LTC6802-2s to connect to the the ADC input resistance will pull C3 to the C2 potential. same serial port of the host processor. Further explanation Similarly, during the measurement of B4, the ADC input of the LTC6802-2 can be found in the Serial Port section resistance pulls C3 to the C4 potential. of the data sheet. Figure 3 shows an open connection at the same point in The LTC6802-2 also contains circuitry to balance cell volt- the cell stack as Figure 2, but this time there is an external ages. Internal MOSFETs can be used to discharge cells. filter network still connected to C3. Depending on the value These internal MOSFETs can also be used to control external of the capacitor remaining on C3, a normal measurement balancing circuits. Figure 1 illustrates cell balancing by of B3 and B4 may not give near zero readings, since the internal discharge. Figure 4 shows the S pin controlling C3 pin is not truly open. In fact, with a large external ca- an external balancing circuit. It is important to note that pacitance on C3, the C3 voltage will be charged midway 68022fa 0

LTC6802-2 operaTion IC #3 TO IC #7 BATTERY V2– V1– POSITIVE V2– V1– LTC6802-2 OE2 OE1 350V LTC6802-2 OE2 OE1 V+ IC #2 CSBI V+ IC #8 CSBI + C12 SDO + C12 SDO S12 SDI S12 SDI C11 SCKI C11 SCKI + S11 A3 V2– V1– + S11 A3 V2– V1– C10 A2 ADDRESS 1 V2+ V1+ 3V C10 A2 ADDRESS 15 V2+ V1+ 3V + + S10 A1 DIGITAL S10 A1 DIGITAL C9 A0 ISOLATOR C9 A0 ISOLATOR + + S9 GPIO2 S9 GPIO2 + C8 GPIO1 + C8 GPIO1 S8 WDTB S8 WDTB + C7 MMB + C7 MMB S7 TOS S7 TOS + C6 VREG + C6 VREG S6 VREF S6 VREF + C5 VTEMP2 + C5 VTEMP2 S5 VTEMP1 S5 VTEMP1 C4 NC C4 NC + S4 V– + S4 V– + C3 S1 + C3 S1 S3 C1 S3 C1 + C2 S2 + C2 S2 + + V2– V1– 3V LTC6802-2 OE2 OE1 V+ IC #1 CSBI MISO MPU MODULE + C12 SDO CS IO S12 SDI MOSI + C11 SCKI CLK S11 A3 V2– V1– + C10 A2 ADDRESS 0 V2+ V1+ 3V S10 A1 DIGITAL + C9 A0 ISOLATOR S9 GPIO2 + C8 GPIO1 S8 WDTB + C7 MMB S7 TOS + C6 VREG S6 VREF + C5 VTEMP2 S5 VTEMP1 + C4 NC S4 V– + C3 S1 S3 C1 + C2 S2 + 68022 F01 Figure 1. 96-Cell Battery Stack, Isolated Interface. In this Diagram the Battery Negative is Isolated from Module Ground. Opto-Couplers or Digital Isolators Allow Each IC to be Addressed Individually. This is a Simplified Schematic Showing the Basic Multi-IC Architecture between C2 and C4 after several cycles of measuring cells turned on during all cell conversions. Referring again to B3 and B4. Thus the measurements for B3 and B4 may Figure 3, with the STOWAD command, the C3 pin will be indicate a valid cell voltage when in fact the exact state of pulled down by the 100µA current source during the B3 B3 and B4 is unknown. cell measurement AND during the B4 cell measurement. This will tend to decrease the B3 measurement result and To reliably detect an open connection, the command increase the B4 measurement result relative to the normal STOWAD is provided. With this command, two 100µA STCVAD command. The biggest change is observed in the current sources are connected to the ADC inputs and 68022fa 

LTC6802-2 operaTion 4. Issue a RDCV command and store all cell measurements LTC6802-2 into array CELLB(n). C4 5. For each value of n from 1 to 11: + B4 C3 If CELLB(n + 1) – CELLA(n + 1) ≥ +200mV, + B3 MUX C2 then Cn is open, otherwise it is not open. + C1 The 200mV threshold is chosen to provide tolerance for + errors in the measurement with the 100µA current source V– 100µA connected. Even without an open connection there is al- ways some difference between a cell measured with and without the 100µA current source because of the IR drop 68022 F02 across the finite resistance of the MUX switches. On the Figure 2. Open Connection other hand, with capacitors larger then 0.1µF remaining on an otherwise open C pin, the 100µA current source may not be enough to move the open C pin 200mV with LTC6802-2 a single STOWAD command. If the STOWAD command + is repeated several times, the large external capacitor C4 + will discharge enough to create a 200mV change in cell B4 CF4 C3 readings. To detect an open connection with larger then + B3 CF3 MUX 0.1µF capacitance still on the pin, one must repeat step 3 C2 + a number of times before proceeding to step 4. C1 + The algorithm above determines if the Cn pin is open V– based on measurements of the n + 1 cell. For example, 100µA in a 12-cell system, the algorithm finds opens on Pins C1 through C11 by looking at the measurements of cells B2 through B12. Therefore the algorithm can not be used to 68022 F03 determine if the topmost C pin is open. Fortunately, an open Figure 3. Open Connection with RC Filtering wire from the battery to the top C pin usually means the V+ B4 measurement when C3 is open. So, the best method to pin is also floating. When this happens, the readings for detect an open wire at input C3 is to look for an increase the top battery cell will always be 0V, indicating a failure. in the measurement of the cell connected between inputs If the top C pin is open yet V+ is still connected, then the C3 and C4 (cell B4). best way to detect an open connection to the top C pin is by comparing the sum of all cell measurements using Thus the following algorithm can be used to detect an the STCVAD command to an auxiliary measurement of the open connection to cell pin Cn: sum of all the cells, using a method similar to that shown 1. Issue a STCVAD command (ADC convert without 100µA in Figure 15. A significantly lower result for the calculated current sources). sum of all 12 cells suggests an open connection to the top 2. Issue a RDCV command and store all cell measurements C pin, provided it was already determined that no other into array CELLA(n). C pin is open. 3. Issue a STOWAD command (ADC convert with 100µA current sources). 68022fa 

LTC6802-2 operaTion DISCHARGING DURING CELL MEASUREMENTS The primary cell voltage A/D measurement commands Cn SI2351DS (STCVAD and STOWAD) automatically turn off a cell’s MM3Z12VT1 + discharge switch while its voltage is being measured. The 15Ω 3.3k discharge switches for the cell above and the cell below will 1W Sn VISHAY CRCW2512 SERIES also be turned off during the measurement. For example, Cn – 1 68022 F04 discharge switches S4, S5, and S6 will be disabled while cell 5 is being measured. Figure 4. External Discharge FET Connection (One Cell Shown) In some systems it may be desirable to allow discharging to continue during cell voltage measurements. The cell POWER DISSIPATION AND THERMAL SHUTDOWN voltage A/D conversion commands STCVDC and STOWDC allow any enabled discharge switches to remain on during The MOSFETs connected to the Pins S1 through S12 can be cell voltage measurements. This feature allows the system used to discharge battery cells. An external resistor should to perform a self test to verify the discharge functionality be used to limit the power dissipated by the MOSFETs. The and multiplexer operation. maximum power dissipation in the MOSFETs is limited by the amount of heat that can be tolerated by the LTC6802-2. All discharge switches are automatically disabled during Excessive heat results in elevated die temperatures. The OV and UV comparison measurements. electrical characteristics are guaranteed for die tempera- tures up to 85°C. Little or no degradation will be observed A/D CONVERTER DIGITAL SELF TEST in the measurement accuracy for die temperatures up Two self-test commands can be used to verify the func- to 105°C. Damage may occur near 150°C, therefore the tionality of the digital portions of the ADC. The self tests recommended maximum die temperature is 125°C. also verify the cell voltage registers and cell temperature To protect the LTC6802-2 from damage due to overheating, registers. During these self tests a test signal is applied a thermal shutdown circuit is included. Overheating of the to the ADC. If the circuitry is working properly the cell device can occur when dissipating significant power in the voltage or cell temperature registers will contain identi- cell discharge switches. The problem is exacerbated when cal codes. For self test 1 the registers will contain 0x555. operating with a large voltage between V+ and V– or when For self test 2, the registers will contain 0xAAA. The time the thermal conductivity of the system is poor. required for the self-test function is the same as required If the temperature detected on the device goes above ap- to measure all cell voltages or all temperature sensors. proximately 145°C, the configuration registers will be reset Perform the self-test function with CDC[2:0] set to 1 in to default states, turning off all discharge switches and the configuration register. disabling A/D conversions. When a thermal shutdown has occurred, the THSD bit in the temperature register group USING THE S PINS AS DIGITAL OUTPUTS OR will go high. The bit is cleared by performing a read of the GATE DRIVERS temperature registers (RDTMP command). The S outputs include an internal 10k pull-up resistor. Since thermal shutdown interrupts normal operation, the Therefore the S pins will behave as a digital output when internal temperature monitor should be used to determine loaded with a high impedance, e.g., the gate of an external when the device temperature is approaching unacceptable MOSFET. For applications requiring high battery discharge levels. currents, connect a discrete PMOS switch device and suit- able discharge resistor to the cell, and the gate terminal to the S output pin, as illustrated in Figure 4. 68022fa 

LTC6802-2 applicaTions inForMaTion USING THE LTC6802-2 WITH LESS THAN 12 CELLS USING THE GENERAL PURPOSE INPUTS/OUTPUTS (GPIO1, GPIO2) The LTC6802-2 can typically be used with as few as 4 cells. The minimum number of cells is governed by the supply The LTC6802-2 has two general purpose digital inputs/out- voltage requirements of the LTC6802-2. The sum of the puts. By writing a GPIO configuration register bit to a logic cell voltages must be 10V to guarantee that all electrical low, the open-drain output can be activated. The GPIOs specifications are met. give the user the ability to turn on/off circuitry around the LTC6802-2. One example might be a circuit to verify the Figure 5 shows an example of the LTC6802-2 when used to operation of the system. monitor 7 cells. The lowest C inputs connect to the 7 cells and the upper C inputs connect to V+. Other configura- When a GPIO configuration bit is written to a logic high, tions, e.g., 9 cells, would be configured in the same way: the corresponding GPIO pin may be used as an input. the lowest C inputs connected to the battery cells and the The read back value of that bit will be the logic level that unused C inputs connected to V+. The unused inputs will appears at the GPIO pin. result in a reading of 0V for those channels. When the MMB pin is low, the GPIO pins and the WDTB The ADC can also be commanded to measure a stack of pin are treated as inputs that set the number of cells to cells by making 10 or 12 measurements, depending on the be monitored. See the Monitor Mode section. state of the CELL10 bit in the control register. Data from all 10 or 12 measurements must be downloaded when read- WATCHDOG TIMER CIRCUIT ing the conversion results. The ADC can be commanded The LTC6802-2 includes a watchdog timer circuit. If no to measure any individual cell voltage. activity is detected on the SCKI pin for 2.5 seconds, the WDTB open-drain output is asserted low. The WDTB pin NEXT HIGHER GROUP OF 7 CELLS remains low until an edge is detected on the SCKI pin. LTC6802-2 V+ When the watchdog timer circuit times out, the configura- C12 S12 tion bits are reset to their default (power-up) state. C11 S11 In the power-up state, the S outputs are off. Therefore, the C10 watchdog timer provides a means to turn off cell discharg- S10 C9 ing should communications to the MPU be interrupted. S9 The IC is in the minimum power standby mode after a C8 time out. Note that externally pulling the WDTB pin low S8 C7 will not reset the configuration bits. + S7 C6 The watchdog timer operation is disabled when MMB + S6 is low. C5 + S5 When reading the configuration register, byte CFG0 bit 7 C4 + S4 will reflect the state of the WDTB pin. C3 + S3 REVISION CODE C2 + S2 The temperature register group contains a 3-bit revision + C1 code. If software detection of device revision is neces- S1 V− sary, then contact the factory for details. Otherwise, the code can be ignored. In all cases, however, the values of NEXT LOWER GROUP OF 7 CELLS 68022 F05 all bits must be used when calculating the packet error code (PEC) CRC byte on data reads. Figure 5. Monitoring 7 Cells with the LTC6802-2 68022fa 

LTC6802-2 applicaTions inForMaTion MODES OF OPERATION If fewer than 12 cells are connected to the LTC6802-2 then it is necessary to mask the unused input channels. The LTC6802-2 has three modes of operation: standby, The MCxI bits in the configuration registers are used to measure and monitor. Standby mode is a power saving state mask channels. If the CELL10 bit is high, then the inputs where all circuits except the serial interface are turned off. for cells 11 and 12 are automatically masked. In measure mode, the LTC6802-2 is used to measure cell voltages and store the results in memory. Measure mode The LTC6802-2 can monitor UV and OV conditions con- will also monitor each cell voltage for overvoltage (OV) tinuously. Alternatively, the duty cycle of the UV and OV and undervoltage (UV) conditions. In monitor mode, the comparisons can be reduced or turned off to lower the device will only monitor cells for UV and OV conditions. overall power consumption. The CDC bits are used to A signal is output on the SDO pin to indicate the UV/OV control the duty cycle. status. The serial interface is disabled. To initiate cell voltage measurements while in measure mode, a Start A/D Conversion and Poll Status command Standby Mode must be sent. After the command has been sent, the The LTC6802-2 defaults (powers up) to standby mode. LTC6802-2 will send the A/D converter status using either Standby mode is the lowest possible supply current state. the toggle polling or the level polling method, as described All circuits are turned off except the serial interface and in the Serial Port section. If the CELL10 bit is high, then the voltage regulator. The LTC6802-2 can be programmed only the bottom 10 cell voltages will be measured, thereby for standby mode by setting configuration bits CDC[2:0] reducing power consumption and measurement time. By to 0. If the part is put into standby mode while ADC default the CELL10 bit is low, enabling measurement of all measurements are in progress, the measurements will 12 cell voltages. During cell voltage measurement com- be interrupted and the cell voltage registers will be in an mands, UV and OV flag conditions, reflected in the flag indeterminate state. To exit standby mode, the CDC bits register group, are also updated. When the measurements must be written to a value other than 0. are complete, the part will go back to monitoring UV and OV conditions at the rate designated by the CDC bits. Measure Mode Monitor Mode The LTC6802-2 is in measure mode when the CDC bits are programmed with a value from 1 to 7. The IC monitors The LTC6802-2 can be used as a simple monitoring circuit each cell voltage and produces an interrupt signal on the with no serial interface by pulling the MMB pin low. When SDO pin indicating all cell voltages are within the UV and in this mode, the interrupt status is indicated on the SDO OV limits. There are two methods for indicating the UV/OV pin using the toggle polling mode described in the Serial interrupt status: toggle polling (using a 1kHz output signal) Port section. Unlike serial port polling commands, however, and level polling (using a high or low output signal). The the toggling is independent of the state of the CSBI pin. polling methods are described in the Serial Port section. When the MMB pin is low, all the device configuration The UV/OV limits are set by the VUV and VOV values in values are reset to the default states shown in Table 15 the configuration registers. When a cell voltage exceeds Memory Bit Descriptions. When MMB is held low the the UV/OV limits a bit is set in the flag register. The UV VUV, VOV, and CDC register values are ignored. Instead and OV flag status for each cell can be determined using VUV and VOV use factory-programmed setings. CDC is the Read Flag Register Group. set to state 5. The number of cells to be monitored is set by the logic levels on the WDTB and GPIO pins, as shown in Table 1. 68022fa 

LTC6802-2 applicaTions inForMaTion (logic high) for polling commands. All interface pins are Table 1. Monitor Mode Cell Selection voltage mode, with voltage levels sensed with respect to WDTB GPIO2 GPIO1 CELL INPUTS MONITORED the V– supply. See Figure 1. 0 0 0 Cells 1 to 5 0 0 1 Cells 1 to 6 Data Link Layer 0 1 0 Cells 1 to 7 0 1 1 Cells 1 to 8 Clock Phase And Polarity: The LTC6802-2 SPI compat- ible interface is configured to operate in a system using 1 0 0 Cells 1 to 9 CPHA = 1 and CPOL = 1. Consequently, data on SDI must 1 0 1 Cells 1 to 10 be stable during the rising edge of SCKI. 1 1 0 Cells 1 to 11 1 1 1 Cells 1 to 12 Data Transfers: Every byte consists of 8 bits. Bytes are transferred with the most significant bit (MSB) first. On a write, the data value on SDI is latched into the device on If MMB is low then brought high, all device configuration the rising edge of SCKI (Figure 6). Similarly, on a read, values are reset to the default states including the VUV, the data value output on SDO is valid during the rising VOV, and CDC configuration bits. edge of SCKI and transitions on the falling edge of SCKI (Figure 7). SERIAL PORT CSBI must remain low for the entire duration of a com- Overview mand sequence, including between a command byte and subsequent data. On a write command, data is latched in The LTC6802-2 has an SPI bus compatible serial port. on the rising edge of CSBI. Devices can be connected in parallel, using digital isolators. Multiple devices are uniquely identified by a part address After a polling command has been entered, the SDO output determined by the A0 to A3 pins. will immediately be driven by the polling state, with the SCKI input ignored (Figure 8). See the Toggle Polling and Physical Layer Level Polling sections. On the LTC6802-2, four pins comprise the serial interface: Network Layer CSBI, SCKI, SDI and SDO. The SDO and SDI may be tied Broadcast Commands: A broadcast command is one to together, if desired, to form a single, bidirectional port. which all devices on the bus will respond, regardless of Four address pins (A0 to A3) set the part address for ad- device address. See the Bus Protocols and Commands dress commands. The TOS pin designates the top device sections. CSBI SCKI SDI MSB (CMD) BIT6 (CMD) LSB (CMD) MSB (DATA) LSB (DATA) 68022 F06 Figure 6. Transmission Format (Write) 68022fa 

LTC6802-2 applicaTions inForMaTion CSBI SCKI SDI MSB (CMD) BIT6 (CMD) LSB (CMD) SDO MSB (DATA) LSB (DATA) 68022 F07 Figure 7. Transmission Format (Read) CSBI SCKI SDI MSB (CMD) BIT6 (CMD) LSB (CMD) SDO POLL STATE 68022 F08 Figure 8. Transmission Format (Poll) With broadcast commands all devices can be sent com- PEC Byte: The packet error code (PEC) byte is a CRC mands simultaneously. This is useful for A/D conversion value calculated for all of the bits in a register group in and polling commands. It can also be used with write the order they are read, using the following characteristic commands when all parts are being written with the same polynomial: data. Broadcast read commands should not be used in x8 + x2 + x + 1 the parallel configuration. On a read command, after sending the last byte of a reg- Address Commands: An address command is one in ister group, the device will shift out the calculated PEC, which only the addressed device on the bus responds. MSB first. The first byte of an address command consists of 4 bits with a value of 1000 and 4 address bits. The second byte Toggle Polling: Toggle polling allows a robust determina- is the command byte. See the Bus Protocols and Com- tion both of device states and of the integrity of the con- mands section. nections between the devices in a stack. Toggle polling 68022fa 

LTC6802-2 applicaTions inForMaTion is enabled when the LVLPL bit is low. After entering a Level polling—Parallel Broadcast Polling: No part address polling command, the data out line will be driven by the is sent, so all devices respond simultaneously. If a device slave devices based on their status. When polling for the is busy/in interrupt, it will pull SDO low. If a device is not A/D converter status, data out will be low when any device busy/not in interrupt, then it will release the SDO line. If is busy performing an A/D conversion and will toggle at any device is busy or in interrupt the SDO signal will be 1kHz when no device is busy. Similarly, when polling for low. If all devices are not busy/not in interrupt, the SDO interrupt status, the output will be low when any device signal will be high. has an interrupt condition and will toggle at 1kHz when The master controller pulls CSBI high to exit polling. none has an interrupt condition. Polling Methods: For A/D conversions, three methods can Toggle Polling—Address Polling: The addressed device be used to determine A/D completion. First, a controller can drives the SDO line based on its state alone—low for start an A/D conversion and wait for the specified conver- busy/in interrupt, toggling at 1kHz for not busy/not in sion time to pass before reading the results. The second interrupt. method is to hold CSBI low after an A/D start command Toggle Polling—Parallel Broadcast Polling: No part has been sent. The A/D conversion status will be output address is sent, so all devices respond simultaneously. on SDO. A problem with the second method is that the If a device is busy/in interrupt, it will pull SDO low. If a controller is not free to do other serial communication device is not busy/not in interrupt, then it will release the while waiting for A/D conversions to complete. The third SDO line (TOS = 0) or attempt to toggle the SDO line at method overcomes this limitation. The controller can send 1kHz (TOS =1). an A/D start command, perform other tasks, and then send a Poll A/D Converter Status (PLADC) command to The master controller pulls CSBI high to exit polling. determine the status of the A/D conversions. Level polling: Level polling is enabled when the LVLPL For OV/UV interrupt status, the poll interrupt status (PLINT) bit is high. After entering a polling command, the data command can be used to quickly determine whether out line will be driven by the slave devices based on their any cell in a stack is in an overvoltage or undervoltage status. When polling for the A/D converter status, data condition. out will be low when any device is busy performing an A/D conversion and will be high when no device is busy. Bus Protocols Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will There are 6 different protocol formats, depicted in Table 3 be high when none has an interrupt condition. through Table 8. Table 2 is the key for reading the protocol diagrams. Level polling—Address Polling: The addressed device drives the SDO line based on its state alone—pulled low for busy/in interrupt, released for not busy/not in interrupt. 68022fa 

LTC6802-2 applicaTions inForMaTion Table 2. Protocol Key PEC Packet error code (CRC-8) Master-to-slave N Number of bits Slave-to-master … Continuation of protocol Complete byte of data Table 3. Broadcast Poll Command 8 Command Poll Data Table 4. Broadcast Read 8 8 8 8 Command Data Byte Low … Data Byte High PEC Table 5. Broadcast Write 8 8 8 Command Data Byte Low … Data Byte High Table 6. Address Poll Command 4 4 8 1000 Address Command Poll Data Table 7. Address Read 4 4 8 8 8 8 1000 Address Command Data Byte Low … Data Byte High PEC Table 8. Address Write 4 4 8 8 8 1000 Address Command Data Byte Low … Data Byte High 68022fa 

LTC6802-2 applicaTions inForMaTion Commands Table 9. Command Codes Write Configuration Register Group WRCFG 0x01 Read Configuration Register Group RDCFG 0x02 Read Cell Voltage Register Group RDCV 0x04 Read Flag Register Group RDFLG 0x06 Read Temperature Register Group RDTMP 0x08 Start Cell Voltage A/D Conversions and Poll Status STCVAD 0x10 (all cell voltage inputs) 0x11 (cell 1 only) 0x12 (cell 2 only) … 0x1A (cell 10 only) 0x1B (cell 11 only, if CELL10 bit=0) 0x1C (cell 12 only, if CELL10 bit=0) 0x1D (unused) 0x1E (cell self test 1; all CV=0x555) 0x1F (cell self test 2; all CV=0xAAA) Start Open-Wire A/D Conversions and Poll Status STOWAD 0x20 (all cell voltage inputs) 0x21 (cell 1 only) 0x22 (cell 2 only) … 0x2A (cell 10 only) 0x2B (cell 11 only, if CELL10 bit=0) 0x2C (cell 12 only, if CELL10 bit=0) 0x2D (unused) 0x2E (cell self test 1; all CV=0x555) 0x2F (cell self test 2; all CV=0xAAA) Start Temperature A/D Conversions and Poll Status STTMPAD 0x30 (all temperature inputs) 0x31 (external temp 1 only) 0x32 (external temp 2 only) 0x33 (internal temp only) 0x34—0x3D (unused) 0x3E (temp self test 1; all TMP=0x555) 0x3F (temp self test 2; all TMP=0xAAA) Poll A/D Converter Status PLADC 0x40 Poll Interrupt Status PLINT 0x50 Start Cell Voltage A/D Conversions and Poll Status, with STCVDC 0x60 (all cell voltage inputs) Discharge Permitted 0x61 (cell 1 only) 0x62 (cell 2 only) … 0x6A (cell 10 only) 0x6B (cell 11 only, if CELL10 bit=0) 0x6C (cell 12 only, if CELL10 bit=0) 0x6D (unused) 0x6E (cell self test 1; all CV=0x555) 0x6F (cell self test 2; all CV=0xAAA) Start Open-Wire A/D Conversions and Poll Status, with STOWDC 0x70 (all cell voltage inputs) Discharge Permitted 0x71 (cell 1 only) 0x72 (cell 2 only) … 0x7A (cell 10 only) 0x7B (cell 11 only, if CELL10 bit=0) 0x7C (cell 12 only, if CELL10 bit=0) 0x7D (unused) 0x7E (cell self test 1; all CV=0x555) 0x7F (cell self test 2; all CV=0xAAA) 68022fa 0

LTC6802-2 applicaTions inForMaTion Memory Map Table 10 through Table 15 show the memory map for the LTC6802-2. Table 15 gives bit descriptions. Table 10. Configuration (CFG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CFGR0 RD/WR WDT GPIO2 GPIO1 LVLPL CELL10 CDC[2] CDC[1] CDC[0] CFGR1 RD/WR DCC8 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 CFGR2 RD/WR MC4I MC3I MC2I MC1I DCC12 DCC11 DCC10 DCC9 CFGR3 RD/WR MC12I MC11I MC10I MC9I MC8I MC7I MC6I MC5I CFGR4 RD/WR VUV[7] VUV[6] VUV[5] VUV[4] VUV[3] VUV[2] VUV[1] VUV[0] CFGR5 RD/WR VOV[7] VOV[6] VOV[5] VOV[4] VOV[3] VOV[2] VOV[1] VOV[0] Table 11. Cell Voltage (CV) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CVR00 RD C1V[7] C1V[6] C1V[5] C1V[4] C1V[3] C1V[2] C1V[1] C1V[0] CVR01 RD C2V[3] C2V[2] C2V[1] C2V[0] C1V[11] C1V[10] C1V[9] C1V[8] CVR02 RD C2V[11] C2V[10] C2V[9] C2V[8] C2V[7] C2V[6] C2V[5] C2V[4] CVR03 RD C3V[7] C3V[6] C3V[5] C3V[4] C3V[3] C3V[2] C3V[1] C3V[0] CVR04 RD C4V[3] C4V[2] C4V[1] C4V[0] C3V[11] C3V[10] C3V[9] C3V[8] CVR05 RD C4V[11] C4V[10] C4V[9] C4V[8] C4V[7] C4V[6] C4V[5] C4V[4] CVR06 RD C5V[7] C5V[6] C5V[5] C5V[4] C5V[3] C5V[2] C5V[1] C5V[0] CVR07 RD C6V[3] C6V[2] C6V[1] C6V[0] C5V[11] C5V[10] C5V[9] C5V[8] CVR08 RD C6V[11] C6V[10] C6V[9] C6V[8] C6V[7] C6V[6] C6V[5] C6V[4] CVR09 RD C7V[7] C7V[6] C7V[5] C7V[4] C7V[3] C7V[2] C7V[1] C7V[0] CVR10 RD C8V[3] C8V[2] C8V[1] C8V[0] C7V[11] C7V[10] C7V[9] C7V[8] CVR11 RD C8V[11] C8V[10] C8V[9] C8V[8] C8V[7] C8V[6] C8V[5] C8V[4] CVR12 RD C9V[7] C9V[6] C9V[5] C9V[4] C9V[3] C9V[2] C9V[1] C9V[0] CVR13 RD C10V[3] C10V[2] C10V[1] C10V[0] C9V[11] C9V[10] C9V[9] C9V[8] CVR14 RD C10V[11] C10V[10] C10V[9] C10V[8] C10V[7] C10V[6] C10V[5] C10V[4] CVR15* RD C11V[7] C11V[6] C11V[5] C11V[4] C11V[3] C11V[2] C11V[1] C11V[0] CVR16* RD C12V[3] C12V[2] C12V[1] C12V[0] C11V[11] C11V[10] C11V[9] C11V[8] CVR17* RD C12V[11] C12V[10] C12V[9] C12V[8] C12V[7] C12V[6] C12V[5] C12V[4] *Registers CVR15, CVR16, and CVR17 can only be read if the CELL10 bit in register CFGR0 is low. 68022fa 

LTC6802-2 applicaTions inForMaTion Table 12. Flag (FLG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FLGR0 RD C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV FLGR1 RD C8OV C8UV C7OV C7UV C6OV C6UV C5OV C5UV FLGR2 RD C12OV* C12UV* C11OV* C11UV* C10OV C10UV C9OV C9UV *Bits C11UV, C12UV, C11OV, and C12OV are always low if the CELL10 bit in register CFGR0 is high. Table 13. Temperature (TMP) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TMPR0 RD ETMP1[7] ETMP1[6] ETMP1[5] ETMP1[4] ETMP1[3] ETMP1[2] ETMP1[1] ETMP1[0] TMPR1 RD ETMP2[3] ETMP2[2] ETMP2[1] ETMP2[0] ETMP1[11] ETMP1[10] ETMP1[9] ETMP1[8] TMPR2 RD ETMP2[11] ETMP2[10] ETMP2[9] ETMP2[8] ETMP2[7] ETMP2[6] ETMP2[5] ETMP2[4] TMPR3 RD ITMP[7] ITMP[6] ITMP[5] ITMP[4] ITMP[3] ITMP[2] ITMP[1] ITMP[0] TMPR4 RD REV[2] REV[1] REV[0] THSD ITMP[11] ITMP[10] ITMP[9] ITMP[8] Table 14. Packet Error Code (PEC) REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PEC RD PEC[7] PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[0] 68022fa 

LTC6802-2 applicaTions inForMaTion Table 15. Memory Bit Descriptions NAME DESCRIPTION VALUES UV/OV COMPARATOR V POWERED DOWN CELL VOLTAGE REF CDC PERIOD BETWEEN MEASUREMENTS MEASUREMENT TIME 0 N/A (Comparator Off) Yes N/A (default) Standby Mode 1 N/A (Comparator Off) No 13ms 2 13ms No 13ms CDC Comparator Duty Cycle 3 130ms No 13ms 4 500ms No 13ms 5* 130ms Yes 21ms 6 500ms Yes 21ms 7 2000ms Yes 21ms *when MMB pin is low, the CDC value is set to 5 CELL10 10-Cell Mode 0=12-cell mode (default); 1=10-cell mode LVLPL Level Polling Mode 0=toggle polling (default); 1=level polling Write: 0=GPIO1 pin pull down on; 1=GPIO1 pin pull down off (default) GPIO1 GPIO1 Pin Control Read: 0=GPIO1 pin at logic ‘0’; 1=GPIO1 pin at logic ‘1’ Write: 0=GPIO2 pin pull down on; 1=GPIO2 pin pull down off (default) GPIO2 GPIO2 Pin Control Read: 0=GPIO2 pin at logic ‘0’; 1=GPIO2 pin at logic ‘1’ WDT Watchdog Timer Read Only: 0=WDTB pin at logic ‘0’; 1=WDTB pin at logic ‘1’ DCCx Discharge Cell x x=1..12 0=turn off shorting switch for cell ‘x’ (default); 1=turn on shorting switch Comparison voltage = VUV * 16 * 1.5mV VUV Undervoltage Comparison Voltage* (default VUV=0. When MMB pin is low a factory programmed comparison voltage is used) Comparison voltage = VOV * 16 * 1.5mV VOV Overvoltage Comparison Voltage* (default VOV=0. When MMB pin is low a factory programmed comparison voltage is used) x=1..12 0=enable interrupts for cell ‘x’ (default) MCxI Mask Cell x Interrupts 1=turn off interrupts and clear flags for cell ‘x’ x=1..12 12-bit ADC measurement value for cell ‘x’ CxV Cell x Voltage* cell voltage for cell ‘x’ = CxV * 1.5mV reads as 0xFFF while A/D conversion in progress x=1..12 cell voltage compared to VUV comparison voltage CxUV Cell x Undervoltage Flag 0=cell ‘x’ not flagged for under voltage condition; 1=cell ‘x’ flagged x=1..12 cell voltage compared to VOV comparison voltage CxOV Cell x Overvoltage Flag 0=cell ‘x’ not flagged for over voltage condition; 1=cell ‘x’ flagged ETMPx External Temperature Measurement* Temperature measurement voltage = ETMPx * 1.5mV 0= thermal shutdown has not occurred; 1=thermal shutdown has occurred THSD Thermal Shutdown Status Status cleared to ‘0’ on read of Thermal Register Group REV Revision Code Device revision code ITMP Internal Temperature Measurement* Temperature measurement voltage = ITMP * 1.5mV = 8mV * T(°K) PEC Packet Error Code CRC value for reads *Voltage determinations use the decimal value of the registers, 0 to 4095 for 12-bit and 0 to 255 for 8-bit registers. 68022fa 

LTC6802-2 applicaTions inForMaTion SERIAL COMMAND Example for LTC6802-2 (Addressable Configuration) Examples below use a configuration of three stacked devices: bottom (B), middle (M), and top (T) Write Configuration Registers (Broadcast Command) 1. Pull CSBI low 2. Send WRCFG command byte 3. Send CFGR0 byte, then CFGR1, CFGR2, … CFGR5 (All devices on bus receive same data) 4. Pull CSBI high; data latched into all devices on rising edge of CSBI Calculation of serial interface time for sequence above: Number of devices in stack= N Number of bytes in sequence = B = 1 command byte and 6 data bytes Serial port frequency per bit = F Time = (1/F) * B * 8 bits/byte = (1/F) * (1+6) * 8 Time for 3 cell stacks example above, with 1MHz serial port = (1/1000000) * (1+6)*8 = 56us Read Cell Voltage Registers (Address Command) 1. Pull CSBI low 2. Send Address byte for bottom device 3. Send RDCV command byte 4. Read CVR00 byte of bottom device, then CVR01 (B), CVR02 (B), … CVR17 (B), and then PEC (B) 5. Pull CSBI high 6. Repeat steps 1-5 for middle device and top device Calculation of serial interface time for sequence above: Number of devices in stack= N Number of bytes in sequence = B = 1 address, 1 command, 18 register, and 1 PEC byte per device = 21*N Serial port frequency per bit = F Time = (1/F) * B * 8 bits/byte = (1/F) * (21*N) * 8 Time for 3-cell stacks example above, with 1MHz serial port = (1/1000000) * (21*3)*8 = 504us Start Cell Voltage A/D Conversions and Poll Status (Broadcast Command with Toggle Polling) 1. Pull CSBI low 2. Send STCVAD command byte (all devices in stack start A/D conversions simultaneously) 3. SDO output of all devices in parallel pulled low for approximately 12ms 4. SDO output toggles at 1kHz rate, indicating conversions complete for all devices 5. Pull CSBI high to exit polling 68022fa 

LTC6802-2 applicaTions inForMaTion Poll Interrupt Status (Level Polling) 1. Pull CSBI low 2. Send Address byte for bottom device 3. Send PLINT command byte 4. SDO output from bottom device pulled low if any device has an interrupt condition; otherwise, SDO high 5. Pull CSBI high to exit polling 6. Repeat steps 1-5 for middle device and top device FAULT PROTECTION battery system during its useful lifespan. Table 16 shows the various situations that should be considered when plan- Overview ning protection circuitry. The first five scenarios are to be anticipated during production and appropriate protection Care should always be taken when using high energy is included within the LTC6802-2 device itself. sources such as batteries. There are numerous ways that systems can be (mis-)configured that might affect a Table 16. LTC6802-2 Failure Mechanism Effect Analysis SCENARIO EFFECT DESIGN MITIGATION Cell input open circuit (random) Power-up sequence at IC inputs Clamp diodes at each pin to V+ and V– (within IC) provide alternate power path. Cell input open circuit (random) Differential input voltage overstress Zener diodes across each cell voltage input pair (within IC) limits stress. Top cell input connection loss (V+) Power will come from highest connected cell input Clamp diodes at each pin to V+ and V– (within IC) provide or via data port fault current alternate power path. Bottom cell input connection loss Power will come from lowest connected cell input Clamp diodes at each pin to V+ and V– (within IC) provide (V–) or via data port fault current alternate power path. Disconnection of a harness between Loss of supply connection to the IC Clamp diodes at each pin to V+ and V– (within IC) provide a group of battery cells and the IC an alternate power path if there are other devices (which can (in a system of stacked groups) supply power) connected to the LTC6802-2. Data link disconnection between Loss of serial communication (no stress to ICs). The device will enter standby mode within 2 seconds of LTC6802-2 and the master. disconnect. Discharge switches are disabled in standby mode. Cell-pack integrity, break between No effect during charge or discharge Use digital isolators to isolate the LTC6802-2 serial port from stacked units other LTC6802-2 serial ports. Cell-pack integrity, break within Cell input reverse overstress during discharge Add parallel Schottky diodes across each cell for load-path stacked unit redundancy. Diode and connections must handle full operating current of stack, will limit stress on IC Cell-pack integrity, break within Cell input positive overstress during charge Add SCR across each cell for charge-path redundancy. SCR stacked unit and connections must handle full charging current of stack, will limit stress on IC by selection of trigger Zener 68022fa 

LTC6802-2 applicaTions inForMaTion Internal Protection Diodes of 30V snapping back to 25V. The forward voltage drop of all Zeners is 0.5V. Refer to this diagram in the event of Each pin of the LTC6802-2 has protection diodes to help unpredictable voltage clamping or current flow. Limiting prevent damage to the internal device structures caused the current flow at any pin to ±10mA will prevent damage by external application of voltages beyond the supply rails to the IC. as shown in Figure 9. The diodes shown are conventional silicon diodes with a Cell-Voltage Filtering forward breakdown voltage of 0.5V. The unlabeled Zener The LTC6802-2 employs a sampling system to perform diode structures have a reverse-breakdown characteristic its analog-to-digital conversions and provides a conver- which initially breaks down at 12V then snaps back to a 7V sion result that is essentially an average over the 0.5ms clamping potential. The Zener diodes labeled Z are CLAMP conversion window, provided there isn’t noise aliasing with higher voltage devices with an initial reverse breakdown respect to the delta-sigma modulator rate of 512kHz. This indicates that a lowpass filter with useful attenuation at V+ LTC6802-2 500kHz may be beneficial. Since the delta-sigma integra- tion bandwidth is about 1kHz, the filter corner need not C12 be lower than this to assure accurate conversions. S12 Series resistors of 100Ω may be inserted in the input C11 paths without introducing meaningful measurement S11 error, provided only external discharge switch FETs are C10 ZCLAMP being used. Shunt capacitors may be added from the cell S10 inputs to V–, creating RC filtering as shown in Figure 10. C9 Note that this filtering is not compatible with use of the S9 internal discharge switches to carry current since this C8 would induce settling errors at the time of conversion as S8 any activated switches temporarily open to provide Kelvin mode cell sensing. As a discharge switch opens, cell wiring C7 S7 A3 resistance will also form a small voltage step (recovery C6 ZCLAMP A2 of the small IR drop), so keeping the frequency cutoff of the filter relatively high will allow adequate settling prior S6 A1 to the actual conversion. A guard time of about 60µs is C5 A0 provided in the ADC timing, so a 16kHz LP is optimal and S5 CSBI offers about 30dB of noise rejection. C4 SDO S4 SDI C3 SCKI Cn S3 VMODE 100Ω 100nF 6.2V C2 ZCLAMP GPIO2 + S2 GPIO1 Sn Cn – 1 C1 WDTB 100Ω 100nF S1 MMB 68021 F10 V– TOS Figure 10. Adding RC Filtering to the Cell Inputs (One Cell Connection Shown) 68022 F09 Figure 9. Internal Protection Diodes 68022fa 

LTC6802-2 applicaTions inForMaTion No resistor should be placed in series with the V– pin. in this case. Probe loads up to about 1mA maximum are Because the supply current flows from the V– pin, any supported in this configuration. Since V is shutdown REF resistance on this pin could generate a significant conver- during the LTC6802-2 idle and shutdown modes, the sion error for CELL1. thermistor drive is also shut off and thus power dissipa- tion minimized. Since V remains always on, the buffer REG op amp (LT6000 shown) is selected for its ultralow power READING EXTERNAL TEMPERATURE PROBES consumption (10µA). Using Dedicated Inputs Expanding Probe Count The LTC6802-2 includes two channels of ADC input, V TEMP1 The LTC6802-2 provides general purpose I/O pins, GPIO1 and V , that are intended to monitor thermistors TEMP2 and GPIO2, that may be used to control multiplexing of (tempco about –4%/°C generally) or diodes (–2.2mV/°C several temperature probes. Using just one of the GPIO typical) located within the cell array. Sensors can be pins, the sensor count can double to four as shown in powered directly from V as shown in Figure 11 (up to REF Figure 13. Using both GPIO pins, up to eight sensor inputs 60µA total). can be supported. For sensors that require higher drive currents, a buffer op amp may be used as shown in Figure 12. Power for the LTC6802-2 SN74LVC1G3157 sensor is actually sourced indirectly from the V pin OR SIMILAR DEVICE REG GPIO1 100k 100k LTC6802-2 100k VREG 100k 100k VREG 100k NTC VREF VREF 100k VTEMP2 VTEMP2 NTC VTEMNVPC1− 1µF 1N0T0Ck VTEMNVPC1− 1µF 1N0T0Ck 100k 1µF 100k NTC NTC 68022 F13 68022 F11 Figure 13. Expanding Sensor Count with Multiplexing Figure 11. Driving Thermistors Directly from V REF Using Diodes to Monitor Temperatures in Multiple Locations + Another method of multiple sensor support is possible LT6000 without the use of any GPIO pins. If the sensors are PN – diodes and several used in parallel, then the hottest diode will produce the lowest forward voltage and effectively LTC6802-2 establish the input signal to the V input(s). The hottest TEMP VREG 10k 10k diode will therefore dominate the readout from the VTEMP VREF inputs that the diodes are connected to. In this scenario, VTEMP2 VTEMP1 the specific location or distribution of heat is not known, NC 10k but such information may not be important in practice. V− NTC Figure 14 shows the basic concept. 10k NTC In any of the sensor configurations shown, a full-scale 68022 F12 cold readout would be an indication of a failed-open sen- Figure 12. Buffering V for Higher Current Sensors sor connection to the LTC6802-2. REF 68022fa 

LTC6802-2 applicaTions inForMaTion 200k total stack potential. This provides a redundant operational LTC6802-2 measurement of the cells in the event of a malfunction in VREG 200k VREF the normal acquisition process, or as a faster means of VTEMP2 monitoring the entire stack potential. Figure 15 shows VTEMP1 NC a means of providing both of these features. A resistor V− divider is used to provide a low voltage representation of the full stack potential (C12 to C0 voltage) with MOSFETs that decouple the divider current under unneeded condi- 68022 F14 tions. Other MOSFETs, in conjunction with an op amp Figure 14. Using Diode Sensors as Hot-Spot Detectors having a shutdown mode, form a voltage selector that allows measurement of the normal cell1 potential (when GPIO1 is low) or a buffered MUX signal. When the MUX ADDING CALIBRATION AND is active (GPIO1 is high), selection can be made between FULL-STACK MEASUREMENTS the reference (4.096V) or the full-stack voltage divider By adding multiplexing hardware, additional signals can (GPOI2 set low will select the reference). During idle time be digitized by the CELL1 ADC channel. One useful signal when the LTC6802-2 WDTB signal goes low, the external to provide is a high accuracy voltage reference, such as circuitry goes into a power-down condition, reducing from an LT®1461A-4 or LTC6652A-4.096. By periodic read- battery drain to a minimum. When not actively perform- ings of this signal, host software can provide correction ing measurements, GPIO1 should be set low and GPIO2 of the LTC6802-2 readings to improve the accuracy over should be set high to achieve the lowest power state for that of the internal LTC6802-2 reference, and/or validate the configuration shown. ADC operation. Another useful signal is a measure of the TP0610K CELL12 2.2M 1M 0 = REF_EN GPIO2 0 = CELL1 VSTACK12 GPIO1 WDTB 1M 1M 10M LT1461A-4 1M DNC DNC VREG VIN DNC 4.096V 2N7002 SD VOUT LTC6802-2 1µF 90.9k GND DNC 2N7002 V− 2.2µF C1 150Ω TP0610K + CELL1 TP0610K TP0610K VDD CH0 CH1 SEL 100Ω SD LT1636 TC4W53FU 100nF – COM INH VEE VSS 1M 68022 F15 Figure 15. Providing Measurement of Calibration Reference and Full-Stack Voltage Through CELL1 Port 68022fa 

LTC6802-2 applicaTions inForMaTion PROVIDING HIGH SPEED OPTO-ISOLATION PCB LAYOUT CONSIDERATIONS OF THE SPI DATA PORT The V and V pins should be bypassed with a 1µF REG REF Isolation techniques that are capable of supporting the capacitor for best performance. 1Mbps data rate of the LTC6802-2 require more power The LTC6802-2 is capable of operation with as much as on the isolated (battery) side than can be furnished by 60V between V+ and V–. Care should be taken on the PCB the V output of the LTC6802-2. To keep battery drain REG layout to maintain physical separation of traces at different minimal, this means that a DC/DC function must be imple- potentials. The pinout of the LTC6802-2 was chosen to mented along with a suitable data isolation circuit, such as facilitate this physical separation. Figure 17 shows the DC shown in Figure 16. Here an optimal Avago 4-channel (3/1 voltage on each pin with respect to V– when twelve 3.6V bidirectional) opto-coupler is used, with a simple isolated battery cells are connected to the LTC6802-2. There is no supply generated by an LTC1693-2 configured as a 200kHz more then 5.5V between any two adjacent pins. The pack- oscillator. The DC/DC function provides an unregulated age body is used to separate the highest voltage (43.5V) logic voltage (~4V) to the opto-coupler isolated side, from the lowest voltage (0V). from energy provided by host-furnished 5V. This circuit provides totally galvanic isolation between the batteries and the host processor, with an insulation rating of 560V continuous, 2500V transient. The Figure 16 functionality is included in the LTC6802-2 demo board. +5V_HOST 330Ω 100k CSBI 3.57k 3.57k 3.57k 100k CSBI SDI TP0610K SDO 100k SCKI SDI 330Ω TP0610K 330Ω SCKI TP0610K VREG 100nF SDO 4.99k 249Ω LTC6802-2 GND_HOST ACSL-6410 ISOLATED VLOGIC 1µF 470pF 20k BAT54S BAT54S VCC1 IN1 OUT1 GND1 1µF 6• •1 33nF VCC2 IN2 10k 4 3 OUT2 GND2 V− PE68386 LTC1693-2 68022 F16 Figure 16. Providing an Isolated High-Speed Data Interface 68022fa 

LTC6802-2 applicaTions inForMaTion LTC6802-2 43.2V V+ CSBI 0V TO 5.5V 43.2V C12 SDO 0V TO 5.5V 43.2V S12 SDI 0V TO 5.5V 39.6V C11 SCKI 0V TO 5.5V 39.6V S11 A3 0V TO 5.5V 36V C10 A2 0V TO 5.5V 36V S10 A1 0V TO 5.5V 32.4V C9 A0 0V TO 5.5V 32.4V S9 GPIO2 0V TO 5.5V 28.8V C8 GPIO1 0V TO 5.5V 28.8V S8 WDTB 0V TO 5.5V 25.2V C7 MMB 0V TO 5.5V 25.2V S7 TOS 0V TO 5.5V 21.6V C6 VREG 5.5V 21.6V S6 VREF 3.1V 18V C5 VTEMP2 1.5V 18V S5 VTEMP1 1.5V 14.4V C4 NC 0V 14.4V S4 V– 0V 10.8V C3 S1 3.6V 10.8V S3 C1 3.6V 7.2V C2 S2 7.2V 68022 F17 Figure 17. Typical Pin Voltages for 12 3.6V Cells ADVANTAGES OF DELTA-SIGMA ADCS to measure several input channels a separate filter will be required for each channel. A low frequency filter cannot The LTC6802-2 employs a delta-sigma analog-to-digital reside between a multiplexer and an ADC and achieve a converter for voltage measurement. The architecture of high scan rate across multiple channels. Another conse- delta-sigma converters can vary considerably, but the quence of filtering a SAR ADC is that any noise reduction common characteristic is that the input is sampled many gained by filtering the input cancels the benefit of having times over the course of a conversion and then filtered or a high sample rate in the first place, since the filter will averaged to produce the digital output code. In contrast, take many conversion cycles to settle. a SAR converter takes a single snapshot of the input voltage and then performs the conversion on this single For a given sample rate, a delta-sigma converter can sample. For measurements in a noisy environment, a achieve excellent noise rejection while settling completely delta-sigma converter provides distinct advantages over in a single conversion—something that a filtered SAR con- a SAR converter. verter cannot do. Noise rejection is particularly important in high voltage switching controllers, where switching While SAR converters can have high sample rates, the full- noise will invariably be present in the measured voltage. power bandwidth of a SAR converter is often greater than Other advantages of delta sigma converters are that they 1MHz, which means the converter is sensitive to noise out are inherently monotonic, meaning they have no missing to this frequency. And many SAR converters have much codes, and they have excellent DC specifications. higher bandwidths—up to 50MHz and beyond. It is pos- sible to filter the input, but if the converter is multiplexed 68022fa 0

LTC6802-2 applicaTions inForMaTion Converter Details is applied to the LTC6802-2 input, the increase in noise seen at the digital output will be the same as an ADC with The LTC6802-2’s ADC has a second-order delta-sigma a wide bandwidth (such as a SAR) preceded by a perfect modulator followed by a Sinc2, finite impulse response 1350Hz brickwall lowpass filter. (FIR) digital filter. The front-end sample rate is 512ksps, which greatly reduces input filtering requirements. A Thus if an analog filter is placed in front of a SAR converter simple 16kHz, 1-pole filter composed of a 100Ω resistor to achieve the same noise rejection as the LTC6802-2 ADC, and a 0.1μF capacitor at each input will provide adequate the SAR will have a slower response to input signals. For filtering for most applications. These component values example, a step input applied to the input of the 850Hz filter will not degrade the DC accuracy of the ADC. will take 1.55ms to settle to 12 bits of precision, while the LTC6802-2 ADC settles in a single 1ms conversion cycle. Each conversion consists of two phases—an autozero This also means that very high sample rates do not provide phase and a measurement phase. The ADC is autozeroed any additional information because the analog filter limits at each conversion, greatly improving CMRR. The second the frequency response. half of the conversion is the actual measurement. While higher order active filters may provide some im- Noise Rejection provement, their complexity makes them impractical for high-channel count measurements as a single filter would Figure 18 shows the frequency response of the ADC. The be required for each input. roll-off follows a Sinc2 response, with the first notch at 4kHz. Also shown is the response of a 1-pole, 850Hz filter Also note that the Sinc2 response has a 2nd order roll-off (187μs time constant) which has the same integrated envelope, providing an additional benefit over a single-pole response to wideband noise as the LTC6802-2’s ADC, analog filter. which is about 1350Hz. This means that if wideband noise 10 0 –10 B) d N ( –20 AI G ER –30 T L FI –40 –50 –60 10 100 1k 10k 100k FREQUENCY (Hz) 68022 F18 Figure 18. Noise Filtering of the LTC6802-2 ADC 68022fa 

LTC6802-2 package DescripTion G Package 44-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1754 Rev Ø) 12.50 – 13.10* (.492 – .516) 1.25 ±0.12 44434241403938373635343332313029282726252423 7.8 – 8.2 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.50 0.25 ±0.05 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 910111213141516171819202122 APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 2.0 5.00 – 5.60* (.197 – .221) 1.65 – 1.85 (.079) (.065 – .073) MAX PARTING 0° – 8° LINE SEATING 0.50 PLANE 0.10 – 0.25 0.55 – 0.95** (.01968) (.004 – .010) (.022 – .037) BSC 0.05 1.25 0.20 – 0.30† (.002) (.0492) (.008 – .012) MIN REF TYP G44 SSOP 0607 REV Ø NOTE: 1.DRAWING IS NOT A JEDEC OUTLINE *DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, 2. CONTROLLING DIMENSION: MILLIMETERS BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE MILLIMETERS 3. DIMENSIONS ARE IN (INCHES) **LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE †THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS. 4. DRAWING NOT TO SCALE DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE 5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE 68022fa 

LTC6802-2 revision hisTory REV DATE DESCRIPTION PAGE NUMBER A 01/10 Additions to Absolute Maximum Ratings 2 Changes to Electrical Characteristics 3, 4 Change to Graph G10 5 Text Changes to Pin Functions 8, 9 Replaced Open-Connection Detection Section 10, 11, 12 Edits to Figures 1, 9 11, 26 Text Changes to Operation Section 13 Text Changes to Applications Information Section 14, 25, 27 Edits to Tables 4, 5, 9, 10, 15, 16 19, 20, 21, 23 68022fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC6802-2 Typical applicaTion Stacked Daisy-Chain SPI Bus for LTC6802-2 VBATT LTC6802-2 VREG IC #3 1M 1.8k 2.2k 2.2k 2.2k WDT NDC7002N ALL NPN: CMPT8099 SDI ALL PNP: CMPT8599 SCKI ALL PN: RS07J ALL SCHOTTKY: CMD5H2-3 CSBI SDO V− LTC6802-2 VREG IC #2 100Ω 2.2k 2.2k 2.2k SDI SCKI CSBI SDO V− LTC6802-2 VREG IC #1 100Ω 2.2k 2.2k 2.2k SDI SCKI CSBI CS SDO CK HOST µP R12 DI 500kbps MAX DATA RATE 2.2k V− DO 68022 TA02 relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTC6802-1 Multicell Battery Stack Monitor with Daisy Chained Functionality equivalent to LTC6802-2, Allows for Multiple Devices to be Serial Interface Daisy Chained 68022fa  Linear Technology Corporation LT 0110 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2009