LTC6801 Independent Multicell Battery Stack Fault Monitor FEATURES DESCRIPTION n Monitors Up to 12 Li-Ion Cells in Series (60V Max) The LTC®6801 is a multicell battery monitoring IC in- n Stackable Architecture Enables > 1000V Systems corporating a 12-bit ADC, a precision voltage reference, n 1% Maximum Overvoltage Detection Level Error sampled comparator, and a high voltage input multiplexer. n Adjustable Overvoltage and Undervoltage Detection The LTC6801 can monitor as many as 12 series con- n Self Test Features Guarantee Accuracy nected battery cells for overvoltage, undervoltage, and n Robust Fault Detection Using Differential Signals overtemperature conditions, indicating whether the cells n Simple Pin-Strapped Configuration Allows Battery are within specified parameters. The LTC6801 generates Monitoring without a Microcontroller a clock output when no fault conditions exist. Differential n 15.5ms to Monitor All Cells in a System clocking provides high noise immunity and ensures that n Programmable Response Time battery stack fault conditions cannot be hidden by frozen n Two Temperature Monitor Inputs bits or short circuit conditions. n Low Power Idle Mode Each LTC6801 can operate with a battery stack voltage up n 36-Lead SSOP Package to 60V and multiple LTC6801 devices can be stacked to monitor each individual cell in a long battery string. When APPLICATIONS multiple devices are stacked, the status signal of each LTC6801 can be daisy-chained, without opto-couplers or n Redundant Battery Monitor isolators, providing a single status output for the entire n Hybrid Electric Vehicles battery string. n Battery Backup Systems The LTC6801 is configurable by external pin strapping. n Power Systems Using Multiple Battery Cells Adjustable overvoltage and undervoltage thresholds sup- L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear port various Li-Ion chemistries. Selectable measurement Technology Corporation. All other trademarks are the property of their respective owners. times allow users to save power. BLOCK DIAGRAM 0V Detection Level Error NEXT HIGHER CELL PACK 1 V+ LTC6801 1.0 V+ = 43.2V C12 0.8 OV = 4.116V 2 0.6 5 TYPICAL UNITS C11 0.4 3 CONTROL %) 0.2 12 C2 MUX ADC 12 LOGIC ENABLE ISOLATION ERROR ( –0.02 INPUT –0.4 C1 “CELLS GOOD” 20 13 CLOCK SIGNAL –0.6 INPUT ENABLES V– THE LTC6801 –0.8 14 –1.0 –40–25–10 5 20 35 50 65 80 95110125 TEMPERATURE (°C) NCEEXLTL L POAWCEKR VTEMP1 VTEMP2 VREF REFERENCE OSTUATTPUUST 22 COLUOTCPKU TS IIGNNDAICLATES 6801 TA01b 15 16 17 SYSTEM “OK” 6801 TA01a NTC NTC 6801fc 1 For more information www.linear.com/LTC6801

LTC6801 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) Total Supply Voltage (V+ to V–) .................................60V TOP VIEW Input Voltage (Relative to V–) V+ 1 36 OV1 C1 ............................................................–0.3V to 9V C12 2 35 OV0 C12 ...........................................V+ –0.3V to V+ + 0.3V C11 3 34 UV1 C10 4 33 UV0 All Other Pins (Not C Inputs) ...................–0.3V to 7V C9 5 32 HYST Voltage Between Inputs C8 6 31 CC1 Cn to Cn-1* ..............................................–0.3V to 9V C7 7 30 CC0 C12 to C8 ...............................................–0.3V to 25V C6 8 29 SLT C8 to C4 .................................................–0.3V to 25V C5 9 28 SLTOK C4 to V– .................................................–0.3V to 25V C4 10 27 DC Operating Temperature Range C3 11 26 EOUT LTC6801I .............................................–40°C to 85°C C2 12 25 EOUT LTC6801H ..........................................–40°C to 125°C C1 13 24 SIN Specified Temperature Range V– 14 23 SIN LTC6801I .............................................–40°C to 85°C VTEMP1 15 22 SOUT LTC6801H ..........................................–40°C to 125°C VTEMP2 16 21 SOUT Junction Temperature ...........................................150°C VREF 17 20 EIN VREG 18 19 EIN Storage Temperature Range ..................–65°C to 150°C G PACKAGE 36-LEAD PLASTIC SSOP *n = 2 to 12 TJMAX = 150°C, θJA = 70°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6801IG#PBF LTC6801IG#TRPBF LTC6801G 36-Lead Plastic SSOP –40°C to 85°C LTC6801HG#PBF LTC6801HG#TRPBF LTC6801G 36-Lead Plastic SSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 6801fc 2 For more information www.linear.com/LTC6801

LTC6801 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C, V+ = 43.2V, V– = 0V unless otherwise noted. A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Specifications V Overvoltage (OV) or Undervoltage (UV) (Note 2) ERR Detection Level Error 2.106V ≤ V ≤ 4.498V –0.8 0.8 % CELL 2.106V ≤ V ≤ 4.498V l –1 1 % CELL 1.531V ≤ V < 2.106V –1 1 % CELL 1.531V ≤ V < 2.106V l –1.3 1.3 % CELL V = 0.766V –1.5 1.5 % CELL V = 0.766V l –2 2 % CELL V Supply Voltage, V+ Relative to V– V Specifications Met l 10 50 V S ERR V Cell Voltage Range Full Scale Voltage Range 5 V CELL V Common Mode Voltage Range Measured V Specifications Met CM ERR Relative to V– Range of Inputs Cn, n = 3 to 11 l 1.8 5 • n V Range of Input C2 l 1.2 10 V Range of Input C1 l 0 5 V V Temperature Input Detection Level Error 10V < V+ < 50V l –13 17 mV TV (Relative to V /2) REF HYS UV/OV Detection Hysteresis Error 10V < V+ < 50V l –25 25 % (Relative to Selected Value) V Reference Pin Voltage V Pin Loaded With 100k to V– 3.043 3.058 3.073 V REF REF l 3.038 3.058 3.078 V Reference Voltage Temperature Coefficient 8 ppm/˚C Reference Voltage Hysteresis 50 ppm Reference Voltage Long Term Drift 60 ppm/√khr V Regulator Pin Voltage 10V < V < 50V, No Load REG S LTC6801IG l 4.5 5 5.5 V LTC6801HG l 4.5 5 5.7 V 10V < V < 50V, I = 4mA S LOAD LTC6801IG l 4.1 4.8 V LTC6801HG l 4.1 4.8 V Regulator Pin Short Circuit Current Limit l 5 9 mA I Input Bias Current In/Out of Pins C1 Thru C12 B When Measuring Cells During Self Test 100 µA When Measuring Cells l –10 10 µA When Idle 1 nA I Supply Current, Monitor Mode Current Into the V+ Pin While Monitoring M for UV and OV Conditions, F = 10kHz ENA Continuous Monitoring 600 750 1000 µA Continuous Monitoring l 500 750 1100 µA Monitor Every 130ms (Note 3) l 110 200 320 µA Monitor Every 500ms (Note 3) l 50 100 160 µA I Supply Current, Idle Current into the V+ Pin When Idle, F = 0 QS ENA LTC6801IG 23 30 42 µA l 20 30 45 µA LTC6801HG 23 30 42 µA l 20 30 48 µA LTC6801 Timing Specifications T Measurement Cycle Time DC = CC1 = CC0 = V l 13 15.5 19 ms CYCLE REG F Valid EIN/EIN Frequency l 2 40 kHz ENA T Valid EIN/EIN Period = 1/ F l 25 500 µs ENA ENA DC Valid EIN/EIN Duty Cycle F = 40kHz l 40 60 % ENA ENA 6801fc 3 For more information www.linear.com/LTC6801

LTC6801 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C, V+ = 43.2V, V– = 0V unless otherwise noted. A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LTC6801 Single Ended Digital I/O Specifications (SLT, SLTOK Pins) V Digital Input Voltage High SLT Pin l 2 V IH V Digital Input Voltage Low SLT Pin l 0.5 V IL V Digital Output Voltage Low, Open Drain SLT Pin, 10k to V l 0.3 V ODL REG V Digital Output Voltage High SLTOK Pin, 10k to V– l V – 0.3 V OH REG V Digital Output Voltage Low SLTOK Pin, 10k to V l 0.3 V OL REG I Pull-Up Current SLT Pin l 2.5 5 10 µA PU-ST LTC6801 Differential Digital Input Specifications (SIN/SIN, EIN/EIN Pins) (See Figure 1) V Minimum Differential Input Voltage High Differential Voltage Applied Between SIN l 1.7 V IDH and SIN or EIN and EIN V Minimum Differential Input Voltage Low l –1.7 V IDL V Valid Input Voltage Low Low Side of Differential Signal, Ref. to V– l 0 1.2 V IL V Valid Input Voltage High High Side of Differential Signal, Ref. to V– l 2.5 6 V IH V Differential Input Hysteresis 1 V DHYS V Open Circuit Voltage l 2 2.5 3 V OPEN R Input Resistance, Common Mode l 100 150 kΩ INCM R Input Resistance, Differential Between SIN to SIN, EIN to EIN l 200 300 kΩ INDIFF LTC6801 Differential Digital Output Specifications (SOUT/SOUT, EOUT/EOUT Pins) V Digital Output Voltage High Output Pins Loaded With 100k to V– l V – 0.4 V ODH REG V Digital Output Voltage Low Output Pins Loaded With 100k to V l 0.4 V ODL REG LTC6801 Three-Level Digital Input Specifications (OV0, OV1, UV0, UV1, HYST, DC, CC0 and CC1 Pins) V Three-Level Digital Input Voltage High l V – 0.3 V 3IH REG V Three-Level Digital Input Voltage Mid l V – 0.3 V + 0.3 V 3IM REF REF V Three-Level Digital Input Voltage Low l 0.3 V 3IL I Pull-Up Current Pins DC, CC0, CC1, UV0 and UV1 l 0.5 1 2 µA PU I Pull-Down Current Pins HYST, OV0 and OV1 l 0.5 1 2 µA PD Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 2: V refers to the voltage applied across the following pin CELL may cause permanent damage to the device. Exposure to any Absolute combinations: Cn to Cn – 1 for n = 2 to 12, C1 to V–. Maximum Rating condition for extended periods may affect device Note 3: Guaranteed by continuous monitoring supply current reliability and lifetime. specifications, not subject to test. EIN VIDH MAX, VIH (VEAINLI D– EHIING H≥ WVIDHHE)N TENA MIN, VIH EIN MAX, VIL VIDL (VALID LOW WHEN EIN – EIN ≤ VIDL) V– = 0V 6801 F01 Figure 1. Differential Input Specifications 6801fc 4 For more information www.linear.com/LTC6801

LTC6801 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current, Monitor Mode Supply Current, Monitor Mode Supply Current, Idle Mode 800 250 40 DC PIN TIED TO VREG CC1 = CC0 = VREG 780 fENA = 10kHz fENA = 10kHz 35 760 85°C 200 25°C 30 85°C 740 A) 720 25°C A) 150 DC PIN = VREF A) 25 (µPLY 700 (µPLY (µPLY 20 –40°C P P P ISU 680 ISU 100 ISU 15 –40°C 660 DC PIN = V– 10 640 50 85°C 5 620 25°C –40°C 600 0 0 10 20 30 40 50 60 10 20 30 40 50 60 10 20 30 40 50 60 V+ (V) V+ (V) V+ (V) 6801 G01 6801 G02 6801 G03 Supply Current, Monitor Mode Supply Current, Monitor Mode Supply Current, Idle Mode 800 250 40 DC PIN TIED TO VREG CC1 = CC0 = VREG 780 fENA = 10kHz V+ = 60V fENA = 10kHz 35 760 200 V+ = 60V 30 740 V+ = 35V DC PIN = VREF A) 720 A) 150 A) 25 (µPLY 700 V+ = 35V (µPLY (µPLY 20 V+ = 10V P P P ISU 680 ISU 100 ISU 15 660 V+ = 10V DC PIN = V– 10 640 50 V+ = 60V 620 V+ = 35V 5 V+ = 10V 600 0 0 –40–25–10 5 20 35 50 65 80 95 110125 –40–25–10 5 20 35 50 65 80 95 110125 –40–25–10 5 20 35 50 65 80 95 110125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 6801 G04 6801 G05 6801 G06 UV Detection Level Error 0V Detection Level Error Supply Current 1.0 V+ = 43.2V 1.0 V+ = 43.2V 800 V+ = 43.2V 0.8 UV = 2.106V 0.8 OV = 4.116V 780 CONTINUOUS MEAS MODE 0.6 0.6 760 5 TYPICAL UNITS 5 TYPICAL UNITS 85°C 0.4 0.4 740 %) 0.2 %) 0.2 A) 720 ERROR ( –0.02 ERROR ( –0.02 (µSUPPLY 760800 25°C I –0.4 –0.4 660 –40°C –0.6 –0.6 640 –0.8 –0.8 620 –1.0 –1.0 600 –40–25–10 5 20 35 50 65 80 95 110125 –40–25–10 5 20 35 50 65 80 95 110125 1 10 100 TEMPERATURE (°C) TEMPERATURE (°C) fENA (kHz) 6801 G07 6801 G08 6801 G09 6801fc 5 For more information www.linear.com/LTC6801

LTC6801 TYPICAL PERFORMANCE CHARACTERISTICS Cell Input Bias Current when UV/OV Detection Level Error Measurement Cycle Time Measuring 4.0 17.0 8.0 RS IN SERIES WITH Cn AND Cn-1 CONTINUOUS MEAS MODE CELL INPUT = 3.6V 3.5 10nF FROM Cn, Cn-1 TO V– CC1 = CC0 = VREG 7.5 %) 85°C ms) 16.5 ERROR RELATIVE TO R = 0 (S21321.....55000 25°C –40°C MEASUREMENT CYCLE TIME ( 11115465....5500 VV++ == 1600VV C PIN BIAS CURRENT (µA) 67655.....50050 0.5 4.5 0 14.0 4.0 0 2 4 6 8 10 –40–25–10 5 20 35 50 65 80 95 110125 –40–25–10 5 20 35 50 65 80 95 110125 EXTERNAL SERIES RESISTANCE, RS (kΩ) TEMPERATURE (°C) TEMPERATURE (°C) 6801 G10 6801 G11 6801 G12 Cell Voltage Measurement Cell Input Bias Current, Idle Mode Hysteresis V Line Regulation REF 50 12 3.070 CELL INPUT = 3.6V UV THRESHOLD = 2.106V NO LOAD OV THRESHOLD = 4.116V NT (nA) 4300 NCY (kHz) 108 HYST = VREG 3.065 C PIN BIAS CURRE 2100 C12 C1 UT CLOCK FREQUE 624 UNDDEETREVCOTLETDAGE V (V)REF 33..006505 25°C –8450°°CC O 0 S 0 C2 TO C11 VTEMP1, VTEMP2 OVERVOLTAGE DETECTED –10 –2 3.050 –40–25–10 5 20 35 50 65 80 95 110125 0 1 2 3 4 5 10 20 30 40 50 60 TEMPERATURE (°C) CELL VOLTAGE (V) V+ (V) 6801 G13 6801 G14 6801 G15 VREF Load Regulation VREF Output Voltage VREG Line Regulation 3.070 3.070 5.5 NO LOAD IDLE MODE 5.4 NO LOAD 5.3 85°C 3.065 3.065 5 TYPICAL UNITS 5.2 25°C 5.1 V) V) V) V (REF3.060 V (REF3.060 V (REG 54..09 –40°C –40°C 4.8 3.055 3.055 4.7 25°C 85°C 4.6 3.050 3.050 4.5 0 50 100 150 200 250 300 –40–25–10 5 20 35 50 65 80 95 110125 10 20 30 40 50 60 ILOAD (µA) TEMPERATURE (°C) V+ (V) 6801 G20 6801 G16 6801 G17 6801fc 6 For more information www.linear.com/LTC6801

LTC6801 TYPICAL PERFORMANCE CHARACTERISTICS VREG Line Regulation VREG Load Regulation VREG Output Voltage 5.5 5.5 5.5 IDLE MODE IDLE MODE IDLE MODE 5.4 4mA LOAD TO V– 5.4 5.3 5.3 5.2 5.2 5.0 NO LOAD 5.1 5.1 V) V) V) (G 5.0 85°C (G (G 5.0 RE RE RE 4mA LOAD V 4.9 V V 4.9 4.8 25°C 4.5 85°C 4.8 25°C 4.7 –40°C –40°C 4.7 V+ = 60V 4.6 V+ = 60V 4.6 V+ = 35V V+ = 10V V+ = 10V 4.5 4.0 4.5 10 20 30 40 50 60 0 2 4 6 8 10 –40–25–10 5 20 35 50 65 80 95 110125 V+ (V) ILOAD (mA) TEMPERATURE (°C) 6801 G18 6801 G19 6801 G21 UV/OV Detection Level Thermal UV/OV Detection Level Thermal Status Output Operating at 10kHz Hysteresis Hysteresis 100k LOAD TO V– 16 TA = 85°C TO 25°C 20 TA = –40°C TO 25°C 18 14 16 SOUT 12 S S14 T T 2V/DIV UNI10 UNI12 F F R O 8 R O10 SOUT MBE 6 MBE 8 U U N N 6 4 4 20µs/DIV 6801 G22 2 2 0 0 –100 –50 0 50 100 150 200 –100 –50 0 50 100 150 200 CHANGE IN DETECTION LEVEL (ppm) CHANGE IN DETECTION LEVEL (ppm) 6801 G23 6801 G24 6801fc 7 For more information www.linear.com/LTC6801

LTC6801 PIN FUNCTIONS V+ (Pin 1): Supply Voltage. Tied to the most positive po- SOUT, SOUT (Pin 21, Pin 22): Differential Status Output. tential in the battery stack. For example, the same potential Swings V– to V . This output will toggle at the same REG as C12 when measuring a stack of 12 cells, or the same frequency as EIN/EIN when a valid signal is detected at potential as C7 when measuring a stack of 7 cells. SIN/SIN and the battery stack being monitored is within specified parameters, otherwise SOUT is low and SOUT high. C12, C11, … C1 (Pin 2 to Pin 13): Cell Voltage Inputs. Up to 12 cells can be monitored. The lowest potential is SIN, SIN (Pin 23, Pin 24): Differential status input from tied to V–. The next lowest potential is tied to C1 and so the IC above. To indicate that the stack is good, SIN must forth. Due to internal overvoltage protection, each C input be the same frequency and phase as EIN. See applications must be tied to a potential equal to or greater than the next circuits for interfacing SIN to the SOUT above. lower numbered C input. See the figures in the Applications EOUT, EOUT (Pin 25, Pin 26): A Buffered Version of EIN/ Information section for more details on connecting batteries EIN. Swings V– to V . Must be capacitively coupled to REG to the LTC6801. See Electrical Characteristics table for the EIN/EIN inputs of the next higher voltage LTC6801 in a voltage range and input bias current requirements. stack, or looped to SIN/SIN of the same chip (pins 23, 24). V– (Pin 14): Tied to the most negative cell potential (bottom DC (Pin 27): Duty Cycle Three-Level Input. This pin may of monitored cell stack). be tied to V , V or V–. The DC pin selects the duty REG REF V , V (Pin 15, Pin 16): Temperature Sensor cycle of the monitoring function and has an internal pull- TEMP1 TEMP2 Inputs. The ADC will measure the voltages on V up to V . See Table 3. TEMP1 REG and V relative to V–. The ADC measurements are TEMP2 SLTOK (Pin 28): Self Test Logic Output. SLTOK is held HIGH referenced to the V pin voltage. Therefore a simple REF (V voltage) upon reset or successful completion of a REG thermistor and resistor combination connected to the V REF self test cycle. A LOW output level (V– voltage) indicates pin can be used to monitor temperature. These pins have the last self test cycle failed. a fixed undervoltage threshold equal to one half V . A REF filtering capacitor to V– is recommended. Temperature SLT (Pin 29): Self Test Open Collector Input/Output. SLT sensor input pins may be tied to V to disable. initiates a self test cycle when it is pulled low externally. REF When a high to low transition is detected, the next scheduled V (Pin 17): Reference Output, Nominally 3.058V. Re- REF measurement cycle will be a self test cycle. SLT indicates a quires a 1µF bypass capacitor to V–. The V pin can REF self test cycle is in progress when pulled low internally. A drive a 100k resistive load connected to V–. V must REF self test is automatically initiated after 1024 measurement be buffered with an LT6003 amplifier, or similar device to cycles. This pin has an internal pull-up to V . REG drive heavier loads. V becomes high impedance when REF the IC is disabled or idle between monitoring events. CC0, CC1 (Pin 30, Pin 31): Cell Count Three-Level Inputs. These pins may be tied to V , V or V–. CC1 and CC0 REG REF V (Pin 18): Regulator Output, Nominally 5V. Requires REG select the number of cells attached to the device and each a 1µF bypass capacitor to V–. The V pin is capable of REG pin has an internal pull-up to V . See Table 5. REG supplying up to 4mA to an external load and is continually enabled. HYST (Pin 32): Hysteresis Three-Level Input. This pin may be tied to V , V or V–. HYST selects the amount of REG REF EIN, EIN (Pin 19, Pin 20): Differential Enable Input. A hysteresis applied to the undervoltage and overvoltage clock signal greater than 2kHz will enable the LTC6801. For threshold settings and has an internal pull-down to V–. operation with a single-ended enable signal (up to 10kHz), See Table 4. drive EIN and connect a 1nF capacitor from EIN to V–. 6801fc 8 For more information www.linear.com/LTC6801

LTC6801 PIN FUNCTIONS UV0, UV1 (Pin 33, Pin 34): Undervoltage Three-Level Table 3. Duty Cycle Select Inputs. These pins may be tied to V , V or V–. UV1 REG REF DC NOMINAL CYCLE TIME* and UV0 select the undervoltage threshold and each pin V 15.5ms REG has an internal pull-up to V . See Table 2. REG V Approximately 130ms REF OV0, OV1 (Pin 35, Pin 36): Overvoltage Three-Level V– Approximately 500ms Inputs. These pins may be tied to V , V or V–. OV1 REG REF *Cycle time based on LTC6801 measuring 12 cells and 2 temperatures. and OV0 select the overvoltage threshold and each pin has an internal pull-down to V–. See Table 1. Table 4. Hysteresis Select Table 1. Overvoltage Inputs HYST UV HYSTERESIS* OV HYSTERESIS OV1 OV0 OVERVOLTAGE THRESHOLD (V) VREG 500mV 200mV VREG VREG 4.498 VREF 250mV 100mV V V 4.403 V– 0mV 0mV REG REF V V– 4.307 *UV hysteresis is disabled when the undervoltage threshold is set to 0.766V. REG V V 4.211 REF REG V V 4.116 Table 5. Cell Count Select REF REF VREF V– 4.020 CC1 CC0 CELL COUNT V– VREG 3.924 VREG VREG 12 V– VREF 3.828 VREG VREF 11 V– V– 3.733 VREG V– 10 V V 9 REF REG Table 2. Undervoltage Inputs VREF VREF 8 UV1 UV0 UNDERVOLTAGE THRESHOLD (V) VREF V– 7 VREG VREG 2.871 V– VREG 6 VREG VREF 2.680 V– VREF 5 V V– 2.489 V– V– 4 REG V V 2.297 REF REG V V 2.106 REF REF V V– 1.914 REF V– V 1.723 REG V– V 1.531 REF V– V– 0.766 6801fc 9 For more information www.linear.com/LTC6801

LTC6801 BLOCK DIAGRAM The LTC6801 measures between 4 and 12 cell voltages ferential clock output signal (SOUT, SOUT). If any of the and 2 temperature inputs. If all measurements are within channels exceed user set upper and lower thresholds, a an acceptable window, the LTC6801 will produce a dif- logic low signal is produced at SOUT. V+ VREG REGULATOR C12 HYST C11 CC1 C10 12 + CC0 C9 ADC DC C8 – C7 DIGITAL UV/OV COMPARATORS FLAGS AND SLT C6 MUX REFERENCE – COLNOTGRICOL SLTOK C5 + EIN + C4 SELF TEST – EIN REFERENCE (REF2) C3 EOUT EOUT C2 C1 + SIN “GOOD” V– – SIN DECODER SOUT SOUT VTEMP1 VTEMP2 VREF OV0 OV1 UV0 UV1 6801 BD 6801fc 10 For more information www.linear.com/LTC6801

LTC6801 BLOCK DIAGRAM OF ENABLE IN/OUT AND STATUS IN/OUT EOUT EOUT VREG 300k SIN + THE FREQUENCY MATCH FREQUENCY VREG 300k DETECT OUTPUT GOES MATCH HIGH WHEN SIN AND EIN ARE THE SAME FREQUENCY DETECT – 300k SIN 300k THE SIGNAL IS HIGH WHEN SOUT SOUT IS ACTIVE WHEN ALL READINGS 1) EIN IS ACTIVE ARE “GOOD” SOUT 2) SIN AND EIN ARE THE SAME FREQUENCY 3) ALL READINGS ARE “GOOD” VREG 300k EIN – THE CLK DETECT VREG 300k OUTPUT GOES CLK HIGH WHEN EIN IS DETECT 2kHz TO 40kHz + 300k EIN 300k 6801 BDa 6801fc 11 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION OVERVIEW INDEPENDENT OPERATION The LTC6801 is designed as an easy to implement, low- Figure 3 shows how three groups of 12 cells can be mon- cost battery stack monitor that provides a simple indica- itored independently. tion of correct battery stack operation without requiring a microcontroller interface. For battery stack monitoring REGULATED OUTPUTS with cell voltage read back and discharge circuitry, refer A regulated voltage is provided at the V pin, biased from to the LTC6802 battery stack monitor data sheet. REG the battery stack. The V pin can supply up to 4mA at REG The LTC6801 contains a 12-bit ADC, a precision voltage 5V and may be used to power small external circuits. The reference, sampled comparator, high voltage multiplexer regulated output remains at 5V continually, as long as the and timer/sequencer. During normal operation, the se- total stack voltage is between 10V and 50V. quencer multiplexes the ADC inputs between each of the A low current, precision reference voltage is provided at the channel input pins in turn, performing a single comparison V pin, which can drive loads of greater than 100k. The to the undervoltage and overvoltage thresholds. The V REF TEMP V output is high impedance when the LTC6801 is idle. inputs are also monitored for an undervoltage at a fixed REF threshold of VREF/2. Both the VREG and VREF pins must be bypassed to V– with a 1µF capacitor. The presence of a status output clock indicates the system is “OK”. Because the status output is dynamic, it cannot get stuck in the “OK” state. CONTROL INPUTS The LTC6801 thresholds are controlled by the UV1, UV0, STACKED OPERATION OV1 and OV0 pins. These pins are designed to be tied directly to V , V or V– in order to set the comparison Each LTC6801 monitors a group of up to 12 series con- REG REF thresholds for all channels simultaneously. The pins are nected cells. Groups of cells can be connected in series not designed to be variable. In particular, changes made or parallel to form a large battery pack. The LTC6801s can to the pins while the chip is not in idle mode may result be daisy chained with simple capacitive or transformer in unpredictable behavior. See Tables 1 and 2 for setting coupling. This allows every cell in a large battery pack and threshold information. to be monitored with a single signal. Figure 2 illustrates monitoring of 36 series connected cells. To cancel systematic duty cycle distortion through the clock buffers, it is recommended that the clock lines are cross-coupled (EOUT goes to EIN etc.) as they route up and down the stack as shown in Figure 2. 6801fc 12 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION ENABLE INPUTS The maximum delay between when a bad cell voltage occurs and when it is detected depends on the measure- In order to support stacked operation, the LTC6801 is ment duty cycle setting. The SOUT clock turns on or off enabled through a differential signal chain encompassing at the end of each measurement cycle. Figure 4 shows the EIN/EIN, EOUT/EOUT, and SIN/SIN pins. the maximum detection delay in continuous monitor mode The LTC6801 will be enabled if a differential square wave (DC pin tied to V ). REG with a frequency between 2kHz and 40kHz is applied at EIN/EIN. Otherwise, the LTC6801 will default to a low FAULT PROTECTION power idle mode. If the differential signal at SIN/SIN is not equal in frequency Overview to the differential signal output at EOUT/EOUT, the LTC6801 Care should always be taken when using high energy will be enabled but SOUT will be held at 0V and SOUT will sources such as batteries. There are countless ways that be held at V . REG systems can be [mis-]configured during the assembly For the simplest operation in a single chip configuration, and service procedures that can impact a battery’s long EOUT should be connected directly to SIN and EOUT should term performance. Table 6 shows various situations to be connected directly to SIN, and a square wave with a consider when planning protection circuitry. frequency between 2kHz and 40kHz should be applied Battery Interconnection Integrity differentially to EIN and EIN. For enable clock frequencies up to 10kHz, a single-ended square wave with a 5V swing Please note: The last condition shown in the FMEA table may be used at EIN while a 1nF capacitor is connected could cause catastrophic IC failures. In this case, the battery from EIN to V–. string integrity is lost within a cell group monitored by an LTC6801. This condition could place excessive stress STATUS OUTPUT on certain cell input signal clamp-diodes and probably lead to IC failure. If this scenario seems at all likely in a If the chip is properly enabled (EIN/EIN, SIN/SIN are the particular application, series fuses and parallel Schottky same frequency), all cells are within the undervoltage diodes should be connected as shown in Figure 5 to limit and overvoltage thresholds, and the voltage at V TEMP1 stress on the IC inputs. The diodes used in this situation and V is over one half V , the differential output TEMP2 REF need current ratings sufficient to open the protective fuse at SOUT/SOUT will toggle at the same frequency and in in the battery tap signal. phase with the signal at EIN/EIN. Otherwise, SOUT will be low and SOUT will be high. 6801fc 13 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION TOP OF TOP OF STACK STACK PROGRAMMED CONDITIONS: CONTINUOUS MONITOR MODE VC+12 LTC6801 OOVV10 VC+12 LTC6801 OOVV10 OUHVVY S==T 42 =..11 2105660VVmV (UV), 100mV (OV) C11 UV1 C11 UV1 CC = 12 C10 UV0 C10 UV0 C9 HYST C9 HYST C8 CC1 C8 CC1 C7 CC0 C7 CC0 C6 SLT C6 SLT C5 SLTOK C5 SLTOK C4 DC C4 DC C3 EOUT C3 EOUT C2 EOUT C2 EOUT C1 SIN C1 SIN V– SIN V– SIN VTEMP1 SOUT VTEMP1 SOUT VTEMP2 SOUT VTEMP2 SOUT VREF EIN VREF EIN VREG EIN VREG EIN V+ OV1 V+ OV1 LTC6801 LTC6801 C12 OV0 C12 OV0 C11 UV1 C11 UV1 C10 UV0 C10 UV0 C9 HYST C9 HYST C8 CC1 C8 CC1 C7 CC0 C7 CC0 C6 SLT C6 SLT C5 SLTOK C5 SLTOK C4 DC C4 DC C3 EOUT C3 EOUT C2 EOUT C2 EOUT C1 SIN C1 SIN V– SIN V– SIN VTEMP1 SOUT VTEMP1 SOUT VTEMP2 SOUT VTEMP2 SOUT VREF EIN VREF EIN VREG EIN VREG EIN V+ OV1 V+ OV1 LTC6801 LTC6801 C12 OV0 C12 OV0 C11 UV1 C11 UV1 C10 UV0 C10 UV0 C9 HYST C9 HYST C8 CC1 C8 CC1 C7 CC0 C7 CC0 C6 SLT C6 SLT C5 SLTOK C5 SLTOK C4 DC C4 DC C3 EOUT C3 EOUT C2 EOUT C2 EOUT C1 SIN C1 SIN ALL CLOCKS V– SIN CLOCK OUT V– SIN OCEULTL WS HGEONO DALL VTEMP1 SOUT WHEN ALL VTEMP1 SOUT VTEMP2 SOUT CELLS GOOD VTEMP2 SOUT VREF EIN USER SUPPLIED VREF EIN USER SUPPLIED VREG EIN CLOCK IN VREG EIN CLOCK IN 6801 F02 6801 F03 BOTTOM BOTTOM OF STACK OF STACK Figure 2. Serial Connection of Status Lines for Multiple 6801s Figure 3. Independent Status Lines for Multiple 6801s on the on the Same PCB (Simplified Schematic, Not All Components Same PCB (Simplified Schematic, Not All Components Shown) Shown) 6801fc 14 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION C3 PS MENT 6801 F04 C1C2 SOUT STOAT END OFMEASURECYCLE 2 T SD UE TATDAT T1 T SUP OU 12 S C 1 1 C 0 1 C 9 C 8 C e d C7 o M C6 nitor o C5 M SOUT STATUSUPDATED C2C3C4 LTC6801 READSA BAD VOLTAGEON CELL 1 y in Continuous a C1 el D C12T1T2 SOUTREMAINSACTIVE (SINCE NOTHINGABNORMAL HASN DETECTED YET) OV Detection EE V/ 11 B U MPLETE MEASUREMENT CYCLE 15.4 ms(~1.1ms PER CELL) C8C9C10C5C6C7 WORST CASE ERROR DETECTIONDELAY ~29.7ms MAX SPECIFICATIONS Figure 4. Cell CO C EMIN/ C1C2C3C4 ALLCELLSGOOD CELL 1 GOES BADIMMEDIATELYAFTER IT IS READ NOTE: SOUT IS NOT TO SCALSEE ELECTRICAL TABLE FOR T S U E SO MPL A X E 6801fc 15 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION Table 6. Failure Mechanism Effect Analysis (FMEA) SCENARIO EFFECT DESIGN MITIGATION Cell input open-circuit (random) Power-up sequence at IC inputs Clamp diodes at each pin to V+ & V– (within IC) provide alternate PowerPath. Cell input open-circuit (random) Differential input voltage overstress Zener diodes across each cell voltage input pair (within IC) limit stress. Top cell input connection loss (V+) Power will come from highest connected cell Clamp diodes at each pin to V+ and V– (within input IC) provide alternate PowerPath. Error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). Bottom cell input connection loss (V–) Power will come from lowest connected cell input Clamp diodes at each pin to V+ and V– (within IC) provide alternate PowerPath. Error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). Power input disconnection Loss of supply connections Clamp diodes at each pin to V+ and V– (within (amongst stacked units) IC) provide alternate PowerPath. Error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). Status link disconnection Break of “daisy chain” communication Daisy chain will be broken and error condition (between stacked units) (no stress to ICs) will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). Short between any two configuration inputs Power supplies connected to pins will be shorted If V or V is shorted to V–, supply will REF REG be removed from internal circuitry and error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). If V is shorted to V , a self test error will be REF REG flagged. Open connection on configuration input Control input will be pulled towards positive or Control input will be pulled to a more stringent negative potential depending on pin condition (larger number of channels, higher UV threshold, lower OV threshold, shorter duty cycle, etc. ensuring either more stringent monitoring or error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). Cell-pack integrity, break between stacked units Daisy-chain voltage reversal up to full stack Full stack potential may appear across status/ potential enable isolation devices, but will not be seen by the IC. isolation capacitors should therefore be rated to withstand the full stack potential. Cell-pack integrity, break within stacked unit Cell input reverse overstress Add battery tap fuses and Schottky diodes in parallel with the cell inputs to limit stress on IC. Diode and connections must handle current sufficient to open fuse 6801fc 16 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION V+ LTC6801 Cn PROTECT AGAINST C12 BREAKS HERE EOUT Cn – 1 C11 EOUT 6801 F05 Figure 5. Using Fuses and Diodes for Cell Input SIN Protection (One Cell Connection Shown) C10 ZCLAMP SIN SOUT Internal Protection Structure C9 SOUT The LTC6801 incorporates a number of protective struc- EIN tures, including parasitic diodes, Zener-like overvoltage C8 suppressors, and other internal features that provide EIN protection against ESD and certain overstress conditions VTEMP1 C7 that could arise in practice. Figure 6 shows a simplified VTEMP2 internal schematic that indicates the significant protective C6 VREF structures and their connectivity. The various diodes indi- ZCLAMP cate the approximate current versus voltage characteristics VREG that are intrinsic to the part, which is useful in analyzing C5 OV1 responses to certain external stresses, such as during a OV0 hot-start scenario. C4 UV1 UV0 SELF TEST CIRCUITRY C3 HYST The LTC6801 has internal circuitry that performs a periodic CC1 self test of all measurement functions. The LTC6801 self C2 ZCLAMP CC0 test circuitry is intended to prevent undetectable failure modes. Accuracy and functionality of the voltage reference C1 SLT and comparator are verified, as well as functionality of SLTOK the high voltage multiplexer and ADC decimation filter. V– DC Additionally, open connections on the cell input pins C1 to C11 are detected (Open connections on V– or C12/ 6801 F06 V+ will cause an undervoltage failure during the normal Figure 6. Internal Protection Structures measurement cycle). 6801fc 17 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION Self Test Pins The self test guarantees that V is within 5% of the REF specified nominal value. Also, this test guarantees the The SLT pin is used to initiate a self test. It is configured analog portion of the ADC is working. as an open collector input/output. The pin should be nor- mally tied to V with a resistor greater than or equal to REG High Voltage Multiplexer Verification 100k or floated. The pin may be pulled low at any time to initiate a self test cycle. The most dangerous failure mode of the high voltage multiplexer would be a stuck bit condition in the address The device will automatically initiate a self test if SLT has decoder. Such a fault would cause some channels to be not been externally activated for 1024 measurement cycles, measured repeatedly while other channels are skipped. and pull down the SLT pin internally to indicate that it is A skipped channel could mean a bad cell reading is not in self test mode. detectable. Other multiplexer failures, like the simultaneous The SLTOK pin is a simple logic output. If the previous self selection of multiple channels, or shorts in the signal path, test failed the output is held low, otherwise the output will would result in an undervoltage or overvoltage condition be high. The SLTOK pin is high upon power-up. The SLTOK on at least one of the channels. output can be connected to a microcontroller through an The LTC6801 incorporates circuitry to ensure that isolation path. all requested channels are measured during each The LTC6801 status output will remain active while the measurement cycle and none are skipped. If a channel SLTOK pin is low. The LTC6801 will continue to monitor is skipped, an error is flagged during the self test cycle. cells if the self test fails. If the next self test passes, the SLTOK output returns high. ADC Decimation Filter Verification The ADC decimation filter test verifies that the digital cir- Reference and Comparator Verification cuits in the ADC are working, i.e. there are no stuck bits A secondary internal bandgap voltage reference (REF2) in the ADC output register. During each self test cycle, is included in the LTC6801 to aid in verification of the the LTC6801 feeds two test waveforms into the ADC. The reference and comparator. During the self test cycle, the internally generated waveforms were designed to generate comparator and main reference are used to measure the complementary zebra patterns (alternating 0’s and 1’s) REF2 voltage. at the ADC output. If either of the waveforms generates an incorrect output value, an error is flagged during the To verify the comparator functionality, the upper and self test cycle. lower thresholds are first set in a close window around the expected REF2 voltage and the comparator output is Open Cell Connection Detection verified. Then the upper threshold is set below the REF2 voltage and the comparator output is verified again. Lastly, The open connection detection algorithm ensures that an the lower threshold is set above the REF2 voltage and the open circuit is not misinterpreted as a valid cell reading. comparator output is verified a third time. 6801fc 18 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION In the absence of external noise filtering, the input resis- self test, this current will cause the cell input to settle to tance of the ADC will cause open wires to produce a near a voltage low enough to trigger an undervoltage condition zero reading. This reading will cause an undervoltage during the normal measurement cycle. failure during the normal measurement cycle. Note, an open cell connection may not be detected when Some applications may include external noise filtering to the UV = 0.766V setting is used. For all other UV settings, improve the quality of the voltage comparisons. When an open cell connection will result in either a self test error an RC network is used to filter noise, an open wire may or no SOUT clock. not produce a zero reading because the comparator input resistance is too large to discharge the capacitors on the Using The LTC6801 with Other Battery Monitors input pin. Charge may build up on the open pin during When used in combination with an LTC6802-1, it is possible successive measurement cycles to the extent that it could to check the LTC6801 self test result via the LTC6802-1 and indicate a valid cell voltage reading. its isolated SPI. As shown in Figure 7, the SLTOK output During each self test cycle, the LTC6801 will sink 100µA is tied to the GPIO2 pin on the LTC6802-1. SLTOK will to V– from each side of the cell being measured. The remain high as long as it is passing the self test. A self test undervoltage threshold is not checked during the self test will occur automatically every 1024 measurement cycles because the 100µA pull-down current would cause false (17 seconds to 9 minutes, depending on measurement failures in some cases. If an input is open, this current will duty cycle). A self test can be initiated by a falling edge discharge any filtering capacitors and cause the input to on SLT, via the LTC6802-1 GPIO1 line. A self test will start float down to approximately 0.7V below the next lower cell after the current measurement cycle is complete, and the input. In most cases, the cell voltage of the cell above the SLTOK status will be valid when the self test completes. open input will exceed the overvoltage threshold and flag The worst case delay before SLTOK is valid in continuous a self test error. During the normal measurement cycle, monitor mode is approximately 15ms for the current cycle the LTC6801 will sink 1µA to V– from each side of the cell to complete plus 17ms for the self test to complete. being measured. If the cell voltages are low enough that The 6802-1 can measure the LTC6801 reference, which an open wire is not detected as an overvoltage during will independently test the analog circuitry of the LTC6802. CSBO CSBI SDOI SDO SCKO SDI V+ SCKI V+ OV1 C12 C12 VMODE IN CMPD6263 C12 C12 OV0 S12 GPIO2 C11 C11 UV1 C11 C11 GPIO1 S11 WDTB OUT C10 C10 UV0 C10 C10 MMB C9 C9 HYST S10 LTC6802-1 TOS 1M 100k C8 C8 LTC6801 CC1 C9 C9 VREG C7 C7 CC0 C8 SC98 VTEVMRPE2F 1µF CC65 CC65 SLTSOLKT S8 VTEMP1 C4 C4 DC C7 C7 NC C3 C3 EOUT S7 V– C2 C2 EOUT C6 C6 S1 C1 C1 SIN S6 C1 V– SIN C5 C5 S2 VTEMP1 SOUT S5 C2 VREF VTEMP2 SOUT C4 C4 S3 VREF EIN S4 C3 1µF VREG EIN 6801 F07 C3 C2 C1 Figure 7. Interconnection of an LTC6802-1 and LTC6801 for Self Test. 6801fc 19 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION CELL-VOLTAGE FILTERING tying both CC1 and CC0 to the V pin, the highest cell REF potential (in this case C8) must be connected to the V+ The LTC6801 employs a sampling system to perform its pin for proper operation. Unused cell connection pins (in analog-to-digital conversions and provides a conversion this case C9 to C12) may be left floating or may also be result that is essentially an average over the 0.5ms conver- tied to the highest cell potential. sion window. If there is significant noise at frequencies near 500kHz there may be aliasing in the delta-sigma modulator. V+ OV1 A lowpass filter with 30dB attenuation at 500kHz may be C12 OV0 beneficial. Since the delta-sigma integration bandwidth is C11 UV1 C10 UV0 about 1kHz, the filter corner need not be lower than this C9 HYST C8 CC1 to assure accurate conversions. C7 LTC6801 CC0 C6 SLT Series resistors of 1k may be inserted in the input paths C5 SLTOK C4 DC without introducing measurement error. Shunt capacitors C3 EOUT 500k 500k 1µF C2 EOUT may be added from the cell inputs to V–, creating RC filter- NTC NTC C1 SIN B = 4567 B = 4567 1µF V– SIN ing as shown in Figure 8. The combination of 1k and 10nF VTEMP1 SOUT is recommended as a robust, cost effective noise filter. VTEMP2 SOUT VREF EIN 100k 100k VREG EIN 6801 F09 MEASURING VARIOUS CELL COUNTS Figure 9. Driving Thermistors Directly from V . REF The LTC6801 is designed to measure up to 12 cells de- Two Independent Probes With a +60°C Trip Point pending on the state of the CC pins (See Table 5). When using an LTC6801 configured for measuring less than V+ OV1 12 cells, for instance choosing to measure 8 cells by C12 OV0 C11 UV1 C10 UV0 C9 HYST C8 CC1 1k C7 LTC6801 CC0 C3 C6 SLT C5 SLTOK C4 DC 1k 10nF C3 EOUT C2 10k 10k 0.5µF C2 EOUT NTC NTC C1 SIN B = 3380 B = 3380 0.5µF V– SIN 1k 10nF VTEMP1 SOUT C1 VTEMP2 SOUT VREF EIN 2.2k 2.2k VREG EIN 10nF 6801 F10 V– + 6801 F08 LT6003 Figure 8. Adding RC Filtering to the Cell inputs – Figure 10. Buffering V for Higher-Current Sensors. REF Two Independent Probes With a +70°C Trip Point 6801fc 20 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION READING EXTERNAL TEMPERATURE PROBES V+ OV1 C12 OV0 The LTC6801 includes two channels of ADC input, V C11 UV1 TEMP1 C10 UV0 and VTEMP2, that are intended to monitor thermistors C9 HYST C8 CC1 (tempco about –4%/°C generally) or diodes (–2.2mV/°C C7 LTC6801 CC0 typical) located within the cell array. Sensors can be C6 SLT C5 SLTOK powered directly from V as shown in Figure 9 (up to C4 DC REF C3 EOUT 30µA typical). 500k 1µF C2 EOUT NTC 1150k C1 SIN The temperature measurement inputs (V , V ) of B = 4567 1µF V– SIN TEMP1 TEMP2 VTEMP1 SOUT the LTC6801 are comparator input channels with a voltage VTEMP2 SOUT 100k VREF EIN threshold of one-half VREF. Input voltages above half VREF 100k NTC VREG EIN are considered good. Voltages below the one-half V B = 4250 6801 F11 REF threshold are considered a fault condition. The inputs Figure 11. Sensing Both Upper and Lower Temperature may be used in combination with resistors, thermistors, Thresholds. This Example Monitors a –20°C to +60°C Window or diodes to sense both an upper and lower temperature Detector. The Thermistors Should Be in Close Proximity limit. Figure 9, Figure 10 and Figure 11 illustrate some possibilities. To ignore these inputs simply connect V For circuits that include filtering capacitance, note that TEMP1 and V to V . A filtering capacitor to V– is recom- only the fastest DC setting (V connection) will keep TEMP2 REF REG mended to minimize the error caused by the approximately V steady and allow the V voltages to settle. To use REF TEMP 700k input impedance of the ADC. the lower power DC settings, V must be buffered (see REF Figure 10), so that a low impedance is presented to the For sensors that require higher drive currents, a buffer ADC, with a time constant of no more than about 1ms. amplifier may be used as shown in Figure 10. Power for the sensor is actually sourced indirectly from the V pin REG in this case. Probe loads up to about 1mA maximum are ADVANTAGES OF DELTA-SIGMA ADCs supported in this configuration. Since V is shut down REF The LTC6801 employs a delta-sigma analog to digital while the LTC6801 is idle between measurement cycles, converter for voltage measurement. The architecture of the thermistor drive is also shut off and thus power dis- delta-sigma converters can vary considerably, but the sipation is minimized. Since V remains always-on, the REG common characteristic is that the input is sampled many buffer op amp (LT6003 shown) is selected for its ultralow times over the course of a conversion and then filtered or current consumption (10µA). averaged to produce the digital output code. 6801fc 21 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION For a given sample rate, a delta-sigma converter can INTERCOMMUNICATION USING DATA ISOLATORS achieve excellent noise rejection while settling completely As shown in Figure 13, an inexpensive and compact in a single conversion. This is particularly important for 2-channel data isolator is used to communicate the enable noisy automotive systems. Other advantages of delta-sigma and the sense clocking signals between devices. The wiring converters are that they are inherently monotonic, meaning carries isolator power and return plus two single-ended they have no missing codes, and they have excellent DC logic signals that are completely isolated at the upper device specifications. interface, so the signals are effectively differential from a The LTC6801’s ADC has a second order delta-sigma common mode ingress perspective. The isolator provides modulator followed by a SINC2, finite impulse response excellent rejection of noise between battery groups, but (FIR) digital filter, with a lowpass bandwidth of 1kHz. The consumes a few mA when operating, so a conventional front-end sample rate is 512ksps, which greatly reduces opto-coupler and a few discretes provide a power-down input filtering requirements. A simple 16kHz, 1 pole filter scheme for periods where no monitoring is needed. Since composed of a 1k resistor and a 10nF capacitor at each the required current would load down V if used directly, REG input will provide adequate filtering for most applications. the NPN transistor is used to form a quasi-regulated 4.3V These component values will not degrade the DC accuracy supply drawing from the full battery group potential, also of the ADC. moving significant thermal loading outside the IC. The PMOS FET is a low resistance switch controlled by the Each conversion consists of two phases – an autozero opto-coupler output. Since the opto-coupler is used to phase and a measurement phase. The ADC is autozeroed switch only a small current, the LED need only be driven at each conversion, greatly improving CMRR. with ~500µA. Powering down the bottom-of-stack isolator on the host µP side automatically powers down the entire USING TRANSFORMERS FOR GALVANIC ISOLATION isolator chain. As shown in Figure 12, small gate-drive signal transform- ers can be used to interconnect devices and transport the DEMO BOARD CIRCUIT enable and sense signals safely across an isolation barrier. An LTC6801 demonstration circuit is shown in Figure 14. Driving a transformer with a squarewave requires transient The circuit includes a 10kHz oscillator (U2) for the enable currents of several mA and frequency of operation at 20kHz excitation and an LED (D15, driven by Q1) to indicate the or higher. Since the output pins of the LTC6801 are current state of the status outputs, plus an assortment of important limited at <1mA, a small external gate pair (NC7WZ17 dual protection components to ensure robust operation and buffer) is used to provide the needed drive current. 330Ω hot-plugging of cell connections. resistors are placed in series with each buffer output to optimize current flow into the transformer primary and a Series resistors (R14 to R21) provide a controlled coupling coupling capacitor provides prevention of current flow in capacitor (C14 to C17) current in the inter-IC connections static conditions. The secondary side is wired in a cen- during startup or other abrupt potential changes, and as- ter-tapped configuration to terminate the common mode sociated clamp diodes (D13 and D14 quad array devices) voltage and thus suppress noise pickup. The differential redirect charge/surge current around the IC. signal is terminated into 1500Ω to optimize the peak signal Input filters to each cell (R1, C1 to R12, C12) also use swing for the IC input (to about ±4V ). Internal biasing P-P 6.2V Zener diodes (D1 to D12) to prevent overstress to features of the IC inputs maintain an optimal DC common the internal ESD clamps. mode level at the transformer secondary. The V+ input filter (R13, C13) has the same time constant as the ADC input filters so that the V+ and C12 pins tend to track during start-up or transients, minimizing stress and ADC error. 6801fc 22 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION TO NEXT CIRCUIT NC7WZ17 100nF 330Ω ENC2+ V+ OV1 C12 LTC6801 OV0 GND V+ 330Ω ENC2– C11 UV1 C10 UV0 10nF C9 HYST C8 CC1 (cid:127) C7 CC0 S2+ C6 SLT (cid:127) C5 SLTOK 1.5k C4 DC (cid:127) S2– C3 EOUT C2 EOUT P0544NL NC7WZ17 C1 SIN 100nF V– SIN 330Ω VTEMP1 SOUT GND V+ 1µF VTEMP2 SOUT 330Ω VREF EIN VREG EIN (cid:127) (cid:127) 1.5k 10nF (cid:127) P0544NL V+ OV1 NC7WZ17 C12 LTC6801 OV0 330Ω 100nF ENC1+ C11 UV1 C10 UV0 GND V+ C9 HYST 330Ω ENC1– C8 CC1 10nF C7 CC0 C6 SLT C5 SLTOK (cid:127) S1+ C4 DC (cid:127) C3 EOUT 1.5k C2 EOUT (cid:127) S1– C1 SIN V– SIN P0544NL VTEMP1 SOUT S_HOST+ 1µF VTEMP2 SOUT S_HOST– VREF EIN EN_HOST+ VREG EIN EN_HOST– 6801 F12 Figure 12. Using Transformers for Galvanic Isolation 6801fc 23 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION V+ OV1 C12 LTC6801 OV0 C11 UV1 C10 UV0 C9 HYST C8 CC1 C7 CC0 TO NEXT C6 SLT CIRCUIT C5 SLTOK COM2 C4 DC 100Ω ENABLE2 C3 EOUT SENSE2 C2 EOUT 1µF VISO2 C1 SIN 1nF V– SIN Si8421 1µF VTEMP1 SOUT VDD1 VDD2 100Ω 1µF VTEMP2 SOUT VREF EIN A1 B1 VREG EIN A2 B2 1nF GND1 GND2 6.8k CZT5551 SI2351DS 33k MOC207-M V+ OV1 C12 LTC6801 OV0 C11 UV1 C10 UV0 C9 HYST C8 CC1 C7 CC0 C6 SLT C5 SLTOK COM1 C4 DC 100Ω ENABLE1 C3 EOUT SENSE1 C2 EOUT 1µF VISO1 C1 SIN 1nF V– SIN Si8421 1µF VTEMP1 SOUT VDD1 VDD2 VCCHOST 100Ω 1µF VTEMP2 SOUT SENSEHOST VREF EIN A1 B1 VREG EIN A2 B2 ENABLEHOST 1nF GND1 GND2 COMHOST 6.8k CZT5551 SI2351DS 33k MOC207-M 6801 F13 Figure 13. IC to IC Communication Using Data Isolators 6801fc 24 For more information www.linear.com/LTC6801

LTC6801 APPLICATIONS INFORMATION –NOTE: IF THE DC PIN IS TIED TO V OR V,REF AND V WILL HAVE ADDITIONALVTEMP1TEMP2MEASUREMENT ERROR DUE TO INSUFFICIENTSETTLING (SEE READING EXTERNAL VTEMPERATURE PROBES)REFVREGGND J2BOTTOM 1234567891011121314C17C16C15C14820pF820pF820pF820pF500V500V500V500V R17100Ω R18R19R20R21D14100Ω100Ω100Ω100ΩPRTR5VOU4D 61 52 43 E4E5E6E7 SOUTEINXEINSOUTX JP8DC R16100Ω 6 5 4 246 JP7CC0135 J3TOP 2468101214 D13R5VOU4D 135791113 PRT 246 JP6JP5CC1HYST211433655 JP9TOPI/O1234LOOPLINK56 R14R15100Ω100Ω 1 2 3 JP11LE01ON35OFF Demo Circuit JP4UV0246 –V E1 SLT E2 SLTOK E3 R2710k1% 6801 F12 C6801 135 T JP3JP2UV1OV0222114443366655 LTC6801IG 36+OV1VLTC680135C12OV034C11UV133C10UV032C9HYST31C8CC130C7CC029C6SLT28C5SLTOK27C4DC26C3EOUT25C2EOUT24C1SIN23–VSIN22VSOUTTEMP121VSOUTTEMP220VEINREF19VEINREG JP10EINX1C19SE31µFDIFF50V5 C231nFR24100kR22NTC1.5kC211%R261nF1.15MD15100VLED1(GRN) 1Q1U22N7002KD163LTC6906CS6CMHD45712116+OUTV2R2825GNDGRD1M34C22DIVSET10nF50VR291M ure 14.Schematic of L JP1OV1135 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 C181µF50V R2322.6k C201nFR25100V100kNTC JP12OSC24ON6OFF Fig C13100nF100V 135 R13100Ω C1210nF100V C1110nF100V C1010nF100V C910nF100V C810nF100V C710nF100V C610nF100V C510nF100V C410nF100V C310nF100V C210nF100V C110nF100V R121k D12 R111k D11 R101k D10R91k D9 R81k D8 R71k D7R61k D6R51k D5 R41k D4 R31k D3 R21k D2 R11k D1 D12: BZT52C6V28 O D1 T P1DGE FINGER16151413121110987654321 J1HEADER 16151413121110987654321 E 6801fc 25 For more information www.linear.com/LTC6801

LTC6801 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.50 – 13.10* (.492 – .516) 1.25 ±0.12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 7.8 – 8.2 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.42 ±0.03 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2.0 5.00 – 5.60** (.079) (.197 – .221) MAX 0° – 8° 0.65 0.09 – 0.25 0.55 – 0.95 (.0256) (.0035 – .010) (.022 – .037) BSC 0.05 NOTE: 0.22 – 0.38 (.002) 1. CONTROLLING DIMENSION: MILLIMETERS (.009 – .015) MIN MILLIMETERS TYP G36 SSOP 0204 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 6801fc 26 For more information www.linear.com/LTC6801

LTC6801 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 5/10 H-grade part added. Reflected throughout the data sheet. 1 to 28 B 7/10 Updated V Conditions. 3 REG Updated Table 3 9 C 8/15 Web links added ALL Typo correction in Overview section 12 6801fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 27 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnectioFno orf mitso crierc iunitfso rams daetsiocnrib wedw hwe.rleiinne wari.llc noomt i/nLfTriCng6e8 0on1 existing patent rights.

LTC6801 TYPICAL APPLICATION 5V FILTERED STATUS VREG (LOW = OK) 1.5k LED_GREEN SOUT 2N7002 10k CMHD457 10nF 1M 6801 F15 Figure 15. Alarm Qualification Filter/Status Indicator RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC6802-1 Multi-Cell Battery Stack Monitor with a Stackable Complete Battery Monitoring IC with 0.25% Cell Measurement Accuracy. Serial Interface Level-Shifting Serial Interface Allows Multiple LTC6802-1 Devices to be Daisy- Chained without Opto-Couplers or Isolators LTC6802-2 Multi-Cell Battery Stack Monitor with an Individually Functionally Equivalent to LTC6802-1: Parallel Connection Between Addressable Serial Interface Microcontroller and Multiple LTC6802-2 Devices 6801fc 28 Linear Technology Corporation LT 0815 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC6801 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC6801  LINEAR TECHNOLOGY CORPORATION 2010

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