LTC6252/LTC6253/LTC6254 720MHz, 3.5mA Power Efficient Rail-to-Rail I/O Op Amps FEATURES DESCRIPTION n Gain Bandwidth Product: 720MHz The LTC®6252/LTC6253/LTC6254 are single/dual/quad low n –3dB Frequency (A = 1): 400MHz power, high speed unity gain stable rail-to-rail input/output V n Low Quiescent Current: 3.5mA Max operational amplifiers. On only 3.5mA of supply current n High Slew Rate: 280V/µs they feature a 720MHz gain-bandwidth product, 280V/µs n Input Common Mode Range Includes Both Rails slew rate and a low 2.75nV/√Hz of input-referred noise. n Output Swings Rail-to-Rail The combination of high bandwidth, high slew rate, low n Low Broadband Voltage Noise: 2.75nV/√Hz power consumption and low broadband noise makes the n Power-Down Mode: 42μA LTC6252 family unique among rail-to-rail input/output op n Fast Output Recovery amps with similar supply currents. They are ideal for lower n Supply Voltage Range: 2.5V to 5.25V supply voltage high speed signal conditioning systems. n Input Offset Voltage: 350µV Max The LTC6252 family maintains high efficiency performance n Large Output Current: 90mA from supply voltage levels of 2.5V to 5.25V and is fully n CMRR: 105dB specified at supplies of 2.7V and 5.0V. n Open Loop Gain: 60V/mV n Operating Temperature Range: –40°C to 125°C For applications that require power-down, the LTC6252 and n Single in 6-Pin TSOT-23 the LTC6253 in MS10 offer a shutdown pin which disables n Dual in MS8, 2mm × 2mm DFN, 8-Pin TS0T-23, MS10 the amplifier and reduces current consumption to 42µA. n Quad in MS16 The LTC6252 family can be used as a plug-in replacement for many commercially available op amps to reduce power APPLICATIONS or to improve input/output range and performance. n Low Voltage, High Frequency Signal Processing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Driving A/D Converters Technology Corporation. All other trademarks are the property of their respective owners. n Rail-to-Rail Buffer Amplifiers n Active Filters n Battery Powered Equipment TYPICAL APPLICATION 5V Single-Supply 16-Bit ADC Driver LTC6253 Driving LTC2393-16 16-Bit ADC 5V Single-Supply Performance 5V 5V 5V 1.8V TO 5V VIN + 0 27.4mV TO 10µF 0.1µF 10µF 0.1µF 4.7µF fS = 1Msps (3.5V + 27.4mV) ½ LTC6253 –20 F1 = 20.111kHz – F1 AMPLITUDE AVP DVP OVP PARALLEL –40 = –1.032dBFS 143Ω 2.5k 2.5k 249Ω 100Ω IN+ SEORRIAL 16 BIT BFS) –60 STHNDR == –9130.208.5d0BdB INTERFACE DE (d –80 SSIFNDARD = = 1 9024..573ddBB 845Ω –½ LTC652V53 390204p9FΩ 100Ω IN– LTC2393-16 BYSTEEROS/WBP/AAC2RPCS AMPLITU––110200 FFFF2345 ==== ––––111100106445....37149038ddddBBBBcccc + REFIN CNVST RESET RD VCM REFOUT PD GND OGND BUSY –140 625234 TA01 –160 ~2.08V 10µF 1µF 0 100 200 300 400 500 SAMPLE CLOCK FREQUENCY (kHz) 624678 TA01b 625234fc 1

LTC6252/LTC6253/LTC6254 ABSOLUTE MAXIMUM RATINGS (Note 1) Total Supply Voltage (V+ to V–) ................................5.5V Specified Temperature Range (Note 5) ..–40°C to 125°C Input Current (+IN, –IN, SHDN) (Note 2) ..............±10mA Storage Temperature Range ..................–65°C to 150°C Output Current (Note 3) .....................................±100mA Junction Temperature ...........................................150°C Operating Temperature Range (Note 4)..–40°C to 125°C Lead Temperature (Soldering, 10 sec) MSOP, TSOT Packages Only .............................300°C PIN CONFIGURATION TOP VIEW TOP VIEW OUT A 1 8 V+ TOP VIEW OUT 1 6 V+ –IN A 2 – 7 OUT B OUT A 1 8V+ V– 2 + – 5 SHDN +IN A 3 + – 6 –IN B –+IINN AA 23 +– – 76O–IUNT B B +IN 3 4 –IN V– 4 9 + 5 +IN B V– 4 + 5+IN B MS8 PACKAGE S6 PACKAGE 6-LEAD PLASTIC TSOT-23 DC PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150°C, qJA = 192°C/W (NOTE 9 ) T8JM-LAEXA =D 1 (225m°Cm, q×J A2 =m 1m0)2 °PCL/AWS (TNICO TDEF N9) TJMAX = 150°C, qJA = 163°C/W (NOTE 9) EXPOSED PAD (PIN 9) IS V–, MUST BE SOLDERED TO PCB TOP VIEW TOP VIEW TOP VIEW OUT A 1 16 OUT D OUT A 1 10 V+ OUT A 1 8 V+ –IN A 2 – – 15 –IN D –+IINNV AA– 234 +– +– 987 O–+IIUNNT BB B –+IINN AA 23 +– – 76 O–IUNT B B ++IINNV AB+ 345 ++ ++ 111432 +V+II–NN DC SHDNA 5 6 SHDNB V– 4 + 5 +IN B –IN B 6 – – 11 –IN C OUT B 7 10 OUT C MS PACKAGE TS8 PACKAGE 8 9 10-LEAD PLASTIC MSOP 8-LEAD PLASTIC TSOT-23 MS PACKAGE TJMAX = 150°C, qJA = 160°C/W (NOTE 9) TJMAX = 150°C, qJA = 195°C/W (NOTE 9) 16-LEAD PLASTIC MSOP TJMAX = 150°C, qJA = 125°C/W (NOTE 9) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6252CS6#TRMPBF LTC6252CS6#TRPBF LTFRW 6-Lead Plastic TSOT-23 0°C to 70°C LTC6252IS6#TRMPBF LTC6252IS6#TRPBF LTFRW 6-Lead Plastic TSOT-23 –40°C to 85°C LTC6252HS6#TRMPBF LTC6252HS6#TRPBF LTFRW 6-Lead Plastic TSOT-23 –40°C to 125°C LTC6253CDC#TRMPBF LTC6253CDC#TRPBF LFRZ 8-Lead (2mm × 2mm) Plastic DFN 0°C to 70°C LTC6253IDC#TRMPBF LTC6253IDC#TRPBF LFRZ 8-Lead (2mm × 2mm) Plastic DFN –40°C to 85°C LTC6253CMS8#PBF LTC6253CMS8#TRPBF LTFRX 8-Lead Plastic MSOP 0°C to 70°C LTC6253IMS8#PBF LTC6253IMS8#TRPBF LTFRX 8-Lead Plastic MSOP –40°C to 85°C LTC6253HMS8#PBF LTC6253HMS8#TRPBF LTFRX 8-Lead Plastic MSOP –40°C to 125°C LTC6253CTS8#TRMPBF LTC6253CTS8#TRPBF LTFRY 8-Lead Plastic TSOT-23 0°C to 70°C LTC6253ITS8#TRMPBF LTC6253ITS8#TRPBF LTFRY 8-Lead Plastic TSOT-23 –40°C to 85°C LTC6253HTS8#TRMPBF LTC6253HTS8#TRPBF LTFRY 8-Lead Plastic TSOT-23 –40°C to 125°C 625234fc 2

LTC6252/LTC6253/LTC6254 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6253CMS#PBF LTC6253CMS#TRPBF LTFSB 10-Lead Plastic MSOP 0°C to 70°C LTC6253IMS#PBF LTC6253IMS#TRPBF LTFSB 10-Lead Plastic MSOP –40°C to 85°C LTC6254CMS#PBF LTC6254CMS#TRPBF 6254 16-Lead Plastic MSOP 0°C to 70°C LTC6254IMS#PBF LTC6254IMS#TRPBF 6254 16-Lead Plastic MSOP –40°C to 85°C LTC6254HMS#PBF LTC6254HMS#TRPBF 6254 16-Lead Plastic MSOP –40°C to 125°C TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS (VS = 5V) The l denotes the specifications which apply across the specified temperature range, otherwise specifications are at T = 25°C. For each amplifier V = 5V, 0V; V = 2V; V = V = A S SHDN CM OUT 2.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage V = Half Supply –350 50 350 µV OS CM l –1000 1000 µV V = V+ – 0.5V, NPN Mode –2.2 0.1 2.2 mV CM l –3.3 –3.3 mV DVOS Input Offset Voltage Match VCM = Half Supply –350 50 350 µV (Channel-to-Channel) (Note 8) l –550 550 µV V = V+ – 0.5V, NPN Mode –2.75 0.1 2.75 mV CM l –4 4 mV V T Input Offset Voltage Drift l –3.5 µV/°C OS C I Input Bias Current (Note 7) V = Half Supply –0.75 –0.1 0.75 µA B CM l –1.15 1.15 µA V = V+ – 0.5V, NPN Mode 0.8 1.4 3.0 µA CM l 0.4 5.0 µA I Input Offset Current V = Half Supply –0.5 –0.03 0.5 µA OS CM l –0.6 0.6 µA V = V+ – 0.5V, NPN Mode –0.5 –0.03 0.5 µA CM l –0.6 0.6 µA e Input Noise Voltage Density f = 1MHz 2.75 nV/√Hz n Input 1/f Noise Voltage f = 0.1Hz to 10Hz 2 µV P-P i Input Noise Current Density f = 1MHz 4 pA/√Hz n C Input Capacitance Differential Mode 2.5 pF IN Common Mode 0.8 pF R Input Resistance Differential Mode 7.2 kΩ IN Common Mode 3 MΩ A Large Signal Voltage Gain R = 1k to Half Supply (Note 10) 35 60 V/mV VOL L l 16 V/mV R = 100Ω to Half Supply (Note 10) 5 13 V/mV L l 2.4 V/mV CMRR Common Mode Rejection Ratio V = 0V to 3.5V 85 105 dB CM l 82 dB 625234fc 3

LTC6252/LTC6253/LTC6254 ELECTRICAL CHARACTERISTICS (VS = 5V) The l denotes the specifications which apply across the specified temperature range, otherwise specifications are at T = 25°C. For each amplifier V = 5V, 0V; V = 2V; V = V = A S SHDN CM OUT 2.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Common Mode Range l 0 V V CMR S PSRR Power Supply Rejection Ratio V = 2.5V to 5.25V 66.5 70 dB S V = 1V l 62 dB CM Supply Voltage Range (Note 6) l 2.5 5.25 V V Output Swing Low (V – V–) No Load 25 40 mV OL OUT l 65 mV I = 5mA 60 90 mV SINK l 120 mV I = 25mA 150 200 mV SINK l 320 mV V Output Swing High (V+ – V ) No Load 65 100 mV OH OUT l 120 mV I = 5mA 115 170 mV SOURCE l 210 mV I = 25mA 270 330 mV SOURCE l 450 mV I Output Short-Circuit Current Sourcing –90 –40 mA SC l –32 mA Sinking 60 100 mA l 40 mA I Supply Current per Amplifier V = Half Supply 3.3 3.5 mA S CM l 4.8 mA V = V+ – 0.5V 4.25 4.85 mA CM l 5.9 mA I Disable Supply Current V = 0.8V 42 55 µA SD SHDN l 75 µA I SHDN Pin Current Low V = 0.8V –3 –1.6 0 µA SHDNL SHDN l –4 0 µA I SHDN Pin Current High V = 2V –300 35 300 nA SHDNH SHDN l –600 600 nA V SHDN Pin Input Voltage Low l 0.8 V L V SHDN Pin Input Voltage High l 2 V H I Output Leakage Current in Shutdown V = 0.8V, Output Shorted to Either 100 nA OSD SHDN Supply t Turn-On Time V = 0.8V to 2V 3.5 µs ON SHDN t Turn-Off Time V = 2V to 0.8V 2 µs OFF SHDN BW –3dB Closed Loop Bandwidth A = 1, R = 1k to Half Supply 400 MHz V L GBW Gain-Bandwidth Product f = 4MHz, R = 1k to Half Supply 450 720 MHz L l 320 MHz t , 0.1% Settling Time to 0.1% A = 1, V = 2V Step R = 1k 36 ns S V O L SR Slew Rate A = –1, 4V Step (Note 11) 280 V/µs V FPBW Full Power Bandwidth V = 4V (Note 13) 9.5 MHz OUT P-P 625234fc 4

LTC6252/LTC6253/LTC6254 E LECTRICAL CHARACTERISTICS (VS = 5V) The l denotes the specifications which apply across the specified temperature range, otherwise specifications are at T = 25°C. For each amplifier V = 5V, 0V; V = 2V; V = V = A S SHDN CM OUT 2.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS HD2/HD3 Harmonic Distortion f = 100kHz, V = 2V 99/109 dBc C O P-P R = 1k to Half Supply f = 1MHz, V = 2V 97/104 dBc L C O P-P f = 2.5MHz, V = 2V 83/82 dBc C O P-P f = 4MHz, V = 2V 77/71 dBc C O P-P R = 100Ω to Half Supply f = 100kHz, V = 2V 97/90 dBc L C O P-P f = 1MHz, V = 2V 95/70 dBc C O P-P f = 2.5MHz, V = 2V 87/65 dBc C O P-P f = 4MHz, V = 2V 78/59 dBc C O P-P DG Differential Gain (Note 14) AV = 2, RL = 150Ω, VS = ±2.5V 0.1 % A = 1, R = 1kΩ, V = ±2.5V 0.02 % V L S Dq Differential Phase (Note 14) AV = 2, RL = 150Ω, VS = ±2.5V 0.25 Deg A = 1, R = 1kΩ, V = ±2.5V 0.05 Deg V L S Crosstalk A = –1, R = 1k to Half Supply, –96 dB V L V = 2V , f = 2.5MHz OUT P-P E LECTRICAL CHARACTERISTICS (VS = 2.7V) The l denotes the specifications which apply across the specified temperature range, otherwise specifications are at T = 25°C. For each amplifier V = 2.7V, 0V; V = 2V; V = V = A S SHDN CM OUT 1.35V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage V = Half Supply 0 700 1250 µV OS CM l –300 1500 µV V = V+ – 0.5V, NPN Mode –1.6 0.9 3.2 mV CM l –2.0 3.4 mV DVOS Input Offset Voltage Match VCM = Half Supply –350 10 350 µV (Channel-to-Channel) (Note 8) l –750 750 µV V = V+ – 0.5V, NPN Mode –2.8 0.1 2.8 mV CM l –4 4 mV V T Input Offset Voltage Drift l 2.75 µV/°C OS C I Input Bias Current (Note 7) V = Half Supply –1000 –275 600 nA B CM l –1500 900 nA V = V+ – 0.5V, NPN Mode 0.6 1.175 2.5 µA CM l 0 4.0 µA I Input Offset Current V = Half Supply –500 –150 500 nA OS CM l –600 600 nA V = V+ – 0.5V, NPN Mode –500 –30 500 nA CM l –600 600 nA e Input Noise Voltage Density f = 1MHz 2.9 nV/√Hz n Input 1/f Noise Voltage f = 0.1Hz to 10Hz 2 µV P-P i Input Noise Current Density f = 1MHz 3.6 pA/√Hz n C Input Capacitance Differential Mode 2.5 pF IN Common Mode 0.8 pF R Input Resistance Differential Mode 7.2 kΩ IN Common Mode 3 MΩ A Large Signal Voltage Gain R = 1k to Half Supply 16.5 36 V/mV VOL L (Note 12) l 7 V/mV R = 100Ω to Half Supply 2.3 6.9 V/mV L (Note 12) l 1.8 V/mV 625234fc 5

LTC6252/LTC6253/LTC6254 ELECTRICAL CHARACTERISTICS (VS = 2.7V) The l denotes the specifications which apply across the specified temperature range, otherwise specifications are at T = 25°C. For each amplifier V = 2.7V, 0V; V = 2V; V = V = A S SHDN CM OUT 1.35V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMRR Common Mode Rejection Ratio V = 0V to 1.2V 80 105 dB CM l 77 dB V Input Common Mode Range l 0 V V CMR S PSRR Power Supply Rejection Ratio V = 2.5V to 5.25V 66.5 70 dB S V = 1V l 62 dB CM Supply Voltage Range (Note 6) l 2.5 5.25 V V Output Swing Low (V – V–) No Load 22 28 mV OL OUT l 40 mV I = 5mA 80 100 mV SINK l 140 mV I = 10mA 110 150 mV SINK l 190 mV V Output Swing High (V+ – V ) No Load 55 75 mV OH OUT l 95 mV I = 5mA 125 150 mV SOURCE l 200 mV I = 10mA 165 200 mV SOURCE l 275 mV I Short-Circuit Current Sourcing –35 –18 mA SC l –14 mA Sinking 20 40 mA l 17 mA I Supply Current per Amplifier V = Half Supply 2.9 3.5 mA S CM l 4.5 mA V = V+ – 0.5V 3.7 4.6 mA CM l 5.5 mA I Disable Supply Current V = 0.8V 24 35 µA SD SHDN l 50 µA I SHDN Pin Current Low V = 0.8V –1 –0.5 0 µA SHDNL SHDN l –1.5 0 µA I SHDN Pin Current High V = 2V –300 45 300 nA SHDNH SHDN l –600 600 nA V SHDN Pin Input Voltage l 0.8 V L V SHDN Pin Input Voltage l 2.0 V H I Output Leakage Current Magnitude in Shutdown V = 0.8V, Output Shorted to Either Supply 100 nA OSD SHDN t Turn-On Time V = 0.8V to 2V 5 µs ON SHDN t Turn-Off Time V = 2V to 0.8V 2 µs OFF SHDN BW –3dB Closed Loop Bandwidth A = 1, R = 1k to Half Supply 350 MHz V L GBW Gain-Bandwidth Product f = 4MHz, R = 1k to Half Supply 630 MHz L t , 0.1 Settling Time to 0.1% A = +1, V = 2V Step R = 1k 34 ns S V O L SR Slew Rate A = –1, 2V Step (Note 11) 170 V/µs V FPBW Full Power Bandwidth V = 2V (Note 13) 8.5 MHz OUT P-P Crosstalk A = –1, R = 1k to Half Supply, 96 dB V L V = 2V , f = 2.5MHz OUT P-P 625234fc 6

LTC6252/LTC6253/LTC6254 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: Supply voltage range is guaranteed by power supply rejection ratio may cause permanent damage to the device. Exposure to any Absolute test. Maximum Rating condition for extended periods may affect device Note 7: The input bias current is the average of the average of the currents reliability and lifetime. at the positive and negative input pins. Note 2: The inputs are protected by back-to-back diodes. If any of Note 8: Matching parameters are the difference between amplifiers A and the input or shutdown pins goes 300mV beyond either supply or the D and between B and C on the LTC6254; between the two amplifiers on the differential input voltage exceeds 1.4V the input current should be limited LTC6253. to less than 10mA. This parameter is guaranteed to meet specified Note 9: Thermal resistance varies with the amount of PC board metal performance through design and/or characterization. It is not production connected to the package. The specified values are with short traces tested. connected to the leads with minimal metal area. Note 3: A heat sink may be required to keep the junction temperature Note 10: The output voltage is varied from 0.5V to 4.5V during below the absolute maximum rating when the output current is high. This measurement. parameter is guaranteed to meet specified performance through design Note 11: Middle 2/3 of the output waveform is observed. R = 1k to half and/or characterization. It is not production tested. L supply. Note 4: The LTC6252C/LTC6253C/LTC6254C and LTC6252I/LTC6253I/ Note 12: The output voltage is varied from 0.5V to 2.2V during LTC6254I are guaranteed functional over the temperature range of –40°C measurement. to 85°C. The LTC6252H/LTC6253H/LTC6254H are guaranteed functional Note 13: FPBW is determined from distortion performance in a gain of +2 over the temperature range of –40°C to 125°C. configuration with HD2, HD3 < –40dBc as the criteria for a valid output. Note 5: The LTC6252C/LTC6253C/LTC6254C are guaranteed to meet Note 14: Differential gain and phase are measured using a Tektronix specified performance from 0°C to 70°C. The LTC6252C/LTC6253C/ TSG120YC/NTSC signal generator and a Tektronix 1780R video LTC6254C are designed, characterized and expected to meet specified measurement set. performance from –40°C to 85°C but are not tested or QA sampled at these temperatures. The LTC6252I/LTC6253I/LTC6254I are guaranteed to meet specified performance from –40°C to 85°C. The LTC6252H/ LTC6253H/LTC6254H are guaranteed to meet specified performance from –40°C to 125°C. TYPICAL PERFORMANCE CHARACTERISTICS V Distribution, V = V /2 V Distribution, V = V /2 V Distribution, V = V+ – 0.5V OS CM S OS CM S OS CM (MS, PNP Stage) (TSOT-23, PNP Stage) (MS, NPN Stage) 40 40 16 VS = 5V, 0V VS = 5V, 0V VS = 5V, 0V 35 VCM = 2.5V 35 VCM = 2.5V 14 VCM = 4.5V %) 30 %) 30 %) 12 NITS ( 25 NITS ( 25 NITS ( 10 U U U OF 20 OF 20 OF 8 CENT 15 CENT 15 CENT 6 R R R PE 10 PE 10 PE 4 5 5 2 0 0 0 –250 –150 –50 50 150 250 –250 –150 –50 50 150 250 –2000 –1200 –400 400 1200 2000 INPUT OFFSET VOLTAGE (µV) INPUT OFFSET VOLTAGE (µV) INPUT OFFSET VOLTAGE (µV) 625234 G01 625234 G02 625234 G03 625234fc 7

LTC6252/LTC6253/LTC6254 TYPICAL PERFORMANCE CHARACTERISTICS V Distribution, V = V+ – 0.5V V vs Temperature, V = 5V, 0V V vs Temperature, V = 5V, 0V OS CM OS S OS S (TSOT-23, NPN Stage) (MS, PNP Stage) (MS, NPN Stage) 18 300 2000 VS = 5V, 0V VS = 5V, 0V 16 VCM = 4.5V 200 VCM = 2.5V 1500 6 DEVICES 14 100 1000 %) V) V) TS ( 12 T (µ 0 T (µ 500 RCENT OF UNI 1086 OLTAGE OFFSE–––123000000 OLTAGE OFFSE–1–0500000 PE V V 4 –400 –1500 VS = 5V, 0V 2 –500 –2000 VCM = 4.5V 6 DEVICES 0 –600 –2500 –2000 –1200 –400 400 1200 2000 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 INPUT OFFSET VOLTAGE (µV) TEMPERATURE (°C) TEMPERATURE (°C) 625234 G04 625234 G05 625234 G06 V vs Temperature, V vs Temperature, Offset Voltage OS OS V = 2.7V, 0V (MS, PNP Stage) V = 2.7V, 0V (MS, NPN Stage) vs Input Common Mode Voltage S S 1200 3200 600 1100 VVSC M= =2 .17.V3, 50VV 2700 400 VS = 5V, 0V 6 DEVICES 200 –55°C 2200 1000 0 VOLTAGE OFFSET (µV) 897600000000 VOLTAGE OFFSET (µV)11–727230000000000 OFFSET VOLTAGE (µV)––––––11246820000000000000 125°C 25°C –1400 –800 500 VS = 2.7V, 0V –1600 –1300 VCM = 2.2V –1800 6 DEVICES 400 –1800 –2000 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 TEMPERATURE (°C) TEMPERATURE (°C) INPUT COMMON MODE VOLTAGE (V) 625234 G07 625234 G08 625234 G09 Input Bias Current Offset Voltage vs Output Current Warm-Up Drift vs Time vs Common Mode Voltage 3.0 20 3000 2.5 VS = ±2.5V TVAS == 2±52°.5CV 2000 VS = 5V, 0V 125°C 2.0 V) 25°C µ GE (mV) 101...550 VOLTAGE ( 15 RENT (nA) 10000 –55°C OFFSET VOLTA –––101...0055 25–°5C5°C 125°C NGE IN OFFSET 105 NPUT BIAS CUR–––312000000000 A I –2.0 CH –4000 –2.5 –3.0 0 –5000 –100 –75 –50 –25 0 25 50 75 100 0 20 40 60 80 100 120 140 160 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 OUTPUT CURRENT (mA) TIME AFTER POWER-UP (sec) COMMON MODE VOLTAGE (V) 625234 G10 625234 G11 625234 G12 625234fc 8

LTC6252/LTC6253/LTC6254 TYPICAL PERFORMANCE CHARACTERISTICS Input Noise Voltage and Noise Input Bias Current vs Temperature 0.1Hz to 10Hz Voltage Noise Current vs Frequency 3000 2000 1000 VS = 5V, 0V 2500 1500 INPUT BIAS CURRENT (nA)211055000000000 VCM = 2V.C5MV = 4.5V VOLTAGE NOISE (500nV/DIV)–11–0505000000000 VOLTAGE NOISE (nV/√Hz)CURRENT NOISE (pA/√Hz)1101.000 en, VCM = 2.5V en, VCM =in ,4 V.5CVM = 2.5V 0 –1500 in, VCM = 4.5V –500 –2000 0.1 –55 –25 5 35 65 95 125 0 1 2 3 4 5 6 7 8 9 10 1 10 100 1k 10k 100k 1M 10M100M TEMPERATURE (°C) TIME (1s/DIV) FREQUENCY (Hz) 624678 G13 624678 G14 624678 G15 Supply Current Supply Current vs Input Common Supply Current Per Amplifier vs Supply Voltage (Per Amplifier) Mode Voltage (Per Amplifier) vs SHDN Pin Voltage 5.0 5 5.0 VS = 5V, 0V VS = 5V, 0V 4.5 AV = 1 4.5 VCM = 2.5V 4.0 4.0 TA = 125°C NT (mA) 33..50 125°C 25°C NT (mA) 4 125°C NT (mA) 33..50 TTAA == –2555°C°C E E E R R R R 2.5 –55°C R 25°C R 2.5 U U U C C C LY 2.0 LY LY 2.0 UPP 1.5 UPP 3 –55°C UPP 1.5 S S S 1.0 1.0 0.5 0.5 0 2 0 0 1 2 3 4 5 0.25 1.25 2.25 3.25 4.254.75 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 TOTAL SUPPLY VOLTAGE (V) COMMON MODE VOLTAGE (V) SHDN PIN VOLTAGE (V) 625234 G16 625234 G17 625234 G18 SHDN Pin Current Minimum Supply Voltage, Minimum Supply Voltage, vs SHDN Pin Voltage V = V /2 (PNP Operation) V = V+ – 0.5V (NPN Operation) CM S CM 0.50 16 16 0.25 VS = 5V, 0V VS = 5V, 0V VS = 5V, 0V 14 14 0 –0.25 12 12 URRENT (µA)––––0011....57020505 TTAA == 2–55°5C°C LTAGE (mV)108 –55°C LTAGE (mV)1086 –55°C SHDN PIN C––––1122....57020505 TA = 125°C OFFSET VO 642 25°C125°C OFFSET VO 420 25°C125°C –2.50 0 –2 –2.75 –3.00 –2 –4 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 SHDN PIN VOLTAGE (V) TOTAL SUPPLY VOLTAGE (V) TOTAL SUPPLY VOLTAGE (V) 625234 G19 625234 G20 625234 G21 625234fc 9

LTC6252/LTC6253/LTC6254 TYPICAL PERFORMANCE CHARACTERISTICS Output Saturation Voltage Output Saturation Voltage Output Short-Circuit Current vs Load Current (Output High) vs Load Current (Output Low) vs Supply Voltage 10 10 160 OLTAGE (V) VS = ±2.5V OLTAGE (V) VS = ±2.5V RENT (mA) 12800 SINK TTAA = = 2 –55°5C°C TA = 125°C ATION V 1 TA = 125°C ATION V 1 UIT CUR 40 PULSE TESTED PUT HIGH SATUR 0.1 TA = 25°C TA = –55°C PUT HIGH SATUR 0.1 TA = 25°C TA T=A 1 =2 5–°5C5°C PUT SHORT-CIRC ––48000 TA = 25°C TA = 125°C OUT OUT OUT –120 SOURCE TA = –55°C 0.01 0.01 –160 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1.25 1.5 1.75 2 2.25 2.5 LOAD CURRENT (mA) LOAD CURRENT (mA) TOTAL SUPPLY VOLTAGE (±V) 625234 G22 625234 G23 625234 G24 Open Loop Gain Open Loop Gain Gain vs Frequency (A = 1) V 500 1600 2 400 TVAS == 255V,° C0V 11420000 RL = 100Ω TO MID SUPPLY TVAS == 225.7°VC, 0V 0 UT OFFSET VOLTAGE (µV)––3211200000000000 RRLL = = 1 1k0 T0OΩ G TNOD MRIDL S= U1Pk PTLOY MID SUPPLY UT OFFSET VOLTAGE (µV)16804200000000000 RL = 1k TO GNDRL = 1k TO MID SUPPLY GAIN (dB) –––624 INP–300 RL = 100Ω TO GND INP–200 RL = 100Ω TO GND –8 VS = ±2.5V –400 –400 TA = 25°C RL = 1k –500 –600 –10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 0.01 0.1 1 10 100 1000 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) FREQUENCY (MHz) 625234 G25 625234 G26 625234 G27 Open Loop Gain and Phase Gain Bandwidth and Phase Gain vs Frequency (A = 2) vs Frequency Margin vs Supply Voltage V 10 75 120 900 70 TA = 25°C 8 65 RL = 1k 105 850 PHASE MARGIN 60 GAIN GAIN (dB) 2064 GAIN (dB) 23455555 PHASE VS = ±1.35V VS = ±2.5V 46795050 PHASE (DEG) N BANDWIDTH (MHz)877605050000 GAIN BANDWIDTH PRODUCT 54320000PHASE MARGIN (DE –2 VS = ±2.5V 15 VS = ±1.35V 30 GAI600 10G) TA = 25°C –4 RRLF == R1kG = 500 5 VS = ±2.5V 15 550 RTAL == 215k°C 0 –6 –5 0 500 –10 0.01 0.1 1 10 100 1000 300k 1M 10M 100M 1G 2.5 3 3.5 4 4.5 5 5.25 FREQUENCY (MHz) FREQUENCY (Hz) TOTAL SUPPLY VOLTAGE (V) 625234 G28 625234 G29 625234 G30 625234fc 10

LTC6252/LTC6253/LTC6254 TYPICAL PERFORMANCE CHARACTERISTICS Gain Bandwidth and Phase Common Mode Rejection Ratio Margin vs Temperature Output Impedance vs Frequency vs Frequency 1200 80 1000 110 1100 RTAL == 215k°C PHASE MARGIN VS = ±2.5V 70 100 VS = ±2.5V O (dB) 90 VS = ±2.5V GAIN BANDWIDTH (MHz)1908700000000 GAIN BANDWIDTHVV PSSR ==O ±±D12U..35C5VTV 65430000 PHASE MARGIN (DEG) OUTPUT IMPEDANCE (Ω) 01.011 AV = 10 AAVV = = 2 1 ON MODE REJECTION RATI 753000 M 600 20 0.01 M 10 O VS = ±1.35V C 500 10 0.001 –10 –55 –35 –15 5 25 45 65 85 105 125 0.1 1 10 100 1000 10k 100k 1M 10M 100M 1G TEMPERATURE (°C) FREQUENCY (MHz) FREQUENCY (Hz) 625234 G31 625234 G32 625234 G33 Power Supply Rejection Ratio Series Output Resistor vs Frequency Slew Rate vs Temperature vs Capacitive Load (A = 1) V 80 360 80 UPPLY REJECTION RATIO (dB) 543276000000 +PSRR –PVSSR =R ±2.5V SLEW RATE (V/µs)333222221240846208000000000 VFAS L=L ±IN2G.5,V VFSA =L L±I1N.3G5, VVSR =IRS I±ISN2I.GN5,GV V, SV S= =± 2±.15.V35V OVERSHOOT (%) 7654300000 VS = ±R2S. 5=V 2V0IΩN RS =+– 10Ω RS VOCULT S 20 ER 10 160 AV = –1, RL = 1k, POW 0 114200 VSOLEUWT = R 4AVTPE- PM (E±A2S.5UVR),E 2DV APT-P (±1.35V) 10 RS = 50Ω MIDDLE 2/3 OF OUTPUT –10 100 0 10 100 1k 10k 100k 1M 10M100M 1G –55 –30 5 20 45 70 95 120 10 100 1000 10000 FREQUENCY (Hz) TEMPERATURE (°C) CAPACITIVE LOAD (pF) 625234 G34 625234 G35 625234 G36 Series Output Resistor Distortion vs Frequency Distortion vs Frequency vs Capacitive Load (AV = 2) (AV = 1, 5V) (AV = 1, 2.7V) 100 –20 –20 90 VS = ±2.5V 500Ω –30 VVSO U=T ±=2 2.5VVP-P –30 RL = 100Ω, 3RD 80 500Ω – RS –40 AV = 1 –40 RL = 100Ω, 2ND VERSHOOT (%) 76540000 VIN + VOCULT STORTION (dBc)–––––5678900000 RL = 100Ω, 3RD RL = 1k, 2ND STORTION (dBc)–––––5678900000 RL = 1k, 2RNL D= 1k, 3RD O 30 RS = 20Ω DI DI –100 –100 20 RS = 10Ω –110 RL = 100Ω, 2ND –110 VS = ±1.35V 10 RS = 50Ω –120 RL = 1k, 3RD –120 VAOV U=T 1= 1VP-P 0 –130 –130 10 100 1000 10000 0.01 0.1 1 10 100 0.01 0.1 1 10 100 CAPACITIVE LOAD (pF) FREQUENCY (MHz) FREQUENCY (MHz) 625234 G37 625234 G38 625234 G39 625234fc 11

LTC6252/LTC6253/LTC6254 TYPICAL PERFORMANCE CHARACTERISTICS Distortion vs Frequency Distortion vs Frequency Maximum Undistorted Output (A = 2, 5V) A = 2, 2.7V) Signal vs Frequency V V –20 –20 6 –30 VVSO U=T ±=2 2.5VVP-P –30 VVSO U=T ±=1 1.3V5PV-P AAVV == 2–1 –40 AV = 2 –40 AV = 2 )P-P5 DISTORTION (dBc)––––––1567890000000 RL = 1R0L0 =Ω 1, k3,R 3DRD RL = 100Ω, 2ND DISTORTION (dBc)––––––1567890000000 RL = 100Ω, 2RNLD = 100Ω, 3RRDL = 1k, 3RD TPUT VOLTAGE SWING (V 432 VS = ±2.5V –110 RL = 1k, 2ND –110 RL = 1k, 2ND OU 1 TA = 25°C –120 –120 RL = 1k HD2, HD3 < –40dBc –130 –130 0 0.01 0.1 1 10 100 0.01 0.1 1 10 100 0.01 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 625234 G40 625234 G41 625234 G42 0.1% Settling Time 0.1% Settling Time vs Output Step (Noninverting) vs Output Step (Inverting) SHDN Pin Response Time 50 60 4450 ATVASV === 2±152°.5CV – VOUT 5550 ATVASV === 2±–521°.5CV 2.5VVS/HDDIVN VIN + 45 0V ns) 35 1k ns) 40 ME ( 30 ME ( 35 NG TI 25 NG TI 30 500Ω VOUT SETTLI 1250 SETTLI 122505 VIN 500Ω +– VOUT 0.8V/D0IVV 10 10 1k 5 5 0 0 –4 –3 –2 –1 0 1 2 3 4 –4 –3 –2 –1 0 1 2 3 4 2µs/DIV 625234 G45 OUTPUT STEP (V) OUTPUT STEP (V) AV = 1 625234 G43 625234 G44 VS = ±2.5V RL = 1k VIN = 1.6V Large Signal Response Small Signal Response Output Overdriven Recovery INPUT VIN (50mV/DIV) 1V/DIV 1V/DIV 0V 0V 0V OUTPUT VOUT (50mV/DIV) 2V/DIV 0V 0V 100ns/DIV 625234 G46 20ns/DIV 625234 G47 20ns/DIV 625234 G48 AV = 1 VS = ±2.5V AV = ±2, TA = 25°C VS = ±2.5V RL = 1k VS = ±2.5V, VIN = 3VP-P TA = 25°C RL = 1k, RF = RG = 500Ω RL = 1k 625234fc 12

LTC6252/LTC6253/LTC6254 PIN FUNCTIONS –IN: Inverting Input of Amplifier. Input range from V– V– : Negative Supply Voltage. Typically 0V. This can be made to V+. a negative voltage as long as 2.5V ≤ (V+ – V–) ≤ 5.25V. +IN: Non-Inverting Input of Amplifier. Input range from SHDN: Active Low Shutdown. Threshold is typically 1.1V V– to V+. referenced to V–. Floating this pin will turn the part on. V+ : Positive Supply Voltage. Total supply voltage ranges OUT: Amplifier Output. Swings rail-to-rail and can typically from 2.5V to 5.25V. source/sink over 90mA of current at a total supply of 5V. APPLICATIONS INFORMATION Circuit Description The LTC6252/LTC6253/LTC6254 have an input and output and the PNP pair becomes inactive for the remaining input signal range that extends from the negative power supply common mode range. Also, at the input stage, devices Q17 to the positive power supply. Figure 1 depicts a simplified to Q19 act to cancel the bias current of the PNP input pair. schematic of the amplifier. The input stage is comprised When Q1/Q2 are active, the current in Q16 is controlled to of two differential amplifiers, a PNP stage, Q1/Q2, and an be the same as the current in Q1 and Q2. Thus, the base NPN stage, Q3/Q4 that are active over different common current of Q16 is nominally equal to the base current of mode input voltages. The PNP stage is active between the input devices. The base current of Q16 is then mirrored the negative supply to nominally 1.2V below the positive by devices Q17 to Q19 to cancel the base current of the supply. As the input voltage approaches the positive sup- input devices Q1/Q2. A pair of complementary common ply, the transistor Q5 will steer the tail current, I , to the emitter stages, Q14/Q15, enable the output to swing from 1 current mirror, Q6/Q7, activating the NPN differential pair rail-to-rail. V+ R3 R4 R5 V+ V– + ESDD1 ESDD2 + I2 I1 Q11 Q12 Q13 Q15 +IN C2 + D6 D8 Q5 VBIAS I3 ESDD5 D5 D7 CC V– –IN Q4 Q3 Q1 Q2 OUT ESDD4 ESDD3 BUFFER Q10 AND OUTPUT BIAS ESDD6 Q16 V– V+ Q9 Q8 Q17 Q18 C1 Q19 Q7 Q6 Q14 R1 R2 V– 625234 F01 Figure 1. LTC6252/LTC6253/LTC6254 Simplified Schematic Diagram 625234fc 13

LTC6252/LTC6253/LTC6254 APPLICATIONS INFORMATION Input Offset Voltage Input Protection The offset voltage will change depending upon which The LTC6252/LTC6253/LTC6254 input stages are protected input stage is active. The PNP input stage is active from against a large differential input voltage of 1.4V or higher the negative supply rail to approximately 1.2V below the by 2 pairs of back-to-back diodes to prevent the emitter- positive supply rail, then the NPN input stage is activated base breakdown of the input transistors. In addition, the for the remaining input range up to the positive supply rail input and shutdown pins have reverse biased diodes con- with the PNP stage inactive. The offset voltage magnitude nected to the supplies. The current in these diodes must for the PNP input stage is trimmed to less than 350µV with be limited to less than 10mA. The amplifiers should not be 5V total supply at room temperature, and is typically less used as comparators or in other open loop applications. than 150μV. The offset voltage for the NPN input stage is less than 2.2mV with 5V total supply at room temperature. ESD The LTC6252 family has reverse-biased ESD protection Input Bias Current diodes on all inputs and outputs as shown in Figure 1. The LTC6252 family uses a bias current cancellation cir- There is an additional clamp between the positive and cuit to compensate for the base current of the PNP input negative supplies that further protects the device during pair. This results in a typical I of about 100nA. When the B ESD strikes. Hot plugging of the device into a powered input common mode voltage is less than 200mV, the bias socket must be avoided since this can trigger the clamp cancellation circuit is no longer effective and the input resulting in larger currents flowing between the supply pins. bias current magnitude can reach a value above 4µA. For common mode voltages ranging from 0.2V above the Capacitive Loads negative supply to 1.2V below the positive supply, the The LTC6252/LTC6253/LTC6254 are optimized for high low input bias current allows the amplifiers to be used in bandwidth and low power applications. Consequently they applications with high source resistances where errors have not been designed to directly drive large capacitive due to voltage drops must be minimized. loads. Increased capacitance at the output creates an ad- Output ditional pole in the open loop frequency response, wors- ening the phase margin. When driving capacitive loads, a The LTC6252 family has excellent output drive capability. resistor of 10Ω to 100Ω should be connected between the The amplifiers can typically deliver 90mA of output drive amplifier output and the capacitive load to avoid ringing current at a total supply of 5V. The maximum output or oscillation. The feedback should be taken directly from current is a function of the total supply voltage. As the the amplifier output. Higher voltage gain configurations supply voltage to the amplifier decreases, the output tend to have better capacitive drive capability than lower current capability also decreases. Attention must be paid gain configurations due to lower closed loop bandwidth to keep the junction temperature of the IC below 150°C and hence higher phase margin. The graphs titled Series (refer to the Power Dissipation Section) when the output Output Resistor vs Capacitive Load demonstrate the tran- is in continuous short-circuit. The output of the amplifier sient response of the amplifier when driving capacitive has reverse-biased diodes connected to each supply. If loads with various series resistors. the output is forced beyond either supply, extremely high current will flow through these diodes which can result in damage to the device. Forcing the output to even 1V beyond either supply could result in several hundred mil- liamps of current through either diode. 625234fc 14

LTC6252/LTC6253/LTC6254 APPLICATIONS INFORMATION Feedback Components Power Dissipation When feedback resistors are used to set up gain, care The LTC6252 and LTC6253 contain one and two amplifiers must be taken to ensure that the pole formed by the respectively. Hence the maximum on-chip power dissipa- feedback resistors and the parasitic capacitance at the tion for them will be less than the maximum on-chip power inverting input does not degrade stability. For example dissipation for the LTC6254, which contains four amplifiers. if the amplifier is set up in a gain of +2 configuration The LTC6254 is housed in a small 16-lead MS package and with gain and feedback resistors of 5k, a parasitic ca- typically has a thermal resistance (q ) of 125°C/ W. It is JA pacitance of 5pF (device + PC board) at the amplifier’s necessary to ensure that the die’s junction temperature inverting input will cause the part to oscillate, due to does not exceed 150°C. The junction temperature, T , is J a pole formed at 12.7MHz. An additional capacitor of calculated from the ambient temperature, T , power dis- A 5pF across the feedback resistor as shown in Figure 2 sipation, PD, and thermal resistance, q : JA will eliminate any ringing or oscillation. In general, if the resistive feedback network results in a pole whose TJ = TA + (PD • qJA) frequency lies within the closed loop bandwidth of the The power dissipation in the IC is a function of the supply amplifier, a capacitor can be added in parallel with the voltage, output voltage and load resistance. For a given feedback resistor to introduce a zero whose frequency supply voltage with output connected to ground or supply, is close to the frequency of the pole, improving stability. the worst-case power dissipation P occurs when D(MAX) the supply current is maximum and the output voltage at 5pF half of either supply voltage for a given load resistance. P is approximately (since I actually changes with D(MAX) S 5k output load current) given by: 2 –  V  CPAR VOUT PD(MAX)=(VS •IS(MAX))+ 2S /RL + 5k Example: For an LTC6254 in a 16-lead MS package operating VIN on ±2.5V supplies and driving a 100Ω load to ground, the 624678 F02 worst-case power dissipation is approximately given by Figure 2. 5pF Feedback Cancels Parasitic Pole P /Amp = (5 • 4.8mA) + (1.25)2/100 = 39.6mW D(MAX) If all four amplifiers are loaded simultaneously then the Shutdown total power dissipation is 158mW. The LTC6252 and LTC6253MS have SHDN pins that can At the Absolute Maximum ambient operating temperature, shut down the amplifier to 42µA typical supply current. The the junction temperature under these conditions will be: SHDN pin needs to be taken within 0.8V of the negative supply for the amplifier to shut down. When left floating, T = T + P • 125°C/W J A D the SHDN pin is internally pulled up to the positive supply = 125 + (0.158W • 125°C/W) = 145°C and the amplifier remains on. which is less than the absolute maximum junction tem- perature for the LTC6254 (150°C). Refer to the Pin Configuration section for thermal resis- tances of various packages. 625234fc 15

LTC6252/LTC6253/LTC6254 TYPICAL APPLICATIONS 5V Single-Supply 16-Bit ADC Driver output can be easily obtained without the amplifier transi- tioning between input regions, thus minimizing crossover Figure 3 shows the LTC6253 driving an LTC2393-16 16-bit distortion. Furthermore, by driving VCM with 2.08V from A/D converter on a single 5V supply. The low wideband the ADC’s VCM pin, the LTC6253 is capable of driving the noise of the LTC6253 helps to achieve better than 93dB LTC2393-16 to within 0.1dB of full scale. Figure 4 shows SNR. A gain of 1.17V/V is taken in the first amplifier, giv- an FFT obtained with a sampling rate of 1Msps and a ing an input voltage range of 3.5V for a full-scale input P-P 20kHz input waveform. Spurious free dynamic range is to the ADC. By taking a small amount of gain, a –1dBFS an excellent 104.7dB. 5V 5V 5V 1.8V TO 5V VIN + 27.4mV TO 10µF 0.1µF 10µF 0.1µF 4.7µF (3.5V + 27.4mV) ½ LTC6253 – AVP DVP OVP PARALLEL 249Ω 100Ω OR 143Ω 2.5k 2.5k IN+ SERIAL 16 BIT INTERFACE 5V 845Ω 3900pF LTC2393-16 SER/PAR – BYTESWAP ½ LTC6253 249Ω 100Ω IN– OB/C2CS + RD VCMREFINREFOUT CNVST PDRESET GNDOGND BUSY 625234 F03 ~2.08V 10µF 1µF SAMPLE CLOCK Figure 3. 5V Single Supply 16-Bit ADC Driver 0 fS = 1Msps –20 F1 = 20.111kHz F1 AMPLITUDE –40 = –1.032dBFS S) SNR = 93.28dB BF –60 THD = –100.50dB d SINAD = 92.53dB DE ( –80 SFDR = 104.7dB U F2 = –106.39dBc T PLI–100 F3 = –104.70dBc M F4 = –114.13dBc A F5 = –105.48dBc –120 –140 –160 0 100 200 300 400 500 FREQUENCY (kHz) 624678 F04 Figure 4. LTC6253 Driving LTC2393-16 16b ADC 5V Single-Supply Performance 625234fc 16

LTC6252/LTC6253/LTC6254 TYPICAL APPLICATIONS Low Noise Gain Block Using Channels in Parallel Multiplexing Channels Figure 5 shows the LTC6254 configured as a low noise The LTC6252 and LTC6253 are available with shutdown gain block. By configuring each channel as a gain of 10 pins in the SOT-23 and MS10 packages. While this allows block and putting all four gain blocks in parallel, the input for reduced power consumption, it also makes the parts referred noise can be reduced significantly. 22Ω resistors suitable for high output impedance applications such as are hooked up to the outputs of each of the channels to muxing. During shutdown, the bases of the amplifier’s ensure even distribution of load currents.For a total sup- output channels are hard tied to their emitters in order to ply current of 13.2mA, measured input referred noise minimize leakage. Figure 6 shows the LTC6253 applied as a density (including contributions from the resistors) be- mux, with the outputs simply shorted together. Depending tween 100kHz and 10MHz was less than 1.6nV/√Hz, with on which device is powered, either the VA or the VB input input referred noise density at 1 MHz being 1.5nV/√Hz. is buffered to VOUT. The MOSFET Q1 provides a simple The measured –3dB frequency was 37MHz for a load logic inversion, so that pulling the gate high selects the resistance of 1k. B path while the FET drain goes low shutting down the A path. R3 is provided to speed up the drain rise time. The 1pF LTC6253 turn-on time is longer than the turn-off time 900Ω (3.5µs vs <2µs) avoiding cross conduction in the output 100Ω 2.5V – 22Ω ¼ LTC6254 R1 5V 330Ω + VA + ½ LTC6253 1pF – SHDNA 900Ω VOUT 100Ω R2 – ¼ LTC6254 22Ω VB 330Ω + + R3 ½ LTC6253 20k 5V – SHDNB 1pF 900Ω Q1 SEL_B 2N7002 100Ω – 22Ω ¼ LTC6254 625234 F06 + Figure 6. Multiplexing Channels 1pF VOUT 900Ω 100Ω – 22Ω ¼ LTC6254 625234 F05 VIN + –2.5V Figure 5. Low Noise Gain Block Using Parallel Channels 625234fc 17

LTC6252/LTC6253/LTC6254 TYPICAL APPLICATIONS stages. See the oscillograph of Figure 7, showing the inputs V and V , the SEL_B control, and the resulting output. A B VA Note that there are protection diodes across the op amp VB inputs, so large signals at the output will feed back into 5V/DIV the upstream off channel through the diodes. R1 and R2 SEL_B were put in place to reduce the loading on the output, as well as to reduce the upstream feedback current and VOUT improve reverse isolation. Some reverse crosstalk can be discerned in the V and V traces during their respective 50µs/DIV 625234 F07 A B off times, however, as the reverse current works back into Figure 7. Oscilloscope Traces Showing the 50Ω source impedance of the function generators. Multiplexing Channels High Speed Low Voltage Instrumentation Amplifier VS+ Figure 8 shows a three op amp instrumentation amplifier IN+ + R4 R6 U1 750Ω 750Ω with a gain of 41V/V which can operate on low supplies. ½ LTC6253 Op amps U1 and U2 are channels from an LTC6253. – VS+ R2 Op amp U3 can be an LTC6252 or one channel of an 1.2k + LTC6253. Figure 9 shows the measured frequency re- U3 R1 R3 ½ LTC6253 VOUT sponse of the instrumentation amplifier for a load of 1kΩ. 60Ω 1.2k – Figure 10 shows the measured CMRR of the instrumenta- tion amplifier, and Figure 11 shows the transient response – R5 VS– R7 for a 50mV input square wave applied to the positive U2 750Ω 750Ω P-P ½ LTC6253 625234 F08 input, with the negative input grounded. IN– + AV = 41 IS = 8.4mA BW = 15MHz VS– VS = ±1.5V Figure 8. High Speed Low Voltage Instrumentation Amplifier 40 120 OUTPUT 35 1V/DIV 100 30 0V 80 25 AIN (dB) 20 MRR (dB) 60 G 15 C INPUT 40 25mV/DIV 10 0V 20 5 0 0 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M 100ns/DIV 625234 F11 FREQUENCY (Hz) FREQUENCY (Hz) 625234 F09 625234 F10 Figure 9. Instrumentation Amplifier Figure 10. Instrumentation Figure 11. Transient Response, Frequency Response Amplifier CMRR Instrumentation Amplifier 625234fc 18

LTC6252/LTC6253/LTC6254 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DC8 Package 8-Lead Plastic DFN (2mm × 2mm) (Reference LTC DWG # 05-08-1719 Rev A) 0.70 ±0.05 2.55 ±0.05 1.15 ±0.050.64 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.45 BSC 1.37 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.115 TYP R = 0.05 5 8 TYP 0.40 ± 0.10 2.00 ±0.10 0.64 ± 0.10 PIN 1 NOTCH PIN 1 BAR (4 SIDES) (2 SIDES) R = 0.20 OR TOP MARK 0.25 × 45° (SEE NOTE 6) CHAMFER (DC8) DFN 0106 REVØ 4 1 0.23 ± 0.05 0.200 REF 0.75 ±0.05 0.45 BSC 1.37 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 625234fc 19

LTC6252/LTC6253/LTC6254 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 3.00 ± 0.102 0.889 ± 0.127 (.118 ± .004) 0.52 (.035 ± .005) 0.254 DETAIL “A” (NOTE 3) 8 7 6 5 (.0205) REF (.010) 0° – 6° TYP 5.23 GAUGE PLANE (.206) 3.20 – 3.45 4.90 ± 0.152 3.00 ± 0.102 MIN (.126 – .136) 0.53 ± 0.152 (.193 ± .006) (.118 ± .004) (NOTE 4) (.021 ± .006) DETAIL “A” 0.42 ± 0.038 0.65 0.18 (.0165 ± .0015) (.0256) (.007) 1 2 3 4 TYP BSC 1.10 0.86 RECOMMENDED SOLDER PAD LAYOUT (.043) (.034) MAX REF NOTE: SEATING 12.. DDIRMAEWNISNIGO NNSO TIN T MO ISLCLAIMLEETER/(INCH) PLANE 0.22 – 0.38 0.1016 ± 0.0508 3 . DMIOMLEDN FSLIOANSH D, OPERSO NTROUT SINIOCNLSU DOER M GOATLED BFULARSRHS, SPHRAOLTLR NUOSITO ENXSC OEERD G 0A.T1E5 2BmUmRR (S.0.06") PER SIDE (.009T Y– P.015) (.00.26556) MS(O.P0 (0M4S8 )± 0 3.007 0RE2V )F 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. BSC INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 625234fc 20

LTC6252/LTC6253/LTC6254 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) 0.889 ± 0.127 (.035 ± .005) 5.23 3.20 – 3.45 (.206) (.126 – .136) MIN 3.00 ± 0.102 0.305 ± 0.038 0.50 (.118 ± .004) 0.497 ± 0.076 (.0120 ± .0015) (.0197) (NOTE 3) (.0196 ± .003) 10 9 8 76 TYP BSC REF RECOMMENDED SOLDER PAD LAYOUT 3.00 ± 0.102 4.90 ± 0.152 0.254 DETAIL “A” (.193 ± .006) (.1(1N8O ±TE . 040)4) (.010) 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.152 (.021 ± .006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING PLANE 0.17 – 0.27 0.1016 ± 0.0508 (.007 – .011) (.004 ± .002) 0.50 TYP (.0197) MSOP (MS) 0307 REV E NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 625234fc 21

LTC6252/LTC6253/LTC6254 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 16-LeaMdS P Plaasctkiacg MeSOP (Reference1 6LT-LCe DaWd GP l#a s0t5ic-0 M8-S1O66P9 Rev Ø) (Reference LTC DWG # 05-08-1669 Rev Ø) 0.889 ± 0.127 (.035 ± .005) 5.23 3.20 – 3.45 (.206) (.126 – .136) MIN 4.039 ± 0.102 0.305 ± 0.038 0.50 (.159 ± .004) (.0120 ± .0015) (.0197) (NOTE 3) 0.280 ± 0.076 TYP BSC 16151413121110 9 (.011 ± .003) RECOMMENDED SOLDER PAD LAYOUT REF DETAIL “A” 3.00 ± 0.102 0.254 4.90 ± 0.152 (.118 ± .004) (.010) 0° – 6° TYP (.193 ± .006) (NOTE 4) GAUGE PLANE 0.53 ± 0.152 1234567 8 (.021 ± .006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING PLANE 0.17 – 0.27 0.1016 ± 0.0508 (.007 – .011) (.004 ± .002) TYP 0.50 NOTE: (.0197) MSOP (MS16) 1107 REV Ø 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 625234fc 22

LTC6252/LTC6253/LTC6254 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 2.90 BSC 0.62 0.95 (NOTE 4) MAX REF 1.22 REF 1.50 – 1.75 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT 0.30 – 0.45 0.95 BSC PER IPC CALCULATOR 6 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 1.90 BSC 0.09 – 0.20 (NOTE 3) S6 TSOT-23 0302 REV B NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 625234fc 23

LTC6252/LTC6253/LTC6254 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 2.90 BSC 0.40 0.65 (NOTE 4) MAX REF 1.22 REF 1.50 – 1.75 3.85 MAX2.62 REF 1.4 MIN 2.80 BSC (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT 0.22 – 0.36 0.65 BSC PER IPC CALCULATOR 8 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 1.95 BSC 0.09 – 0.20 TS8 TSOT-23 0710 REV A (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 625234fc 24

LTC6252/LTC6253/LTC6254 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 9/10 Revised I Parameters in Electrical Characteristics section 4, 5 SD B 6/11 Added H-grade MS8 to Order Information section 2 C 1/12 Updated Electrical Characteristics 3 to 6 625234fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 25 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC6252/LTC6253/LTC6254 TYPICAL APPLICATION 2MHz, 1MΩ Single Supply Photodiode Amplifier Photodiode Amplifier Noise Spectrum 500 R1 1M, 1% C1 3V 0.1pF 50nV/√Hz R1k2 3V PER DIV + IPD Q1 NXP LTC6252 VOUT ≈ 0.5V + IPD • 1M BF862 – PD1 C2 –3dB BW = 2MHz 0 OSFSHR2A1M3 6FOI.RL8M nNFPO R1k3 0.C13µF IOCUCT =P 4U.T5 mNOAISE = 360µVRMS 5kHz 100kHz 625234 TA20M2bHz MEASURED ON A 2MHz BW Photodiode Amplifier Transient Response R4 R5 10k 20k 3V 5V/DIV 625234 TA02a LED DRIVER VOLTAGE 500mV/DIV OUTPUT WAVEFORM 0V 200ns/DIV 625234 TA02c RELATED PARTS PART NUMBER DESCRIPTION COMMENTS Operational Amplifiers LT1818/LT1819 Single/Dual Wide Bandwidth, High Slew Rate Low Noise and 400MHz, 9mA, 6nV/√Hz, 2500V/µs, 1.5mV –85dBc at 5MHz Distortion Op Amps LT1806/LT1807 Single/Dual Low Noise Rail-to-Rail Input and Output Op Amps 325MHz, 13mA, 3.5nV/√Hz, 140V/µs, 550µV, 85mA Output Drive LTC6246/LTC6247/ Single/Dual/Quad High Speed Rail-to-Rail Input and Output 180MHz, 1mA, 4.2nV/√Hz, 90V/µs, 0.5mV LTC6248 Op Amps LT6230/LT6231/ Single/Dual/Quad Low Noise Rail-to-Rail Output Op Amps 215MHz, 3.5mA, 1.1nV/√Hz, 70V/µs, 350µV LT6232 LT6200/LT6201 Single/Dual Ultralow Noise Rail-to-Rail Input/Output Op Amps 165MHz, 20mA, 0.95nV/√Hz, 44V/µs, 1mV LT6202/LT6203/ Single/Dual/Quad Ultralow Noise Rail-to-Rail Op Amp 100MHz, 3mA, 1.9nV/√Hz, 25V/µs, 0.5mV LT6204 LT1468 16-Bit Accurate Precision High Speed Op Amp 90MHz, 3.9mA, 5nV/√Hz, 22V/µs, 175µV, –96.5dB THD at 10V , 100kHz P-P LT1801/LT1802 Dual/Quad Low Power High Speed Rail-to-Rail Input and 80MHz, 2mA, 8.5nV√Hz, 25V/µs, 350µV Output Op Amps LT1028 Ultralow Noise, Precision High Speed Op Amps 75MHz, 9.5mA, 0.85nV/√Hz, 11V/µs, 40µV LTC6350 Low Noise Single-Ended to Differential Converter/ADC Driver 33MHz (–3dB), 4.8mA, 1.9nV/√Hz, 240ns Settling to 0.01% 8V P-P ADCs LTC2393-16 1Msps 16-Bit SAR ADC 94dB SNR LTC2366 3Msps, 12-Bit ADC Serial I/O 72dB SNR, 7.8mW No Data Latency TSOT-23 Package LTC2365 1Msps, 12-Bit ADC Serial I/O 73dB SNR, 7.8mW No Data Latency TSOT-23 Package 625234fc 26 Linear Technology Corporation LT 0112 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com ” LINEAR TECHNOLOGY CORPORATION 2010