LTC6240/LTC6241/LTC6242 Single/Dual/Quad 18MHz, Low Noise, Rail-to-Rail Output, CMOS Op Amps FEATURES DESCRIPTION n 0.1Hz to 10Hz Noise: 550nV The LTC®6240/6241/LTC6242 are single, dual and quad P-P n Input Bias Current: low noise, low offset, rail-to-rail output, unity gain stable 0.2pA (Typ at 25°C) CMOS op amps that feature 1pA of input bias current. Input 1pA Max (LTC6240) bias current is guaranteed to be 1pA max on the single n Low Offset Voltage: 125μV Max LTC6240. The 0.1Hz to 10Hz noise of only 550nV , along P-P n Low Offset Drift: 2.5μV/°C Max with an offset of just 125μV are signifi cant improvements n Gain Bandwidth Product: 18MHz over traditional CMOS op amps. Additionally, noise is n Output Swings Rail-to-Rail guaranteed to be less than 10nV/√Hz at 1kHz. An 18MHz n Supply Operation: gain bandwidth, and 10V/μs slew rate, along with the wide 2.8V to 6V LTC6240/LTC6241/LTC6242 supply range and low input capacitance, make them perfect 2.8V to ±5.5V LTC6240HV/LTC6241HV/LTC6242HV for use as fast signal processing amplifi ers. n Low Input Capacitance These op amps have an output stage that swings within n H-Grade Temperature Range: –40°C to 125°C 30mV of either supply rail to maximize the signal dynamic n Single LTC6240 in 5-Pin Low Profi le (1mm) range in low supply applications. The input common mode ThinSOT™ Package and 8-Pin SO for PCB Guard Ring range extends to the negative supply. They are fully speci- n Dual LTC6241 in 8-Pin SO and Tiny DFN Packages fi ed on 3V and 5V, and an HV version guarantees operation n Quad LTC6242 in 16-Pin SSOP and 5mm × 3mm on supplies up to ±5V. DFN Packages The LTC6240 is available in the 8-pin SO and the 5-pin SOT- APPLICATIONS 23 packages. The LTC6241 is available in the 8-pin SO, and n Photo Diode Amplifi ers for compact designs it is packaged in a tiny dual fi ne pitch n Charge Coupled Amplifi ers leadless (DFN) package. The LTC6242 is available in the n Low Noise Signal Processing 16-pin SSOP as well as the 5mm × 3mm DFN package. n Medical Instrumentation L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. n High Impedance Transducer Amplifi er All other trademarks are the property of their respective owners. TYPICAL APPLICATION Low Noise Single-Ended Input to Differential Output Amplifi er Noise Voltage vs Frequency C3 60 10pF TA = 25°C VS = ±2.5V 1C0p4F 4.R949k Hz) 50 VCM = 0V VIN 2R001k 1C01pF 4.R939k +–LT+C216./522V41 VOUT+ OISE VOLTAGE (nV/√ 234000 – N 1/2 –2.5V 10 LTC6241 VOUT– + R2 0 200k 1 10 100 1k 10k 100k FREQUENCY (Hz) C2 6241 TA01a 6241 TA01b 10pF 624012fe 1

LTC6240/LTC6241/LTC6242 ABSOLUTE MAXIMUM RATINGS (Note 1) Total Supply Voltage (V+ to V–) Specifi ed Temperature Range (Note 3) LTC6240/LTC6241/LTC6242 ...................................7V LTC6240C/LTC6241C/LTC6242C ..............0°C to 70°C LTC6240HV/LTC6241HV/LTC6242HV ....................12V LTC6240I/LTC6241I/LTC6242I .............–40°C to 85°C Input Voltage ..........................(V+ + 0.3V) to (V– – 0.3V) LTC6240H/LTC6241H/LTC6242H .......–40°C to 125°C Input Current ........................................................±10mA Junction Temperature ...........................................150°C Output Short-Circuit Duration (Note 2) ............Indefi nite DHC, DD Package .............................................125°C Operating Temperature Range Storage Temperature Range ..................–65°C to 150°C LTC6240C/LTC6241C/LTC6242C ..........–40°C to 85°C DHC, DD Package ..............................–65°C to 125°C LTC6240I/LTC6241I/LTC6242I .............–40°C to 85°C Lead Temperature (Soldering, 10 sec)...................300°C LTC6240H/LTC6241H/LTC6242H .......–40°C to 125°C PIN CONFIGURATION LTC6240 LTC6240 TOP VIEW TOP VIEW NC 1 8 NC OUT 1 5 V+ –IN 2 – 7 V+ V– 2 +IN 3 + – 4 –IN +IN 3 + 6 OUT V– 4 5 NC S5 PACKAGE 5-LEAD PLASTIC TSOT-23 S8 PACKAGE TJMAX = 150°C, θJA = 250°C/W 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 190°C/W LTC6241 LTC6241 TOP VIEW TOP VIEW OUT A 1 8 V+ OUT A 1 8 V+ –IN A 2 7 OUT B A –IN A 2 7 OUT B +IN A 3 6 –IN B A B V– 4 5 +IN B +IN A 3 B 6 –IN B V– 4 5 +IN B DD PACKAGE S8 PACKAGE 8-LEAD (3mm (cid:115) 3mm) PLASTIC DFN 8-LEAD PLASTIC SO UNDETRJMSIADXE = M 12E5TA°CL, CθOJAN =N E4C3T°CED/W TO V– TJMAX = 150°C, θJA = 190°C/W (PCB CONNECTION OPTIONAL) LTC6242 LTC6242 TOP VIEW TOP VIEW OUT A 1 16 OUT D OUT A 1 16 OUT D –IN A 2 15 –IN D A D –IN A 2 15 –IN D A D +IN A 3 14 +IN D +IN A 3 14 +IN D V+ 4 17 13 V– V+ 4 13 V– +IN B 5 12 +IN C B C +IN B 5 12 +IN C B C –IN B 6 11 –IN C –IN B 6 11 –IN C OUT B 7 10 OUT C OUT B 7 10 OUT C NC 8 9 NC NC 8 9 NC DHC PACKAGE GN PACKAGE 16-LEAD (5mm (cid:115) 3mm) PLASTIC DFN 16-LEAD PLASTIC SSOP UNDERSIDE METAL CTOJMNANXE =C T1E2D5 °TCO, θVJ–A (=P C4B3° CCO/WNNECTION OPTIONAL) TJMAX = 150°C, θJA = 135°C/W 624012fe 2

LTC6240/LTC6241/LTC6242 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6240CS5#PBF LTC6240CS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 0°C to 70°C LTC6240HVCS5#PBF LTC6240HVCS5#TRPBF LTCRS 5-Lead Plastic TSOT-23 0°C to 70°C LTC6240IS5#PBF LTC6240IS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 –40°C to 85°C LTC6240HVIS5#PBF LTC6240HVIS5 #TRPBF LTCRS 5-Lead Plastic TSOT-23 –40°C to 85°C LTC6240HS5#PBF LTC6240HS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 –40°C to 125°C LTC6240HVHS5#PBF LTC6240HVHS5#TRPBF LTCRS 5-Lead Plastic TSOT-23 –40°C to 125°C LTC6240CS8#PBF LTC6240CS8#TRPBF 6240 8-Lead Plastic SO 0°C to 70°C LTC6240HVCS8#PBF LTC6240HVCS8#TRPBF 6240HV 8-Lead Plastic SO 0°C to 70°C LTC6240IS8#PBF LTC6240IS8#TRPBF 6240I 8-Lead Plastic SO –40°C to 85°C LTC6240HVIS8#PBF LTC6240HVIS8#TRPBF 240HVI 8-Lead Plastic SO –40°C to 85°C LTC6240HS8#PBF LTC6240HS8#TRPBF 6240H 8-Lead Plastic SO –40°C to 125°C LTC6240HVHS8#PBF LTC6240HVHS8#TRPBF 240HVH 8-Lead Plastic SO –40°C to 125°C LTC6241CDD#PBF LTC6241CDD#TRPBF LBPD 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LTC6241HVCDD#PBF LTC6241HVCDD#TRPBF LBRR 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LTC6241IDD#PBF LTC6241IDD#TRPBF LBPD 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6241HVIDD#PBF LTC6241HVIDD#TRPBF LBRR 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6241CS8#PBF LTC6241CS8#TRPBF 6241 8-Lead Plastic SO 0°C to 70°C LTC6241HVCS8#PBF LTC6241HVCS8#TRPBF 6241HV 8-Lead Plastic SO 0°C to 70°C LTC6241IS8#PBF LTC6241IS8#TRPBF 6241I 8-Lead Plastic SO –40°C to 85°C LTC6241HVIS8#PBF LTC6241HVIS8#TRPBF 241HVI 8-Lead Plastic SO –40°C to 85°C LTC6241HS8#PBF LTC6241HS8#TRPBF 6241H 8-Lead Plastic SO –40°C to 125°C LTC6241HVHS8#PBF LTC6241HVHS8#TRPBF 241HVH 8-Lead Plastic SO –40°C to 125°C LTC6242CDHC#PBF LTC6242CDHC#TRPBF 6242 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C LTC6242HVCDHC#PBF LTC6242HVCDHC#TRPBF 6242HV 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C LTC6242IDHC#PBF LTC6242IDHC#TRPBF 6242 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C LTC6242HVIDHC#PBF LTC6242HVIDHC#TRPBF 6242HV 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C LTC6242CGN#PBF LTC6242CGN#TRPBF 6242 16-Lead Plastic SSOP 0°C to 70°C LTC6242HVCGN#PBF LTC6242HVCGN#TRPBF 6242HV 16-Lead Plastic SSOP 0°C to 70°C LTC6242IGN#PBF LTC6242IGN#TRPBF 6242I 16-Lead Plastic SSOP –40°C to 85°C LTC6242HVIGN#PBF LTC6242HVIGN#TRPBF 242HVI 16-Lead Plastic SSOP –40°C to 85°C LTC6242HGN#PBF LTC6242HGN#TRPBF 6242H 16-Lead Plastic SSOP –40°C to 125°C LTC6242HVHGN#PBF LTC6242HVHGN#TRPBF 242HVH 16-Lead Plastic SSOP –40°C to 125°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ 624012fe 3

LTC6240/LTC6241/LTC6242 AVAILABLE OPTIONS PART NUMBER AMPS/PACKAGE SPECIFIED TEMP RANGE SPECIFIED SUPPLY VOLTAGE PACKAGE PART MARKING LTC6240CS5 1 0°C to 70°C 3V, 5V SOT-23 LTCRR LTC6240CS8 1 0°C to 70°C 3V, 5V SO-8 6240 LTC6240HVCS5 1 0°C to 70°C 3V, 5V, ±5V SOT-23 LTCRS LTC6240HVCS8 1 0°C to 70°C 3V, 5V, ±5V SO-8 6240HV LTC6240IS5 1 –40°C to 85°C 3V, 5V SOT-23 LTCRR LTC6240IS8 1 –40°C to 85°C 3V, 5V SO-8 6240I LTC6240HVIS5 1 –40°C to 85°C 3V, 5V, ±5V SOT-23 LTCRS LTC6240HVIS8 1 –40°C to 85°C 3V, 5V, ±5V SO-8 240HVI LTC6240HS5 1 –40°C to 125°C 3V, 5V SOT-23 LTCRR LTC6240HS8 1 –40°C to 125°C 3V, 5V SO-8 6240H LTC6240HVHS5 1 –40°C to 125°C 3V, 5V, ±5V SOT-23 LTCRS LTC6240HVHS8 1 –40°C to 125°C 3V, 5V, ±5V SO-8 240HVH LTC6241CS8 2 0°C to 70°C 3V, 5V SO-8 6241 LTC6241CDD 2 0°C to 70°C 3V, 5V DD LBPD LTC6241HVCS8 2 0°C to 70°C 3V, 5V, ±5V SO-8 6241HV LTC6241HVCDD 2 0°C to 70°C 3V, 5V, ±5V DD LBRR LTC6241IS8 2 –40°C to 85°C 3V, 5V SO-8 6241I LTC6241IDD 2 –40°C to 85°C 3V, 5V DD LBPD LTC6241HVIS8 2 –40°C to 85°C 3V, 5V, ±5V SO-8 241HVI LTC6241HVIDD 2 –40°C to 85°C 3V, 5V, ±5V DD LBRR LTC6241HS8 2 –40°C to 125°C 3V, 5V SO-8 6241H LTC6241HVHS8 2 –40°C to 125°C 3V, 5V, ±5V SO-8 241HVH LTC6242CGN 4 0°C to 70°C 3V, 5V GN 6242 LTC6242CDHC 4 0°C to 70°C 3V, 5V DHC 6242 LTC6242HVCGN 4 0°C to 70°C 3V, 5V, ±5V GN 6242HV LTC6242HVCDHC 4 0°C to 70°C 3V, 5V, ±5V DHC 6242HV LTC6242IGN 4 –40°C to 85°C 3V, 5V GN 6242I LTC6242IDHC 4 –40°C to 85°C 3V, 5V DHC 6242 LTC6242HVIGN 4 –40°C to 85°C 3V, 5V, ±5V GN 242HVI LTC6242HVIDHC 4 –40°C to 85°C 3V, 5V, ±5V DHC 6242HV LTC6242HGN 4 –40°C to 125°C 3V, 5V GN 6242H LTC6242HVHGN 4 –40°C to 125°C 3V, 5V, ±5V GN 242HVH 624012fe 4

LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 5V, 0V, V = 2.5V unless otherwise noted. A S CM SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage (Note 4) LTC6241 S8 40 125 μV OS 0°C to 70°C l 250 μV –40°C to 85°C l 300 μV LTC6242 GN 50 150 μV 0°C to 70°C l 275 μV –40°C to 85°C l 300 μV LTC6240 50 175 μV 0°C to 70°C l 300 μV –40°C to 85°C l 350 μV LTC6241 DD, LTC6242 DHC 100 550 μV 0°C to 70°C l 650 μV –40°C to 85°C l 725 μV V Match Channel-to-Channel (Note 5) LTC6241 S8 40 160 μV OS 0°C to 70°C l 300 μV –40°C to 85°C l 375 μV LTC6242 GN 50 185 μV 0°C to 70°C l 325 μV –40°C to 85°C l 400 μV LTC6241 DD, LTC6242 DHC 150 650 μV 0°C to 70°C l 700 μV –40°C to 85°C l 750 μV TC V Input Offset Voltage Drift (Note 6) l 0.7 2.5 μV/°C OS I Input Bias Current (Notes 4, 7) LTC6241, LTC6242 0.2 pA B l 75 pA LTC6240 0.2 1 pA l 75 pA I Input Offset Current (Notes 4, 7) LTC6241, LTC6242 0.2 pA OS l 75 pA LTC6240 0.2 1 pA l 75 pA Input Noise Voltage 0.1Hz to 10Hz 550 nV P-P e Input Noise Voltage Density f = 1kHz 7 10 nV/√Hz n i Input Noise Current Density (Note 8) 0.56 fA/√Hz n R Input Resistance Common Mode 1012 Ω IN C Input Capacitance f = 100kHz IN Differential Mode 3.5 pF Common Mode 3 pF V Input Voltage Range Guaranteed by CMRR l 0 3.5 V CM CMRR Common Mode Rejection 0V ≤ V ≤ 3.5V l 80 105 dB CM CMRR Match Channel-to-Channel (Note 5) l 76 95 dB 624012fe 5

LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 5V, 0V, V = 2.5V unless otherwise noted. A S CM SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS A Large Signal Voltage Gain V = 1V to 4V VOL O R = 10k to V /2 425 1600 V/mV L S 0°C to 70°C l 300 V/mV –40°C to 85°C l 200 V/mV V = 1.5V to 3.5V O R = 1k to V /2 90 215 V/mV L S 0°C to 70°C l 60 V/mV –40°C to 85°C l 50 V/mV V Output Voltage Swing Low (Note 9) No Load l 7 30 mV OL I = 1mA l 40 75 mV SINK I = 5mA l 190 325 mV SINK V Output Voltage Swing High (Note 9) No Load l 11 30 mV OH I = 1mA l 45 75 mV SOURCE I = 5mA l 190 325 mV SOURCE PSRR Power Supply Rejection V = 2.8V to 6V, V = 0.2V l 80 104 dB S CM PSRR Match Channel-to-Channel (Note 5) l 74 100 dB Minimum Supply Voltage (Note 10) l 2.8 V I Short-Circuit Current l 15 30 mA SC I Supply Current per Amplifi er LTC6241, LTC6242 1.8 2.2 mA S 0°C to 70°C l 2.3 mA –40°C to 85°C l 2.4 mA LTC6240 2 2.4 mA 0°C to 70°C l 2.5 mA –40°C to 85°C l 2.6 mA GBW Gain Bandwidth Product Frequency = 20kHz, R = 1kΩ l 13 18 MHz L SR Slew Rate (Note 11) A = –2, R = 1kΩ l 5 10 V/μs V L FPBW Full Power Bandwidth (Note 12) V = 3V , R = 1kΩ l 0.53 1.06 MHz OUT P-P L t Settling Time V = 2V, A = –1, R = 1kΩ, 0.1% 1100 ns s STEP V L 624012fe 6

LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 3V, 0V, V = 1.5V unless otherwise noted. A S CM SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage (Note 4) LTC6241 S8 40 175 μV OS 0°C to 70°C l 275 μV –40°C to 85°C l 325 μV LTC6242 GN 60 200 μV 0°C to 70°C l 275 μV –40°C to 85°C l 325 μV LTC6240 50 200 μV 0°C to 70°C l 325 μV –40°C to 85°C l 375 μV LTC6241 DD, LTC6242 DHC 100 550 μV 0°C to 70°C l 650 μV –40°C to 85°C l 725 μV V Match Channel-to-Channel (Note 5) LTC6241 S8 40 200 μV OS 0°C to 70°C l 325 μV –40°C to 85°C l 400 μV LTC6242 GN 60 225 μV 0°C to 70°C l 325 μV –40°C to 85°C l 400 μV LTC6241 DD, LTC6242 DHC 150 650 μV 0°C to 70°C l 700 μV –40°C to 85°C l 750 μV TC V Input Offset Voltage Drift (Note 6) l 0.7 2.5 μV/°C OS I Input Bias Current (Notes 4, 7) LTC6241, LTC6242 0.2 pA B l 75 pA LTC6240 0.2 1 pA l 75 pA I Input Offset Current (Notes 4, 7) LTC6241, LTC6242 0.2 pA OS l 75 pA LTC6240 0.2 1 pA l 75 pA V Input Voltage Range Guaranteed by CMRR l 0 1.5 V CM CMRR Common Mode Rejection 0V ≤ V ≤ 1.5V l 78 100 dB CM CMRR Match Channel-to-Channel (Note 5) l 76 95 dB A Large Signal Voltage Gain V = 1V to 2V VOL O R = 10k to V /2 140 600 V/mV L S 0°C to 70°C l 100 V/mV –40°C to 85°C l 75 V/mV V Output Voltage Swing Low (Note 9) No Load l 3 30 mV OL I = 1mA l 65 110 mV SINK V Output Voltage Swing High (Note 9) No Load l 4 30 mV OH I = 1mA l 70 120 mV SOURCE PSRR Power Supply Rejection V = 2.8V to 6V, V = 0.2V l 80 104 dB S CM PSRR Match Channel-to-Channel (Note 5) l 74 100 dB Minimum Supply Voltage (Note 10) l 2.8 V I Short-Circuit Current l 3 6 mA SC 624012fe 7

LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 3V, 0V, V = 1.5V unless otherwise noted. A S CM SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Supply Current per Amplifi er LTC6241, LTC6242 1.4 1.7 mA S 0°C to 70°C l 1.8 mA –40°C to 85°C l 1.9 mA LTC6240 1.5 1.9 mA 0°C to 70°C l 2 mA –40°C to 85°C l 2.1 mA GBW Gain Bandwidth Product Frequency = 20kHz, R = 1kΩ l 12 17 MHz L (LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = ±5V, 0V, V = 0V unless otherwise noted. A S CM SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage (Note 4) LTC6241 S8 50 175 μV OS 0°C to 70°C l 275 μV –40°C to 85°C l 325 μV LTC6242 GN 60 200 μV 0°C to 70°C l 275 μV –40°C to 85°C l 325 μV LTC6240 60 250 μV 0°C to 70°C l 350 μV –40°C to 85°C l 400 μV LTC6241 DD, LTC6242 DHC 100 550 μV 0°C to 70°C l 650 μV –40°C to 85°C l 725 μV V Match Channel-to-Channel (Note 5) LTC6241 S8 50 200 μV OS 0°C to 70°C l 325 μV –40°C to 85°C l 400 μV LTC6242 GN 60 225 μV 0°C to 70°C l 325 μV –40°C to 85°C l 400 μV LTC6241 DD, LTC6242 DHC 150 650 μV 0°C to 70°C l 700 μV –40°C to 85°C l 750 μV TC V Input Offset Voltage Drift (Note 6) l 0.7 2.5 μV/°C OS I Input Bias Current (Notes 4, 7) LTC6241, LTC6242 0.5 pA B l 75 pA LTC6240 0.5 1 pA l 75 pA I Input Offset Current (Notes 4, 7) LTC6241, LTC6242 0.2 pA OS l 75 pA LTC6240 0.2 1 pA l 75 pA Input Noise Voltage 0.1Hz to 10Hz 550 nV P-P 624012fe 8

LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = ±5V, 0V, V = 0V A S CM unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS e Input Noise Voltage Density f = 1kHz 7 10 nV/√Hz n i Input Noise Current Density (Note 8) 0.56 fA/√Hz n R Input Resistance Common Mode 1012 Ω IN C Input Capacitance f = 100kHz IN Differential Mode 3.5 pF Common Mode 3 pF V Input Voltage Range Guaranteed by CMRR l –5 3.5 V CM CMRR Common Mode Rejection –5V ≤ V ≤ 3.5V l 83 105 dB CM CMRR Match Channel-to-Channel (Note 5) l 76 95 dB A Large Signal Voltage Gain V = –3.5V to 3.5V VOL O R = 10k 775 2700 V/mV L 0°C to 70°C l 600 V/mV –40°C to 85°C l 500 V/mV R = 1k 150 360 V/mV L 0°C to 70°C l 90 V/mV –40°C to 85°C l 75 V/mV V Output Voltage Swing Low (Note 9) No Load l 15 30 mV OL I = 1mA l 45 75 mV SINK I = 10mA l 360 550 mV SINK V Output Voltage Swing High (Note 9) No Load l 15 30 mV OH I = 1mA l 45 75 mV SOURCE I = 10mA l 360 550 mV SOURCE PSRR Power Supply Rejection V = 2.8V to 11V, V = 0.2V l 85 110 dB S CM PSRR Match Channel-to-Channel (Note 5) l 82 106 dB Minimum Supply Voltage (Note 10) l 2.8 V I Short-Circuit Current l 15 35 mA SC I Supply Current per Amplifi er LTC6241, LTC6242 2.5 3.2 mA S 0°C to 70°C l 3.3 mA –40°C to 85°C l 3.7 mA LTC6240 2.7 3.3 mA 0°C to 70°C l 3.4 mA –40°C to 85°C l 3.8 mA GBW Gain Bandwidth Product Frequency = 20kHz, R = 1kΩ l 13 18 MHz L SR Slew Rate (Note 11) A = –2, R = 1kΩ l 5.5 10 V/μs V L FPBW Full Power Bandwidth (Note 12) V = 3V , R = 1kΩ l 0.58 1.06 MHz OUT P-P L t Settling Time V = 2V, A = –1, R = 1kΩ, 0.1% 900 ns s STEP V L 624012fe 9

LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The l denotes the specifi cations which apply from –40°C to 125°C, otherwise specifi cations are at T = 25°C. V = 5V, 0V, V = 2.5V A S CM unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage (Note 4) LTC6241 S8 40 125 μV OS l 400 μV LTC6242 GN 50 150 μV l 400 μV LTC6240 50 175 μV l 450 μV V Match Channel-to-Channel (Note 5) LTC6241 S8 40 160 μV OS l 400 μV LTC6242 GN 50 185 μV l 400 μV TC V Input Offset Voltage Drift (Note 6) l 0.7 2.5 μV/°C OS I Input Bias Current (Notes 4, 7) LTC6241, LTC6242 0.2 pA B l 1.5 nA LTC6240 0.2 1 pA l 2.5 nA I Input Offset Current (Notes 4, 7) LTC6241, LTC6242 0.2 pA OS l 150 pA LTC6240 0.2 1 pA l 750 pA V Input Voltage Range Guaranteed by CMRR l 0 3.5 V CM CMRR Common Mode Rejection 0V ≤ V ≤ 3.5V l 78 dB CM CMRR Match Channel-to-Channel (Note 5) l 74 dB A Large Signal Voltage Gain V = 1V to 4V VOL O R = 10k to V /2 425 1600 V/mV L S l 200 V/mV V = 1.5V to 3.5V O R = 1k to V /2 90 215 V/mV L S l 40 V/mV V Output Voltage Swing Low (Note 9) No Load l 30 mV OL I = 1mA l 85 mV SINK I = 5mA l 325 mV SINK V Output Voltage Swing High (Note 9) No Load l 30 mV OH I = 1mA l 85 mV SOURCE I = 5mA l 325 mV SOURCE PSRR Power Supply Rejection V = 2.8V to 6V, V = 0.2V l 78 dB S CM PSRR Match Channel-to-Channel (Note 5) l 74 dB Minimum Supply Voltage (Note 10) l 2.8 V I Short-Circuit Current l 15 mA SC I Supply Current per Amplifi er LTC6241, LTC6242 1.8 2.2 mA S l 2.4 mA LTC6240 2 2.4 mA l 2.8 mA GBW Gain Bandwidth Product Frequency = 20kHz, R = 1kΩ l 12 MHz L SR Slew Rate (Note 11) A = –2, R = 1kΩ l 4.5 V/μs V L FPBW Full Power Bandwidth (Note 12) V = 3V , R = 1kΩ l 0.48 MHz OUT P-P L 624012fe 10

LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The l denotes the specifi cations which apply from –40°C to 125°C, otherwise specifi cations are at T = 25°C. V = 3V, 0V, V = 1.5V A S CM unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage (Note 4) LTC6241 S8 40 175 μV OS l 400 μV LTC6242 GN 60 200 μV l 400 μV LTC6240 50 200 μV l 450 μV V Match Channel-to-Channel (Note 5) LTC6241 S8 40 200 μV OS l 400 μV LTC6242 GN 60 225 μV l 400 μV TC V Input Offset Voltage Drift (Note 6) l 0.7 2.5 μV/°C OS I Input Bias Current (Notes 4, 7) LTC6241, LTC6242 0.2 pA B l 1.5 nA LTC6240 0.2 1 pA l 2.5 nA I Input Offset Current (Notes 4, 7) LTC6241, LTC6242 0.2 pA OS l 150 pA LTC6240 0.2 1 pA l 750 pA V Input Voltage Range Guaranteed by CMRR l 0 1.5 V CM CMRR Common Mode Rejection 0V ≤ V ≤ 1.5V l 75 dB CM CMRR Match Channel-to-Channel (Note 5) l 74 dB A Large Signal Voltage Gain V = 1V to 2V VOL O R = 10k to V /2 140 600 V/mV L S l 65 V/mV V Output Voltage Swing Low (Note 9) No Load l 30 mV OL I = 1mA l 130 mV SINK V Output Voltage Swing High (Note 9) No Load l 30 mV OH I = 1mA l 130 mV SOURCE PSRR Power Supply Rejection V = 2.8V to 6V, V = 0.2V l 78 dB S CM PSRR Match Channel-to-Channel (Note 5) l 74 dB Minimum Supply Voltage (Note 10) l 2.8 V I Short-Circuit Current l 2.5 mA SC I Supply Current per Amplifi er LTC6241, LTC6242 1.4 1.7 mA S l 1.9 mA LTC6240 1.5 1.9 mA l 2.1 mA GBW Gain Bandwidth Product Frequency = 20kHz, R = 1kΩ l 10 MHz L 624012fe 11

LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240HVH/LTC6241HVH/LTC6242HVH) The l denotes the specifi cations which apply from –40°C to 125°C, otherwise specifi cations are at T = 25°C. V = ±5V, V = 0V unless otherwise noted. A S CM SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage (Note 4) LTC6241 S8 50 175 μV OS l 400 μV LTC6242 GN 60 200 μV l 400 μV LTC6240 60 250 μV l 450 μV V Match Channel-to-Channel (Note 5) LTC6241 S8 50 200 μV OS l 400 μV LTC6242 GN 60 225 μV l 400 μV TC V Input Offset Voltage Drift (Note 6) l 0.7 2.5 μV/°C OS I Input Bias Current (Notes 4, 7) LTC6241, LTC6242 0.5 pA B l 1.5 nA LTC6240 0.5 1 pA l 2.5 nA I Input Offset Current (Notes 4, 7) LTC6241, LTC6242 0.2 pA OS l 150 pA LTC6240 0.2 1 pA l 750 pA V Input Voltage Range Guaranteed by CMRR l –5 3.5 V CM CMRR Common Mode Rejection –5V ≤ V ≤ 3.5V l 80 dB CM CMRR Match Channel-to-Channel (Note 5) l 76 dB A Large Signal Voltage Gain V = –3.5V to 3.5V VOL O R = 10k 775 2700 V/mV L l 350 V/mV R = 1k 150 360 V/mV L l 60 V/mV V Output Voltage Swing Low (Note 9) No Load l 30 mV OL I = 1mA l 85 mV SINK I = 10mA l 600 mV SINK V Output Voltage Swing High (Note 9) No Load l 30 mV OH I = 1mA l 85 mV SOURCE I = 10mA l 600 mV SOURCE PSRR Power Supply Rejection V = 2.8V to 11V, V = 0.2V l 83 dB S CM PSRR Match Channel-to-Channel (Note 5) l 82 dB Minimum Supply Voltage (Note 10) l 2.8 V I Short-Circuit Current l 15 mA SC I Supply Current per Amplifi er LTC6241, LTC6242 2.5 3.2 mA S l 3.7 mA LTC6240 2.7 3.3 mA l 3.8 mA GBW Gain Bandwidth Product Frequency = 20kHz, R = 1kΩ l 12 MHz L SR Slew Rate (Note 11) A = –2, R = 1kΩ l 5 V/μs V L FPBW Full Power Bandwidth (Note 12) V = 3V , R = 1kΩ l 0.53 MHz OUT P-P L 624012fe 12

LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: This parameter is not 100% tested. may cause permanent damage to the device. Exposure to any Absolute Note 7: Bias current at T = 25°C is 100% tested and guaranteed for the A Maximum Rating condition for extended periods may affect device LTC6240 in the S8 package. The LTC6240S5, LTC6241 and LTC6242 are reliability and lifetime. expected to achieve the same performance as the LTC6240S8. All parts are Note 2: A heat sink may be required to keep the junction temperature guaranteed to meet specifi cations over temperature. below the absolute maximum rating when the output is shorted Note 8: Current noise is calculated from the formula: i = (2qI )1/2 where n B indefi nitely. q = 1.6 × 10–19 coulomb. The noise of source resistors up to 50GΩ Note 3: The LTC6240C/LTC6240HVC/LTC6241C/LTC6241HVC, LTC6242C/ dominates the contribution of current noise. See also Typical Performance LTC6242HVC are guaranteed to meet specifi ed performance from 0°C to Characteristics curve Noise Current vs Frequency. 70°C. They are designed, characterized and expected to meet specifi ed Note 9: Output voltage swings are measured between the output and performance from –40°C to 85°C, but are not tested or QA sampled at power supply rails. these temperatures. The LTC6240I/LTC6240HVI, LTC6241I/LTC6241HVI, Note 10: Minimum supply voltage is guaranteed by the power supply LTC6242I/LTC6242HVI are guaranteed to meet specifi ed performance rejection ratio test. from –40°C to 85°C. All versions of the LTC6240H/LTC6241H/LTC6242H Note 11: Slew rate is measured in a gain of –2 with R = 1k and R = are guaranteed to meet specifi ed performance from –40°C to 125°C. F G 500Ω. On the LTC6240/LTC6241/LTC6242, V = ±2.5V, V is ±1V and S IN Note 4: ESD (Electrostatic Discharge) sensitive device. ESD protection V slew rate is measured between –1V and +1V. On the LTC6240HV/ OUT devices are used extensively internal to the LTC6240/LTC6241/LTC6242; LTC6241HV/LTC6242HV, V is ±2V and V slew rate is measured IN OUT however, high electrostatic discharge can damage or degrade the device. between –2V and +2V. Use proper ESD handling precautions. Note 12: Full-power bandwidth is calculated from the slew rate: Note 5: Matching parameters are the difference between the two amplifi ers FPBW = SR/πV . P-P A and D and between B and C of the LTC6242; between the two amplifi ers of the LTC6241. CMRR and PSRR match are defi ned as follows: CMRR and PSRR are measured in μV/V on the matched amplifi ers. The difference is calculated between the matching sides in μV/V. The result is converted to dB. 624012fe 13

LTC6240/LTC6241/LTC6242 TYPICAL PERFORMANCE CHARACTERISTICS V Temperature Coeffi cient OS V Distribution LTC6241 V Distribution LTC6241 Distribution LTC6241 OS OS 90 120 16 VS = ±2.5V VS = ±2.5V VS = ±2.5V 80 SO-8 PACKAGE DD PACKAGE 14 2 LOTS 100 –55°C TO 125°C 70 12 TS 60 TS 80 TS NI NI NI 10 ER OF U 4500 ER OF U 60 ER OF U 8 B B B M M M 6 U 30 U 40 U N N N 20 4 20 10 2 0 0 0 –70 –50 –30 –10 10 30 50 70 –350 –250 –150 –50 50 150 250 350 –1.0 –0.6 –0.2 0.2 0.6 1.0 1.4 1.8 INPUT OFFSET VOLTAGE (μV) INPUT OFFSET VOLTAGE (μV) DISTRIBUTION (μV/°C) 6241 G01 6241 G02 6241 G03 V Temperature Coeffi cient OS V Distribution LTC6240 Distribution LTC6240 Supply Current vs Supply Voltage OS 35 18 3.5 VS = ±2.5V VS = 5V, 0 16 VCM = 2.5V TA = 25°C 30 2 LOTS A)3.0 m PERCENT OF UNITS 11220505 NUMBER OF UNITS 11168024 –SP4OA0C-°8KC AA TGNOED S 1S2O5T°2C3 LY CURRENT PER AMP (2211....0550 TA = –55T°AC = 125°C 4 PP U 5 S0.5 2 0 0 0 –110–90 –70 –50 –30 –10 10 30 50 70 –0.6 –0.2 0.2 0.6 1.0 1.4 1.8 0 2 4 6 8 10 12 INPUT OFFSET VOLTAGE (μV) DISTRIBUTION (μV/°C) TOTAL SUPPLY VOLTAGE (V) 6241 G04 6241 G05 6241 G06 Offset Voltage Input Bias Current Input Bias Current vs Input Common Mode Voltage vs Common Mode Voltage vs Common Mode Voltage 300 1000 700 VS = 5V, 0V VS = 5V, 0V VS = 5V, 0V 250 600 200 TA = 125°C 500 AGE (μV) 11505000 TTAA == 12255°°CC RRENT (pA) 100 RRENT (pA) 234000000 TA = 25°C TA = 125°C VOLT 0 S CU 10 S CU 100 ET –50 TA = –55°C BIA TA = 85°C BIA 0 OFFS ––110500 NPUT 1 NPUT –100 I I–200 TA = 85°C –200 TA = 25°C –250 –300 –300 0.1 –400 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –0.8–0.6–0.4–0.2 0 0.2 0.4 0.6 0.8 1.0 INPUT COMMON MODE VOLTAGE (V) COMMON MODE VOLTAGE (V) COMMON MODE VOLTAGE (V) 6241 G07 6241 G08 6241 G09 624012fe 14

LTC6240/LTC6241/LTC6242 TYPICAL PERFORMANCE CHARACTERISTICS Output Saturation Voltage Output Saturation Voltage Input Bias Current vs Temperature vs Load Current (Output Low) vs Load Current (Output High) 1000 10 10 VCM = VS/2 V) VS = 5V, 0V V) VS = 5V, 0V GE ( TA = 25°C GE ( S CURRENT (pA) 10100 VS = 10V VS = 5V URATION VOLTA 0.11 TA = 125°C TA = –55°C URATION VOLTA 1 TA = 1T2A5 =° C25°C INPUT BIA 1 OUTPUT LOW SAT 0.01 OUTPUT HIGH SAT 0.1 TA = –55°C 0.1 0.001 0.01 25 35 45 55 65 75 85 95 105115125 0.1 1 10 100 0.1 1 10 100 TEMPERATURE (°C) LOAD CURRENT (mA) LOAD CURRENT (mA) 6241 G10 6241 G11 6241 G12 Gain Bandwidth and Phase Gain Bandwidth and Phase Margin vs Temperature Open Loop Gain vs Frequency Margin vs Supply Voltage 70 80 120 70 CL = 5pF CL = 5pF TA = 25°C VS = ±5V RL = 1k 60 6700 PHASE RVCLM = =1 kVS/2 81000 CRLL == 51pkF 60 GAIN BANDWIDTH (MHz)234000 VPSH =A S±5EV MARGIN VS =G A±I1N.5 BVANDWIDTH 345000PHASE MARGIN (DEG) GAIN (dB)1234500000 GAIN VS = ±1.5VVS V=S ± =1 .±55VV VS = ±5V –246020000PHASE (DEG) GAIN BANDWIDTH (MHz)2300 PHASE MARGIN 4500PHASE MARGIN (DEG) 0 –40 GAIN BANDWIDTH 10 VS = ±1.5V 10 –10 –60 0 –20 –80 0 –55 –35 –15 5 25 45 65 85 105 125 10k 100k 1M 10M 100M 0 2 4 6 8 10 12 TEMPERATURE (°C) FREQUENCY (Hz) TOTAL SUPPLY VOLTAGE (V) 6241 G13 6241 G14 6241 G15 Common Mode Rejection Ratio Slew Rate vs Temperature Output Impedance vs Frequency vs Frequency 20 10k 100 AV = –2 TA = 25°C TA = 25°C 18 RF = 1k, RG = 500Ω VS = ±2.5V 90 VS = ±2.5V CONDITIONS: SEE NOTE 12 1k B)80 d 16 Ω) N (70 RATE (V/μs) 1124 VS = ±2.5V FALLING VS = ±5V FALLING MPEDANCE ( 11000 AV = 10 AV = 2 DE REJECTIO456000 SLEW 180 VS = ±5V RISING UTPUT I 1 AV = 1 MON MO2300 6 VS = ±2.5V RISING O0.10 COM10 0 4 0.01 –10 –55 –35 –15 5 25 45 65 85 105 125 10k 100k 1M 10M 10k 100k 1M 10M 100M TEMPERATURE (°C) FREQUENCY (Hz) FREQUENCY (Hz) 6241 G16 6241 G17 6241 G18 624012fe 15

LTC6240/LTC6241/LTC6242 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Rejection Ratio Channel Separation vs Frequency vs Frequency Input Capacitance vs Frequency 0 90 16 –10 VTAS == 2±52°.5CV dB) 80 VTAS == 2±52°.5CV 14 VS = ±1.5V –20 AV = 1 O ( –30 ATI 70 F) 12 CCM VOLTAGE GAIN (dB)––––––456798000000 R SUPPLY REJECTION R 6543200000 NEGATIVE SUPPPOLSYITIVE SUPPLY INPUT CAPACITANCE (p 10864 –100 WE –110 PO 10 2 –120 0 0 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) 6241 G19 6241 G20 6241 G21 Output Short-Circuit Current Minimum Supply Voltage vs Power Supply Voltage Open Loop Gain 100 50 120 CHANGE IN OFFSET VOLTAGE (μV) ––––24688462000000000 VTCAM = =1 2V5S°/C2 TAT A= =– 5255°°CC UTPUT SHORT-CIRCUIT CURRENT (mA) ––––12344231000000000 SSOINUKRICNIGNG TTAAT ==A ––=55 2555°°°CCC TTAA == 112255°°CC INPUT VOLTAGE (μV) 10246800000 RRLL = = 1 1000kkTVAS == 235V°, C0V O –100 –50 0 0 1 2 3 4 5 6 7 8 9 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 TOTAL SUPPLY VOLTAGE (V) POWER SUPPLY VOLTAGE (±V) OUTPUT VOLTAGE (V) 6241 G22 6241 G23 6241 G24 Open Loop Gain Open Loop Gain Offset Voltage vs Output Current 120 100 500 TA = 25°C TA = 25°C VS = ±5V 100 VS = 5V, 0V 80 VS = ±5V 400 300 60 TA = 125°C INPUT VOLTAGE (μV) 24680000 RRLL == 110kk INPUT VOLTAGE (μV) –2420000 RRLL == 110kk OFFSET VOLTAGE (μV)––1212000000000 TA = T–A5 5=° 2C5°C –300 0 –40 –400 –20 –60 –500 0 1 2 3 4 5 –5 –4 –3 –2 –1 0 1 2 3 4 5 –50–40–30–20–10 0 10 20 30 40 50 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT CURRENT (mA) 6241 G25 6241 G26 6241 G27 624012fe 16

LTC6240/LTC6241/LTC6242 TYPICAL PERFORMANCE CHARACTERISTICS Warm-Up Drift vs Time Noise Voltage vs Frequency 0.1Hz to 10Hz Voltage Noise 25 TA = 25°C 60 TA = 25°C VS = 5V, 0V VS = ±2.5V GE IN OFFSET VOLTAGE (μV) 1215005 VVS S= =± 2±.55VV OISE VOLTAGE (nV/√Hz) 23450000 VCM = 0V LTAGE NOISE (200nV/DIV) N N O A V CH 0 VS = ±1.5V 10 –5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 1 10 100 1k 10k 100k TIME AFTER POWER UP (s) FREQUENCY (Hz) TIME (1s/DIV) 6241 G28 6241 G29 6241 G30 Series Output Resistance and Minimum Output Series Noise Current vs Frequency Overshoot vs Capacitive Load Resistance vs Capacitive Load 1000 60 1000 TA = 25°C 75pF VS = ±2.5V VS = ±2.5V <30% OVERSHOOT VCM = 0V 50 Ω) A/√Hz) 100 %) 40 1k +– 1k CRLS TANCE ( 100 NOISE CURRENT (f 110 OVERSHOOT ( 3200 RS = 10Ω RS = 50Ω PUT SERIES RESIS 110 T 10 U O VS = ±2.5V AV = –1 0.1 0 0.1 100 1k 10k 100k 10 100 1000 10pF 100pF 1000pF0.01μF 0.1μF 1μF 10μF FREQUENCY (Hz) CAPACITIVE LOAD (pF) CAPACITIVE LOAD 6241 G31 6241 G32 6241 G33 Series Output Resistance and Settling Time vs Output Step Settling Time vs Output Step Overshoot vs Capacitive Load (Non-Inverting) (Inverting) 60 3.5 3.0 75pF TA = 25°C TA = 25°C VS = ±5V VS = ±5V HOOT (%) 543000 500Ω +– 1k CRLS G TIME (μs) 223...050 AV = 1 VIN +– VO1UkT 1mV G TIME (μs)122...505 AV = –11mVIVN 1k +– 1kVOUT 1k1mV OVERS 20 RS = 10Ω RS = 50Ω SETTLIN 11..50 1mV SETTLIN1.0 10mV 10 0.5 10mV 0.5 10mV VS = ±2.5V 10mV AV = –2 0 0 0 10 100 1000 –4 –3 –2 –1 0 1 2 3 4 –4 –3 –2 –1 0 1 2 3 4 CAPACITIVE LOAD (pF) OUTPUT STEP (V) OUTPUT STEP (V) 6241 G35 6241 G36 6241 G34 624012fe 17

LTC6240/LTC6241/LTC6242 TYPICAL PERFORMANCE CHARACTERISTICS Maximum Undistorted Output Signal vs Frequency Distortion vs Frequency Distortion vs Frequency 10 –30 –30 VS = ±2.5V VS = ±5V )P-P 9 –40 AVVO U=T 1 = 2VP-P –40 AVVO U=T 1 = 2VP-P WINGING (V 786 AV = +2 AV = –1 N (dBc)––6500 RL = 1k, 2ND N (dBc)––6500 T VOLTAGE S 45 DISTORTIO––8700 RL = 1k, 3RD DISTORTIO––8700 RL = 1k, 2ND RL = 1k, 3RD PU 3 UT TA = 25°C –90 –90 O 2 VS = ±5V HD2, HD3 < –40dBc 1 –100 –100 10k 100k 1M 10M 10k 100k 1M 10M 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) 6241 G37 6241 G38 6241 G39 Distortion vs Frequency Distortion vs Frequency Small Signal Response –30 –30 VS = ±2.5V VS = ±5V AV = 2 AV = 2 –40 VOUT = 2VP-P –40 VOUT = 2VP-P –50 –50 c) c) B B d d N (–60 N (–60 RL = 1k, 2ND 0V TIO RL = 1k, 2ND TIO OR–70 OR–70 T T DIS–80 DIS–80 RL = 1k, 3RD RL = 1k, 3RD –90 –90 VS = ±2.5V 6241 G42 AV = 1 –100 –100 RL = ∞ 10k 100k 1M 10M 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) 6241 G40 6241 G41 Large Signal Response Large Signal Response Output Overdrive Recovery 0V 0V 0V VIN (1V/DIV) 0V VOUT (2V/DIV) VS = ±5V 6241 G43 VS = ±2.5V 6241 G44 VS = ±2.5V 500ns/DIV 6241 G45 AV = 1 AV = –1 AV = 3 RL = ∞ RL = 1k RL = ∞ 624012fe 18

LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION Amplifi er Characteristics The amplifi er input bias current is the leakage current of these ESD diodes. This leakage is a function of the tempera- Figure 1 is a simplifi ed schematic of the amplifi er, which ture and common mode voltage of the amplifi er, as shown has a pair of low noise input transistors M1 and M2. A in the Typical Performance Characteristics curves. simple folded cascode Q1, Q2 and R1, R2 allow the input stage to swing to the negative rail, while performing level Noise shift to the differential drive generator. Low offset voltage is accomplished by laser trimming the input stage. The LTC6240/LTC6241/LTC6242 exhibit exceptionally low 1/f noise in the 0.1Hz to 10Hz region. This 550nV P-P Capacitor C1 reduces the unity cross frequency and im- noise allows these op amps to be used in a wide variety proves the frequency stability without degrading the gain of high impedance low frequency applications, where bandwidth of the amplifi er. Capacitor CM sets the overall zero-drift amplifi ers might be inappropriate due to their amplifi er gain bandwidth. The differential drive generator charge injection. supplies signals to transistors M3 and M4 that swing the output from rail-to-rail. In the frequency region above 1kHz the LTC6240/LTC6241/ LTC6242 also show good noise voltage performance. In The photo of Figure 2 shows the output response to an this frequency region, noise can easily be dominated by input overdrive with the amplifi er connected as a voltage the total source resistance of the particular application. follower. If the negative going input signal is less than Specifi cally, these amplifi ers exhibit the noise of a 3.1kΩ a diode drop below V–, no phase inversion occurs. For resistor, meaning it is desirable to keep the source and input signals greater than a diode drop below V–, limit the feedback resistance at or below this value, i.e. R + R ||R S G FB current to 3mA with a series resistor R to avoid phase S ≤ 3.1kΩ. Above this total source impedance, the noise inversion. voltage is not dominated by the amplifi er. ESD Noise current can be estimated from the expression i = n √2qI , where q = 1.6 • 10–19 coulombs. Equating √4kTRΔf The LTC6240/LTC6241/LTC6242 have reverse-biased ESD B and R√2qI Δf shows that for source resistors below 50GΩ protection diodes on all input and outputs as shown in B the amplifi er noise is dominated by the source resistance. Figure 1. If these pins are forced beyond either supply, See the Typical Performance Characteristics curve Noise unlimited current will fl ow through these diodes. If the Current vs Frequency. current is transient and limited to one hundred milliamps or less, no damage to the device will occur. VDD = +2.5V V+ ITAIL CM M3 V– V+ V+ DESD1 DESD2 DESD5 –V2S.S5 V= DIFFERENTIAL VIN+ M1 M2 DRIVE VO GENERATOR CLAMP C1 DESD6 VOUT AND VIN OF FOLLOWER WITH LARGE INPUT OVERDRIVE VIN– V– Q1 Q2 V– +2.5V BIAS M4 RS + DESD3 DESD4 VIN LTC6240 VOUT V– V+ – R1 R2 V– –2.5V 6241 F01 6241 F02 Figure 1. Simplifi ed Schematic Figure 2. Unity Gain Follower Test Circuit 624012fe 19

LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION Proprietary design techniques are used to obtain simulta- Half the Noise neous low 1/f noise and low input capacitance. Low input The circuit shown in Figure 3 can be used to achieve even capacitance is important when the amplifi er is used with lower noise voltage. By paralleling 4 amplifi ers the noise high value source and feedback resistors. High frequency voltage can be lowered by √4, or half as much noise. The noise from the amplifi er tail current source, I in Fig- – TAIL √ comes about from an RMS summing of uncorrelated ure 1, couples through the input capacitance and appears noise sources. This circuit maintains extremely high input across these large source and feedback resistors. As an resistance, and has a 250Ω output resistance. For lower example, the photodiode amplifi er of Figure 15 on the last output resistance, a buffer amplifi er can be added without page of this data sheet shows the noise results from the infl uencing the noise. LTC6241 and the results of a competitive CMOS amplifi er. The LTC6241 output is the ideal noise of a 1MΩ resistor Stability at room temperature, 130nV√Hz. The good noise performance of these op amps can be at- +2.5 tributed to large input devices in the differential pair. Above + several hundred kilohertz, the input capacitance rises and 1/4 1k can cause amplifi er stability problems if left unchecked. LTC6242 – When the feedback around the op amp is resistive (R ), a F pole will be created with R , the source resistance, source –2.5 F capacitance (R , C ), and the amplifi er input capacitance. S S 1k 10Ω In low gain confi gurations and with R and R in even F S the kilohm range (Figure 4), this pole can create excess phase shift and possibly oscillation. A small capacitor C + F 1/4 1k in parallel with RF eliminates this problem. LTC6242 – Low Noise Single-Ended Input to Differential Output Amplifi er VIN 1k VO 10Ω The circuit on the fi rst page of the data sheet is a low noise single-ended input to differential output amplifi er, with a 200k input impedance. The very low input bias current + 1/4 1k of the LTC6241 allows for these large input and feedback LTC6242 resistors. The 200k resistors, R1 and R2, along with C1 and – C2 set the –3dB bandwidth to 80kHz. Capacitor C3 is used to cancel effects of input capacitance, while C4 adds phase lead to compensate the phase lag of the second amplifi er. 1k 10Ω CF + 1/4 1k RF LTC6242 – – CIN OUTPUT RS CS 1k 10Ω + 6241 F04 6241 F03 Figure 3. Parallel Amplifi er Lowers Noise by 2x Figure 4. Compensating Input Capacitance 624012fe 20

LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION The op amp’s good input offset voltage match and low The guard ring should extend as far as necessary to shield input bias current means that the typical differential output the high impedance signal from any and all leakage paths. offset voltage is less than 40μV. A noise spectrum plot of Figure 6 shows the use of a guard ring on the LTC6241 in the differential output is shown in Figure 5. a unity gain confi guration. In this case the guard ring is connected to the output and is shielding the high impedance Hz)140 noninverting input from V–. Figure 7 shows the inverting V/√ VS = ±2.5V gain confi guration. Y (n120 T–A3 d=B 2 B5W°C = 80kHz T SI N A Digitally Programmable AC Difference Amplifi er E100 D E AG 80 The LTC6241 confi gured as a difference amplifi er, can be T L O combined with a programmable gain amplifi er (PGA) to V T 60 PU obtain a low noise high speed programmable difference T OU 40 amplifi er. Figure 8 shows the LTC6241 based as a single- L A NTI 20 supply AC amplifi er. One LTC6241 op amp is used at the E R circuit’s input as a standard four resistor difference amplifi er. E FF 0 DI 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) LTC6241 S8 6241 F05 Figure 5. Differential Output Noise OUT+ NO SOLDER MASK NO LEAKAGE OVER THE GUARD RING CURRENT IN– Achieving Low Input Bias Current R The DD package is leadless and makes contact to the PCB IN+ beneath the package. Solder fl ux used during the attach- LEAKAGE ment of the part to the PCB can create leakage current CURRENT GUARD V– paths and can degrade the input bias current performance RING LTC6241 F06 of the part. All inputs are susceptible because the backside paddle is connected to V– internally. As the input voltage changes or if V– changes, a leakage path can be formed Figure 6. Sample Layout. Unity Gain Confi guration, Using Guard Ring to Shield High Impedance Input from Board Leakage and alter the observed input bias current. For lowest bias current, use the LTC6240/LTC6241 in the SO-8 and provide LTC6241 S8 a guard ring around the inputs that are tied to a potential OUT+ near the input voltage. R Layout Considerations and a PCB Guard Ring R In high source impedance applications such as pH probes, IN– photodiodes, strain gauges, et cetera, the low input bias VIN current of these parts requires a clean board layout to IN+ minimize additional leakage current into a high impedance signal node. A mere 100GΩ of PC board resistance GND between a 5V supply trace and an input trace adds 50pA V– of leakage current, far greater then the input bias current LTC6241 F07 of the operational amplifi er. A guard ring around the high impedance input traces driven by a low impedance source Figure 7. Sample Layout. Inverting Gain Confi guration, Using Guard Ring to Shield High Impedance Input from Board Leakage equal to the input voltage prevents such leakage problems. 624012fe 21

LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION R3 V+ contribute any signifi cant error to the LT6650 reference G2 G1 G0 0.1μF voltage. The LT6650 VREF voltage has a maximum error C1 8 7 6 5 R1 of ±2% with 1% resistors. The upper –3dB frequency of V1 LTC6910-2 the amplifi er is set by resistor R3 and capacitor C1 and + OUT AGND IN V– is limited by the bandwidth of the PGA when operated at 1/2 1 2 3 4 LTC6241 a gain of 64. Capacitor C2 is equal to C1 and is added to – VOUT maintain good common mode rejection at high frequency. R2 R4 100Ω C3 R7 V2 The lower –3dB frequency is set by the integrator resistor C2 R7, capacitor C3, and the gain setting of the LTC6910-2 V+ R1 = R2 = R3 = R4 PGA. This lower –3dB zero frequency is multiplied by the 0.1μF PGA gain. The rail-to-rail output of the LTC6910-2 PGA R5 – allows for a maximum output peak-to-peak voltage equal 1/2 1000pF LTC6241 to twice the V voltage. At the maximum gain setting of + REF R6 64, the maximum peak-to-peak difference between inputs 20k 1 LT6650 5 V1 and V2 is equal to twice VREF divided by 64. 2 VREF 1μF Example Design: Design a programmable gain AC differ- 3 4 1k V+ ence amplifi er, with a bandwidth of at least 10Hz to 100kHz, 1μF an input impedance equal to or greater than 100kΩ, and an output DC reference equal to 1V. DGIG2ITAGL 1INPUGTOS GAIN VOUT = (V1 – V2) GAIN + VREF a. Select input resistors R1, R2, R3 and R4 equal to 00 00 01 –01 VREF=0.4•(cid:165)(cid:167)(cid:166)RR65+1(cid:180)(cid:182)(cid:181) 100k. 0 1 0 –2 R5=10k•(cid:8)5•VREF–2(cid:9) R6=20k b. If the upper –3dB frequency is 100kHz then C1 = 1/(2π 0 1 1 –4 1 0 0 –8 –3dBANDWIDTH=(cid:8)fHIGH–fLOW(cid:9) • R2 • f3dB) = 1/(6.28 • 100kΩ • 100kHz) = 15pF (to 1 0 1 –16 1 GAIN 1 1 0 –32 fHIGH=2•(cid:80)•R3•C1 fLOW=2•(cid:80)•R7•C3 the nearest 5% value) and C2 = C1 = 15pF. 1 1 1 –64 6241 F08 c. Select R7 equal to one 1M and set the lower –3dB Figure 8. Wideband Difference Amplifi er with High frequency to 10Hz at the highest PGA gain of 64, then Input Impedance and Digitally Programmable Gain C3 = Gain/(2π • R7 • f3dB) = 64/(6.28 • 100kΩ • 10Hz) = 1μF. Lower gains settings will give a lower f3dB. The low bias current and current noise of the LTC6241 allow the use of high valued input resistors, 100k or d. Calculate the value of R5 to set the LT6650 reference greater. Resistors R1, R2, R3 and R4 are equal and the equal to 1V; gain of the difference amplifi er is one. An LTC6910-2 PGA V = 0.4(R5/R6 + 1), so R5 = R6(2.5V – 1). For REF REF amplifi es the difference amplifi er output with inverting R6 = 20kΩ, R5 = 30kΩ gains of –1, –2, –4, –8, –16, –32 and –64. The second With V = 1V the maximum input difference voltage LTC6241 op amp is used as an integrator to set the DC REF is equal to 2V/64 = 31.2mV. output voltage equal to the LT6650 reference voltage V . REF The integrator drives the PGA analog ground to provide 40nVpp Noise, 0.05μV/°C Drift, Chopped FET a feedback loop, in addition to blocking any DC voltage Amplifi er through the PGA. The reference voltage of the LT6650 can be set to a voltage from 400mV to V+ – 350mV with Figure 9’s circuit combines the ±5V rail-to-rail performance resistors R5 and R6. If R6 is 20k or less, the error due of the LTC6241HV with a pair of extremely low noise JFETs to the LT6650 op amp bias current is negligible. The low confi gured in a chopper based carrier modulation scheme voltage offset and drift of the LTC6241 integrator will not 624012fe 22

LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION to achieve an extraordinarily low noise and low DC drift. with the input chopper, proper amplitude and polarity The performance of this circuit is suited for the demand- information is presented to A2, the DC output amplifi er. ing transducer signal conditioning situations such as high This stage integrates the square wave into a DC voltage, resolution scales and magnetic search coils. providing the output. The output is divided down (R2 and R1) and fed back to the input chopper where it serves as The LTC1799’s output is divided down to form a 2-phase a zero signal reference. Gain, in this case 1000, is set by 925Hz square wave clock. This frequency, harmonically the R1-R2 ratio. Because A1 is AC coupled, its DC offset unrelated to 60Hz, provides excellent immunity to harmonic and drift do not affect the overall circuit offset, resulting beating or mixing effects which could cause instabilities. in the extremely low offset and drift noted. The JFETs S1 and S2 receive complementary drive, causing A1 to have an input RC damper that minimizes offset voltage see a chopped version of the input voltage. A1’s square contribution due to parasitic switch behavior, resulting in wave output is synchronously demodulated by S3 and the 1μV offset specifi cation. S4. Because these switches are synchronously driven 5V –5V TO LTC201 V+ PIN TO LTC201 V– PIN 1μF 1μF + + 5V 5V 18.5kHz V+ 5V DIV LTC1799 OUT 74C90 ÷ 10 74C74 ÷ 2 RSET Q Q 925Hz 54.2k* TO TO 5V Ø1 Ø2 Ø1 POINTS POINTS 8 898Ω** 898Ω** 30.1Ω 7 6 INPUT S1 Ø2 0.01μF S2 1 1μF 10 11 LSK389 – A1 1μF 2 3 9 LTC6241HV S3 240k Ø2 499Ω** + S4 – 10M A2 –5V 15 14 LTC6241HV OUTPUT 16 + 10k Ø1 R2 1μF 10k * = 0.1% METAL FILM RESISTOR NOISE= 40nVP-P 0.1Hz TO 10Hz R1 ** = 1% METAL FILM RESISTOR OFFSET= 1μV 10Ω = LTC201 QUAD DRIFT= 0.05μV/°C R2 GAIN= +1 = LSK389 10 = LINEAR INTEGRATED SYSTEMS OPEN-LOOP GAIN= 109 FREMONT, CA IBIAS= 500pA 6241 F09 Figure 9. Ultralow Noise Chopper Amplifi er 624012fe 23

LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION The noise measured over a 50 second interval, in Figure 10, by the sensor is forced across the feedback capacitor is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is at- by the op amp action. Because the feedback capacitor tributed to the input JFET’s die size and current density. is 100 times smaller than the sensor, it will be forced to 100 times what would have been the sensor’s open circuit voltage. So the circuit gain is 100. The benefi t of this ap- proach is that the signal gain of the circuit is independent of any cable capacitance introduced between the sensor and the amplifi er. Hence this circuit is favored for remote 20nV/DIV accelerometers where the cable length may vary. Diffi culties with the circuit are inaccuracy of the gain setting with the small capacitor, and low frequency cutoff due to the bias resistor working into the small feedback capacitor. 5s/DIV 6241 F10 Figure 12 shows a noninverting amplifi er approach. This Figure 10. Noise in a 0.1Hz to 10Hz Bandwidth approach has many advantages. First of all, the gain is set accurately with resistors rather than with a small capaci- Low Noise Shock Sensor Amplifi ers tor. Second, the low frequency cutoff is dictated by the bias resistor working into the large 770pF sensor, rather Figures 11 and 12 show the amplifi ers realizing two dif- than into a small feedback capacitor, for lower frequency ferent approaches to amplifying signals from a capacitive response. Third, the noninverting topology can be paral- sensor. The sensor in both cases is a 770pF piezoelectric leled and summed (as shown) for scalable reductions in shock sensor accelerometer, which generates charge under voltage noise. The only drawback to this circuit is that the physical acceleration. parasitic capacitance at the input reduces the gain slightly. Figure 11 shows the classical “charge amplifi er” approach. This circuit is favored in cases where parasitic input The LTC6240 is in the inverting confi guration so the sensor capacitances such as traces and cables will be relatively looks into a virtual ground. All of the charge generated small and invariant. VS+ + 1/2 SHOCK SENSOR LTC6241HV + MURATA-ERIE – PKGS-00LD 1k LTC6240 770pF SHOCK SENSOR 100Ω 10k MURATA-ERIE – VOUT PKGS-00LD Cf VOUT = 110mV/g 770pF 7.7pF 1G 1k + BIAS RESISTOR 1/2 MAIN VISHAY-TECHNO LTC6241HV Rf GAIN-SETTING CRHV2512AF1007G – CABLE HAS 1G ELEMENT IS A (OR EQUIVALENT) VOUT = 110mV/g UNKNOWN C BIAS RESISTOR CAPACITOR VS– VBSW = = ± 01..24HVz t oto ± 150.5kHVz VISHAY-TECHNO 100Ω 10k CRHV2512AF1007G (OR EQUIVALENT) 6241 F11 6241 F12 Figure 11. Classical Inverting Charge Amplifi er Figure 12. Low Noise Noninverting Shock Sensor Amplifi er 624012fe 24

LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION 1M Transimpedance Amplifi er with 43nV/√Hz By achieving an output swing of 50V before attenuation, Output Noise the circuit provides an output swing to 5V after attenu- ation. The 10M resistor sets the gain of the TIA stage In a normal 1M transimpedance amplifi er, like that shown and has a noise density of 400nV/√Hz. After attenuation, on the back page of this data sheet, the output noise density the effective TIA gain drops to 1M while the noise fl oor must be at least 130nV/√Hz at room temperature. This is drops to 40nV/√Hz, which clearly dominates the observed true even should the op amp be perfectly noiseless, because 43nV/√Hz. Note the additional benefi t that the offset voltage the 1M resistor provides 130nV/√Hz of voltage noise at of the op amp is divided by 10. Worst-case output offset room temperature independently of the op amp. for this circuit is 150μV over temperature. The circuit of Figure 13 provides an overall transimpedance gain of 1MΩ, but it has an output noise density of only Reference Buffer 43nV/√Hz, about 1/3 of the normal transimpedance ampli- Figure 14 shows the LTC6240 being utilized as a buffer fi er. It does this by taking a higher initial transimpedance in conjunction with the LT1019 reference. The passive gain of 10M and then attenuating by a factor of 10. The R-C fi lter attenuates the reference noise and the LTC6240 transistor section provides voltage gain and works on a provides a low noise buffer, resulting in an output noise 54V supply voltage to guarantee adequate output swing. of 8nV/√Hz. 54V 0.3pF 33k MPSA06 5V 10M 10M GAIN 1% (10V/μA) + 10k 3pF LTC6240HV MPSA06 9.09k PHOTODIODE – 1% –1.5V 100pF 1/4W VOUT –5V 10k 2.4k 43k 1M GAIN (1V/μA) 1k 1k 1% –5V 6241 F13 Figure 13. 1M Transimpedance Amplifi er with 43nV/√Hz Output Noise 5V 1M 180nV/√Hz LT1019-2.5 + 0.2Ω 8nV/√Hz 1μF LTC6240HV VOUT – 10μF CERAMIC –5V OR FILM 6241 F14 Figure 14. Low Noise Reference Buffer 624012fe 25

LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) 0.70(cid:112)0.05 3.5(cid:112)0.05 1.65(cid:112)0.05 2.10(cid:112)0.05 (2 SIDES) PACKAGE OUTLINE 0.25(cid:112) 0.05 0.50 BSC 2.38(cid:112)0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.125 0.40(cid:112) 0.10 TYP 5 8 3.00(cid:112)0.10 1.65(cid:112) 0.10 (4 SIDES) (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD8) DFN 0509 REV C 4 1 0.200 REF 0.75(cid:112)0.05 0.25(cid:112) 0.05 0.50 BSC 2.38(cid:112)0.10 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 624012fe 26

LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTION DHC Package 16-Lead Plastic DFN (5mm × 3mm) (Reference LTC DWG # 05-08-1706) 0.65 ±0.05 3.50 ±0.05 1.65 ±0.05 2.20 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 4.40 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 5.00 ±0.10 R = 0.115 0.40 ± 0.10 TYP (2 SIDES) 9 16 R = 0.20 TYP 3.00 ±0.10 1.65 ± 0.10 (2 SIDES) (2 SIDES) PIN 1 PIN 1 TOP MARK NOTCH (SEE NOTE 6) (DHC16) DFN 1103 8 1 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 BSC 4.40 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 624012fe 27

LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 ±.005 .189 – .196* (4.801 – 4.978) .009 (0.229) 16 15 14 13 12 11 109 REF .254 MIN .150 – .165 .229 – .244 .150 – .157** (5.817 – 6.198) (3.810 – 3.988) .0165 ±.0015 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 .015 ± .004 × 45° .0532 – .0688 .004 – .0098 (0.38 ± 0.10) (1.35 – 1.75) (0.102 – 0.249) .007 – .0098 0° – 8° TYP (0.178 – 0.249) .016 – .050 .008 – .012 .0250 GN16 (SSOP) 0204 (0.406 – 1.270) (0.203 – 0.305) (0.635) NOTE: TYP BSC 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 624012fe 28

LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTION S5 Package 5-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1635 Rev B) 0.62 0.95 2.90 BSC MAX REF (NOTE 4) 1.22 REF 1.50 – 1.75 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC (NOTE 4) PIN ONE RECOMMENDED SOLDER PAD LAYOUT 0.30 – 0.45 TYP 0.95 BSC PER IPC CALCULATOR 5 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 1.90 BSC NOTE: (NOTE 3) S5 TSOT-23 0302 REV B 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 624012fe 29

LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 .045 ±.005 (4.801 – 5.004) .050 BSC NOTE 3 8 7 6 5 .245 MIN .160 ±.005 .150 – .157 .228 – .244 (3.810 – 3.988) (5.791 – 6.197) NOTE 3 .030 ±.005 TYP 1 2 3 4 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° .053 – .069 (0.254 – 0.508) (1.346 – 1.752) .004 – .010 .008 – .010 (0.203 – 0.254) 0°– 8° TYP (0.101 – 0.254) .016 – .050 .014 – .019 .050 (0.406 – 1.270) (0.355 – 0.483) (1.270) NOTE: INCHES TYP BSC 1. DIMENSIONS IN (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 0303 624012fe 30

LTC6240/LTC6241/LTC6242 REVISION HISTORY (Revision history begins at Rev E) REV DATE DESCRIPTION PAGE NUMBER E 07/10 Update to Simplifi ed Schematic (Figure 1) 19 624012fe Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 31 However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC6240/LTC6241/LTC6242 TYPICAL APPLICATION 1MΩ TIA 150kHz 3RD ORDER BUTTERWORTH FILTER + R1 R2 R3 C2 +1.5V 1/2 866Ω 1.69k 2k 1500pF + LTC6241 1/2 – C1 C3 LTC6241 RF 1500pF 180pF 1M – SFH213FA –1.5V OR EQUIVALENT (≤4pF) 6241 TA02a CF –1.5V 1pF Figure 15. Ultralow Noise 1MΩ 150kHz Photodiode Amplifi er LTC6241 Output Noise Spectrum. 1MΩ Resistor Noise Competition Output Noise Spectrum. Op Amp Noise Dominates; Dominates; Ideal Performance Performance Compromised V V DI DI R R E E P P Hz Hz √ √ V/ V/ n n 0 0 3 3 0V 0V 1kHz 10kHz/DIV 101kHz 1kHz 10kHz/DIV 101kHz 6241 TA02b 6241 TA02c RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1151 ±15V Zero-Drift Op Amp Dual High Voltage Operation ±18V LT1792 Low Noise Precision JFET Op Amp 6nV/√Hz Noise, ±15V Operation LTC2050 Zero-Drift Op Amp 2.7 Volt Operation, SOT-23 LTC2051/LTC2052 Dual/Quad Zero-Drift Op Amp Dual/Quad Version of LTC2050 in MS8/GN16 Packages LTC2054/LTC2055 Single/Dual Zero-Drift Op Amp Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages LTC6244 Dual 50MHz Rail-to-Rail Op Amp 100μV V , 1pA I , 40V/μV, Slew Rate OS(MAX) BIAS 624012fe 32 Linear Technology Corporation LT 0710 REV E • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC6240IS5#TRPBF LTC6240CS8#TRPBF LTC6241HS8 LTC6241HVIS8 LTC6242IDHC#TR LTC6242HVCDHC#TRPBF LTC6240HVHS5#TRMPBF LTC6242HGN LTC6242IDHC#TRPBF LTC6242HVIGN LTC6241HVCDD#TRPBF LTC6241HVHS8#PBF LTC6242CDHC#PBF LTC6242HVCDHC#TR LTC6242CGN#TRPBF LTC6242HVHGN#PBF LTC6241IDD#TR LTC6242HVIDHC#TRPBF LTC6241HVCDD#TR LTC6242CDHC LTC6240HVHS8#TRPBF LTC6241HVIDD#TRPBF LTC6240HVCS5#PBF LTC6241CDD#PBF LTC6241HVCS8#PBF LTC6242HVHGN#TRPBF LTC6242HVIDHC#TR LTC6240HS5#TRMPBF LTC6240HS8#PBF LTC6242HVHGN LTC6242CGN#TR LTC6242CDHC#TRPBF LTC6241CDD LTC6241HVIDD#TR LTC6241IDD LTC6241HS8#PBF LTC6240HVIS5#TRMPBF LTC6241HVIS8#PBF LTC6242HVIGN#PBF LTC6240HVHS5#TRPBF LTC6240HVCS8#PBF LTC6241CS8#PBF LTC6240HS5#PBF LTC6241CS8#TR LTC6240HS8#TRPBF LTC6241HVCDD LTC6241HVIDD#PBF LTC6242HVCDHC LTC6240CS5#TRMPBF LTC6242IGN#TR LTC6242HVCGN#TR LTC6242HVIDHC#PBF LTC6241IS8#TR LTC6241IS8#PBF LTC6240HVCS5#TRMPBF LTC6240HVIS5#PBF LTC6240HVCS8#TRPBF LTC6241HVIDD LTC6242HGN#TRPBF LTC6240HVIS5#TRPBF LTC6240IS5#PBF LTC6241CS8 LTC6242CGN LTC6242HVCGN#PBF LTC6241HVIS8#TRPBF LTC6240HVIS8#TRPBF LTC6241HVIS8#TR LTC6240CS5#PBF LTC6240HVHS8 LTC6242IGN LTC6241IDD#PBF LTC6241HVCS8 LTC6241IS8 LTC6242HVIGN#TR LTC6240CS5#TRPBF LTC6240HVIS8#PBF LTC6240HVHS8#PBF LTC6240CS8#PBF LTC6241CS8#TRPBF LTC6242HVIDHC LTC6242CDHC#TR LTC6242HVCGN#TRPBF LTC6240HS5#TRPBF LTC6242HVHGN#TR LTC6241HS8#TRPBF LTC6241HVHS8#TR LTC6241IS8#TRPBF LTC6241HVCS8#TRPBF LTC6240HVHS5#PBF LTC6240HVCS5#TRPBF LTC6242IDHC#PBF LTC6241CDD#TR LTC6240IS5#TRMPBF LTC6242HVCDHC#PBF LTC6240IS8#TRPBF LTC6242IGN#TRPBF LTC6241IDD#TRPBF LTC6241CDD#TRPBF LTC6240IS8#PBF LTC6242IDHC