LTC6078/LTC6079 Micropower Precision, Dual/Quad CMOS Rail-to-Rail Input/Output Amplifi ers FEATURES DESCRIPTIOU ■ Maximum Offset Voltage of 25µV (25°C) The LTC®6078/LTC6079 are dual/quad, low offset, low ■ Maximum Offset Drift of 0.7µV/°C noise operational amplifi ers with low power consumption ■ Maximum Input Bias: and rail-to-rail input/output swing. 1pA (25°C) Input offset voltage is trimmed to less than 25µV and the 50pA (≤85°C) CMOS inputs draw less than 50pA of bias current. The low ■ Micropower: 54µA per Amp offset drift, excellent CMRR, and high voltage gain make ■ 95dB CMRR (Min) it a good choice for precision signal conditioning. ■ 100dB PSRR (Min) ■ Input Noise Voltage Density: 16nV/√Hz Each amplifi er draws only 54µA current on a 3V supply. The ■ Rail-to-Rail Inputs and Outputs micropower, rail-to-rail operation of the LTC6078/LTC6079 ■ 2.7V to 5.5V Operation Voltage is well suited for portable instruments and single supply ■ LTC6078 Available in 8-Lead MSOP and 10-Lead DFN applications. Packages; LTC6079 Available in 16-Lead SSOP and The LTC6078/LTC6079 are specifi ed on power supply DFN Packages voltages of 3V and 5V from –40 to 125°C. The dual am- plifi er LTC6078 is available in 8-lead MSOP and 10-lead APPLICATIOUS DFN packages. The quad amplifi er LTC6079 is available in 16-lead SSOP and DFN packages. ■ Photodiode Amplifi er , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. ■ High Impedance Sensor Amplifi er All other trademarks are the property of their respective owners. Patent Pending. ■ Microvolt Accuracy Threshold Detection ■ Instrumentation Amplifi ers ■ Battery Powered Applications TYPICAL APPLICATIOU Thermocouple Signal Conditioner V Distribution OS 14 LTC6078MS8 NFOLROMATAILNLGY 11S/5M40WTk +5V OF 200 1120 VVTASC M == =23 5V0°.C5V 0.1µF 1/2 OUT = 10mV/°C UT 5TC-OTMT-EKG-3A0-36 –LTC6078 0°C TO 500°C ±0.5°C PS O 8 THERMOCOUPLE 1S/M4WT 5V 2.49M 1k F AM 6 O 150k R K 40.6µV/°C BE 4 LT1025 10k M 100pF U N 5.6pF 2 60789 TA01a AMPLIFIER PROTECTED TO ±190V, ACCIDENTAL CONTACT 0–11 –9 –7 –5 –3 –1 1 3 5 7 9 VOS (µV) 60789 TA01b 60789fa 1

LTC6078/LTC6079 ABSOLUTE WAXIWUW RATIUGS (Note 1) Total Supply Voltage (V+ to V–) ...................................6V Specifi ed Temperature Range (Note 4) Input Voltage ......................................................V– to V+ LTC6078C, LTC6079C ..............................0°C to 70°C Output Short Circuit Duration (Note 2) ............Indefi nite LTC6078I, LTC6079I ............................–40°C to 85°C Operating Temperature Range (Note 3) LTC6078H, LTC6079H ........................–40°C to 125°C LTC6078C, LTC6079C ..........................–40°C to 85°C Junction Temperature LTC6078I, LTC6079I ............................–40°C to 85°C DFN Packages ...................................................125°C LTC6078H, LTC6079H ........................–40°C to 125°C All Other Packages ............................................150°C (Not Available in DFN Package) Storage Temperature Range DFN Packages ....................................–65°C to 125°C All Other Packages .............................–65°C to 150°C Lead Temperature (Soldering, 10 Sec) ..................300°C PACKAGE/ORDER IUFORWATIOU ORDER PART DD PART NUMBER MARKING* TOP VIEW LTC6078CDD LBBB LTC6078IDD LBBB OUTA 1 10 V+ TOP VIEW –INA 2 A 9 OUTB OUTA1 8V+ ORDER PART MS8 PART +INVA– 43 B 78 –+IINNBB –+IINNVAA–234 A B 765O–+IIUNNTBBB NUMBER MARKING* SHDN_A 5 6 SHDN_B MS8 PACKAGE LTC6078ACMS8 LTAJZ 8-LEAD PLASTIC MSOP DD PACKAGE LTC6078CMS8 LTAJZ 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 200°C/W LTC6078AIMS8 LTAJZ TJMAX = 125°C, θJA = 43°C/W UNDERSIDE METAL CONNECTED TO V– LTC6078IMS8 LTAJZ LTC6078AHMS8 LTAJZ LTC6078HMS8 LTAJZ TOP VIEW ORDER PART DHC PART TOP VIEW NUMBER MARKING* OUTA 1 16 OUTD OUTA 1 16 OUTD –INA 2 A D 15 –IND –INA 2 A D 15 –IND LTC6079CDHC 6079 +INA 3 14 +IND +INA 3 14 +IND LTC6079IDHC 6079 V+ 4 13 V– V+ 4 13 V– +INB 5 B C 12 +INC +INB 5 B C 12 +INC ORDER PART GN PART –INB 6 11 –INC NUMBER MARKING –INB 6 11 –INC OUTB 7 10 OUTC OUTB 7 10 OUTC LTC6079CGN 6079 NC 8 9 NC NC 8 9 NC LTC6079IGN 6079I 16-LEAD (5mDHmC × P 3AmCKmA)G PELASTIC DFN 16-LEGAND PPALCAKSATIGCE SSOP LTC6079HGN 6079H UNDETRJMSIADXE = M 12E5TA°CL, CθOJAN =N E4C3T°CED/W TO V– TJMAX = 150°C, θJA = 110°C/W Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grades and parametric grades are identifi ed by a label on the shipping container. 60789fa 2

LTC6078/LTC6079 ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. Test conditions are V+ = 3V, V– = 0V, V = 0.5V unless otherwise noted. A CM SYMBOL PARAMETER CONDITIONS C, I SUFFIXES H SUFFIX UNITS MIN TYP MAX MIN TYP MAX V Offset Voltage (Note 5) LTC6078MS8, LTC6078AMS8, LTC6079GN OS V = 0.5V, 2.5V ±7 ±25 ±7 ±25 μV CM LTC6078DD, LTC6079DHC V = 0.5V, 2.5V ±7 ±30 μV CM LTC6078AMS8 V = 0.5V ● ±20 ±70 ±25 ±95 μV CM LTC6078MS8 V = 0.5V ● ±25 ±97 ±30 ±135 μV CM LTC6079GN V = 0.5V ● ±30 ±115 ±35 ±165 μV CM LTC6078DD V = 0.5V ● ±30 ±120 μV CM LTC6079DHC V = 0.5V ● ±35 ±150 μV CM ΔVOS⁄ΔT Input Offset Voltage Drift LTC6078AMS8 ● ±0.2 ±0.7 ±0.2 ±0.7 μV/°C (Note 5) LTC6078MS8 ● ±1.1 ±1.1 μV/°C LTC6078DD, LTC6079GN ● ±0.3 ±1.4 ±0.3 ±1.4 μV/°C LTC6079DHC ● ±0.3 ±1.8 μV/°C I Input Bias Current V = V+/2 0.2 1 0.2 1 pA B CM (Note 6) V = V+/2 ● 10 50 150 350 pA CM I Input Offset Current V = V+/2 0.1 0.1 pA OS CM (Note 6) V = V+/2 ● 0.5 25 10 100 pA CM e Input Noise Voltage 0.1Hz to 10Hz 1 1 µV n P-P Input Noise Voltage Density f = 1kHz 18 18 nV/√Hz f = 10kHz 16 16 nV/√Hz i Input Noise Current Density 0.56 0.56 fA/√Hz n (Note 8) Input Common Mode Range ● V– V+ V– V+ V C Differential Input Capacitance 10 10 pF DIFF C Common Mode Input 18 18 pF CM Capacitance CMRR Common Mode Rejection All Packages V = 0V to 3V 95 110 95 110 dB CM Ratio LTC6078AMS8 V = 0V to 3V ● 87 105 87 103 dB CM LTC6078AMS8 V = 0V to 1.7V ● 91 103 91 103 dB CM LTC6078MS8 V = 0V to 3V ● 85 102 85 100 dB CM LTC6078MS8 V = 0V to 1.7V ● 89 102 89 102 dB CM LTC6079GN V = 0V to 3V ● 84 102 84 100 dB CM LTC6079GN V = 0V to 1.7V ● 88 102 88 102 dB CM LTC6078DD, LTC6079DHC V = 0V to 3V ● 83 100 dB CM LTC6078DD, LTC6079DHC V = 0V to 1.7V ● 87 102 dB CM PSRR Power Supply Rejection Ratio V = 2.7V to 5.5V 100 120 100 120 dB S ● 97 97 dB V Output Voltage, High No Load 1 1 mV OUT (Referred to V+) I = 0.2mA ● 35 15 40 15 mV SOURCE I = 2mA ● 350 150 400 150 mV SOURCE Output Voltage, Low No Load 1 1 mV (Referred to V–) I = 0.2mA ● 10 30 10 35 mV SINK I = 2mA ● 100 300 100 350 mV SINK A Large-Signal Voltage Gain R = 10k, 0.5V ≤ V ≤ 2.5V ● 115 130 110 125 dB VOL LOAD OUT I Output Short-Circuit Current Source ● 5 10 4 10 mA SC Sink ● 7 14 6 14 mA SR Slew Rate A = 1 0.05 0.05 V/μs V GBW Gain-Bandwidth Product R = 100k 420 750 420 750 kHz L (f = 10kHz) ● 360 320 kHz TEST Φ0 Phase Margin RL = 10k, CL = 200pF 66 66 Deg t Settling Time 0.1% A = 1, 1V Step 24 24 μs S V 60789fa 3

LTC6078/LTC6079 ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. Test conditions are V+ = 3V, V– = 0V, V = 0.5V unless otherwise noted. A CM SYMBOL PARAMETER CONDITIONS C, I SUFFIXES H SUFFIX UNITS MIN TYP MAX MIN TYP MAX I Supply Current No Load 54 72 54 72 μA S (per Amplifi er) ● 78 80 μA Shutdown Current Shutdown, V ≤ 0.8V, LTC6078DD ● 0.3 1 μA SHDN (per Amplifi er) V Supply Voltage Range Guaranteed by the PSRR Test ● 2.7 5.5 2.7 5.5 V S Channel Separation f = 10kHz, R = 10k –110 –110 dB s L Shutdown Logic SHDN High, LTC6078DD ● 2 2 V SHDN Low, LTC6078DD ● 0.8 0.8 V t Turn on Time V = 0.8V to 2V, LTC6078DD 50 50 µs ON SHDN t Turn off Time V = 2V to 0.8V, LTC6078DD 2 2 µs OFF SHDN Leakage of SHDN Pin V = 0V, LTC6078DD 0.6 μA SHDN The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. Test conditions are V+ = 5V, V– = 0V, V = 0.5V unless otherwise noted. CM SYMBOL PARAMETER CONDITIONS C, I SUFFIXES H SUFFIX UNITS MIN TYP MAX MIN TYP MAX V Offset Voltage LTC6078MS8, LTC6078AMS8, LTC6079GN OS V = 0.5V ±10 ±30 ±10 ±30 μV CM LTC6078DD, LTC6079DHC V = 0.5V ±10 ±35 μV CM LTC6078AMS8 V = 0.5V ● ±20 ±75 ±25 ±100 μV CM LTC6078MS8 V = 0.5V ● ±25 ±102 ±30 ±140 μV CM LTC6079GN V = 0.5V ● ±30 ±120 ±35 ±170 μV CM LTC6078DD V = 0.5V ● ±30 ±125 μV CM LTC6079DHC V = 0.5V ● ±35 ±155 μV CM ΔVOS⁄ΔT Input Offset Voltage Drift LTC6078AMS8 ● ±0.2 ±0.7 ±0.2 ±0.7 μV/°C (Note 7) LTC6078MS8 ● ±1.1 ±1.1 μV/°C LTC6078DD, LTC6079GN ● ±0.3 ±1.4 ±0.3 ±1.4 μV/°C LTC6079DHC ● ±0.3 ±1.8 μV/°C I Input Bias Current V = V+/2 0.2 1 0.2 1 pA B CM V = V+/2 ● 10 50 150 350 pA CM I Input Offset Current V = V+/2 0.1 0.1 pA OS CM V = V+/2 ● 0.5 25 10 100 pA CM e Input Noise Voltage 0.1Hz to 10Hz 1 1 µV n P-P Input Noise Voltage Density f = 1kHz 18 18 nV/√Hz f = 10kHz 16 16 nV/√Hz i Input Noise Current Density 0.56 0.56 fA/√Hz n (Note 8) Input Common Mode Range ● V– V+ V– V+ V C Differential Input Capacitance 10 10 pF DIFF C Common Mode Input 18 18 pF CM Capacitance 60789fa 4

LTC6078/LTC6079 ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. Test conditions are V+ = 5V, V– = 0V, V = 0.5V unless otherwise noted. A CM SYMBOL PARAMETER CONDITIONS C, I SUFFIXES H SUFFIX UNITS MIN TYP MAX MIN TYP MAX CMRR Common Mode Rejection All Packages V = 0V to 5V 91 105 91 105 dB CM Ratio LTC6078AMS8 V = 0V to 5V ● 90 105 90 105 dB CM LTC6078AMS8 V = 0V to 3.7V ● 94 105 94 105 dB CM LTC6078MS8 V = 0V to 5V ● 88 100 88 100 dB CM LTC6078MS8 V = 0V to 3.7V ● 90 105 90 105 dB CM LTC6079GN V = 0V to 5V ● 86 100 86 100 dB CM LTC6079GN V = 0V to 3.7V ● 90 105 90 105 dB CM LTC6078DD, LTC6079DHC V = 0V to 5V ● 86 100 dB CM LTC6078DD, LTC6079DHC V = 0V to 3.7V ● 90 105 dB CM PSRR Power Supply Rejection Ratio V = 2.7V to 5.5V 100 120 120 dB S ● 97 97 dB V Output Voltage, High No Load 2 2 mV OUT (Referred to V+) ISOURCE = 0.5mA ● 50 20 55 20 mV ISOURCE = 5mA ● 500 200 550 200 mV Output Voltage, Low No Load 1 1 mV (Referred to V–) ISINK = 0.5mA ● 15 40 15 45 mV ISINK = 5mA ● 150 400 150 450 mV A Large-Signal Voltage Gain R = 10k, 0.5V ≤ V ≤ 4.5V ● 115 130 110 125 dB VOL LOAD OUT I Output Short-Circuit Current Source ● 14 25 12 25 mA SC Sink ● 14 25 12 25 mA SR Slew Rate A = 1 0.05 0.05 V/μs V GBW Gain-Bandwidth Product R = 100k 420 750 420 750 kHz L (f = 10kHz) ● 360 320 kHz TEST Φ0 Phase Margin RL = 10k, CL = 200pF 66 66 Deg t Settling Time 0.1% A = 1, 1V Step 24 24 μs S V I Supply Current No Load 55 74 55 74 μA S (per Amplifi er) ● 82 84 μA Shutdown Current Shutdown, V ≤ 1.2V, LTC6078DD ● 1.5 5 1.5 5 μA SHDN (per Amplifi er) V Supply Voltage Range Guaranteed by the PSRR Test ● 2.7 5.5 2.7 5.5 V S Channel Separation f = 10kHz, R = 10k –110 –110 dB s L Shutdown Logic SHDN High, LTC6078DD ● 3.5 3.5 V SHDN Low, LTC6078DD ● 1.2 1.2 V t Turn on Time V = 1.2V to 3.5V, LTC6078DD 50 50 µs ON SHDN t Turn off Time V = 1.2V to 3.5V, LTC6078DD 2 2 µs OFF SHDN Leakage of SHDN Pin V = 0V, LTC6078DD 0.6 μA SHDN Note 1: Stresses beyond those listed under Absolute Maximum Ratings performance from 0°C to 70°C. The LTC6078C/LTC6079C are designed, may cause permanent damage to the device. Exposure to any Absolute characterized and expected to meet specifi ed performance from –40°C Maximum Rating condition for extended periods may affect device to 85°C but are not tested or QA sampled at these temperatures. The reliability and lifetime. LTC6078I/LTC6079I are guaranteed to meet specifi ed performance from Note 2: A heat sink may be required to keep the junction temperature –40°C to 85°C. The LTC6078H/LTC6079H are guaranteed to meet specifi ed below the absolute maximum. This depends on the power supply voltage performance from –40°C to 125°C. and how many amplifi ers are shorted. Note 5: V and V drift are 100% tested at 25°C and 125°C. OS OS Note 3: The LTC6078C/LTC6079C and LTC6078I/LTC6079I are guaranteed Note 6: I and I are guaranteed by the V = 5V test. B OS S functional over the operating temperature range of –40°C to 85°C. The Note 7: V drift is guaranteed by the V = 3V test. OS S LTC6078H/LTC6079H are guaranteed functional over the operating Note 8: Current noise is calculated from i = √2qI , where q = 1.6 • 10–19 n B temperature range of –40°C to 125°C. coulomb. Note 4: The LTC6078C/LTC6079C are guaranteed to meet specifi ed 60789fa 5

LTC6078/LTC6079 TYPICAL PERFORW AU CE CHARACTERISTICS V Distribution V vs V V vs V OS OS CM OS CM 14 LTC6078MS8 40 VS = 3V 100 VS = 5V 0 12 VVSCM = =3 V0.5V 30 TRAE P=R 2E5S°ECNTATIVE PARTS 80 TRAE P=R 2E5S°ECNTATIVE PARTS 20 TA = 25°C 60 T OF 10 20 40 S OU 8 V) 10 V) 20 P µ µ R OF AM 6 V (OS –100 V (OS –200 BE 4 –40 M –20 NU –60 2 –30 –80 0 –40 –100 –11 –9 –7 –5 –3 –1 1 3 5 7 9 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOS (µV) VCM (V) VCM (V) 60789 G01 60789 G02 60789 G03 V Drift Distribution Input Bias vs Temperature Input Bias vs V OS CM 50 180 30 LTC6078MS8 VS = 5V VS = 5V 45 VS = 3V 160 VCM = 2.5V 24 NUMBER OF AMPS OUT OF 200 43322110055050 VTAC M= =– 400.5°CV TO 125°C INPUT BIAS CURRENT (pA) 111402468000000 INPUT BIAS CURRENT (pA)––11––118260628 TTAA = = 8 750°°CC 5 20 –24 0 0 –30 –0.8–0.6–0.4–0.2 0 0.2 0.4 0.6 0.8 0 25 50 75 100 125 0 1 2 3 4 5 µV/°C TEMPERATURE (°C) VCM (V) 60789 G04 60789 G05 60789 G06 0.1Hz to 10Hz Output Voltage Input Bias vs V Voltage Noise Spectrum Noise CM 400 90 VS = 5V VS = 5V 300 TA = 125°C 80 VCM = 0.5V S CURRENT (pA) 2100–000 √LTAGE (nV/Hz) 76540000 OISE (500nV/DIV) A O N INPUT BI ––120000 NOISE V 3200 VVSC M= =3 V0.5V VOLTAGE –300 10 VS = 5V VCM = 0.5V –400 0 0 1 2 3 4 5 1 10 100 1k 10k 100k TIME (5s/DIV) VCM (V) FREQUENCY (Hz) 60789 G09 60789 G07 60789 G08 60789fa 6

LTC6078/LTC6079 TYPICAL PERFORW AU CE CHARACTERISTICS Output Voltage Swing vs Load Current Supply Current vs Supply Voltage Supply Current vs Temperature +VS 60 65 PER AMPLIFIER G (V)LTAGE) ++VVSS ––01..50 SOURCE A) 50 A) 60 VCM = 0.5V VS = 5V OUTPUT VOLTAGE SWINREFERRED TO SUPPLY VO ++–––VVVVVSSSSS ––+++12211.....50050 VVSC M= TT=5AA V0 ==.7 12V255°C°C SINK µSUPPLY CURRENT ( 43210000 PER AMPLIFIER µSUPPLY CURRENT ( 545055 VS = 3V ( –VS +0.5 TA = –55°C VCM = 0.5V –VS 0 TA = 25°C 40 0.01 0.1 1 10 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –40–25–10 5 20 35 50 65 80 95 110125 LOAD CURRENT (mA) SUPPLY VOLTAGE (V) TEMPERATURE (°C) 60789 G10 60789 G11 60789 G12 Open Loop Gain vs Frequency CMRR vs Frequency PSRR vs Frequency 100 100 120 140 RL = 10k VS = 5V VS = 5V RL = 100k VCM = 0.5V VCM = 0.5V 80 80 100 TA = 25°C 120 TA = 25°C RL = 1k 60 60 80 100 PHASE P GAIN (dB) 4200 4200 HASE (DEG CMRR (dB) 6400 PSRR (dB) 8600 ) 0 0 20 40 VS = 5V GAIN –20 VCM = 0.5V –20 0 20 CL = 200pF TA = 25°C –40 –40 –20 0 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) 60789 G13 60789 G14 60789 G15 Output Impedance vs Frequency Small Signal Transient Large Signal Transient 10000 VS = 5V VCM = 0.5V 1000 TA = 25°C ΩNCE () 100 AV = 10A0V = 10 20mV/DIV 1V/DIV A D PE 10 T IM AV = 1 PU 1 T U O 0.1 20µs/DIV 60789 G17 200µs/DIV 60789 G18 VS = 5V VS = 5V 0.01100 1k 10k 100k 1M RCLL == 11000kpF RCLL == 11000kpF FREQUENCY (Hz) 60789 G16 60789fa 7

LTC6078/LTC6079 TYPICAL PERFORW AU CE CHARACTERISTICS Disabled Output Impedence vs Frequency Overshoot vs C Channel Separation vs Frequency L 1000 50 –100 VS = 5V VS = 5V VS = 5V VCM = 0.5V 45 VCM = 0.5V VCM = 0.5V TA = 25°C TA = 25°C –105 RL = 10k Ω) 100 AV = 1 40 dB) UTPUT IMPEDANCE (k 101 OVERSHOOT (%) 3322150505 AV = 1 ANNEL SEPARATION (––––111111220505 O 0.1 10 AV = 10 CH –130 5 0.01 0 –135 100 1k 10k 100k 1M 10M 10 100 1000 100 1k 10k 100k 1M 10M FREQUENCY (Hz) CAPACITIVE LOAD (pF) FREQUENCY (Hz) 60789 G19 60789 G20 60789 G21 PIU FUUCTIOUS OUT: Amplifi er Output ⎯S⎯H⎯D⎯N⎯_⎯A: Shutdown Pin of Amplifi er A, active low and only valid for LTC6078DD. An internal current source pulls the –IN: Inverting Input pin to V+ when fl oating. +IN: Noninverting Input ⎯S⎯H⎯D⎯N⎯_⎯B: Shutdown Pin of Amplifi er B, active low and only V+: Positive Supply valid for LTC6078DD. An internal current source pulls the pin to V+ when fl oating. V–: Negative Supply NC: Not internally connected. Exposed Pad: Connected to V–. 60789fa 8

LTC6078/LTC6079 APPLICATIOUS IUFORWATIOU Preserving Input Precision Capacitive Load Preserving input accuracy of the LTC6078/LTC6079 re- LTC6078/LTC6079 can drive capactive load up to 200pF in quires that the application circuit and PC board layout do unity gain. The capacitive load driving capability increases not introduce errors comparable or greater than the 10µV as the amplifi er is used in higher gain confi gurations. A typical offset of the amplifi ers. Temperature differentials small series resistance between the ouput and the load across the input connections can generate thermocouple further increases the amount of capacitance the amplifi er voltages of 10’s of microvolts so the connections to the can drive. input leads should be short, close together and away from heat dissipating components. Air current across the board ⎯S⎯H⎯D⎯N Pins can also generate temperature differentials. Pins 5 and 6 are used for power shutdown on the LTC6078 The extremely low input bias currents (0.2pA typical) al- in the DD package. If they are fl oating, internal current low high accuracy to be maintained with high impedance sources pull Pins 5 and 6 to V+ and the amplifi ers operate sources and feedback resistors. Leakage currents on the normally. In shutdown, the amplifi er output is high imped- PC board can be higher than the input bias current. For ance, and each amplifi er draws less than 2µA current. example, 10GΩ of leakage between a 5V supply lead and When the chip is turned on, the supply current per amplifi er an input lead will generate 500pA! Surround the input is about 35µA larger than its normal values for 50µs. leads with a guard ring driven to the same potential as the input common mode to avoid excessive leakage in high Rail-to-Rail Input impedance applications. The input stage of LTC6078/LTC6079 combines both PMOS and NMOS differential pairs, extending its input common Input Clamps mode voltage range to both positive and negative supply Large differential voltages across the inputs over very voltages. At high input common mode range, the NMOS long time periods can impact the precisely trimmed input pair is on. At low common mode range, the PMOS pair is offset voltage of the LTC6078/LTC6079. As an example, on. The transition happens when the common voltage is a 2V differential voltage between the inputs over a period between 1.3V and 0.9V below the positive supply. of 100 hours can shift the input offset voltage by tens of microvolts. If the amplifi er is to be subjected to large Thermal Hysteresis differential input voltages, adding back-to-back diodes Figure 2 shows the input offset hysteresis of LTC6078MS8 between the two inputs will minimize this shift and retain for 3 thermal cycles from –45°C to 90°C. The typical offset the DC precision. If necessary, current-limiting series shift after the 3 cycles is only 1µV. resistors can be added in front of the diodes, as shown in Figure 1. These diodes are not necessary for normal 50 closed loop applications. 45 VVSC M= =3 V0.5V 1ST CYCLE 40 S 2ND CYCLE 500Ω + PLIFIER 3350 3RD CYCLE M 500Ω – R OF A 2250 E B 60789 F01 M 15 U N Figure 1. Op Amp with Input Voltage Clamp 10 5 0 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 VOS CHANGE FROM INITIAL VALUE 60789 F02 Figure 2. V Thermal Hysteresis of LTC6078MS8 OS 60789fa 9

LTC6078/LTC6079 APPLICATIOUS IUFORWATIOU PC Board Layout the fourth side. Figure 3 shows the layout of a LTC6078DD with slots at three sides. Mechanical stress on a PC board and soldering-induced stress can cause the V and V drift to shift. The DD OS OS and DHC packages are more sensitive to stress. A simple way to reduce the stress-related shifts is to mount the IC LONG DIMENSION near the short edge of the PC board, or in a corner. The board edge acts as a stress boundary, or a region where the fl exure of the board is minimum. The package should SLOTS always be mounted so that the leads absorb the stress and not the package. The package is generally aligned with the leads paralled to the long side of the PC board. The most effective technique to relieve the PC board stress is to cut slots in the board around the op amp. These slots 60789 F03 can be cut on three sides of the IC and the leads can exit on Figure 3. Vertical Orientation of LTC6078DD with Slots SIW PLIFIED SCHEW ATIC V+ R1 R2 M10 M11 M8 I1 C1 1µA I2 V+ – + A1 V– D4 VBIAS M5 V+ +IN D7 V+ D3 OUTPUT M1 M2 M6 M7 OUT CONTROL V– D6 D8 V+ –IN V– D2 D5 A2 BIAS SHDN GENERATION V– – + C2 D1 NOTE: SHDN IS ONLY AVAILABLE M3 M4 M9 V– IN THE DFN10 PACKAGE R3 R4 V– 60789 SS Simplifi ed Schematic of the Amplifi er 60789fa 10

LTC6078/LTC6079 TYPICAL APPLICATIOUS 2.7V High Side Current Sense VDD VDD R1 + RS 1/2 LTC6078 2N7002 – IL VOUT LOAD R2 R2 R2 VOUT = IL • R1 • RS – VOS • R1 0V ≤ VOUT ≤ VDD – VGS, MOSFET 60789 TA02 Low Average Power IR LED Driver VDD VDD 5V ON/OFF 909k + HSDL-4220 0V 1/2 100k LTC6078 2N7002 – SHDN 49.9Ω VARYING ON DUTY CYCLE REDUCES AVERAGE POWER CONSUMPTION 60789 TA03 Accelerometer Signal Conditioner 2.5V COLUMBIA RESEARCH LABS + 3021 ACCELERATOR 1/2 LTC6078 VOUT – 1M –2.5V VOUT = 60mV/g 1000pF WHERE g = EARTH'S GRAVITATIONAL CONSTANT 60789 TA04 Photodiode Amplifi er 2.5V 1M – 3.8pF TIRE MPHDO10T0O0DIODE LTC16/2078 VOUT + –2.5V AT 870nm (IR), VOUT = 600mV/µW RECEIVED POWER 60789 TA05 60789fa 11

LTC6078/LTC6079 TYPICAL APPLICATIOUS 6 Decade Current Log Amplifi er – C + 100Ω + B 100Ω – 33µF Q1 Q2 100k 133k VDD – 1000pF A – 1.58k + D PRECISION + IIN VOUT RESISTOR PT146 1k VCC LT6650 +3500ppm/°C IN OUT 1µF GND 1µF 10nA ≤ IIN ≤ 10mA 60789 TA07 Q1, Q2: DIODES INC. DMMT3906W A TO D: LTC6079 VOUT ≈ 150mV • log (IIN) + 1.23V, IIN IN AMPS Humidity Sensor Signal Conditioner VSUP IN OUT VDD 5.2V TO 20V 5V 1µF LT1761-5 0.01µF 1µF SHDN BYP VDD VDD 49.9k 100k VBIAS 49.9k 100k M1 GAIN TRIM BAT54S 75pF VDD H 34.8k 1k 100k LTC6906 1000pF – 499k 1k VDD OUT – 100k B – VOUT 0.1µF GRD GND A + C 0V TO 5V VBIAS + 0.1µF + 0% TO 100% RH SET DIV VDD VDD 10k 47.5k 1M A TO C: LTC6079 H: GE PARAMETRICS G-CAP 2 HUMIDITY SENSOR 100k 60789 TA08 148pF TO 178pF, 0% TO 90% RH OFFSET TRIM M1: VN2222L 60789fa 12

LTC6078/LTC6079 TYPICAL APPLICATIOUS LDO Load Balancing VIN IN OUT BALLAST RESISTANCE: 1.8V TO 20V + IDENTICAL LENGTH 10µF LT1763 0.01µF 10µF THERMALLY MATED SHDN BYP WIRE OR PCB TRACE FB R1 R2 2k 2k ⎛ R1⎞ IN OUT VOUT = 1.22V ⎝⎜1 +R2⎠⎟ LT1763 0.01µF 10µF SHDN BYP 100Ω FB ILOAD LOAD 2k 2k 1k 0.1µF – A 10k + IN OUT LT1763 0.01µF 10µF SHDN BYP 100Ω FB 2k 2k 01 .≤22 IVLO ≤A DV O≤U 1T. 5≤A VDD 0.1µF 1k LDO LOADS MATCH TO WITHIN VDD 1mA WITH 10mΩ OF BALLAST – RESISTANCE (2 INCHES OF AWG 28 GAUGE STRANDED WIRE) B A, B: LTC6078 10k + 60789 TA09 pH Probe Amplifi er PRECISION RESISTOR PT146 1k + +3500ppm/°C 1k A pH – VCC – 57.6k B VOUT + LT1634 1000pF 1.25V SENSOR: SENSOREX S200C pH PROBE 60789 TA10 LTC6078 INPUT IMPEDANCE ≈ 1TΩ OR GREATER VOUT = 1.25V + 59.2mV • (pH – 7) A, B: LTC6078 60789fa 13

LTC6078/LTC6079 TYPICAL APPLICATIOUS Thermistor Amplifi er with Overtemperature Alarm VDD – 1k D TOV L1T.2156V34 0.01µF 200k 29.4k 71.5k + + B + 3200Ω – C VOUT + – YSI #44201 THERMOLINEAR A NETWORK 6250Ω – 100k 100k 100k 143k 178k 60789 TA12 H B 20k 50k OFFSET TRIM GAIN TRIM A TO D:LTC6079, VDD = 2.7V TO 5.5V, VSS = GND VOUT = 0 → 1V FOR 0°C TO 100°C, LINEAR TOV → HIGH WHEN T ≥ 90°C Precision Sample-and-Hold LTC6943 VDD 6 9 – – 7 LTC6078 LTC6078 VOUT A B VIN + 1 5 + 4 0.1µF ISUPPLY < 200µA 14 VOLTAGE DROOP = 130nV/ms TYP SLEW RATE = 0.05V/ms TYP S/H ACQ TIME = 84µs TYP TO 0.1% 60789 TA13 60789fa 14

LTC6078/LTC6079 TYPICAL APPLICATIOUS Precision Voltage-Controlled Current Source VDD VIN + 1/2 LTC6078 – IOUT =RVSIENT IERROR < 0.1% AT IOUT = 1µA 0.68µF 1k 6 7 9 1µF 1µF RSET 1k 10 IOUT 11 12 LTC6943 15 14 0.001µF 60789 TA14 60Hz Notch 2.5V R2 – R1 1/2 LTC6078 VOUT 10M 10M + VIN 540pF –2.5V 270pF 270pF ( ) R2 VOUT = 1 +R1 • VIN 5M NOTCH DEPTH = –60dB AT 60Hz, RTI 60789 TA15 60789fa 15

LTC6078/LTC6079 PACKAGE DESCRIPTIOU DD Package 10-Lead Plastic DFN (3mm (cid:215) 3mm) (Reference LTC DWG # 05-08-1699) 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 0.38 ± 0.10 TYP 6 10 3.00 ±0.10 1.65 ± 0.10 (4 SIDES) (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) (DD10) DFN 1103 5 1 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2.DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 60789fa 16

LTC6078/LTC6079 PACKAGE DESCRIPTIOU DHC Package 16-Lead Plastic DFN (5mm (cid:215) 3mm) (Reference LTC DWG # 05-08-1706) 0.65 ±0.05 3.50 ±0.05 1.65 ±0.05 2.20 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 4.40 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 5.00 ±0.10 R = 0.115 0.40 ± 0.10 TYP (2 SIDES) 9 16 R = 0.20 TYP 3.00 ±0.10 1.65 ± 0.10 (2 SIDES) (2 SIDES) PIN 1 PIN 1 TOP MARK NOTCH (SEE NOTE 6) (DHC16) DFN 1103 8 1 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 BSC 4.40 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 60789fa 17

LTC6078/LTC6079 PACKAGE DESCRIPTIOU MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 0.889 ± 0.127 (.035 ± .005) 5.23 3.20 – 3.45 (.206) (.126 – .136) MIN 3.00 ± 0.102 0.42 ± 0.038 0.65 (.118 ± .004) 0.52 (.0165 ± .0015) (.0256) (NOTE 3) 8 7 6 5 (.0205) TYP BSC REF RECOMMENDED SOLDER PAD LAYOUT 4.90 ± 0.152 3.00 ± 0.102 0.254 DETAIL “A” (.193 ± .006) (.118 ± .004) (NOTE 4) (.010) 0° – 6° TYP GAUGE PLANE 1 2 3 4 0.53 ± 0.152 (.021 ± .006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING PLANE 0.22 – 0.38 0.127 ± 0.076 (.009 – .015) (.005 ± .003) TYP 0.65 MSOP (MS8) 0204 (.0256) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 60789fa 18

LTC6078/LTC6079 PACKAGE DESCRIPTIOU GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 ±.005 .189 – .196* (4.801 – 4.978) .009 (0.229) 16 15 14 13 12 11 109 REF .254 MIN .150 – .165 .229 – .244 .150 – .157** (5.817 – 6.198) (3.810 – 3.988) .0165 ±.0015 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 .015 ± .004 × 45° .0532 – .0688 .004 – .0098 (0.38 ± 0.10) (1.35 – 1.75) (0.102 – 0.249) .007 – .0098 0° – 8° TYP (0.178 – 0.249) .016 – .050 .008 – .012 .0250 GN16 (SSOP) 0204 (0.406 – 1.270) (0.203 – 0.305) (0.635) NOTE: TYP BSC 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 60789fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 19 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC6078/LTC6079 TYPICAL APPLICATIOU DC Accurate Composite Amplifi er, Gain of 1000 VCC VIN + LT1226 VOUT – 1M VDD 0.1µF – VEE 10k 100Ω 1/2 VCC LTC6078 + 10Ω 10k 2.49k VDD VSS LT1634BCS8-5 10Ω VSS CIRCUIT BW ≈ 1.25MHz 2.49k en = 2.6nV/√Hz (RTI) AT 1kHz CIRCUIT VOS = 25µV (MAX) RTI VEE 60789 TA06 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2051/LTC2052 Dual/Quad Zero-Drift Op Amps 3µV V , 30nV/°C V Drift OS OS LT6011/LT6012 Dual/Quad Precision Op Amps 60µV V , I = 300pA, I = 135µA OS B S 60789fa 20 Linear Technology Corporation LT 0506 REV A (cid:149) PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com ' LINEAR TECHNOLOGY CORPORATION 2005

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