LTC4417 Prioritized PowerPath™ Controller FeaTures DescripTion n Selects Highest Priority Supply from Three Inputs The LTC®4417 connects one of three valid power supplies n Blocks Reverse and Cross Conduction Currents to a common output based on priority. Priority is defined n Wide Operating Voltage Range: 2.5V to 36V by pin assignment, with V1 assigned the highest priority n –42V Protection Against Reverse Battery and V3 the lowest priority. A power supply is defined as Connection valid when its voltage has been within its overvoltage (OV) n Fast Switchover Minimizes Output Voltage Droop and undervoltage (UV) window continuously for at least n Low 28µA Operating Current 256ms. If the highest priority valid input falls out of the n <1µA Current Draw from Supplies Less than V OV/UV window, the channel is immediately disconnected OUT n 1.5% Input Overvoltage/Undervoltage Protection and the next highest priority valid input is connected to the n Adjustable Overvoltage/Undervoltage Hysteresis common output. Two or more LTC4417s can be cascaded n P-Channel MOSFET Gate Protection Clamp to provide switchover between more than three inputs. n Cascadable for Additional Input Supplies The LTC4417 incorporates fast non-overlap switching n 24-Lead Narrow SSOP and 4mm × 4mm QFN circuitry to prevent both reverse and cross conduction Packages while minimizing output droop. The gate driver includes applicaTions a 6V clamp to protect external MOSFETs. A controlled output ramp feature minimizes start-up inrush current. n Industrial Handheld Instruments Open drain VALID outputs indicate the input supplies have n High Availability Systems been within their OV/UV window for 256ms. n Battery Backup Systems L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and n Servers and Computer Peripherals PowerPath, ThinSOT and Hot Swap are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion V1: 12V IRF7324 WALL ADAPTER 2A OUTPUT V2: 14.8V Li-Ion MAIN/SWAPPABLE IRF7324 Priority Switching from 12V V1 to 14.8V V2 V3: 12V SLA BACKUP IRF7324 1144..88VV V2 V1 VS1 G1 VS2 G2 VS3 G3 12V VOUT 806k VOUT V1 UV1 1M 1M 1M 2V/DIV 39.2k VALID1 OV1 VALID2 60.4k VALID3 V1 UV FAULT V2 1.05M V3 = 0V, IL = 2A CL = 120µF UV2 LTC4417 31.6k 50ms/DIV 4417 TA01b OV2 68.1k V3 EN 698k SHDN UV3 HYS CAS 16.9k OV3 GND 4417 TA01a 49.9k 4417f 1

LTC4417 absoluTe MaxiMuM raTings (Notes 1, 2) Supply Voltages Output Voltages V1, V2, V3 ...............................................–42V to 42V VALID1, VALID2, VALID3 ........................–0.3V to 42V V , VS1, VS2, VS3 ..............................–0.3V to 42V CAS ..........................................................–0.3V to 6V OUT Voltage from V1, V2, V3 to V .................–84V to 42V Output Currents OUT Voltage from VS1, VS2, VS3 to VALID1, VALID2, VALID3, CAS .............................2mA G1, G2, G3 ..................................................–0.3V to 7.5V Operating Ambient Temperature Range Input Voltages LTC4417C ................................................0°C to 70°C EN, SHDN ..............................................–0.3V to 42V LTC4417I..............................................–40°C to 85°C OV1, OV2, OV3, UV1, UV2, UV3 ...............–0.3V to 6V LTC4417H ..........................................–40°C to 125°C HYS .........................................................–0.3V to 1V Storage Temperature Range ..................–65°C to 150°C Input Currents Lead Temperature OV1, OV2, OV3, UV1, UV2, UV3, HYS ...............–3mA GN Package (Soldering, 10 sec) ........................300°C pin conFiguraTion TOP VIEW N EN 1 24 V1 YS HD N 1 2 3 H S E V V V SHDN 2 23 V2 24 23 22 21 20 19 HYS 3 22 V3 UV1 1 18 VS1 UV1 4 21 VS1 OV1 2 17 G1 OV1 5 20 G1 UV2 3 16 VS2 25 UV2 6 19 VS2 OV2 4 15 G2 OV2 7 18 G2 UV3 5 14 VS3 UV3 8 17 VS3 OV3 6 13 G3 OV3 9 16 G3 7 8 9 10 11 12 VVAALLIIDD12 1101 1154 CVOAUST ALID1 ALID2 ALID3 GND CAS VOUT V V V VALID3 12 13 GND UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN GN PACKAGE TJMAX = 150°C, θJA = 47°C/W, θJC = 4.5°C/W 24-LEAD NARROW PLASTIC SSOP EXPOSED PAD (PIN 25) PCB GND CONNECTION OPTIONAL TJMAX = 150°C, θJA = 85°C/W, θJC = 30°C/W orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4417CGN#PBF LTC4417CGN#TRPBF LTC4417GN 24-Lead Narrow Plastic SSOP 0°C to 70°C LTC4417IGN#PBF LTC4417IGN#TRPBF LTC4417GN 24-Lead Narrow Plastic SSOP –40°C to 85°C LTC4417HGN#PBF LTC4417HGN#TRPBF LTC4417GN 24-Lead Narrow Plastic SSOP –40°C to 125°C LTC4417CUF#PBF LTC4417CUF#TRPBF 4417 24-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C LTC4417IUF#PBF LTC4417IUF#TRPBF 4417 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C LTC4417HUF#PBF LTC4417HUF#TRPBF 4417 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4417f 2

LTC4417 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. For all tests, V1 = VS1, V2 = VS2, V3 = VS3. Unless otherwise noted, A V1 = V2 = V3 = V = 12V, HYS = GND. OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Start-Up V1-V3,V V1 to V3,V Operating Supply Range l 2.5 36 V OUT OUT I Total Supply Current with Channels Enabled V1 = 5V, V2 = 12V, V3 = 2.5V, V = 4V, l 28 78 µA V1-V3,VOUT(EN) OUT (Notes 3, 4) I Total Supply Current with Channels Disabled V1 = 5V, V2 = 12V, V3 = 2.5V, V = EN = 0V, l 31 93 µA V1-V3(EN) OUT (Notes 3, 4) I Total Supply Current When Shutdown V1 = 5V, V2 = 12V, V3 = 2.5V, V = SHDN = l 15.4 84 µA V1-V3(SHDN) OUT 0V, (Notes 3, 4) I V Supply Current V1 = 5V, V2 = 12V, V3 = 2.5V, V = 4V l 14 30 µA VOUT OUT OUT I Current from Highest V1 to V3 Priority Input V1 = 5V, V2 = 12V, V3 = 2.5V, V = 4V l 2.6 6 µA PRIORITY OUT Source (V1) V1 = 5V, V2 = 12V, V3 = 2.5V, V = EN = 0V l 20 45 µA OUT I Current from Highest V1 to V3 Voltage Input V1 = 5V, V2 = 12V, V3 = 2.5V, V = 4V, l 11 72 µA HIGHEST OUT Source (Note 3, 4) V1 = 5V, V2 = 12V, V3 = 2.5V, V = EN = 0V, l 15 80 µA OUT SHDN = 0V, (Note 3, 4) I Current from V1 to V3 Input Voltage Sources V1 = 5V, V2 = 12V, V3 = 2.5V, V = 4V –5 0.2 1 µA LOWER OUT Lower than V Not Highest Valid Priority OUT Gate Control ∆V Open (VS – VG) Clamp Voltage V = 11V, G1 to G3 = Open l 5.4 6.2 6.7 V G OUT ∆V Sourcing (VS – VG) Clamp Voltage V = 11V, I = –10µA l 5.8 6.6 7 V G(SOURCE) OUT ∆V Sinking (VS – VG) Clamp Voltage V = 11V, I = 10µA l 4.5 5.2 6 V G(SINK) OUT ∆V G1 to G3 Off (VS – VG) Threshold V1 = V2 = V3 = 2.8V, V = 2.6V, G1 to G3 l 0.12 0.35 0.6 V G(OFF) OUT Rising Edge ∆V G1 to G3 Pull-Down Slew Rate V = 11V, C = 10nF (Note 5) l 4 9 20 V/µs G(SLEW,ON) OUT GATE ∆V G1 to G3 Pull-Up Slew Rate V = 11V, C = 10nF (Note 6) l 7.5 13 22 V/µs G(SLEW,OFF) OUT GATE I G1 to G3 Low Pull-Down Current V = 2.6V, V1 to V3 = 2.8V, (G1 to G3) = ∆V 0.8 2 7 µA G(DN) OUT G + 300mV R G1 to G3 OFF Resistance V = 4V, V1 to V3 = 5V, I = –10mA l 9 16 26 Ω G(OFF) OUT G V Reverse Voltage Threshold Measure (V1 to V3) – V , V Falling l 30 120 200 mV REV OUT OUT t Pin Break-Before-Make Time V = 11V, C = 10nF, (Note 7) l 0.7 2 3 µs G(SWITCHOVER) OUT GATE t G1 to G3 Turn-Off Delay From SHDN V = 11V, Falling Edge SHDN to l 20 50 100 µs pG(SHDN) OUT (G1 to G3) = (VS1 to VS3) – 3V, C = 10nF GATE t G1 to G3 Turn-Off Delay From EN V = 11V, Falling EN Edge to l 0.3 0.7 1.4 µs pG(EN,OFF) OUT (G1 to G3) = (VS1 to VS3) – 3V, C = 10nF GATE t G1 to G3 Turn-On Delay From EN V = 11V, Rising EN Edge to l 1 1.4 2 µs pG(EN,ON) OUT (G1 to G3) = (VS1 to VS3) – 3V, C = 10nF GATE 4417f 3

LTC4417 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. For all tests, V1 = VS1, V2 = VS2, V3 = VS3. Unless otherwise noted, A V1 = V2 = V3 = V = 12V, HYS = GND. OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input/Output Pins V VALID1 to VALID3 Output Low Voltage I = 1mA, (V1 to V3) = 2.5V, V = 0V l 0.25 0.55 V VALID(OL) OUT t VALID1 to VALID3 Delay OFF From OV/UV Fault l 5 8 13 µs pVALID(OFF) V CAS Output High Voltage I = –1µA l 1.4 2 3 V CAS(OH) V CAS Output Low Voltage I = 1mA l 0.2 0.4 V CAS(OL) I CAS Pull-Up Current SHDN = 0V, CAS = 1V l –6 –20 –40 µA CAS t CAS Delay from V V = 11V l 0.4 0.7 1.3 µs pCAS(EN) G(OFF) OUT V EN Threshold Voltage EN Rising l 0.6 1 1.4 V EN(THR) V SHDN Threshold Voltage SHDN Rising l 0.4 0.8 1.2 V SHDN(THR) V SHDN, EN Threshold Hysteresis 100 mV SHDN_EN(HYS) I SHDN, EN Pull-Up Current SHDN = EN = 0V l –0.5 –2 –5 µA SHDN_EN I SHDN, EN, VALID1 to VALID3, CAS Leakage SHDN = EN = (VALID1 to VALID3) = 36V, l ±1 µA LEAK Current CAS = 5.5V OV, UV Protection Circuitry V OV1 to OV3, UV1 to UV3 Comparator Threshold V = 11V, OV1 to OV3 Rising, UV1 to UV3 l 0.985 1 1.015 V OV_UV(THR) OUT Falling V OV1 to OV3, UV1 to UV3 Comparator V = 11V l 15 30 45 mV OV_UV(HYS) OUT Hysteresis I OV1 to OV3, UV1 to UV3 Leakage Current OV1 to OV3 = 1.015V, UV1 to UV3 = 0.985V l ±20 nA UV_OV(LEAK) I Minimum External Hysteresis Current I = –400nA l 35 50 75 nA OV_UV(MIN) HYS I Maximum External Hysteresis Current I = –4µA l 420 520 620 nA OV_UV(MAX) HYS V HYS Voltage I = –4µA l 470 495 520 mV HYS HYS t V1 to V3 Validation Time 100 256 412 ms VALID Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: Specification represents the total diode-ORed current of V1 to V3 may cause permanent damage to the device. Exposure to any Absolute input supplies, selecting the highest voltage as the input source. If two Maximum Rating condition for extended periods may affect device input supplies are similar in voltage and higher than the remaining input reliability and lifetime. supply voltage, the current is split evenly between the two higher voltage Note 2: All currents into device pins are positive; all currents out of device supplies. Current is split evenly if all supplies are equal. pins are negative. All voltages are referenced to GND unless otherwise Note 5: Falling edge of G1 to G3 measured from 11V to 8V. specified. Note 6: Rising edge of G1 to G3 measured from 7V to 11V. Note 3: Each V1 to V3 supply current specification includes current into Note 7: UV1 driven below V . Time is measured from respective OV,UV(THR) the corresponding VS1 to VS3 for the channel(s) being tested. rising edge G1 to G3 crossing (VS1 to VS3) – 3V to next valid priority falling edge G1 to G3 crossing (VS1 to VS3) – 3V. 4417f 4

LTC4417 Typical perForMance characTerisTics Total Shutdown Supply Current Total Enabled Supply Current vs Supply Voltage vs Supply Voltage I vs Supply Voltage V1-V3,VOUT(EN) 25 40 16 N SUPPLY CURRENT (µA) 2105 SUPPLY CURRENT (µA) 32325500 (µA)VOUT(EN) 1114028 VOUT = 4.9VV2 = VS2 SHUTDOW 105 L ENABLE 1105 IV1-V3, 46 V1 = VS1 = 5V TOTAL ATOLLG ESTUHPEPRLY, V AONUDT =V S0 VPINS CONNECTED TOTA 5 APLINLS S CUOPNPNLYE, CVTSE DAN TDO GVEOTUHTER 2 V3 = VS3 = 2.8V 0 0 0 0 10 20 30 40 0 10 20 30 40 0 10 20 30 40 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) V2 = VS2 VOLTAGE (V) 4417 G01 4417 G02 4417 G03 Gate Falling Slew Rate Gate Rising Slew Rate ΔV vs Temperature vs Temperature vs Temperature G 6.40 16 16 CGATE = 10nF V1 = 12V, 24V, 36V 6.35 14 V1 = 36V V1 = V2 = V3 ∆V (V)G 66666.....2321150005 GATE FALLING SLEW RATE (V/µs) 1102846 V1 = 5VV1 = 12V V1 = 24V GATE RISING SLEW RATE (V/µs) 1248 VV11 == 25.V7V 6.05 2 V1 = V2 = V3 V1 = 2.7V CGATE = 10nF 6.00 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4417 G04 4417 G05 4417 G06 Valid Delay Off Time I vs Temperature Switchover Time vs Temperature vs Temperature G(DN) 3.0 3.0 8.5 8.4 2.5 2.5 I (µA)G(DN) 121...500 (µs)G(SWITCHOVER) 121...500 LID DELAY TIME (µs) 8888....2310 t A V 7.9 0.5 0.5 7.8 0 0 7.7 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4417 G07 4417 G08 4417 G09 4417f 5

LTC4417 Typical perForMance characTerisTics V vs Pull-Up Current V vs Temperature Deglitched Connection VALID(OL) OV,UV 0.5 1.04 1.03 V2 0.4 VUV(RISING) 1.02 VOUT 2V/DIV V (V)VALID(OL) 00..23 V (V)OV,UV110...009109 VOV,UV(THR) V1 100ms/DIV 4417 G12 0.98 0.1 0.97 VOV(FALLING) ICLL = = 1 1A22µF –40V PCH FDD4685 0 0.96 0 0.5 1.0 1.5 2.0 –50 –25 0 25 50 75 100 125 PULL-UP CURRENT (mA) TEMPERATURE (°C) 4417 G10 4417 G11 V Switching from Lower to OUT V Switching from Higher to Higher Voltage with Slew Rate OUT Lower Voltage Control Circuitry Reverse Voltage Blocking V2 V2, VOUT V2 2V/DIV 10V/DIV VOUT VOUT V1 V1 = 20V 2V/DIV 2V/DIV V1 IVOUT 5A/DIV V1 = –20V 100µs/DIV 4417 G13 20µs/DIV 4417 G14 5µs/DIV 4417 G15 CL = 122µF RS = 1.43kΩ CL = 122µF IL = 1A CS = 6.8nF IL = 1A –40V PCH FDD4685 CL = 100µF –40V PCH FDD4685 IL = 1A –40V PCH FDD4685 pin FuncTions CAS: Cascade Output. Digital output used for cascad- EN: Channel Enable Input. EN is a high voltage input that ing multiple LTC4417s. Connect CAS to EN of another allows the user to quickly connect and disconnect chan- LTC4417 to increase the number of multiplexed input nels without resetting the OV/UV timers. When below 1V, supplies. CAS is pulled up to the internal V voltage all external back-to-back P-channel MOSFETs are driven LDO by an internal 20µA current source to indicate when all off by pulling G1, G2 and G3 to their respective VS1, VS2 inputs are invalid, the external P-channel MOSFETs are and VS3. When above 1V, the highest valid priority chan- determined to be off, and EN is above 1V. CAS also pulls nel is connected to the output. EN is pulled to the internal high when SHDN is driven below 1V. CAS is pulled low V voltage with a 2µA current source and can be pulled LDO when any input supply is within the OV/UV window for at up externally to a maximum voltage of 36V. Leave open least 256ms and both SHDN and EN are above 1V. CAS when not used. also pulls low when EN is driven below 1V. CAS can be Exposed Pad (UF Package Only): Exposed pad may be driven to 5.5V independent of the input supply voltages. left open or connected to device ground. Leave open if not used. 4417f 6

LTC4417 pin FuncTions G1, G2, G3: P-Channel MOSFET Gate Drive Outputs. G1, V1: Highest Priority Input Supply. When V1 is within its user G2 and G3 are used to control external back-to-back P- defined OV/UV window for 256ms, it is connected to V OUT channel MOSFETs. When driven low, G1, G2 and G3 are via its external back-to-back P-channel MOSFETs. Connect clamped 6V below their corresponding VS1, VS2 and VS3. V1 to ground when channel is not used. See Applications Connect G1, G2 and G3 to external P-channel MOSFET Information for bypass capacitor recommendations. gate pins. See Dual Channel Applications Section for con- V2: Second Priority Input Supply. When V2 is within its necting unused channels. OV/UV window for 256ms, it is connected to V via OUT GND: Device Ground. its external back-to-back P-channel MOSFETs only if V1 does not meet its OV/UV requirements. Connect to ground HYS: OV/UV Comparator Hysteresis Input. Connecting HYS when channel is not used. See Applications Information to ground sets a fixed 30mV hysteresis for the OV and UV for bypass capacitor recommendations. comparators. Connecting a resistor, R , between HYS HYS and ground disables the internal 30mV hysteresis and sets V3: Third Priority Input Supply. When V3 is within its OV/UV a 63mV/R hysteresis current which is sourced from window for 256ms, it is connected to V via its external HYS OUT each OV1, OV2 and OV3 and sunk into each UV1, UV2 and back-to-back P-channel MOSFETs only if V1 and V2 do UV3 pin. Connect to ground when not used. not meet their OV/UV requirements. Connect to ground when channel is not used. See Applications Information OV1, OV2, OV3: Overvoltage Comparator Inputs. Rising for bypass capacitor recommendations. voltages above 1V signal an over voltage event, invalidating the respective input supply channel. Connect OV1, OV2 and VALID1, VALID2, VALID3: Valid Channel Indicator Outputs. OV3 to an external resistive divider from its respective V1, VALID1, VALID2 and VALID3 are high voltage open drain V2 and V3 to achieve the desired overvoltage threshold. outputs that pull low when the respective V1, V2 and V3 are The comparator hysteresis can be set to an internally fixed within the OV/UV window for at least 256ms and release 30mV or set externally via the HYS pin. Connect unused when the respective V1, V2 and V3 are outside the OV/ pins to ground. UV window. Connect a resistor between VALID1, VALID2 and VALID3 and a desired supply, up to a maximum of SHDN: Shutdown Input. Driving SHDN below 0.8V turns 36V, to provide the pull-up. Leave open when not used. off all external back-to-back P-channel MOSFET devices, forces the LTC4417 into a low current state, and resets VS1, VS2, VS3: External P-Channel MOSFET Common the 256ms timers used to validate V1, V2 and V3. Driving Source Connection. VS1, VS2 and VS3 supply the higher SHDN above 0.8V allows channels to validate and connect. voltage of V1, V2 and V3 or V to the gate drivers. OUT SHDN is pulled high to the internal V voltage with a Connect VS1, VS2 and VS3 to the respective common LDO 2µA current source and can be pulled up externally to a source connection of the back-to-back P-channel MOS- maximum voltage of 36V. Leave open when not used. FETs. Connect to ground when channel is not used. See Applications Information section for bypass capacitor UV1, UV2, UV3: Undervoltage Comparator Inputs. Falling recommendations. voltages below 1V signal an undervoltage event, invalidat- ing the respective input supply channel. Connect UV1, UV2 V : Output Voltage Supply and Sense. V is an output OUT OUT and UV3 through a resistive divider between the respec- voltage sense pin used to prevent any input supply from tive V1, V2 and V3 and ground to achieve the desired connecting to the output if the output voltage is not at undervoltage threshold. The comparator hysteresis can least 120mV below the input supply voltage. During nor- be set to an internally fixed 30mV or set externally via the mal operation, V powers most of the internal circuitry OUT HYS pin. Connect pins from unused channels to ground. when its voltage exceeds 2.4V. Connect V to the output. OUT See Applications Information section for bypass capacitor recommendations. 4417f 7

LTC4417 FuncTional block DiagraM VLDO ISHDN V1V2V3 VOUT 2µA VLDO SHDN D2 + VBESTGEN P1 LDO VBLDO SHDN 1V – V1 P2 + VLDOIEN VBLDO VV23 PP43 PRIOLRDIOTIZER RITY VOUT – 2.4V 2µA VLDO VBEST P5 PRIO EN D3 + EN BAUNVDLGOAP VLDO VALID VLDO VLDO 1V – SHDN HEST I2C0AµSA G ILIM HI VLDO 5µA M2 CURRENT SENSE/8 VLDO D1 + HYS VLDO CAS 0.24V – + 0.5V M3 M4 OT–A 30mV GND PRIORITIZED HYS IHYS/8 EXTERNAL NONOVERLAP HYS CONTROL LOGIC HYSTERESIS VS1 120mV VLDO – +– UV1 + V1 + REV UV2 1V – UV CH1 V2 UV3 VLDO + 256ms VALID V3 TIMER VS1 1V + OV1 – VS1 – OV2 OV VGS + +– DZ1 VS2 OV3 350mV 6.2V VS3 G1 VALID1 VALID2 M1 GATE G2 DRIVER VALID3 G3 CHANNEL 1 CHANNEL 2 CHANNEL 3 4417 BD 4417f 8

LTC4417 TiMing DiagraM G2 G1 VALID2 VALID1 UV2 UV1 EN SHDN 4417 TD tVALID tpVALID(OFF) tG(SWITCHOVER) tpG(EN,OFF) tpG(EN,ON) tpG(SHDN) 4417f 9

LTC4417 operaTion The Functional Block Diagram displays the main functional by the reverse current blocking threshold of 120mV. The blocks of this device. The LTC4417 connects one of three output of the REV comparator is latched, resetting when power supplies to a common output, V , based on user its respective channel is turned off. OUT defined priority. Connection is made by enhancing external The LTC4417 gate driver pulls down on G1, G2 and back-to-back P-channel MOSFETs. Unlike a diode-OR, G3 with a strong P-channel source follower and a 2µA which always passes the highest supply voltage to the current source. When the clamp voltage is reached, the output, the LTC4417 lets one use a lower voltage supply P-channel source follower is back biased, leaving the for primary power and a higher voltage supply as second- 2µA current source to hold G1, G2 and G3 at the clamp ary or backup power. voltage. To minimize inrush current at start-up, the gate During normal operation the LTC4417 continuously moni- driver soft-starts the first input supply to connect V , OUT tors V1, V2 and V3 through its respective OV1, OV2 and OV3 at a rate of around 5V/ms terminating when any channel and UV1, UV2 and UV3 pins using precision overvoltage disconnects or 32ms has elapsed. Once slew rate control and undervoltage comparators. The highest priority input has terminated, the gate driver quickly turns on and off supply whose voltage is within its respective OV/UV window external back-to-back P-channel MOSFETs as needed. A for at least 256ms is considered valid and is connected to SHDN low to high transition or V drooping below 0.7V OUT V through external back-to-back P-channel MOSFETs. reactivates soft-start. OUT VALID1, VALID2 and VALID3 pull low to indicate when the When EN is driven above 1V the highest valid priority V1, V2 and V3 input supplies are valid. input supply is connected to V . The high voltage EN OUT Hysteresis on the OV and UV threshold is adjustable. comparator disconnects all channels when EN is driven Connecting a resistor, R , between HYS and ground below 1V. The LTC4417 continues to monitor the OV and HYS forces 63mV/R current to flow out of OV1, OV2 and UV pins and reflects the current input supply status with HYS OV3 and into UV1, UV2 and UV3 to create hysteresis when VALID1, VALID2 and VALID3. When four or more sup- outside their respective OV/UV windows. Connecting HYS plies need to be prioritized, connect the higher priority to ground sets the OV and UV comparator hysteresis to LTC4417’s CAS to the lower priority LTC4417’s EN. If 30mV. See the Application Information for more details. V is allowed to fall below 0.7V, the next connecting OUT input supply is soft-started. During channel transitions, monitoring circuitry prevents cross conduction between input channels and reverse con- The high voltage SHDN comparator forces the LTC4417 into duction from V using a break-before-make architecture. a low current state when SHDN is forced below 0.8V. While OUT The VGS comparator monitors the disconnecting channel’s in the low current state, all channels are disconnected, OV gate pin voltage (G1, G2 or G3). When the gate voltage is and UV comparators are disabled, and all 256ms timers 350mV from its common source connection (VS1, VS2 or are reset. When SHDN transitions from low to high, the VS3), the VGS comparator latches the output to indicate first validated input to connect to V is soft-started. OUT the channel is off and allows the next valid priority input Two separate internal power rails ensure the LTC4417 is supply to connect to V , preventing cross conduction OUT functional when one or more input supply is present and between channels. The latch is reset when the channel is above 2.3V. V generates a VB rail from the BESTGEN LDO turned on. highest V1, V2 and V3 and V voltage. VB powers OUT LDO To prevent reverse conduction from V to V1, V2 and V3 the UVLO, bandgap, and V comparator. The internal OUT OUT during channel switchover, the REV comparator monitors V powers all other circuits from V provided V is LDO OUT OUT the connecting input supply (V1, V2 or V3) and output greater than 2.4V. If V is less than 2.3V, V powers OUT LDO voltage (V ). The REV comparator delays the connection all other circuits from the highest priority supply available. OUT until the output voltage droops lower than the input voltage If all sources are invalid or the LTC4417 is shut down, V connects to VB . LDO LDO 4417f 10

LTC4417 applicaTions inForMaTion INTRODUCTION highest valid priority is connected to the common output. If a lower priority input supply is connected to V and a The LTC4417 is an intelligent high voltage triple load switch OUT higher priority input supply becomes valid, the LTC4417 which automatically connects one of three input supplies disconnects the lower priority supply and connects the to a common output based on predefined pin priorities higher priority input supply to V . and validity. V1 is defined to be the highest priority and OUT V3 the lowest priority, regardless of voltage. An input Typical LTC4417 applications are systems where predict- supply is defined valid when the voltage remains in the able autonomous load control of multiple input supplies is user defined overvoltage (OV) and undervoltage (UV) desired. These supplies may not necessarily be different window for at least 256ms. in voltage, nor must the highest voltage be the primary supply. A typical LTC4417 application circuit is shown in If a connected input supply falls out of the user defined Figure 1. External component selection is discussed in OV/UV window and remains outside the OV/UV window detail in the following sections. for at least 8µs, the channel is disconnected and the next 12V WALL IRF7324 ADAPTER M1 M2 VOUT + + CIN1 CL 2200µF 100µF 7.4V Li-Ion PRIMARY IRF7324 BATTERY M3 M4 + 7.4V Li-Ion SECONDARY IRF7324 BATTERY M5 M6 + LTC3690 SWITCHING REGULATOR CVS1 CVS2 CVS3 0.1µF 0.1µF 0.1µF 3.3V CV3 CV2 CV1 VS1 G1 VS2 G2 VS3 G3 R10 R11 R12 4A 0.1µF 0.1µF 0.1µF V1 VOUT 1M 1M 1M R3 806k ADAPTER UV1 INVALID R2 VALID1 39.2k PRIMARY INVALID OV1 VALID2 SECONDARY INVALID R1 VALID3 60.4k V2 R6 931k LTC4417 UV2 R5 63.4k OV2 R4 137k V3 EN R9 SHDN 931k UV3 HYS R8 CAS 63.4k OV3 GND R7 4417 F01 137k Figure 1. Typical Hand Held Computer Application. 4417f 11

LTC4417 applicaTions inForMaTion DEFINING OPERATIONAL RANGE V1 INPUT SUPPLY To guard against noise and transient voltage events during V1 + UV LTC4417 VOUT R10 R7 R3 UV1 live insertion, the LTC4417 requires an input supply remain R12 UV1 UV1 UV1 1V – VALID VALID1 RP in the OV/UV window for at least 256ms to be valid. The R6 IHYS/8 OV/UV window for each input supply is set by a resistive R9 R11 R5 divider (for example, R1, R2 and R3 for V1 input supply) OV1 OV1 256ms connected from the input supply to GND, as shown in R8 R4 R2 VLDO TIMER M1 Figure 1. When setting the resistive divider values for the T-RESISTIVE DUAL- OV and UV input supply threshold, take into consideration CONNECTION CROENSNIESCTTIVIOEN IHYS/8 HYS IHYS OV1 the tolerance of the input supply, 1.5% error in the OV OPTIONHAYLS TINERDEESPIESNDENT R1 1V + OV OV1 R12H4YkS and UV comparators, tolerance of R1, R2 and R3, and the GND – VALID TO 1.24M ±20nA maximum OV/UV pin leakage currents. 4417 F03 Figure 3. LTC4417 External Hysteresis In addition to tolerance considerations, hysteresis reduces the valid input supply operating range. Input supplies will Independent OV and UV hysteresis values are available need to be within the reduced input supply operating range by separating the single string resistive dividers R1, R2 to validate. Referring to Figure 2, V1 supply voltage must and R3, shown in Figure 3, into two resistive strings, R4- be greater than UV to exit the UV fault. If an OV fault R5 and R6-R7. In such a configuration, the top resistor HYS occurs, the V1 supply voltage must return to a voltage defines the amount of hysteresis and the bottom resistor lower than the OV voltage to exit the OV fault. defines the threshold. Use Equations (2) and (3) to cal- HYS culate the values. OV HYST OVHYS RTOP = (2) I ROEPDERUACTEIDNG OWVIN/UDVOW OVUV(HYS) WINDOW UVHYS where HYST is the desired hysteresis voltage at V1. UV V1 R UV1 FAULT R = TOP (3) BOTTOM (OV/UVThreshold)–1 OV1 FAULT V1 VALID 4417 F02 When large independent hysteresis voltages are required, Figure 2. OV and UV Thresholds and Hysteresis Voltage a resistive T structure can be used to define hysteresis values, also shown in Figure 3. After the desired OV and Hysteresis for the OV and UV comparators are set via the UV thresholds are set with resistors R8 through R10, R11 HYS pin. Two options are available. Connecting a resistor, and R12 are calculated using: R , between HYS and GND, as shown in Figure 3, sets HYS the hysteresis current IOV_UV(HYS) that is sunk into UV1, R8•⎡⎣OVHYS –IOVUV(HYS)•(R9+R10)⎤⎦ UV2 and UV3 and sourced out of OV1, OV2 and OV3. The R11= (4) I •(R8+R9+R10) value of RHYS is calculated with Equation (1). Choose RHYS OVUV(HYS) to limit the hysteresis current to between 50nA and 500nA. (R8+R9)•⎡UV –I •R10⎤ 63mV R12= ⎣ HYS OVUV(HYS) ⎦ (5) R = (1) HYS I •(R8+R9+R10) IOVUV(HYS) OVUV(HYS) where OV , UV are the desired OV and UV hysteresis where 50nA ≤ I ≤ 500nA HYS HYS OVUV(HYS) voltage magnitudes at V1 through V3, and I is OVUV(HYS) the programmed hysteresis current. 4417f 12

LTC4417 applicaTions inForMaTion Reduction of the valid operating range can be used to FILTERING NOISE ON OV AND UV PINS prevent disconnected high impedance input supplies The LTC4417 provides an 8µs OV/UV fault filter time. If from reconnecting. For example, if 3 series connected AA the 8µs filter time is not sufficient, add a filter capacitor Alkaline batteries with a total series resistance of 675mΩ between the OV or UV pin and GND to extend the fault is used to source 500mA, the voltage drop due to the se- filter time and ride through transient events. A UV pin fault ries resistance would be 337.5mV. Once the batteries are filter time extension capacitor, C , is shown in Figure 5. UVF discharged and are disconnected due to a UV fault, the AA battery stack would recover the 337.5mV drop across the Use Equation (6) to select CUVF for the UV pin and Equa- internal series resistance. Using the 30mV fixed internal tion (7) to select COVF for the OV pin. hysteresis allows only 81mV of hysteresis at the input R1+R2+R3 ⎡V –V ⎤ pin, possibly allowing the input supply to revalidate and C =t • •ln⎢ i f ⎥ (6) UVF DELAY reconnect. Using external hysteresis, the hysteresis volt- R3•(R1+R2) ⎣1V–Vf⎦ age can be increased to 400mV, reducing or eliminating R1+R2+R3 ⎡V –V ⎤ the reconnection issue, as shown in Figure 4. C =t • •ln⎢ i f ⎥ (7) OVF DELAY R1•(R2+R3) ⎣1V–V ⎦ f FULLY CHARGED 3 × AA BATTERY V1 337.5mV RECOVERY VALID UV where the final input voltage V and the initial voltage V WHEN LOAD IS RANGE f i DISCONNECTED FOR 400mV are the resistively divided down values of the input supply 400mV HYSTERESIS HYSTERESIS VALID UV step, as shown in Figure 6. RANGE FOR 81mV 81mV HYSTERESIS 2.7V UV THRESHOLD HYSTERESIS VIN(INIT) V1 UV FAULT AND 4417 F06 INPUT SUPPLY STEP DISCONNECTS VIN(FINAL) Figure 4. Setting a Higher UV Hysteresis to Prevent Unwanted Reconnections Vi=VINR(IN1I+T)R•2(R+1R+3R2) WTIITMHE F EAXUTLETN FSILIOTENR Connecting HYS to GND, as shown in Figure 5, selects WITHOUT FAULT FILTER an internal 30mV fixed hysteresis, resulting in 3% of the TIME EXTENSION input supply voltage. 1V VOVUV(THR) V1 INPUT Vf=VIN(FRIN1A+LR)2•(+RR1+3R2) SUPPLY tDELAY V1 LTC4417 VOUT 4417 F05 R3 UV1 1V + UV UV1 VALID1 RP Figure 6. Fault Filter Time Extension CUVF – VALID 1.03V Extending the filter time delay will result in a slower response to fast UV and OV faults. Extending the UV pin OPTIONAL FILTER 256ms M1 CAPACITOR TIMER fault filter time delay will also add delay to the OV pin. If this is not desirable, separate the single resistive string 1V M2 R2 + OV OV1 into two resistive strings, as shown in Figure 3. OV10.97V – VALID R1 OPTIONAL DISCONNECT GND HYS PRIORITY REASSIGNMENT 4417 F04 A connected input supply can be manually disconnected Figure 5. LTC4417 Internal Hysteresis with Optional Filter Capacitor and Manual Disconnect MOSFET by artificially creating a UV fault. An example is shown in Figure 5. When N-channel MOSFET, M2, is turned on, the 4417f 13

LTC4417 applicaTions inForMaTion UV1 pin is pulled below 1V. The LTC4417 then discon- In normal operation, the external P-channel MOSFET de- nects V1 and connects the next highest valid priority to vices are either fully on, dissipating relatively low power, V . When selecting the external N-channel MOSFET, or off, dissipating no power. However, during slew-rate OUT be sure to account for drain leakage current when setting controlled start-up, significant power is dissipated in the UV and OV thresholds by adjusting the resistive divider to external P-channel MOSFETs. The external P-channel consume more current. MOSFETs dissipate the maximum amount of power during the initial slew-rate limited turn on, where the full input voltage is applied across the MOSFET while it sources SELECTING EXTERNAL P-CHANNEL MOSFETS current. Power dissipation immediately starts to decrease The LTC4417 drives external back-to-back P-channel as the output voltage rises, decreasing the voltage drop MOSFETs to conduct or block load current between an across the MOSFETs. input supply and load. When selecting external P-channel A conservative approach for determining if a particular MOSFETs, the key parameters to consider are on-resistance device is capable of supporting soft-start, is to ensure its (R ), absolute maximum rated drain to source break- DS(ON) maximum instantaneous power, at the start of the output down voltage (BV ), threshold voltage (V ), DSS(MAX) GS(TH) slewing, is within the manufacturer’s SOA curve. First power dissipation, and safe operating area (SOA). determine the duration of soft-start using Equation (9) To determine the required R use Equation (8), where DS(ON) and find the inrush current into the load capacitor using V is the maximum desired voltage drop across the DROP Equation (10). two series MOSFETs at full load current, I , for the L(MAX) V application. External P-channel MOSFET devices may be t = IN (9) STARTUP paralleled to further decrease resistance and decrease 5[V/ms] power dissipation of each paralleled MOSFET. I = C • 5000[V/s] (10) MAXCAP L V RDS(ON) ≤ 2•IDROP (8) Using VIN and IMAXCAP, the power dissipated by the external L(MAX) MOSFETs during start-up, P , is defined by Equation (11). SS If the LTC4417 soft-starts with a live I , the extra load cur- The clamped gate drive output is 4.5V (minimum) from L rent needs to be added to I , and P is calculated the common source connection. Select logic level or lower MAXCAP SS by Equation (12). threshold external MOSFETs to ensure adequate overdrive. For applications with input supplies lower than the clamp P = V • I (11) SS IN MAXCAP voltage, choose external MOSFET with thresholds suf- P = V • (I + I ) (12) ficiently lower than the input supply voltage to guarantee SS IN MAXCAP L full enhancement. Check to ensure P with a t single pulse duration SS STARTUP lies within the safe operating area (SOA) of the chosen It is imperative that external P-channel MOSFET devices MOSFET. Ensure the resistive dividers can sink the drain- never exceed their BV rating in the application. DSS(MAX) source leakage current at the maximum operating tem- Select devices with BV ratings higher than seen DSS(MAX) perature. Refer to manufacturer’s data sheet for maximum in the application. Switching inductive supply inputs with drain to source leakage currents, I . low value input and/or output capacitances may require DSS additional precautions; see Transient Supply Protection A list of suggested P-channel MOSFETs is shown in section in this data sheet for more information. Table 1. Use procedures outlined in this section and the SOA curves in the chosen MOSFET manufacturer’s data sheet to verify suitability for the application. 4417f 14

LTC4417 applicaTions inForMaTion Table 1. List of Suggested P-Channel MOSFETs V2 DISCONNECTS V2 = 18V MAX RATED V1, V2, V3 MOSFET VTH(MAX) VGS(MAX) VDS(MAX) RDS(ON) AT 25°C VOUT dV I OUT= L ≤5V Si4465ADY –1V ±8V –8V 9mΩ at –4.5V dt CL 11mΩ at –2.5V V1 VALIDATES ≤10V Si4931DY* –1V ±8V –12V 18mΩ at –4.5V 22mΩ at –2.5V V1 = 12V 256ms ≤18V FDS8433A –1V ±8V –20V 47mΩ at –4.5V 70mΩ at –2.5V VOUT ≤18V IRF7324* –1V ±12V –20V 18mΩ at –4.5V 26mΩ at –2.5V V1 = 12V ≤28V Si7135DP –3V ±20V –30V 6.2mΩ at –4.5V VREV = ≤28V FDS6675BNZ –3V ±20V –30V 22mΩ at –4.5V 120mV V1 CONNECTS AT ≤28V AO4803A* –2.5V ±20V –30V 46mΩ at –4.5V VOUT = 11.88V 4417 F07 ≤36V SUD50P04 –2.5V ±20V –40V 30mΩ at –4.5V Figure 7. Reverse Current Blocking ≤36V FDD4685 –3V ±20V –40V 35mΩ at –4.5V ≤36V FDS4685 –3V ±20V –40V 35mΩ at –4.5V The LTC4417 validates V1 and disconnects V2, allowing ≤36V Si4909DY* –2.5V ±20V –40V 34mΩ at –4.5V VOUT to decay from 18V to 11.88V at a slew rate determined ≤36V Si7489DP –3V ±20V –100V 47mΩ at –4.5V by the load current divided by the load capacitance. Once *Denotes Dual P-Channel VOUT falls to 11.88V, the LTC4417 connects V1 to VOUT. SELECTING V CAPACITANCE REVERSE VOLTAGE PROTECTION OUT To ensure there is minimal droop at the output, select a The LTC4417 is designed to withstand reverse voltages low ESR capacitor large enough to ride through the dead applied to V1, V2 and V3 with respect to V of up to OUT time between channel switchover. A low ESR bulk capacitor –84V. The large reverse voltage rating protects 36V input will reduce IR drops to the output voltage while the load supplies and downstream devices connected to V OUT current is sourced from the capacitor. Use Equation (13) against high reverse voltage connections of –42V (absolute to calculate the load capacitor value that will ride through maximum) with margin. the OV/UV comparator delay, t , plus the break- pVALID(OFF) Select back-to-back P-channel MOSFETS with BVDSS(MAX) before-make time, tG(SWITCHOVER). ratings capable of handling any anticipated reverse voltages between VOUT and V1, V2 or V3. Ensure transient voltage C IL(MAX)•(tG(SWITCHOVER)+tpVALID(OFF)) (13) suppressors (TVS) connected to reverse connection pro- L V OUT_DROOP(MAX) tected inputs (V1, V2 and V3) are bidirectional and input capacitors are rated for the negative voltage. where I is the maximum load current drawn and L(MAX) V is the maximum acceptable amount of OUT_DROOP(MAX) voltage droop at the output. REVERSE CURRENT BLOCKING Equation (13) assumes no inrush current limiting circuitry When switching channels from higher voltages to lower is required. If it is required, refer to Figure 8 and use the voltages, the REV comparator verifies the V voltage is OUT following Equation (14) for C . below the connecting channel’s voltage by 120mV before L the new channel is allowed to connect to VOUT. This ensures CL≥ (14) little to no reverse conduction occurs during switching. ( ) I • t +t +0.79•R •C L(MAX) G(SWITCHOVER) pVALID(OFF) S S An example is shown in Figure 7. V2 is initially connected V OUT_DROOP(MAX) to V when a higher priority input supply, V1, is inserted. OUT 4417f 15

LTC4417 applicaTions inForMaTion where R and C are component values shown in Figure 8. channel disconnects or 32ms has elapsed. Once soft-start S S The selection of R and C involves an iterative process. has terminated, the gate driver quickly turns on and off S L Begin by assuming 0.79 • R • C = 10µs and choosing external back-to-back P-channel MOSFETs as needed. A S S C using Equation (14). See the Inrush Current and Input SHDN low to high transition or V drooping below 0.7V L OUT Voltage Droop section for more details regarding inrush reactivates soft-start. current limiting circuitry, and for selecting R . S INRUSH CURRENT AND INPUT VOLTAGE DROOP IRF7324 12V WALL V1 M1 M2 When switching control of V from a lower voltage supply OUT ADAPTER + C68INµ1F CS to a higher voltage supply, the higher voltage supply may experience significant voltage droop due to high inrush CVS1 DBAST54 RS current during a fast connection to a lower voltage output bulk capacitor with low ESR. This high inrush current may be sufficient to trigger an undesirable UV Fault. VS1 G1 VOUT + VOUT LTC4417 CL To prevent a UV fault when connecting a higher voltage 47µF input to a lower voltage output, without adding any inrush 4417 F08 current limiting, size the input bypass capacitor large Figure 8. Slew Rate Limiting Gate Drive enough to provide the required inrush current, as shown by Equation (15). GATE DRIVER ⎛V1–V ⎞ When turning a channel on, the LTC4417 pulls the common C ≥C •⎜ OUT(INIT) –1⎟ (15) V1 L gate connection (G1, G2 and G3) down with a P-channel ⎝ V1DROOP ⎠ source follower and a 2µA current source. VS1, VS2 and where V is the initial output voltage when being VS3 voltages at or above 5V will produce rising slew rates OUT(INIT) powered from a supply voltage less than V1, C is the of 12V/µs and falling slew rates of 4V/µs with 10nF between V1 bypass capacitor connected to V1, C is the output capaci- the VS and G pins. VS1, VS2 and VS3 voltages lower than L tor and V1 is the maximum allowed voltage droop 5V will result in lower slew rates, see typical curves for DROOP on V1. Make sure C is a low ESR capacitor to minimize more detail. As G1, G2 and G3 approaches the 6.2V clamp V1 the voltage step across the ESR. voltage, the source follower smoothly reduces its current while the 2µA hold current continues to pull G1, G2 and In situations where input and output capacitances can- G3 to the final clamp voltage, back biasing the source not be chosen to set the desired maximum input voltage follower. Clamping the G1, G2 and G3 voltage prevents droop, or the peak inrush current violates the maximum any overvoltage stress on the gate to source oxide of the Pulsed Drain Current (I ) of the external P-channel MOS- DM external back-to-back P-channel MOSFETs. If leakage into FETs, inrush current can be limited by slew rate limiting G1, G2 and G3 exceeds the 2µA hold current, the G1, G2 the output voltage. The gate driver can be configured to and G3 voltage will rise above the clamp voltage, where slew rate limit the output with a resistor, capacitor and the source follower enhances to sink the excess current. Schottky diode, as shown in Figure 8. The series resistor When turning a channel off, the gate driver pulls the com- R and capacitor, C , slew rate limit the output, while the S S mon gate to the common source with a switch having an Schottky diode, D , provides a fast turn off path when G1 S on-resistance of 16Ω, to effect a quick turn-off. is pulled to VS1. To minimize inrush current at start-up, the gate driver soft- With a desired input voltage drop, V1 , and known DROOP starts the gate drive of the first input to connect to VOUT. supply resistance RSRC, the series resistance, RS, can The gate pin is regulated to create a constant 5V/ms rise be calculated with Equation (16), where ∆V is G(SINK) rate on VOUT. Slew rate control is terminated when any the LTC4417’s sink clamp voltage, VGS is the external 4417f 16

LTC4417 applicaTions inForMaTion P-channel’s gate to source voltage when driving the load TRANSIENT SUPPLY PROTECTION and inrush current, C is the slew rate capacitor and C S L The LTC4417’s abrupt switching due to OV or UV faults is the V hold up capacitance. The output load current OUT can create large transient overvoltage events with inductive I is neglected for simplicity. Choose C to be at least ten L S input supplies, such as supplies connected by a long cable. times the external P-channel MOSFET’s C , and RSS(MAX) At times the transient overvoltage condition can exceed C to be ten times C . VS S twice the nominal voltage. Such events can damage external (ΔV –V )•C •R devices and the LTC4417. It is imperative that external G(SINK) GS L SRC R ≥ (16) back-to-back P-channel MOSFET devices do not exceed S C •V1 S DROOP their single pulse avalanche energy specification (EAS) in unclamped inductive applications and input voltages to the Use Equation (17) to verify the inrush current limit is lower LTC4417 never exceed the Absolute Maximum Ratings. than the absolute maximum pulsed drain current, I . DM To minimize inductive voltage spikes, use wider and/or V1 I = DROOP (17) heavier trace plating. Adding a snubber circuit will dampen INRUSH RSRC input voltage spikes as discussed in Linear Application Note 88, and a transient surge suppressor at the input will If the external P-channel MOSFET’s reverse transfer clamp the voltage. Transient voltage suppressors (TVS) capacitance, C , is used instead of C , replace C with RSS S S should be placed on any input supply pin, V1, V2 and V3, C in Equation (16), where C is taken at the minimum RSS RSS where input shorts, or reverse voltage connection can be V voltage, and calculate for R . Depending on the size DS S made. If short-circuit of input sources powering V are OUT of C , R may be large. Care should be used to ensure RSS S possible, transient voltage suppressors should also be gate leakages do not inadvertently turn off the channel over placed on V , as shown in Figure 9. OUT temperature. This is particularly true of built in Zener gate- When selecting transient voltage suppressors, ensure the source protected devices. Careful bench characterization reverse standoff voltage (V ) is equal to or greater than is strongly recommended, as C is non-linear. R RSS the application operating voltage, the peak pulse current The preceding analysis assumes a small input inductance (I ) is higher than the peak transient voltage divided by PP between the input supply voltage and the drain of the ex- the source impedance, the maximum clamping voltage ternal P-channel MOSFET. If the input inductance is large, (V ) at the rated I is less than the absolute maxi- CLAMP PP choose C to be much greater than C and replace R V1 L SRC mum ratings of the LTC4417 and BV of all the external DSS with the ESR of C . V1 back-to-back P-channel MOSFETs. When slew rate limiting the output, ensure power dis- In applications below 20V, transient voltage suppressors sipation does not exceed the manufacturer’s SOA for the may not be required if the voltage spikes are lower than the chosen external P-channel MOSFET. Refer to the Selecting BV of the external P-channel MOSFETs and the LTC4417 DSS External P-channel MOSFETs section. INPUT OUTPUT PARASITIC FDD4685 FDD4685 PARASITIC INDUCTANCE INDUCTANCE 24V WALL M1 M2 ADAPTER + VOUT RSN OR D1 C0.V11µF COUT OR D2 C33L0µF SMBJ26CA 10µF SMBJ26A CSN VS1 G1 VOUT LTC4417 SNUBBER 4417 F09 Figure 9. Transient Voltage Suppression 4417f 17

LTC4417 applicaTions inForMaTion Absolute Maximum Ratings. If the BV of the external from the output before the output is dragged below the DSS P-channel MOSFET is momentarily exceeded, ensure the operating voltage of the LTC4417. The event would cause avalanche energy absorbed by the MOSFETs do not exceed the LTC4417’s internal V supply voltage to collapse. A LDO the single pulse avalanche energy specification (EAS). 100Ω and 10nF R-C filter on V will allow the LTC4417 OUT Voltage spikes can be dampened further with a snubber. to ride through such shorts to the input and output, as shown in Figure 10. Because V is also a sense pin OUT for the REV comparator, care should be taken to ensure INPUT SUPPLY AND V SHORTS OUT the voltage drop across the resistor is low enough to not Input shorts can cause high current slew rates. Coupled affect the reverse comparator’s threshold. If the 1µs R-C with series parasitic inductances in the input and output time constant does not address the issue, increase the paths, potentially destructive transients may appear at the capacitance to lengthen the time constant. input and output pins. If the short occurs on an input that is not powering V , the impact to the system is benign. OUT IRF7324 Back-to-back P-channel MOSFETs with their common gates M3 M4 connected to their common sources naturally prevent any current flow regardless of the applied voltages on either IRF7324 M5 M6 side of the drain connections, as long as the BV is not DSS exceeded. If the short occurs on an input that is powering VOUT, the VS2 G2 VS3 G3 RF VOUT 100Ω OUTPUT issue is compounded by high conduction current and low LTC4417 VOUT + impedance connection to the output via the back-to-back C10FnF CL IL P-channel MOSFETs. Once the LTC4417 blocks the high 4417 F10 input short current, V1, V2 and V3 may experience large Figure 10. R-C Filter to Ride Through Input Shorts negative voltage spikes while the output may experience large positive voltage spikes. The initial lag due to the R-C filter on the LTC4417’s V OUT To prevent damage to the LTC4417 and associated de- sense and supply pin will cause additional delay in sensing vices in the event of an input or output short, it may be when a reverse condition has cleared, resulting in addi- necessary to protect the input pins and output pins as tional droop when transitioning from a higher voltage to shown in Figure 9. Protect the input pins, V1, V2 and V3, a lower voltage. If the reverse voltage duration is longer with either unidirectional or bidirectional TVS and V than the R-C delay, the voltage differential between the OUT with a unidirectional TVS. An input and output capacitor output and the filtered VOUT, ∆V, can be calculated with between 0.1µF and 10µF with intentional or parasitic series Equation (18). IL is the output load current during the resistance will aid in dampening voltage spikes; see Linear reverse voltage condition and IVOUT is current into VOUT, Technology’s Application Note 88 for general consideration. specified in the electrical table. Due to the low impedance connection from V1, V2 and V3 ⎛I ⎞ ΔV=⎜ L •C –I ⎟•R (18) to V , shorts to the output will result in an input supply F VOUT F OUT ⎝C ⎠ L UV fault. If the UV threshold is high enough and the short resistive enough, the LTC4417 will disconnect the input. The fast change in current may force the output below I PATH SELECTION CC GND, while the input will increase in voltage. Two separate internal power rails ensure the LTC4417 is If UV thresholds are set close to the minimum operating functional when one or more input supplies are present voltage of the LTC4417, it may not disconnect the input and above 2.4V as well as limit current draw from lower 4417f 18

LTC4417 priority back up input supplies. An internal diode-OR est input voltage input supply as the source. See Typical structure selects the highest voltage input supply as the Performance Characteristics for more detail. source for VB . If two supplies are similar in voltage and LDO higher than the remaining input supply, the current will be DUAL SUPPLY OPERATION equally divided between the similar voltage supplies. If all For instances where only two supplies are prioritized and input supplies are equal in voltage, the current is divided no features of the third channel are used, ground the evenly between them. V3, OV3, UV3, VS3 and G3 pins of the unused channel. To limit current consumption from lower priority backup Alternatively, the lowest priority OV and UV comparators supplies, the LTC4417 prioritizes the internal V ’s source LDO can be utilized for voltage monitoring when V3 and VS3 supply. The highest priority source is V , which powers OUT are connected to the output and G3 is left open. Figure 11 the V when V is above 2.4V. If V is lower than LDO OUT OUT shows an example of the spare OV and UV comparators 2.4V, V switches to the highest valid priority input LDO used to monitor the 5V output of the LTC3060. VALID3 supply, V1, V2 and V3. If no input supply is valid, V LDO acts as an open drain OV/UV window comparator output. is connected to VB , where the diode-OR selects high- LDO 12V WALL IRF7324 ADAPTER M1 M2 + + VOUT CIN CL 2200µF 100µF 14.4V NiCd IRF7324 BATTERY M3 M4 + CS 6.8nF LTC3060 LINEAR CVS1 CVS2 REGULATOR 0.1µF 1µF DBAST54 RS 2.21k 5V OUTPUT CV3 CV2 CV1 VS1 G1 VS2 G2 VS3 G3 R10 R11 R12 0.1µF 0.1µF 0.1µF V1 VOUT 1M 1M 1M R3 806k UV1 V1 INVALID R2 VALID1 39.2k V2 INVALID OV1 VALID2 5V OUTPUT INVALID R1 VALID3 60.4k V2 R6 845k LTC4417 UV2 R5 26.1k OV2 R4 51.1k V3 EN R9 SHDN 340k HYS UV3 R8 CAS 21.5k OV3 GND R7 4417 F11 78.7k Figure 11. Dual Channel with Output Voltage Monitoring 4417f 19

LTC4417 applicaTions inForMaTion DISABLING ALL CHANNELS WITH EN AND SHDN IRF7324 M1 M2 Driving EN below 1V turns off all external back-to-back P-channel MOSFETs but does not interrupt input supply monitoring or reset the 256ms timers. Driving EN above 1V enables the highest valid priority channel. This feature CVS1_1 0.1µF is essential in cascading applications. For applications where EN could be driven below ground, limit the current VS1 G1 from EN with a 10k resistor. VOUT Forcing SHDN below 0.8V turns off all external back-to-back LTC4417 P-channel MOSFETs, disables all OV and UV comparators MASTER EN DISABLE ALL CHANNELS and resets all 256ms timers. VALID1, VALID2 and VALID3 SHDN SHDN MASTER CAS release high to indicate all inputs are invalid, regardless of the input supply condition. The LTC4417 enters into a low current state, consuming only 15µA. When SHDN is released or driven above 0.8V, the LTC4417 is required IRF7324 M3 M4 to revalidate the input supplies before connecting the inputs to V , as described in the Operation section. For OUT applications where SHDN could be driven below ground, limit the current from SHDN with a 10k resistor. CVS1_2 0.1µF CASCADING VS1 G1 VOUT VOUT + The LTC4417 can be cascaded to prioritize four or more CL 47µF input supplies. To prioritize four to six supplies, use two LTC4417 LTC4417s with their VOUT pins connected together and the SLAVE EN master LTC4417’s CAS connected to the slave LTC4417’s SHDN CAS EN as shown in Figure 12. The first LTC4417 to validate an input will soft-start the common output. Once the output 4417 F12 is above 2.4V, power will be drawn from V by the other OUT Figure 12. Cascading Application LTC4417 regardless of its input supply conditions. When the master LTC4417 wants to connect one of its from V before releasing CAS. CAS is pulled to the in- OUT input supplies to the V , it simultaneously initiates a ternal V rail with a 20µA current source, allowing the OUT LDO channel turn on and pulls its CAS pin low to force the slave slave LTC4417 to connect its highest valid priority channel LTC4417 to disconnect its channels. A small amount of to V . Confirmation that all channels are off before the OUT reverse conduction may occur in this case. The amount slave is allowed to connect its channel to V prevents OUT of cross conduction will depend on the total turn-on delay cross conduction from occurring. of the master channel compared with the turn-off delay Driving the master LTC4417’s EN low forces both master of the slave channel. Care should be taken to ensure the and slave to disconnect all channels from the common connection between CAS and EN is as short as possible, output and continue monitoring the input supplies. Driv- to minimize the capacitance and hence the turn-off delay ing the master LTC4417’s SHDN low places it in to a low of the slave channel. current state. While in the low current state, all of its chan- When all of the inputs to the master LTC4417 are invalid, nels are disconnected and CAS is pulled high with a 20µA the master confirms that all its inputs are disconnected current source, allowing the slave LTC4417 to become the 4417f 20

LTC4417 applicaTions inForMaTion master and connect its highest valid priority channel to source, R is source resistance of V1, ESR(C ) is the SRC L the common output. If seven, or more, input supplies are ESR of the load capacitor, and R is the on-resistance DS(ON) prioritized, additional LTC4417s can be added by connect- of the external back-to-back MOSFET. ing all individual V pins together and connecting each OUT Given a total series resistance from input to output, the LTC4417’s CAS to the next lower priority LTC4417’s EN. worst case inrush current will occur when V1 is running 20% high, at 14.4V, and V is at its undervoltage limit OUT DESIGN EXAMPLE of 5.6V. During this condition, a maximum inrush current of 83A will occur, as shown in Equation (20). A 2A multiple input supply system consisting of a 12V supply with a source resistance of 20mΩ, 7.4V main 14.4V–5.6V I = =83A (20) lithium-ion battery, and a backup 7.4V lithium-ion battery INRUSH 20mΩ+50mΩ+36mΩ is designed with priority sourcing from the 12V supply, as shown in Figure 13. Power is sourced from the main Because the 83A of inrush current exceeds the 71A ab- battery when the 12V supply is absent and the backup solute maximum pulsed drain current rating, I , of the DM battery is only used when the main battery and 12V supply IRF7324, inrush current limiting is required. are not available. The ambient conditions of the system Calculating the load capacitance, C , and inrush current L will be between 25°C and 85°C. limiting circuitry component, R , is an iterative process. S The design limits the output voltage droop to 800mV To start, use Equation (14), with 0.79 • R • C initially set S S during switchover. The load capacitor is assumed to have to 10µs. To limit the output voltage droop to the desired a minimum ESR of 50mΩ at 85°C and 80mΩ at 25°C 800mV, reserve 200mV for initial droop due to the load through paralleling low ESR rated aluminum electrolytic current flowing in the ESR of the output capacitor. Next, capacitors. The input source is allowed to drop 1V. choose C to set the maximum V droop to 600mV, as L OUT shown in Equation (21). Selecting External P-Channel MOSFET 2A•(3µs+12µs+10µs) C = The design starts with selecting a suitable 2A rated L 600mV (21) P-channel MOSFET with desired R . Reviewing several DS(ON) C =83.3µF MOSFET options, the low 18mΩ R , dual P-channel L DS(ON) IRF7324 with a –20V BV , is chosen for this application. DSS For margin, choose the initial C value equal to 100µF and L The low 18mΩ RDS(ON) results in a 72mV combined drop use Equation (16) to determine RS. With an allowable 1V at 25°C and 85mV drop at 85°C. Each P-channel MOSFET input voltage drop and source resistance, RSRC, of 20mΩ, dissipates 72mW at 25°C and 85mW at 85°C. the input voltage droop of 700mV is used to set the inrush current of 35A. The other terms in the equation come Inrush Current Limiting from the external P-channel MOSFET manufacturer’s data sheet. The transfer characteristics curve shows the gate When connecting a higher voltage source to a lower voltage voltage, V , is approximately 1.8V when driving the 35A output, significant inrush current can occur. The magnitude GS inrush current and the capacitance verses drain-to-source of the inrush current can be calculated with Equation (19). voltage curve shows the maximum C is approximately RSS V1–V 600pF. C is set to be greater than ten times C , or I = OUT(INIT) S RSS INRUSH R +ESR(C )+2•R (19) 6.8nF. To ensure the designed inrush current is lower SRC L DS(ON) than the absolute maximum pulse drain current rating, where VOUT(INIT) is the VOUT voltage when initially powered IDM, calculate RS using the maximum value for ∆VG(SINK) from a supply voltage less than V1, V1 is the higher voltage and CL, and the minimum value for CS. For aluminum 4417f 21

LTC4417 applicaTions inForMaTion IRF7324 12V SUPPLY M1 M2 + CIN CS 2700µF 6.8nF 7.4V Li-Ion BATTERY IRF7324 (2 × 3.7V) M3 M4 + 7B.4AVT TLEi-RIoYn DBAST54 R2.S21k IRF7324 (2 × 3.7V) M5 M6 + CVS1 CVS2 CVS3 + 68nF 0.1µF 0.1µF CL 100µF CV3 CV2 CV1 VS1 G1 VS2 G2 VS3 G3 0.1µF 0.1µF 0.1µF VOUT V1 VOUT R3 R10 R11 R12 806k 1M 1M 1M UV1 R2 41.2k V1 INVALID OV1 VALID1 R1 V2 INVALID 60.4k VALID2 V3 INVALID V2 VALID3 R6 768k 140k LTC4417 UV2 R5 53.6k OV2 R4 113k V3 EN R9 SHDN 768k 140k UV3 HYS RHYS R8 CAS 255k 53.6k 1% OV3 GND R7 4417 F13 113k Figure 13. Industrial Hand Held Computer electrolytic capacitors, add 20% to C and for ceramic With R and C known, the desired load capacitance with L S S NP0 C capacitors subtract 5%. inrush current limiting is checked with Equation (14) S as shown in Equation (23). Because the required load (6V–1.8V)•120µF•20mΩ R = capacitance of 90µF is lower than the chosen load ca- S 6.5nF•700mV (22) pacitor of 100µF, the initial choice of 100µF is suitable. R =2.22kΩ S 2A•(3µs+12µs+0.79•2.21kΩ•6.8nF) C ≥ L 600mV The standard value of 2.21kΩ is chosen for R and C (23) S VS1 C ≥90µF is chosen to be ten times CS or 68nF. Although 1.8V is a L typical value for V , there is sufficient margin – even if GS V = 0V, the resulting I is lower than the 71A rating. GS DM 4417f 22

LTC4417 applicaTions inForMaTion Significant power is dissipated during the channel transi- Setting Operational Range tion time. The SOA of the P-channel MOSFET should be Assuming the 12V source has a tolerance of ±20%, the checked to make sure their SOA is not violated. input source has an operational undervoltage limit of Worst case slew rate limited channel transition time 9.6V and an overvoltage limit of 14.4V. Ideally the UV1, would occur when the lithium-ion batteries are running UV2 and UV3 and OV1, OV2 and OV3 thresholds would low at 5.6V, and the supply connects while running 20% be set to these limits. However, since the actual threshold high, at 14.4V. This results in a time of 25µs, as shown varies by 1.5% and resistor tolerances are 1%, OV and in Equation (24). UV limits must be adjusted to ±26% or 8.9V and 15.1V. Further, instead of using the internal fixed 30mV, a UV (14.4V–5.6V)•100µF dt= hysteresis of 200mV is set using an external hysteresis 35A (24) current of 250nA. dt=25µs The design process starts with setting RHYS using Equation (1). The IRF7324 thermal response curve at 25µs shows Z θJA to be approximately 0.18 for a single pulse. The Z of 63mV θJA R = =252kΩ (28) 0.18 results in a maximum transient power dissipation of HYS 250nA 694W at 25°C and 361W at 85°C. The external P-channel The nearest standard value is 255kΩ. MOSFETs will dissipate no more than 8.8V • 37A = 325W during this period, below the available 361W at 85°C. Now set the UV hysteresis value using R3 The initial soft-start period will also force the external Desired Hysteresis 200mV R3= = =810kΩ (29) back-to-back MOSFETs to dissipate significant power. To I 247nA check the SOA during this period, start with Equation (9). OVUV(HYS) 12V The nearest standard value is 806kΩ. t (ms)= STARTUP 5[V/ms] With R3 set, the remaining resistance can be determined (25) t (ms)=2.4ms with STARTUP R3 R1,2= IMAXCAP current of 500mA is calculated using Equation (10). UVTH(FALLING)–VOVUV(THR) IMAXCAP = 100µF • 5[V/ms] 806kΩ (30) (26) = =102kΩ I = 500mA 8.9V–1V MAXCAP The worst case soft-start power dissipation from Equa- R1 is tion (11) is: R1,2+R3 102kΩ+806kΩ P (W) = 12V • 500mA R1= = =60.1kΩ (31) SS (27) OV 15.1V P (W) = 6W TH(RISING) SS The nearest 1% standard value is: 60.4kΩ. The soft-start power dissipation of 6W is well below the calculated transient power dissipation (PDM) of 79.4W at R2 is a T of 25°C. An ambient temperature, T , of 85°C results C A R2 = R1,2 – R3 = 102kΩ – 60.4kΩ = 41.6kΩ (32) in a P of 41.3W, indicating it is sufficient to handle the DM 2.4ms transient 6W power dissipation. A graphical check The nearest 1% standard value is 41.2kΩ. with the manufacturer’s SOA curves confirms sufficient operating margin. 4417f 23

LTC4417 applicaTions inForMaTion Because this is a single resistive string R2, R3, and Layout Considerations I sets the hysteresis voltage with Equation (30) OV_UV(HYS) Sheet resistance of 1oz copper is ~530µΩ per square. OV = (R2 + R3) • I = Although small, resistances add up quickly in high current HYS OVUV(HYS) (33) applications. Keep high current traces short with minimum (41.2kΩ + 806kΩ) • 247nA = 209mV trace widths of 0.02" per amp to ensure traces stay at a This results in an OV threshold of 15.0V and UV threshold reasonable temperatures. Using 0.03" per amp or wider of 8.9V. With hysteresis, the OVHYS threshold is 14.8V is recommended. To improve noise immunity, place OV/ and the UVHYS threshold is 9.1V. For the desired OV and UV resistive dividers as close to the LTC4417 as possible. UV 6% accuracy, 1% resistors used in this example are Transient voltage suppressors should be located as close acceptable. to the input connector as possible with short wide traces to GND. Figure 14 shows a partial layout that addresses Values for R4 to R6 and R7 to R9 for V2 and V3 are these issues. similarly calculated. TO V3 INPUT SUPPLY S G TO OUTPUT FROM V2 D D INPUT SOURCE G S S G FROM V1 D D INPUT SOURCE G S TRANSIENT 0.03" PER AMPERE VOLTAGE 1 EN V1 24 CV1 SUPPRESSOR 2 SHDN V2 23 CV2 R3 3 HYS V3 22 CV3 4 UV1 VS1 21 R6 R2 5 OV1 G1 20 6 UV2 VS2 19 R5 R1 7 OV2 G2 18 R9 8 UV3 VS3 17 TO V3 COMMON SOURCE R4 9 OV3 G3 16 TO V3 COMMON GATE R8 10 VALID1 VOUT 15 11 VALID2 CAS 14 R7 12 VALID3 GND 13 GND NOT TO SCALE GND Figure 14. Recommended PCB Layout 4417f 24

LTC4417 Typical applicaTions 12V System Using Swappable and Backup Batteries 12V WALL IRF7324 ADAPTER M1 M2 + CIN1 2200µF 12V NiCd IRF7324 BATTERY M3 M4 + CS 6.8nF DS RS 11.1V Li-Ion BAT54 2.21k BATTERY IRF7324 (3 × 3.7V) M5 M6 + + CL 100µF CVS1 CVS2 CVS3 0.1µF 1µF 0.1µF CV3 CV2 CV1 VS1 G1 VS2 G2 VS3 G3 0.1µF 0.1µF 0.1µF VOUT V1 VOUT R3 R10 R11 R12 1.02M 1M 1M 1M UV1 R2 48.7k V1 INVALID OV1 VALID1 R1 V2 INVALID 76.8k VALID2 V3 INVALID V2 VALID3 R6 1.02M LTC4417 UV2 R5 36.5k OV2 R4 76.8k V3 EN R9 SHDN 1.0M HYS R8 UV3 CAS RHYS 316k 40.2k OV3 GND R7 90.9k 4417 TA02 4417f 25

LTC4417 Typical applicaTions 18V System with Reverse Voltage Protection 18V FDS4685 FDS4685 WALL ADAPTER M1 M2 VOUT D1 C22IN010µF D4 SMBJ26CA SMBJ26A CVS1 11.1V Li-Ion 0.1µF FDS4685 FDS4685 BATTERY M3 M4 + D2 SMBJ26CA CVS2 C10L0µF 12V LEAD-ACID 0.1µF FDS4685 FDS4685 BATTERY M5 M6 + D3 SMBJ26CA CVS3 CV1 0.1µF 0.1µF VS1 G1 VS2 G2 VS3 G3 V1 VOUT CV3 CV2 R3 0.1µF 0.1µF 1.02M UV1 R2 11.8k OV1 VALID1 R1 54.9k VALID2 V2 VALID3 R6 768k LTC4417 UV2 R5 90.9k OV2 R4 75k V3 EN R9 SHDN 698k HYS UV3 R8 CAS 16.9k OV3 GND R7 49.9k 4417 TA03 4417f 26

LTC4417 Typical applicaTions M5 5V, 15A OUTPUTC2330µF2× R13100k R101M VOUT +CL100µF C1547pFR15255k R1648.7k R12R111M1M R321MR301MR3159kR2940.2k R282k Q3BC817-25 R2730.1k L20.68µH D3MBRS340 R1710k 28V Transient Hold-Up Supply for Solid State Drives (SSD) D2MBRS360C74.7µFVC11INEN/UVLOINTVL1BCC10µF33µHR26SW10kR21VMODE536kFBLT3956PWMR22L1ACTRLPWMOUT25k33µHR2514kISPVR23REF1ΩSSISNRTC10VCR2410µFGNDC828.7k10nF LT3956 SUPERCAP CHARGER WITH INPUT CURRENT LIMITPLEASE REFER TO THE LT3956 DATA SHEET FOR SPECIFIC APPLICATION INFORMATION D1CMDSH2-3 INTVVCCINR18C5100k4.7µFQ1TGPGO0DSTD30NFL06LC4PLLIN/MODE0.1µFRUNBOOSTTK/SSSWC9Q20.1µFLTC3851BGSTD30NFL06L FREQ/PLLFLTRC17VR20FB0.1µF82.5kC1G3VS3+2200pFSENSE IC16R19THC3R140.22µF13k330pF15k–SENSEGND VOUTLTC3851-1.5V/15A BUCKPLEASE REFER TO THE LTC3851 DATA SHEET FOR SPECIFIC APPLICATION INFORMATION INVALID 12V SYSTEMVALID1INVALID SUPERCAPVALID2SUPERCAP NOT FULLY CHARGEDVALID3 ENSHDNHYSR9CAS124k 4417 TA04 FDS4685M2 CS6.8nF FDS4685FDS4685M3M4 CVS20.1µF DRSSBAT541.43k G1VS2G2 LTC4417 GND FDS4685M1 CVS11µF VS1 V1R3806kUV1R215.8kOV1R166.5k V2R6806kUV2R5127kOV2R433.2k V3R81.02MUV3R741.2kOV3 + 12V SYSTEM SUPPLYCV1470µF CV235V TANTALUM 4417f 27

LTC4417 Typical applicaTions Selecting from USB, FireWire, and Li-Ion Battery Power Sources 4.35V TO 5.25V FDS4685 FDS4685 USB M1 M2 VOUT CIN1 CL 10µF 47µF 8V TO 30V FireWire FDS4685 FDS4685 IEEE1394 M3 M4 CIN2 CS 22µF 6.8nF 0C.1VµSF1 C1VµSF2 DBAST54 R1kS 7.4V Li-Ion FDS4685 FDS4685 BATTERY M5 M6 + CV1 0.1µF CVS3 0.1µF CV2 VS1 G1 VS2 G2 VS3 G3 0.1µF V1 VOUT R3 R10 R11 R12 309k 1M 1M 1M UV1 R2 24.9k OV1 USB INVALID CV3 R1 VALID1 FireWire INVALID 0.1µF 75k VALID2 Li_Ion INVALID V2 VALID3 R6 576k LTC4417 UV2 R5 78.7k OV2 R4 20.5k V3 EN R9 SHDN 931k HYS UV3 R8 CAS 63.4k OV3 GND R7 137k 4417 TA05 4417f 28

LTC4417 Typical applicaTions Wall Adapter and USB Input with Battery Backup 5V WALL Si4931DY ADAPTER M1 M2 VOUT + + CIN1 CL 1000µF 47µF 4.35V TO 5.25V Si4931DY USB M3 M4 CIN2 10µF CV1 0.1µF 4 × AA Si4931DY BATTERY M5 M6 + CVS1 CVS2 CVS3 0.1µF 0.1µF 0.1µF VS1 G1 VS2 G2 VS3 G3 0.C1µVF2 V1 VOUT R3 R13 R12 R14 412k 1M 1M 1M UV1 R2 37.4k CV3 OV1 VALID1 WALL ADAPTER INVALID 0.1µF R1 USB INVALID 95.3k VALID2 4 × AA BATTERY INVALID V2 VALID3 R4 412k LTC4417 UV2 R5 33.2k OV2 R6 100k V3 EN R9 R11 SHDN 432k 562k HYS UV3 R8 CAS RHYS 80.6k 249k OV3 GND R7 R10 86.6k 52.3k 4417 TA06 4417f 29

LTC4417 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. GN Package 24-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641 Rev B) .337 – .344* (8.560 – 8.738) .033 (0.838) 24 23 22 21 20 19 18 17 16 15 1413 REF .045 ±.005 .229 – .244 .150 – .157** (5.817 – 6.198) (3.810 – 3.988) .254 MIN .150 – .165 1 2 3 4 5 6 7 8 9 10 11 12 .0165 ±.0015 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT .015 ±.004 × 45° .0532 – .0688 .004 – .0098 (0.38 ±0.10) (1.35 – 1.75) (0.102 – 0.249) .0075 – .0098 0° – 8° TYP (0.19 – 0.25) .016 – .050 .008 – .012 .0250 GN24 REV B 0212  (0.406 – 1.270) (0.203 – 0.305) (0.635) NOTE: TYP BSC 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 4417f 30

LTC4417 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697 Rev B) 0.70 ±0.05 4.50 ±0.05 2.45 ±0.05 3.10 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 4.00 ±0.10 0.75 ±0.05 R = 0.115 0.35 × 45° CHAMFER TYP (4 SIDES) 23 24 PIN 1 0.40 ±0.10 TOP MARK (NOTE 6) 1 2 2.45 ±0.10 (4-SIDES) (UF24) QFN 0105 REV B 0.200 REF 0.25 ±0.05 0.00 – 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4417f 31 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC4417 Typical applicaTion Dual Channel LTC4417 Application with Output Voltage Monitoring Using Third Channel 12V WALL IRF7324 ADAPTER M1 M2 VOUT + + CIN CL 2200µF 100µF OUT IN 10µF C2 LT3060-5 14.4V NiCd IRF7324 10nF ADJ SHDN BATTERY M3 M4 + REF/BYP GND CS C1 6.8nF 10nF 0C.1VµSF1 C1VµSF2 DS RS BAT54 2.21k 5V OUTPUT CV3 CV2 CV1 VS1 G1 VS2 G2 VS3 G3 R10 R11 R12 0.1µF 0.1µF 0.1µF V1 VOUT 1M 1M 1M R3 806k UV1 R2 VALID1 V1 INVALID 39.2k OV1 VALID2 V2 INVALID R1 VALID3 5V OUTPUT INVALID 60.4k V2 R6 845k LTC4417 UV2 R5 26.1k OV2 R4 51.1k V3 EN R9 SHDN 357k HYS UV3 R8 CAS 15.4k OV3 GND R7 4417 TA07 84.5k relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTC4411 2.6A Low Loss Ideal Diode in ThinSOT™ Internal 2.6A P-channel, 2.6V to 5.5V, 40µA I , SOT-23 Package Q LTC4412HV 36V Low Loss PowerPath Controller in ThinSOT 2.5V to 36V, P-channel, 11µA I , SOT-23 Package Q LTC4415 Dual 4A Ideal Diodes with Adjustable Current Limit Dual Internal P-channel, 1.7V to 5.5V, MSOP-16 and DFN-16 Packages LTC4416 36V Low Loss Dual PowerPath Controller for Large PFETs 3.6V to 36V, 35µA I per Supply, MSOP-10 Package Q LTC4355 Positive High Voltage Ideal Diode-OR with Supply and Dual N-channel, 9V to 80V, SO-16, MSOP-16 and DFN-14 Packages Fuse Monitors LTC4359 Ideal Diode Controller with Reverse Input Protection N-channel, 4V to 80V, MSOP-8 and DFN-6 Packages LTC2952 Pushbutton PowerPath Controller with Supervisor 2.7V to 28V, On/Off Timers, ±8kV HBM ESD, TSSOP-20 and QFN-20 Packages 4417f 32 Linear Technology Corporation LT 1112 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2012

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